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----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 16/07/2014
--! Module Name: MUX2_Nbit
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--! MUX 2x1, data 16 bit
entity MUX2_Nbit is
generic (N : integer := 1);
port (
data0 : in std_logic_vector((N-1) downto 0);
data1 : in std_logic_vector((N-1) downto 0);
sel : in std_logic;
data_out : out std_logic_vector((N-1) downto 0)
);
end MUX2_Nbit;
--architecture low_level_MUX2_Nbit of MUX2_Nbit is
--begin
--GENERATE_BIT_MUX2: for I in 0 to (N-1) generate
--MUXF7n : MUXF7 port map (data_out(I), data0(I), data1(I), sel);
--end generate GENERATE_BIT_MUX2;
--end low_level_MUX2_Nbit;
architecture behavioral of MUX2_Nbit is
begin
process(data0, data1, sel)
begin
if sel = '0' then
data_out <= data0;
else
data_out <= data1;
end if;
end process;
end behavioral; |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 16/07/2014
--! Module Name: MUX2_Nbit
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--! MUX 2x1, data 16 bit
entity MUX2_Nbit is
generic (N : integer := 1);
port (
data0 : in std_logic_vector((N-1) downto 0);
data1 : in std_logic_vector((N-1) downto 0);
sel : in std_logic;
data_out : out std_logic_vector((N-1) downto 0)
);
end MUX2_Nbit;
--architecture low_level_MUX2_Nbit of MUX2_Nbit is
--begin
--GENERATE_BIT_MUX2: for I in 0 to (N-1) generate
--MUXF7n : MUXF7 port map (data_out(I), data0(I), data1(I), sel);
--end generate GENERATE_BIT_MUX2;
--end low_level_MUX2_Nbit;
architecture behavioral of MUX2_Nbit is
begin
process(data0, data1, sel)
begin
if sel = '0' then
data_out <= data0;
else
data_out <= data1;
end if;
end process;
end behavioral; |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 16/07/2014
--! Module Name: MUX2_Nbit
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--! MUX 2x1, data 16 bit
entity MUX2_Nbit is
generic (N : integer := 1);
port (
data0 : in std_logic_vector((N-1) downto 0);
data1 : in std_logic_vector((N-1) downto 0);
sel : in std_logic;
data_out : out std_logic_vector((N-1) downto 0)
);
end MUX2_Nbit;
--architecture low_level_MUX2_Nbit of MUX2_Nbit is
--begin
--GENERATE_BIT_MUX2: for I in 0 to (N-1) generate
--MUXF7n : MUXF7 port map (data_out(I), data0(I), data1(I), sel);
--end generate GENERATE_BIT_MUX2;
--end low_level_MUX2_Nbit;
architecture behavioral of MUX2_Nbit is
begin
process(data0, data1, sel)
begin
if sel = '0' then
data_out <= data0;
else
data_out <= data1;
end if;
end process;
end behavioral; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1985.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p02n01i01985ent IS
END c07s02b02x00p02n01i01985ent;
ARCHITECTURE c07s02b02x00p02n01i01985arch OF c07s02b02x00p02n01i01985ent IS
BEGIN
TESTING: PROCESS
constant meg : integer := 1000000;
variable bigpos : integer := 2000 * meg;
variable bigneg : integer := -2000 * meg;
variable smallpos : integer := 2000;
variable smallneg : integer := -2000;
variable zero : integer := 0;
BEGIN
assert NOT( ( bigneg < smallneg) and
( bigneg < zero) and
( bigneg < smallpos) and
( bigneg < bigpos) and
( smallneg < zero) and
( smallneg < smallpos) and
( smallneg < bigpos) and
( zero < smallpos) and
( zero < bigpos) and
( smallpos < bigpos) and
( not(bigneg >= smallneg)) and
( not(bigneg >= zero)) and
( not(bigneg >= smallpos)) and
( not(bigneg >= bigpos)) and
( not(smallneg >= zero)) and
( not(smallneg >= smallpos)) and
( not(smallneg >= bigpos)) and
( not(zero >= smallpos)) and
( not(zero >= bigpos)) and
( not(smallpos >= bigpos)) and
( bigneg <= smallneg) and
( bigneg <= zero) and
( bigneg <= smallpos) and
( bigneg <= bigpos) and
( smallneg <= zero) and
( smallneg <= smallpos) and
( smallneg <= bigpos) and
( zero <= smallpos) and
( zero <= bigpos) and
( smallpos <= bigpos) and
( bigneg <= bigneg) and
( smallneg <= smallneg) and
( zero <= zero) and
( smallpos <= smallpos) and
( bigpos <= bigpos) and
( not(bigneg > smallneg)) and
( not(bigneg > zero)) and
( not(bigneg > smallpos)) and
( not(bigneg > bigpos)) and
( not(smallneg > zero)) and
( not(smallneg > smallpos)) and
( not(smallneg > bigpos)) and
( not(zero > smallpos)) and
( not(zero > bigpos)) and
( not(smallpos > bigpos)) and
( not(bigneg > bigneg)) and
( not(smallneg > smallneg)) and
( not(zero > zero)) and
( not(smallpos > smallpos)) and
( not(bigpos > bigpos)) )
report "***PASSED TEST: c07s02b02x00p02n01i01985"
severity NOTE;
assert ( ( bigneg < smallneg) and
( bigneg < zero) and
( bigneg < smallpos) and
( bigneg < bigpos) and
( smallneg < zero) and
( smallneg < smallpos) and
( smallneg < bigpos) and
( zero < smallpos) and
( zero < bigpos) and
( smallpos < bigpos) and
( not(bigneg >= smallneg)) and
( not(bigneg >= zero)) and
( not(bigneg >= smallpos)) and
( not(bigneg >= bigpos)) and
( not(smallneg >= zero)) and
( not(smallneg >= smallpos)) and
( not(smallneg >= bigpos)) and
( not(zero >= smallpos)) and
( not(zero >= bigpos)) and
( not(smallpos >= bigpos)) and
( bigneg <= smallneg) and
( bigneg <= zero) and
( bigneg <= smallpos) and
( bigneg <= bigpos) and
( smallneg <= zero) and
( smallneg <= smallpos) and
( smallneg <= bigpos) and
( zero <= smallpos) and
( zero <= bigpos) and
( smallpos <= bigpos) and
( bigneg <= bigneg) and
( smallneg <= smallneg) and
( zero <= zero) and
( smallpos <= smallpos) and
( bigpos <= bigpos) and
( not(bigneg > smallneg)) and
( not(bigneg > zero)) and
( not(bigneg > smallpos)) and
( not(bigneg > bigpos)) and
( not(smallneg > zero)) and
( not(smallneg > smallpos)) and
( not(smallneg > bigpos)) and
( not(zero > smallpos)) and
( not(zero > bigpos)) and
( not(smallpos > bigpos)) and
( not(bigneg > bigneg)) and
( not(smallneg > smallneg)) and
( not(zero > zero)) and
( not(smallpos > smallpos)) and
( not(bigpos > bigpos)) )
report "***FAILED TEST: c07s02b02x00p02n01i01985 - Relational operators truth table test for data type of Integer failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p02n01i01985arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1985.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p02n01i01985ent IS
END c07s02b02x00p02n01i01985ent;
ARCHITECTURE c07s02b02x00p02n01i01985arch OF c07s02b02x00p02n01i01985ent IS
BEGIN
TESTING: PROCESS
constant meg : integer := 1000000;
variable bigpos : integer := 2000 * meg;
variable bigneg : integer := -2000 * meg;
variable smallpos : integer := 2000;
variable smallneg : integer := -2000;
variable zero : integer := 0;
BEGIN
assert NOT( ( bigneg < smallneg) and
( bigneg < zero) and
( bigneg < smallpos) and
( bigneg < bigpos) and
( smallneg < zero) and
( smallneg < smallpos) and
( smallneg < bigpos) and
( zero < smallpos) and
( zero < bigpos) and
( smallpos < bigpos) and
( not(bigneg >= smallneg)) and
( not(bigneg >= zero)) and
( not(bigneg >= smallpos)) and
( not(bigneg >= bigpos)) and
( not(smallneg >= zero)) and
( not(smallneg >= smallpos)) and
( not(smallneg >= bigpos)) and
( not(zero >= smallpos)) and
( not(zero >= bigpos)) and
( not(smallpos >= bigpos)) and
( bigneg <= smallneg) and
( bigneg <= zero) and
( bigneg <= smallpos) and
( bigneg <= bigpos) and
( smallneg <= zero) and
( smallneg <= smallpos) and
( smallneg <= bigpos) and
( zero <= smallpos) and
( zero <= bigpos) and
( smallpos <= bigpos) and
( bigneg <= bigneg) and
( smallneg <= smallneg) and
( zero <= zero) and
( smallpos <= smallpos) and
( bigpos <= bigpos) and
( not(bigneg > smallneg)) and
( not(bigneg > zero)) and
( not(bigneg > smallpos)) and
( not(bigneg > bigpos)) and
( not(smallneg > zero)) and
( not(smallneg > smallpos)) and
( not(smallneg > bigpos)) and
( not(zero > smallpos)) and
( not(zero > bigpos)) and
( not(smallpos > bigpos)) and
( not(bigneg > bigneg)) and
( not(smallneg > smallneg)) and
( not(zero > zero)) and
( not(smallpos > smallpos)) and
( not(bigpos > bigpos)) )
report "***PASSED TEST: c07s02b02x00p02n01i01985"
severity NOTE;
assert ( ( bigneg < smallneg) and
( bigneg < zero) and
( bigneg < smallpos) and
( bigneg < bigpos) and
( smallneg < zero) and
( smallneg < smallpos) and
( smallneg < bigpos) and
( zero < smallpos) and
( zero < bigpos) and
( smallpos < bigpos) and
( not(bigneg >= smallneg)) and
( not(bigneg >= zero)) and
( not(bigneg >= smallpos)) and
( not(bigneg >= bigpos)) and
( not(smallneg >= zero)) and
( not(smallneg >= smallpos)) and
( not(smallneg >= bigpos)) and
( not(zero >= smallpos)) and
( not(zero >= bigpos)) and
( not(smallpos >= bigpos)) and
( bigneg <= smallneg) and
( bigneg <= zero) and
( bigneg <= smallpos) and
( bigneg <= bigpos) and
( smallneg <= zero) and
( smallneg <= smallpos) and
( smallneg <= bigpos) and
( zero <= smallpos) and
( zero <= bigpos) and
( smallpos <= bigpos) and
( bigneg <= bigneg) and
( smallneg <= smallneg) and
( zero <= zero) and
( smallpos <= smallpos) and
( bigpos <= bigpos) and
( not(bigneg > smallneg)) and
( not(bigneg > zero)) and
( not(bigneg > smallpos)) and
( not(bigneg > bigpos)) and
( not(smallneg > zero)) and
( not(smallneg > smallpos)) and
( not(smallneg > bigpos)) and
( not(zero > smallpos)) and
( not(zero > bigpos)) and
( not(smallpos > bigpos)) and
( not(bigneg > bigneg)) and
( not(smallneg > smallneg)) and
( not(zero > zero)) and
( not(smallpos > smallpos)) and
( not(bigpos > bigpos)) )
report "***FAILED TEST: c07s02b02x00p02n01i01985 - Relational operators truth table test for data type of Integer failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p02n01i01985arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1985.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p02n01i01985ent IS
END c07s02b02x00p02n01i01985ent;
ARCHITECTURE c07s02b02x00p02n01i01985arch OF c07s02b02x00p02n01i01985ent IS
BEGIN
TESTING: PROCESS
constant meg : integer := 1000000;
variable bigpos : integer := 2000 * meg;
variable bigneg : integer := -2000 * meg;
variable smallpos : integer := 2000;
variable smallneg : integer := -2000;
variable zero : integer := 0;
BEGIN
assert NOT( ( bigneg < smallneg) and
( bigneg < zero) and
( bigneg < smallpos) and
( bigneg < bigpos) and
( smallneg < zero) and
( smallneg < smallpos) and
( smallneg < bigpos) and
( zero < smallpos) and
( zero < bigpos) and
( smallpos < bigpos) and
( not(bigneg >= smallneg)) and
( not(bigneg >= zero)) and
( not(bigneg >= smallpos)) and
( not(bigneg >= bigpos)) and
( not(smallneg >= zero)) and
( not(smallneg >= smallpos)) and
( not(smallneg >= bigpos)) and
( not(zero >= smallpos)) and
( not(zero >= bigpos)) and
( not(smallpos >= bigpos)) and
( bigneg <= smallneg) and
( bigneg <= zero) and
( bigneg <= smallpos) and
( bigneg <= bigpos) and
( smallneg <= zero) and
( smallneg <= smallpos) and
( smallneg <= bigpos) and
( zero <= smallpos) and
( zero <= bigpos) and
( smallpos <= bigpos) and
( bigneg <= bigneg) and
( smallneg <= smallneg) and
( zero <= zero) and
( smallpos <= smallpos) and
( bigpos <= bigpos) and
( not(bigneg > smallneg)) and
( not(bigneg > zero)) and
( not(bigneg > smallpos)) and
( not(bigneg > bigpos)) and
( not(smallneg > zero)) and
( not(smallneg > smallpos)) and
( not(smallneg > bigpos)) and
( not(zero > smallpos)) and
( not(zero > bigpos)) and
( not(smallpos > bigpos)) and
( not(bigneg > bigneg)) and
( not(smallneg > smallneg)) and
( not(zero > zero)) and
( not(smallpos > smallpos)) and
( not(bigpos > bigpos)) )
report "***PASSED TEST: c07s02b02x00p02n01i01985"
severity NOTE;
assert ( ( bigneg < smallneg) and
( bigneg < zero) and
( bigneg < smallpos) and
( bigneg < bigpos) and
( smallneg < zero) and
( smallneg < smallpos) and
( smallneg < bigpos) and
( zero < smallpos) and
( zero < bigpos) and
( smallpos < bigpos) and
( not(bigneg >= smallneg)) and
( not(bigneg >= zero)) and
( not(bigneg >= smallpos)) and
( not(bigneg >= bigpos)) and
( not(smallneg >= zero)) and
( not(smallneg >= smallpos)) and
( not(smallneg >= bigpos)) and
( not(zero >= smallpos)) and
( not(zero >= bigpos)) and
( not(smallpos >= bigpos)) and
( bigneg <= smallneg) and
( bigneg <= zero) and
( bigneg <= smallpos) and
( bigneg <= bigpos) and
( smallneg <= zero) and
( smallneg <= smallpos) and
( smallneg <= bigpos) and
( zero <= smallpos) and
( zero <= bigpos) and
( smallpos <= bigpos) and
( bigneg <= bigneg) and
( smallneg <= smallneg) and
( zero <= zero) and
( smallpos <= smallpos) and
( bigpos <= bigpos) and
( not(bigneg > smallneg)) and
( not(bigneg > zero)) and
( not(bigneg > smallpos)) and
( not(bigneg > bigpos)) and
( not(smallneg > zero)) and
( not(smallneg > smallpos)) and
( not(smallneg > bigpos)) and
( not(zero > smallpos)) and
( not(zero > bigpos)) and
( not(smallpos > bigpos)) and
( not(bigneg > bigneg)) and
( not(smallneg > smallneg)) and
( not(zero > zero)) and
( not(smallpos > smallpos)) and
( not(bigpos > bigpos)) )
report "***FAILED TEST: c07s02b02x00p02n01i01985 - Relational operators truth table test for data type of Integer failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p02n01i01985arch;
|
architecture RTL of ENTITY_NAME is
type T_FLAG_TYPE is protected -- protected type declaration
procedure init (foo : real);
impure function myfunct return boolean;
end protected T_FLAG_TYPE;
begin
end architecture RTL;
|
architecture RTL of FIFO is
TYPE state_machine is (idle, write, read, done);
-- Violations below
TYPE state_machine is (idle, write, read, done);
begin
end architecture RTL;
|
-- $Id: comlib.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: comlib
-- Description: communication components
--
-- Dependencies: -
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-09-17 410 1.4 now numeric_std clean; use for crc8 'A6' polynomial
-- of Koopman et al.; crc8_update(_tbl) now function
-- 2011-07-30 400 1.3 added byte2word, word2byte
-- 2007-10-12 88 1.2.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-07-08 65 1.2 added procedure crc8_update_tbl
-- 2007-06-29 61 1.1.1 rename for crc8 SALT->INIT
-- 2007-06-17 58 1.1 add crc8
-- 2007-06-03 45 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
package comlib is
component byte2word is -- 2 byte -> 1 word stream converter
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv8; -- input data (byte)
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv16; -- output data (word)
VAL : out slbit; -- read valid
HOLD : in slbit; -- read hold
ODD : out slbit -- odd byte pending
);
end component;
component word2byte is -- 1 word -> 2 byte stream converter
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv16; -- input data (word)
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv8; -- output data (byte)
VAL : out slbit; -- read valid
HOLD : in slbit; -- read hold
ODD : out slbit -- odd byte pending
);
end component;
component cdata2byte is -- 9bit comma,data -> byte stream
generic (
CPREF : slv4 := "1000"; -- comma prefix
NCOMM : positive := 4); -- number of comma chars
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv9; -- input data; bit 8 = komma flag
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv8; -- output data
VAL : out slbit; -- read valid
HOLD : in slbit -- read hold
);
end component;
component byte2cdata is -- byte stream -> 9bit comma,data
generic (
CPREF : slv4 := "1000"; -- comma prefix
NCOMM : positive := 4); -- number of comma chars
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv8; -- input data
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv9; -- output data; bit 8 = komma flag
VAL : out slbit; -- read valid
HOLD : in slbit -- read hold
);
end component;
component crc8 is -- crc-8 generator, checker
generic (
INIT: slv8 := "00000000"); -- initial state of crc register
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ENA : in slbit; -- update enable
DI : in slv8; -- input data
CRC : out slv8 -- crc code
);
end component;
function crc8_update (crc : in slv8; data : in slv8) return slv8;
function crc8_update_tbl (crc : in slv8; data : in slv8) return slv8;
end package comlib;
-- ----------------------------------------------------------------------------
package body comlib is
function crc8_update (crc: in slv8; data: in slv8) return slv8 is
variable t : slv8 := (others=>'0');
variable n : slv8 := (others=>'0');
begin
t := data xor crc;
n(0) := t(5) xor t(4) xor t(2) xor t(0);
n(1) := t(6) xor t(5) xor t(3) xor t(1);
n(2) := t(7) xor t(6) xor t(5) xor t(0);
n(3) := t(7) xor t(6) xor t(5) xor t(4) xor t(2) xor t(1) xor t(0);
n(4) := t(7) xor t(6) xor t(5) xor t(3) xor t(2) xor t(1);
n(5) := t(7) xor t(6) xor t(4) xor t(3) xor t(2);
n(6) := t(7) xor t(3) xor t(2) xor t(0);
n(7) := t(4) xor t(3) xor t(1);
return n;
end function crc8_update;
function crc8_update_tbl (crc: in slv8; data: in slv8) return slv8 is
type crc8_tbl_type is array (0 to 255) of integer;
variable crc8_tbl : crc8_tbl_type := -- generated with gen_crc8_tbl
( 0, 77, 154, 215, 121, 52, 227, 174, -- 00-07
242, 191, 104, 37, 139, 198, 17, 92, -- 00-0f
169, 228, 51, 126, 208, 157, 74, 7, -- 10-17
91, 22, 193, 140, 34, 111, 184, 245, -- 10-1f
31, 82, 133, 200, 102, 43, 252, 177, -- 20-27
237, 160, 119, 58, 148, 217, 14, 67, -- 20-2f
182, 251, 44, 97, 207, 130, 85, 24, -- 30-37
68, 9, 222, 147, 61, 112, 167, 234, -- 30-3f
62, 115, 164, 233, 71, 10, 221, 144, -- 40-47
204, 129, 86, 27, 181, 248, 47, 98, -- 40-4f
151, 218, 13, 64, 238, 163, 116, 57, -- 50-57
101, 40, 255, 178, 28, 81, 134, 203, -- 50-5f
33, 108, 187, 246, 88, 21, 194, 143, -- 60-67
211, 158, 73, 4, 170, 231, 48, 125, -- 60-6f
136, 197, 18, 95, 241, 188, 107, 38, -- 70-70
122, 55, 224, 173, 3, 78, 153, 212, -- 70-7f
124, 49, 230, 171, 5, 72, 159, 210, -- 80-87
142, 195, 20, 89, 247, 186, 109, 32, -- 80-8f
213, 152, 79, 2, 172, 225, 54, 123, -- 90-97
39, 106, 189, 240, 94, 19, 196, 137, -- 90-9f
99, 46, 249, 180, 26, 87, 128, 205, -- a0-a7
145, 220, 11, 70, 232, 165, 114, 63, -- a0-af
202, 135, 80, 29, 179, 254, 41, 100, -- b0-b7
56, 117, 162, 239, 65, 12, 219, 150, -- b0-bf
66, 15, 216, 149, 59, 118, 161, 236, -- c0-c7
176, 253, 42, 103, 201, 132, 83, 30, -- c0-cf
235, 166, 113, 60, 146, 223, 8, 69, -- d0-d7
25, 84, 131, 206, 96, 45, 250, 183, -- d0-df
93, 16, 199, 138, 36, 105, 190, 243, -- e0-e7
175, 226, 53, 120, 214, 155, 76, 1, -- e0-ef
244, 185, 110, 35, 141, 192, 23, 90, -- f0-f7
6, 75, 156, 209, 127, 50, 229, 168 -- f0-ff
);
begin
return slv(to_unsigned(crc8_tbl(to_integer(unsigned(data xor crc))), 8));
end function crc8_update_tbl;
end package body comlib;
|
-- $Id: comlib.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: comlib
-- Description: communication components
--
-- Dependencies: -
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-09-17 410 1.4 now numeric_std clean; use for crc8 'A6' polynomial
-- of Koopman et al.; crc8_update(_tbl) now function
-- 2011-07-30 400 1.3 added byte2word, word2byte
-- 2007-10-12 88 1.2.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-07-08 65 1.2 added procedure crc8_update_tbl
-- 2007-06-29 61 1.1.1 rename for crc8 SALT->INIT
-- 2007-06-17 58 1.1 add crc8
-- 2007-06-03 45 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
package comlib is
component byte2word is -- 2 byte -> 1 word stream converter
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv8; -- input data (byte)
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv16; -- output data (word)
VAL : out slbit; -- read valid
HOLD : in slbit; -- read hold
ODD : out slbit -- odd byte pending
);
end component;
component word2byte is -- 1 word -> 2 byte stream converter
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv16; -- input data (word)
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv8; -- output data (byte)
VAL : out slbit; -- read valid
HOLD : in slbit; -- read hold
ODD : out slbit -- odd byte pending
);
end component;
component cdata2byte is -- 9bit comma,data -> byte stream
generic (
CPREF : slv4 := "1000"; -- comma prefix
NCOMM : positive := 4); -- number of comma chars
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv9; -- input data; bit 8 = komma flag
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv8; -- output data
VAL : out slbit; -- read valid
HOLD : in slbit -- read hold
);
end component;
component byte2cdata is -- byte stream -> 9bit comma,data
generic (
CPREF : slv4 := "1000"; -- comma prefix
NCOMM : positive := 4); -- number of comma chars
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv8; -- input data
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv9; -- output data; bit 8 = komma flag
VAL : out slbit; -- read valid
HOLD : in slbit -- read hold
);
end component;
component crc8 is -- crc-8 generator, checker
generic (
INIT: slv8 := "00000000"); -- initial state of crc register
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ENA : in slbit; -- update enable
DI : in slv8; -- input data
CRC : out slv8 -- crc code
);
end component;
function crc8_update (crc : in slv8; data : in slv8) return slv8;
function crc8_update_tbl (crc : in slv8; data : in slv8) return slv8;
end package comlib;
-- ----------------------------------------------------------------------------
package body comlib is
function crc8_update (crc: in slv8; data: in slv8) return slv8 is
variable t : slv8 := (others=>'0');
variable n : slv8 := (others=>'0');
begin
t := data xor crc;
n(0) := t(5) xor t(4) xor t(2) xor t(0);
n(1) := t(6) xor t(5) xor t(3) xor t(1);
n(2) := t(7) xor t(6) xor t(5) xor t(0);
n(3) := t(7) xor t(6) xor t(5) xor t(4) xor t(2) xor t(1) xor t(0);
n(4) := t(7) xor t(6) xor t(5) xor t(3) xor t(2) xor t(1);
n(5) := t(7) xor t(6) xor t(4) xor t(3) xor t(2);
n(6) := t(7) xor t(3) xor t(2) xor t(0);
n(7) := t(4) xor t(3) xor t(1);
return n;
end function crc8_update;
function crc8_update_tbl (crc: in slv8; data: in slv8) return slv8 is
type crc8_tbl_type is array (0 to 255) of integer;
variable crc8_tbl : crc8_tbl_type := -- generated with gen_crc8_tbl
( 0, 77, 154, 215, 121, 52, 227, 174, -- 00-07
242, 191, 104, 37, 139, 198, 17, 92, -- 00-0f
169, 228, 51, 126, 208, 157, 74, 7, -- 10-17
91, 22, 193, 140, 34, 111, 184, 245, -- 10-1f
31, 82, 133, 200, 102, 43, 252, 177, -- 20-27
237, 160, 119, 58, 148, 217, 14, 67, -- 20-2f
182, 251, 44, 97, 207, 130, 85, 24, -- 30-37
68, 9, 222, 147, 61, 112, 167, 234, -- 30-3f
62, 115, 164, 233, 71, 10, 221, 144, -- 40-47
204, 129, 86, 27, 181, 248, 47, 98, -- 40-4f
151, 218, 13, 64, 238, 163, 116, 57, -- 50-57
101, 40, 255, 178, 28, 81, 134, 203, -- 50-5f
33, 108, 187, 246, 88, 21, 194, 143, -- 60-67
211, 158, 73, 4, 170, 231, 48, 125, -- 60-6f
136, 197, 18, 95, 241, 188, 107, 38, -- 70-70
122, 55, 224, 173, 3, 78, 153, 212, -- 70-7f
124, 49, 230, 171, 5, 72, 159, 210, -- 80-87
142, 195, 20, 89, 247, 186, 109, 32, -- 80-8f
213, 152, 79, 2, 172, 225, 54, 123, -- 90-97
39, 106, 189, 240, 94, 19, 196, 137, -- 90-9f
99, 46, 249, 180, 26, 87, 128, 205, -- a0-a7
145, 220, 11, 70, 232, 165, 114, 63, -- a0-af
202, 135, 80, 29, 179, 254, 41, 100, -- b0-b7
56, 117, 162, 239, 65, 12, 219, 150, -- b0-bf
66, 15, 216, 149, 59, 118, 161, 236, -- c0-c7
176, 253, 42, 103, 201, 132, 83, 30, -- c0-cf
235, 166, 113, 60, 146, 223, 8, 69, -- d0-d7
25, 84, 131, 206, 96, 45, 250, 183, -- d0-df
93, 16, 199, 138, 36, 105, 190, 243, -- e0-e7
175, 226, 53, 120, 214, 155, 76, 1, -- e0-ef
244, 185, 110, 35, 141, 192, 23, 90, -- f0-f7
6, 75, 156, 209, 127, 50, 229, 168 -- f0-ff
);
begin
return slv(to_unsigned(crc8_tbl(to_integer(unsigned(data xor crc))), 8));
end function crc8_update_tbl;
end package body comlib;
|
-- megafunction wizard: %ALTFP_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altfp_compare
-- ============================================================
-- File Name: fp_cmp.vhd
-- Megafunction Name(s):
-- altfp_compare
--
-- Simulation Library Files(s):
--
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altfp_compare CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone II" PIPELINE=1 WIDTH_EXP=8 WIDTH_MAN=23 aclr agb clk_en clock dataa datab
--VERSION_BEGIN 9.1SP2 cbx_altfp_compare 2010:03:24:20:34:20:SJ cbx_cycloneii 2010:03:24:20:34:20:SJ cbx_lpm_add_sub 2010:03:24:20:34:20:SJ cbx_lpm_compare 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ cbx_stratix 2010:03:24:20:34:20:SJ cbx_stratixii 2010:03:24:20:34:20:SJ VERSION_END
LIBRARY lpm;
USE lpm.all;
--synthesis_resources = lpm_compare 4 reg 1
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_cmp_altfp_compare_v5c IS
PORT
(
aclr : IN STD_LOGIC := '0';
agb : OUT STD_LOGIC;
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_cmp_altfp_compare_v5c;
ARCHITECTURE RTL OF fp_cmp_altfp_compare_v5c IS
SIGNAL out_agb_w_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_cmpr1_aeb : STD_LOGIC;
SIGNAL wire_cmpr1_agb : STD_LOGIC;
SIGNAL wire_cmpr2_aeb : STD_LOGIC;
SIGNAL wire_cmpr2_agb : STD_LOGIC;
SIGNAL wire_cmpr3_aeb : STD_LOGIC;
SIGNAL wire_cmpr3_agb : STD_LOGIC;
SIGNAL wire_cmpr4_aeb : STD_LOGIC;
SIGNAL wire_cmpr4_agb : STD_LOGIC;
SIGNAL wire_w_lg_w304w305w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w316w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_agb_w_dffe2_wo314w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_flip_outputs_dffe2_wo310w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range11w17w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range21w27w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range31w37w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range41w47w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range51w57w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range61w67w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range71w77w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range14w19w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range24w29w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range34w39w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range44w49w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range54w59w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range64w69w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range74w79w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_aeb_range233w245w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_aeb_range237w247w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_aeb_range241w249w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_eq_grp_range251w253w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_eq_grp_range251w259w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_eq_grp_range254w255w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_eq_grp_range254w261w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_eq_grp_range256w263w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w304w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_aligned_dataa_sign_adjusted_dffe2_wo313w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_both_inputs_zero_dffe2_wo312w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_a_not_zero_dffe1_wo293w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_agb_w_dffe2_wo309w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_b_not_zero_dffe1_wo294w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_zero_w296w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_zero_w298w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_out_aeb_w308w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_out_unordered_w302w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w304w305w306w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range141w142w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range147w148w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range157w158w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range163w164w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range169w170w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range175w176w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range181w182w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range187w188w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range193w194w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range87w88w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range199w200w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range205w206w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range211w212w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range11w12w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range21w22w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range31w32w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range41w42w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range51w52w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range61w62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range93w94w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range71w72w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range99w100w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range105w106w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range111w112w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range117w118w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range123w124w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range129w130w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range135w136w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range144w145w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range150w151w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range160w161w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range166w167w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range172w173w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range178w179w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range184w185w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range190w191w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range196w197w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range90w91w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range202w203w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range208w209w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range214w215w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range14w15w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range24w25w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range34w35w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range44w45w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range54w55w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range64w65w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range96w97w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range74w75w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range102w103w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range108w109w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range114w115w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range120w121w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range126w127w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range132w133w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range138w139w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_agb_tmp_w_range265w267w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_agb_tmp_w_range268w269w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_agb_tmp_w_range270w271w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_a_not_zero_dffe1_wo_range285w286w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_b_not_zero_dffe1_wo_range288w289w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_aligned_dataa_sign_adjusted_dffe2_wo303w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL aligned_dataa_sign_adjusted_dffe2_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_adjusted_dffe2_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_adjusted_w : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe1_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe1_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_w : STD_LOGIC;
SIGNAL aligned_dataa_w : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL aligned_datab_sign_adjusted_dffe2_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_adjusted_dffe2_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_adjusted_w : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe1_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe1_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_w : STD_LOGIC;
SIGNAL aligned_datab_w : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL both_inputs_zero : STD_LOGIC;
SIGNAL both_inputs_zero_dffe2_wi : STD_LOGIC;
SIGNAL both_inputs_zero_dffe2_wo : STD_LOGIC;
SIGNAL exp_a_all_one_dffe1_wi : STD_LOGIC;
SIGNAL exp_a_all_one_dffe1_wo : STD_LOGIC;
SIGNAL exp_a_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_a_not_zero_dffe1_wi : STD_LOGIC;
SIGNAL exp_a_not_zero_dffe1_wo : STD_LOGIC;
SIGNAL exp_a_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_aeb : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL exp_aeb_tmp_w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL exp_aeb_w : STD_LOGIC;
SIGNAL exp_aeb_w_dffe2_wi : STD_LOGIC;
SIGNAL exp_aeb_w_dffe2_wo : STD_LOGIC;
SIGNAL exp_agb : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL exp_agb_tmp_w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL exp_agb_w : STD_LOGIC;
SIGNAL exp_agb_w_dffe2_wi : STD_LOGIC;
SIGNAL exp_agb_w_dffe2_wo : STD_LOGIC;
SIGNAL exp_b_all_one_dffe1_wi : STD_LOGIC;
SIGNAL exp_b_all_one_dffe1_wo : STD_LOGIC;
SIGNAL exp_b_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_b_not_zero_dffe1_wi : STD_LOGIC;
SIGNAL exp_b_not_zero_dffe1_wo : STD_LOGIC;
SIGNAL exp_b_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_eq_grp : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL exp_eq_gt_grp : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL flip_outputs_dffe2_wi : STD_LOGIC;
SIGNAL flip_outputs_dffe2_wo : STD_LOGIC;
SIGNAL flip_outputs_w : STD_LOGIC;
SIGNAL input_dataa_nan_dffe2_wi : STD_LOGIC;
SIGNAL input_dataa_nan_dffe2_wo : STD_LOGIC;
SIGNAL input_dataa_nan_w : STD_LOGIC;
SIGNAL input_dataa_zero_w : STD_LOGIC;
SIGNAL input_datab_nan_dffe2_wi : STD_LOGIC;
SIGNAL input_datab_nan_dffe2_wo : STD_LOGIC;
SIGNAL input_datab_nan_w : STD_LOGIC;
SIGNAL input_datab_zero_w : STD_LOGIC;
SIGNAL man_a_not_zero_dffe1_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL man_a_not_zero_dffe1_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL man_a_not_zero_merge_w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL man_a_not_zero_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_b_not_zero_dffe1_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL man_b_not_zero_dffe1_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL man_b_not_zero_merge_w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL man_b_not_zero_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL out_aeb_w : STD_LOGIC;
SIGNAL out_agb_dffe3_wi : STD_LOGIC;
SIGNAL out_agb_dffe3_wo : STD_LOGIC;
SIGNAL out_agb_w : STD_LOGIC;
SIGNAL out_unordered_w : STD_LOGIC;
SIGNAL wire_w_dataa_range141w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range147w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range157w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range163w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range169w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range175w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range181w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range187w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range193w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range87w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range199w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range205w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range211w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range11w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range21w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range31w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range41w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range51w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range93w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range71w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range99w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range105w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range111w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range117w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range123w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range129w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range135w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range144w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range150w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range160w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range166w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range172w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range178w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range184w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range190w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range196w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range90w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range202w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range208w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range214w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range14w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range24w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range34w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range44w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range54w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range64w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range96w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range74w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range102w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range108w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range114w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range120w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range126w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range132w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range138w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range7w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range18w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range28w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range38w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range48w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range58w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range68w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range2w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range13w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range23w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range33w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range43w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range53w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range63w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_aeb_range233w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_aeb_range237w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_aeb_range241w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_aeb_tmp_w_range243w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_aeb_tmp_w_range246w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_aeb_tmp_w_range248w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_agb_range234w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_agb_range238w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_agb_range242w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_agb_tmp_w_range265w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_agb_tmp_w_range268w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_agb_tmp_w_range270w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range9w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range20w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range30w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range40w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range50w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range70w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range5w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range16w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range26w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range36w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range46w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range56w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range66w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_eq_grp_range251w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_eq_grp_range254w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_eq_grp_range256w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_eq_gt_grp_range260w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_eq_gt_grp_range262w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_eq_gt_grp_range264w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_dffe1_wo_range285w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_merge_w_range280w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range82w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range143w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range154w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range159w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range165w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range171w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range177w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range183w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range189w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range195w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range89w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range201w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range207w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range95w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range101w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range107w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range113w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range119w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range125w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range131w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range137w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_dffe1_wo_range288w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_merge_w_range283w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range85w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range146w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range156w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range162w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range168w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range174w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range180w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range186w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range192w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range198w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range92w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range204w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range210w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range98w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range104w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range110w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range116w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range122w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range128w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range134w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range140w : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT lpm_compare
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_compare"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aeb : OUT STD_LOGIC;
agb : OUT STD_LOGIC;
ageb : OUT STD_LOGIC;
alb : OUT STD_LOGIC;
aleb : OUT STD_LOGIC;
aneb : OUT STD_LOGIC;
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
wire_w_lg_w304w305w(0) <= wire_w304w(0) AND exp_aeb_w_dffe2_wo;
wire_w316w(0) <= wire_w_lg_aligned_dataa_sign_adjusted_dffe2_wo313w(0) AND aligned_datab_sign_adjusted_dffe2_wo;
wire_w_lg_exp_agb_w_dffe2_wo314w(0) <= exp_agb_w_dffe2_wo AND wire_w_lg_aligned_dataa_sign_adjusted_dffe2_wo313w(0);
wire_w_lg_flip_outputs_dffe2_wo310w(0) <= flip_outputs_dffe2_wo AND wire_w_lg_exp_agb_w_dffe2_wo309w(0);
wire_w_lg_w_dataa_range11w17w(0) <= wire_w_dataa_range11w(0) AND wire_w_exp_a_all_one_w_range7w(0);
wire_w_lg_w_dataa_range21w27w(0) <= wire_w_dataa_range21w(0) AND wire_w_exp_a_all_one_w_range18w(0);
wire_w_lg_w_dataa_range31w37w(0) <= wire_w_dataa_range31w(0) AND wire_w_exp_a_all_one_w_range28w(0);
wire_w_lg_w_dataa_range41w47w(0) <= wire_w_dataa_range41w(0) AND wire_w_exp_a_all_one_w_range38w(0);
wire_w_lg_w_dataa_range51w57w(0) <= wire_w_dataa_range51w(0) AND wire_w_exp_a_all_one_w_range48w(0);
wire_w_lg_w_dataa_range61w67w(0) <= wire_w_dataa_range61w(0) AND wire_w_exp_a_all_one_w_range58w(0);
wire_w_lg_w_dataa_range71w77w(0) <= wire_w_dataa_range71w(0) AND wire_w_exp_a_all_one_w_range68w(0);
wire_w_lg_w_datab_range14w19w(0) <= wire_w_datab_range14w(0) AND wire_w_exp_b_all_one_w_range9w(0);
wire_w_lg_w_datab_range24w29w(0) <= wire_w_datab_range24w(0) AND wire_w_exp_b_all_one_w_range20w(0);
wire_w_lg_w_datab_range34w39w(0) <= wire_w_datab_range34w(0) AND wire_w_exp_b_all_one_w_range30w(0);
wire_w_lg_w_datab_range44w49w(0) <= wire_w_datab_range44w(0) AND wire_w_exp_b_all_one_w_range40w(0);
wire_w_lg_w_datab_range54w59w(0) <= wire_w_datab_range54w(0) AND wire_w_exp_b_all_one_w_range50w(0);
wire_w_lg_w_datab_range64w69w(0) <= wire_w_datab_range64w(0) AND wire_w_exp_b_all_one_w_range60w(0);
wire_w_lg_w_datab_range74w79w(0) <= wire_w_datab_range74w(0) AND wire_w_exp_b_all_one_w_range70w(0);
wire_w_lg_w_exp_aeb_range233w245w(0) <= wire_w_exp_aeb_range233w(0) AND wire_w_exp_aeb_tmp_w_range243w(0);
wire_w_lg_w_exp_aeb_range237w247w(0) <= wire_w_exp_aeb_range237w(0) AND wire_w_exp_aeb_tmp_w_range246w(0);
wire_w_lg_w_exp_aeb_range241w249w(0) <= wire_w_exp_aeb_range241w(0) AND wire_w_exp_aeb_tmp_w_range248w(0);
wire_w_lg_w_exp_eq_grp_range251w253w(0) <= wire_w_exp_eq_grp_range251w(0) AND wire_w_exp_aeb_range233w(0);
wire_w_lg_w_exp_eq_grp_range251w259w(0) <= wire_w_exp_eq_grp_range251w(0) AND wire_w_exp_agb_range234w(0);
wire_w_lg_w_exp_eq_grp_range254w255w(0) <= wire_w_exp_eq_grp_range254w(0) AND wire_w_exp_aeb_range237w(0);
wire_w_lg_w_exp_eq_grp_range254w261w(0) <= wire_w_exp_eq_grp_range254w(0) AND wire_w_exp_agb_range238w(0);
wire_w_lg_w_exp_eq_grp_range256w263w(0) <= wire_w_exp_eq_grp_range256w(0) AND wire_w_exp_agb_range242w(0);
wire_w304w(0) <= NOT wire_w_lg_aligned_dataa_sign_adjusted_dffe2_wo303w(0);
wire_w_lg_aligned_dataa_sign_adjusted_dffe2_wo313w(0) <= NOT aligned_dataa_sign_adjusted_dffe2_wo;
wire_w_lg_both_inputs_zero_dffe2_wo312w(0) <= NOT both_inputs_zero_dffe2_wo;
wire_w_lg_exp_a_not_zero_dffe1_wo293w(0) <= NOT exp_a_not_zero_dffe1_wo;
wire_w_lg_exp_agb_w_dffe2_wo309w(0) <= NOT exp_agb_w_dffe2_wo;
wire_w_lg_exp_b_not_zero_dffe1_wo294w(0) <= NOT exp_b_not_zero_dffe1_wo;
wire_w_lg_input_dataa_zero_w296w(0) <= NOT input_dataa_zero_w;
wire_w_lg_input_datab_zero_w298w(0) <= NOT input_datab_zero_w;
wire_w_lg_out_aeb_w308w(0) <= NOT out_aeb_w;
wire_w_lg_out_unordered_w302w(0) <= NOT out_unordered_w;
wire_w_lg_w_lg_w304w305w306w(0) <= wire_w_lg_w304w305w(0) OR both_inputs_zero_dffe2_wo;
wire_w_lg_w_dataa_range141w142w(0) <= wire_w_dataa_range141w(0) OR wire_w_man_a_not_zero_w_range137w(0);
wire_w_lg_w_dataa_range147w148w(0) <= wire_w_dataa_range147w(0) OR wire_w_man_a_not_zero_w_range143w(0);
wire_w_lg_w_dataa_range157w158w(0) <= wire_w_dataa_range157w(0) OR wire_w_man_a_not_zero_w_range154w(0);
wire_w_lg_w_dataa_range163w164w(0) <= wire_w_dataa_range163w(0) OR wire_w_man_a_not_zero_w_range159w(0);
wire_w_lg_w_dataa_range169w170w(0) <= wire_w_dataa_range169w(0) OR wire_w_man_a_not_zero_w_range165w(0);
wire_w_lg_w_dataa_range175w176w(0) <= wire_w_dataa_range175w(0) OR wire_w_man_a_not_zero_w_range171w(0);
wire_w_lg_w_dataa_range181w182w(0) <= wire_w_dataa_range181w(0) OR wire_w_man_a_not_zero_w_range177w(0);
wire_w_lg_w_dataa_range187w188w(0) <= wire_w_dataa_range187w(0) OR wire_w_man_a_not_zero_w_range183w(0);
wire_w_lg_w_dataa_range193w194w(0) <= wire_w_dataa_range193w(0) OR wire_w_man_a_not_zero_w_range189w(0);
wire_w_lg_w_dataa_range87w88w(0) <= wire_w_dataa_range87w(0) OR wire_w_man_a_not_zero_w_range82w(0);
wire_w_lg_w_dataa_range199w200w(0) <= wire_w_dataa_range199w(0) OR wire_w_man_a_not_zero_w_range195w(0);
wire_w_lg_w_dataa_range205w206w(0) <= wire_w_dataa_range205w(0) OR wire_w_man_a_not_zero_w_range201w(0);
wire_w_lg_w_dataa_range211w212w(0) <= wire_w_dataa_range211w(0) OR wire_w_man_a_not_zero_w_range207w(0);
wire_w_lg_w_dataa_range11w12w(0) <= wire_w_dataa_range11w(0) OR wire_w_exp_a_not_zero_w_range2w(0);
wire_w_lg_w_dataa_range21w22w(0) <= wire_w_dataa_range21w(0) OR wire_w_exp_a_not_zero_w_range13w(0);
wire_w_lg_w_dataa_range31w32w(0) <= wire_w_dataa_range31w(0) OR wire_w_exp_a_not_zero_w_range23w(0);
wire_w_lg_w_dataa_range41w42w(0) <= wire_w_dataa_range41w(0) OR wire_w_exp_a_not_zero_w_range33w(0);
wire_w_lg_w_dataa_range51w52w(0) <= wire_w_dataa_range51w(0) OR wire_w_exp_a_not_zero_w_range43w(0);
wire_w_lg_w_dataa_range61w62w(0) <= wire_w_dataa_range61w(0) OR wire_w_exp_a_not_zero_w_range53w(0);
wire_w_lg_w_dataa_range93w94w(0) <= wire_w_dataa_range93w(0) OR wire_w_man_a_not_zero_w_range89w(0);
wire_w_lg_w_dataa_range71w72w(0) <= wire_w_dataa_range71w(0) OR wire_w_exp_a_not_zero_w_range63w(0);
wire_w_lg_w_dataa_range99w100w(0) <= wire_w_dataa_range99w(0) OR wire_w_man_a_not_zero_w_range95w(0);
wire_w_lg_w_dataa_range105w106w(0) <= wire_w_dataa_range105w(0) OR wire_w_man_a_not_zero_w_range101w(0);
wire_w_lg_w_dataa_range111w112w(0) <= wire_w_dataa_range111w(0) OR wire_w_man_a_not_zero_w_range107w(0);
wire_w_lg_w_dataa_range117w118w(0) <= wire_w_dataa_range117w(0) OR wire_w_man_a_not_zero_w_range113w(0);
wire_w_lg_w_dataa_range123w124w(0) <= wire_w_dataa_range123w(0) OR wire_w_man_a_not_zero_w_range119w(0);
wire_w_lg_w_dataa_range129w130w(0) <= wire_w_dataa_range129w(0) OR wire_w_man_a_not_zero_w_range125w(0);
wire_w_lg_w_dataa_range135w136w(0) <= wire_w_dataa_range135w(0) OR wire_w_man_a_not_zero_w_range131w(0);
wire_w_lg_w_datab_range144w145w(0) <= wire_w_datab_range144w(0) OR wire_w_man_b_not_zero_w_range140w(0);
wire_w_lg_w_datab_range150w151w(0) <= wire_w_datab_range150w(0) OR wire_w_man_b_not_zero_w_range146w(0);
wire_w_lg_w_datab_range160w161w(0) <= wire_w_datab_range160w(0) OR wire_w_man_b_not_zero_w_range156w(0);
wire_w_lg_w_datab_range166w167w(0) <= wire_w_datab_range166w(0) OR wire_w_man_b_not_zero_w_range162w(0);
wire_w_lg_w_datab_range172w173w(0) <= wire_w_datab_range172w(0) OR wire_w_man_b_not_zero_w_range168w(0);
wire_w_lg_w_datab_range178w179w(0) <= wire_w_datab_range178w(0) OR wire_w_man_b_not_zero_w_range174w(0);
wire_w_lg_w_datab_range184w185w(0) <= wire_w_datab_range184w(0) OR wire_w_man_b_not_zero_w_range180w(0);
wire_w_lg_w_datab_range190w191w(0) <= wire_w_datab_range190w(0) OR wire_w_man_b_not_zero_w_range186w(0);
wire_w_lg_w_datab_range196w197w(0) <= wire_w_datab_range196w(0) OR wire_w_man_b_not_zero_w_range192w(0);
wire_w_lg_w_datab_range90w91w(0) <= wire_w_datab_range90w(0) OR wire_w_man_b_not_zero_w_range85w(0);
wire_w_lg_w_datab_range202w203w(0) <= wire_w_datab_range202w(0) OR wire_w_man_b_not_zero_w_range198w(0);
wire_w_lg_w_datab_range208w209w(0) <= wire_w_datab_range208w(0) OR wire_w_man_b_not_zero_w_range204w(0);
wire_w_lg_w_datab_range214w215w(0) <= wire_w_datab_range214w(0) OR wire_w_man_b_not_zero_w_range210w(0);
wire_w_lg_w_datab_range14w15w(0) <= wire_w_datab_range14w(0) OR wire_w_exp_b_not_zero_w_range5w(0);
wire_w_lg_w_datab_range24w25w(0) <= wire_w_datab_range24w(0) OR wire_w_exp_b_not_zero_w_range16w(0);
wire_w_lg_w_datab_range34w35w(0) <= wire_w_datab_range34w(0) OR wire_w_exp_b_not_zero_w_range26w(0);
wire_w_lg_w_datab_range44w45w(0) <= wire_w_datab_range44w(0) OR wire_w_exp_b_not_zero_w_range36w(0);
wire_w_lg_w_datab_range54w55w(0) <= wire_w_datab_range54w(0) OR wire_w_exp_b_not_zero_w_range46w(0);
wire_w_lg_w_datab_range64w65w(0) <= wire_w_datab_range64w(0) OR wire_w_exp_b_not_zero_w_range56w(0);
wire_w_lg_w_datab_range96w97w(0) <= wire_w_datab_range96w(0) OR wire_w_man_b_not_zero_w_range92w(0);
wire_w_lg_w_datab_range74w75w(0) <= wire_w_datab_range74w(0) OR wire_w_exp_b_not_zero_w_range66w(0);
wire_w_lg_w_datab_range102w103w(0) <= wire_w_datab_range102w(0) OR wire_w_man_b_not_zero_w_range98w(0);
wire_w_lg_w_datab_range108w109w(0) <= wire_w_datab_range108w(0) OR wire_w_man_b_not_zero_w_range104w(0);
wire_w_lg_w_datab_range114w115w(0) <= wire_w_datab_range114w(0) OR wire_w_man_b_not_zero_w_range110w(0);
wire_w_lg_w_datab_range120w121w(0) <= wire_w_datab_range120w(0) OR wire_w_man_b_not_zero_w_range116w(0);
wire_w_lg_w_datab_range126w127w(0) <= wire_w_datab_range126w(0) OR wire_w_man_b_not_zero_w_range122w(0);
wire_w_lg_w_datab_range132w133w(0) <= wire_w_datab_range132w(0) OR wire_w_man_b_not_zero_w_range128w(0);
wire_w_lg_w_datab_range138w139w(0) <= wire_w_datab_range138w(0) OR wire_w_man_b_not_zero_w_range134w(0);
wire_w_lg_w_exp_agb_tmp_w_range265w267w(0) <= wire_w_exp_agb_tmp_w_range265w(0) OR wire_w_exp_eq_gt_grp_range260w(0);
wire_w_lg_w_exp_agb_tmp_w_range268w269w(0) <= wire_w_exp_agb_tmp_w_range268w(0) OR wire_w_exp_eq_gt_grp_range262w(0);
wire_w_lg_w_exp_agb_tmp_w_range270w271w(0) <= wire_w_exp_agb_tmp_w_range270w(0) OR wire_w_exp_eq_gt_grp_range264w(0);
wire_w_lg_w_man_a_not_zero_dffe1_wo_range285w286w(0) <= wire_w_man_a_not_zero_dffe1_wo_range285w(0) OR wire_w_man_a_not_zero_merge_w_range280w(0);
wire_w_lg_w_man_b_not_zero_dffe1_wo_range288w289w(0) <= wire_w_man_b_not_zero_dffe1_wo_range288w(0) OR wire_w_man_b_not_zero_merge_w_range283w(0);
wire_w_lg_aligned_dataa_sign_adjusted_dffe2_wo303w(0) <= aligned_dataa_sign_adjusted_dffe2_wo XOR aligned_datab_sign_adjusted_dffe2_wo;
agb <= out_agb_dffe3_wo;
aligned_dataa_sign_adjusted_dffe2_wi <= aligned_dataa_sign_adjusted_w;
aligned_dataa_sign_adjusted_dffe2_wo <= aligned_dataa_sign_adjusted_dffe2_wi;
aligned_dataa_sign_adjusted_w <= (aligned_dataa_sign_dffe1_wo AND wire_w_lg_input_dataa_zero_w296w(0));
aligned_dataa_sign_dffe1_wi <= aligned_dataa_sign_w;
aligned_dataa_sign_dffe1_wo <= aligned_dataa_sign_dffe1_wi;
aligned_dataa_sign_w <= dataa(31);
aligned_dataa_w <= ( dataa(30 DOWNTO 0));
aligned_datab_sign_adjusted_dffe2_wi <= aligned_datab_sign_adjusted_w;
aligned_datab_sign_adjusted_dffe2_wo <= aligned_datab_sign_adjusted_dffe2_wi;
aligned_datab_sign_adjusted_w <= (aligned_datab_sign_dffe1_wo AND wire_w_lg_input_datab_zero_w298w(0));
aligned_datab_sign_dffe1_wi <= aligned_datab_sign_w;
aligned_datab_sign_dffe1_wo <= aligned_datab_sign_dffe1_wi;
aligned_datab_sign_w <= datab(31);
aligned_datab_w <= ( datab(30 DOWNTO 0));
both_inputs_zero <= (input_dataa_zero_w AND input_datab_zero_w);
both_inputs_zero_dffe2_wi <= both_inputs_zero;
both_inputs_zero_dffe2_wo <= both_inputs_zero_dffe2_wi;
exp_a_all_one_dffe1_wi <= exp_a_all_one_w(7);
exp_a_all_one_dffe1_wo <= exp_a_all_one_dffe1_wi;
exp_a_all_one_w <= ( wire_w_lg_w_dataa_range71w77w & wire_w_lg_w_dataa_range61w67w & wire_w_lg_w_dataa_range51w57w & wire_w_lg_w_dataa_range41w47w & wire_w_lg_w_dataa_range31w37w & wire_w_lg_w_dataa_range21w27w & wire_w_lg_w_dataa_range11w17w & dataa(23));
exp_a_not_zero_dffe1_wi <= exp_a_not_zero_w(7);
exp_a_not_zero_dffe1_wo <= exp_a_not_zero_dffe1_wi;
exp_a_not_zero_w <= ( wire_w_lg_w_dataa_range71w72w & wire_w_lg_w_dataa_range61w62w & wire_w_lg_w_dataa_range51w52w & wire_w_lg_w_dataa_range41w42w & wire_w_lg_w_dataa_range31w32w & wire_w_lg_w_dataa_range21w22w & wire_w_lg_w_dataa_range11w12w & dataa(23));
exp_aeb <= ( wire_cmpr4_aeb & wire_cmpr3_aeb & wire_cmpr2_aeb & wire_cmpr1_aeb);
exp_aeb_tmp_w <= ( wire_w_lg_w_exp_aeb_range241w249w & wire_w_lg_w_exp_aeb_range237w247w & wire_w_lg_w_exp_aeb_range233w245w & exp_aeb(0));
exp_aeb_w <= exp_aeb_tmp_w(3);
exp_aeb_w_dffe2_wi <= exp_aeb_w;
exp_aeb_w_dffe2_wo <= exp_aeb_w_dffe2_wi;
exp_agb <= ( wire_cmpr4_agb & wire_cmpr3_agb & wire_cmpr2_agb & wire_cmpr1_agb);
exp_agb_tmp_w <= ( wire_w_lg_w_exp_agb_tmp_w_range270w271w & wire_w_lg_w_exp_agb_tmp_w_range268w269w & wire_w_lg_w_exp_agb_tmp_w_range265w267w & exp_eq_gt_grp(0));
exp_agb_w <= exp_agb_tmp_w(3);
exp_agb_w_dffe2_wi <= exp_agb_w;
exp_agb_w_dffe2_wo <= exp_agb_w_dffe2_wi;
exp_b_all_one_dffe1_wi <= exp_b_all_one_w(7);
exp_b_all_one_dffe1_wo <= exp_b_all_one_dffe1_wi;
exp_b_all_one_w <= ( wire_w_lg_w_datab_range74w79w & wire_w_lg_w_datab_range64w69w & wire_w_lg_w_datab_range54w59w & wire_w_lg_w_datab_range44w49w & wire_w_lg_w_datab_range34w39w & wire_w_lg_w_datab_range24w29w & wire_w_lg_w_datab_range14w19w & datab(23));
exp_b_not_zero_dffe1_wi <= exp_b_not_zero_w(7);
exp_b_not_zero_dffe1_wo <= exp_b_not_zero_dffe1_wi;
exp_b_not_zero_w <= ( wire_w_lg_w_datab_range74w75w & wire_w_lg_w_datab_range64w65w & wire_w_lg_w_datab_range54w55w & wire_w_lg_w_datab_range44w45w & wire_w_lg_w_datab_range34w35w & wire_w_lg_w_datab_range24w25w & wire_w_lg_w_datab_range14w15w & datab(23));
exp_eq_grp <= ( wire_w_lg_w_exp_eq_grp_range254w255w & wire_w_lg_w_exp_eq_grp_range251w253w & exp_aeb(0));
exp_eq_gt_grp <= ( wire_w_lg_w_exp_eq_grp_range256w263w & wire_w_lg_w_exp_eq_grp_range254w261w & wire_w_lg_w_exp_eq_grp_range251w259w & exp_agb(0));
flip_outputs_dffe2_wi <= flip_outputs_w;
flip_outputs_dffe2_wo <= flip_outputs_dffe2_wi;
flip_outputs_w <= (aligned_dataa_sign_adjusted_w AND aligned_datab_sign_adjusted_w);
input_dataa_nan_dffe2_wi <= input_dataa_nan_w;
input_dataa_nan_dffe2_wo <= input_dataa_nan_dffe2_wi;
input_dataa_nan_w <= (exp_a_all_one_dffe1_wo AND man_a_not_zero_merge_w(1));
input_dataa_zero_w <= wire_w_lg_exp_a_not_zero_dffe1_wo293w(0);
input_datab_nan_dffe2_wi <= input_datab_nan_w;
input_datab_nan_dffe2_wo <= input_datab_nan_dffe2_wi;
input_datab_nan_w <= (exp_b_all_one_dffe1_wo AND man_b_not_zero_merge_w(1));
input_datab_zero_w <= wire_w_lg_exp_b_not_zero_dffe1_wo294w(0);
man_a_not_zero_dffe1_wi <= ( man_a_not_zero_w(22) & man_a_not_zero_w(11));
man_a_not_zero_dffe1_wo <= man_a_not_zero_dffe1_wi;
man_a_not_zero_merge_w <= ( wire_w_lg_w_man_a_not_zero_dffe1_wo_range285w286w & man_a_not_zero_dffe1_wo(0));
man_a_not_zero_w <= ( wire_w_lg_w_dataa_range211w212w & wire_w_lg_w_dataa_range205w206w & wire_w_lg_w_dataa_range199w200w & wire_w_lg_w_dataa_range193w194w & wire_w_lg_w_dataa_range187w188w & wire_w_lg_w_dataa_range181w182w & wire_w_lg_w_dataa_range175w176w & wire_w_lg_w_dataa_range169w170w & wire_w_lg_w_dataa_range163w164w & wire_w_lg_w_dataa_range157w158w & dataa(12) & wire_w_lg_w_dataa_range147w148w & wire_w_lg_w_dataa_range141w142w & wire_w_lg_w_dataa_range135w136w & wire_w_lg_w_dataa_range129w130w & wire_w_lg_w_dataa_range123w124w & wire_w_lg_w_dataa_range117w118w & wire_w_lg_w_dataa_range111w112w & wire_w_lg_w_dataa_range105w106w & wire_w_lg_w_dataa_range99w100w & wire_w_lg_w_dataa_range93w94w & wire_w_lg_w_dataa_range87w88w & dataa(0));
man_b_not_zero_dffe1_wi <= ( man_b_not_zero_w(22) & man_b_not_zero_w(11));
man_b_not_zero_dffe1_wo <= man_b_not_zero_dffe1_wi;
man_b_not_zero_merge_w <= ( wire_w_lg_w_man_b_not_zero_dffe1_wo_range288w289w & man_b_not_zero_dffe1_wo(0));
man_b_not_zero_w <= ( wire_w_lg_w_datab_range214w215w & wire_w_lg_w_datab_range208w209w & wire_w_lg_w_datab_range202w203w & wire_w_lg_w_datab_range196w197w & wire_w_lg_w_datab_range190w191w & wire_w_lg_w_datab_range184w185w & wire_w_lg_w_datab_range178w179w & wire_w_lg_w_datab_range172w173w & wire_w_lg_w_datab_range166w167w & wire_w_lg_w_datab_range160w161w & datab(12) & wire_w_lg_w_datab_range150w151w & wire_w_lg_w_datab_range144w145w & wire_w_lg_w_datab_range138w139w & wire_w_lg_w_datab_range132w133w & wire_w_lg_w_datab_range126w127w & wire_w_lg_w_datab_range120w121w & wire_w_lg_w_datab_range114w115w & wire_w_lg_w_datab_range108w109w & wire_w_lg_w_datab_range102w103w & wire_w_lg_w_datab_range96w97w & wire_w_lg_w_datab_range90w91w & datab(0));
out_aeb_w <= (wire_w_lg_w_lg_w304w305w306w(0) AND wire_w_lg_out_unordered_w302w(0));
out_agb_dffe3_wi <= out_agb_w;
out_agb_dffe3_wo <= out_agb_w_dffe3;
out_agb_w <= (((wire_w316w(0) OR (wire_w_lg_exp_agb_w_dffe2_wo314w(0) AND wire_w_lg_both_inputs_zero_dffe2_wo312w(0))) OR (wire_w_lg_flip_outputs_dffe2_wo310w(0) AND wire_w_lg_out_aeb_w308w(0))) AND wire_w_lg_out_unordered_w302w(0));
out_unordered_w <= (input_dataa_nan_dffe2_wo OR input_datab_nan_dffe2_wo);
wire_w_dataa_range141w(0) <= dataa(10);
wire_w_dataa_range147w(0) <= dataa(11);
wire_w_dataa_range157w(0) <= dataa(13);
wire_w_dataa_range163w(0) <= dataa(14);
wire_w_dataa_range169w(0) <= dataa(15);
wire_w_dataa_range175w(0) <= dataa(16);
wire_w_dataa_range181w(0) <= dataa(17);
wire_w_dataa_range187w(0) <= dataa(18);
wire_w_dataa_range193w(0) <= dataa(19);
wire_w_dataa_range87w(0) <= dataa(1);
wire_w_dataa_range199w(0) <= dataa(20);
wire_w_dataa_range205w(0) <= dataa(21);
wire_w_dataa_range211w(0) <= dataa(22);
wire_w_dataa_range11w(0) <= dataa(24);
wire_w_dataa_range21w(0) <= dataa(25);
wire_w_dataa_range31w(0) <= dataa(26);
wire_w_dataa_range41w(0) <= dataa(27);
wire_w_dataa_range51w(0) <= dataa(28);
wire_w_dataa_range61w(0) <= dataa(29);
wire_w_dataa_range93w(0) <= dataa(2);
wire_w_dataa_range71w(0) <= dataa(30);
wire_w_dataa_range99w(0) <= dataa(3);
wire_w_dataa_range105w(0) <= dataa(4);
wire_w_dataa_range111w(0) <= dataa(5);
wire_w_dataa_range117w(0) <= dataa(6);
wire_w_dataa_range123w(0) <= dataa(7);
wire_w_dataa_range129w(0) <= dataa(8);
wire_w_dataa_range135w(0) <= dataa(9);
wire_w_datab_range144w(0) <= datab(10);
wire_w_datab_range150w(0) <= datab(11);
wire_w_datab_range160w(0) <= datab(13);
wire_w_datab_range166w(0) <= datab(14);
wire_w_datab_range172w(0) <= datab(15);
wire_w_datab_range178w(0) <= datab(16);
wire_w_datab_range184w(0) <= datab(17);
wire_w_datab_range190w(0) <= datab(18);
wire_w_datab_range196w(0) <= datab(19);
wire_w_datab_range90w(0) <= datab(1);
wire_w_datab_range202w(0) <= datab(20);
wire_w_datab_range208w(0) <= datab(21);
wire_w_datab_range214w(0) <= datab(22);
wire_w_datab_range14w(0) <= datab(24);
wire_w_datab_range24w(0) <= datab(25);
wire_w_datab_range34w(0) <= datab(26);
wire_w_datab_range44w(0) <= datab(27);
wire_w_datab_range54w(0) <= datab(28);
wire_w_datab_range64w(0) <= datab(29);
wire_w_datab_range96w(0) <= datab(2);
wire_w_datab_range74w(0) <= datab(30);
wire_w_datab_range102w(0) <= datab(3);
wire_w_datab_range108w(0) <= datab(4);
wire_w_datab_range114w(0) <= datab(5);
wire_w_datab_range120w(0) <= datab(6);
wire_w_datab_range126w(0) <= datab(7);
wire_w_datab_range132w(0) <= datab(8);
wire_w_datab_range138w(0) <= datab(9);
wire_w_exp_a_all_one_w_range7w(0) <= exp_a_all_one_w(0);
wire_w_exp_a_all_one_w_range18w(0) <= exp_a_all_one_w(1);
wire_w_exp_a_all_one_w_range28w(0) <= exp_a_all_one_w(2);
wire_w_exp_a_all_one_w_range38w(0) <= exp_a_all_one_w(3);
wire_w_exp_a_all_one_w_range48w(0) <= exp_a_all_one_w(4);
wire_w_exp_a_all_one_w_range58w(0) <= exp_a_all_one_w(5);
wire_w_exp_a_all_one_w_range68w(0) <= exp_a_all_one_w(6);
wire_w_exp_a_not_zero_w_range2w(0) <= exp_a_not_zero_w(0);
wire_w_exp_a_not_zero_w_range13w(0) <= exp_a_not_zero_w(1);
wire_w_exp_a_not_zero_w_range23w(0) <= exp_a_not_zero_w(2);
wire_w_exp_a_not_zero_w_range33w(0) <= exp_a_not_zero_w(3);
wire_w_exp_a_not_zero_w_range43w(0) <= exp_a_not_zero_w(4);
wire_w_exp_a_not_zero_w_range53w(0) <= exp_a_not_zero_w(5);
wire_w_exp_a_not_zero_w_range63w(0) <= exp_a_not_zero_w(6);
wire_w_exp_aeb_range233w(0) <= exp_aeb(1);
wire_w_exp_aeb_range237w(0) <= exp_aeb(2);
wire_w_exp_aeb_range241w(0) <= exp_aeb(3);
wire_w_exp_aeb_tmp_w_range243w(0) <= exp_aeb_tmp_w(0);
wire_w_exp_aeb_tmp_w_range246w(0) <= exp_aeb_tmp_w(1);
wire_w_exp_aeb_tmp_w_range248w(0) <= exp_aeb_tmp_w(2);
wire_w_exp_agb_range234w(0) <= exp_agb(1);
wire_w_exp_agb_range238w(0) <= exp_agb(2);
wire_w_exp_agb_range242w(0) <= exp_agb(3);
wire_w_exp_agb_tmp_w_range265w(0) <= exp_agb_tmp_w(0);
wire_w_exp_agb_tmp_w_range268w(0) <= exp_agb_tmp_w(1);
wire_w_exp_agb_tmp_w_range270w(0) <= exp_agb_tmp_w(2);
wire_w_exp_b_all_one_w_range9w(0) <= exp_b_all_one_w(0);
wire_w_exp_b_all_one_w_range20w(0) <= exp_b_all_one_w(1);
wire_w_exp_b_all_one_w_range30w(0) <= exp_b_all_one_w(2);
wire_w_exp_b_all_one_w_range40w(0) <= exp_b_all_one_w(3);
wire_w_exp_b_all_one_w_range50w(0) <= exp_b_all_one_w(4);
wire_w_exp_b_all_one_w_range60w(0) <= exp_b_all_one_w(5);
wire_w_exp_b_all_one_w_range70w(0) <= exp_b_all_one_w(6);
wire_w_exp_b_not_zero_w_range5w(0) <= exp_b_not_zero_w(0);
wire_w_exp_b_not_zero_w_range16w(0) <= exp_b_not_zero_w(1);
wire_w_exp_b_not_zero_w_range26w(0) <= exp_b_not_zero_w(2);
wire_w_exp_b_not_zero_w_range36w(0) <= exp_b_not_zero_w(3);
wire_w_exp_b_not_zero_w_range46w(0) <= exp_b_not_zero_w(4);
wire_w_exp_b_not_zero_w_range56w(0) <= exp_b_not_zero_w(5);
wire_w_exp_b_not_zero_w_range66w(0) <= exp_b_not_zero_w(6);
wire_w_exp_eq_grp_range251w(0) <= exp_eq_grp(0);
wire_w_exp_eq_grp_range254w(0) <= exp_eq_grp(1);
wire_w_exp_eq_grp_range256w(0) <= exp_eq_grp(2);
wire_w_exp_eq_gt_grp_range260w(0) <= exp_eq_gt_grp(1);
wire_w_exp_eq_gt_grp_range262w(0) <= exp_eq_gt_grp(2);
wire_w_exp_eq_gt_grp_range264w(0) <= exp_eq_gt_grp(3);
wire_w_man_a_not_zero_dffe1_wo_range285w(0) <= man_a_not_zero_dffe1_wo(1);
wire_w_man_a_not_zero_merge_w_range280w(0) <= man_a_not_zero_merge_w(0);
wire_w_man_a_not_zero_w_range82w(0) <= man_a_not_zero_w(0);
wire_w_man_a_not_zero_w_range143w(0) <= man_a_not_zero_w(10);
wire_w_man_a_not_zero_w_range154w(0) <= man_a_not_zero_w(12);
wire_w_man_a_not_zero_w_range159w(0) <= man_a_not_zero_w(13);
wire_w_man_a_not_zero_w_range165w(0) <= man_a_not_zero_w(14);
wire_w_man_a_not_zero_w_range171w(0) <= man_a_not_zero_w(15);
wire_w_man_a_not_zero_w_range177w(0) <= man_a_not_zero_w(16);
wire_w_man_a_not_zero_w_range183w(0) <= man_a_not_zero_w(17);
wire_w_man_a_not_zero_w_range189w(0) <= man_a_not_zero_w(18);
wire_w_man_a_not_zero_w_range195w(0) <= man_a_not_zero_w(19);
wire_w_man_a_not_zero_w_range89w(0) <= man_a_not_zero_w(1);
wire_w_man_a_not_zero_w_range201w(0) <= man_a_not_zero_w(20);
wire_w_man_a_not_zero_w_range207w(0) <= man_a_not_zero_w(21);
wire_w_man_a_not_zero_w_range95w(0) <= man_a_not_zero_w(2);
wire_w_man_a_not_zero_w_range101w(0) <= man_a_not_zero_w(3);
wire_w_man_a_not_zero_w_range107w(0) <= man_a_not_zero_w(4);
wire_w_man_a_not_zero_w_range113w(0) <= man_a_not_zero_w(5);
wire_w_man_a_not_zero_w_range119w(0) <= man_a_not_zero_w(6);
wire_w_man_a_not_zero_w_range125w(0) <= man_a_not_zero_w(7);
wire_w_man_a_not_zero_w_range131w(0) <= man_a_not_zero_w(8);
wire_w_man_a_not_zero_w_range137w(0) <= man_a_not_zero_w(9);
wire_w_man_b_not_zero_dffe1_wo_range288w(0) <= man_b_not_zero_dffe1_wo(1);
wire_w_man_b_not_zero_merge_w_range283w(0) <= man_b_not_zero_merge_w(0);
wire_w_man_b_not_zero_w_range85w(0) <= man_b_not_zero_w(0);
wire_w_man_b_not_zero_w_range146w(0) <= man_b_not_zero_w(10);
wire_w_man_b_not_zero_w_range156w(0) <= man_b_not_zero_w(12);
wire_w_man_b_not_zero_w_range162w(0) <= man_b_not_zero_w(13);
wire_w_man_b_not_zero_w_range168w(0) <= man_b_not_zero_w(14);
wire_w_man_b_not_zero_w_range174w(0) <= man_b_not_zero_w(15);
wire_w_man_b_not_zero_w_range180w(0) <= man_b_not_zero_w(16);
wire_w_man_b_not_zero_w_range186w(0) <= man_b_not_zero_w(17);
wire_w_man_b_not_zero_w_range192w(0) <= man_b_not_zero_w(18);
wire_w_man_b_not_zero_w_range198w(0) <= man_b_not_zero_w(19);
wire_w_man_b_not_zero_w_range92w(0) <= man_b_not_zero_w(1);
wire_w_man_b_not_zero_w_range204w(0) <= man_b_not_zero_w(20);
wire_w_man_b_not_zero_w_range210w(0) <= man_b_not_zero_w(21);
wire_w_man_b_not_zero_w_range98w(0) <= man_b_not_zero_w(2);
wire_w_man_b_not_zero_w_range104w(0) <= man_b_not_zero_w(3);
wire_w_man_b_not_zero_w_range110w(0) <= man_b_not_zero_w(4);
wire_w_man_b_not_zero_w_range116w(0) <= man_b_not_zero_w(5);
wire_w_man_b_not_zero_w_range122w(0) <= man_b_not_zero_w(6);
wire_w_man_b_not_zero_w_range128w(0) <= man_b_not_zero_w(7);
wire_w_man_b_not_zero_w_range134w(0) <= man_b_not_zero_w(8);
wire_w_man_b_not_zero_w_range140w(0) <= man_b_not_zero_w(9);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN out_agb_w_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN out_agb_w_dffe3 <= out_agb_dffe3_wi;
END IF;
END IF;
END PROCESS;
cmpr1 : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTH => 8
)
PORT MAP (
aeb => wire_cmpr1_aeb,
agb => wire_cmpr1_agb,
dataa => aligned_dataa_w(30 DOWNTO 23),
datab => aligned_datab_w(30 DOWNTO 23)
);
cmpr2 : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTH => 8
)
PORT MAP (
aeb => wire_cmpr2_aeb,
agb => wire_cmpr2_agb,
dataa => aligned_dataa_w(22 DOWNTO 15),
datab => aligned_datab_w(22 DOWNTO 15)
);
cmpr3 : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTH => 8
)
PORT MAP (
aeb => wire_cmpr3_aeb,
agb => wire_cmpr3_agb,
dataa => aligned_dataa_w(14 DOWNTO 7),
datab => aligned_datab_w(14 DOWNTO 7)
);
cmpr4 : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTH => 7
)
PORT MAP (
aeb => wire_cmpr4_aeb,
agb => wire_cmpr4_agb,
dataa => aligned_dataa_w(6 DOWNTO 0),
datab => aligned_datab_w(6 DOWNTO 0)
);
END RTL; --fp_cmp_altfp_compare_v5c
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_cmp IS
PORT
(
aclr : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
agb : OUT STD_LOGIC
);
END fp_cmp;
ARCHITECTURE RTL OF fp_cmp IS
SIGNAL sub_wire0 : STD_LOGIC ;
COMPONENT fp_cmp_altfp_compare_v5c
PORT (
aclr : IN STD_LOGIC ;
agb : OUT STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
agb <= sub_wire0;
fp_cmp_altfp_compare_v5c_component : fp_cmp_altfp_compare_v5c
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
datab => datab,
dataa => dataa,
agb => sub_wire0
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: FPM_FORMAT NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: PIPELINE NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
-- Retrieval info: USED_PORT: agb 0 0 0 0 OUTPUT NODEFVAL "agb"
-- Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
-- Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
-- Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
-- Retrieval info: CONNECT: agb 0 0 0 0 @agb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_cmp.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_cmp.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_cmp.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_cmp.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_cmp_inst.vhd FALSE
|
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity user_io_board_controller_opbw is
generic (
C_BASEADDR: std_logic_vector(0 to 31) := X"00000000";
C_HIGHADDR: std_logic_vector(0 to 31) := X"0003FFFF";
C_OPB_AWIDTH: integer := 32;
C_OPB_DWIDTH: integer := 32
);
port (
ce: in std_logic;
opb_abus: in std_logic_vector(0 to 31);
opb_be: in std_logic_vector(0 to 3);
opb_clk: in std_logic;
opb_dbus: in std_logic_vector(0 to 31);
opb_rnw: in std_logic;
opb_rst: in std_logic;
opb_select: in std_logic;
opb_seqaddr: in std_logic;
reset: in std_logic;
cs: out std_logic;
resetlcd: out std_logic;
scl: out std_logic;
sdi: out std_logic;
sgp_dbus: out std_logic_vector(0 to 31);
sgp_errack: out std_logic;
sgp_retry: out std_logic;
sgp_toutsup: out std_logic;
sgp_xferack: out std_logic
);
end user_io_board_controller_opbw;
architecture structural of user_io_board_controller_opbw is
signal ce_x0: std_logic;
signal clk: std_logic;
signal cs_x0: std_logic;
signal opb_abus_x0: std_logic_vector(31 downto 0);
signal opb_be_x0: std_logic_vector(3 downto 0);
signal opb_dbus_x0: std_logic_vector(31 downto 0);
signal opb_rnw_x0: std_logic;
signal opb_rst_x0: std_logic;
signal opb_select_x0: std_logic;
signal opb_seqaddr_x0: std_logic;
signal reset_x0: std_logic;
signal resetlcd_x0: std_logic;
signal scl_x0: std_logic;
signal sdi_x0: std_logic;
signal sgp_dbus_x0: std_logic_vector(31 downto 0);
signal sgp_errack_x0: std_logic;
signal sgp_retry_x0: std_logic;
signal sgp_toutsup_x0: std_logic;
signal sgp_xferack_x0: std_logic;
begin
ce_x0 <= ce;
opb_abus_x0 <= opb_abus xor C_BASEADDR;
opb_be_x0 <= opb_be;
clk <= opb_clk;
opb_dbus_x0 <= opb_dbus;
opb_rnw_x0 <= opb_rnw;
opb_rst_x0 <= opb_rst;
opb_select_x0 <= opb_select;
opb_seqaddr_x0 <= opb_seqaddr;
reset_x0 <= reset;
cs <= cs_x0;
resetlcd <= resetlcd_x0;
scl <= scl_x0;
sdi <= sdi_x0;
sgp_dbus <= sgp_dbus_x0;
sgp_errack <= sgp_errack_x0;
sgp_retry <= sgp_retry_x0;
sgp_toutsup <= sgp_toutsup_x0;
sgp_xferack <= sgp_xferack_x0;
sysgen_dut: entity work.user_io_board_controller_cw
port map (
ce => ce_x0,
clk => clk,
opb_abus => opb_abus_x0,
opb_be => opb_be_x0,
opb_dbus => opb_dbus_x0,
opb_rnw => opb_rnw_x0,
opb_rst => opb_rst_x0,
opb_select => opb_select_x0,
opb_seqaddr => opb_seqaddr_x0,
reset => reset_x0,
cs => cs_x0,
resetlcd => resetlcd_x0,
scl => scl_x0,
sdi => sdi_x0,
sgp_dbus => sgp_dbus_x0,
sgp_errack => sgp_errack_x0,
sgp_retry => sgp_retry_x0,
sgp_toutsup => sgp_toutsup_x0,
sgp_xferack => sgp_xferack_x0
);
end structural;
|
entity conv1 is
end entity;
architecture test of conv1 is
type my_bit_vector is array (natural range <>) of bit;
signal x : bit_vector(7 downto 0);
signal y : my_bit_vector(3 downto 0);
begin
process is
begin
x <= X"ab";
wait for 1 ns;
y <= my_bit_vector(x(3 downto 0));
wait for 1 ns;
assert y = X"b";
wait;
end process;
end architecture;
|
entity conv1 is
end entity;
architecture test of conv1 is
type my_bit_vector is array (natural range <>) of bit;
signal x : bit_vector(7 downto 0);
signal y : my_bit_vector(3 downto 0);
begin
process is
begin
x <= X"ab";
wait for 1 ns;
y <= my_bit_vector(x(3 downto 0));
wait for 1 ns;
assert y = X"b";
wait;
end process;
end architecture;
|
entity conv1 is
end entity;
architecture test of conv1 is
type my_bit_vector is array (natural range <>) of bit;
signal x : bit_vector(7 downto 0);
signal y : my_bit_vector(3 downto 0);
begin
process is
begin
x <= X"ab";
wait for 1 ns;
y <= my_bit_vector(x(3 downto 0));
wait for 1 ns;
assert y = X"b";
wait;
end process;
end architecture;
|
entity conv1 is
end entity;
architecture test of conv1 is
type my_bit_vector is array (natural range <>) of bit;
signal x : bit_vector(7 downto 0);
signal y : my_bit_vector(3 downto 0);
begin
process is
begin
x <= X"ab";
wait for 1 ns;
y <= my_bit_vector(x(3 downto 0));
wait for 1 ns;
assert y = X"b";
wait;
end process;
end architecture;
|
entity conv1 is
end entity;
architecture test of conv1 is
type my_bit_vector is array (natural range <>) of bit;
signal x : bit_vector(7 downto 0);
signal y : my_bit_vector(3 downto 0);
begin
process is
begin
x <= X"ab";
wait for 1 ns;
y <= my_bit_vector(x(3 downto 0));
wait for 1 ns;
assert y = X"b";
wait;
end process;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3093.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s01b00x00p02n01i03093ent IS
END c05s01b00x00p02n01i03093ent;
ARCHITECTURE c05s01b00x00p02n01i03093arch OF c05s01b00x00p02n01i03093ent IS
type a is range 1 to 10;
attribute left : integer;
attribute left of a : is 5; --- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c05s01b00x00p02n01i03093 - Missing entity class."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s01b00x00p02n01i03093arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3093.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s01b00x00p02n01i03093ent IS
END c05s01b00x00p02n01i03093ent;
ARCHITECTURE c05s01b00x00p02n01i03093arch OF c05s01b00x00p02n01i03093ent IS
type a is range 1 to 10;
attribute left : integer;
attribute left of a : is 5; --- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c05s01b00x00p02n01i03093 - Missing entity class."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s01b00x00p02n01i03093arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3093.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s01b00x00p02n01i03093ent IS
END c05s01b00x00p02n01i03093ent;
ARCHITECTURE c05s01b00x00p02n01i03093arch OF c05s01b00x00p02n01i03093ent IS
type a is range 1 to 10;
attribute left : integer;
attribute left of a : is 5; --- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c05s01b00x00p02n01i03093 - Missing entity class."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s01b00x00p02n01i03093arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--
-- SDRAM controller. This uses the Altera sdr_sdram component to interface with
-- the SDRAM, and couple it to the 68k bus.
--
entity BusSDRAM is
PORT(
-- system signals
reset: IN std_logic;
reset_n: IN std_logic;
sdram_clk: IN std_logic; -- 100 MHz
-- CPU bus
bus_cs: IN std_logic; -- when high, outs is Z
bus_clk: IN std_logic; -- clock for bus
bus_address: IN std_logic_vector(22 downto 0);
bus_data: INOUT std_logic_vector(15 downto 0);
bus_rw: IN std_logic;
bus_as: IN std_logic;
bus_dtack: OUT std_logic;
bus_uds: IN std_logic;
bus_lds: IN std_logic;
-- connect to SDRAM
DRAM_CS_N: OUT std_logic;
DRAM_WE_N: OUT std_logic;
DRAM_CAS_N: OUT std_logic;
DRAM_RAS_N: OUT std_logic;
DRAM_ADDR: OUT std_logic_vector(11 downto 0);
DRAM_BA_0: OUT std_logic;
DRAM_BA_1: OUT std_logic;
DRAM_CKE: OUT std_logic;
DRAM_CLK: OUT std_logic;
DRAM_DQ: INOUT std_logic_vector(15 downto 0);
DRAM_LDQM: OUT std_logic;
DRAM_UDQM: OUT std_logic
);
end BusSDRAM;
architecture behavioral of BusSDRAM is
signal sdr_addr: std_logic_vector(22 downto 0);
signal sdr_cmd: std_logic_vector(2 downto 0);
signal sdr_cmdack: std_logic;
signal sdr_din: std_logic_vector(15 downto 0);
signal sdr_dout: std_logic_vector(15 downto 0);
signal sdr_data_mask: std_logic_vector(1 downto 0);
signal dram_bank: std_logic_vector(1 downto 0);
signal dram_cs: std_logic_vector(1 downto 0);
signal dram_dqm: std_logic_vector(1 downto 0);
begin
-- contat separate bank signals into one
DRAM_BA_0 <= dram_bank(0);
DRAM_BA_1 <= dram_bank(1);
DRAM_CS_N <= dram_cs(0);
DRAM_LDQM <= dram_dqm(0);
DRAM_UDQM <= dram_dqm(1);
-- SDRAM controller
u_sdram_controller: entity work.sdr_sdram(RTL)
port map(
CLK => sdram_clk,
RESET_N => reset_N,
-- interfacing with controller
ADDR => sdr_addr,
DATAIN => sdr_din,
DATAOUT => sdr_dout,
DM => sdr_data_mask, -- data masks
CMD => sdr_cmd,
CMDACK => sdr_cmdack,
-- to SDRAM
SA => DRAM_ADDR,
BA => dram_bank,
CS_N => dram_cs,
CKE => DRAM_CKE,
RAS_N => DRAM_RAS_N,
CAS_N => DRAM_CAS_N,
WE_N => DRAM_WE_N,
DQ => DRAM_DQ,
DQM => dram_dqm
);
-- 68k bus interface
process(bus_clk, reset, bus_cs, bus_rw)
begin
-- in reset state, don't drive the bus
if reset='0' then
bus_data <= (others => 'Z');
bus_dtack <= 'Z';
elsif rising_edge(bus_clk) then
-- is chip select asserted?
if bus_cs='0' then
-- write cycle
if bus_rw='0' then
bus_dtack <= '1';
-- read cycle
else
bus_dtack <= '1';
end if;
-- not selected: don't drive bus
else
bus_data <= (others => 'Z');
bus_dtack <= 'Z';
end if;
end if;
end process;
end behavioral; |
-- Fairly simple VGA (640x480 @ 60hz) output for the machine.
-- Connected to some memory so that it can get bytes in and then outputs the right RGB based
-- on the corresponding bit value in each byte. Fakes the cellophane overlays from the original
-- if colourOutput is high.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity video is
port (
clkin25mhz : in STD_LOGIC;
red : out STD_LOGIC_VECTOR (3 downto 0);
green : out STD_LOGIC_VECTOR (3 downto 0);
blue : out STD_LOGIC_VECTOR (3 downto 0);
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
vramAddr : out STD_LOGIC_VECTOR (12 downto 0);
vramData : in STD_LOGIC_VECTOR (7 downto 0);
colourOutput : in STD_LOGIC
);
end video;
architecture Behavioral of video is
signal hcount : unsigned(9 downto 0) := (others => '0');
signal vcount : unsigned(9 downto 0) := (others => '0');
signal hindex : unsigned(7 downto 0) := (others => '0');
signal vindex : unsigned(7 downto 0) := "11111111";
begin
vramAddr <= std_logic_vector(hindex) & std_logic_vector(vindex(7 downto 3));
process (clkin25mhz)
begin
if rising_edge(clkin25mhz) then
if (hcount = 799) then
hcount <= (others => '0');
hindex <= (others => '0');
if vcount = 524 then
vcount <= (others => '0');
else
vcount <= vcount + 1;
if (vcount > 111 and vcount < 368) then
vindex <= vindex - 1;
else
vindex <= "11111111";
end if;
end if;
else
hcount <= hcount + 1;
end if;
if vcount >= 490 and vcount < 492 then
vsync <= '0';
else
vsync <= '1';
end if;
if hcount >= 656 and hcount < 752 then
hsync <= '0';
else
hsync <= '1';
end if;
if (vcount > 111 and vcount < 368 and hcount > 207 and hcount < 432) then
if (colourOutput = '1' and vramData(to_integer(unsigned(vindex(2 downto 0)))) = '1') then
if ((vcount > 111+191 and vcount < 111+241)
or (vcount >= 352 and hcount > 232 and hcount < 344)) then
red<="0000";
green<="1111";
blue<="0000";
elsif (vcount > 143 and vcount < 161) then -- was > 142
red<="1111";
green<="0000";
blue<="0000";
else
red<="1111";
green<="1111";
blue<="1111";
end if;
else
red <= "0000";
green <= "0000";
blue <= "0000";
end if;
hindex <= hindex + 1;
else
red <= "0000";
green <= "0000";
blue <= "0000";
end if;
end if;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.command_if_pkg.all;
entity command_protocol is
port (
clock : in std_logic;
reset : in std_logic;
-- io interface for local cpu
io_req : in t_io_req; -- we get a 2K range
io_resp : out t_io_resp;
-- C64 side interface
slot_req : in t_slot_req;
slot_resp : out t_slot_resp;
freeze : out std_logic;
-- block memory
address : out unsigned(10 downto 0);
rdata : in std_logic_vector(7 downto 0);
wdata : out std_logic_vector(7 downto 0);
en : out std_logic;
we : out std_logic );
end entity;
-- How does the protocol work?
-- The Ultimate software initializes the command and response buffers that the C64 can write to.
-- Each buffer has a start address, an end address, and a current read/write pointer as seen
-- from the C64 side.
-- The C64 can write into the command buffer and set a handshake flag. The 1541U software
-- triggers on the flag, and reads the write pointer, copies the command, and stores the
-- result and status in their respective buffers, and sets the respective handshake flags back
-- to the C64. The buffers on the ultimate side are direct mapped; on the C64 side, each
-- buffer has its own data register. One bidirectional register (on the C64 side) acts as
-- handshake register. Command queueing is not supported.
-- Protocol:
-- There are 4 states:
-- 00: Ultimate is ready and waiting for new command
-- 01: C64 has written data into the Ultimate command buffer, and the Ultimate is processing it
-- 11: Ultimate has processed the command and replied with data/status. This is not the last data.
-- 10: Ultimate has processed the command and replied with data/status. This is the last data.
-- The status register (seen by the C64) holds the following bits:
-- Bit 7: Response data available
-- Bit 6: Status data available
-- Bit 5..4: State
-- Bit 3: Error flag (write 1 to clear)
-- Bit 2: Abort flag set (cleared by Ultimate software)
-- Bit 1: Data accepted bit set (cleared by Ultimate software)
-- Bit 0: New command (set when new command is written, should NOT be used by C64)
architecture gideon of command_protocol is
signal enabled : std_logic;
signal slot_base : unsigned(6 downto 0);
signal do_write : std_logic;
signal command_pointer : unsigned(10 downto 0);
signal response_pointer : unsigned(10 downto 0);
signal status_pointer : unsigned(10 downto 0);
signal command_length : unsigned(10 downto 0);
signal response_length : unsigned(10 downto 0);
signal status_length : unsigned(10 downto 0);
-- signal response_valid : std_logic;
-- signal status_valid : std_logic;
signal rdata_resp : std_logic_vector(7 downto 0);
signal rdata_stat : std_logic_vector(7 downto 0);
signal slot_status : std_logic_vector(7 downto 0);
alias response_valid : std_logic is slot_status(7);
alias status_valid : std_logic is slot_status(6);
alias state : std_logic_vector(1 downto 0) is slot_status(5 downto 4);
alias error_busy : std_logic is slot_status(3);
alias handshake_in : std_logic_vector(2 downto 0) is slot_status(2 downto 0);
begin
-- assert false report integer'image(to_integer(c_cmd_if_command_buffer_end)) severity warning;
-- assert false report integer'image(to_integer(c_cmd_if_response_buffer_end)) severity warning;
-- assert false report integer'image(to_integer(c_cmd_if_status_buffer_end)) severity warning;
--
command_length <= command_pointer - c_cmd_if_command_buffer_addr;
with slot_req.bus_address(1 downto 0) select slot_resp.data <=
slot_status when c_cif_slot_control,
X"C9" when c_cif_slot_command,
rdata_resp when c_cif_slot_response,
rdata_stat when others;
rdata_resp <= rdata when response_valid='1' else X"00";
rdata_stat <= rdata when status_valid='1' else X"00";
slot_resp.reg_output <= enabled when slot_req.bus_address(8 downto 2) = slot_base else '0';
slot_resp.irq <= '0';
-- signals to RAM
en <= enabled;
we <= do_write;
wdata <= slot_req.data;
address <= command_pointer when do_write='1' else
response_pointer when slot_req.bus_address(0)='0' else
status_pointer;
do_write <= '1' when slot_req.io_write='1' and slot_req.io_address(8 downto 0) = (slot_base & c_cif_slot_command) else '0';
p_control: process(clock)
procedure reset_response is
begin
response_pointer <= c_cmd_if_response_buffer_addr;
status_pointer <= c_cmd_if_status_buffer_addr;
response_length <= (others => '0');
status_length <= (others => '0');
end procedure;
begin
if rising_edge(clock) then
if (response_pointer - c_cmd_if_response_buffer_addr) < response_length then
response_valid <= '1';
else
response_valid <= '0';
end if;
if (status_pointer - c_cmd_if_status_buffer_addr) < status_length then
status_valid <= '1';
else
status_valid <= '0';
end if;
if (slot_req.io_address(8 downto 2) = slot_base) and (enabled = '1') then
if slot_req.io_write='1' then
case slot_req.io_address(1 downto 0) is
when c_cif_slot_command =>
if command_pointer /= c_cmd_if_command_buffer_end then
command_pointer <= command_pointer + 1;
end if;
when c_cif_slot_control =>
if slot_req.data(3)='1' then
error_busy <= '0';
end if;
if slot_req.data(0)='1' then
freeze <= slot_req.data(7);
if state = "00" then
reset_response;
state <= "01";
handshake_in(0) <= '1';
else
error_busy <= '1';
end if;
end if;
if slot_req.data(1)='1' and state(1) = '1' then -- data accept
handshake_in(1) <= '1'; -- data accepted, only ultimate can clear it
reset_response;
state(1) <= '0'; -- either goes to idle, or back to wait for software
end if;
if slot_req.data(2)='1' then
handshake_in(2) <= '1'; -- abort, only ultimate can clear it.
reset_response;
end if;
when others =>
null;
end case;
elsif slot_req.io_read='1' then
case slot_req.io_address(1 downto 0) is
when c_cif_slot_response =>
if response_pointer /= c_cmd_if_response_buffer_end then
response_pointer <= response_pointer + 1;
end if;
when c_cif_slot_status =>
if status_pointer /= c_cmd_if_status_buffer_end then
status_pointer <= status_pointer + 1;
end if;
when others =>
null;
end case;
end if;
end if;
io_resp <= c_io_resp_init;
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_cif_io_slot_base =>
slot_base <= unsigned(io_req.data(slot_base'range));
when c_cif_io_slot_enable =>
enabled <= io_req.data(0);
when c_cif_io_handshake_out =>
if io_req.data(0)='1' then -- reset
handshake_in(0) <= '0';
command_pointer <= c_cmd_if_command_buffer_addr;
end if;
if io_req.data(1)='1' then -- data seen
handshake_in(1) <= '0';
end if;
if io_req.data(2)='1' then -- abort bit
handshake_in(2) <= '0';
end if;
if io_req.data(4)='1' then -- validate data
freeze <= '0';
state(1) <= '1';
state(0) <= io_req.data(5); -- more bit
end if;
if io_req.data(7)='1' then
freeze <= '0';
reset_response;
state <= "00";
end if;
when c_cif_io_status_length =>
status_pointer <= c_cmd_if_status_buffer_addr;
status_length(7 downto 0) <= unsigned(io_req.data); -- FIXME
when c_cif_io_response_len_l =>
response_pointer <= c_cmd_if_response_buffer_addr;
response_length(7 downto 0) <= unsigned(io_req.data);
when c_cif_io_response_len_h =>
response_length(10 downto 8) <= unsigned(io_req.data(2 downto 0));
when others =>
null;
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_cif_io_slot_base =>
io_resp.data(slot_base'range) <= std_logic_vector(slot_base);
when c_cif_io_slot_enable =>
io_resp.data(0) <= enabled;
when c_cif_io_handshake_out =>
io_resp.data(5 downto 4) <= state;
when c_cif_io_handshake_in =>
io_resp.data <= slot_status;
when c_cif_io_command_start =>
io_resp.data <= std_logic_vector(c_cmd_if_command_buffer_addr(10 downto 3));
when c_cif_io_command_end =>
io_resp.data <= std_logic_vector(c_cmd_if_command_buffer_end(10 downto 3));
when c_cif_io_response_start =>
io_resp.data <= std_logic_vector(c_cmd_if_response_buffer_addr(10 downto 3));
when c_cif_io_response_end =>
io_resp.data <= std_logic_vector(c_cmd_if_response_buffer_end(10 downto 3));
when c_cif_io_status_start =>
io_resp.data <= std_logic_vector(c_cmd_if_status_buffer_addr(10 downto 3));
when c_cif_io_status_end =>
io_resp.data <= std_logic_vector(c_cmd_if_status_buffer_end(10 downto 3));
when c_cif_io_status_length =>
io_resp.data <= std_logic_vector(status_length(7 downto 0)); -- fixme
when c_cif_io_response_len_l =>
io_resp.data <= std_logic_vector(response_length(7 downto 0));
when c_cif_io_response_len_h =>
io_resp.data(2 downto 0) <= std_logic_vector(response_length(10 downto 8));
when c_cif_io_command_len_l =>
io_resp.data <= std_logic_vector(command_length(7 downto 0));
when c_cif_io_command_len_h =>
io_resp.data(2 downto 0) <= std_logic_vector(command_length(10 downto 8));
when others =>
null;
end case;
end if;
if reset='1' then
command_pointer <= c_cmd_if_command_buffer_addr;
reset_response;
handshake_in <= "000";
state <= "00";
enabled <= '0';
error_busy <= '0';
slot_base <= (others => '0');
freeze <= '0';
end if;
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.command_if_pkg.all;
entity command_protocol is
port (
clock : in std_logic;
reset : in std_logic;
-- io interface for local cpu
io_req : in t_io_req; -- we get a 2K range
io_resp : out t_io_resp;
-- C64 side interface
slot_req : in t_slot_req;
slot_resp : out t_slot_resp;
freeze : out std_logic;
-- block memory
address : out unsigned(10 downto 0);
rdata : in std_logic_vector(7 downto 0);
wdata : out std_logic_vector(7 downto 0);
en : out std_logic;
we : out std_logic );
end entity;
-- How does the protocol work?
-- The Ultimate software initializes the command and response buffers that the C64 can write to.
-- Each buffer has a start address, an end address, and a current read/write pointer as seen
-- from the C64 side.
-- The C64 can write into the command buffer and set a handshake flag. The 1541U software
-- triggers on the flag, and reads the write pointer, copies the command, and stores the
-- result and status in their respective buffers, and sets the respective handshake flags back
-- to the C64. The buffers on the ultimate side are direct mapped; on the C64 side, each
-- buffer has its own data register. One bidirectional register (on the C64 side) acts as
-- handshake register. Command queueing is not supported.
-- Protocol:
-- There are 4 states:
-- 00: Ultimate is ready and waiting for new command
-- 01: C64 has written data into the Ultimate command buffer, and the Ultimate is processing it
-- 11: Ultimate has processed the command and replied with data/status. This is not the last data.
-- 10: Ultimate has processed the command and replied with data/status. This is the last data.
-- The status register (seen by the C64) holds the following bits:
-- Bit 7: Response data available
-- Bit 6: Status data available
-- Bit 5..4: State
-- Bit 3: Error flag (write 1 to clear)
-- Bit 2: Abort flag set (cleared by Ultimate software)
-- Bit 1: Data accepted bit set (cleared by Ultimate software)
-- Bit 0: New command (set when new command is written, should NOT be used by C64)
architecture gideon of command_protocol is
signal enabled : std_logic;
signal slot_base : unsigned(6 downto 0);
signal do_write : std_logic;
signal command_pointer : unsigned(10 downto 0);
signal response_pointer : unsigned(10 downto 0);
signal status_pointer : unsigned(10 downto 0);
signal command_length : unsigned(10 downto 0);
signal response_length : unsigned(10 downto 0);
signal status_length : unsigned(10 downto 0);
-- signal response_valid : std_logic;
-- signal status_valid : std_logic;
signal rdata_resp : std_logic_vector(7 downto 0);
signal rdata_stat : std_logic_vector(7 downto 0);
signal slot_status : std_logic_vector(7 downto 0);
alias response_valid : std_logic is slot_status(7);
alias status_valid : std_logic is slot_status(6);
alias state : std_logic_vector(1 downto 0) is slot_status(5 downto 4);
alias error_busy : std_logic is slot_status(3);
alias handshake_in : std_logic_vector(2 downto 0) is slot_status(2 downto 0);
begin
-- assert false report integer'image(to_integer(c_cmd_if_command_buffer_end)) severity warning;
-- assert false report integer'image(to_integer(c_cmd_if_response_buffer_end)) severity warning;
-- assert false report integer'image(to_integer(c_cmd_if_status_buffer_end)) severity warning;
--
command_length <= command_pointer - c_cmd_if_command_buffer_addr;
with slot_req.bus_address(1 downto 0) select slot_resp.data <=
slot_status when c_cif_slot_control,
X"C9" when c_cif_slot_command,
rdata_resp when c_cif_slot_response,
rdata_stat when others;
rdata_resp <= rdata when response_valid='1' else X"00";
rdata_stat <= rdata when status_valid='1' else X"00";
slot_resp.reg_output <= enabled when slot_req.bus_address(8 downto 2) = slot_base else '0';
slot_resp.irq <= '0';
-- signals to RAM
en <= enabled;
we <= do_write;
wdata <= slot_req.data;
address <= command_pointer when do_write='1' else
response_pointer when slot_req.bus_address(0)='0' else
status_pointer;
do_write <= '1' when slot_req.io_write='1' and slot_req.io_address(8 downto 0) = (slot_base & c_cif_slot_command) else '0';
p_control: process(clock)
procedure reset_response is
begin
response_pointer <= c_cmd_if_response_buffer_addr;
status_pointer <= c_cmd_if_status_buffer_addr;
response_length <= (others => '0');
status_length <= (others => '0');
end procedure;
begin
if rising_edge(clock) then
if (response_pointer - c_cmd_if_response_buffer_addr) < response_length then
response_valid <= '1';
else
response_valid <= '0';
end if;
if (status_pointer - c_cmd_if_status_buffer_addr) < status_length then
status_valid <= '1';
else
status_valid <= '0';
end if;
if (slot_req.io_address(8 downto 2) = slot_base) and (enabled = '1') then
if slot_req.io_write='1' then
case slot_req.io_address(1 downto 0) is
when c_cif_slot_command =>
if command_pointer /= c_cmd_if_command_buffer_end then
command_pointer <= command_pointer + 1;
end if;
when c_cif_slot_control =>
if slot_req.data(3)='1' then
error_busy <= '0';
end if;
if slot_req.data(0)='1' then
freeze <= slot_req.data(7);
if state = "00" then
reset_response;
state <= "01";
handshake_in(0) <= '1';
else
error_busy <= '1';
end if;
end if;
if slot_req.data(1)='1' and state(1) = '1' then -- data accept
handshake_in(1) <= '1'; -- data accepted, only ultimate can clear it
reset_response;
state(1) <= '0'; -- either goes to idle, or back to wait for software
end if;
if slot_req.data(2)='1' then
handshake_in(2) <= '1'; -- abort, only ultimate can clear it.
reset_response;
end if;
when others =>
null;
end case;
elsif slot_req.io_read='1' then
case slot_req.io_address(1 downto 0) is
when c_cif_slot_response =>
if response_pointer /= c_cmd_if_response_buffer_end then
response_pointer <= response_pointer + 1;
end if;
when c_cif_slot_status =>
if status_pointer /= c_cmd_if_status_buffer_end then
status_pointer <= status_pointer + 1;
end if;
when others =>
null;
end case;
end if;
end if;
io_resp <= c_io_resp_init;
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_cif_io_slot_base =>
slot_base <= unsigned(io_req.data(slot_base'range));
when c_cif_io_slot_enable =>
enabled <= io_req.data(0);
when c_cif_io_handshake_out =>
if io_req.data(0)='1' then -- reset
handshake_in(0) <= '0';
command_pointer <= c_cmd_if_command_buffer_addr;
end if;
if io_req.data(1)='1' then -- data seen
handshake_in(1) <= '0';
end if;
if io_req.data(2)='1' then -- abort bit
handshake_in(2) <= '0';
end if;
if io_req.data(4)='1' then -- validate data
freeze <= '0';
state(1) <= '1';
state(0) <= io_req.data(5); -- more bit
end if;
if io_req.data(7)='1' then
freeze <= '0';
reset_response;
state <= "00";
end if;
when c_cif_io_status_length =>
status_pointer <= c_cmd_if_status_buffer_addr;
status_length(7 downto 0) <= unsigned(io_req.data); -- FIXME
when c_cif_io_response_len_l =>
response_pointer <= c_cmd_if_response_buffer_addr;
response_length(7 downto 0) <= unsigned(io_req.data);
when c_cif_io_response_len_h =>
response_length(10 downto 8) <= unsigned(io_req.data(2 downto 0));
when others =>
null;
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_cif_io_slot_base =>
io_resp.data(slot_base'range) <= std_logic_vector(slot_base);
when c_cif_io_slot_enable =>
io_resp.data(0) <= enabled;
when c_cif_io_handshake_out =>
io_resp.data(5 downto 4) <= state;
when c_cif_io_handshake_in =>
io_resp.data <= slot_status;
when c_cif_io_command_start =>
io_resp.data <= std_logic_vector(c_cmd_if_command_buffer_addr(10 downto 3));
when c_cif_io_command_end =>
io_resp.data <= std_logic_vector(c_cmd_if_command_buffer_end(10 downto 3));
when c_cif_io_response_start =>
io_resp.data <= std_logic_vector(c_cmd_if_response_buffer_addr(10 downto 3));
when c_cif_io_response_end =>
io_resp.data <= std_logic_vector(c_cmd_if_response_buffer_end(10 downto 3));
when c_cif_io_status_start =>
io_resp.data <= std_logic_vector(c_cmd_if_status_buffer_addr(10 downto 3));
when c_cif_io_status_end =>
io_resp.data <= std_logic_vector(c_cmd_if_status_buffer_end(10 downto 3));
when c_cif_io_status_length =>
io_resp.data <= std_logic_vector(status_length(7 downto 0)); -- fixme
when c_cif_io_response_len_l =>
io_resp.data <= std_logic_vector(response_length(7 downto 0));
when c_cif_io_response_len_h =>
io_resp.data(2 downto 0) <= std_logic_vector(response_length(10 downto 8));
when c_cif_io_command_len_l =>
io_resp.data <= std_logic_vector(command_length(7 downto 0));
when c_cif_io_command_len_h =>
io_resp.data(2 downto 0) <= std_logic_vector(command_length(10 downto 8));
when others =>
null;
end case;
end if;
if reset='1' then
command_pointer <= c_cmd_if_command_buffer_addr;
reset_response;
handshake_in <= "000";
state <= "00";
enabled <= '0';
error_busy <= '0';
slot_base <= (others => '0');
freeze <= '0';
end if;
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.command_if_pkg.all;
entity command_protocol is
port (
clock : in std_logic;
reset : in std_logic;
-- io interface for local cpu
io_req : in t_io_req; -- we get a 2K range
io_resp : out t_io_resp;
-- C64 side interface
slot_req : in t_slot_req;
slot_resp : out t_slot_resp;
freeze : out std_logic;
-- block memory
address : out unsigned(10 downto 0);
rdata : in std_logic_vector(7 downto 0);
wdata : out std_logic_vector(7 downto 0);
en : out std_logic;
we : out std_logic );
end entity;
-- How does the protocol work?
-- The Ultimate software initializes the command and response buffers that the C64 can write to.
-- Each buffer has a start address, an end address, and a current read/write pointer as seen
-- from the C64 side.
-- The C64 can write into the command buffer and set a handshake flag. The 1541U software
-- triggers on the flag, and reads the write pointer, copies the command, and stores the
-- result and status in their respective buffers, and sets the respective handshake flags back
-- to the C64. The buffers on the ultimate side are direct mapped; on the C64 side, each
-- buffer has its own data register. One bidirectional register (on the C64 side) acts as
-- handshake register. Command queueing is not supported.
-- Protocol:
-- There are 4 states:
-- 00: Ultimate is ready and waiting for new command
-- 01: C64 has written data into the Ultimate command buffer, and the Ultimate is processing it
-- 11: Ultimate has processed the command and replied with data/status. This is not the last data.
-- 10: Ultimate has processed the command and replied with data/status. This is the last data.
-- The status register (seen by the C64) holds the following bits:
-- Bit 7: Response data available
-- Bit 6: Status data available
-- Bit 5..4: State
-- Bit 3: Error flag (write 1 to clear)
-- Bit 2: Abort flag set (cleared by Ultimate software)
-- Bit 1: Data accepted bit set (cleared by Ultimate software)
-- Bit 0: New command (set when new command is written, should NOT be used by C64)
architecture gideon of command_protocol is
signal enabled : std_logic;
signal slot_base : unsigned(6 downto 0);
signal do_write : std_logic;
signal command_pointer : unsigned(10 downto 0);
signal response_pointer : unsigned(10 downto 0);
signal status_pointer : unsigned(10 downto 0);
signal command_length : unsigned(10 downto 0);
signal response_length : unsigned(10 downto 0);
signal status_length : unsigned(10 downto 0);
-- signal response_valid : std_logic;
-- signal status_valid : std_logic;
signal rdata_resp : std_logic_vector(7 downto 0);
signal rdata_stat : std_logic_vector(7 downto 0);
signal slot_status : std_logic_vector(7 downto 0);
alias response_valid : std_logic is slot_status(7);
alias status_valid : std_logic is slot_status(6);
alias state : std_logic_vector(1 downto 0) is slot_status(5 downto 4);
alias error_busy : std_logic is slot_status(3);
alias handshake_in : std_logic_vector(2 downto 0) is slot_status(2 downto 0);
begin
-- assert false report integer'image(to_integer(c_cmd_if_command_buffer_end)) severity warning;
-- assert false report integer'image(to_integer(c_cmd_if_response_buffer_end)) severity warning;
-- assert false report integer'image(to_integer(c_cmd_if_status_buffer_end)) severity warning;
--
command_length <= command_pointer - c_cmd_if_command_buffer_addr;
with slot_req.bus_address(1 downto 0) select slot_resp.data <=
slot_status when c_cif_slot_control,
X"C9" when c_cif_slot_command,
rdata_resp when c_cif_slot_response,
rdata_stat when others;
rdata_resp <= rdata when response_valid='1' else X"00";
rdata_stat <= rdata when status_valid='1' else X"00";
slot_resp.reg_output <= enabled when slot_req.bus_address(8 downto 2) = slot_base else '0';
slot_resp.irq <= '0';
-- signals to RAM
en <= enabled;
we <= do_write;
wdata <= slot_req.data;
address <= command_pointer when do_write='1' else
response_pointer when slot_req.bus_address(0)='0' else
status_pointer;
do_write <= '1' when slot_req.io_write='1' and slot_req.io_address(8 downto 0) = (slot_base & c_cif_slot_command) else '0';
p_control: process(clock)
procedure reset_response is
begin
response_pointer <= c_cmd_if_response_buffer_addr;
status_pointer <= c_cmd_if_status_buffer_addr;
response_length <= (others => '0');
status_length <= (others => '0');
end procedure;
begin
if rising_edge(clock) then
if (response_pointer - c_cmd_if_response_buffer_addr) < response_length then
response_valid <= '1';
else
response_valid <= '0';
end if;
if (status_pointer - c_cmd_if_status_buffer_addr) < status_length then
status_valid <= '1';
else
status_valid <= '0';
end if;
if (slot_req.io_address(8 downto 2) = slot_base) and (enabled = '1') then
if slot_req.io_write='1' then
case slot_req.io_address(1 downto 0) is
when c_cif_slot_command =>
if command_pointer /= c_cmd_if_command_buffer_end then
command_pointer <= command_pointer + 1;
end if;
when c_cif_slot_control =>
if slot_req.data(3)='1' then
error_busy <= '0';
end if;
if slot_req.data(0)='1' then
freeze <= slot_req.data(7);
if state = "00" then
reset_response;
state <= "01";
handshake_in(0) <= '1';
else
error_busy <= '1';
end if;
end if;
if slot_req.data(1)='1' and state(1) = '1' then -- data accept
handshake_in(1) <= '1'; -- data accepted, only ultimate can clear it
reset_response;
state(1) <= '0'; -- either goes to idle, or back to wait for software
end if;
if slot_req.data(2)='1' then
handshake_in(2) <= '1'; -- abort, only ultimate can clear it.
reset_response;
end if;
when others =>
null;
end case;
elsif slot_req.io_read='1' then
case slot_req.io_address(1 downto 0) is
when c_cif_slot_response =>
if response_pointer /= c_cmd_if_response_buffer_end then
response_pointer <= response_pointer + 1;
end if;
when c_cif_slot_status =>
if status_pointer /= c_cmd_if_status_buffer_end then
status_pointer <= status_pointer + 1;
end if;
when others =>
null;
end case;
end if;
end if;
io_resp <= c_io_resp_init;
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_cif_io_slot_base =>
slot_base <= unsigned(io_req.data(slot_base'range));
when c_cif_io_slot_enable =>
enabled <= io_req.data(0);
when c_cif_io_handshake_out =>
if io_req.data(0)='1' then -- reset
handshake_in(0) <= '0';
command_pointer <= c_cmd_if_command_buffer_addr;
end if;
if io_req.data(1)='1' then -- data seen
handshake_in(1) <= '0';
end if;
if io_req.data(2)='1' then -- abort bit
handshake_in(2) <= '0';
end if;
if io_req.data(4)='1' then -- validate data
freeze <= '0';
state(1) <= '1';
state(0) <= io_req.data(5); -- more bit
end if;
if io_req.data(7)='1' then
freeze <= '0';
reset_response;
state <= "00";
end if;
when c_cif_io_status_length =>
status_pointer <= c_cmd_if_status_buffer_addr;
status_length(7 downto 0) <= unsigned(io_req.data); -- FIXME
when c_cif_io_response_len_l =>
response_pointer <= c_cmd_if_response_buffer_addr;
response_length(7 downto 0) <= unsigned(io_req.data);
when c_cif_io_response_len_h =>
response_length(10 downto 8) <= unsigned(io_req.data(2 downto 0));
when others =>
null;
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_cif_io_slot_base =>
io_resp.data(slot_base'range) <= std_logic_vector(slot_base);
when c_cif_io_slot_enable =>
io_resp.data(0) <= enabled;
when c_cif_io_handshake_out =>
io_resp.data(5 downto 4) <= state;
when c_cif_io_handshake_in =>
io_resp.data <= slot_status;
when c_cif_io_command_start =>
io_resp.data <= std_logic_vector(c_cmd_if_command_buffer_addr(10 downto 3));
when c_cif_io_command_end =>
io_resp.data <= std_logic_vector(c_cmd_if_command_buffer_end(10 downto 3));
when c_cif_io_response_start =>
io_resp.data <= std_logic_vector(c_cmd_if_response_buffer_addr(10 downto 3));
when c_cif_io_response_end =>
io_resp.data <= std_logic_vector(c_cmd_if_response_buffer_end(10 downto 3));
when c_cif_io_status_start =>
io_resp.data <= std_logic_vector(c_cmd_if_status_buffer_addr(10 downto 3));
when c_cif_io_status_end =>
io_resp.data <= std_logic_vector(c_cmd_if_status_buffer_end(10 downto 3));
when c_cif_io_status_length =>
io_resp.data <= std_logic_vector(status_length(7 downto 0)); -- fixme
when c_cif_io_response_len_l =>
io_resp.data <= std_logic_vector(response_length(7 downto 0));
when c_cif_io_response_len_h =>
io_resp.data(2 downto 0) <= std_logic_vector(response_length(10 downto 8));
when c_cif_io_command_len_l =>
io_resp.data <= std_logic_vector(command_length(7 downto 0));
when c_cif_io_command_len_h =>
io_resp.data(2 downto 0) <= std_logic_vector(command_length(10 downto 8));
when others =>
null;
end case;
end if;
if reset='1' then
command_pointer <= c_cmd_if_command_buffer_addr;
reset_response;
handshake_in <= "000";
state <= "00";
enabled <= '0';
error_busy <= '0';
slot_base <= (others => '0');
freeze <= '0';
end if;
end if;
end process;
end architecture;
|
architecture struct of trfsm is
constant MaxRowWidth : integer := 9; -- sync with entity generics "NumRowsX"
type NumRows_t is array (0 to MaxRowWidth) of integer;
constant NumRows : NumRows_t := (NumRows0,NumRows1,NumRows2,NumRows3,NumRows4,NumRows5,NumRows6,NumRows7,NumRows8,NumRows9);
constant RowOffset : NumRows_t := (0,
NumRows0,
NumRows0+NumRows1,
NumRows0+NumRows1+NumRows2,
NumRows0+NumRows1+NumRows2+NumRows3,
NumRows0+NumRows1+NumRows2+NumRows3+NumRows4,
NumRows0+NumRows1+NumRows2+NumRows3+NumRows4+NumRows5,
NumRows0+NumRows1+NumRows2+NumRows3+NumRows4+NumRows5+NumRows6,
NumRows0+NumRows1+NumRows2+NumRows3+NumRows4+NumRows5+NumRows6+NumRows7,
NumRows0+NumRows1+NumRows2+NumRows3+NumRows4+NumRows5+NumRows6+NumRows7+NumRows8
);
constant NumTransitionRows_c : integer := NumRows0+NumRows1+NumRows2+NumRows3+NumRows4+NumRows5+NumRows6+NumRows7+NumRows8+NumRows9;
type NextState_t is array (0 to NumTransitionRows_c-1) of std_logic_vector(StateWidth-1 downto 0);
type Output_t is array (0 to NumTransitionRows_c-1) of std_logic_vector(OutputWidth-1 downto 0);
signal RowMatch_s : std_logic_vector(NumTransitionRows_c-1 downto 0);
signal RowNextState_s : NextState_t;
signal RowNextStateVec_s : std_logic_vector(NumTransitionRows_c*StateWidth-1 downto 0);
signal RowOutput_s : Output_t;
signal RowOutputVec_s : std_logic_vector(NumTransitionRows_c*OutputWidth-1 downto 0);
signal State_s : std_logic_vector(StateWidth-1 downto 0);
signal NextState_s : std_logic_vector(StateWidth-1 downto 0);
signal CfgData : std_logic_vector(NumTransitionRows_c downto 0);
begin -- struct
GenerateTransitionRowsOfWidth: for RowWidth in 0 to 9 generate
GenerateTransitionRows: for i in 0 to NumRows(RowWidth)-1 generate
TransitionRow_inst: TransitionRow
generic map (
TotalInputWidth => InputWidth,
MyInputWidth => RowWidth,
StateWidth => StateWidth,
OutputWidth => OutputWidth)
port map (
Reset_n_i => Reset_n_i,
Input_i => Input_i,
State_i => State_s,
Match_o => RowMatch_s (RowOffset(RowWidth)+i),
NextState_o => RowNextState_s(RowOffset(RowWidth)+i),
Output_o => RowOutput_s (RowOffset(RowWidth)+i),
CfgMode_i => CfgMode_i,
CfgClk_i => CfgClk_i,
CfgShift_i => CfgShift_i,
CfgDataIn_i => CfgData(RowOffset(RowWidth)+i), -- serial connection of all rows
CfgDataOut_o => CfgData(RowOffset(RowWidth)+i+1));
RowNextStateVec_s((RowOffset(RowWidth)+i+1)*StateWidth-1 downto (RowOffset(RowWidth)+i)*StateWidth ) <= RowNextState_s(RowOffset(RowWidth)+i);
RowOutputVec_s ((RowOffset(RowWidth)+i+1)*OutputWidth-1 downto (RowOffset(RowWidth)+i)*OutputWidth) <= RowOutput_s (RowOffset(RowWidth)+i);
end generate GenerateTransitionRows;
end generate GenerateTransitionRowsOfWidth;
CfgData(0) <= CfgDataIn_i;
CfgDataOut_o <= CfgData(NumTransitionRows_c);
SelectNextState_inst: LargeMux
generic map (
NumTransitionRows => NumTransitionRows_c,
Width => StateWidth)
port map (
Select_i => RowMatch_s,
Inputs_i => RowNextStateVec_s,
Output_o => NextState_s);
StateRegister_1: StateRegister
generic map (
StateWidth => StateWidth)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
State_o => State_s,
NextState_i => NextState_s);
SelectOutput_inst: LargeMux
generic map (
NumTransitionRows => NumTransitionRows_c,
Width => OutputWidth)
port map (
Select_i => RowMatch_s,
Inputs_i => RowOutputVec_s,
Output_o => Output_o);
end struct; -- of trfsm
|
architecture struct of trfsm is
constant MaxRowWidth : integer := 9; -- sync with entity generics "NumRowsX"
type NumRows_t is array (0 to MaxRowWidth) of integer;
constant NumRows : NumRows_t := (NumRows0,NumRows1,NumRows2,NumRows3,NumRows4,NumRows5,NumRows6,NumRows7,NumRows8,NumRows9);
constant RowOffset : NumRows_t := (0,
NumRows0,
NumRows0+NumRows1,
NumRows0+NumRows1+NumRows2,
NumRows0+NumRows1+NumRows2+NumRows3,
NumRows0+NumRows1+NumRows2+NumRows3+NumRows4,
NumRows0+NumRows1+NumRows2+NumRows3+NumRows4+NumRows5,
NumRows0+NumRows1+NumRows2+NumRows3+NumRows4+NumRows5+NumRows6,
NumRows0+NumRows1+NumRows2+NumRows3+NumRows4+NumRows5+NumRows6+NumRows7,
NumRows0+NumRows1+NumRows2+NumRows3+NumRows4+NumRows5+NumRows6+NumRows7+NumRows8
);
constant NumTransitionRows_c : integer := NumRows0+NumRows1+NumRows2+NumRows3+NumRows4+NumRows5+NumRows6+NumRows7+NumRows8+NumRows9;
type NextState_t is array (0 to NumTransitionRows_c-1) of std_logic_vector(StateWidth-1 downto 0);
type Output_t is array (0 to NumTransitionRows_c-1) of std_logic_vector(OutputWidth-1 downto 0);
signal RowMatch_s : std_logic_vector(NumTransitionRows_c-1 downto 0);
signal RowNextState_s : NextState_t;
signal RowNextStateVec_s : std_logic_vector(NumTransitionRows_c*StateWidth-1 downto 0);
signal RowOutput_s : Output_t;
signal RowOutputVec_s : std_logic_vector(NumTransitionRows_c*OutputWidth-1 downto 0);
signal State_s : std_logic_vector(StateWidth-1 downto 0);
signal NextState_s : std_logic_vector(StateWidth-1 downto 0);
signal CfgData : std_logic_vector(NumTransitionRows_c downto 0);
begin -- struct
GenerateTransitionRowsOfWidth: for RowWidth in 0 to 9 generate
GenerateTransitionRows: for i in 0 to NumRows(RowWidth)-1 generate
TransitionRow_inst: TransitionRow
generic map (
TotalInputWidth => InputWidth,
MyInputWidth => RowWidth,
StateWidth => StateWidth,
OutputWidth => OutputWidth)
port map (
Reset_n_i => Reset_n_i,
Input_i => Input_i,
State_i => State_s,
Match_o => RowMatch_s (RowOffset(RowWidth)+i),
NextState_o => RowNextState_s(RowOffset(RowWidth)+i),
Output_o => RowOutput_s (RowOffset(RowWidth)+i),
CfgMode_i => CfgMode_i,
CfgClk_i => CfgClk_i,
CfgShift_i => CfgShift_i,
CfgDataIn_i => CfgData(RowOffset(RowWidth)+i), -- serial connection of all rows
CfgDataOut_o => CfgData(RowOffset(RowWidth)+i+1));
RowNextStateVec_s((RowOffset(RowWidth)+i+1)*StateWidth-1 downto (RowOffset(RowWidth)+i)*StateWidth ) <= RowNextState_s(RowOffset(RowWidth)+i);
RowOutputVec_s ((RowOffset(RowWidth)+i+1)*OutputWidth-1 downto (RowOffset(RowWidth)+i)*OutputWidth) <= RowOutput_s (RowOffset(RowWidth)+i);
end generate GenerateTransitionRows;
end generate GenerateTransitionRowsOfWidth;
CfgData(0) <= CfgDataIn_i;
CfgDataOut_o <= CfgData(NumTransitionRows_c);
SelectNextState_inst: LargeMux
generic map (
NumTransitionRows => NumTransitionRows_c,
Width => StateWidth)
port map (
Select_i => RowMatch_s,
Inputs_i => RowNextStateVec_s,
Output_o => NextState_s);
StateRegister_1: StateRegister
generic map (
StateWidth => StateWidth)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
State_o => State_s,
NextState_i => NextState_s);
SelectOutput_inst: LargeMux
generic map (
NumTransitionRows => NumTransitionRows_c,
Width => OutputWidth)
port map (
Select_i => RowMatch_s,
Inputs_i => RowOutputVec_s,
Output_o => Output_o);
end struct; -- of trfsm
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_vga_framebuffer_v1_0_S_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 11
);
port (
-- Users to add ports here
clk : in std_logic;
active : in std_logic;
x_addr_w : in std_logic_vector(9 downto 0);
y_addr_w : in std_logic_vector(9 downto 0);
x_addr_r : in std_logic_vector(9 downto 0);
y_addr_r : in std_logic_vector(9 downto 0);
data_w : in std_logic_vector(23 downto 0);
data_r : out std_logic_vector(23 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end axi_vga_framebuffer_v1_0_S_AXI;
architecture arch_imp of axi_vga_framebuffer_v1_0_S_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 8;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 266
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg13 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg14 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg15 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg16 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg17 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg18 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg19 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg20 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg21 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg22 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg23 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg24 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg25 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg26 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg27 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg28 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg29 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg30 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg31 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg32 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg33 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg34 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg35 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg36 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg37 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg38 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg39 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg40 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg41 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg42 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg43 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg44 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg45 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg46 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg47 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg48 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg49 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg50 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg51 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg52 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg53 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg54 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg55 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg56 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg57 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg58 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg59 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg60 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg61 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg62 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg63 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg64 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg65 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg66 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg67 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg68 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg69 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg70 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg71 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg72 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg73 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg74 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg75 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg76 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg77 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg78 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg79 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg80 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg81 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg82 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg83 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg84 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg85 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg86 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg87 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg88 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg89 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg90 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg91 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg92 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg93 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg94 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg95 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg96 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg97 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg98 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg99 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg100 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg101 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg102 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg103 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg104 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg105 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg106 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg107 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg108 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg109 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg110 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg111 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg112 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg113 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg114 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg115 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg116 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg117 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg118 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg119 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg120 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg121 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg122 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg123 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg124 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg125 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg126 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg127 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg128 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg129 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg130 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg131 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg132 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg133 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg134 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg135 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg136 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg137 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg138 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg139 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg140 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg141 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg142 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg143 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg144 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg145 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg146 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg147 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg148 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg149 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg150 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg151 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg152 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg153 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg154 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg155 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg156 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg157 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg158 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg159 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg160 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg161 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg162 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg163 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg164 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg165 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg166 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg167 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg168 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg169 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg170 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg171 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg172 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg173 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg174 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg175 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg176 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg177 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg178 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg179 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg180 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg181 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg182 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg183 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg184 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg185 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg186 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg187 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg188 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg189 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg190 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg191 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg192 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg193 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg194 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg195 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg196 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg197 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg198 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg199 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg200 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg201 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg202 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg203 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg204 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg205 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg206 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg207 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg208 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg209 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg210 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg211 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg212 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg213 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg214 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg215 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg216 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg217 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg218 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg219 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg220 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg221 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg222 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg223 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg224 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg225 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg226 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg227 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg228 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg229 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg230 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg231 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg232 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg233 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg234 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg235 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg236 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg237 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg238 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg239 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg240 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg241 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg242 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg243 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg244 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg245 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg246 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg247 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg248 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg249 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg250 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg251 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg252 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg253 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg254 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg255 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg256 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg257 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg258 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg259 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg260 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg261 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg262 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg263 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg264 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg265 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
type CHUNK is array(15 downto 0) of std_logic_vector(23 downto 0);
type CHUNKS is array(15 downto 0) of CHUNK;
signal memory : CHUNKS;
signal chunk_offset_x, chunk_offset_y : unsigned(9 downto 0);
signal req_chunk : std_logic := '0';
signal req_chunk_x : unsigned(9 downto 0);
signal req_chunk_y : unsigned(9 downto 0);
signal req_write : std_logic_vector(3 downto 0) := "0000";
signal req_write_addr_0, req_write_addr_1, req_write_addr_2, req_write_addr_3, req_write_data_0, req_write_data_1, req_write_data_2, req_write_data_3 : std_logic_vector(31 downto 0);
signal busy : std_logic := '0';
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
--slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
--slv_reg2 <= (others => '0');
--slv_reg3 <= (others => '0');
--slv_reg4 <= (others => '0');
--slv_reg5 <= (others => '0');
--slv_reg6 <= (others => '0');
--slv_reg7 <= (others => '0');
--slv_reg8 <= (others => '0');
--slv_reg9 <= (others => '0');
slv_reg10 <= (others => '0');
slv_reg11 <= (others => '0');
slv_reg12 <= (others => '0');
slv_reg13 <= (others => '0');
slv_reg14 <= (others => '0');
slv_reg15 <= (others => '0');
slv_reg16 <= (others => '0');
slv_reg17 <= (others => '0');
slv_reg18 <= (others => '0');
slv_reg19 <= (others => '0');
slv_reg20 <= (others => '0');
slv_reg21 <= (others => '0');
slv_reg22 <= (others => '0');
slv_reg23 <= (others => '0');
slv_reg24 <= (others => '0');
slv_reg25 <= (others => '0');
slv_reg26 <= (others => '0');
slv_reg27 <= (others => '0');
slv_reg28 <= (others => '0');
slv_reg29 <= (others => '0');
slv_reg30 <= (others => '0');
slv_reg31 <= (others => '0');
slv_reg32 <= (others => '0');
slv_reg33 <= (others => '0');
slv_reg34 <= (others => '0');
slv_reg35 <= (others => '0');
slv_reg36 <= (others => '0');
slv_reg37 <= (others => '0');
slv_reg38 <= (others => '0');
slv_reg39 <= (others => '0');
slv_reg40 <= (others => '0');
slv_reg41 <= (others => '0');
slv_reg42 <= (others => '0');
slv_reg43 <= (others => '0');
slv_reg44 <= (others => '0');
slv_reg45 <= (others => '0');
slv_reg46 <= (others => '0');
slv_reg47 <= (others => '0');
slv_reg48 <= (others => '0');
slv_reg49 <= (others => '0');
slv_reg50 <= (others => '0');
slv_reg51 <= (others => '0');
slv_reg52 <= (others => '0');
slv_reg53 <= (others => '0');
slv_reg54 <= (others => '0');
slv_reg55 <= (others => '0');
slv_reg56 <= (others => '0');
slv_reg57 <= (others => '0');
slv_reg58 <= (others => '0');
slv_reg59 <= (others => '0');
slv_reg60 <= (others => '0');
slv_reg61 <= (others => '0');
slv_reg62 <= (others => '0');
slv_reg63 <= (others => '0');
slv_reg64 <= (others => '0');
slv_reg65 <= (others => '0');
slv_reg66 <= (others => '0');
slv_reg67 <= (others => '0');
slv_reg68 <= (others => '0');
slv_reg69 <= (others => '0');
slv_reg70 <= (others => '0');
slv_reg71 <= (others => '0');
slv_reg72 <= (others => '0');
slv_reg73 <= (others => '0');
slv_reg74 <= (others => '0');
slv_reg75 <= (others => '0');
slv_reg76 <= (others => '0');
slv_reg77 <= (others => '0');
slv_reg78 <= (others => '0');
slv_reg79 <= (others => '0');
slv_reg80 <= (others => '0');
slv_reg81 <= (others => '0');
slv_reg82 <= (others => '0');
slv_reg83 <= (others => '0');
slv_reg84 <= (others => '0');
slv_reg85 <= (others => '0');
slv_reg86 <= (others => '0');
slv_reg87 <= (others => '0');
slv_reg88 <= (others => '0');
slv_reg89 <= (others => '0');
slv_reg90 <= (others => '0');
slv_reg91 <= (others => '0');
slv_reg92 <= (others => '0');
slv_reg93 <= (others => '0');
slv_reg94 <= (others => '0');
slv_reg95 <= (others => '0');
slv_reg96 <= (others => '0');
slv_reg97 <= (others => '0');
slv_reg98 <= (others => '0');
slv_reg99 <= (others => '0');
slv_reg100 <= (others => '0');
slv_reg101 <= (others => '0');
slv_reg102 <= (others => '0');
slv_reg103 <= (others => '0');
slv_reg104 <= (others => '0');
slv_reg105 <= (others => '0');
slv_reg106 <= (others => '0');
slv_reg107 <= (others => '0');
slv_reg108 <= (others => '0');
slv_reg109 <= (others => '0');
slv_reg110 <= (others => '0');
slv_reg111 <= (others => '0');
slv_reg112 <= (others => '0');
slv_reg113 <= (others => '0');
slv_reg114 <= (others => '0');
slv_reg115 <= (others => '0');
slv_reg116 <= (others => '0');
slv_reg117 <= (others => '0');
slv_reg118 <= (others => '0');
slv_reg119 <= (others => '0');
slv_reg120 <= (others => '0');
slv_reg121 <= (others => '0');
slv_reg122 <= (others => '0');
slv_reg123 <= (others => '0');
slv_reg124 <= (others => '0');
slv_reg125 <= (others => '0');
slv_reg126 <= (others => '0');
slv_reg127 <= (others => '0');
slv_reg128 <= (others => '0');
slv_reg129 <= (others => '0');
slv_reg130 <= (others => '0');
slv_reg131 <= (others => '0');
slv_reg132 <= (others => '0');
slv_reg133 <= (others => '0');
slv_reg134 <= (others => '0');
slv_reg135 <= (others => '0');
slv_reg136 <= (others => '0');
slv_reg137 <= (others => '0');
slv_reg138 <= (others => '0');
slv_reg139 <= (others => '0');
slv_reg140 <= (others => '0');
slv_reg141 <= (others => '0');
slv_reg142 <= (others => '0');
slv_reg143 <= (others => '0');
slv_reg144 <= (others => '0');
slv_reg145 <= (others => '0');
slv_reg146 <= (others => '0');
slv_reg147 <= (others => '0');
slv_reg148 <= (others => '0');
slv_reg149 <= (others => '0');
slv_reg150 <= (others => '0');
slv_reg151 <= (others => '0');
slv_reg152 <= (others => '0');
slv_reg153 <= (others => '0');
slv_reg154 <= (others => '0');
slv_reg155 <= (others => '0');
slv_reg156 <= (others => '0');
slv_reg157 <= (others => '0');
slv_reg158 <= (others => '0');
slv_reg159 <= (others => '0');
slv_reg160 <= (others => '0');
slv_reg161 <= (others => '0');
slv_reg162 <= (others => '0');
slv_reg163 <= (others => '0');
slv_reg164 <= (others => '0');
slv_reg165 <= (others => '0');
slv_reg166 <= (others => '0');
slv_reg167 <= (others => '0');
slv_reg168 <= (others => '0');
slv_reg169 <= (others => '0');
slv_reg170 <= (others => '0');
slv_reg171 <= (others => '0');
slv_reg172 <= (others => '0');
slv_reg173 <= (others => '0');
slv_reg174 <= (others => '0');
slv_reg175 <= (others => '0');
slv_reg176 <= (others => '0');
slv_reg177 <= (others => '0');
slv_reg178 <= (others => '0');
slv_reg179 <= (others => '0');
slv_reg180 <= (others => '0');
slv_reg181 <= (others => '0');
slv_reg182 <= (others => '0');
slv_reg183 <= (others => '0');
slv_reg184 <= (others => '0');
slv_reg185 <= (others => '0');
slv_reg186 <= (others => '0');
slv_reg187 <= (others => '0');
slv_reg188 <= (others => '0');
slv_reg189 <= (others => '0');
slv_reg190 <= (others => '0');
slv_reg191 <= (others => '0');
slv_reg192 <= (others => '0');
slv_reg193 <= (others => '0');
slv_reg194 <= (others => '0');
slv_reg195 <= (others => '0');
slv_reg196 <= (others => '0');
slv_reg197 <= (others => '0');
slv_reg198 <= (others => '0');
slv_reg199 <= (others => '0');
slv_reg200 <= (others => '0');
slv_reg201 <= (others => '0');
slv_reg202 <= (others => '0');
slv_reg203 <= (others => '0');
slv_reg204 <= (others => '0');
slv_reg205 <= (others => '0');
slv_reg206 <= (others => '0');
slv_reg207 <= (others => '0');
slv_reg208 <= (others => '0');
slv_reg209 <= (others => '0');
slv_reg210 <= (others => '0');
slv_reg211 <= (others => '0');
slv_reg212 <= (others => '0');
slv_reg213 <= (others => '0');
slv_reg214 <= (others => '0');
slv_reg215 <= (others => '0');
slv_reg216 <= (others => '0');
slv_reg217 <= (others => '0');
slv_reg218 <= (others => '0');
slv_reg219 <= (others => '0');
slv_reg220 <= (others => '0');
slv_reg221 <= (others => '0');
slv_reg222 <= (others => '0');
slv_reg223 <= (others => '0');
slv_reg224 <= (others => '0');
slv_reg225 <= (others => '0');
slv_reg226 <= (others => '0');
slv_reg227 <= (others => '0');
slv_reg228 <= (others => '0');
slv_reg229 <= (others => '0');
slv_reg230 <= (others => '0');
slv_reg231 <= (others => '0');
slv_reg232 <= (others => '0');
slv_reg233 <= (others => '0');
slv_reg234 <= (others => '0');
slv_reg235 <= (others => '0');
slv_reg236 <= (others => '0');
slv_reg237 <= (others => '0');
slv_reg238 <= (others => '0');
slv_reg239 <= (others => '0');
slv_reg240 <= (others => '0');
slv_reg241 <= (others => '0');
slv_reg242 <= (others => '0');
slv_reg243 <= (others => '0');
slv_reg244 <= (others => '0');
slv_reg245 <= (others => '0');
slv_reg246 <= (others => '0');
slv_reg247 <= (others => '0');
slv_reg248 <= (others => '0');
slv_reg249 <= (others => '0');
slv_reg250 <= (others => '0');
slv_reg251 <= (others => '0');
slv_reg252 <= (others => '0');
slv_reg253 <= (others => '0');
slv_reg254 <= (others => '0');
slv_reg255 <= (others => '0');
slv_reg256 <= (others => '0');
slv_reg257 <= (others => '0');
slv_reg258 <= (others => '0');
slv_reg259 <= (others => '0');
slv_reg260 <= (others => '0');
slv_reg261 <= (others => '0');
slv_reg262 <= (others => '0');
slv_reg263 <= (others => '0');
slv_reg264 <= (others => '0');
slv_reg265 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"000000000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
--slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
--slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
--slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
--slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
--slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
--slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
--slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000001000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 8
--slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000001001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 9
-- slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000001010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 10
slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000001011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 11
slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000001100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 12
slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000001101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 13
slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000001110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 14
slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000001111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 15
slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000010000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 16
slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000010001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 17
slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000010010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 18
slv_reg18(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000010011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 19
slv_reg19(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000010100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 20
slv_reg20(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000010101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 21
slv_reg21(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000010110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 22
slv_reg22(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000010111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 23
slv_reg23(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000011000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 24
slv_reg24(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000011001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 25
slv_reg25(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000011010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 26
slv_reg26(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000011011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 27
slv_reg27(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000011100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 28
slv_reg28(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000011101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 29
slv_reg29(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000011110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 30
slv_reg30(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000011111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 31
slv_reg31(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000100000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 32
slv_reg32(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000100001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 33
slv_reg33(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000100010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 34
slv_reg34(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000100011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 35
slv_reg35(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000100100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 36
slv_reg36(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000100101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 37
slv_reg37(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000100110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 38
slv_reg38(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000100111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 39
slv_reg39(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000101000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 40
slv_reg40(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000101001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 41
slv_reg41(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000101010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 42
slv_reg42(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000101011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 43
slv_reg43(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000101100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 44
slv_reg44(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000101101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 45
slv_reg45(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000101110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 46
slv_reg46(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000101111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 47
slv_reg47(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000110000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 48
slv_reg48(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000110001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 49
slv_reg49(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000110010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 50
slv_reg50(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000110011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 51
slv_reg51(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000110100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 52
slv_reg52(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000110101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 53
slv_reg53(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000110110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 54
slv_reg54(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000110111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 55
slv_reg55(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000111000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 56
slv_reg56(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000111001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 57
slv_reg57(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000111010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 58
slv_reg58(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000111011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 59
slv_reg59(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000111100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 60
slv_reg60(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000111101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 61
slv_reg61(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000111110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 62
slv_reg62(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000111111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 63
slv_reg63(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001000000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 64
slv_reg64(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001000001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 65
slv_reg65(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001000010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 66
slv_reg66(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001000011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 67
slv_reg67(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001000100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 68
slv_reg68(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001000101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 69
slv_reg69(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001000110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 70
slv_reg70(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001000111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 71
slv_reg71(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001001000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 72
slv_reg72(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001001001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 73
slv_reg73(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001001010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 74
slv_reg74(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001001011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 75
slv_reg75(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001001100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 76
slv_reg76(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001001101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 77
slv_reg77(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001001110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 78
slv_reg78(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001001111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 79
slv_reg79(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001010000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 80
slv_reg80(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001010001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 81
slv_reg81(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001010010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 82
slv_reg82(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001010011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 83
slv_reg83(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001010100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 84
slv_reg84(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001010101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 85
slv_reg85(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001010110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 86
slv_reg86(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001010111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 87
slv_reg87(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001011000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 88
slv_reg88(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001011001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 89
slv_reg89(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001011010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 90
slv_reg90(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001011011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 91
slv_reg91(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001011100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 92
slv_reg92(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001011101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 93
slv_reg93(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001011110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 94
slv_reg94(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001011111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 95
slv_reg95(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001100000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 96
slv_reg96(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001100001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 97
slv_reg97(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001100010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 98
slv_reg98(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001100011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 99
slv_reg99(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001100100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 100
slv_reg100(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001100101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 101
slv_reg101(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001100110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 102
slv_reg102(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001100111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 103
slv_reg103(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001101000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 104
slv_reg104(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001101001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 105
slv_reg105(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001101010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 106
slv_reg106(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001101011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 107
slv_reg107(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001101100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 108
slv_reg108(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001101101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 109
slv_reg109(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001101110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 110
slv_reg110(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001101111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 111
slv_reg111(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001110000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 112
slv_reg112(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001110001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 113
slv_reg113(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001110010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 114
slv_reg114(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001110011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 115
slv_reg115(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001110100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 116
slv_reg116(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001110101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 117
slv_reg117(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001110110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 118
slv_reg118(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001110111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 119
slv_reg119(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001111000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 120
slv_reg120(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001111001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 121
slv_reg121(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001111010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 122
slv_reg122(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001111011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 123
slv_reg123(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001111100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 124
slv_reg124(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001111101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 125
slv_reg125(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001111110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 126
slv_reg126(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001111111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 127
slv_reg127(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010000000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 128
slv_reg128(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010000001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 129
slv_reg129(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010000010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 130
slv_reg130(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010000011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 131
slv_reg131(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010000100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 132
slv_reg132(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010000101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 133
slv_reg133(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010000110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 134
slv_reg134(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010000111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 135
slv_reg135(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010001000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 136
slv_reg136(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010001001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 137
slv_reg137(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010001010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 138
slv_reg138(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010001011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 139
slv_reg139(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010001100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 140
slv_reg140(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010001101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 141
slv_reg141(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010001110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 142
slv_reg142(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010001111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 143
slv_reg143(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010010000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 144
slv_reg144(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010010001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 145
slv_reg145(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010010010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 146
slv_reg146(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010010011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 147
slv_reg147(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010010100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 148
slv_reg148(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010010101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 149
slv_reg149(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010010110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 150
slv_reg150(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010010111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 151
slv_reg151(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010011000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 152
slv_reg152(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010011001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 153
slv_reg153(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010011010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 154
slv_reg154(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010011011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 155
slv_reg155(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010011100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 156
slv_reg156(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010011101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 157
slv_reg157(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010011110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 158
slv_reg158(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010011111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 159
slv_reg159(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010100000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 160
slv_reg160(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010100001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 161
slv_reg161(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010100010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 162
slv_reg162(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010100011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 163
slv_reg163(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010100100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 164
slv_reg164(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010100101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 165
slv_reg165(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010100110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 166
slv_reg166(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010100111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 167
slv_reg167(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010101000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 168
slv_reg168(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010101001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 169
slv_reg169(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010101010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 170
slv_reg170(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010101011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 171
slv_reg171(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010101100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 172
slv_reg172(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010101101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 173
slv_reg173(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010101110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 174
slv_reg174(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010101111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 175
slv_reg175(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010110000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 176
slv_reg176(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010110001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 177
slv_reg177(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010110010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 178
slv_reg178(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010110011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 179
slv_reg179(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010110100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 180
slv_reg180(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010110101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 181
slv_reg181(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010110110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 182
slv_reg182(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010110111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 183
slv_reg183(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010111000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 184
slv_reg184(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010111001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 185
slv_reg185(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010111010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 186
slv_reg186(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010111011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 187
slv_reg187(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010111100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 188
slv_reg188(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010111101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 189
slv_reg189(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010111110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 190
slv_reg190(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010111111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 191
slv_reg191(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011000000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 192
slv_reg192(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011000001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 193
slv_reg193(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011000010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 194
slv_reg194(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011000011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 195
slv_reg195(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011000100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 196
slv_reg196(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011000101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 197
slv_reg197(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011000110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 198
slv_reg198(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011000111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 199
slv_reg199(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011001000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 200
slv_reg200(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011001001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 201
slv_reg201(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011001010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 202
slv_reg202(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011001011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 203
slv_reg203(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011001100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 204
slv_reg204(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011001101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 205
slv_reg205(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011001110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 206
slv_reg206(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011001111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 207
slv_reg207(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011010000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 208
slv_reg208(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011010001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 209
slv_reg209(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011010010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 210
slv_reg210(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011010011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 211
slv_reg211(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011010100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 212
slv_reg212(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011010101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 213
slv_reg213(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011010110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 214
slv_reg214(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011010111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 215
slv_reg215(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011011000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 216
slv_reg216(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011011001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 217
slv_reg217(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011011010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 218
slv_reg218(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011011011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 219
slv_reg219(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011011100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 220
slv_reg220(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011011101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 221
slv_reg221(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011011110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 222
slv_reg222(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011011111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 223
slv_reg223(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011100000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 224
slv_reg224(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011100001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 225
slv_reg225(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011100010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 226
slv_reg226(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011100011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 227
slv_reg227(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011100100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 228
slv_reg228(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011100101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 229
slv_reg229(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011100110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 230
slv_reg230(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011100111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 231
slv_reg231(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011101000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 232
slv_reg232(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011101001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 233
slv_reg233(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011101010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 234
slv_reg234(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011101011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 235
slv_reg235(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011101100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 236
slv_reg236(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011101101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 237
slv_reg237(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011101110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 238
slv_reg238(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011101111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 239
slv_reg239(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011110000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 240
slv_reg240(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011110001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 241
slv_reg241(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011110010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 242
slv_reg242(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011110011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 243
slv_reg243(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011110100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 244
slv_reg244(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011110101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 245
slv_reg245(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011110110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 246
slv_reg246(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011110111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 247
slv_reg247(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011111000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 248
slv_reg248(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011111001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 249
slv_reg249(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011111010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 250
slv_reg250(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011111011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 251
slv_reg251(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011111100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 252
slv_reg252(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011111101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 253
slv_reg253(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011111110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 254
slv_reg254(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011111111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 255
slv_reg255(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100000000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 256
slv_reg256(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100000001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 257
slv_reg257(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100000010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 258
slv_reg258(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100000011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 259
slv_reg259(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100000100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 260
slv_reg260(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100000101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 261
slv_reg261(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100000110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 262
slv_reg262(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100000111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 263
slv_reg263(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100001000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 264
slv_reg264(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100001001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 265
slv_reg265(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
-- slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
--slv_reg2 <= slv_reg2;
--slv_reg3 <= slv_reg3;
--slv_reg4 <= slv_reg4;
--slv_reg5 <= slv_reg5;
--slv_reg6 <= slv_reg6;
--slv_reg7 <= slv_reg7;
--slv_reg8 <= slv_reg8;
-- slv_reg9 <= slv_reg9;
slv_reg10 <= slv_reg10;
slv_reg11 <= slv_reg11;
slv_reg12 <= slv_reg12;
slv_reg13 <= slv_reg13;
slv_reg14 <= slv_reg14;
slv_reg15 <= slv_reg15;
slv_reg16 <= slv_reg16;
slv_reg17 <= slv_reg17;
slv_reg18 <= slv_reg18;
slv_reg19 <= slv_reg19;
slv_reg20 <= slv_reg20;
slv_reg21 <= slv_reg21;
slv_reg22 <= slv_reg22;
slv_reg23 <= slv_reg23;
slv_reg24 <= slv_reg24;
slv_reg25 <= slv_reg25;
slv_reg26 <= slv_reg26;
slv_reg27 <= slv_reg27;
slv_reg28 <= slv_reg28;
slv_reg29 <= slv_reg29;
slv_reg30 <= slv_reg30;
slv_reg31 <= slv_reg31;
slv_reg32 <= slv_reg32;
slv_reg33 <= slv_reg33;
slv_reg34 <= slv_reg34;
slv_reg35 <= slv_reg35;
slv_reg36 <= slv_reg36;
slv_reg37 <= slv_reg37;
slv_reg38 <= slv_reg38;
slv_reg39 <= slv_reg39;
slv_reg40 <= slv_reg40;
slv_reg41 <= slv_reg41;
slv_reg42 <= slv_reg42;
slv_reg43 <= slv_reg43;
slv_reg44 <= slv_reg44;
slv_reg45 <= slv_reg45;
slv_reg46 <= slv_reg46;
slv_reg47 <= slv_reg47;
slv_reg48 <= slv_reg48;
slv_reg49 <= slv_reg49;
slv_reg50 <= slv_reg50;
slv_reg51 <= slv_reg51;
slv_reg52 <= slv_reg52;
slv_reg53 <= slv_reg53;
slv_reg54 <= slv_reg54;
slv_reg55 <= slv_reg55;
slv_reg56 <= slv_reg56;
slv_reg57 <= slv_reg57;
slv_reg58 <= slv_reg58;
slv_reg59 <= slv_reg59;
slv_reg60 <= slv_reg60;
slv_reg61 <= slv_reg61;
slv_reg62 <= slv_reg62;
slv_reg63 <= slv_reg63;
slv_reg64 <= slv_reg64;
slv_reg65 <= slv_reg65;
slv_reg66 <= slv_reg66;
slv_reg67 <= slv_reg67;
slv_reg68 <= slv_reg68;
slv_reg69 <= slv_reg69;
slv_reg70 <= slv_reg70;
slv_reg71 <= slv_reg71;
slv_reg72 <= slv_reg72;
slv_reg73 <= slv_reg73;
slv_reg74 <= slv_reg74;
slv_reg75 <= slv_reg75;
slv_reg76 <= slv_reg76;
slv_reg77 <= slv_reg77;
slv_reg78 <= slv_reg78;
slv_reg79 <= slv_reg79;
slv_reg80 <= slv_reg80;
slv_reg81 <= slv_reg81;
slv_reg82 <= slv_reg82;
slv_reg83 <= slv_reg83;
slv_reg84 <= slv_reg84;
slv_reg85 <= slv_reg85;
slv_reg86 <= slv_reg86;
slv_reg87 <= slv_reg87;
slv_reg88 <= slv_reg88;
slv_reg89 <= slv_reg89;
slv_reg90 <= slv_reg90;
slv_reg91 <= slv_reg91;
slv_reg92 <= slv_reg92;
slv_reg93 <= slv_reg93;
slv_reg94 <= slv_reg94;
slv_reg95 <= slv_reg95;
slv_reg96 <= slv_reg96;
slv_reg97 <= slv_reg97;
slv_reg98 <= slv_reg98;
slv_reg99 <= slv_reg99;
slv_reg100 <= slv_reg100;
slv_reg101 <= slv_reg101;
slv_reg102 <= slv_reg102;
slv_reg103 <= slv_reg103;
slv_reg104 <= slv_reg104;
slv_reg105 <= slv_reg105;
slv_reg106 <= slv_reg106;
slv_reg107 <= slv_reg107;
slv_reg108 <= slv_reg108;
slv_reg109 <= slv_reg109;
slv_reg110 <= slv_reg110;
slv_reg111 <= slv_reg111;
slv_reg112 <= slv_reg112;
slv_reg113 <= slv_reg113;
slv_reg114 <= slv_reg114;
slv_reg115 <= slv_reg115;
slv_reg116 <= slv_reg116;
slv_reg117 <= slv_reg117;
slv_reg118 <= slv_reg118;
slv_reg119 <= slv_reg119;
slv_reg120 <= slv_reg120;
slv_reg121 <= slv_reg121;
slv_reg122 <= slv_reg122;
slv_reg123 <= slv_reg123;
slv_reg124 <= slv_reg124;
slv_reg125 <= slv_reg125;
slv_reg126 <= slv_reg126;
slv_reg127 <= slv_reg127;
slv_reg128 <= slv_reg128;
slv_reg129 <= slv_reg129;
slv_reg130 <= slv_reg130;
slv_reg131 <= slv_reg131;
slv_reg132 <= slv_reg132;
slv_reg133 <= slv_reg133;
slv_reg134 <= slv_reg134;
slv_reg135 <= slv_reg135;
slv_reg136 <= slv_reg136;
slv_reg137 <= slv_reg137;
slv_reg138 <= slv_reg138;
slv_reg139 <= slv_reg139;
slv_reg140 <= slv_reg140;
slv_reg141 <= slv_reg141;
slv_reg142 <= slv_reg142;
slv_reg143 <= slv_reg143;
slv_reg144 <= slv_reg144;
slv_reg145 <= slv_reg145;
slv_reg146 <= slv_reg146;
slv_reg147 <= slv_reg147;
slv_reg148 <= slv_reg148;
slv_reg149 <= slv_reg149;
slv_reg150 <= slv_reg150;
slv_reg151 <= slv_reg151;
slv_reg152 <= slv_reg152;
slv_reg153 <= slv_reg153;
slv_reg154 <= slv_reg154;
slv_reg155 <= slv_reg155;
slv_reg156 <= slv_reg156;
slv_reg157 <= slv_reg157;
slv_reg158 <= slv_reg158;
slv_reg159 <= slv_reg159;
slv_reg160 <= slv_reg160;
slv_reg161 <= slv_reg161;
slv_reg162 <= slv_reg162;
slv_reg163 <= slv_reg163;
slv_reg164 <= slv_reg164;
slv_reg165 <= slv_reg165;
slv_reg166 <= slv_reg166;
slv_reg167 <= slv_reg167;
slv_reg168 <= slv_reg168;
slv_reg169 <= slv_reg169;
slv_reg170 <= slv_reg170;
slv_reg171 <= slv_reg171;
slv_reg172 <= slv_reg172;
slv_reg173 <= slv_reg173;
slv_reg174 <= slv_reg174;
slv_reg175 <= slv_reg175;
slv_reg176 <= slv_reg176;
slv_reg177 <= slv_reg177;
slv_reg178 <= slv_reg178;
slv_reg179 <= slv_reg179;
slv_reg180 <= slv_reg180;
slv_reg181 <= slv_reg181;
slv_reg182 <= slv_reg182;
slv_reg183 <= slv_reg183;
slv_reg184 <= slv_reg184;
slv_reg185 <= slv_reg185;
slv_reg186 <= slv_reg186;
slv_reg187 <= slv_reg187;
slv_reg188 <= slv_reg188;
slv_reg189 <= slv_reg189;
slv_reg190 <= slv_reg190;
slv_reg191 <= slv_reg191;
slv_reg192 <= slv_reg192;
slv_reg193 <= slv_reg193;
slv_reg194 <= slv_reg194;
slv_reg195 <= slv_reg195;
slv_reg196 <= slv_reg196;
slv_reg197 <= slv_reg197;
slv_reg198 <= slv_reg198;
slv_reg199 <= slv_reg199;
slv_reg200 <= slv_reg200;
slv_reg201 <= slv_reg201;
slv_reg202 <= slv_reg202;
slv_reg203 <= slv_reg203;
slv_reg204 <= slv_reg204;
slv_reg205 <= slv_reg205;
slv_reg206 <= slv_reg206;
slv_reg207 <= slv_reg207;
slv_reg208 <= slv_reg208;
slv_reg209 <= slv_reg209;
slv_reg210 <= slv_reg210;
slv_reg211 <= slv_reg211;
slv_reg212 <= slv_reg212;
slv_reg213 <= slv_reg213;
slv_reg214 <= slv_reg214;
slv_reg215 <= slv_reg215;
slv_reg216 <= slv_reg216;
slv_reg217 <= slv_reg217;
slv_reg218 <= slv_reg218;
slv_reg219 <= slv_reg219;
slv_reg220 <= slv_reg220;
slv_reg221 <= slv_reg221;
slv_reg222 <= slv_reg222;
slv_reg223 <= slv_reg223;
slv_reg224 <= slv_reg224;
slv_reg225 <= slv_reg225;
slv_reg226 <= slv_reg226;
slv_reg227 <= slv_reg227;
slv_reg228 <= slv_reg228;
slv_reg229 <= slv_reg229;
slv_reg230 <= slv_reg230;
slv_reg231 <= slv_reg231;
slv_reg232 <= slv_reg232;
slv_reg233 <= slv_reg233;
slv_reg234 <= slv_reg234;
slv_reg235 <= slv_reg235;
slv_reg236 <= slv_reg236;
slv_reg237 <= slv_reg237;
slv_reg238 <= slv_reg238;
slv_reg239 <= slv_reg239;
slv_reg240 <= slv_reg240;
slv_reg241 <= slv_reg241;
slv_reg242 <= slv_reg242;
slv_reg243 <= slv_reg243;
slv_reg244 <= slv_reg244;
slv_reg245 <= slv_reg245;
slv_reg246 <= slv_reg246;
slv_reg247 <= slv_reg247;
slv_reg248 <= slv_reg248;
slv_reg249 <= slv_reg249;
slv_reg250 <= slv_reg250;
slv_reg251 <= slv_reg251;
slv_reg252 <= slv_reg252;
slv_reg253 <= slv_reg253;
slv_reg254 <= slv_reg254;
slv_reg255 <= slv_reg255;
slv_reg256 <= slv_reg256;
slv_reg257 <= slv_reg257;
slv_reg258 <= slv_reg258;
slv_reg259 <= slv_reg259;
slv_reg260 <= slv_reg260;
slv_reg261 <= slv_reg261;
slv_reg262 <= slv_reg262;
slv_reg263 <= slv_reg263;
slv_reg264 <= slv_reg264;
slv_reg265 <= slv_reg265;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, slv_reg20, slv_reg21, slv_reg22, slv_reg23, slv_reg24, slv_reg25, slv_reg26, slv_reg27, slv_reg28, slv_reg29, slv_reg30, slv_reg31, slv_reg32, slv_reg33, slv_reg34, slv_reg35, slv_reg36, slv_reg37, slv_reg38, slv_reg39, slv_reg40, slv_reg41, slv_reg42, slv_reg43, slv_reg44, slv_reg45, slv_reg46, slv_reg47, slv_reg48, slv_reg49, slv_reg50, slv_reg51, slv_reg52, slv_reg53, slv_reg54, slv_reg55, slv_reg56, slv_reg57, slv_reg58, slv_reg59, slv_reg60, slv_reg61, slv_reg62, slv_reg63, slv_reg64, slv_reg65, slv_reg66, slv_reg67, slv_reg68, slv_reg69, slv_reg70, slv_reg71, slv_reg72, slv_reg73, slv_reg74, slv_reg75, slv_reg76, slv_reg77, slv_reg78, slv_reg79, slv_reg80, slv_reg81, slv_reg82, slv_reg83, slv_reg84, slv_reg85, slv_reg86, slv_reg87, slv_reg88, slv_reg89, slv_reg90, slv_reg91, slv_reg92, slv_reg93, slv_reg94, slv_reg95, slv_reg96, slv_reg97, slv_reg98, slv_reg99, slv_reg100, slv_reg101, slv_reg102, slv_reg103, slv_reg104, slv_reg105, slv_reg106, slv_reg107, slv_reg108, slv_reg109, slv_reg110, slv_reg111, slv_reg112, slv_reg113, slv_reg114, slv_reg115, slv_reg116, slv_reg117, slv_reg118, slv_reg119, slv_reg120, slv_reg121, slv_reg122, slv_reg123, slv_reg124, slv_reg125, slv_reg126, slv_reg127, slv_reg128, slv_reg129, slv_reg130, slv_reg131, slv_reg132, slv_reg133, slv_reg134, slv_reg135, slv_reg136, slv_reg137, slv_reg138, slv_reg139, slv_reg140, slv_reg141, slv_reg142, slv_reg143, slv_reg144, slv_reg145, slv_reg146, slv_reg147, slv_reg148, slv_reg149, slv_reg150, slv_reg151, slv_reg152, slv_reg153, slv_reg154, slv_reg155, slv_reg156, slv_reg157, slv_reg158, slv_reg159, slv_reg160, slv_reg161, slv_reg162, slv_reg163, slv_reg164, slv_reg165, slv_reg166, slv_reg167, slv_reg168, slv_reg169, slv_reg170, slv_reg171, slv_reg172, slv_reg173, slv_reg174, slv_reg175, slv_reg176, slv_reg177, slv_reg178, slv_reg179, slv_reg180, slv_reg181, slv_reg182, slv_reg183, slv_reg184, slv_reg185, slv_reg186, slv_reg187, slv_reg188, slv_reg189, slv_reg190, slv_reg191, slv_reg192, slv_reg193, slv_reg194, slv_reg195, slv_reg196, slv_reg197, slv_reg198, slv_reg199, slv_reg200, slv_reg201, slv_reg202, slv_reg203, slv_reg204, slv_reg205, slv_reg206, slv_reg207, slv_reg208, slv_reg209, slv_reg210, slv_reg211, slv_reg212, slv_reg213, slv_reg214, slv_reg215, slv_reg216, slv_reg217, slv_reg218, slv_reg219, slv_reg220, slv_reg221, slv_reg222, slv_reg223, slv_reg224, slv_reg225, slv_reg226, slv_reg227, slv_reg228, slv_reg229, slv_reg230, slv_reg231, slv_reg232, slv_reg233, slv_reg234, slv_reg235, slv_reg236, slv_reg237, slv_reg238, slv_reg239, slv_reg240, slv_reg241, slv_reg242, slv_reg243, slv_reg244, slv_reg245, slv_reg246, slv_reg247, slv_reg248, slv_reg249, slv_reg250, slv_reg251, slv_reg252, slv_reg253, slv_reg254, slv_reg255, slv_reg256, slv_reg257, slv_reg258, slv_reg259, slv_reg260, slv_reg261, slv_reg262, slv_reg263, slv_reg264, slv_reg265, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"000000000" =>
reg_data_out <= slv_reg0;
when b"000000001" =>
reg_data_out <= slv_reg1;
when b"000000010" =>
reg_data_out <= slv_reg2;
when b"000000011" =>
reg_data_out <= slv_reg3;
when b"000000100" =>
reg_data_out <= slv_reg4;
when b"000000101" =>
reg_data_out <= slv_reg5;
when b"000000110" =>
reg_data_out <= slv_reg6;
when b"000000111" =>
reg_data_out <= slv_reg7;
when b"000001000" =>
reg_data_out <= slv_reg8;
when b"000001001" =>
reg_data_out <= slv_reg9;
when b"000001010" =>
reg_data_out <= slv_reg10;
when b"000001011" =>
reg_data_out <= slv_reg11;
when b"000001100" =>
reg_data_out <= slv_reg12;
when b"000001101" =>
reg_data_out <= slv_reg13;
when b"000001110" =>
reg_data_out <= slv_reg14;
when b"000001111" =>
reg_data_out <= slv_reg15;
when b"000010000" =>
reg_data_out <= slv_reg16;
when b"000010001" =>
reg_data_out <= slv_reg17;
when b"000010010" =>
reg_data_out <= slv_reg18;
when b"000010011" =>
reg_data_out <= slv_reg19;
when b"000010100" =>
reg_data_out <= slv_reg20;
when b"000010101" =>
reg_data_out <= slv_reg21;
when b"000010110" =>
reg_data_out <= slv_reg22;
when b"000010111" =>
reg_data_out <= slv_reg23;
when b"000011000" =>
reg_data_out <= slv_reg24;
when b"000011001" =>
reg_data_out <= slv_reg25;
when b"000011010" =>
reg_data_out <= slv_reg26;
when b"000011011" =>
reg_data_out <= slv_reg27;
when b"000011100" =>
reg_data_out <= slv_reg28;
when b"000011101" =>
reg_data_out <= slv_reg29;
when b"000011110" =>
reg_data_out <= slv_reg30;
when b"000011111" =>
reg_data_out <= slv_reg31;
when b"000100000" =>
reg_data_out <= slv_reg32;
when b"000100001" =>
reg_data_out <= slv_reg33;
when b"000100010" =>
reg_data_out <= slv_reg34;
when b"000100011" =>
reg_data_out <= slv_reg35;
when b"000100100" =>
reg_data_out <= slv_reg36;
when b"000100101" =>
reg_data_out <= slv_reg37;
when b"000100110" =>
reg_data_out <= slv_reg38;
when b"000100111" =>
reg_data_out <= slv_reg39;
when b"000101000" =>
reg_data_out <= slv_reg40;
when b"000101001" =>
reg_data_out <= slv_reg41;
when b"000101010" =>
reg_data_out <= slv_reg42;
when b"000101011" =>
reg_data_out <= slv_reg43;
when b"000101100" =>
reg_data_out <= slv_reg44;
when b"000101101" =>
reg_data_out <= slv_reg45;
when b"000101110" =>
reg_data_out <= slv_reg46;
when b"000101111" =>
reg_data_out <= slv_reg47;
when b"000110000" =>
reg_data_out <= slv_reg48;
when b"000110001" =>
reg_data_out <= slv_reg49;
when b"000110010" =>
reg_data_out <= slv_reg50;
when b"000110011" =>
reg_data_out <= slv_reg51;
when b"000110100" =>
reg_data_out <= slv_reg52;
when b"000110101" =>
reg_data_out <= slv_reg53;
when b"000110110" =>
reg_data_out <= slv_reg54;
when b"000110111" =>
reg_data_out <= slv_reg55;
when b"000111000" =>
reg_data_out <= slv_reg56;
when b"000111001" =>
reg_data_out <= slv_reg57;
when b"000111010" =>
reg_data_out <= slv_reg58;
when b"000111011" =>
reg_data_out <= slv_reg59;
when b"000111100" =>
reg_data_out <= slv_reg60;
when b"000111101" =>
reg_data_out <= slv_reg61;
when b"000111110" =>
reg_data_out <= slv_reg62;
when b"000111111" =>
reg_data_out <= slv_reg63;
when b"001000000" =>
reg_data_out <= slv_reg64;
when b"001000001" =>
reg_data_out <= slv_reg65;
when b"001000010" =>
reg_data_out <= slv_reg66;
when b"001000011" =>
reg_data_out <= slv_reg67;
when b"001000100" =>
reg_data_out <= slv_reg68;
when b"001000101" =>
reg_data_out <= slv_reg69;
when b"001000110" =>
reg_data_out <= slv_reg70;
when b"001000111" =>
reg_data_out <= slv_reg71;
when b"001001000" =>
reg_data_out <= slv_reg72;
when b"001001001" =>
reg_data_out <= slv_reg73;
when b"001001010" =>
reg_data_out <= slv_reg74;
when b"001001011" =>
reg_data_out <= slv_reg75;
when b"001001100" =>
reg_data_out <= slv_reg76;
when b"001001101" =>
reg_data_out <= slv_reg77;
when b"001001110" =>
reg_data_out <= slv_reg78;
when b"001001111" =>
reg_data_out <= slv_reg79;
when b"001010000" =>
reg_data_out <= slv_reg80;
when b"001010001" =>
reg_data_out <= slv_reg81;
when b"001010010" =>
reg_data_out <= slv_reg82;
when b"001010011" =>
reg_data_out <= slv_reg83;
when b"001010100" =>
reg_data_out <= slv_reg84;
when b"001010101" =>
reg_data_out <= slv_reg85;
when b"001010110" =>
reg_data_out <= slv_reg86;
when b"001010111" =>
reg_data_out <= slv_reg87;
when b"001011000" =>
reg_data_out <= slv_reg88;
when b"001011001" =>
reg_data_out <= slv_reg89;
when b"001011010" =>
reg_data_out <= slv_reg90;
when b"001011011" =>
reg_data_out <= slv_reg91;
when b"001011100" =>
reg_data_out <= slv_reg92;
when b"001011101" =>
reg_data_out <= slv_reg93;
when b"001011110" =>
reg_data_out <= slv_reg94;
when b"001011111" =>
reg_data_out <= slv_reg95;
when b"001100000" =>
reg_data_out <= slv_reg96;
when b"001100001" =>
reg_data_out <= slv_reg97;
when b"001100010" =>
reg_data_out <= slv_reg98;
when b"001100011" =>
reg_data_out <= slv_reg99;
when b"001100100" =>
reg_data_out <= slv_reg100;
when b"001100101" =>
reg_data_out <= slv_reg101;
when b"001100110" =>
reg_data_out <= slv_reg102;
when b"001100111" =>
reg_data_out <= slv_reg103;
when b"001101000" =>
reg_data_out <= slv_reg104;
when b"001101001" =>
reg_data_out <= slv_reg105;
when b"001101010" =>
reg_data_out <= slv_reg106;
when b"001101011" =>
reg_data_out <= slv_reg107;
when b"001101100" =>
reg_data_out <= slv_reg108;
when b"001101101" =>
reg_data_out <= slv_reg109;
when b"001101110" =>
reg_data_out <= slv_reg110;
when b"001101111" =>
reg_data_out <= slv_reg111;
when b"001110000" =>
reg_data_out <= slv_reg112;
when b"001110001" =>
reg_data_out <= slv_reg113;
when b"001110010" =>
reg_data_out <= slv_reg114;
when b"001110011" =>
reg_data_out <= slv_reg115;
when b"001110100" =>
reg_data_out <= slv_reg116;
when b"001110101" =>
reg_data_out <= slv_reg117;
when b"001110110" =>
reg_data_out <= slv_reg118;
when b"001110111" =>
reg_data_out <= slv_reg119;
when b"001111000" =>
reg_data_out <= slv_reg120;
when b"001111001" =>
reg_data_out <= slv_reg121;
when b"001111010" =>
reg_data_out <= slv_reg122;
when b"001111011" =>
reg_data_out <= slv_reg123;
when b"001111100" =>
reg_data_out <= slv_reg124;
when b"001111101" =>
reg_data_out <= slv_reg125;
when b"001111110" =>
reg_data_out <= slv_reg126;
when b"001111111" =>
reg_data_out <= slv_reg127;
when b"010000000" =>
reg_data_out <= slv_reg128;
when b"010000001" =>
reg_data_out <= slv_reg129;
when b"010000010" =>
reg_data_out <= slv_reg130;
when b"010000011" =>
reg_data_out <= slv_reg131;
when b"010000100" =>
reg_data_out <= slv_reg132;
when b"010000101" =>
reg_data_out <= slv_reg133;
when b"010000110" =>
reg_data_out <= slv_reg134;
when b"010000111" =>
reg_data_out <= slv_reg135;
when b"010001000" =>
reg_data_out <= slv_reg136;
when b"010001001" =>
reg_data_out <= slv_reg137;
when b"010001010" =>
reg_data_out <= slv_reg138;
when b"010001011" =>
reg_data_out <= slv_reg139;
when b"010001100" =>
reg_data_out <= slv_reg140;
when b"010001101" =>
reg_data_out <= slv_reg141;
when b"010001110" =>
reg_data_out <= slv_reg142;
when b"010001111" =>
reg_data_out <= slv_reg143;
when b"010010000" =>
reg_data_out <= slv_reg144;
when b"010010001" =>
reg_data_out <= slv_reg145;
when b"010010010" =>
reg_data_out <= slv_reg146;
when b"010010011" =>
reg_data_out <= slv_reg147;
when b"010010100" =>
reg_data_out <= slv_reg148;
when b"010010101" =>
reg_data_out <= slv_reg149;
when b"010010110" =>
reg_data_out <= slv_reg150;
when b"010010111" =>
reg_data_out <= slv_reg151;
when b"010011000" =>
reg_data_out <= slv_reg152;
when b"010011001" =>
reg_data_out <= slv_reg153;
when b"010011010" =>
reg_data_out <= slv_reg154;
when b"010011011" =>
reg_data_out <= slv_reg155;
when b"010011100" =>
reg_data_out <= slv_reg156;
when b"010011101" =>
reg_data_out <= slv_reg157;
when b"010011110" =>
reg_data_out <= slv_reg158;
when b"010011111" =>
reg_data_out <= slv_reg159;
when b"010100000" =>
reg_data_out <= slv_reg160;
when b"010100001" =>
reg_data_out <= slv_reg161;
when b"010100010" =>
reg_data_out <= slv_reg162;
when b"010100011" =>
reg_data_out <= slv_reg163;
when b"010100100" =>
reg_data_out <= slv_reg164;
when b"010100101" =>
reg_data_out <= slv_reg165;
when b"010100110" =>
reg_data_out <= slv_reg166;
when b"010100111" =>
reg_data_out <= slv_reg167;
when b"010101000" =>
reg_data_out <= slv_reg168;
when b"010101001" =>
reg_data_out <= slv_reg169;
when b"010101010" =>
reg_data_out <= slv_reg170;
when b"010101011" =>
reg_data_out <= slv_reg171;
when b"010101100" =>
reg_data_out <= slv_reg172;
when b"010101101" =>
reg_data_out <= slv_reg173;
when b"010101110" =>
reg_data_out <= slv_reg174;
when b"010101111" =>
reg_data_out <= slv_reg175;
when b"010110000" =>
reg_data_out <= slv_reg176;
when b"010110001" =>
reg_data_out <= slv_reg177;
when b"010110010" =>
reg_data_out <= slv_reg178;
when b"010110011" =>
reg_data_out <= slv_reg179;
when b"010110100" =>
reg_data_out <= slv_reg180;
when b"010110101" =>
reg_data_out <= slv_reg181;
when b"010110110" =>
reg_data_out <= slv_reg182;
when b"010110111" =>
reg_data_out <= slv_reg183;
when b"010111000" =>
reg_data_out <= slv_reg184;
when b"010111001" =>
reg_data_out <= slv_reg185;
when b"010111010" =>
reg_data_out <= slv_reg186;
when b"010111011" =>
reg_data_out <= slv_reg187;
when b"010111100" =>
reg_data_out <= slv_reg188;
when b"010111101" =>
reg_data_out <= slv_reg189;
when b"010111110" =>
reg_data_out <= slv_reg190;
when b"010111111" =>
reg_data_out <= slv_reg191;
when b"011000000" =>
reg_data_out <= slv_reg192;
when b"011000001" =>
reg_data_out <= slv_reg193;
when b"011000010" =>
reg_data_out <= slv_reg194;
when b"011000011" =>
reg_data_out <= slv_reg195;
when b"011000100" =>
reg_data_out <= slv_reg196;
when b"011000101" =>
reg_data_out <= slv_reg197;
when b"011000110" =>
reg_data_out <= slv_reg198;
when b"011000111" =>
reg_data_out <= slv_reg199;
when b"011001000" =>
reg_data_out <= slv_reg200;
when b"011001001" =>
reg_data_out <= slv_reg201;
when b"011001010" =>
reg_data_out <= slv_reg202;
when b"011001011" =>
reg_data_out <= slv_reg203;
when b"011001100" =>
reg_data_out <= slv_reg204;
when b"011001101" =>
reg_data_out <= slv_reg205;
when b"011001110" =>
reg_data_out <= slv_reg206;
when b"011001111" =>
reg_data_out <= slv_reg207;
when b"011010000" =>
reg_data_out <= slv_reg208;
when b"011010001" =>
reg_data_out <= slv_reg209;
when b"011010010" =>
reg_data_out <= slv_reg210;
when b"011010011" =>
reg_data_out <= slv_reg211;
when b"011010100" =>
reg_data_out <= slv_reg212;
when b"011010101" =>
reg_data_out <= slv_reg213;
when b"011010110" =>
reg_data_out <= slv_reg214;
when b"011010111" =>
reg_data_out <= slv_reg215;
when b"011011000" =>
reg_data_out <= slv_reg216;
when b"011011001" =>
reg_data_out <= slv_reg217;
when b"011011010" =>
reg_data_out <= slv_reg218;
when b"011011011" =>
reg_data_out <= slv_reg219;
when b"011011100" =>
reg_data_out <= slv_reg220;
when b"011011101" =>
reg_data_out <= slv_reg221;
when b"011011110" =>
reg_data_out <= slv_reg222;
when b"011011111" =>
reg_data_out <= slv_reg223;
when b"011100000" =>
reg_data_out <= slv_reg224;
when b"011100001" =>
reg_data_out <= slv_reg225;
when b"011100010" =>
reg_data_out <= slv_reg226;
when b"011100011" =>
reg_data_out <= slv_reg227;
when b"011100100" =>
reg_data_out <= slv_reg228;
when b"011100101" =>
reg_data_out <= slv_reg229;
when b"011100110" =>
reg_data_out <= slv_reg230;
when b"011100111" =>
reg_data_out <= slv_reg231;
when b"011101000" =>
reg_data_out <= slv_reg232;
when b"011101001" =>
reg_data_out <= slv_reg233;
when b"011101010" =>
reg_data_out <= slv_reg234;
when b"011101011" =>
reg_data_out <= slv_reg235;
when b"011101100" =>
reg_data_out <= slv_reg236;
when b"011101101" =>
reg_data_out <= slv_reg237;
when b"011101110" =>
reg_data_out <= slv_reg238;
when b"011101111" =>
reg_data_out <= slv_reg239;
when b"011110000" =>
reg_data_out <= slv_reg240;
when b"011110001" =>
reg_data_out <= slv_reg241;
when b"011110010" =>
reg_data_out <= slv_reg242;
when b"011110011" =>
reg_data_out <= slv_reg243;
when b"011110100" =>
reg_data_out <= slv_reg244;
when b"011110101" =>
reg_data_out <= slv_reg245;
when b"011110110" =>
reg_data_out <= slv_reg246;
when b"011110111" =>
reg_data_out <= slv_reg247;
when b"011111000" =>
reg_data_out <= slv_reg248;
when b"011111001" =>
reg_data_out <= slv_reg249;
when b"011111010" =>
reg_data_out <= slv_reg250;
when b"011111011" =>
reg_data_out <= slv_reg251;
when b"011111100" =>
reg_data_out <= slv_reg252;
when b"011111101" =>
reg_data_out <= slv_reg253;
when b"011111110" =>
reg_data_out <= slv_reg254;
when b"011111111" =>
reg_data_out <= slv_reg255;
when b"100000000" =>
reg_data_out <= slv_reg256;
when b"100000001" =>
reg_data_out <= slv_reg257;
when b"100000010" =>
reg_data_out <= slv_reg258;
when b"100000011" =>
reg_data_out <= slv_reg259;
when b"100000100" =>
reg_data_out <= slv_reg260;
when b"100000101" =>
reg_data_out <= slv_reg261;
when b"100000110" =>
reg_data_out <= slv_reg262;
when b"100000111" =>
reg_data_out <= slv_reg263;
when b"100001000" =>
reg_data_out <= slv_reg264;
when b"100001001" =>
reg_data_out <= slv_reg265;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
memory(0)(0) <= slv_reg10;
memory(0)(1) <= slv_reg11;
memory(0)(2) <= slv_reg12;
memory(0)(3) <= slv_reg13;
memory(0)(4) <= slv_reg14;
memory(0)(5) <= slv_reg15;
memory(0)(6) <= slv_reg16;
memory(0)(7) <= slv_reg17;
memory(0)(8) <= slv_reg18;
memory(0)(9) <= slv_reg19;
memory(0)(10) <= slv_reg20;
memory(0)(11) <= slv_reg21;
memory(0)(12) <= slv_reg22;
memory(0)(13) <= slv_reg23;
memory(0)(14) <= slv_reg24;
memory(0)(15) <= slv_reg25;
memory(1)(0) <= slv_reg26;
memory(1)(1) <= slv_reg27;
memory(1)(2) <= slv_reg28;
memory(1)(3) <= slv_reg29;
memory(1)(4) <= slv_reg30;
memory(1)(5) <= slv_reg31;
memory(1)(6) <= slv_reg32;
memory(1)(7) <= slv_reg33;
memory(1)(8) <= slv_reg34;
memory(1)(9) <= slv_reg35;
memory(1)(10) <= slv_reg36;
memory(1)(11) <= slv_reg37;
memory(1)(12) <= slv_reg38;
memory(1)(13) <= slv_reg39;
memory(1)(14) <= slv_reg40;
memory(1)(15) <= slv_reg41;
memory(2)(0) <= slv_reg42;
memory(2)(1) <= slv_reg43;
memory(2)(2) <= slv_reg44;
memory(2)(3) <= slv_reg45;
memory(2)(4) <= slv_reg46;
memory(2)(5) <= slv_reg47;
memory(2)(6) <= slv_reg48;
memory(2)(7) <= slv_reg49;
memory(2)(8) <= slv_reg50;
memory(2)(9) <= slv_reg51;
memory(2)(10) <= slv_reg52;
memory(2)(11) <= slv_reg53;
memory(2)(12) <= slv_reg54;
memory(2)(13) <= slv_reg55;
memory(2)(14) <= slv_reg56;
memory(2)(15) <= slv_reg57;
memory(3)(0) <= slv_reg58;
memory(3)(1) <= slv_reg59;
memory(3)(2) <= slv_reg60;
memory(3)(3) <= slv_reg61;
memory(3)(4) <= slv_reg62;
memory(3)(5) <= slv_reg63;
memory(3)(6) <= slv_reg64;
memory(3)(7) <= slv_reg65;
memory(3)(8) <= slv_reg66;
memory(3)(9) <= slv_reg67;
memory(3)(10) <= slv_reg68;
memory(3)(11) <= slv_reg69;
memory(3)(12) <= slv_reg70;
memory(3)(13) <= slv_reg71;
memory(3)(14) <= slv_reg72;
memory(3)(15) <= slv_reg73;
memory(4)(0) <= slv_reg74;
memory(4)(1) <= slv_reg75;
memory(4)(2) <= slv_reg76;
memory(4)(3) <= slv_reg77;
memory(4)(4) <= slv_reg78;
memory(4)(5) <= slv_reg79;
memory(4)(6) <= slv_reg80;
memory(4)(7) <= slv_reg81;
memory(4)(8) <= slv_reg82;
memory(4)(9) <= slv_reg83;
memory(4)(10) <= slv_reg84;
memory(4)(11) <= slv_reg85;
memory(4)(12) <= slv_reg86;
memory(4)(13) <= slv_reg87;
memory(4)(14) <= slv_reg88;
memory(4)(15) <= slv_reg89;
memory(5)(0) <= slv_reg90;
memory(5)(1) <= slv_reg91;
memory(5)(2) <= slv_reg92;
memory(5)(3) <= slv_reg93;
memory(5)(4) <= slv_reg94;
memory(5)(5) <= slv_reg95;
memory(5)(6) <= slv_reg96;
memory(5)(7) <= slv_reg97;
memory(5)(8) <= slv_reg98;
memory(5)(9) <= slv_reg99;
memory(5)(10) <= slv_reg100;
memory(5)(11) <= slv_reg101;
memory(5)(12) <= slv_reg102;
memory(5)(13) <= slv_reg103;
memory(5)(14) <= slv_reg104;
memory(5)(15) <= slv_reg105;
memory(6)(0) <= slv_reg106;
memory(6)(1) <= slv_reg107;
memory(6)(2) <= slv_reg108;
memory(6)(3) <= slv_reg109;
memory(6)(4) <= slv_reg110;
memory(6)(5) <= slv_reg111;
memory(6)(6) <= slv_reg112;
memory(6)(7) <= slv_reg113;
memory(6)(8) <= slv_reg114;
memory(6)(9) <= slv_reg115;
memory(6)(10) <= slv_reg116;
memory(6)(11) <= slv_reg117;
memory(6)(12) <= slv_reg118;
memory(6)(13) <= slv_reg119;
memory(6)(14) <= slv_reg120;
memory(6)(15) <= slv_reg121;
memory(7)(0) <= slv_reg122;
memory(7)(1) <= slv_reg123;
memory(7)(2) <= slv_reg124;
memory(7)(3) <= slv_reg125;
memory(7)(4) <= slv_reg126;
memory(7)(5) <= slv_reg127;
memory(7)(6) <= slv_reg128;
memory(7)(7) <= slv_reg129;
memory(7)(8) <= slv_reg130;
memory(7)(9) <= slv_reg131;
memory(7)(10) <= slv_reg132;
memory(7)(11) <= slv_reg133;
memory(7)(12) <= slv_reg134;
memory(7)(13) <= slv_reg135;
memory(7)(14) <= slv_reg136;
memory(7)(15) <= slv_reg137;
memory(8)(0) <= slv_reg138;
memory(8)(1) <= slv_reg139;
memory(8)(2) <= slv_reg140;
memory(8)(3) <= slv_reg141;
memory(8)(4) <= slv_reg142;
memory(8)(5) <= slv_reg143;
memory(8)(6) <= slv_reg144;
memory(8)(7) <= slv_reg145;
memory(8)(8) <= slv_reg146;
memory(8)(9) <= slv_reg147;
memory(8)(10) <= slv_reg148;
memory(8)(11) <= slv_reg149;
memory(8)(12) <= slv_reg150;
memory(8)(13) <= slv_reg151;
memory(8)(14) <= slv_reg152;
memory(8)(15) <= slv_reg153;
memory(9)(0) <= slv_reg154;
memory(9)(1) <= slv_reg155;
memory(9)(2) <= slv_reg156;
memory(9)(3) <= slv_reg157;
memory(9)(4) <= slv_reg158;
memory(9)(5) <= slv_reg159;
memory(9)(6) <= slv_reg160;
memory(9)(7) <= slv_reg161;
memory(9)(8) <= slv_reg162;
memory(9)(9) <= slv_reg163;
memory(9)(10) <= slv_reg164;
memory(9)(11) <= slv_reg165;
memory(9)(12) <= slv_reg166;
memory(9)(13) <= slv_reg167;
memory(9)(14) <= slv_reg168;
memory(9)(15) <= slv_reg169;
memory(10)(0) <= slv_reg170;
memory(10)(1) <= slv_reg171;
memory(10)(2) <= slv_reg172;
memory(10)(3) <= slv_reg173;
memory(10)(4) <= slv_reg174;
memory(10)(5) <= slv_reg175;
memory(10)(6) <= slv_reg176;
memory(10)(7) <= slv_reg177;
memory(10)(8) <= slv_reg178;
memory(10)(9) <= slv_reg179;
memory(10)(10) <= slv_reg180;
memory(10)(11) <= slv_reg181;
memory(10)(12) <= slv_reg182;
memory(10)(13) <= slv_reg183;
memory(10)(14) <= slv_reg184;
memory(10)(15) <= slv_reg185;
memory(11)(0) <= slv_reg186;
memory(11)(1) <= slv_reg187;
memory(11)(2) <= slv_reg188;
memory(11)(3) <= slv_reg189;
memory(11)(4) <= slv_reg190;
memory(11)(5) <= slv_reg191;
memory(11)(6) <= slv_reg192;
memory(11)(7) <= slv_reg193;
memory(11)(8) <= slv_reg194;
memory(11)(9) <= slv_reg195;
memory(11)(10) <= slv_reg196;
memory(11)(11) <= slv_reg197;
memory(11)(12) <= slv_reg198;
memory(11)(13) <= slv_reg199;
memory(11)(14) <= slv_reg200;
memory(11)(15) <= slv_reg201;
memory(12)(0) <= slv_reg202;
memory(12)(1) <= slv_reg203;
memory(12)(2) <= slv_reg204;
memory(12)(3) <= slv_reg205;
memory(12)(4) <= slv_reg206;
memory(12)(5) <= slv_reg207;
memory(12)(6) <= slv_reg208;
memory(12)(7) <= slv_reg209;
memory(12)(8) <= slv_reg210;
memory(12)(9) <= slv_reg211;
memory(12)(10) <= slv_reg212;
memory(12)(11) <= slv_reg213;
memory(12)(12) <= slv_reg214;
memory(12)(13) <= slv_reg215;
memory(12)(14) <= slv_reg216;
memory(12)(15) <= slv_reg217;
memory(13)(0) <= slv_reg218;
memory(13)(1) <= slv_reg219;
memory(13)(2) <= slv_reg220;
memory(13)(3) <= slv_reg221;
memory(13)(4) <= slv_reg222;
memory(13)(5) <= slv_reg223;
memory(13)(6) <= slv_reg224;
memory(13)(7) <= slv_reg225;
memory(13)(8) <= slv_reg226;
memory(13)(9) <= slv_reg227;
memory(13)(10) <= slv_reg228;
memory(13)(11) <= slv_reg229;
memory(13)(12) <= slv_reg230;
memory(13)(13) <= slv_reg231;
memory(13)(14) <= slv_reg232;
memory(13)(15) <= slv_reg233;
memory(14)(0) <= slv_reg234;
memory(14)(1) <= slv_reg235;
memory(14)(2) <= slv_reg236;
memory(14)(3) <= slv_reg237;
memory(14)(4) <= slv_reg238;
memory(14)(5) <= slv_reg239;
memory(14)(6) <= slv_reg240;
memory(14)(7) <= slv_reg241;
memory(14)(8) <= slv_reg242;
memory(14)(9) <= slv_reg243;
memory(14)(10) <= slv_reg244;
memory(14)(11) <= slv_reg245;
memory(14)(12) <= slv_reg246;
memory(14)(13) <= slv_reg247;
memory(14)(14) <= slv_reg248;
memory(14)(15) <= slv_reg249;
memory(15)(0) <= slv_reg250;
memory(15)(1) <= slv_reg251;
memory(15)(2) <= slv_reg252;
memory(15)(3) <= slv_reg253;
memory(15)(4) <= slv_reg254;
memory(15)(5) <= slv_reg255;
memory(15)(6) <= slv_reg256;
memory(15)(7) <= slv_reg257;
memory(15)(8) <= slv_reg258;
memory(15)(9) <= slv_reg259;
memory(15)(10) <= slv_reg260;
memory(15)(11) <= slv_reg261;
memory(15)(12) <= slv_reg262;
memory(15)(13) <= slv_reg263;
memory(15)(14) <= slv_reg264;
memory(15)(15) <= slv_reg265;
process(clk)
variable x, y : unsigned(9 downto 0);
variable chunk_x, chunk_y, chunk_mapped_x, chunk_mapped_y : unsigned(9 downto 0);
variable chunk_index, chunk_mem_index : unsigned(3 downto 0);
begin
if rising_edge(clk) then
if active = '1' then
x := unsigned(x_addr_r);
y := unsigned(y_addr_r);
chunk_x := x srl 2;
chunk_y := y srl 2;
chunk_mapped_x := chunk_x - chunk_offset_x;
chunk_mapped_y := chunk_y - chunk_offset_y;
chunk_index(1 downto 0) := chunk_mapped_x(1 downto 0);
chunk_index(3 downto 2) := chunk_mapped_y(1 downto 0);
chunk_mem_index(1 downto 0) := x(1 downto 0);
chunk_mem_index(3 downto 2) := y(1 downto 0);
data_r(23 downto 0) <= memory(to_integer(chunk_index))(to_integer(chunk_mem_index));
if req_chunk = '0' then
if chunk_mapped_x(1 downto 0) = "00" then
req_chunk_x <= chunk_x - 1;
elsif chunk_mapped_x(1 downto 0) = "11" then
req_chunk_x <= chunk_x + 1;
end if;
if chunk_mapped_y(1 downto 0) = "00" then
req_chunk_y <= chunk_y - 1;
elsif chunk_mapped_y(1 downto 0) = "11" then
req_chunk_y <= chunk_y + 1;
end if;
if chunk_mapped_y(1 downto 0) = "00" or chunk_mapped_y(1 downto 0) = "11" or
chunk_mapped_x(1 downto 0) = "00" or chunk_mapped_x(1 downto 0) = "11" then
req_chunk <= '1';
end if;
end if;
if req_write(0) = '0' then
req_write(0) <= '1';
req_write_addr_0(9 downto 0) <= x_addr_w;
req_write_addr_0(19 downto 10) <= y_addr_w;
req_write_data_0(23 downto 0) <= data_w;
elsif req_write(1) = '0' then
req_write(1) <= '1';
req_write_addr_1(9 downto 0) <= x_addr_w;
req_write_addr_1(19 downto 10) <= y_addr_w;
req_write_data_1(23 downto 0) <= data_w;
elsif req_write(2) = '0' then
req_write(2) <= '1';
req_write_addr_2(9 downto 0) <= x_addr_w;
req_write_addr_2(19 downto 10) <= y_addr_w;
req_write_data_2(23 downto 0) <= data_w;
elsif req_write(3) = '0' then
req_write(3) <= '1';
req_write_addr_3(9 downto 0) <= x_addr_w;
req_write_addr_3(19 downto 10) <= y_addr_w;
req_write_data_3(23 downto 0) <= data_w;
end if;
end if;
end if;
end process;
process(S_AXI_ACLK)
variable control : std_logic_vector(1 downto 0) := "00";
begin
if rising_edge(S_AXI_ACLK) then
if slv_reg1(0) = '0' and busy = '0' then
-- idle
control := "00";
if req_write(0) = '1' then
slv_reg2 <= req_write_addr_0;
slv_reg3 <= req_write_data_0;
req_write(0) <= '0';
control := "01";
elsif req_write(1) = '1' then
slv_reg4 <= req_write_addr_1;
slv_reg5 <= req_write_data_1;
req_write(1) <= '0';
control := "01";
elsif req_write(2) = '1' then
slv_reg6 <= req_write_addr_2;
slv_reg7 <= req_write_data_2;
req_write(2) <= '0';
control := "01";
elsif req_write(3) = '1' then
slv_reg8 <= req_write_addr_3;
slv_reg9 <= req_write_data_3;
req_write(3) <= '0';
control := "01";
end if;
if req_chunk = '1' then
req_chunk <= '0';
slv_reg0(6) <= '1';
slv_reg0(16 downto 7) <= std_logic_vector(req_chunk_x);
slv_reg0(26 downto 17) <= std_logic_vector(req_chunk_y);
control := "01";
else
slv_reg0(6) <= '0';
end if;
if control = "01" then
slv_reg0(1 downto 0) <= control;
slv_reg0(5 downto 2) <= req_write;
busy <= '1';
end if;
end if;
if busy = '1' then
if slv_reg1(0) = '1' then
-- done, acknowledge
slv_reg0(1 downto 0) <= "10";
busy <= '0';
end if;
end if;
end if;
end process;
-- User logic ends
end arch_imp;
|
-------------------------------------------------------------------------------
-- Title : Goertzel Algorithm pipelined with BRAM
-- Project :
-------------------------------------------------------------------------------
-- File : goertzel_pipelined_v2.vhd
-- Author : strongly-typed
-- Created : 2012-04-24
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
--
-- ToDos : The throughput can be increased by:
-- i) Reduce steps in pipeline
-- ii) Do not wait to put a new value into the pipeline until the
-- last result was processed. Alternate reading and writing to
-- the BRAM. Need to store the address of the the data
-- currently in progress.
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.signalprocessing_pkg.all;
entity goertzel_pipelined_v2 is
generic (
FREQUENCIES : positive;
CHANNELS : positive := 12;
SAMPLES : positive := 250;
Q : positive := 13);
port (
start_p : in std_logic;
bram_addr_p : out std_logic_vector(7 downto 0);
bram_data_i : in std_logic_vector(35 downto 0);
bram_data_o : out std_logic_vector(35 downto 0);
bram_we_p : out std_logic;
ready_p : out std_logic;
enable_p : in std_logic;
coefs_p : in goertzel_coefs_type(FREQUENCIES-1 downto 0);
inputs_p : in goertzel_inputs_type(CHANNELS-1 downto 0);
clk : in std_logic);
end entity goertzel_pipelined_v2;
architecture structural of goertzel_pipelined_v2 is
signal start_s : std_logic := '0';
-- select signals of muxes
signal mux_delay1_s : std_logic := '0';
signal mux_delay2_s : std_logic := '0';
signal mux_coef_s : natural range FREQUENCIES-1 downto 0 := 0;
signal mux_input_s : natural range CHANNELS-1 downto 0 := 0;
-- outputs of the muxes
signal muxed_delay1_s : goertzel_data_type := (others => '0');
signal muxed_delay2_s : goertzel_data_type := (others => '0');
signal muxed_coef_s : goertzel_coef_type := (others => '0');
signal muxed_input_s : goertzel_input_type := (others => '0');
-- inter-instance routing
signal bram_data_i_s : goertzel_result_type := (others => (others => '0'));
signal goertzel_result_to_bram_s : goertzel_result_type := (others => (others => '0'));
signal pipeline_input_s : goertzel_result_type := (others => (others => '0'));
begin -- architecture structural
start_s <= start_p;
pipeline_input_s(0) <= muxed_delay1_s;
pipeline_input_s(1) <= muxed_delay2_s;
-- map generic std_logic_vector(35 downto 0) form bram
-- to strongly-tyed goertzel_result_type of pipeline
-- |35 ---- 18||17 ------ 0| BRAM
-- |--delay2--||--delay1--|| pipeline
bram_data_i_s(0) <= signed(bram_data_i(17 downto 0));
bram_data_i_s(1) <= signed(bram_data_i(35 downto 18));
-- from pipeline to bram
bram_data_o <= std_logic_vector(goertzel_result_to_bram_s(1)) & std_logic_vector(goertzel_result_to_bram_s(0));
-- muxes to multiplex one of the channels to the pipeline
goertzel_muxes_1 : entity work.goertzel_muxes
generic map (
CHANNELS => CHANNELS,
FREQUENCIES => FREQUENCIES)
port map (
mux_delay1_p => mux_delay1_s,
mux_delay2_p => mux_delay2_s,
mux_coef => mux_coef_s,
mux_input => mux_input_s,
bram_data => bram_data_i_s,
coefs_p => coefs_p,
inputs_p => inputs_p,
delay1_p => muxed_delay1_s,
delay2_p => muxed_delay2_s,
coef_p => muxed_coef_s,
input_p => muxed_input_s);
-- control the pipeline
goertzel_control_unit_1 : entity work.goertzel_control_unit
generic map (
SAMPLES => SAMPLES,
FREQUENCIES => FREQUENCIES,
CHANNELS => CHANNELS)
port map (
start_p => start_s,
ready_p => ready_p,
-- output to the bram
bram_addr_p => bram_addr_p,
bram_we_p => bram_we_p,
-- outputs to the mux
mux_delay1_p => mux_delay1_s,
mux_delay2_p => mux_delay2_s,
mux_coef_p => mux_coef_s,
mux_input_p => mux_input_s,
clk => clk);
-- the actual pipiline working on one frequency and on one channel
goertzel_pipeline_1 : entity work.goertzel_pipeline
generic map (
Q => Q)
port map (
coef_p => muxed_coef_s,
input_p => muxed_input_s,
delay_p => pipeline_input_s,
result_p => goertzel_result_to_bram_s,
clk => clk);
end architecture structural;
|
-------------------------------------------------------------------------------
-- Title : Goertzel Algorithm pipelined with BRAM
-- Project :
-------------------------------------------------------------------------------
-- File : goertzel_pipelined_v2.vhd
-- Author : strongly-typed
-- Created : 2012-04-24
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
--
-- ToDos : The throughput can be increased by:
-- i) Reduce steps in pipeline
-- ii) Do not wait to put a new value into the pipeline until the
-- last result was processed. Alternate reading and writing to
-- the BRAM. Need to store the address of the the data
-- currently in progress.
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.signalprocessing_pkg.all;
entity goertzel_pipelined_v2 is
generic (
FREQUENCIES : positive;
CHANNELS : positive := 12;
SAMPLES : positive := 250;
Q : positive := 13);
port (
start_p : in std_logic;
bram_addr_p : out std_logic_vector(7 downto 0);
bram_data_i : in std_logic_vector(35 downto 0);
bram_data_o : out std_logic_vector(35 downto 0);
bram_we_p : out std_logic;
ready_p : out std_logic;
enable_p : in std_logic;
coefs_p : in goertzel_coefs_type(FREQUENCIES-1 downto 0);
inputs_p : in goertzel_inputs_type(CHANNELS-1 downto 0);
clk : in std_logic);
end entity goertzel_pipelined_v2;
architecture structural of goertzel_pipelined_v2 is
signal start_s : std_logic := '0';
-- select signals of muxes
signal mux_delay1_s : std_logic := '0';
signal mux_delay2_s : std_logic := '0';
signal mux_coef_s : natural range FREQUENCIES-1 downto 0 := 0;
signal mux_input_s : natural range CHANNELS-1 downto 0 := 0;
-- outputs of the muxes
signal muxed_delay1_s : goertzel_data_type := (others => '0');
signal muxed_delay2_s : goertzel_data_type := (others => '0');
signal muxed_coef_s : goertzel_coef_type := (others => '0');
signal muxed_input_s : goertzel_input_type := (others => '0');
-- inter-instance routing
signal bram_data_i_s : goertzel_result_type := (others => (others => '0'));
signal goertzel_result_to_bram_s : goertzel_result_type := (others => (others => '0'));
signal pipeline_input_s : goertzel_result_type := (others => (others => '0'));
begin -- architecture structural
start_s <= start_p;
pipeline_input_s(0) <= muxed_delay1_s;
pipeline_input_s(1) <= muxed_delay2_s;
-- map generic std_logic_vector(35 downto 0) form bram
-- to strongly-tyed goertzel_result_type of pipeline
-- |35 ---- 18||17 ------ 0| BRAM
-- |--delay2--||--delay1--|| pipeline
bram_data_i_s(0) <= signed(bram_data_i(17 downto 0));
bram_data_i_s(1) <= signed(bram_data_i(35 downto 18));
-- from pipeline to bram
bram_data_o <= std_logic_vector(goertzel_result_to_bram_s(1)) & std_logic_vector(goertzel_result_to_bram_s(0));
-- muxes to multiplex one of the channels to the pipeline
goertzel_muxes_1 : entity work.goertzel_muxes
generic map (
CHANNELS => CHANNELS,
FREQUENCIES => FREQUENCIES)
port map (
mux_delay1_p => mux_delay1_s,
mux_delay2_p => mux_delay2_s,
mux_coef => mux_coef_s,
mux_input => mux_input_s,
bram_data => bram_data_i_s,
coefs_p => coefs_p,
inputs_p => inputs_p,
delay1_p => muxed_delay1_s,
delay2_p => muxed_delay2_s,
coef_p => muxed_coef_s,
input_p => muxed_input_s);
-- control the pipeline
goertzel_control_unit_1 : entity work.goertzel_control_unit
generic map (
SAMPLES => SAMPLES,
FREQUENCIES => FREQUENCIES,
CHANNELS => CHANNELS)
port map (
start_p => start_s,
ready_p => ready_p,
-- output to the bram
bram_addr_p => bram_addr_p,
bram_we_p => bram_we_p,
-- outputs to the mux
mux_delay1_p => mux_delay1_s,
mux_delay2_p => mux_delay2_s,
mux_coef_p => mux_coef_s,
mux_input_p => mux_input_s,
clk => clk);
-- the actual pipiline working on one frequency and on one channel
goertzel_pipeline_1 : entity work.goertzel_pipeline
generic map (
Q => Q)
port map (
coef_p => muxed_coef_s,
input_p => muxed_input_s,
delay_p => pipeline_input_s,
result_p => goertzel_result_to_bram_s,
clk => clk);
end architecture structural;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use work.gencomp.all;
entity leon3_net is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
clk2x : integer := 1;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic; -- free-running clock
gclk2 : in std_ulogic; -- gated 2x clock
gfclk2 : in std_ulogic; -- gated 2x FPU clock
clk2 : in std_ulogic; -- free-running 2x clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
-- ahbso : in ahb_slv_out_vector;
irqi_irl : in std_logic_vector(3 downto 0);
irqi_rst : in std_ulogic;
irqi_run : in std_ulogic;
irqi_rstvec : in std_logic_vector(31 downto 12);
irqi_iact : in std_ulogic;
irqi_index : in std_logic_vector(3 downto 0);
irqi_hrdrst : in std_ulogic;
irqo_intack : out std_ulogic;
irqo_irl : out std_logic_vector(3 downto 0);
irqo_pwd : out std_ulogic;
irqo_fpen : out std_ulogic;
irqo_idle : out std_ulogic;
dbgi_dsuen : in std_ulogic; -- DSU enable
dbgi_denable : in std_ulogic; -- diagnostic register access enablee
dbgi_dbreak : in std_ulogic; -- debug break-in
dbgi_step : in std_ulogic; -- single step
dbgi_halt : in std_ulogic; -- halt processor
dbgi_reset : in std_ulogic; -- reset processor
dbgi_dwrite : in std_ulogic; -- read/write
dbgi_daddr : in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata : in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa : in std_ulogic; -- break on IU trap
dbgi_btrape : in std_ulogic; -- break on IU trap
dbgi_berror : in std_ulogic; -- break on IU error mode
dbgi_bwatch : in std_ulogic; -- break on IU watchpoint
dbgi_bsoft : in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable : in std_ulogic;
dbgi_timer : in std_logic_vector(30 downto 0);
dbgo_data : out std_logic_vector(31 downto 0);
dbgo_crdy : out std_ulogic;
dbgo_dsu : out std_ulogic;
dbgo_dsumode : out std_ulogic;
dbgo_error : out std_ulogic;
dbgo_halt : out std_ulogic;
dbgo_pwd : out std_ulogic;
dbgo_idle : out std_ulogic;
dbgo_ipend : out std_ulogic;
dbgo_icnt : out std_ulogic;
dbgo_fcnt : out std_ulogic;
dbgo_optype : out std_logic_vector(5 downto 0); -- instruction type
dbgo_bpmiss : out std_ulogic; -- branch predict miss
dbgo_istat_cmiss : out std_ulogic;
dbgo_istat_tmiss : out std_ulogic;
dbgo_istat_chold : out std_ulogic;
dbgo_istat_mhold : out std_ulogic;
dbgo_dstat_cmiss : out std_ulogic;
dbgo_dstat_tmiss : out std_ulogic;
dbgo_dstat_chold : out std_ulogic;
dbgo_dstat_mhold : out std_ulogic;
dbgo_wbhold : out std_ulogic; -- write buffer hold
dbgo_su : out std_ulogic;
-- fpui : out grfpu_in_type;
-- fpuo : in grfpu_out_type;
clken : in std_ulogic
);
end ;
architecture rtl of leon3_net is
signal disasen : std_ulogic;
component leon3ft_unisim
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 1 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 1 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0
);
port(
clk : in std_logic;
rstn : in std_logic;
ahbi_hgrant : in std_logic_vector (0 to 15);
ahbi_hready : in std_logic;
ahbi_hresp : in std_logic_vector (1 downto 0);
ahbi_hrdata : in std_logic_vector (31 downto 0);
ahbi_hirq : in std_logic_vector (31 downto 0);
ahbo_hbusreq : out std_logic;
ahbo_hlock : out std_logic;
ahbo_htrans : out std_logic_vector (1 downto 0);
ahbo_haddr : out std_logic_vector (31 downto 0);
ahbo_hwrite : out std_logic;
ahbo_hsize : out std_logic_vector (2 downto 0);
ahbo_hburst : out std_logic_vector (2 downto 0);
ahbo_hprot : out std_logic_vector (3 downto 0);
ahbo_hwdata : out std_logic_vector (31 downto 0);
ahbo_hirq : out std_logic_vector (31 downto 0);
ahbsi_hsel : in std_logic_vector (0 to 15);
ahbsi_haddr : in std_logic_vector (31 downto 0);
ahbsi_hwrite : in std_logic;
ahbsi_htrans : in std_logic_vector (1 downto 0);
ahbsi_hsize : in std_logic_vector (2 downto 0);
ahbsi_hburst : in std_logic_vector (2 downto 0);
ahbsi_hwdata : in std_logic_vector (31 downto 0);
ahbsi_hprot : in std_logic_vector (3 downto 0);
ahbsi_hready : in std_logic;
ahbsi_hmaster : in std_logic_vector (3 downto 0);
ahbsi_hmastlock : in std_logic;
ahbsi_hmbsel : in std_logic_vector (0 to 3);
ahbsi_hirq : in std_logic_vector (31 downto 0);
irqi_irl : in std_logic_vector (3 downto 0);
irqi_rst : in std_logic;
irqi_run : in std_logic;
irqo_intack : out std_logic;
irqo_irl : out std_logic_vector (3 downto 0);
irqo_pwd : out std_logic;
dbgi_dsuen : in std_logic;
dbgi_denable : in std_logic;
dbgi_dbreak : in std_logic;
dbgi_step : in std_logic;
dbgi_halt : in std_logic;
dbgi_reset : in std_logic;
dbgi_dwrite : in std_logic;
dbgi_daddr : in std_logic_vector (23 downto 2);
dbgi_ddata : in std_logic_vector (31 downto 0);
dbgi_btrapa : in std_logic;
dbgi_btrape : in std_logic;
dbgi_berror : in std_logic;
dbgi_bwatch : in std_logic;
dbgi_bsoft : in std_logic;
dbgi_tenable : in std_logic;
dbgi_timer : in std_logic_vector (30 downto 0);
dbgo_data : out std_logic_vector (31 downto 0);
dbgo_crdy : out std_logic;
dbgo_dsu : out std_logic;
dbgo_dsumode : out std_logic;
dbgo_error : out std_logic;
dbgo_halt : out std_logic;
dbgo_pwd : out std_logic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic;
disasen : in std_logic);
end component;
component leon3ft_axcelerator is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0);
port (
clk: in std_ulogic;
rstn: in std_ulogic;
ahbi_hgrant: in std_logic_vector(0 to NAHBMST-1); -- bus grant
ahbi_hready: in std_ulogic; -- transfer done
ahbi_hresp: in std_logic_vector(1 downto 0); -- response type
ahbi_hrdata: in std_logic_vector(31 downto 0); -- read data bus
ahbi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
ahbo_hbusreq: out std_ulogic; -- bus request
ahbo_hlock: out std_ulogic; -- lock request
ahbo_htrans: out std_logic_vector(1 downto 0); -- transfer type
ahbo_haddr: out std_logic_vector(31 downto 0); -- address bus (byte)
ahbo_hwrite: out std_ulogic; -- read/write
ahbo_hsize: out std_logic_vector(2 downto 0); -- transfer size
ahbo_hburst: out std_logic_vector(2 downto 0); -- burst type
ahbo_hprot: out std_logic_vector(3 downto 0); -- protection control
ahbo_hwdata: out std_logic_vector(31 downto 0); -- write data bus
ahbo_hirq: out std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
ahbsi_hsel: in std_logic_vector(0 to NAHBSLV-1); -- slave select
ahbsi_haddr: in std_logic_vector(31 downto 0); -- address bus (byte)
ahbsi_hwrite: in std_ulogic; -- read/write
ahbsi_htrans: in std_logic_vector(1 downto 0); -- transfer type
ahbsi_hsize: in std_logic_vector(2 downto 0); -- transfer size
ahbsi_hburst: in std_logic_vector(2 downto 0); -- burst type
ahbsi_hwdata: in std_logic_vector(31 downto 0); -- write data bus
ahbsi_hprot: in std_logic_vector(3 downto 0); -- protection control
ahbsi_hready: in std_ulogic; -- transfer done
ahbsi_hmaster: in std_logic_vector(3 downto 0); -- current master
ahbsi_hmastlock: in std_ulogic; -- locked access
ahbsi_hmbsel: in std_logic_vector(0 to NAHBAMR-1); -- memory bank select
ahbsi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
irqi_irl: in std_logic_vector(3 downto 0);
irqi_rst: in std_ulogic;
irqi_run: in std_ulogic;
irqo_intack: out std_ulogic;
irqo_irl: out std_logic_vector(3 downto 0);
irqo_pwd: out std_ulogic;
dbgi_dsuen: in std_ulogic; -- DSU enable
dbgi_denable: in std_ulogic; -- diagnostic register access enable
dbgi_dbreak: in std_ulogic; -- debug break-in
dbgi_step: in std_ulogic; -- single step
dbgi_halt: in std_ulogic; -- halt processor
dbgi_reset: in std_ulogic; -- reset processor
dbgi_dwrite: in std_ulogic; -- read/write
dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa: in std_ulogic; -- break on IU trap
dbgi_btrape: in std_ulogic; -- break on IU trap
dbgi_berror: in std_ulogic; -- break on IU error mode
dbgi_bwatch: in std_ulogic; -- break on IU watchpoint
dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable: in std_ulogic;
dbgi_timer: in std_logic_vector(30 downto 0);
dbgo_data: out std_logic_vector(31 downto 0);
dbgo_crdy: out std_ulogic;
dbgo_dsu: out std_ulogic;
dbgo_dsumode: out std_ulogic;
dbgo_error: out std_ulogic;
dbgo_halt: out std_ulogic;
dbgo_pwd: out std_logic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic;
disasen : in std_logic);
end component;
component leon3ft_proasic3 is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0);
port (
clk: in std_ulogic;
rstn: in std_ulogic;
ahbi_hgrant: in std_logic_vector(0 to NAHBMST-1); -- bus grant
ahbi_hready: in std_ulogic; -- transfer done
ahbi_hresp: in std_logic_vector(1 downto 0); -- response type
ahbi_hrdata: in std_logic_vector(31 downto 0); -- read data bus
ahbi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
ahbo_hbusreq: out std_ulogic; -- bus request
ahbo_hlock: out std_ulogic; -- lock request
ahbo_htrans: out std_logic_vector(1 downto 0); -- transfer type
ahbo_haddr: out std_logic_vector(31 downto 0); -- address bus (byte)
ahbo_hwrite: out std_ulogic; -- read/write
ahbo_hsize: out std_logic_vector(2 downto 0); -- transfer size
ahbo_hburst: out std_logic_vector(2 downto 0); -- burst type
ahbo_hprot: out std_logic_vector(3 downto 0); -- protection control
ahbo_hwdata: out std_logic_vector(31 downto 0); -- write data bus
ahbo_hirq: out std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
ahbsi_hsel: in std_logic_vector(0 to NAHBSLV-1); -- slave select
ahbsi_haddr: in std_logic_vector(31 downto 0); -- address bus (byte)
ahbsi_hwrite: in std_ulogic; -- read/write
ahbsi_htrans: in std_logic_vector(1 downto 0); -- transfer type
ahbsi_hsize: in std_logic_vector(2 downto 0); -- transfer size
ahbsi_hburst: in std_logic_vector(2 downto 0); -- burst type
ahbsi_hwdata: in std_logic_vector(31 downto 0); -- write data bus
ahbsi_hprot: in std_logic_vector(3 downto 0); -- protection control
ahbsi_hready: in std_ulogic; -- transfer done
ahbsi_hmaster: in std_logic_vector(3 downto 0); -- current master
ahbsi_hmastlock: in std_ulogic; -- locked access
ahbsi_hmbsel: in std_logic_vector(0 to NAHBAMR-1); -- memory bank select
ahbsi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
irqi_irl: in std_logic_vector(3 downto 0);
irqi_rst: in std_ulogic;
irqi_run: in std_ulogic;
irqo_intack: out std_ulogic;
irqo_irl: out std_logic_vector(3 downto 0);
irqo_pwd: out std_ulogic;
dbgi_dsuen: in std_ulogic; -- DSU enable
dbgi_denable: in std_ulogic; -- diagnostic register access enable
dbgi_dbreak: in std_ulogic; -- debug break-in
dbgi_step: in std_ulogic; -- single step
dbgi_halt: in std_ulogic; -- halt processor
dbgi_reset: in std_ulogic; -- reset processor
dbgi_dwrite: in std_ulogic; -- read/write
dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa: in std_ulogic; -- break on IU trap
dbgi_btrape: in std_ulogic; -- break on IU trap
dbgi_berror: in std_ulogic; -- break on IU error mode
dbgi_bwatch: in std_ulogic; -- break on IU watchpoint
dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable: in std_ulogic;
dbgi_timer: in std_logic_vector(30 downto 0);
dbgo_data: out std_logic_vector(31 downto 0);
dbgo_crdy: out std_ulogic;
dbgo_dsu: out std_ulogic;
dbgo_dsumode: out std_ulogic;
dbgo_error: out std_ulogic;
dbgo_halt: out std_ulogic;
dbgo_pwd: out std_logic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic;
disasen : in std_logic);
end component;
component leon3ft_proasic3e is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0);
port (
clk: in std_ulogic;
rstn: in std_ulogic;
ahbi_hgrant: in std_logic_vector(0 to NAHBMST-1); -- bus grant
ahbi_hready: in std_ulogic; -- transfer done
ahbi_hresp: in std_logic_vector(1 downto 0); -- response type
ahbi_hrdata: in std_logic_vector(31 downto 0); -- read data bus
ahbi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
ahbo_hbusreq: out std_ulogic; -- bus request
ahbo_hlock: out std_ulogic; -- lock request
ahbo_htrans: out std_logic_vector(1 downto 0); -- transfer type
ahbo_haddr: out std_logic_vector(31 downto 0); -- address bus (byte)
ahbo_hwrite: out std_ulogic; -- read/write
ahbo_hsize: out std_logic_vector(2 downto 0); -- transfer size
ahbo_hburst: out std_logic_vector(2 downto 0); -- burst type
ahbo_hprot: out std_logic_vector(3 downto 0); -- protection control
ahbo_hwdata: out std_logic_vector(31 downto 0); -- write data bus
ahbo_hirq: out std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
ahbsi_hsel: in std_logic_vector(0 to NAHBSLV-1); -- slave select
ahbsi_haddr: in std_logic_vector(31 downto 0); -- address bus (byte)
ahbsi_hwrite: in std_ulogic; -- read/write
ahbsi_htrans: in std_logic_vector(1 downto 0); -- transfer type
ahbsi_hsize: in std_logic_vector(2 downto 0); -- transfer size
ahbsi_hburst: in std_logic_vector(2 downto 0); -- burst type
ahbsi_hwdata: in std_logic_vector(31 downto 0); -- write data bus
ahbsi_hprot: in std_logic_vector(3 downto 0); -- protection control
ahbsi_hready: in std_ulogic; -- transfer done
ahbsi_hmaster: in std_logic_vector(3 downto 0); -- current master
ahbsi_hmastlock: in std_ulogic; -- locked access
ahbsi_hmbsel: in std_logic_vector(0 to NAHBAMR-1); -- memory bank select
ahbsi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
irqi_irl: in std_logic_vector(3 downto 0);
irqi_rst: in std_ulogic;
irqi_run: in std_ulogic;
irqo_intack: out std_ulogic;
irqo_irl: out std_logic_vector(3 downto 0);
irqo_pwd: out std_ulogic;
dbgi_dsuen: in std_ulogic; -- DSU enable
dbgi_denable: in std_ulogic; -- diagnostic register access enable
dbgi_dbreak: in std_ulogic; -- debug break-in
dbgi_step: in std_ulogic; -- single step
dbgi_halt: in std_ulogic; -- halt processor
dbgi_reset: in std_ulogic; -- reset processor
dbgi_dwrite: in std_ulogic; -- read/write
dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa: in std_ulogic; -- break on IU trap
dbgi_btrape: in std_ulogic; -- break on IU trap
dbgi_berror: in std_ulogic; -- break on IU error mode
dbgi_bwatch: in std_ulogic; -- break on IU watchpoint
dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable: in std_ulogic;
dbgi_timer: in std_logic_vector(30 downto 0);
dbgo_data: out std_logic_vector(31 downto 0);
dbgo_crdy: out std_ulogic;
dbgo_dsu: out std_ulogic;
dbgo_dsumode: out std_ulogic;
dbgo_error: out std_ulogic;
dbgo_halt: out std_ulogic;
dbgo_pwd: out std_logic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic;
disasen : in std_logic);
end component;
component leon3ft_proasic3l is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0);
port (
clk: in std_ulogic;
rstn: in std_ulogic;
ahbi_hgrant: in std_logic_vector(0 to NAHBMST-1); -- bus grant
ahbi_hready: in std_ulogic; -- transfer done
ahbi_hresp: in std_logic_vector(1 downto 0); -- response type
ahbi_hrdata: in std_logic_vector(31 downto 0); -- read data bus
ahbi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
ahbo_hbusreq: out std_ulogic; -- bus request
ahbo_hlock: out std_ulogic; -- lock request
ahbo_htrans: out std_logic_vector(1 downto 0); -- transfer type
ahbo_haddr: out std_logic_vector(31 downto 0); -- address bus (byte)
ahbo_hwrite: out std_ulogic; -- read/write
ahbo_hsize: out std_logic_vector(2 downto 0); -- transfer size
ahbo_hburst: out std_logic_vector(2 downto 0); -- burst type
ahbo_hprot: out std_logic_vector(3 downto 0); -- protection control
ahbo_hwdata: out std_logic_vector(31 downto 0); -- write data bus
ahbo_hirq: out std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
ahbsi_hsel: in std_logic_vector(0 to NAHBSLV-1); -- slave select
ahbsi_haddr: in std_logic_vector(31 downto 0); -- address bus (byte)
ahbsi_hwrite: in std_ulogic; -- read/write
ahbsi_htrans: in std_logic_vector(1 downto 0); -- transfer type
ahbsi_hsize: in std_logic_vector(2 downto 0); -- transfer size
ahbsi_hburst: in std_logic_vector(2 downto 0); -- burst type
ahbsi_hwdata: in std_logic_vector(31 downto 0); -- write data bus
ahbsi_hprot: in std_logic_vector(3 downto 0); -- protection control
ahbsi_hready: in std_ulogic; -- transfer done
ahbsi_hmaster: in std_logic_vector(3 downto 0); -- current master
ahbsi_hmastlock: in std_ulogic; -- locked access
ahbsi_hmbsel: in std_logic_vector(0 to NAHBAMR-1); -- memory bank select
ahbsi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
irqi_irl: in std_logic_vector(3 downto 0);
irqi_rst: in std_ulogic;
irqi_run: in std_ulogic;
irqo_intack: out std_ulogic;
irqo_irl: out std_logic_vector(3 downto 0);
irqo_pwd: out std_ulogic;
dbgi_dsuen: in std_ulogic; -- DSU enable
dbgi_denable: in std_ulogic; -- diagnostic register access enable
dbgi_dbreak: in std_ulogic; -- debug break-in
dbgi_step: in std_ulogic; -- single step
dbgi_halt: in std_ulogic; -- halt processor
dbgi_reset: in std_ulogic; -- reset processor
dbgi_dwrite: in std_ulogic; -- read/write
dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa: in std_ulogic; -- break on IU trap
dbgi_btrape: in std_ulogic; -- break on IU trap
dbgi_berror: in std_ulogic; -- break on IU error mode
dbgi_bwatch: in std_ulogic; -- break on IU watchpoint
dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable: in std_ulogic;
dbgi_timer: in std_logic_vector(30 downto 0);
dbgo_data: out std_logic_vector(31 downto 0);
dbgo_crdy: out std_ulogic;
dbgo_dsu: out std_ulogic;
dbgo_dsumode: out std_ulogic;
dbgo_error: out std_ulogic;
dbgo_halt: out std_ulogic;
dbgo_pwd: out std_logic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic;
disasen : in std_logic);
end component;
component leon3ft_atc18rha
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 1 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 1 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0
);
port (
clk: in std_ulogic;
gclk: in std_ulogic;
rstn: in std_ulogic;
ahbi_hgrant: in std_logic_vector(0 to NAHBMST-1); -- bus grant
ahbi_hready: in std_ulogic; -- transfer done
ahbi_hresp: in std_logic_vector(1 downto 0); -- response type
ahbi_hrdata: in std_logic_vector(31 downto 0); -- read data bus
ahbi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
ahbi_testen: in std_ulogic;
ahbi_testrst: in std_ulogic;
ahbi_scanen: in std_ulogic;
ahbi_testoen: in std_ulogic;
ahbo_hbusreq: out std_ulogic; -- bus request
ahbo_hlock: out std_ulogic; -- lock request
ahbo_htrans: out std_logic_vector(1 downto 0); -- transfer type
ahbo_haddr: out std_logic_vector(31 downto 0); -- address bus (byte)
ahbo_hwrite: out std_ulogic; -- read/write
ahbo_hsize: out std_logic_vector(2 downto 0); -- transfer size
ahbo_hburst: out std_logic_vector(2 downto 0); -- burst type
ahbo_hprot: out std_logic_vector(3 downto 0); -- protection control
ahbo_hwdata: out std_logic_vector(31 downto 0); -- write data bus
ahbo_hirq: out std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
ahbsi_hsel: in std_logic_vector(0 to NAHBSLV-1); -- slave select
ahbsi_haddr: in std_logic_vector(31 downto 0); -- address bus (byte)
ahbsi_hwrite: in std_ulogic; -- read/write
ahbsi_htrans: in std_logic_vector(1 downto 0); -- transfer type
ahbsi_hsize: in std_logic_vector(2 downto 0); -- transfer size
ahbsi_hburst: in std_logic_vector(2 downto 0); -- burst type
ahbsi_hwdata: in std_logic_vector(31 downto 0); -- write data bus
ahbsi_hprot: in std_logic_vector(3 downto 0); -- protection control
ahbsi_hready: in std_ulogic; -- transfer done
ahbsi_hmaster: in std_logic_vector(3 downto 0); -- current master
ahbsi_hmastlock: in std_ulogic; -- locked access
ahbsi_hmbsel: in std_logic_vector(0 to NAHBAMR-1); -- memory bank select
ahbsi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
irqi_irl: in std_logic_vector(3 downto 0);
irqi_rst: in std_ulogic;
irqi_run: in std_ulogic;
irqo_intack: out std_ulogic;
irqo_irl: out std_logic_vector(3 downto 0);
irqo_pwd: out std_ulogic;
dbgi_dsuen: in std_ulogic; -- DSU enable
dbgi_denable: in std_ulogic; -- diagnostic register access enable
dbgi_dbreak: in std_ulogic; -- debug break-in
dbgi_step: in std_ulogic; -- single step
dbgi_halt: in std_ulogic; -- halt processor
dbgi_reset: in std_ulogic; -- reset processor
dbgi_dwrite: in std_ulogic; -- read/write
dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa: in std_ulogic; -- break on IU trap
dbgi_btrape: in std_ulogic; -- break on IU trap
dbgi_berror: in std_ulogic; -- break on IU error mode
dbgi_bwatch: in std_ulogic; -- break on IU watchpoint
dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable: in std_ulogic;
dbgi_timer: in std_logic_vector(30 downto 0);
dbgo_data: out std_logic_vector(31 downto 0);
dbgo_crdy: out std_ulogic;
dbgo_dsu: out std_ulogic;
dbgo_dsumode: out std_ulogic;
dbgo_error: out std_ulogic;
dbgo_halt: out std_ulogic;
dbgo_pwd: out std_ulogic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic;
disasen : in std_ulogic);
end component;
component leon3ft_cycloneiv
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic; -- free-running clock
gclk2 : in std_ulogic; -- gated 2x clock
gfclk2 : in std_ulogic; -- gated 2x FPU clock
clk2 : in std_ulogic; -- free-running 2x clock
rstn : in std_ulogic;
ahbi_hgrant: in std_logic_vector(0 to NAHBMST-1); -- bus grant
ahbi_hready: in std_ulogic; -- transfer done
ahbi_hresp: in std_logic_vector(1 downto 0); -- response type
ahbi_hrdata: in std_logic_vector(31 downto 0); -- read data bus
ahbi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
ahbi_testen: in std_ulogic;
ahbi_testrst: in std_ulogic;
ahbi_scanen: in std_ulogic;
ahbi_testoen: in std_ulogic;
ahbo_hbusreq: out std_ulogic; -- bus request
ahbo_hlock: out std_ulogic; -- lock request
ahbo_htrans: out std_logic_vector(1 downto 0); -- transfer type
ahbo_haddr: out std_logic_vector(31 downto 0); -- address bus (byte)
ahbo_hwrite: out std_ulogic; -- read/write
ahbo_hsize: out std_logic_vector(2 downto 0); -- transfer size
ahbo_hburst: out std_logic_vector(2 downto 0); -- burst type
ahbo_hprot: out std_logic_vector(3 downto 0); -- protection control
ahbo_hwdata: out std_logic_vector(31 downto 0); -- write data bus
ahbo_hirq: out std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
ahbsi_hsel: in std_logic_vector(0 to NAHBSLV-1); -- slave select
ahbsi_haddr: in std_logic_vector(31 downto 0); -- address bus (byte)
ahbsi_hwrite: in std_ulogic; -- read/write
ahbsi_htrans: in std_logic_vector(1 downto 0); -- transfer type
ahbsi_hsize: in std_logic_vector(2 downto 0); -- transfer size
ahbsi_hburst: in std_logic_vector(2 downto 0); -- burst type
ahbsi_hwdata: in std_logic_vector(31 downto 0); -- write data bus
ahbsi_hprot: in std_logic_vector(3 downto 0); -- protection control
ahbsi_hready: in std_ulogic; -- transfer done
ahbsi_hmaster: in std_logic_vector(3 downto 0); -- current master
ahbsi_hmastlock: in std_ulogic; -- locked access
ahbsi_hmbsel: in std_logic_vector(0 to NAHBAMR-1); -- memory bank select
ahbsi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
irqi_irl : in std_logic_vector(3 downto 0);
irqi_rst : in std_ulogic;
irqi_run : in std_ulogic;
irqi_rstvec : in std_logic_vector(31 downto 12);
irqi_iact : in std_ulogic;
irqi_index : in std_logic_vector(3 downto 0);
irqi_hrdrst : in std_ulogic;
irqo_intack : out std_ulogic;
irqo_irl : out std_logic_vector(3 downto 0);
irqo_pwd : out std_ulogic;
irqo_fpen : out std_ulogic;
irqo_idle : out std_ulogic;
dbgi_dsuen : in std_ulogic; -- DSU enable
dbgi_denable : in std_ulogic; -- diagnostic register access enablee
dbgi_dbreak : in std_ulogic; -- debug break-in
dbgi_step : in std_ulogic; -- single step
dbgi_halt : in std_ulogic; -- halt processor
dbgi_reset : in std_ulogic; -- reset processor
dbgi_dwrite : in std_ulogic; -- read/write
dbgi_daddr : in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata : in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa : in std_ulogic; -- break on IU trap
dbgi_btrape : in std_ulogic; -- break on IU trap
dbgi_berror : in std_ulogic; -- break on IU error mode
dbgi_bwatch : in std_ulogic; -- break on IU watchpoint
dbgi_bsoft : in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable : in std_ulogic;
dbgi_timer : in std_logic_vector(30 downto 0);
dbgo_data : out std_logic_vector(31 downto 0);
dbgo_crdy : out std_ulogic;
dbgo_dsu : out std_ulogic;
dbgo_dsumode : out std_ulogic;
dbgo_error : out std_ulogic;
dbgo_halt : out std_ulogic;
dbgo_pwd : out std_ulogic;
dbgo_idle : out std_ulogic;
dbgo_ipend : out std_ulogic;
dbgo_icnt : out std_ulogic;
dbgo_fcnt : out std_ulogic;
dbgo_optype : out std_logic_vector(5 downto 0); -- instruction type
dbgo_bpmiss : out std_ulogic; -- branch predict miss
dbgo_istat_cmiss : out std_ulogic;
dbgo_istat_tmiss : out std_ulogic;
dbgo_istat_chold : out std_ulogic;
dbgo_istat_mhold : out std_ulogic;
dbgo_dstat_cmiss : out std_ulogic;
dbgo_dstat_tmiss : out std_ulogic;
dbgo_dstat_chold : out std_ulogic;
dbgo_dstat_mhold : out std_ulogic;
dbgo_wbhold : out std_ulogic; -- write buffer hold
dbgo_su : out std_ulogic;
-- fpui : out grfpu_in_type;
-- fpuo : in grfpu_out_type;
clken : in std_ulogic);
end component;
signal ahbi_hgrant: std_logic_vector(0 to NAHBMST-1);
signal ahbi_hready: std_ulogic;
signal ahbi_hresp: std_logic_vector(1 downto 0);
signal ahbi_hrdata: std_logic_vector(31 downto 0);
signal ahbi_hirq: std_logic_vector(NAHBIRQ-1 downto 0);
signal ahbi_testen: std_ulogic;
signal ahbi_testrst: std_ulogic;
signal ahbi_scanen: std_ulogic;
signal ahbi_testoen: std_ulogic;
signal ahbo_hbusreq: std_ulogic;
signal ahbo_hlock: std_ulogic;
signal ahbo_htrans: std_logic_vector(1 downto 0);
signal ahbo_haddr: std_logic_vector(31 downto 0);
signal ahbo_hwrite: std_ulogic;
signal ahbo_hsize: std_logic_vector(2 downto 0);
signal ahbo_hburst: std_logic_vector(2 downto 0);
signal ahbo_hprot: std_logic_vector(3 downto 0);
signal ahbo_hwdata: std_logic_vector(31 downto 0);
signal ahbo_hirq: std_logic_vector(NAHBIRQ-1 downto 0);
signal ahbsi_hsel: std_logic_vector(0 to NAHBSLV-1);
signal ahbsi_haddr: std_logic_vector(31 downto 0);
signal ahbsi_hwrite: std_ulogic;
signal ahbsi_htrans: std_logic_vector(1 downto 0);
signal ahbsi_hsize: std_logic_vector(2 downto 0);
signal ahbsi_hburst: std_logic_vector(2 downto 0);
signal ahbsi_hwdata: std_logic_vector(31 downto 0);
signal ahbsi_hprot: std_logic_vector(3 downto 0);
signal ahbsi_hready: std_ulogic;
signal ahbsi_hmaster: std_logic_vector(3 downto 0);
signal ahbsi_hmastlock: std_ulogic;
signal ahbsi_hmbsel: std_logic_vector(0 to NAHBAMR-1);
signal ahbsi_hirq: std_logic_vector(NAHBIRQ-1 downto 0);
constant L3DI :integer := GAISLER_LEON3
;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg (VENDOR_GAISLER, L3DI, 0, 3, 0),
others => zero32);
begin
disasen <= '1' when disas /= 0 else '0';
-- Plug&Play information
ahbo.hconfig <= hconfig;
ahbo.hindex <= hindex;
ax : if fabtech = axcel generate
-- pragma translate_off
assert false
report "LEON3 netlist: netlist for this technology is deprecated"
severity failure;
-- pragma translate_on
wrp: leon3ft_axcelerator
generic map (fpu => fpu, v8 => v8, mmuen => mmuen, isets => isets, isetsize => isetsize)
port map(
clk => clk,
rstn => rstn,
ahbi_hgrant => ahbi_hgrant,
ahbi_hready => ahbi_hready,
ahbi_hresp => ahbi_hresp,
ahbi_hrdata => ahbi_hrdata,
ahbi_hirq => ahbi_hirq,
ahbo_hbusreq => ahbo_hbusreq,
ahbo_hlock => ahbo_hlock,
ahbo_htrans => ahbo_htrans,
ahbo_haddr => ahbo_haddr,
ahbo_hwrite => ahbo_hwrite,
ahbo_hsize => ahbo_hsize,
ahbo_hburst => ahbo_hburst,
ahbo_hprot => ahbo_hprot,
ahbo_hwdata => ahbo_hwdata,
ahbo_hirq => ahbo_hirq,
ahbsi_hsel => ahbsi_hsel,
ahbsi_haddr => ahbsi_haddr,
ahbsi_hwrite => ahbsi_hwrite,
ahbsi_htrans => ahbsi_htrans,
ahbsi_hsize => ahbsi_hsize,
ahbsi_hburst => ahbsi_hburst,
ahbsi_hwdata => ahbsi_hwdata,
ahbsi_hprot => ahbsi_hprot,
ahbsi_hready => ahbsi_hready,
ahbsi_hmaster => ahbsi_hmaster,
ahbsi_hmastlock => ahbsi_hmastlock,
ahbsi_hmbsel => ahbsi_hmbsel,
ahbsi_hirq => ahbsi_hirq,
irqi_irl => irqi_irl,
irqi_rst => irqi_rst,
irqi_run => irqi_run,
irqo_intack => irqo_intack,
irqo_irl => irqo_irl,
irqo_pwd => irqo_pwd,
dbgi_dsuen => dbgi_dsuen,
dbgi_denable => dbgi_denable,
dbgi_dbreak => dbgi_dbreak,
dbgi_step => dbgi_step,
dbgi_halt => dbgi_halt,
dbgi_reset => dbgi_reset,
dbgi_dwrite => dbgi_dwrite,
dbgi_daddr => dbgi_daddr,
dbgi_ddata => dbgi_ddata,
dbgi_btrapa => dbgi_btrapa,
dbgi_btrape => dbgi_btrape,
dbgi_berror => dbgi_berror,
dbgi_bwatch => dbgi_bwatch,
dbgi_bsoft => dbgi_bsoft,
dbgi_tenable => dbgi_tenable,
dbgi_timer => dbgi_timer,
dbgo_data => dbgo_data,
dbgo_crdy => dbgo_crdy,
dbgo_dsu => dbgo_dsu,
dbgo_dsumode => dbgo_dsumode,
dbgo_error => dbgo_error,
dbgo_halt => dbgo_halt,
dbgo_pwd => dbgo_pwd,
dbgo_idle => dbgo_idle,
dbgo_ipend => dbgo_ipend,
dbgo_icnt => dbgo_icnt,
disasen => disasen);
end generate;
pa3 : if (fabtech = apa3) generate
-- pragma translate_off
assert false
report "LEON3 netlist: netlist for this technology is deprecated"
severity failure;
-- pragma translate_on
wrp: leon3ft_proasic3
generic map (fpu => fpu, v8 => v8, mmuen => mmuen, isets => isets, isetsize => isetsize)
port map(
clk => clk,
rstn => rstn,
ahbi_hgrant => ahbi_hgrant,
ahbi_hready => ahbi_hready,
ahbi_hresp => ahbi_hresp,
ahbi_hrdata => ahbi_hrdata,
ahbi_hirq => ahbi_hirq,
ahbo_hbusreq => ahbo_hbusreq,
ahbo_hlock => ahbo_hlock,
ahbo_htrans => ahbo_htrans,
ahbo_haddr => ahbo_haddr,
ahbo_hwrite => ahbo_hwrite,
ahbo_hsize => ahbo_hsize,
ahbo_hburst => ahbo_hburst,
ahbo_hprot => ahbo_hprot,
ahbo_hwdata => ahbo_hwdata,
ahbo_hirq => ahbo_hirq,
ahbsi_hsel => ahbsi_hsel,
ahbsi_haddr => ahbsi_haddr,
ahbsi_hwrite => ahbsi_hwrite,
ahbsi_htrans => ahbsi_htrans,
ahbsi_hsize => ahbsi_hsize,
ahbsi_hburst => ahbsi_hburst,
ahbsi_hwdata => ahbsi_hwdata,
ahbsi_hprot => ahbsi_hprot,
ahbsi_hready => ahbsi_hready,
ahbsi_hmaster => ahbsi_hmaster,
ahbsi_hmastlock => ahbsi_hmastlock,
ahbsi_hmbsel => ahbsi_hmbsel,
ahbsi_hirq => ahbsi_hirq,
irqi_irl => irqi_irl,
irqi_rst => irqi_rst,
irqi_run => irqi_run,
irqo_intack => irqo_intack,
irqo_irl => irqo_irl,
irqo_pwd => irqo_pwd,
dbgi_dsuen => dbgi_dsuen,
dbgi_denable => dbgi_denable,
dbgi_dbreak => dbgi_dbreak,
dbgi_step => dbgi_step,
dbgi_halt => dbgi_halt,
dbgi_reset => dbgi_reset,
dbgi_dwrite => dbgi_dwrite,
dbgi_daddr => dbgi_daddr,
dbgi_ddata => dbgi_ddata,
dbgi_btrapa => dbgi_btrapa,
dbgi_btrape => dbgi_btrape,
dbgi_berror => dbgi_berror,
dbgi_bwatch => dbgi_bwatch,
dbgi_bsoft => dbgi_bsoft,
dbgi_tenable => dbgi_tenable,
dbgi_timer => dbgi_timer,
dbgo_data => dbgo_data,
dbgo_crdy => dbgo_crdy,
dbgo_dsu => dbgo_dsu,
dbgo_dsumode => dbgo_dsumode,
dbgo_error => dbgo_error,
dbgo_halt => dbgo_halt,
dbgo_pwd => dbgo_pwd,
dbgo_idle => dbgo_idle,
dbgo_ipend => dbgo_ipend,
dbgo_icnt => dbgo_icnt,
disasen => disasen);
end generate;
pa3e : if (fabtech = apa3e) generate
-- pragma translate_off
assert false
report "LEON3 netlist: netlist for this technology is deprecated"
severity failure;
-- pragma translate_on
wrp: leon3ft_proasic3e
generic map (fpu => fpu, v8 => v8, mmuen => mmuen, isets => isets, isetsize => isetsize)
port map(
clk => clk,
rstn => rstn,
ahbi_hgrant => ahbi_hgrant,
ahbi_hready => ahbi_hready,
ahbi_hresp => ahbi_hresp,
ahbi_hrdata => ahbi_hrdata,
ahbi_hirq => ahbi_hirq,
ahbo_hbusreq => ahbo_hbusreq,
ahbo_hlock => ahbo_hlock,
ahbo_htrans => ahbo_htrans,
ahbo_haddr => ahbo_haddr,
ahbo_hwrite => ahbo_hwrite,
ahbo_hsize => ahbo_hsize,
ahbo_hburst => ahbo_hburst,
ahbo_hprot => ahbo_hprot,
ahbo_hwdata => ahbo_hwdata,
ahbo_hirq => ahbo_hirq,
ahbsi_hsel => ahbsi_hsel,
ahbsi_haddr => ahbsi_haddr,
ahbsi_hwrite => ahbsi_hwrite,
ahbsi_htrans => ahbsi_htrans,
ahbsi_hsize => ahbsi_hsize,
ahbsi_hburst => ahbsi_hburst,
ahbsi_hwdata => ahbsi_hwdata,
ahbsi_hprot => ahbsi_hprot,
ahbsi_hready => ahbsi_hready,
ahbsi_hmaster => ahbsi_hmaster,
ahbsi_hmastlock => ahbsi_hmastlock,
ahbsi_hmbsel => ahbsi_hmbsel,
ahbsi_hirq => ahbsi_hirq,
irqi_irl => irqi_irl,
irqi_rst => irqi_rst,
irqi_run => irqi_run,
irqo_intack => irqo_intack,
irqo_irl => irqo_irl,
irqo_pwd => irqo_pwd,
dbgi_dsuen => dbgi_dsuen,
dbgi_denable => dbgi_denable,
dbgi_dbreak => dbgi_dbreak,
dbgi_step => dbgi_step,
dbgi_halt => dbgi_halt,
dbgi_reset => dbgi_reset,
dbgi_dwrite => dbgi_dwrite,
dbgi_daddr => dbgi_daddr,
dbgi_ddata => dbgi_ddata,
dbgi_btrapa => dbgi_btrapa,
dbgi_btrape => dbgi_btrape,
dbgi_berror => dbgi_berror,
dbgi_bwatch => dbgi_bwatch,
dbgi_bsoft => dbgi_bsoft,
dbgi_tenable => dbgi_tenable,
dbgi_timer => dbgi_timer,
dbgo_data => dbgo_data,
dbgo_crdy => dbgo_crdy,
dbgo_dsu => dbgo_dsu,
dbgo_dsumode => dbgo_dsumode,
dbgo_error => dbgo_error,
dbgo_halt => dbgo_halt,
dbgo_pwd => dbgo_pwd,
dbgo_idle => dbgo_idle,
dbgo_ipend => dbgo_ipend,
dbgo_icnt => dbgo_icnt,
disasen => disasen);
end generate;
pa3l : if (fabtech = apa3l) generate
-- pragma translate_off
assert false
report "LEON3 netlist: netlist for this technology is deprecated"
severity failure;
-- pragma translate_on
wrp: leon3ft_proasic3l
generic map (fpu => fpu, v8 => v8, mmuen => mmuen, isets => isets, isetsize => isetsize)
port map(
clk => clk,
rstn => rstn,
ahbi_hgrant => ahbi_hgrant,
ahbi_hready => ahbi_hready,
ahbi_hresp => ahbi_hresp,
ahbi_hrdata => ahbi_hrdata,
ahbi_hirq => ahbi_hirq,
ahbo_hbusreq => ahbo_hbusreq,
ahbo_hlock => ahbo_hlock,
ahbo_htrans => ahbo_htrans,
ahbo_haddr => ahbo_haddr,
ahbo_hwrite => ahbo_hwrite,
ahbo_hsize => ahbo_hsize,
ahbo_hburst => ahbo_hburst,
ahbo_hprot => ahbo_hprot,
ahbo_hwdata => ahbo_hwdata,
ahbo_hirq => ahbo_hirq,
ahbsi_hsel => ahbsi_hsel,
ahbsi_haddr => ahbsi_haddr,
ahbsi_hwrite => ahbsi_hwrite,
ahbsi_htrans => ahbsi_htrans,
ahbsi_hsize => ahbsi_hsize,
ahbsi_hburst => ahbsi_hburst,
ahbsi_hwdata => ahbsi_hwdata,
ahbsi_hprot => ahbsi_hprot,
ahbsi_hready => ahbsi_hready,
ahbsi_hmaster => ahbsi_hmaster,
ahbsi_hmastlock => ahbsi_hmastlock,
ahbsi_hmbsel => ahbsi_hmbsel,
ahbsi_hirq => ahbsi_hirq,
irqi_irl => irqi_irl,
irqi_rst => irqi_rst,
irqi_run => irqi_run,
irqo_intack => irqo_intack,
irqo_irl => irqo_irl,
irqo_pwd => irqo_pwd,
dbgi_dsuen => dbgi_dsuen,
dbgi_denable => dbgi_denable,
dbgi_dbreak => dbgi_dbreak,
dbgi_step => dbgi_step,
dbgi_halt => dbgi_halt,
dbgi_reset => dbgi_reset,
dbgi_dwrite => dbgi_dwrite,
dbgi_daddr => dbgi_daddr,
dbgi_ddata => dbgi_ddata,
dbgi_btrapa => dbgi_btrapa,
dbgi_btrape => dbgi_btrape,
dbgi_berror => dbgi_berror,
dbgi_bwatch => dbgi_bwatch,
dbgi_bsoft => dbgi_bsoft,
dbgi_tenable => dbgi_tenable,
dbgi_timer => dbgi_timer,
dbgo_data => dbgo_data,
dbgo_crdy => dbgo_crdy,
dbgo_dsu => dbgo_dsu,
dbgo_dsumode => dbgo_dsumode,
dbgo_error => dbgo_error,
dbgo_halt => dbgo_halt,
dbgo_pwd => dbgo_pwd,
dbgo_idle => dbgo_idle,
dbgo_ipend => dbgo_ipend,
dbgo_icnt => dbgo_icnt,
disasen => disasen);
end generate;
xil : if (is_unisim(fabtech) = 1) generate
-- pragma translate_off
assert false
report "LEON3 netlist: netlist for this technology is deprecated"
severity failure;
-- pragma translate_on
wrp: leon3ft_unisim
generic map (fabtech => fabtech, fpu => fpu, v8 => v8, mmuen => mmuen, isets => isets, isetsize => isetsize)
port map(
clk => clk,
rstn => rstn,
ahbi_hgrant => ahbi_hgrant,
ahbi_hready => ahbi_hready,
ahbi_hresp => ahbi_hresp,
ahbi_hrdata => ahbi_hrdata,
ahbi_hirq => ahbi_hirq,
ahbo_hbusreq => ahbo_hbusreq,
ahbo_hlock => ahbo_hlock,
ahbo_htrans => ahbo_htrans,
ahbo_haddr => ahbo_haddr,
ahbo_hwrite => ahbo_hwrite,
ahbo_hsize => ahbo_hsize,
ahbo_hburst => ahbo_hburst,
ahbo_hprot => ahbo_hprot,
ahbo_hwdata => ahbo_hwdata,
ahbo_hirq => ahbo_hirq,
ahbsi_hsel => ahbsi_hsel,
ahbsi_haddr => ahbsi_haddr,
ahbsi_hwrite => ahbsi_hwrite,
ahbsi_htrans => ahbsi_htrans,
ahbsi_hsize => ahbsi_hsize,
ahbsi_hburst => ahbsi_hburst,
ahbsi_hwdata => ahbsi_hwdata,
ahbsi_hprot => ahbsi_hprot,
ahbsi_hready => ahbsi_hready,
ahbsi_hmaster => ahbsi_hmaster,
ahbsi_hmastlock => ahbsi_hmastlock,
ahbsi_hmbsel => ahbsi_hmbsel,
ahbsi_hirq => ahbsi_hirq,
irqi_irl => irqi_irl,
irqi_rst => irqi_rst,
irqi_run => irqi_run,
irqo_intack => irqo_intack,
irqo_irl => irqo_irl,
irqo_pwd => irqo_pwd,
dbgi_dsuen => dbgi_dsuen,
dbgi_denable => dbgi_denable,
dbgi_dbreak => dbgi_dbreak,
dbgi_step => dbgi_step,
dbgi_halt => dbgi_halt,
dbgi_reset => dbgi_reset,
dbgi_dwrite => dbgi_dwrite,
dbgi_daddr => dbgi_daddr,
dbgi_ddata => dbgi_ddata,
dbgi_btrapa => dbgi_btrapa,
dbgi_btrape => dbgi_btrape,
dbgi_berror => dbgi_berror,
dbgi_bwatch => dbgi_bwatch,
dbgi_bsoft => dbgi_bsoft,
dbgi_tenable => dbgi_tenable,
dbgi_timer => dbgi_timer,
dbgo_data => dbgo_data,
dbgo_crdy => dbgo_crdy,
dbgo_dsu => dbgo_dsu,
dbgo_dsumode => dbgo_dsumode,
dbgo_error => dbgo_error,
dbgo_halt => dbgo_halt,
dbgo_pwd => dbgo_pwd,
dbgo_idle => dbgo_idle,
dbgo_ipend => dbgo_ipend,
dbgo_icnt => dbgo_icnt,
disasen => disasen);
end generate;
atc : if fabtech = atc18rha generate
-- pragma translate_off
assert false
report "LEON3 netlist: netlist for this technology is deprecated"
severity failure;
-- pragma translate_on
wrp: leon3ft_atc18rha
generic map (fpu => fpu, v8 => v8, mmuen => mmuen, isets => isets, isetsize => isetsize)
port map(
clk => clk,
gclk => gclk2,
rstn => rstn,
ahbi_hgrant => ahbi_hgrant,
ahbi_hready => ahbi_hready,
ahbi_hresp => ahbi_hresp,
ahbi_hrdata => ahbi_hrdata,
ahbi_hirq => ahbi_hirq,
ahbi_testen => ahbi_testen,
ahbi_testrst => ahbi_testrst,
ahbi_scanen => ahbi_scanen,
ahbi_testoen => ahbi_testoen,
ahbo_hbusreq => ahbo_hbusreq,
ahbo_hlock => ahbo_hlock,
ahbo_htrans => ahbo_htrans,
ahbo_haddr => ahbo_haddr,
ahbo_hwrite => ahbo_hwrite,
ahbo_hsize => ahbo_hsize,
ahbo_hburst => ahbo_hburst,
ahbo_hprot => ahbo_hprot,
ahbo_hwdata => ahbo_hwdata,
ahbo_hirq => ahbo_hirq,
ahbsi_hsel => ahbsi_hsel,
ahbsi_haddr => ahbsi_haddr,
ahbsi_hwrite => ahbsi_hwrite,
ahbsi_htrans => ahbsi_htrans,
ahbsi_hsize => ahbsi_hsize,
ahbsi_hburst => ahbsi_hburst,
ahbsi_hwdata => ahbsi_hwdata,
ahbsi_hprot => ahbsi_hprot,
ahbsi_hready => ahbsi_hready,
ahbsi_hmaster => ahbsi_hmaster,
ahbsi_hmastlock => ahbsi_hmastlock,
ahbsi_hmbsel => ahbsi_hmbsel,
ahbsi_hirq => ahbsi_hirq,
irqi_irl => irqi_irl,
irqi_rst => irqi_rst,
irqi_run => irqi_run,
irqo_intack => irqo_intack,
irqo_irl => irqo_irl,
irqo_pwd => irqo_pwd,
dbgi_dsuen => dbgi_dsuen,
dbgi_denable => dbgi_denable,
dbgi_dbreak => dbgi_dbreak,
dbgi_step => dbgi_step,
dbgi_halt => dbgi_halt,
dbgi_reset => dbgi_reset,
dbgi_dwrite => dbgi_dwrite,
dbgi_daddr => dbgi_daddr,
dbgi_ddata => dbgi_ddata,
dbgi_btrapa => dbgi_btrapa,
dbgi_btrape => dbgi_btrape,
dbgi_berror => dbgi_berror,
dbgi_bwatch => dbgi_bwatch,
dbgi_bsoft => dbgi_bsoft,
dbgi_tenable => dbgi_tenable,
dbgi_timer => dbgi_timer,
dbgo_data => dbgo_data,
dbgo_crdy => dbgo_crdy,
dbgo_dsu => dbgo_dsu,
dbgo_dsumode => dbgo_dsumode,
dbgo_error => dbgo_error,
dbgo_halt => dbgo_halt,
dbgo_pwd => dbgo_pwd,
dbgo_idle => dbgo_idle,
dbgo_ipend => dbgo_ipend,
dbgo_icnt => dbgo_icnt,
disasen => disasen);
end generate;
cyciv : if fabtech = cyclone3 generate
wrp: leon3ft_cycloneiv
generic map (
hindex => hindex,
fabtech => fabtech,
memtech => memtech,
nwindows => nwindows,
dsu => dsu,
fpu => fpu,
v8 => v8,
cp => cp,
mac => mac,
pclow => pclow,
notag => notag,
nwp => nwp,
icen => icen,
irepl => irepl,
isets => isets,
ilinesize => ilinesize,
isetsize => isetsize,
isetlock => isetlock,
dcen => dcen,
drepl => drepl,
dsets => dsets,
dlinesize => dlinesize,
dsetsize => dsetsize,
dsetlock => dsetlock,
dsnoop => dsnoop,
ilram => ilram,
ilramsize => ilramsize,
ilramstart => ilramstart,
dlram => dlram,
dlramsize => dlramsize,
dlramstart => dlramstart,
mmuen => mmuen,
itlbnum => itlbnum,
dtlbnum => dtlbnum,
tlb_type => tlb_type,
tlb_rep => tlb_rep,
lddel => lddel,
disas => disas,
tbuf => tbuf,
pwd => pwd,
svt => svt,
rstaddr => rstaddr,
smp => smp,
iuft => iuft,
fpft => fpft,
cmft => cmft,
cached => cached,
scantest => scantest,
mmupgsz => mmupgsz,
bp => bp,
npasi => npasi,
pwrpsr => pwrpsr)
port map(
clk => clk,
gclk2 => gclk2,
gfclk2 => gfclk2,
clk2 => clk2,
rstn => rstn,
ahbi_hgrant => ahbi_hgrant,
ahbi_hready => ahbi_hready,
ahbi_hresp => ahbi_hresp,
ahbi_hrdata => ahbi_hrdata,
ahbi_hirq => ahbi_hirq,
ahbi_testen => ahbi_testen,
ahbi_testrst => ahbi_testrst,
ahbi_scanen => ahbi_scanen,
ahbi_testoen => ahbi_testoen,
ahbo_hbusreq => ahbo_hbusreq,
ahbo_hlock => ahbo_hlock,
ahbo_htrans => ahbo_htrans,
ahbo_haddr => ahbo_haddr,
ahbo_hwrite => ahbo_hwrite,
ahbo_hsize => ahbo_hsize,
ahbo_hburst => ahbo_hburst,
ahbo_hprot => ahbo_hprot,
ahbo_hwdata => ahbo_hwdata,
ahbo_hirq => ahbo_hirq,
ahbsi_hsel => ahbsi_hsel,
ahbsi_haddr => ahbsi_haddr,
ahbsi_hwrite => ahbsi_hwrite,
ahbsi_htrans => ahbsi_htrans,
ahbsi_hsize => ahbsi_hsize,
ahbsi_hburst => ahbsi_hburst,
ahbsi_hwdata => ahbsi_hwdata,
ahbsi_hprot => ahbsi_hprot,
ahbsi_hready => ahbsi_hready,
ahbsi_hmaster => ahbsi_hmaster,
ahbsi_hmastlock => ahbsi_hmastlock,
ahbsi_hmbsel => ahbsi_hmbsel,
ahbsi_hirq => ahbsi_hirq,
irqi_irl => irqi_irl,
irqi_rst => irqi_rst,
irqi_run => irqi_run,
irqi_rstvec => irqi_rstvec,
irqi_iact => irqi_iact,
irqi_index => irqi_index,
irqi_hrdrst => irqi_hrdrst,
irqo_intack => irqo_intack,
irqo_irl => irqo_irl,
irqo_pwd => irqo_pwd,
irqo_fpen => irqo_fpen,
irqo_idle => irqo_idle,
dbgi_dsuen => dbgi_dsuen,
dbgi_denable => dbgi_denable,
dbgi_dbreak => dbgi_dbreak,
dbgi_step => dbgi_step,
dbgi_halt => dbgi_halt,
dbgi_reset => dbgi_reset,
dbgi_dwrite => dbgi_dwrite,
dbgi_daddr => dbgi_daddr,
dbgi_ddata => dbgi_ddata,
dbgi_btrapa => dbgi_btrapa,
dbgi_btrape => dbgi_btrape,
dbgi_berror => dbgi_berror,
dbgi_bwatch => dbgi_bwatch,
dbgi_bsoft => dbgi_bsoft,
dbgi_tenable => dbgi_tenable,
dbgi_timer => dbgi_timer,
dbgo_data => dbgo_data,
dbgo_crdy => dbgo_crdy,
dbgo_dsu => dbgo_dsu,
dbgo_dsumode => dbgo_dsumode,
dbgo_error => dbgo_error,
dbgo_halt => dbgo_halt,
dbgo_pwd => dbgo_pwd,
dbgo_idle => dbgo_idle,
dbgo_ipend => dbgo_ipend,
dbgo_icnt => dbgo_icnt,
dbgo_fcnt => dbgo_fcnt,
dbgo_optype => dbgo_optype,
dbgo_bpmiss => dbgo_bpmiss,
dbgo_istat_cmiss => dbgo_istat_cmiss,
dbgo_istat_tmiss => dbgo_istat_tmiss,
dbgo_istat_chold => dbgo_istat_chold,
dbgo_istat_mhold => dbgo_istat_mhold,
dbgo_dstat_cmiss => dbgo_dstat_cmiss,
dbgo_dstat_tmiss => dbgo_dstat_tmiss,
dbgo_dstat_chold => dbgo_dstat_chold,
dbgo_dstat_mhold => dbgo_dstat_mhold,
dbgo_wbhold => dbgo_wbhold,
dbgo_su => dbgo_su,
clken => clken);
end generate;
ahbi_hgrant(0) <= ahbi.hgrant(hindex);
ahbi_hgrant(1 to NAHBMST-1) <= (others => '0');
ahbi_hready <= ahbi.hready;
ahbi_hresp <= ahbi.hresp;
ahbi_hrdata <= ahbi.hrdata(31 downto 0);
ahbi_hirq <= ahbi.hirq;
ahbi_testen <= ahbi.testen;
ahbi_testrst <= ahbi.testrst;
ahbi_scanen <= ahbi.scanen;
ahbi_testoen <= ahbi.testoen;
ahbo.hbusreq <= ahbo_hbusreq;
ahbo.hlock <= ahbo_hlock;
ahbo.htrans <= ahbo_htrans;
ahbo.haddr <= ahbo_haddr;
ahbo.hwrite <= ahbo_hwrite;
ahbo.hsize <= '0' & ahbo_hsize(1 downto 0);
ahbo.hburst <= "00" & ahbo_hburst(0);
ahbo.hprot <= ahbo_hprot;
ahbo.hwdata(31 downto 0) <= ahbo_hwdata;
ahbo.hirq <= (others => '0'); --ahbo_hirq;
ahbsi_hsel <= ahbsi.hsel;
ahbsi_haddr <= ahbsi.haddr;
ahbsi_hwrite <= ahbsi.hwrite;
ahbsi_htrans <= ahbsi.htrans;
ahbsi_hsize <= ahbsi.hsize;
ahbsi_hburst <= ahbsi.hburst;
ahbsi_hwdata <= ahbsi.hwdata(31 downto 0);
ahbsi_hprot <= ahbsi.hprot;
ahbsi_hready <= ahbsi.hready;
ahbsi_hmaster <= ahbsi.hmaster;
ahbsi_hmastlock <= ahbsi.hmastlock;
ahbsi_hmbsel <= ahbsi.hmbsel;
ahbsi_hirq <= ahbsi.hirq;
-- pragma translate_off
assert NAHBSLV=16
report "LEON3 netlist: Only NAHBSLV=16 supported by wrapper"
severity Failure;
-- pragma translate_on
end architecture;
|
package p is
procedure foo(x : in integer; y : out integer);
procedure yah is -- Error
begin
null;
end procedure;
end package;
package body p is
procedure foo(x : in integer; y : out integer) is
variable i : integer;
begin
y := x + 1;
end procedure;
procedure bar(x : in integer; signal y : out integer) is
begin
y <= x + 1;
end procedure;
procedure yam is
begin
return; -- OK
return 5; -- Error
end procedure;
procedure foo_wrap(y : out integer) is
begin
foo(5, y);
end procedure;
procedure has_def(x : in integer; y : in integer := 7) is
begin
end procedure;
procedure calls_has_def is
begin
has_def(5);
end procedure;
procedure bad_def(x : in bit := 6) is
begin
end procedure;
procedure bad_def2(x : in bit := '1'; y : in integer) is
begin
end procedure;
procedure diff_types(x : in integer; y : in string) is
begin
end procedure;
procedure test_named is
begin
diff_types(1, "foo"); -- OK
diff_types(1, y => "bar"); -- OK
diff_types(x => 1, y => "foo"); -- OK
diff_types(y => "la", x => 6); -- OK
diff_types(y => "foo"); -- Error
diff_types(y => "f", 6); -- Error
end procedure;
procedure overload(x : in bit) is
begin
end procedure;
procedure overload(x : in integer) is
begin
end procedure;
procedure test_overload is
begin
overload('1');
overload(1);
end procedure;
procedure test1(x : in integer; y : out integer) is
begin
y := y + 1; -- Error
x := 6;
end procedure;
procedure test2(signal x : in bit) is
begin
-- These are errors according to LRM 93 section 2.1.1.2
assert x'stable;
assert x'quiet;
assert x'transaction = '1';
assert x'delayed(1 ns) = '1';
end procedure;
type int_ptr is access integer;
procedure test3(constant x : inout int_ptr); -- Error
procedure test4(x : in int_ptr); -- Error
procedure test4(x : int_ptr); -- Error
procedure test4(x : out int_ptr); -- OK
procedure test5_a(variable x : integer) is
begin
end procedure;
procedure test5_b(x : integer) is
alias a : integer is x;
begin
test5_a(a);
end procedure;
type int2d is array (natural range <>, natural range <>) of integer;
procedure test6 (
variable a : inout bit_vector;
constant b : in int2d;
constant c : in natural ) is
begin
end procedure;
procedure test6 (
variable a : inout bit_vector;
constant b : in int2d ) is
begin
test6 ( b => b,
c => 1,
a => a );
end procedure;
procedure test7a(x : in bit_vector(1 to 2)) is
begin
end procedure;
procedure test7b is
begin
test7a(x(1) => '0', x(2) => '1');
end procedure;
procedure test8(x : out int_ptr) is
begin
if x /= null then -- Error
end if;
end procedure;
procedure test9(x : out integer) is
begin
x <= 5; -- Error
end procedure;
end package body;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc966.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s03b00x00p04n01i00966pkg is
constant tPLH : TIME := 10 ns;
constant tPHL : TIME := 12 ns;
end c06s03b00x00p04n01i00966pkg;
ENTITY c06s03b00x00p04n01i00966ent IS
END c06s03b00x00p04n01i00966ent;
ARCHITECTURE c06s03b00x00p04n01i00966arch OF c06s03b00x00p04n01i00966ent IS
BEGIN
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert NOT(work.c06s03b00x00p04n01i00966pkg.tPLH = 10 ns and work.c06s03b00x00p04n01i00966pkg.tPHL = 12 ns)
report "***PASSED TEST: c06s03b00x00p04n01i00966"
severity NOTE;
assert (work.c06s03b00x00p04n01i00966pkg.tPLH = 10 ns and work.c06s03b00x00p04n01i00966pkg.tPHL = 12 ns)
report "***FAILED TEST: c06s03b00x00p04n01i00966 - Selected name should be able to be used to denote a named entity whose declaration is contained within a package."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p04n01i00966arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc966.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s03b00x00p04n01i00966pkg is
constant tPLH : TIME := 10 ns;
constant tPHL : TIME := 12 ns;
end c06s03b00x00p04n01i00966pkg;
ENTITY c06s03b00x00p04n01i00966ent IS
END c06s03b00x00p04n01i00966ent;
ARCHITECTURE c06s03b00x00p04n01i00966arch OF c06s03b00x00p04n01i00966ent IS
BEGIN
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert NOT(work.c06s03b00x00p04n01i00966pkg.tPLH = 10 ns and work.c06s03b00x00p04n01i00966pkg.tPHL = 12 ns)
report "***PASSED TEST: c06s03b00x00p04n01i00966"
severity NOTE;
assert (work.c06s03b00x00p04n01i00966pkg.tPLH = 10 ns and work.c06s03b00x00p04n01i00966pkg.tPHL = 12 ns)
report "***FAILED TEST: c06s03b00x00p04n01i00966 - Selected name should be able to be used to denote a named entity whose declaration is contained within a package."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p04n01i00966arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc966.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s03b00x00p04n01i00966pkg is
constant tPLH : TIME := 10 ns;
constant tPHL : TIME := 12 ns;
end c06s03b00x00p04n01i00966pkg;
ENTITY c06s03b00x00p04n01i00966ent IS
END c06s03b00x00p04n01i00966ent;
ARCHITECTURE c06s03b00x00p04n01i00966arch OF c06s03b00x00p04n01i00966ent IS
BEGIN
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert NOT(work.c06s03b00x00p04n01i00966pkg.tPLH = 10 ns and work.c06s03b00x00p04n01i00966pkg.tPHL = 12 ns)
report "***PASSED TEST: c06s03b00x00p04n01i00966"
severity NOTE;
assert (work.c06s03b00x00p04n01i00966pkg.tPLH = 10 ns and work.c06s03b00x00p04n01i00966pkg.tPHL = 12 ns)
report "***FAILED TEST: c06s03b00x00p04n01i00966 - Selected name should be able to be used to denote a named entity whose declaration is contained within a package."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p04n01i00966arch;
|
----------------------------------------------------------------------------------
-- Company: UOM
-- Engineer: Gihan Karunarathne
--
-- Create Date: 11:40:23 08/21/2013
-- Design Name:
-- Module Name: Full_Subtractor - Behavioral
-- Project Name: Tutorial I
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Full_Subtractor is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : in STD_LOGIC;
D : out STD_LOGIC;
B : out STD_LOGIC);
end Full_Subtractor;
architecture Behavioral of Full_Subtractor is
begin
D <= x xor y xor z;
B <= (z and not(x xor y)) or (not x and y) ;
end Behavioral;
|
-- $Id: genlib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: genlib
-- Description: some general purpose components
--
-- Dependencies: -
-- Tool versions: ise 8.1-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-04-02 757 1.1 move cdc_pulse to cdclib
-- 2016-03-25 751 1.0.10 add gray_cnt_6
-- 2012-12-29 466 1.0.9 add led_pulse_stretch
-- 2011-11-09 421 1.0.8 add cdc_pulse
-- 2010-04-17 277 1.0.7 timer: no default for START,DONE,BUSY; drop STOP
-- 2010-04-02 273 1.0.6 add timer
-- 2008-01-20 112 1.0.5 rename clkgen->clkdivce
-- 2007-12-26 106 1.0.4 added gray_cnt_(4|5|n|gen) and gray2bin_gen
-- 2007-12-25 105 1.0.3 RESET:='0' defaults
-- 2007-06-17 58 1.0.2 added debounce_gen
-- 2007-06-16 57 1.0.1 added cnt_array_dram, cnt_array_regs
-- 2007-06-03 45 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package genlib is
component clkdivce is -- generate usec/msec ce pulses
generic (
CDUWIDTH : positive := 6; -- usec clock divider width
USECDIV : positive := 50; -- divider ratio for usec pulse
MSECDIV : positive := 1000); -- divider ratio for msec pulse
port (
CLK : in slbit; -- input clock
CE_USEC : out slbit; -- usec pulse
CE_MSEC : out slbit -- msec pulse
);
end component;
component cnt_array_dram is -- counter array, dram based
generic (
AWIDTH : positive := 4; -- address width
DWIDTH : positive := 16); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- clear counters
CE : in slv(2**AWIDTH-1 downto 0); -- count enables
ADDR : out slv(AWIDTH-1 downto 0); -- counter address
DATA : out slv(DWIDTH-1 downto 0); -- counter data
ACT : out slbit -- active (not reseting)
);
end component;
component cnt_array_regs is -- counter array, register based
generic (
AWIDTH : positive := 4; -- address width
DWIDTH : positive := 16); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- clear counters
CE : in slv(2**AWIDTH-1 downto 0); -- count enables
ADDR : in slv(AWIDTH-1 downto 0); -- address
DATA : out slv(DWIDTH-1 downto 0) -- counter data
);
end component;
component debounce_gen is -- debounce, generic vector
generic (
CWIDTH : positive := 2; -- clock interval counter width
CEDIV : positive := 3; -- clock interval divider
DWIDTH : positive := 8); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_INT : in slbit; -- clock interval enable (usec or msec)
DI : in slv(DWIDTH-1 downto 0); -- data in
DO : out slv(DWIDTH-1 downto 0) -- data out
);
end component;
component gray_cnt_gen is -- gray code counter, generic vector
generic (
DWIDTH : positive := 4); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv(DWIDTH-1 downto 0) -- data out
);
end component;
component gray_cnt_4 is -- 4 bit gray code counter (ROM based)
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv4 -- data out
);
end component;
component gray_cnt_5 is -- 5 bit gray code counter (ROM based)
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv5 -- data out
);
end component;
component gray_cnt_6 is -- 6 bit gray code counter (ROM based)
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv5 -- data out
);
end component;
component gray_cnt_n is -- n bit gray code counter
generic (
DWIDTH : positive := 8); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv(DWIDTH-1 downto 0) -- data out
);
end component;
component gray2bin_gen is -- gray->bin converter, generic vector
generic (
DWIDTH : positive := 4); -- data width
port (
DI : in slv(DWIDTH-1 downto 0); -- gray code input
DO : out slv(DWIDTH-1 downto 0) -- binary code output
);
end component;
component timer is -- retriggerable timer
generic (
TWIDTH : positive := 4; -- timer counter width
RETRIG : boolean := true); -- re-triggerable true/false
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DELAY : in slv(TWIDTH-1 downto 0) := (others=>'1'); -- timer delay
START : in slbit; -- start timer
STOP : in slbit := '0'; -- stop timer
DONE : out slbit; -- mark last delay cycle
BUSY : out slbit -- timer running
);
end component;
component led_pulse_stretch is -- pulse stretcher for leds
port (
CLK : in slbit; -- clock
CE_INT : in slbit; -- pulse time unit clock enable
RESET : in slbit := '0'; -- reset
DIN : in slbit; -- data in
POUT : out slbit -- pulse out
);
end component;
end package genlib;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity valid is
generic
(
clock_speed0: std_logic; -- $SOL:0:0$
clock_speed1: std_logic := '0'; -- $SOL:1:0$
clock_g_speed2: natural; -- $SOL:2:0$
clock_g_speed3: natural := 3; -- $SOL:3:0$
i_g_g_param : std_logic -- $SOL:4:0$
);
end;
architecture RTL of valid is
begin
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc396.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p06n02i00396ent IS
END c03s02b01x01p06n02i00396ent;
ARCHITECTURE c03s02b01x01p06n02i00396arch OF c03s02b01x01p06n02i00396ent IS
type I1 is range 1 to 1;
type A1 is array (I1 range <>) of BOOLEAN;
type A2 is array (I1'(1) to I1'(1)) of A1; -- Failure_here
-- ERROR - SEMANTIC ERROR: ARRAY ELEMENT CANNOT BE AN UNCONSTRAINED ARRAY
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p06n02i00396 - Array element cannot be an unconstrained array."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p06n02i00396arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc396.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p06n02i00396ent IS
END c03s02b01x01p06n02i00396ent;
ARCHITECTURE c03s02b01x01p06n02i00396arch OF c03s02b01x01p06n02i00396ent IS
type I1 is range 1 to 1;
type A1 is array (I1 range <>) of BOOLEAN;
type A2 is array (I1'(1) to I1'(1)) of A1; -- Failure_here
-- ERROR - SEMANTIC ERROR: ARRAY ELEMENT CANNOT BE AN UNCONSTRAINED ARRAY
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p06n02i00396 - Array element cannot be an unconstrained array."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p06n02i00396arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc396.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p06n02i00396ent IS
END c03s02b01x01p06n02i00396ent;
ARCHITECTURE c03s02b01x01p06n02i00396arch OF c03s02b01x01p06n02i00396ent IS
type I1 is range 1 to 1;
type A1 is array (I1 range <>) of BOOLEAN;
type A2 is array (I1'(1) to I1'(1)) of A1; -- Failure_here
-- ERROR - SEMANTIC ERROR: ARRAY ELEMENT CANNOT BE AN UNCONSTRAINED ARRAY
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p06n02i00396 - Array element cannot be an unconstrained array."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p06n02i00396arch;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity spi_sreg is
generic (
size_g : integer := 8
);
port (
clk : in std_logic;
rst : in std_logic;
--control signals
shift : in std_logic; --shift left
load : in std_logic; --load parallel
--data signals
din : in std_logic_vector(size_g-1 downto 0); --parallel data in (latched)
dout : out std_logic_vector(size_g-1 downto 0); --parallel data out
sin : in std_logic; --serial data in (to lsb)
sout : out std_logic --serial data out (from msb)
);
end spi_sreg;
architecture rtl of spi_sreg is
signal shiftReg : std_logic_vector(size_g-1 downto 0);
begin
theShiftRegister : process(clk, rst)
begin
if rst = '1' then
shiftReg <= (others => '0');
elsif clk = '1' and clk'event then
if shift = '1' then
shiftReg <= shiftReg(size_g-2 downto 0) & sin;
elsif load = '1' then
shiftReg <= din;
end if;
end if;
end process;
dout <= shiftReg;
sout <= shiftReg(size_g-1);
end rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity spi_sreg is
generic (
size_g : integer := 8
);
port (
clk : in std_logic;
rst : in std_logic;
--control signals
shift : in std_logic; --shift left
load : in std_logic; --load parallel
--data signals
din : in std_logic_vector(size_g-1 downto 0); --parallel data in (latched)
dout : out std_logic_vector(size_g-1 downto 0); --parallel data out
sin : in std_logic; --serial data in (to lsb)
sout : out std_logic --serial data out (from msb)
);
end spi_sreg;
architecture rtl of spi_sreg is
signal shiftReg : std_logic_vector(size_g-1 downto 0);
begin
theShiftRegister : process(clk, rst)
begin
if rst = '1' then
shiftReg <= (others => '0');
elsif clk = '1' and clk'event then
if shift = '1' then
shiftReg <= shiftReg(size_g-2 downto 0) & sin;
elsif load = '1' then
shiftReg <= din;
end if;
end if;
end process;
dout <= shiftReg;
sout <= shiftReg(size_g-1);
end rtl;
|
entity clock_Generator is
port (
Clock : out bit
);
end entity;
entity clock_Monitor is
port (
Clock : in bit
);
end entity;
package clock is
end package;
library Clock;
use Clock.clock.all;
entity test is
end entity;
architecture tb of test is
signal Clock : bit;
begin
gen: entity Clock.clock_Generator
port map (
Clock => Clock
);
mon: entity Clock.clock_Monitor
port map (
Clock => Clock
);
end architecture;
|
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when input = "0100" and input = "1100" else
my_sig4 when input = "0010" else
'0';
my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when a = "0000" and func1(345) or
b = "1000" and func2(567) and
c = "00" else
sig1 when a = "1000" and func2(560) and
b = "0010" else
'0';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
-- Testing no code after assignment
my_signal <=
'1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
my_signal <=
(others => '0') when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
end architecture rtl;
|
---------------------------------------------------------
-- JAM CPU core
-- Simple 32bit RISC CPU
--
-- Copyright © 2002:
-- Anders Lindström, Johan E. Thelin, Michael Nordseth
---------------------------------------------------------
-- This is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Library General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
library IEEE;
library work;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned.conv_integer;
entity CPU is
port(
--clock and reset
clk, reset : in std_logic;
--in and out ports
inport : in std_logic_vector(31 downto 0);
outport : out std_logic_vector(31 downto 0);
--IO interface
synctrap : in std_logic;
put : out std_logic;
curpsw11_31 : out std_logic_vector(31 downto 11);
curpsw0_7 : out std_logic_vector(7 downto 0);
newpsw11_31 : in std_logic_vector(31 downto 11);
newpsw0_7 : in std_logic_vector(7 downto 0);
--IM
im_cs : out std_logic_vector(7 downto 0);
im_oe : out std_logic;
im_wri : out std_logic;
im_adr : out std_logic_vector( 16 downto 0 );
im_dat : inout std_logic_vector( 63 downto 0 );
--DM
dm_cs : out std_logic_vector(7 downto 0);
dm_oe : out std_logic;
dm_wri : out std_logic;
dm_adr : out std_logic_vector( 16 downto 0 );
dm_dat : inout std_logic_vector( 63 downto 0 ));
end;
architecture rev1 of CPU is
--The location of the traphandler
constant trap_vector : std_logic_vector(31 downto 0) := (others => '0');
--PC is reset to this value on reset
constant start_vector : std_logic_vector(31 downto 0) := (others => '0');
---------------------------------------------------
-- Pipelineregisters declarative part
--
-- foo_reg - signals out from pipelineregister
-- foo_in - signals to be clocked into the reg
-- foo_reset - output zeros next tick
-- foo_hold - hold signal out next tick
---------------------------------------------------
-- IF/ID
type ifid_struct is record
iword : std_logic_vector(31 downto 0); --instruction word
pc : std_logic_vector(31 downto 0); --pc for this instruction
cm_hw_int : std_logic; --hw interupt
end record;
signal ifid_reg : ifid_struct;
signal ifid_in : ifid_struct;
signal ifid_reset : std_logic;
signal ifid_hold : std_logic;
-- ID/EX
type idex_struct is record
-- data
pc : std_logic_vector(31 downto 0);
areg : std_logic_vector(31 downto 0);
breg : std_logic_vector(31 downto 0);
imm : std_logic_vector(31 downto 0);
-- reg index
src1 : std_logic_vector(4 downto 0);
src2 : std_logic_vector(4 downto 0);
dest : std_logic_vector(4 downto 0);
-- control signals to EX stage
cex_asel : std_logic;
cex_bsel : std_logic;
cex_ressel : std_logic;
cex_regsel : std_logic_vector(1 downto 0);
cex_aluop : std_logic_vector(2 downto 0);
cex_domult : std_logic;
cex_multop : std_logic;
cex_invin2 : std_logic;
cex_valid_reg : std_logic;
cex_valid_res : std_logic;
cex_psw_enable: std_logic;
cex_put : std_logic;
-- control signals to MEM stage
cm_valid_mem : std_logic;
cm_valid_reg : std_logic;
cm_write : std_logic;
cm_read : std_logic;
cm_hw_int : std_logic;
cm_bad_op : std_logic;
cm_sw_int : std_logic;
cm_jump : std_logic;
-- control signals to WB stage
cwb_sel : std_logic;
cwb_enable : std_logic;
cwb_valid : std_logic;
cwb_branch : std_logic;
end record;
signal idex_reg : idex_struct;
signal idex_in : idex_struct;
signal idex_reset : std_logic;
signal idex_hold : std_logic;
-- EX/MEM
type exmem_struct is record
pc : std_logic_vector(31 downto 0);
res : std_logic_vector(31 downto 0);
reg : std_logic_vector(31 downto 0);
dest : std_logic_vector(4 downto 0);
cm_write : std_logic;
cm_read : std_logic;
cm_valid_mem : std_logic;
cm_valid_reg : std_logic;
cm_hw_int : std_logic;
cm_bad_op : std_logic;
cm_sw_int : std_logic;
cm_jump : std_logic;
cm_ovf : std_logic;
cwb_sel : std_logic;
cwb_enable : std_logic;
cwb_valid : std_logic;
cwb_branch : std_logic;
end record;
signal exmem_reg : exmem_struct;
signal exmem_in : exmem_struct;
signal exmem_reset : std_logic;
signal exmem_hold : std_logic;
-- MEM/WB
type memwb_struct is record
mem : std_logic_vector(31 downto 0);
reg : std_logic_vector(31 downto 0);
dest : std_logic_vector(4 downto 0);
cwb_sel : std_logic;
cwb_enable : std_logic;
cwb_valid : std_logic;
cwb_branch : std_logic;
end record;
signal memwb_reg : memwb_struct;
signal memwb_in : memwb_struct;
signal memwb_reset : std_logic;
signal memwb_hold : std_logic;
---------------------------------------------------
-- IF declarative part
---------------------------------------------------
-- memory access unit (IM)
component MAU
port(
-- Signalas from/to CPU/CONTROLL
CLK : in std_logic;
CTRL_R : in std_logic; -- Read Mem
CTRL_W : in std_logic; -- Write Mem
RESET : in std_logic;
STALL : out std_logic; -- Used to stall one cycle on write
IN_ADDR : in std_logic_vector(31 downto 0); -- Adress Buss from CPU
IN_DATA : in std_logic_vector(31 downto 0); -- Data Buss from CPU
OUT_DATA : out std_logic_vector(31 downto 0); -- Data Buss to CPU
-- Signals from/to MEM
DM_CS : out std_logic_vector(7 downto 0); -- Chip Select (active low)
DM_OE : out std_logic; -- Output Enable (active low)
DM_WRITE : out std_logic; -- Write Data, Mem (data -> HighZ) (active low)
DM_ADDR : out std_logic_vector(16 downto 0); -- Address Buss to mem
DM_DATA : inout std_logic_vector(63 downto 0) -- Mem Data Buss (Bidirectional)
);
end component;
for if_mau: MAU use entity work.MAU;
signal if_pc : std_logic_vector(31 downto 0); -- current PC register
signal if_pc_word : std_logic_vector(31 downto 0);
signal if_int : std_logic;
signal if_iword : std_logic_vector(31 downto 0);
signal if_zero : std_logic;
signal if_one : std_logic;
signal if_zero32 : std_logic_vector(31 downto 0);
---------------------------------------------------
-- ID declarative part
---------------------------------------------------
-- Register file
component regs
port (
ra, rb, rw : in std_logic_vector(4 downto 0);
value_w : in std_logic_vector(31 downto 0);
clk : in std_logic;
value_a, value_b : out std_logic_vector(31 downto 0) );
end component;
-- The format handler
component imm_ext
port (
mode : in std_logic_vector(1 downto 0);
op5 : in std_logic;
imm : in std_logic_vector(15 downto 0);
r : out std_logic_vector(31 downto 0) );
end component;
-- Control unit
component control
port (
op : in std_logic_vector (5 downto 0); -- The op code
ex_asel : out std_logic; -- (ra,psw)
ex_bsel : out std_logic; -- (rb,imm)
ex_ressel : out std_logic; -- (res,sign)
ex_regsel : out std_logic_vector (1 downto 0); -- (psw,pc,b,in)
ex_aluop : out std_logic_vector (2 downto 0); -- (nop,add,sub,op,and,xor,shz,shs)
ex_domult : out std_logic; -- (off,on)
ex_multop : out std_logic; -- (low,high)
ex_invin2 : out std_logic; -- (off,on)
ex_valid_reg : out std_logic; -- valid data
ex_valid_res : out std_logic; -- valid data
ex_psw_enable: out std_logic; -- write to psw?
ex_put : out std_logic; -- write to outport
m_read : out std_logic; -- DM read
m_write : out std_logic; -- DM write
m_valid_reg : out std_logic; -- valid data
m_valid_mem : out std_logic; -- valid data
wb_sel : out std_logic; -- (mem,reg)
wb_enable : out std_logic; -- (off,on)
id_bsel : out std_logic; -- '1' if rd is used as r2
id_beq : out std_logic; -- '1' if the op is a branch
id_bne : out std_logic; -- '1' if the op is a branch n.eq.
illegal_op : out std_logic; -- '1' when illegal op
trap : out std_logic; -- trap
jump : out std_logic); -- jump instr.
end component;
for id_regs: regs use entity work.regs(rev1);
for id_ix: imm_ext use entity work.imm_ext(rev1);
for id_ctrl: control use entity work.control(rev1);
signal id_rb : std_logic_vector(4 downto 0);
signal id_branchadr : std_logic_vector(31 downto 0);
signal id_a : std_logic_vector(31 downto 0);
signal id_b : std_logic_vector(31 downto 0);
signal id_stalling : std_logic;
signal cid_branch : std_logic; -- branch?
signal cid_cmp : std_logic; -- High when a == b
signal cid_bsel : std_logic;
signal cid_beq : std_logic;
signal cid_bne : std_logic;
-- Valid signals from control
signal cex_valid_reg : std_logic;
signal cex_valid_res : std_logic;
signal cm_valid_mem : std_logic;
signal cm_valid_reg : std_logic;
---------------------------------------------------
-- EX declarative part
---------------------------------------------------
-- integer unit (ALU + mult)
component IU
port(
a_in, b_in : in std_logic_vector(31 downto 0); -- IU input
do_mult : in std_logic; -- Do multicycle mult?
mult_op : in std_logic; -- Return [0=LSW] or [1=MSW) of mult result
alu_op : in std_logic_vector(2 downto 0); -- ALU op
inv_in2 : in std_logic; -- Invert operator in2 in ALU
clk : in std_logic; -- Global clock
reset : in std_logic; -- Global reset
ovf : out std_logic; -- Overflow
result : out std_logic_vector(31 downto 0); -- IU result
mc : out std_logic); -- Goes high during the last cycle of a multicycle op
end component;
for ex_iu: IU use entity work.IU(rev1);
signal ex_ain : std_logic_vector(31 downto 0);
signal ex_bin : std_logic_vector(31 downto 0);
signal ex_breg : std_logic_vector(31 downto 0);
signal ex_psw : std_logic_vector(31 downto 0);
signal ex_result : std_logic_vector(31 downto 0);
signal ex_wb_data_buf : std_logic_vector(31 downto 0);
signal ex_wb_dest_buf : std_logic_vector(4 downto 0);
signal ex_wb_valid_buf : std_logic;
signal ex_stalling : std_logic;
signal ex_lw_hazard : std_logic;
signal ex_mc_finished : std_logic;
signal ex_do_mult : std_logic;
---------------------------------------------------
-- MEM declarative part
---------------------------------------------------
-- memory access unit (DM)
for mem_mau: MAU use entity work.MAU;
signal mem_stalling : std_logic;
signal mem_clear : std_logic;
signal mem_res : std_logic_vector(31 downto 0);
signal mem_data : std_logic_vector(31 downto 0);
signal mem_adr_word : std_logic_vector(31 downto 0);
signal mem_jump_trap : std_logic;
---------------------------------------------------
-- WB declarative part
---------------------------------------------------
signal wb_rw : std_logic_vector(4 downto 0);
signal wb_value : std_logic_vector (31 downto 0);
begin
---------------------------------------------------
-- Pipeline registers
---------------------------------------------------
--IF/ID
process(clk)
begin
if clk'event and clk='1' then
if ( (ifid_reset = '1') or (reset = '1') ) then
ifid_reg <= ((others => '0'), (others => '0'), '0');
elsif ifid_hold /= '1' then
ifid_reg <= ifid_in;
end if;
end if;
end process;
-- Stall/nop logic
ifid_hold <=
'1' when ( (id_stalling = '1') or (ex_stalling = '1') or (mem_stalling = '1') ) else
'0';
ifid_reset <= mem_clear;
--ID/EX
process(clk)
begin
if clk'event and clk='1' then
if ( (idex_reset = '1') or (reset = '1') ) then
idex_reg <= ((others => '0'),(others => '0'),(others => '0'),(others => '0'),(others => '0'),(others => '0'),(others => '0'),'0','0','0',(others => '0'),(others => '0'),'0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0');
elsif idex_hold /= '1' then
idex_reg <= idex_in;
end if;
end if;
end process;
-- Stall/nop logic
idex_hold <=
'1' when ( (ex_stalling = '1') or (mem_stalling = '1') ) else
'0';
idex_reset <=
'1' when ( ( (id_stalling = '1') and (idex_hold = '0') ) or (mem_clear = '1') ) else
'0';
--EX/MEM
process(clk)
begin
if clk'event and clk='1' then
if ( (exmem_reset = '1') or (reset = '1') ) then
exmem_reg <= ((others => '0'),(others => '0'),(others => '0'),(others => '0'),'0','0','0','0','0','0','0','0','0','0','0','0','0');
elsif exmem_hold /= '1' then
exmem_reg <= exmem_in;
end if;
end if;
end process;
-- Stall/nop logic
exmem_hold <=
'1' when (mem_stalling = '1') else
'0';
exmem_reset <=
'1' when mem_clear = '1' else
'1' when ( (ex_stalling = '1') and (mem_stalling = '0') ) else
'0';
--MEM/WB latch
process(clk)
begin
if clk'event and clk='1' then
if ( (memwb_reset = '1') or (reset = '1') ) then
memwb_reg <= ((others => '0'),(others => '0'),(others => '0'),'0','0','0','0');
elsif memwb_hold /= '1' then
memwb_reg <= memwb_in;
end if;
end if;
end process;
-- Stall/nop logic
memwb_hold <=
'1' when (mem_stalling = '1') else
'0';
memwb_reset <= '0';
---------------------------------------------------
-- IF Stage
---------------------------------------------------
-- IM is read only
if_zero <= '0';
if_one <= '1';
if_zero32 <= (others => '0');
if_pc_word <= "00" & if_pc(31 downto 2);
-- [PORTMAP] IM
if_mau : MAU port map(
CLK => clk,
RESET => reset,
CTRL_W => if_zero,
CTRL_R => if_one,
--STALL =>
IN_ADDR => if_pc_word,
IN_DATA => if_zero32,
OUT_DATA => if_iword,
DM_CS => im_cs,
DM_OE => im_oe,
DM_WRITE => im_wri,
DM_ADDR => im_adr,
DM_DATA => im_dat
);
ifid_in.pc <= if_pc;
--ifid_in.iword <= rom_image(conv_integer(if_pc(31 downto 2))); --fetch instruction from ROM (in simcpu nowdays)
ifid_in.iword <=
if_iword when if_int = '0' else
"10100100000000000000000000000000"; --inject trap
-- HW interupt injector
ifid_in.cm_hw_int <= if_int;
-- handle PC
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
if_pc <= start_vector;
--Update PC
elsif ifid_hold = '0' then
if exmem_reg.cm_jump = '1' then
if_pc <= exmem_reg.res;
elsif mem_jump_trap = '1' then
if_pc <= trap_vector;
elsif cid_branch = '1' then
if_pc <= id_branchadr;
else
if_pc <= if_pc + "100"; -- pc+=4
end if;
end if;
end if;
end process;
-- Interupt injector
process(clk)
begin
if clk'event and clk='1' then
if ( (reset = '1') or (exmem_reg.cm_hw_int = '1') ) then
if_int <= '0';
elsif ( (synctrap='1') or (if_int = '1') ) then
if_int <= '1';
end if;
end if;
end process;
---------------------------------------------------
-- ID Stage
---------------------------------------------------
-- Some stupid instructions use dest for regb, this handles them!
-- We can let control handle this or do it ourself.
id_rb <=
--ifid_reg.iword(25 downto 21) when cid_bsel = '0' else
ifid_reg.iword(25 downto 21) when (ifid_reg.iword(31 downto 26) = "100111") else --SW
ifid_reg.iword(25 downto 21) when (ifid_reg.iword(31 downto 26) = "010111") else --BNE
ifid_reg.iword(25 downto 21) when (ifid_reg.iword(31 downto 26) = "010011") else --BEQ
ifid_reg.iword(15 downto 11);
-- Destination field in the iword
idex_in.dest <= ifid_reg.iword(25 downto 21);
-- [PORTMAP] The register bank
id_regs : regs port map(
ra => ifid_reg.iword(20 downto 16),
rb => id_rb,
rw => wb_rw,
value_w => wb_value,
clk => clk,
value_a => idex_in.areg,
value_b => idex_in.breg);
-- Send sourceregs. to idex reg (used for forwarding logic)
idex_in.src1 <= ifid_reg.iword(20 downto 16);
idex_in.src2 <= id_rb;
-- [PORTMAP] The immediate extender unit, does magic to the imm field
id_ix : imm_ext port map(
mode => ifid_reg.iword(27 downto 26),
op5 => ifid_reg.iword(31),
imm => ifid_reg.iword(15 downto 0),
r => idex_in.imm);
-- Forwarding logic for branch compare
id_a <=
--exmem_in.res when ( (idex_in.src1 = idex_reg.dest) and (idex_reg.cex_valid_res = '1') ) else -- critical path
--exmem_in.reg when ( (idex_in.src1 = idex_reg.dest) and (idex_reg.cex_valid_reg = '1') ) else -- we stall instead
exmem_reg.res when ( (idex_in.src1 = exmem_reg.dest) and (exmem_reg.cm_valid_mem = '1') ) else
exmem_reg.reg when ( (idex_in.src1 = exmem_reg.dest) and (exmem_reg.cm_valid_reg = '1') ) else
idex_in.areg;
id_b <=
--exmem_in.res when ( (idex_in.src2 = idex_reg.dest) and (idex_reg.cex_valid_res = '1') ) else
--exmem_in.reg when ( (idex_in.src2 = idex_reg.dest) and (idex_reg.cex_valid_reg = '1') ) else
exmem_reg.res when ( (idex_in.src2 = exmem_reg.dest) and (exmem_reg.cm_valid_mem = '1') ) else
exmem_reg.reg when ( (idex_in.src2 = exmem_reg.dest) and (exmem_reg.cm_valid_reg = '1') ) else
idex_in.breg;
--Stall when we need data from EX in branch logic
id_stalling <=
'0' when ( (cid_bne = '0') and (cid_beq = '0') ) else
'1' when ( (idex_in.src1 = idex_reg.dest) and ( (idex_reg.cex_valid_res = '1') or (idex_reg.cex_valid_reg = '1') ) ) else
'1' when ( (idex_in.src2 = idex_reg.dest) and ( (idex_reg.cex_valid_res = '1') or (idex_reg.cex_valid_reg = '1') ) ) else
'0';
-- The branch logic
cid_cmp <=
'1' when (id_a = id_b) else
'0';
cid_branch <=
'1' when ( (cid_cmp = '0') and (cid_bne = '1') ) else
'1' when ( (cid_cmp = '1') and (cid_beq = '1') ) else
'0';
-- Save branch flag for branch delay slot detection by trap handler
idex_in.cwb_branch <= cid_branch;
-- Jumpdestination calc.
id_branchadr <= idex_in.imm + ifid_reg.pc;
-- [PORTMAP] The control unit
id_ctrl : control port map(
op => ifid_reg.iword(31 downto 26),
ex_asel => idex_in.cex_asel,
ex_bsel => idex_in.cex_bsel,
ex_ressel => idex_in.cex_ressel,
ex_regsel => idex_in.cex_regsel,
ex_aluop => idex_in.cex_aluop,
ex_domult => idex_in.cex_domult,
ex_multop => idex_in.cex_multop,
ex_invin2 => idex_in.cex_invin2,
ex_valid_res => cex_valid_res,
ex_valid_reg => cex_valid_reg,
ex_psw_enable => idex_in.cex_psw_enable,
ex_put => idex_in.cex_put,
m_write => idex_in.cm_write,
m_read => idex_in.cm_read,
m_valid_mem => cm_valid_mem,
m_valid_reg => cm_valid_reg,
wb_sel => idex_in.cwb_sel,
wb_enable => idex_in.cwb_enable,
id_bsel => cid_bsel,
id_beq => cid_beq,
id_bne => cid_bne,
illegal_op => idex_in.cm_bad_op,
trap => idex_in.cm_sw_int,
jump => idex_in.cm_jump
);
-- The valid data control signals
idex_in.cex_valid_reg <=
'0' when ifid_reg.iword(25 downto 21) = "00000" else
cex_valid_reg;
idex_in.cex_valid_res <=
'0' when ifid_reg.iword(25 downto 21) = "00000" else
cex_valid_res;
idex_in.cm_valid_mem <=
'0' when ifid_reg.iword(25 downto 21) = "00000" else
cm_valid_mem;
idex_in.cm_valid_reg <=
'0' when ifid_reg.iword(25 downto 21) = "00000" else
cm_valid_reg;
idex_in.cwb_valid <=
'0' when idex_in.dest = "00000" else --R0
'0' when idex_in.cwb_enable = '0' else --No valid data
'1';
-- copy to next pipeline stage
idex_in.pc <= ifid_reg.pc;
idex_in.cm_hw_int <= ifid_reg.cm_hw_int;
---------------------------------------------------
-- EX Stage
---------------------------------------------------
-- [PORTMAP] Integer unit
ex_iu : IU port map(
a_in => ex_ain,
b_in => ex_bin,
do_mult => ex_do_mult,
mult_op => idex_reg.cex_multop,
alu_op => idex_reg.cex_aluop,
inv_in2 => idex_reg.cex_invin2,
clk => clk,
reset => reset,
ovf => exmem_in.cm_ovf,
result => ex_result,
mc => ex_mc_finished
);
-- LW hazard (we need the result from a LW)?
ex_lw_hazard <=
'0' when exmem_reg.cm_read = '0' else
'1' when ((exmem_reg.dest = idex_reg.src1) or (exmem_reg.dest = idex_reg.src2)) else
'0';
-- EX stall logic
ex_stalling <=
--stall on mult
'0' when ex_mc_finished = '1' else
'1' when idex_reg.cex_domult = '1' else
-- stall on LW (and we need the result)
'1' when ex_lw_hazard = '1' else
'0';
-- don't start mult on LW stall
ex_do_mult <=
'0' when ex_lw_hazard = '1' else
idex_reg.cex_domult;
-- copy signals to next pipeline stage
exmem_in.pc <= idex_reg.pc;
exmem_in.dest <= idex_reg.dest;
exmem_in.cm_read <= idex_reg.cm_read;
exmem_in.cm_write <= idex_reg.cm_write;
exmem_in.cm_valid_mem <= idex_reg.cm_valid_mem;
exmem_in.cm_valid_reg <= idex_reg.cm_valid_reg;
exmem_in.cm_hw_int <= idex_reg.cm_hw_int;
exmem_in.cm_bad_op <= idex_reg.cm_bad_op;
exmem_in.cm_sw_int <= idex_reg.cm_sw_int;
exmem_in.cm_jump <= idex_reg.cm_jump;
exmem_in.cwb_sel <= idex_reg.cwb_sel;
exmem_in.cwb_enable <= idex_reg.cwb_enable;
exmem_in.cwb_valid <= idex_reg.cwb_valid;
exmem_in.cwb_branch <= idex_reg.cwb_branch;
-- outport pins on CPU
outport <= idex_reg.areg;
put <= idex_reg.cex_put;
-- A input to IU
ex_ain <=
ex_psw when idex_reg.cex_asel = '1' else
exmem_reg.res when ( (idex_reg.src1 = exmem_reg.dest) and (exmem_reg.cm_valid_mem = '1') ) else -- Forwarding from mem to ex
exmem_reg.reg when ( (idex_reg.src1 = exmem_reg.dest) and (exmem_reg.cm_valid_reg = '1') ) else -- Forwarding from mem to ex
wb_value when ( (idex_reg.src1 = memwb_reg.dest) and (memwb_reg.cwb_valid = '1') ) else -- Forwarding from wb to ex
ex_wb_data_buf when ( (idex_reg.src1 = ex_wb_dest_buf) and (ex_wb_valid_buf ='1') ) else
idex_reg.areg;
-- Forwarding logic for breg data
ex_breg <=
exmem_reg.res when ( (idex_reg.src2 = exmem_reg.dest) and (exmem_reg.cm_valid_mem = '1') ) else -- Forwarding from mem to ex
exmem_reg.reg when ( (idex_reg.src2 = exmem_reg.dest) and (exmem_reg.cm_valid_reg = '1') ) else -- Forwarding from mem to ex
wb_value when ( (idex_reg.src2 = memwb_reg.dest) and (memwb_reg.cwb_valid = '1') ) else -- Forwarding from wb to ex
ex_wb_data_buf when ( (idex_reg.src2 = ex_wb_dest_buf) and (ex_wb_valid_buf ='1') ) else
idex_reg.breg;
-- B input on IU
ex_bin <=
idex_reg.imm when idex_reg.cex_bsel = '1' else
ex_breg;
-- Mux after IU
exmem_in.res <=
(0 => ex_result(31), others => '0') when idex_reg.cex_ressel = '1' else
ex_result;
-- Data for reg
exmem_in.reg <=
ex_psw when idex_reg.cex_regsel = "00" else
idex_reg.pc when idex_reg.cex_regsel = "01" else
ex_breg when idex_reg.cex_regsel = "10" else
inport;
-- Mirror PSW to outside world
curpsw11_31 <= ex_psw(31 downto 11);
curpsw0_7 <= ex_psw(7 downto 0);
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
-- reset PSW
ex_psw <= "11111111111111111111111100000000";
ex_wb_valid_buf <= '0';
else
--We must buffer the WB stage data on LW hazards
if ex_lw_hazard = '1' then
ex_wb_valid_buf <= memwb_reg.cwb_valid;
ex_wb_dest_buf <= wb_rw;
ex_wb_data_buf <= wb_value;
else
ex_wb_valid_buf <= '0';
end if;
--Update psw
if exmem_reg.cm_bad_op = '1' then
ex_psw(9) <= '1';
elsif exmem_reg.cm_ovf = '1' then
ex_psw(8) <= '1';
elsif idex_reg.cex_psw_enable = '1' then
ex_psw <= ex_result;
end if;
if ifid_reg.cm_hw_int = '1' then
ex_psw(31 downto 11) <= newpsw11_31;
ex_psw(7 downto 0) <= newpsw0_7;
end if;
end if;
end if;
end process;
---------------------------------------------------
-- MEM Stage
---------------------------------------------------
mem_adr_word <= "00" & exmem_reg.res(31 downto 2);
--[PORTMAP] DM
mem_mau : MAU port map(
CLK => clk,
RESET => reset,
CTRL_W => exmem_reg.cm_write,
CTRL_R => exmem_reg.cm_read,
STALL => mem_stalling,
IN_ADDR => mem_adr_word,
IN_DATA => mem_data, -- To forw. mux
OUT_DATA => mem_res,
DM_CS => dm_cs,
DM_OE => dm_oe,
DM_WRITE => dm_wri,
DM_ADDR => dm_adr,
DM_DATA => dm_dat
);
-- copy signals and regs to next pipe stage
memwb_in.cwb_enable <= exmem_reg.cwb_enable;
memwb_in.cwb_valid <= exmem_reg.cwb_valid;
memwb_in.cwb_branch <= exmem_reg.cwb_branch;
-- Forwarding from wb to mem only when SW.
mem_data <=
wb_value when ( (exmem_reg.cm_write = '1') and (exmem_reg.dest = memwb_reg.dest) and (memwb_reg.cwb_valid = '1') ) else
exmem_reg.reg;
-- Mux, selecting mem-result or IU-result.
memwb_in.mem <=
mem_res when exmem_reg.cm_read = '1' else
exmem_reg.res;
-- Jump to trap handler?
mem_jump_trap <=
'0' when memwb_reg.cwb_branch = '1' else --this is a delay slot (ignore trap)
'1' when exmem_reg.cm_hw_int = '1' else
'1' when exmem_reg.cm_bad_op = '1' else
'1' when exmem_reg.cm_sw_int = '1' else
'1' when exmem_reg.cm_ovf = '1' else
'0';
-- Make WB write PC to R31 on trap (else copy normal values)
memwb_in.dest <=
"11111" when mem_jump_trap = '1' else
exmem_reg.dest;
memwb_in.cwb_sel <=
'1' when mem_jump_trap = '1' else
exmem_reg.cwb_sel;
memwb_in.reg <=
exmem_reg.pc when mem_jump_trap = '1' else
exmem_reg.reg;
-- Clear IF/ID, ID/EX and EX/MEM
mem_clear <=
'1' when ( (exmem_reg.cm_jump = '1') or (mem_jump_trap = '1') ) else
'0';
---------------------------------------------------
-- WB Stage
---------------------------------------------------
-- Write what to regs?
wb_value <=
memwb_reg.mem when memwb_reg.cwb_sel = '0' else
memwb_reg.reg;
-- Write or not to write, that is the question...
wb_rw <=
"00000" when memwb_reg.cwb_enable = '0' else
memwb_reg.dest;
end;
|
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CountEvents is
port(
Entrada: in std_logic;
Reset: in std_logic;
Reset_cont: in std_logic;
Output: out std_logic_vector (31 downto 0));
end CountEvents;
architecture Behavioral of CountEvents is
signal temp: std_logic_vector (31 downto 0);
begin
process(Reset, Entrada, Reset_cont)
begin
if Reset_cont='1' then
temp <= "00000000000000000000000000000000";
elsif Reset='1' then
temp <= "00000000000000000000000000000000";
elsif(Entrada'event and Entrada='1') then
if temp="11111111111111111111111111111111" then
temp<="00000000000000000000000000000000";
else
temp <= temp + 1;
end if;
end if;
end process;
Output <= temp;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CountEvents is
port(
Entrada: in std_logic;
Reset: in std_logic;
Reset_cont: in std_logic;
Output: out std_logic_vector (31 downto 0));
end CountEvents;
architecture Behavioral of CountEvents is
signal temp: std_logic_vector (31 downto 0);
begin
process(Reset, Entrada, Reset_cont)
begin
if Reset_cont='1' then
temp <= "00000000000000000000000000000000";
elsif Reset='1' then
temp <= "00000000000000000000000000000000";
elsif(Entrada'event and Entrada='1') then
if temp="11111111111111111111111111111111" then
temp<="00000000000000000000000000000000";
else
temp <= temp + 1;
end if;
end if;
end process;
Output <= temp;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity AtomGodilVideo is
generic (
CImplGraphicsExt : boolean;
CImplSoftChar : boolean;
CImplSID : boolean;
CImplVGA80x40 : boolean;
CImplHWScrolling : boolean;
CImplMouse : boolean;
CImplUart : boolean;
CImplDoubleVideo : boolean;
MainClockSpeed : integer;
DefaultBaud : integer
);
port (
-- clock_vga is a full speed VGA clock (25MHz ish)
clock_vga : in std_logic;
-- clock_main is the main clock
clock_main : in std_logic;
-- A fixed 32MHz clock for the SID
clock_sid_32MHz : in std_logic;
-- As fast a clock as possible for the SID DAC
clock_sid_dac : in std_logic;
-- Reset signal (active high)
reset : in std_logic;
-- Reset signal to 6847 (active high), not currently used
reset_vid : in std_logic;
-- Main Address / Data Bus signals
din : in std_logic_vector (7 downto 0);
dout : out std_logic_vector (7 downto 0);
addr : in std_logic_vector (12 downto 0);
-- 6847 signals
CSS : in std_logic;
AG : in std_logic;
GM : in std_logic_vector (2 downto 0);
nFS : out std_logic;
-- RAM signals
ram_we : in std_logic;
-- SID signals
reg_cs : in std_logic;
reg_we : in std_logic;
-- SID signals
sid_cs : in std_logic;
sid_we : in std_logic;
sid_audio : out std_logic;
sid_audio_d : out std_logic_vector(17 downto 0);
-- PS/2 Mouse signals
PS2_CLK : inout std_logic;
PS2_DATA : inout std_logic;
-- UART signals
uart_cs : in std_logic;
uart_we : in std_logic;
uart_RxD : in std_logic;
uart_TxD : out std_logic;
uart_escape : out std_logic;
uart_break : out std_logic;
-- VGA Signals
final_red : out std_logic;
final_green1 : out std_logic;
final_green0 : out std_logic;
final_blue : out std_logic;
final_vsync : out std_logic;
final_hsync : out std_logic;
final_blank : out std_logic;
-- Default CharSet
charSet : in std_logic;
-- Uart interrupt
uart_irq_n : out std_logic
);
end AtomGodilVideo;
architecture BEHAVIORAL of AtomGodilVideo is
constant MAJOR_VERSION : std_logic_vector(3 downto 0) := "0001";
constant MINOR_VERSION : std_logic_vector(3 downto 0) := "0100";
-- Set this to 0 if you want dark green/dark orange background on text
-- Set this to 1 if you want black background on text (authentic Atom)
constant BLACK_BACKGND : std_logic := '1';
signal clock_vga_en : std_logic;
-- Internal 1MHz clocks for SID
signal div32 : std_logic_vector (4 downto 0);
signal clock_sid_1MHz : std_logic;
-- VGA colour signals out of mc6847, only top 2 bits are used
signal vga_red : std_logic_vector (7 downto 0);
signal vga_green : std_logic_vector (7 downto 0);
signal vga_blue : std_logic_vector (7 downto 0);
signal vga_vsync : std_logic;
signal vga_hsync : std_logic;
signal vga_blank : std_logic;
signal vga_vblank : std_logic;
signal vga_hblank : std_logic;
-- 8Kx8 Dual port video RAM signals
-- Port A connects to Atom and is read/write
-- Port B connects to MC6847 and is read only
signal douta : std_logic_vector (7 downto 0);
signal addrb : std_logic_vector (12 downto 0);
signal doutb : std_logic_vector (7 downto 0);
-- Masked (by nRST) version of the mode control signals
signal mask : std_logic;
signal gm_masked : std_logic_vector (2 downto 0);
signal ag_masked : std_logic;
signal css_masked : std_logic;
-- SID signals
signal sid_do : std_logic_vector (7 downto 0);
-- Atom extension register signals
signal reg_addr : std_logic_vector (4 downto 0);
signal reg_do : std_logic_vector (7 downto 0);
signal extensions : std_logic_vector (7 downto 0);
signal char_addr : std_logic_vector (7 downto 0);
signal ocrx : std_logic_vector (7 downto 0);
signal ocry : std_logic_vector (7 downto 0);
signal octl : std_logic_vector (7 downto 0);
signal octl2 : std_logic_vector (7 downto 0);
signal char_we : std_logic;
signal char_reg : std_logic_vector (7 downto 0);
signal mc6847_an_s : std_logic;
signal mc6847_intn_ext : std_logic;
signal mc6847_inv : std_logic;
signal mc6847_css : std_logic;
signal mc6847_d_final : std_logic_vector (7 downto 0);
signal mc6847_d : std_logic_vector (7 downto 0);
signal mc6847_d_with_pointer : std_logic_vector (7 downto 0);
signal mc6847_char_a : std_logic_vector (10 downto 0);
signal mc6847_addrb : std_logic_vector (12 downto 0);
signal mc6847_addrb_hw : std_logic_vector (12 downto 0);
signal char_d_o : std_logic_vector (7 downto 0);
signal pointer_nr : std_logic_vector (7 downto 0);
signal pointer_nr_rd : std_logic_vector (7 downto 0);
signal pointer_x : std_logic_vector (7 downto 0);
signal pointer_y : std_logic_vector (7 downto 0);
signal pointer_y_inv : std_logic_vector (7 downto 0);
signal pointer_left : std_logic;
signal pointer_middle : std_logic;
signal pointer_right : std_logic;
signal hwscrollmode : std_logic;
signal scroll_left : std_logic_vector (7 downto 0);
signal scroll_right : std_logic_vector (7 downto 0);
signal scroll_h : std_logic_vector (7 downto 0);
signal scroll_top : std_logic_vector (7 downto 0);
signal scroll_bottom : std_logic_vector (7 downto 0);
signal scroll_v : std_logic_vector (7 downto 0);
signal width32 : std_logic;
signal lines : std_logic_vector (7 downto 0);
signal vga80x40mode : std_logic;
signal int_char_a : std_logic_vector (10 downto 0);
signal final_char_a : std_logic_vector (10 downto 0);
signal vga80_R : std_logic;
signal vga80_G : std_logic;
signal vga80_B : std_logic;
signal vga80_vsync : std_logic;
signal vga80_hsync : std_logic;
signal vga80_blank : std_logic;
signal vga80_invert : std_logic;
signal vga80_char_a : std_logic_vector (10 downto 0);
signal vga80_char_d : std_logic_vector (7 downto 0);
signal vga80_addrb : std_logic_vector (12 downto 0);
signal vga80_addrb_hw: std_logic_vector (12 downto 0);
signal uart_do : std_logic_vector (7 downto 0);
signal bank0_douta : std_logic_vector (7 downto 0);
signal bank0_doutb : std_logic_vector (7 downto 0);
signal bank0_we : std_logic;
signal bank1_douta : std_logic_vector (7 downto 0);
signal bank1_doutb : std_logic_vector (7 downto 0);
signal bank1_we : std_logic;
signal bank_sela : std_logic;
signal bank_selb : std_logic;
signal fs_n : std_logic;
signal hs_n : std_logic;
signal hs_n1 : std_logic;
signal CSS1 : std_logic;
signal CSS2 : std_logic;
signal CSS3 : std_logic;
signal AG1 : std_logic;
signal AG2 : std_logic;
signal AG3 : std_logic;
signal GM1 : std_logic_vector (2 downto 0);
signal GM2 : std_logic_vector (2 downto 0);
signal GM3 : std_logic_vector (2 downto 0);
function truncate(x: in std_logic_vector; constant length: in integer)
return std_logic_vector is
variable result : std_logic_vector(length-1 downto 0);
begin
result := x(length-1 downto 0);
return result;
end function;
function modulo5 (x : std_logic_vector(7 downto 0))
return std_logic_vector is
variable tmp1 : std_logic_vector(4 downto 0);
variable tmp2 : std_logic_vector(3 downto 0);
begin
-- uses some tricks from here:
-- http://homepage.cs.uiowa.edu/~jones/bcd/mod.shtml
-- calculate modulo 15
tmp1 := ('0' & X(7 downto 4)) + ('0' & X(3 downto 0));
if (tmp1 = 30) then
tmp1 := "00000";
elsif (tmp1 >= 15) then
tmp1 := tmp1 - 15;
end if;
-- calculate modulo 5
tmp2 := tmp1(3 downto 0);
if (tmp2 >= 10) then
tmp2 := tmp2 - 5;
end if;
if (tmp2 >= 5) then
tmp2 := tmp2 - 5;
end if;
return tmp2(2 downto 0);
end modulo5;
begin
-----------------------------------------------------------------------------
-- Core
-----------------------------------------------------------------------------
-- Motorola MC6847
-- Original version: https://svn.pacedev.net/repos/pace/sw/src/component/video/mc6847.vhd
-- Updated by AlanD for his Atom FPGA: http://stardot.org.uk/forums/viewtopic.php?f=3&t=6313
-- A further few bugs fixed by myself
Inst_mc6847 : entity work.mc6847
port map (
clk => clock_vga,
clk_ena => clock_vga_en,
reset => reset_vid,
da0 => open,
videoaddr => mc6847_addrb,
dd => mc6847_d_final,
hs_n => hs_n,
fs_n => fs_n,
an_g => ag_masked,
an_s => mc6847_an_s,
intn_ext => mc6847_intn_ext,
gm => gm_masked,
css => mc6847_css,
inv => mc6847_inv,
red => vga_red,
green => vga_green,
blue => vga_blue,
hsync => vga_hsync,
vsync => vga_vsync,
artifact_en => '0',
artifact_set => '0',
artifact_phase => '0',
hblank => vga_hblank,
vblank => vga_vblank,
cvbs => open,
black_backgnd => BLACK_BACKGND,
char_a => mc6847_char_a,
char_d_o => char_d_o
);
vga_blank <= vga_vblank or vga_hblank;
nFS <= fs_n;
mc6847_d_final <= mc6847_d_with_pointer when CImplMouse else mc6847_d;
Optional_not_DoubleVideo: if not CImplDoubleVideo generate
-- 8Kx8 Dual port video RAM
-- Port A connects to Atom and is read/write
-- Port B connects to MC6847 and is read only
Inst_VideoRam : entity work.VideoRam
port map (
clka => clock_main,
wea => ram_we,
addra => addr,
dina => din,
douta => douta,
clkb => clock_vga,
web => '0',
addrb => addrb,
dinb => (others => '0'),
doutb => doutb
);
end generate;
Optional_DoubleVideo: if CImplDoubleVideo generate
-- Double Buffered 8Kx8 Dual port video RAM
-- Port A connects to Atom and is read/write
-- Port B connects to MC6847 and is read only
Inst_VideoRam0 : entity work.VideoRam
port map (
clka => clock_main,
wea => bank0_we,
addra => addr,
dina => din,
douta => bank0_douta,
clkb => clock_vga,
web => '0',
addrb => addrb,
dinb => (others => '0'),
doutb => bank0_doutb
);
Inst_VideoRam1 : entity work.VideoRam
port map (
clka => clock_main,
wea => bank1_we,
addra => addr,
dina => din,
douta => bank1_douta,
clkb => clock_vga,
web => '0',
addrb => addrb,
dinb => (others => '0'),
doutb => bank1_doutb
);
bank0_we <= ram_we when bank_sela = '0' else '0';
bank1_we <= ram_we when bank_sela = '1' else '0';
douta <= bank1_douta when bank_sela = '1' else bank0_douta;
doutb <= bank1_doutb when bank_selb = '1' else bank0_doutb;
end generate;
bank_sela <= extensions(4) when CImplDoubleVideo else '0';
bank_selb <= extensions(5) when CImplDoubleVideo else '0';
hwscrollmode <= extensions(6) when CImplHWScrolling else '0';
addrb <= mc6847_addrb when vga80x40mode = '0' and hwscrollmode = '0' else
mc6847_addrb_hw when vga80x40mode = '0' and hwscrollmode = '1' else
vga80_addrb when hwscrollmode = '0' else
vga80_addrb_hw;
-- VGA Multiplexing between two controllers
vga80x40mode <= extensions(7) when CImplVGA80x40 else '0';
final_red <= vga_red(7) when vga80x40mode = '0' else vga80_R;
final_green1 <= vga_green(7) when vga80x40mode = '0' else vga80_G;
final_green0 <= vga_green(6) when vga80x40mode = '0' else vga80_G;
final_blue <= vga_blue(7) when vga80x40mode = '0' else vga80_B;
final_vsync <= vga_vsync when vga80x40mode = '0' else vga80_vsync;
final_hsync <= vga_hsync when vga80x40mode = '0' else vga80_hsync;
final_blank <= vga_blank when vga80x40mode = '0' else vga80_blank;
-- int_char_a(10 downto 4) select character 0..127
-- int_chat_a( 3 downto 0) select row 0..11
int_char_a <= mc6847_char_a when vga80x40mode = '0' else vga80_char_a;
final_char_a <= int_char_a when extensions(3) = '0' or int_char_a(10) = '1' else
int_char_a(9 downto 4) & "01100" when int_char_a(3 downto 0) = "0010" else
int_char_a(9 downto 4) & "01101" when int_char_a(3 downto 0) = "0011" else
int_char_a(9 downto 4) & "01110" when int_char_a(3 downto 0) = "0100" else
int_char_a(9 downto 4) & "01111" when int_char_a(3 downto 0) = "0101" else
int_char_a(9 downto 4) & "11100" when int_char_a(3 downto 0) = "0110" else
int_char_a(9 downto 4) & "11101" when int_char_a(3 downto 0) = "0111" else
int_char_a(9 downto 4) & "11110" when int_char_a(3 downto 0) = "1000" else
int_char_a(9 downto 4) & "11111" when int_char_a(3 downto 0) = "1001" else
"00000000000";
-- Hold internal reset low for two frames after nRST released
-- This avoids any diaplay glitches
process (clock_vga)
variable state : std_logic_vector(2 downto 0);
begin
if rising_edge(clock_vga) then
if (reset = '1') then
state := "000";
elsif (state = "000" and vga_vsync = '0') then
state := "001";
elsif (state = "001" and vga_vsync = '1') then
state := "010";
elsif (state = "010" and vga_vsync = '0') then
state := "011";
elsif (state = "011" and vga_vsync = '1') then
state := "100";
end if;
mask <= state(2);
end if;
end process;
process (clock_vga)
begin
if rising_edge(clock_vga) then
-- Sample the mode inputs, so we can later use a majority vote system
-- This is necessary to make these imputs more robust to noise
CSS1 <= CSS;
CSS2 <= CSS1;
CSS3 <= CSS2;
AG1 <= AG;
AG2 <= AG1;
AG3 <= AG2;
GM1 <= GM;
GM2 <= GM1;
GM3 <= GM2;
clock_vga_en <= not clock_vga_en;
hs_n1 <= hs_n;
-- Sample the mode inputs only during the active part of the display
if (hs_n = '0' and hs_n1 = '1' and fs_n = '1') then
-- During reset, force the 6847 mode select inputs low
-- (this is necessary to stop the mode changing during reset, as the GODIL has 1.5K pullups)
if (mask = '1') then
gm_masked(0) <= (GM1(0) and GM2(0)) or (GM2(0) and GM3(0)) or (GM1(0) and GM3(0));
gm_masked(1) <= (GM1(1) and GM2(1)) or (GM2(1) and GM3(1)) or (GM1(1) and GM3(1));
gm_masked(2) <= (GM1(2) and GM2(2)) or (GM2(2) and GM3(2)) or (GM1(2) and GM3(2));
ag_masked <= (AG1 and AG2) or (AG2 and AG3) or (AG1 and AG3);
css_masked <= (CSS1 and CSS2) or (CSS2 and CSS3) or (CSS1 and CSS3);
else
gm_masked <= (others => '0');
ag_masked <= '0';
css_masked <= '0';
end if;
end if;
end if;
end process;
reg_addr <= addr(4 downto 0);
reg_do <= extensions when reg_addr = "00000" and (CImplGraphicsExt or CImplVGA80x40 or CImplHWScrolling or CImplDoubleVideo) else
char_addr when reg_addr = "00001" and CImplSoftChar else
ocrx when reg_addr = "00010" and CImplVGA80x40 else
ocry when reg_addr = "00011" and CImplVGA80x40 else
octl when reg_addr = "00100" and CImplVGA80x40 else
octl2 when reg_addr = "00101" and CImplVGA80x40 else
scroll_h when reg_addr = "00110" and CImplHWScrolling else
scroll_v when reg_addr = "00111" and CImplHWScrolling else
pointer_x when reg_addr = "01000" and CImplMouse else
pointer_y_inv when reg_addr = "01001" and CImplMouse else
pointer_nr_rd when reg_addr = "01010" and CImplMouse else
scroll_left when reg_addr = "01011" and CImplHWScrolling else
scroll_right when reg_addr = "01100" and CImplHWScrolling else
scroll_top when reg_addr = "01101" and CImplHWScrolling else
scroll_bottom when reg_addr = "01110" and CImplHWScrolling else
MAJOR_VERSION & MINOR_VERSION when reg_addr = "01111" else
char_reg when CImplSoftChar else
x"f1";
dout <= sid_do when sid_cs = '1' and CimplSID else
uart_do when uart_cs = '1' and CimplUart else
reg_do when reg_cs = '1' else
douta;
-----------------------------------------------------------------------------
-- Optional Soft Character Set
-----------------------------------------------------------------------------
Optional_SoftChar: if CImplSoftChar generate
-- A register to control extra 6847 features
process (clock_main)
begin
if rising_edge(clock_main) then
if (reset = '1') then
char_addr <= (others => '0');
elsif (reg_cs = '1' and reg_we = '1') then
case reg_addr is
-- char_addr register
when "00001" =>
char_addr <= din;
when others =>
end case;
end if;
end if;
end process;
char_we <= '1' when reg_cs = '1' and reg_we = '1' and char_addr(7) = '1' and reg_addr(4) = '1' else '0';
---- ram for char generator
charrom_inst : entity work.CharRam
port map(
clka => clock_main,
wea => char_we,
addra(10 downto 4) => char_addr(6 downto 0),
addra(3 downto 0) => addr(3 downto 0),
dina => din,
douta => char_reg,
clkb => clock_vga,
web => '0',
addrb => final_char_a,
dinb => (others => '0'),
doutb => char_d_o
);
end generate;
Optional_Not_SoftChar: if not CImplSoftChar generate
---- ram for char generator
charrom_inst : entity work.CharRom
port map(
CLK => clock_vga,
ADDR => final_char_a,
DATA => char_d_o
);
end generate;
-----------------------------------------------------------------------------
-- Graphics Extension Register
-- shared by several optional functions
-----------------------------------------------------------------------------
Optional_GraphicsExtReg: if CImplGraphicsExt or CImplVGA80x40 or CImplHWScrolling generate
-- A register to control extra 6847 features
process (clock_main)
begin
if rising_edge(clock_main) then
if (reset = '1') then
extensions <= (others => '0');
extensions(3) <= charSet;
elsif (reg_cs = '1' and reg_we = '1') then
case reg_addr is
-- extensions register
when "00000" =>
extensions <= din;
when others =>
end case;
end if;
end if;
end process;
end generate;
-----------------------------------------------------------------------------
-- Optional Graphics Modes
-----------------------------------------------------------------------------
Optional_GraphicsExt: if CImplGraphicsExt generate
-- Adjust the inputs to the 6847 based on the extensions register
process (extensions, doutb, css_masked, ag_masked)
begin
case extensions(2 downto 0) is
-- Text plus 8 Colour Semigraphics 4
when "001" =>
mc6847_an_s <= doutb(6);
mc6847_intn_ext <= '0';
mc6847_inv <= doutb(7);
-- Replace the 64-127 and 192-255 blocks with Semigraphics 4
-- Only tweak the data bus when actually displaying semigraphics
if (ag_masked = '0' and doutb(6) = '1') then
mc6847_d <= '0' & doutb(7) & doutb(5 downto 0);
else
mc6847_d <= doutb;
end if;
mc6847_css <= css_masked;
-- 2 Colour Text Only
when "010" =>
mc6847_an_s <= '0';
mc6847_intn_ext <= '0';
mc6847_inv <= doutb(7);
if (ag_masked = '0' and doutb(6) = '1') then
mc6847_d <= "00" & doutb(5 downto 0);
else
mc6847_d <= doutb;
end if;
mc6847_css <= doutb(6) xor css_masked;
-- 4 Colour Semigraphics 6 Only
when "011" =>
mc6847_an_s <= '1';
mc6847_intn_ext <= '1';
mc6847_inv <= doutb(7);
mc6847_d <= doutb;
mc6847_css <= css_masked;
-- Extended character set, lower case replaces Red Semigraphics
-- 00-3F - Normal Upper Case
-- 40-7F - Yellow Semigraphics 6
-- 80-BF - Inverse Upper Case
-- C0-FF - Normal Lower Case
when "100" =>
mc6847_an_s <= doutb(6) and not doutb(7);
mc6847_intn_ext <= doutb(6);
mc6847_inv <= not doutb(6) and doutb(7);
mc6847_d <= doutb;
mc6847_css <= css_masked;
-- Extended character set, lower case replaces Red and Yello Semigraphics
-- 00-3F - Normal Upper Case
-- 40-7F - Normal Lower Case
-- 80-BF - Inverse Upper Case
-- C0-FF - Inverse Lower Case
when "101" =>
mc6847_an_s <= '0';
mc6847_intn_ext <= '0';
mc6847_inv <= doutb(7);
mc6847_d <= doutb;
mc6847_css <= css_masked;
-- Extended character set, lower case replaces inverse
-- 00-3F - Normal Upper Case
-- 40-7F - Yellow Semigraphics 6 -- Blue
-- 80-BF - Normal Lower Case
-- C0-FF - Red Semigraphics 6
when "110" =>
mc6847_an_s <= doutb(6);
mc6847_intn_ext <= doutb(6);
mc6847_inv <= '0';
if (ag_masked = '0' and doutb(7 downto 6) = "10") then
mc6847_d <= "01" & doutb(5 downto 0);
else
mc6847_d <= doutb;
end if;
mc6847_css <= css_masked;
-- Just replace inverse upper case (32 chars) with lower case
-- 00-3F - Normal Upper Case
-- 40-7F - Yellow Semigraphics 6
-- 80-BF - Lower Case/Inverse Upper Case
-- C0-FF - Red Semigraphics 6
when "111" =>
mc6847_an_s <= doutb(6);
mc6847_intn_ext <= doutb(6);
mc6847_inv <= doutb(7) and doutb(5);
if (ag_masked = '0' and doutb(7 downto 5) = "100") then
mc6847_d <= "01" & doutb(5 downto 0);
else
mc6847_d <= doutb;
end if;
mc6847_css <= css_masked;
-- Default Atom Behaviour
-- 00-3F - Normal Upper Case
-- 40-7F - Yellow Semigraphics 6
-- 80-BF - Inverse Upper Case
-- C0-FF - Red Semigraphics 6
when others =>
mc6847_an_s <= doutb(6);
mc6847_intn_ext <= doutb(6);
mc6847_inv <= doutb(7);
mc6847_d <= doutb;
mc6847_css <= css_masked;
end case;
end process;
end generate;
Optional_Not_GraphicsExt: if not CImplGraphicsExt generate
mc6847_an_s <= doutb(6);
mc6847_intn_ext <= doutb(6);
mc6847_inv <= doutb(7);
mc6847_d <= doutb;
mc6847_css <= css_masked;
end generate;
-----------------------------------------------------------------------------
-- Optional SID
-----------------------------------------------------------------------------
Optional_SID: if CImplSID generate
Inst_sid6581: entity work.sid6581
port map (
clk_1MHz => clock_sid_1MHz,
clk32 => clock_sid_32MHz,
clk_DAC => clock_sid_dac,
reset => reset,
cs => sid_cs,
we => sid_we,
addr => reg_addr,
di => din,
do => sid_do,
pot_x => '0',
pot_y => '0',
audio_out => sid_audio,
audio_data => sid_audio_d
);
-- Clock_Sid_1MHz is derived by dividing down thw 32MHz clock
process (clock_sid_32MHz)
begin
if rising_edge(clock_sid_32MHz) then
div32 <= div32 + 1;
end if;
end process;
clock_sid_1MHz <= div32(4);
end generate;
-----------------------------------------------------------------------------
-- Optional VGA80x40 Mode
-----------------------------------------------------------------------------
Optional_VGA80x40: if CImplVGA80x40 generate
-- A register to control extra 6847 features
process (clock_main)
begin
if rising_edge(clock_main) then
if (reset = '1') then
ocrx <= (others => '0');
ocry <= (others => '0');
-- Default to Green Foreground
octl <= "10000010";
-- Default to Black Background
octl2 <= "00000000";
elsif (reg_cs = '1' and reg_we = '1') then
case reg_addr is
when "00010" =>
ocrx <= din;
when "00011" =>
ocry <= din;
when "00100" =>
octl <= din;
when "00101" =>
octl2 <= din;
when others =>
end case;
end if;
end if;
end process;
Inst_vga80x40: entity work.vga80x40 PORT MAP(
reset => reset_vid,
clk25MHz => clock_vga,
TEXT_A => vga80_addrb,
TEXT_D => mc6847_d,
FONT_A(10 downto 0) => vga80_char_a,
FONT_A(11) => vga80_invert,
FONT_D => vga80_char_d,
ocrx => ocrx,
ocry => ocry,
octl => octl,
octl2 => octl2,
R => vga80_R,
G => vga80_G,
B => vga80_B,
hsync => vga80_hsync,
vsync => vga80_vsync,
blank => vga80_blank
);
vga80_char_d <= char_d_o when vga80_invert='0' else char_d_o xor "11111111";
end generate;
-----------------------------------------------------------------------------
-- Optional HW Scrolling of Atom Modes
-----------------------------------------------------------------------------
Optional_HWScrolling_Atom: if CImplHWScrolling generate
-- A register to control extra 6847 features
process (clock_main)
begin
if rising_edge(clock_main) then
if (reset = '1') then
scroll_h <= (others => '0');
scroll_left <= (others => '0');
scroll_right <= (others => '0');
scroll_v <= (others => '0');
scroll_top <= (others => '0');
scroll_bottom <= (others => '0');
elsif (reg_cs = '1' and reg_we = '1') then
case reg_addr is
when "00110" =>
scroll_h <= din;
when "00111" =>
scroll_v <= din;
when "01011" =>
scroll_left <= din;
when "01100" =>
scroll_right <= din;
when "01101" =>
scroll_top <= din;
when "01110" =>
scroll_bottom <= din;
when others =>
end case;
end if;
end if;
end process;
-- 32 bytes wide in Modes 0, 2a, 3a, 4a, 4
-- 16 bytes wide in Modes 1a, 1, 2, 3
width32 <= '1' when ag_masked = '0' or
gm_masked = "010" or gm_masked = "100" or
gm_masked = "110" or gm_masked = "111" else '0';
lines <= "00010000" when ag_masked = '0' else
"01000000" when gm_masked = "000" or gm_masked = "001" or gm_masked = "010" else
"01100000" when gm_masked = "011" or gm_masked = "100" else
"11000000";
-- Hardware Scrolling of atom modes
-- mc6847_addrb -> mc6847_addrb_hw
process (lines, width32, scroll_left, scroll_right, scroll_h, scroll_top, scroll_bottom, scroll_v, mc6847_addrb)
variable x : std_logic_vector(5 downto 0);
variable y : std_logic_vector(8 downto 0);
variable scroll_h_min : std_logic_vector(7 downto 0);
variable scroll_h_max : std_logic_vector(7 downto 0);
variable scroll_v_min : std_logic_vector(7 downto 0);
variable scroll_v_max : std_logic_vector(7 downto 0);
begin
scroll_h_min := scroll_left;
scroll_v_min := scroll_top;
scroll_v_max := lines - scroll_bottom;
if (width32 = '0') then
x := "00" & mc6847_addrb(3 downto 0);
y := "0" & mc6847_addrb(11 downto 4);
scroll_h_max := 16 - scroll_right;
else
x := "0" & mc6847_addrb(4 downto 0);
y := "0" & mc6847_addrb(12 downto 5);
scroll_h_max := 32 - scroll_right;
end if;
if (x >= scroll_h_min and x < scroll_h_max) and (y >= scroll_v_min and y < scroll_v_max) then
x := truncate(x + scroll_h, 6);
if (x >= scroll_h_max) then
x := truncate(x - (scroll_h_max - scroll_h_min), 6);
end if;
y := y + scroll_v;
if (y >= scroll_v_max) then
y := y - (scroll_v_max - scroll_v_min);
end if;
end if;
if (width32 = '0') then
mc6847_addrb_hw(3 downto 0) <= x(3 downto 0);
mc6847_addrb_hw(12 downto 4) <= y;
else
mc6847_addrb_hw(4 downto 0) <= x(4 downto 0);
mc6847_addrb_hw(12 downto 5) <= y(7 downto 0);
end if;
end process;
end generate;
-----------------------------------------------------------------------------
-- Optional HW Scrolling of VGA80x40 Modes
-----------------------------------------------------------------------------
Optional_HWScrolling_VGA80x40: if CImplHWScrolling and CImplVGA80x40 generate
-- Hardware Scrolling of vga80x40 mode
-- vga80_addrb -> vga80_addrb_hw
process (scroll_h, scroll_v, vga80_addrb)
variable addr1 : std_logic_vector(11 downto 0);
variable addr2 : std_logic_vector(13 downto 0);
variable attr : std_logic;
variable display_start : std_logic_vector(11 downto 0);
variable x1 : std_logic_vector(6 downto 0);
variable x2 : std_logic_vector(7 downto 0);
begin
-- determine if this is an attribute access or not
if (vga80_addrb < 3200) then
attr := '0';
else
attr := '1';
end if;
-- calculate an address in the range 0..3199 regardless of whether char or attr being accessed
if (attr = '0') then
addr1 := vga80_addrb(11 downto 0);
else
addr1 := truncate(vga80_addrb - 3200, 12);
end if;
-- calculate x from the address modulo 80
x1 := modulo5(addr1(11 downto 4)) & addr1(3 downto 0);
-- calculate the new x after the scroll_h has been added, modulo 80
x2 := truncate(('0' & x1) + ('0' & scroll_h), 8);
if (x2 >= 80) then
x2 := x2 - 80;
end if;
-- calculate the display start as 80 * scroll_v
display_start := (scroll_v(5 downto 0) & "000000") + ("00" & scroll_v(5 downto 0) & "0000");
-- calculate the new screen start address, extending the precision by one bit
addr2 := ('0' & vga80_addrb) + ("00" & display_start) - ("0000000" & x1) + ("0000000" & x2(6 downto 0));
-- detect wrapping in wrapping in the character and attributevregions
if ((attr = '0' and addr2 >= 3200) or addr2 >= 6400) then
vga80_addrb_hw <= truncate(addr2 - 3200, 13);
else
vga80_addrb_hw <= addr2(12 downto 0);
end if;
end process;
end generate;
-----------------------------------------------------------------------------
-- Optional Mouse
-----------------------------------------------------------------------------
Optional_Mouse: if CImplMouse generate
Inst_Pointer: entity work.Pointer PORT MAP (
CLK => clock_vga,
PO => not pointer_nr(7),
PS => pointer_nr(4 downto 0),
X => pointer_x,
Y => pointer_y,
ADDR => mc6847_addrb,
DIN => mc6847_d,
DOUT => mc6847_d_with_pointer
);
Inst_MouseRefComp: entity work.MouseRefComp
generic map (
MainClockSpeed => MainClockSpeed
)
PORT MAP (
CLK => clock_main,
RESOLUTION => '1', -- select 256x192 resolution
RST => reset,
SWITCH => '0',
LEFT => pointer_left,
MIDDLE => pointer_middle,
NEW_EVENT => open,
RIGHT => pointer_right,
XPOS(7 downto 0) => pointer_x,
XPOS(9 downto 8) => open,
YPOS(7 downto 0) => pointer_y,
YPOS(9 downto 8) => open,
ZPOS => open,
PS2_CLK => PS2_CLK,
PS2_DATA => PS2_DATA
);
pointer_nr_rd <= pointer_nr(7) & "1111" & not pointer_middle & not pointer_right & not pointer_left;
pointer_y_inv <= pointer_y xor "11111111";
process (clock_main)
begin
if rising_edge(clock_main) then
if (reset = '1') then
pointer_nr <= "10000000";
elsif (reg_cs = '1' and reg_we = '1') then
case reg_addr is
when "01010" =>
pointer_nr <= din;
when others =>
end case;
end if;
end if;
end process;
end generate;
-----------------------------------------------------------------------------
-- Optional Mouse
-----------------------------------------------------------------------------
Optional_Uart: if CImplUart generate
inst_miniuart: entity work.miniuart
generic map (
MainClockSpeed => MainClockSpeed,
DefaultBaud => DefaultBaud
)
port map (
wb_clk_i => clock_main,
wb_rst_i => reset,
wb_adr_i => addr(1 downto 0),
wb_dat_i => din,
wb_dat_o => uart_do,
wb_we_i => uart_we,
wb_stb_i => uart_cs,
wb_ack_o => open,
inttx_o => open,
intrx_o => open,
br_clk_i => clock_main,
txd_pad_o => uart_TxD,
rxd_pad_i => uart_RxD,
esc_o => uart_escape,
break_o => uart_break,
uart_irq_n => uart_irq_n
);
end generate;
Optional_Not_Uart: if not CImplUart generate
uart_TxD <= '1';
uart_escape <= '1';
uart_break <= '1';
end generate;
end BEHAVIORAL;
|
---------------------------------------------------------------------------
-- This file is part of lt24ctrl, a video controler IP core for Terrasic
-- LT24 LCD display
-- Copyright (C) 2017 Ludovic Noury <[email protected]>
--
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as
-- published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
---------------------------------------------------------------------------
entity lt24_fsm is
port(clk : in std_logic;
resetn : in std_logic;
tick_1ms : in std_logic;
tick_10ms : in std_logic;
tick_120ms : in std_logic;
tick_tmin : in std_logic;
clr_cptdelay: out std_logic;
clr_init_rom_addr: out std_logic;
inc_init_rom_addr: out std_logic;
end_init_rom : in std_logic;
init_rom_data : in std_logic_vector(16 downto 0);
clr_cptpix: out std_logic;
inc_cptpix: out std_logic;
end_cptpix: in std_logic;
color : in std_logic_vector(15 downto 0);
lt24_reset_n: out std_logic;
lt24_lcd_on : out std_logic;
lt24_cs_n : out std_logic;
lt24_rs : out std_logic;
lt24_rd_n : out std_logic;
lt24_wr_n : out std_logic;
lt24_d : out std_logic_vector(15 downto 0));
end;
---------------------------------------------------------------------------
architecture rtl of lt24_fsm is
type state_type is (reset0 , reset1 , reset2,
init_a , init_b,
display_cmd0_a , display_cmd0_b,
display_cmd0_data0_a, display_cmd0_data0_b,
display_cmd0_data1_a, display_cmd0_data1_b,
display_cmd1_a , display_cmd1_b,
display_cmd1_data0_a, display_cmd1_data0_b,
display_cmd1_data1_a, display_cmd1_data1_b,
display_cmd2_a , display_cmd2_b,
display_cmd3_a , display_cmd3_b,
display_pix_a , display_pix_b);
signal state, next_state : state_type;
begin
update_state:process (clk, resetn)
begin
if resetn = '0' then
state <= reset0;
elsif rising_edge(clk) then
state <= next_state;
end if;
end process;
nextstate_and_outputs:process (state, tick_1ms, tick_10ms, tick_120ms, tick_tmin,
init_rom_data, color, end_init_rom, end_cptpix)
begin
next_state <= state;
clr_cptdelay <= '0';
clr_init_rom_addr <= '0';
inc_init_rom_addr <= '0';
clr_cptpix <= '0';
inc_cptpix <= '0';
lt24_reset_n <= '1';
lt24_lcd_on <= '1';
lt24_cs_n <= '1';
lt24_rs <= '0';
lt24_rd_n <= '1';
lt24_wr_n <= '1';
lt24_d <= x"0000";
case state is
----------------------------------------------------------------
when reset0 =>
if tick_1ms = '1' then
next_state <= reset1;
end if;
lt24_reset_n <= '1';
clr_cptdelay <= tick_1ms;
----------------------------------------------------------------
when reset1 =>
if tick_10ms = '1' then
next_state <= reset2;
end if;
lt24_reset_n <= '0';
clr_cptdelay <= tick_10ms;
----------------------------------------------------------------
when reset2 =>
if tick_120ms = '1' then
next_state <= init_a;
end if;
lt24_reset_n <= '1';
clr_init_rom_addr <= '1';
clr_cptdelay <= tick_120ms;
----------------------------------------------------------------
when init_a =>
if tick_tmin = '1' then
next_state <= init_b;
end if;
lt24_wr_n <= '0';
lt24_cs_n <= '0';
lt24_rs <= init_rom_data(16);
lt24_d <= init_rom_data(15 downto 0);
clr_cptdelay <= tick_tmin;
----------------------------------------------------------------
when init_b =>
if (tick_tmin = '1') and (end_init_rom = '1') then
next_state <= display_cmd0_a;
elsif (tick_tmin = '1') and (end_init_rom = '0') then
next_state <= init_a;
end if;
lt24_wr_n <= '1';
lt24_cs_n <= '0';
lt24_rs <= init_rom_data(16);
lt24_d <= init_rom_data(15 downto 0);
inc_init_rom_addr <= tick_tmin; --'1';
clr_cptdelay <= tick_tmin;
----------------------------------------------------------------
when display_cmd0_a =>
if tick_tmin = '1' then
next_state <= display_cmd0_b;
end if;
lt24_wr_n <= '0';
lt24_cs_n <= '0';
lt24_rs <= '0';
lt24_d <= x"002A";
clr_cptdelay <= tick_tmin;
----------------------------------------------------------------
when display_cmd0_b =>
if tick_tmin = '1' then
next_state <= display_cmd0_data0_a;
end if;
lt24_wr_n <= '1';
lt24_cs_n <= '0';
lt24_rs <= '0';
lt24_d <= x"002A";
clr_cptdelay <= tick_tmin;
----------------------------------------------------------------
when display_cmd0_data0_a =>
if tick_tmin = '1' then
next_state <= display_cmd0_data0_b;
end if;
lt24_wr_n <= '0';
lt24_cs_n <= '0';
lt24_rs <= '1';
lt24_d <= x"0000";
clr_cptdelay <= tick_tmin;
----------------------------------------------------------------
when display_cmd0_data0_b =>
if tick_tmin = '1' then
next_state <= display_cmd0_data1_a;
end if;
lt24_wr_n <= '1';
lt24_cs_n <= '0';
lt24_rs <= '1';
lt24_d <= x"0000";
clr_cptdelay <= tick_tmin;
----------------------------------------------------------------
when display_cmd0_data1_a =>
if tick_tmin = '1' then
next_state <= display_cmd0_data1_b;
end if;
lt24_wr_n <= '0';
lt24_cs_n <= '0';
lt24_rs <= '1';
lt24_d <= x"0000";
clr_cptdelay <= tick_tmin;
----------------------------------------------------------------
when display_cmd0_data1_b =>
if tick_tmin = '1' then
next_state <= display_cmd1_a;
end if;
lt24_wr_n <= '1';
lt24_cs_n <= '0';
lt24_rs <= '1';
lt24_d <= x"0000";
clr_cptdelay <= tick_tmin;
----------------------------------------------------------------
when display_cmd1_a =>
if tick_tmin = '1' then
next_state <= display_cmd1_b;
end if;
lt24_wr_n <= '0';
lt24_cs_n <= '0';
lt24_rs <= '0';
lt24_d <= x"002B";
clr_cptdelay <= tick_tmin;
----------------------------------------------------------------
when display_cmd1_b =>
if tick_tmin = '1' then
next_state <= display_cmd1_data0_a;
end if;
lt24_wr_n <= '1';
lt24_cs_n <= '0';
lt24_rs <= '0';
lt24_d <= x"002B";
clr_cptdelay <= tick_tmin;
----------------------------------------------------------------
when display_cmd1_data0_a =>
if tick_tmin = '1' then
next_state <= display_cmd1_data0_b;
end if;
lt24_wr_n <= '0';
lt24_cs_n <= '0';
lt24_rs <= '1';
lt24_d <= x"0000";
clr_cptdelay <= tick_tmin;
----------------------------------------------------------------
when display_cmd1_data0_b =>
if tick_tmin = '1' then
next_state <= display_cmd1_data1_a;
end if;
lt24_wr_n <= '1';
lt24_cs_n <= '0';
lt24_rs <= '1';
lt24_d <= x"0000";
clr_cptdelay <= tick_tmin;
----------------------------------------------------------------
when display_cmd1_data1_a =>
if tick_tmin = '1' then
next_state <= display_cmd1_data1_b;
end if;
lt24_wr_n <= '0';
lt24_cs_n <= '0';
lt24_rs <= '1';
lt24_d <= x"0000";
clr_cptdelay <= tick_tmin;
----------------------------------------------------------------
when display_cmd1_data1_b =>
if tick_tmin = '1' then
next_state <= display_cmd2_a;
end if;
lt24_wr_n <= '1';
lt24_cs_n <= '0';
lt24_rs <= '1';
lt24_d <= x"0000";
clr_cptdelay <= tick_tmin;
----------------------------------------------------------------
when display_cmd2_a =>
if tick_tmin = '1' then
next_state <= display_cmd2_b;
end if;
lt24_wr_n <= '0';
lt24_cs_n <= '0';
lt24_rs <= '0';
lt24_d <= x"002C";
clr_cptdelay <= tick_tmin;
----------------------------------------------------------------
when display_cmd2_b =>
if tick_tmin = '1' then
next_state <= display_cmd3_a;
end if;
lt24_wr_n <= '1';
lt24_cs_n <= '0';
lt24_rs <= '0';
lt24_d <= x"002C";
clr_cptdelay <= tick_tmin;
----------------------------------------------------------------
when display_cmd3_a =>
if tick_tmin = '1' then
next_state <= display_cmd3_b;
end if;
lt24_wr_n <= '0';
lt24_cs_n <= '0';
lt24_rs <= '0';
lt24_d <= x"002C";
clr_cptdelay <= tick_tmin;
----------------------------------------------------------------
when display_cmd3_b =>
if tick_tmin = '1' then
next_state <= display_pix_a;
end if;
lt24_wr_n <= '1';
lt24_cs_n <= '0';
lt24_rs <= '0';
lt24_d <= x"002C";
clr_cptpix <= '1';
clr_cptdelay <= tick_tmin;
----------------------------------------------------------------
when display_pix_a =>
if tick_tmin = '1' then
next_state <= display_pix_b;
end if;
lt24_wr_n <= '0';
lt24_cs_n <= '0';
lt24_rs <= '1';
lt24_d <= color;
clr_cptdelay <= tick_tmin;
----------------------------------------------------------------
when display_pix_b =>
if (tick_tmin = '1') and (end_cptpix = '1') then
next_state <= display_cmd0_a;
elsif (tick_tmin = '1') and (end_cptpix = '0') then
next_state <= display_pix_a;
end if;
lt24_wr_n <= '1';
lt24_cs_n <= '0';
lt24_rs <= '1';
lt24_d <= color;
inc_cptpix <= tick_tmin;
clr_cptdelay <= tick_tmin;
end case;
end process;
end;
---------------------------------------------------------------------------
|
architecture RTL of FIFO is begin end architecture RTL;
-- This should not fail
architecture RTL of FIFO is begin end architecture RTL;
-- This should fail
library ieee;
architecture RTL of FIFO is begin end architecture RTL;
-- This should not fail
library ieee;
architecture RTL of FIFO is begin end architecture RTL;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (17 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(17 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(17 DOWNTO 0):= hex_to_std_logic_vector("0",18);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (8191 downto 0) of std_logic_vector(17 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(17 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(0,
1,
"LUTROM.mif",
DEFAULT_DATA,
18,
8192);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>8192 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(12 DOWNTO 0) <= READ_ADDR(12 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ_REG(0);
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 8192 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
|
-- megafunction wizard: %LPM_FF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_ff
-- ============================================================
-- File Name: lpm_dff_uart0.vhd
-- Megafunction Name(s):
-- lpm_ff
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_dff_uart0 IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END lpm_dff_uart0;
ARCHITECTURE SYN OF lpm_dff_uart0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
COMPONENT lpm_ff
GENERIC (
lpm_fftype : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(15 DOWNTO 0);
lpm_ff_component : lpm_ff
GENERIC MAP (
lpm_fftype => "DFF",
lpm_type => "LPM_FF",
lpm_width => 16
)
PORT MAP (
clock => clock,
data => data,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: DFF NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "16"
-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff_uart0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff_uart0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff_uart0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff_uart0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff_uart0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
entity test is
subtype t is foo(bar (open)(open)(baz (quz'xxx)));
end;
|
-------------------------------------------------------------------------------------
-- FILE NAME : tb_toggle.vhd
-- AUTHOR : Luis
-- COMPANY :
-- UNITS : Entity -
-- Architecture - Behavioral
-- LANGUAGE : VHDL
-- DATE : May 21, 2010
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
--
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- LIBRARIES
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
Library UNISIM;
use UNISIM.vcomponents.all;
--Library xil_defaultlib;
-------------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------------
entity tb_toggle is
end tb_toggle;
-------------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------------
architecture Behavioral of tb_toggle is
-------------------------------------------------------------------------------------
-- CONSTANTS
-------------------------------------------------------------------------------------
constant CLK_10_MHZ : time := 100 ns;
constant CLK_200_MHZ : time := 5 ns;
constant CLK_125_MHZ : time := 8 ns;
constant CLK_100_MHZ : time := 10 ns;
constant CLK_368_MHZ : time := 2.7126 ns;
constant CLK_25_MHZ : time := 40 ns;
constant CLK_167_MHZ : time := 6 ns;
constant DATA_WIDTH : natural := 8;
constant ADDR_WIDTH : natural := 8;
type bus064 is array(natural range <>) of std_logic_vector(63 downto 0);
type bus008 is array(natural range <>) of std_logic_vector(7 downto 0);
type bus016 is array(natural range <>) of std_logic_vector(15 downto 0);
-----------------------------------------------------------------------------------
-- SIGNALS
-----------------------------------------------------------------------------------
signal sysclk_p : std_logic := '1';
signal sysclk_n : std_logic := '0';
signal clk : std_logic := '1';
signal clk200 : std_logic := '1';
signal clk100 : std_logic := '1';
signal rst : std_logic := '1';
signal rstn : std_logic := '0';
signal rst_rstin : std_logic_vector(31 downto 0) := (others=>'1');
signal clk_clkin : std_logic_vector(31 downto 0) := (others=>'1');
signal clk_cmd : std_logic;
signal in_cmd_val : std_logic;
signal in_cmd : std_logic_vector(63 downto 0);
signal out_cmd_val : std_logic;
signal out_cmd : std_logic_vector(63 downto 0);
signal host_data_in : std_logic_vector(63 downto 0);
signal host_data_out : std_logic_vector(63 downto 0);
signal host_val_in : std_logic;
signal host_val_out : std_logic;
signal host_stop_out : std_logic;
signal host_stop_in : std_logic;
signal lvds_in_n : std_logic_vector(1 downto 0);
signal lvds_in_p : std_logic_vector(1 downto 0);
signal lvds_out_n : std_logic_vector(1 downto 0);
signal lvds_out_p : std_logic_vector(1 downto 0);
--***********************************************************************************
begin
--***********************************************************************************
-- Clock & reset generation
sysclk_p <= not sysclk_p after CLK_25_MHZ/2;
sysclk_n <= not sysclk_p;
clk <= not clk after CLK_125_MHZ / 2;
clk200 <= not clk200 after CLK_200_MHZ / 2;
clk100 <= not clk100 after CLK_100_MHZ / 2;
rst <= '0' after CLK_125_MHZ * 10;
rstn <= '1' after CLK_125_MHZ * 10;
rst_rstin <= (0=>rst, 1 => rst, 2=> rst, others =>'0');
clk_clkin <= (13 => clk200, 14 => clk100, others=>clk);
-----------------------------------------------------------------------------------
-- Host Interface
-----------------------------------------------------------------------------------
inst0_generic_host: entity work.generic_host_emu
generic map (
global_start_addr_gen => x"0000000",
global_stop_addr_gen => x"00000FF",
private_start_addr_gen => x"0000000",
private_stop_addr_gen => x"00000FF"
)
port map (
cmdclk_out_cmdclk => clk_cmd, -- out std_logic;
cmd_in_cmdin => out_cmd , -- in std_logic_vector(63 downto 0);
cmd_in_cmdin_val => out_cmd_val, -- in std_logic;
cmd_out_cmdout => in_cmd, -- out std_logic_vector(63 downto 0);
cmd_out_cmdout_val => in_cmd_val, -- out std_logic;
ifpga_rst_out_ifpga_rst => open, -- out std_logic;
clk_clkin => (others=>'0'),-- in std_logic_vector(31 downto 0);
rst_rstin => (others=>'0'),-- in std_logic_vector(31 downto 0);
sys_clk => clk, -- in std_logic;
sys_reset_n => rstn, -- in std_logic;
in_data_in_stop => host_stop_in, -- out std_logic;
in_data_in_dval => host_val_in, -- in std_logic;
in_data_in_data => host_data_in, -- in std_logic_vector(63 downto 0);
out_data_out_stop => host_stop_out,-- in std_logic;
out_data_out_dval => host_val_out, -- out std_logic;
out_data_out_data => host_data_out -- out std_logic_vector(63 downto 0)
);
IDELAYCTRL_inst : IDELAYCTRL
port map (
RDY => open, -- 1-bit output: Ready output
REFCLK => clk200, -- 1-bit input: Reference clock input
RST => '0' -- 1-bit input: Active high reset input
);
-----------------------------------------------------------------------------------
-- Unit under test
-----------------------------------------------------------------------------------
sip_toggle_4lvds_inst0:
entity work.sip_toggle_4lvds
generic map (
global_start_addr_gen => x"0000000",
global_stop_addr_gen => x"0001FFF",
private_start_addr_gen => x"0000100",
private_stop_addr_gen => x"00001FF"
)
port map (
clk_clkin => clk_clkin,
rst_rstin => rst_rstin,
cmdclk_in_cmdclk => clk_cmd,
cmd_in_cmdin => in_cmd,
cmd_in_cmdin_val => in_cmd_val,
cmd_out_cmdout => out_cmd,
cmd_out_cmdout_val => out_cmd_val,
lvds_in_n => lvds_in_n,
lvds_in_p => lvds_in_p,
lvds_out_n => lvds_out_n,
lvds_out_p => lvds_out_p
);
lvds_in_n(0) <= sysclk_n;
lvds_in_p(0) <= sysclk_p;
lvds_in_n(1) <= sysclk_n;
lvds_in_p(1) <= sysclk_p;
--***********************************************************************************
end architecture Behavioral;
--***********************************************************************************
|
-----LIBRARIES-----
library ieee;
use ieee.std_logic_1164.all;
-----ENTITY-----
entity SevenSegCase is
port (
-- Inputs, outputs, inouts go here...
bin : in std_logic_vector(3 downto 0);
seg : out std_logic_vector(6 downto 0)
);
end entity;
-----Architecture-----
architecture Decode of SevenSegCase is
-- declare signals, components here...
begin
-- architecture body...
process(bin)
begin
case(bin) is
when "0000" => seg <= "1000000"; --0
when "0001" => seg <= "1111001"; --1
when "0010" => seg <= "0100100"; --2
when "0011" => seg <= "0110000"; --3
when "0100" => seg <= "0011001"; --4
when "0101" => seg <= "0010010"; --5
when "0110" => seg <= "0000010"; --6
when "0111" => seg <= "1111000"; --7
when "1000" => seg <= "0000000"; --8
when "1001" => seg <= "0011000"; --9
when "1010" => seg <= "0001000"; --A
when "1011" => seg <= "0000011"; --b
when "1100" => seg <= "1000110"; --C
when "1101" => seg <= "0100001"; --d
when "1110" => seg <= "0000110"; --E
when "1111" => seg <= "0001110"; --F
when others => seg <= "1111111";
end case;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_243 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_243;
architecture augh of sub_243 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_243 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_243;
architecture augh of sub_243 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2626.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02626ent IS
END c13s03b01x00p02n01i02626ent;
ARCHITECTURE c13s03b01x00p02n01i02626arch OF c13s03b01x00p02n01i02626ent IS
BEGIN
TESTING: PROCESS
variable k[k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02626 - Identifier can not contain '['."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02626arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2626.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02626ent IS
END c13s03b01x00p02n01i02626ent;
ARCHITECTURE c13s03b01x00p02n01i02626arch OF c13s03b01x00p02n01i02626ent IS
BEGIN
TESTING: PROCESS
variable k[k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02626 - Identifier can not contain '['."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02626arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2626.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02626ent IS
END c13s03b01x00p02n01i02626ent;
ARCHITECTURE c13s03b01x00p02n01i02626arch OF c13s03b01x00p02n01i02626ent IS
BEGIN
TESTING: PROCESS
variable k[k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02626 - Identifier can not contain '['."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02626arch;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity notch_filter is
port ( terminal input, output, vdd, vss, gnd : electrical );
end entity notch_filter;
----------------------------------------------------------------
architecture opamp_based of notch_filter is
component simple_opamp is
port ( terminal plus_in, minus_in, output, vdd, vss, gnd : electrical );
end component simple_opamp;
-- ...
terminal opamp1_in, opamp1_out, opamp2_in, -- ...
-- not in book
other_terminal
-- end not in book
: electrical;
begin
opamp1 : component simple_opamp
port map ( plus_in => gnd, minus_in => opamp1_in, output => opamp1_out,
vdd => vdd, vss => vss, gnd => gnd );
opamp2 : component simple_opamp
port map ( plus_in => gnd, minus_in => opamp2_in, output => output,
vdd => vdd, vss => vss, gnd => gnd );
-- other component instances
-- ...
end architecture opamp_based;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity notch_filter is
port ( terminal input, output, vdd, vss, gnd : electrical );
end entity notch_filter;
----------------------------------------------------------------
architecture opamp_based of notch_filter is
component simple_opamp is
port ( terminal plus_in, minus_in, output, vdd, vss, gnd : electrical );
end component simple_opamp;
-- ...
terminal opamp1_in, opamp1_out, opamp2_in, -- ...
-- not in book
other_terminal
-- end not in book
: electrical;
begin
opamp1 : component simple_opamp
port map ( plus_in => gnd, minus_in => opamp1_in, output => opamp1_out,
vdd => vdd, vss => vss, gnd => gnd );
opamp2 : component simple_opamp
port map ( plus_in => gnd, minus_in => opamp2_in, output => output,
vdd => vdd, vss => vss, gnd => gnd );
-- other component instances
-- ...
end architecture opamp_based;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity notch_filter is
port ( terminal input, output, vdd, vss, gnd : electrical );
end entity notch_filter;
----------------------------------------------------------------
architecture opamp_based of notch_filter is
component simple_opamp is
port ( terminal plus_in, minus_in, output, vdd, vss, gnd : electrical );
end component simple_opamp;
-- ...
terminal opamp1_in, opamp1_out, opamp2_in, -- ...
-- not in book
other_terminal
-- end not in book
: electrical;
begin
opamp1 : component simple_opamp
port map ( plus_in => gnd, minus_in => opamp1_in, output => opamp1_out,
vdd => vdd, vss => vss, gnd => gnd );
opamp2 : component simple_opamp
port map ( plus_in => gnd, minus_in => opamp2_in, output => output,
vdd => vdd, vss => vss, gnd => gnd );
-- other component instances
-- ...
end architecture opamp_based;
|
use work.pkg.all;
use work.all;
entity repro is
end repro;
architecture behav of repro is
component comp is
end component;
begin
c : comp;
end behav;
|
use work.pkg.all;
use work.all;
entity repro is
end repro;
architecture behav of repro is
component comp is
end component;
begin
c : comp;
end behav;
|
entity sub is
end entity;
architecture test of sub is
type rec is record
x : integer;
end record;
constant c : rec := (x => 2);
signal ss : rec := c;
function add1(x : integer) return integer is
begin
return x + 1;
end function;
begin
process is
variable r : rec := c;
begin
r.x := add1(ss.x);
assert r.x = 3;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity record9 is
end entity;
architecture test of record9 is
type rec is record
x : bit_vector(1 to 3);
end record;
constant c : rec := (x => "101");
signal s : rec := c;
begin
uut: entity work.sub;
s.x <= "111";
process is
begin
assert s = c;
wait for 1 ns;
assert s = (x => "111");
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_spi_master_v1_0_S00_AXI is
generic (
-- Users to add parameters here
SPI_DATA_WIDTH : integer := 8;
SPI_CLK_DIV : integer := 100;
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 1
);
port (
-- Users to add ports here
spi_mosi : out std_logic;
spi_miso : in std_logic;
spi_ss : out std_logic;
spi_sclk : out std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end axi_spi_master_v1_0_S00_AXI;
architecture arch_imp of axi_spi_master_v1_0_S00_AXI is
-- Components
component word2byte is
generic (
DATA_WIDTH : integer
);
port (
clk_i : in std_logic;
en_i : in std_logic;
rstn_i : in std_logic;
shift_cnt_i : in std_logic_vector(2 downto 0);
send_i : in std_logic;
data_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
busy_o : out std_logic;
done_o : out std_logic;
shift_o : out std_logic_vector(7 downto 0);
ss_o : out std_logic
) ;
end component;
component byte2word is
generic (
DATA_WIDTH : integer
);
port (
clk_i : in std_logic;
en_i : in std_logic;
rstn_i : in std_logic;
shift_cnt_i : in std_logic_vector(2 downto 0);
shift_i : in std_logic_vector(7 downto 0);
done_o : out std_logic;
data_o : out std_logic_vector(DATA_WIDTH-1 downto 0)
) ;
end component;
component spi_master is
generic(
DATA_WIDTH : integer;
CLK_DIV : integer -- input clock divider to generate output serial clock; o_sclk frequency = i_clk/(2*CLK_DIV)
);
port(
--Out port
o_sclk : out std_logic := '1';
o_mosi : out std_logic := '1';
o_ss : out std_logic := '1';
o_tx_rx_busy : out std_logic := '0';
o_tx_rx_end : out std_logic := '0';
o_data_rx : out std_logic_vector(DATA_WIDTH-1 downto 0) := (others=>'0');
--In port
i_miso : in std_logic := '0';
i_data_tx : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others=>'0'); -- data to send
--Control
i_clk : in std_logic := '0';
i_reset : in std_logic := '0';
i_tx_rx_start : in std_logic := '0' -- Start TX
);
end component;
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Packet logic
signal packet_byte_cnt : std_logic_vector(2 downto 0) := "100";
-- SPI interface signals
signal spi_tx_rx_start : std_logic := '0';
signal spi_tx_rx_busy : std_logic := '0';
signal spi_tx_rx_done : std_logic := '0';
signal spi_tx_byte : std_logic_vector(SPI_DATA_WIDTH-1 downto 0);
signal spi_rx_byte : std_logic_vector(SPI_DATA_WIDTH-1 downto 0);
-- PISO SIPO converters interface signals
signal p2s_load : std_logic := '0';
signal p2s_send : std_logic := '0';
signal p2s_busy : std_logic := '0';
signal p2s_ss : std_logic := '0';
signal p2s_done : std_logic := '0';
signal s2p_en : std_logic := '0';
signal s2p_done : std_logic := '0';
-- Registers
signal slv_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_wdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
wr_addr_valid: process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
wr_addr_latch: process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
wr_data_valid: process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and p2s_busy='0' and spi_tx_rx_busy='0') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
slv_wdata <= S_AXI_WDATA;
case S_AXI_WSTRB is
when "0001"=>
packet_byte_cnt <= "001";
when "0011"=>
packet_byte_cnt <= "010";
when "0111"=>
packet_byte_cnt <= "011";
when "1111"=>
packet_byte_cnt <= "100";
when others=>
packet_byte_cnt <= "100";
end case;
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
wr_response: process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
rd_addr_valid: process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1' and s2p_done='1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
rd_response: process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
axi_rdata <= slv_rdata;
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Add user logic here
start_interface: process(S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
p2s_load <= '0';
else
if (p2s_load='0' and p2s_busy='0') and ((axi_bvalid='1') or (S_AXI_ARVALID='1')) then
p2s_load <= '1';
else
p2s_load <= '0';
end if;
end if;
end if;
end process;
p2s_send <= not(spi_tx_rx_busy) and not(spi_tx_rx_start);
s2p_en <= spi_tx_rx_done;
spi_tx_rx_start <= not(p2s_ss);
word2byte_inst: word2byte
generic map(
DATA_WIDTH => C_S_AXI_DATA_WIDTH
)
port map(
clk_i => S_AXI_ACLK,
en_i => p2s_load,
rstn_i => S_AXI_ARESETN,
shift_cnt_i => packet_byte_cnt,
send_i => p2s_send,
busy_o => p2s_busy,
data_i => slv_wdata,
shift_o => spi_tx_byte,
ss_o => p2s_ss
);
byte2word_inst: byte2word
generic map(
DATA_WIDTH => C_S_AXI_DATA_WIDTH
)
port map(
clk_i => S_AXI_ACLK,
en_i => s2p_en,
rstn_i => S_AXI_ARESETN,
shift_cnt_i => packet_byte_cnt,
shift_i => spi_rx_byte,
done_o => s2p_done,
data_o => slv_rdata
);
spi_master_inst: spi_master
generic map(
DATA_WIDTH => SPI_DATA_WIDTH,
CLK_DIV => SPI_CLK_DIV
)
port map(
--Out port
o_sclk => spi_sclk,
o_mosi => spi_mosi,
o_ss => spi_ss,
o_tx_rx_busy => spi_tx_rx_busy,
o_tx_rx_end => spi_tx_rx_done,
o_data_rx => spi_rx_byte,
--In port
i_miso => spi_miso,
i_data_tx => spi_tx_byte,
--Control
i_clk => S_AXI_ACLK,
i_reset => S_AXI_ARESETN,
i_tx_rx_start => spi_tx_rx_start
);
-- User logic ends
end arch_imp;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_spi_master_v1_0_S00_AXI is
generic (
-- Users to add parameters here
SPI_DATA_WIDTH : integer := 8;
SPI_CLK_DIV : integer := 100;
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 1
);
port (
-- Users to add ports here
spi_mosi : out std_logic;
spi_miso : in std_logic;
spi_ss : out std_logic;
spi_sclk : out std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end axi_spi_master_v1_0_S00_AXI;
architecture arch_imp of axi_spi_master_v1_0_S00_AXI is
-- Components
component word2byte is
generic (
DATA_WIDTH : integer
);
port (
clk_i : in std_logic;
en_i : in std_logic;
rstn_i : in std_logic;
shift_cnt_i : in std_logic_vector(2 downto 0);
send_i : in std_logic;
data_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
busy_o : out std_logic;
done_o : out std_logic;
shift_o : out std_logic_vector(7 downto 0);
ss_o : out std_logic
) ;
end component;
component byte2word is
generic (
DATA_WIDTH : integer
);
port (
clk_i : in std_logic;
en_i : in std_logic;
rstn_i : in std_logic;
shift_cnt_i : in std_logic_vector(2 downto 0);
shift_i : in std_logic_vector(7 downto 0);
done_o : out std_logic;
data_o : out std_logic_vector(DATA_WIDTH-1 downto 0)
) ;
end component;
component spi_master is
generic(
DATA_WIDTH : integer;
CLK_DIV : integer -- input clock divider to generate output serial clock; o_sclk frequency = i_clk/(2*CLK_DIV)
);
port(
--Out port
o_sclk : out std_logic := '1';
o_mosi : out std_logic := '1';
o_ss : out std_logic := '1';
o_tx_rx_busy : out std_logic := '0';
o_tx_rx_end : out std_logic := '0';
o_data_rx : out std_logic_vector(DATA_WIDTH-1 downto 0) := (others=>'0');
--In port
i_miso : in std_logic := '0';
i_data_tx : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others=>'0'); -- data to send
--Control
i_clk : in std_logic := '0';
i_reset : in std_logic := '0';
i_tx_rx_start : in std_logic := '0' -- Start TX
);
end component;
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Packet logic
signal packet_byte_cnt : std_logic_vector(2 downto 0) := "100";
-- SPI interface signals
signal spi_tx_rx_start : std_logic := '0';
signal spi_tx_rx_busy : std_logic := '0';
signal spi_tx_rx_done : std_logic := '0';
signal spi_tx_byte : std_logic_vector(SPI_DATA_WIDTH-1 downto 0);
signal spi_rx_byte : std_logic_vector(SPI_DATA_WIDTH-1 downto 0);
-- PISO SIPO converters interface signals
signal p2s_load : std_logic := '0';
signal p2s_send : std_logic := '0';
signal p2s_busy : std_logic := '0';
signal p2s_ss : std_logic := '0';
signal p2s_done : std_logic := '0';
signal s2p_en : std_logic := '0';
signal s2p_done : std_logic := '0';
-- Registers
signal slv_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_wdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
wr_addr_valid: process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
wr_addr_latch: process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
wr_data_valid: process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and p2s_busy='0' and spi_tx_rx_busy='0') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
slv_wdata <= S_AXI_WDATA;
case S_AXI_WSTRB is
when "0001"=>
packet_byte_cnt <= "001";
when "0011"=>
packet_byte_cnt <= "010";
when "0111"=>
packet_byte_cnt <= "011";
when "1111"=>
packet_byte_cnt <= "100";
when others=>
packet_byte_cnt <= "100";
end case;
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
wr_response: process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
rd_addr_valid: process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1' and s2p_done='1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
rd_response: process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
axi_rdata <= slv_rdata;
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Add user logic here
start_interface: process(S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
p2s_load <= '0';
else
if (p2s_load='0' and p2s_busy='0') and ((axi_bvalid='1') or (S_AXI_ARVALID='1')) then
p2s_load <= '1';
else
p2s_load <= '0';
end if;
end if;
end if;
end process;
p2s_send <= not(spi_tx_rx_busy) and not(spi_tx_rx_start);
s2p_en <= spi_tx_rx_done;
spi_tx_rx_start <= not(p2s_ss);
word2byte_inst: word2byte
generic map(
DATA_WIDTH => C_S_AXI_DATA_WIDTH
)
port map(
clk_i => S_AXI_ACLK,
en_i => p2s_load,
rstn_i => S_AXI_ARESETN,
shift_cnt_i => packet_byte_cnt,
send_i => p2s_send,
busy_o => p2s_busy,
data_i => slv_wdata,
shift_o => spi_tx_byte,
ss_o => p2s_ss
);
byte2word_inst: byte2word
generic map(
DATA_WIDTH => C_S_AXI_DATA_WIDTH
)
port map(
clk_i => S_AXI_ACLK,
en_i => s2p_en,
rstn_i => S_AXI_ARESETN,
shift_cnt_i => packet_byte_cnt,
shift_i => spi_rx_byte,
done_o => s2p_done,
data_o => slv_rdata
);
spi_master_inst: spi_master
generic map(
DATA_WIDTH => SPI_DATA_WIDTH,
CLK_DIV => SPI_CLK_DIV
)
port map(
--Out port
o_sclk => spi_sclk,
o_mosi => spi_mosi,
o_ss => spi_ss,
o_tx_rx_busy => spi_tx_rx_busy,
o_tx_rx_end => spi_tx_rx_done,
o_data_rx => spi_rx_byte,
--In port
i_miso => spi_miso,
i_data_tx => spi_tx_byte,
--Control
i_clk => S_AXI_ACLK,
i_reset => S_AXI_ARESETN,
i_tx_rx_start => spi_tx_rx_start
);
-- User logic ends
end arch_imp;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_spi_master_v1_0_S00_AXI is
generic (
-- Users to add parameters here
SPI_DATA_WIDTH : integer := 8;
SPI_CLK_DIV : integer := 100;
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 1
);
port (
-- Users to add ports here
spi_mosi : out std_logic;
spi_miso : in std_logic;
spi_ss : out std_logic;
spi_sclk : out std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end axi_spi_master_v1_0_S00_AXI;
architecture arch_imp of axi_spi_master_v1_0_S00_AXI is
-- Components
component word2byte is
generic (
DATA_WIDTH : integer
);
port (
clk_i : in std_logic;
en_i : in std_logic;
rstn_i : in std_logic;
shift_cnt_i : in std_logic_vector(2 downto 0);
send_i : in std_logic;
data_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
busy_o : out std_logic;
done_o : out std_logic;
shift_o : out std_logic_vector(7 downto 0);
ss_o : out std_logic
) ;
end component;
component byte2word is
generic (
DATA_WIDTH : integer
);
port (
clk_i : in std_logic;
en_i : in std_logic;
rstn_i : in std_logic;
shift_cnt_i : in std_logic_vector(2 downto 0);
shift_i : in std_logic_vector(7 downto 0);
done_o : out std_logic;
data_o : out std_logic_vector(DATA_WIDTH-1 downto 0)
) ;
end component;
component spi_master is
generic(
DATA_WIDTH : integer;
CLK_DIV : integer -- input clock divider to generate output serial clock; o_sclk frequency = i_clk/(2*CLK_DIV)
);
port(
--Out port
o_sclk : out std_logic := '1';
o_mosi : out std_logic := '1';
o_ss : out std_logic := '1';
o_tx_rx_busy : out std_logic := '0';
o_tx_rx_end : out std_logic := '0';
o_data_rx : out std_logic_vector(DATA_WIDTH-1 downto 0) := (others=>'0');
--In port
i_miso : in std_logic := '0';
i_data_tx : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others=>'0'); -- data to send
--Control
i_clk : in std_logic := '0';
i_reset : in std_logic := '0';
i_tx_rx_start : in std_logic := '0' -- Start TX
);
end component;
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Packet logic
signal packet_byte_cnt : std_logic_vector(2 downto 0) := "100";
-- SPI interface signals
signal spi_tx_rx_start : std_logic := '0';
signal spi_tx_rx_busy : std_logic := '0';
signal spi_tx_rx_done : std_logic := '0';
signal spi_tx_byte : std_logic_vector(SPI_DATA_WIDTH-1 downto 0);
signal spi_rx_byte : std_logic_vector(SPI_DATA_WIDTH-1 downto 0);
-- PISO SIPO converters interface signals
signal p2s_load : std_logic := '0';
signal p2s_send : std_logic := '0';
signal p2s_busy : std_logic := '0';
signal p2s_ss : std_logic := '0';
signal p2s_done : std_logic := '0';
signal s2p_en : std_logic := '0';
signal s2p_done : std_logic := '0';
-- Registers
signal slv_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_wdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
wr_addr_valid: process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
wr_addr_latch: process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
wr_data_valid: process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and p2s_busy='0' and spi_tx_rx_busy='0') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
slv_wdata <= S_AXI_WDATA;
case S_AXI_WSTRB is
when "0001"=>
packet_byte_cnt <= "001";
when "0011"=>
packet_byte_cnt <= "010";
when "0111"=>
packet_byte_cnt <= "011";
when "1111"=>
packet_byte_cnt <= "100";
when others=>
packet_byte_cnt <= "100";
end case;
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
wr_response: process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
rd_addr_valid: process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1' and s2p_done='1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
rd_response: process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
axi_rdata <= slv_rdata;
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Add user logic here
start_interface: process(S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
p2s_load <= '0';
else
if (p2s_load='0' and p2s_busy='0') and ((axi_bvalid='1') or (S_AXI_ARVALID='1')) then
p2s_load <= '1';
else
p2s_load <= '0';
end if;
end if;
end if;
end process;
p2s_send <= not(spi_tx_rx_busy) and not(spi_tx_rx_start);
s2p_en <= spi_tx_rx_done;
spi_tx_rx_start <= not(p2s_ss);
word2byte_inst: word2byte
generic map(
DATA_WIDTH => C_S_AXI_DATA_WIDTH
)
port map(
clk_i => S_AXI_ACLK,
en_i => p2s_load,
rstn_i => S_AXI_ARESETN,
shift_cnt_i => packet_byte_cnt,
send_i => p2s_send,
busy_o => p2s_busy,
data_i => slv_wdata,
shift_o => spi_tx_byte,
ss_o => p2s_ss
);
byte2word_inst: byte2word
generic map(
DATA_WIDTH => C_S_AXI_DATA_WIDTH
)
port map(
clk_i => S_AXI_ACLK,
en_i => s2p_en,
rstn_i => S_AXI_ARESETN,
shift_cnt_i => packet_byte_cnt,
shift_i => spi_rx_byte,
done_o => s2p_done,
data_o => slv_rdata
);
spi_master_inst: spi_master
generic map(
DATA_WIDTH => SPI_DATA_WIDTH,
CLK_DIV => SPI_CLK_DIV
)
port map(
--Out port
o_sclk => spi_sclk,
o_mosi => spi_mosi,
o_ss => spi_ss,
o_tx_rx_busy => spi_tx_rx_busy,
o_tx_rx_end => spi_tx_rx_done,
o_data_rx => spi_rx_byte,
--In port
i_miso => spi_miso,
i_data_tx => spi_tx_byte,
--Control
i_clk => S_AXI_ACLK,
i_reset => S_AXI_ARESETN,
i_tx_rx_start => spi_tx_rx_start
);
-- User logic ends
end arch_imp;
|
entity ODD_PARITY_TB is
end;
library ieee;
use ieee.std_logic_1164.all;
architecture
OP_TB_ARCH of ODD_PARITY_TB is
component Parity_Generator1
port(
input_stream : in input;
clk : in std_logic;
parity : out bit);
end component;
signal input_stream : input;
signal clk :std_logic;
signal parity :bit ;
begin
U1: Parity_Generator1 port map (input_stream, clk, parity => parity );
input1 : process (clk)
begin
if clk <= 'U' then clk <= '0' after 1 ns;
else clk <= not clk after 1 ns;
end if;
end process;
input2: process (input_stream)
begin
input_stream <= "10100110" after 1 ns,
"01111100" after 2 ns;
end process;
end OP_TB_ARCH;
configuration cfg_op of ODD_PARITY_TB is
for OP_TB_ARCH
end for;
end cfg_op; |
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.math_real.all ;
use ieee.math_complex.all ;
architecture hosted_bladerf of bladerf is
component nios_system is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
dac_MISO : in std_logic := 'X'; -- MISO
dac_MOSI : out std_logic; -- MOSI
dac_SCLK : out std_logic; -- SCLK
dac_SS_n : out std_logic; -- SS_n
spi_MISO : in std_logic := 'X'; -- MISO
spi_MOSI : out std_logic; -- MOSI
spi_SCLK : out std_logic; -- SCLK
spi_SS_n : out std_logic; -- SS_n
uart_rxd : in std_logic;
uart_txd : out std_logic;
oc_i2c_scl_pad_o : out std_logic;
oc_i2c_scl_padoen_o : out std_logic;
oc_i2c_sda_pad_i : in std_logic;
oc_i2c_sda_pad_o : out std_logic;
oc_i2c_sda_padoen_o : out std_logic;
oc_i2c_arst_i : in std_logic;
oc_i2c_scl_pad_i : in std_logic;
gpio_export : out std_logic_vector(31 downto 0)
);
end component nios_system;
signal ramp_out : signed(11 downto 0) ;
signal lms_tx_clock : std_logic ;
signal \38.4MHz\ : std_logic ;
signal \76.8MHz\ : std_logic ;
signal \76.8MHz@90\ : std_logic ;
signal rs232_clock : std_logic ;
signal rs232_locked : std_logic ;
signal sfifo_din : std_logic_vector(7 downto 0) ;
signal sfifo_dout : std_logic_vector(7 downto 0) ;
signal sfifo_full : std_logic ;
signal sfifo_empty : std_logic ;
signal sfifo_re : std_logic ;
signal sfifo_we : std_logic ;
attribute noprune : boolean ;
signal rx_i : signed(11 downto 0) ;
signal rx_q : signed(11 downto 0) ;
attribute noprune of rx_i : signal is true ;
attribute noprune of rx_q : signal is true ;
signal fsk_real : signed(15 downto 0) ;
signal fsk_imag : signed(15 downto 0) ;
signal fsk_valid : std_logic ;
attribute noprune of fsk_real : signal is true ;
attribute noprune of fsk_imag : signal is true ;
signal nios_uart_txd : std_logic ;
signal nios_uart_rxd : std_logic ;
signal nios_gpio : std_logic_vector(31 downto 0) ;
attribute noprune of nios_uart_txd : signal is true ;
attribute noprune of nios_uart_rxd : signal is true ;
signal demod_in_i : signed(15 downto 0) ;
signal demod_in_q : signed(15 downto 0) ;
signal demod_ssd : signed(15 downto 0) ;
signal demod_valid : std_logic ;
signal qualifier : unsigned(5 downto 0) := (others =>'0') ;
attribute noprune of qualifier : signal is true ;
signal i2c_scl_in : std_logic ;
signal i2c_scl_out : std_logic ;
signal i2c_scl_oen : std_logic ;
signal i2c_sda_in : std_logic ;
signal i2c_sda_out : std_logic ;
signal i2c_sda_oen : std_logic ;
signal gpif_var : std_logic_vector(31 downto 0) ;
signal rf_fifo_rcnt : signed(12 downto 0);
--- RF rx FIFO signals
signal rf_rx_fifo_full : std_logic;
signal rf_rx_fifo_clr : std_logic;
signal rf_rx_fifo_read : std_logic;
signal rf_rx_fifo_cnt : std_logic_vector(9 downto 0);
signal rf_rx_fifo_q : std_logic_vector(31 downto 0);
signal rf_rx_fifo_w : std_logic;
signal rf_rx_fifo_enough : std_logic;
signal rf_rx_fifo_sample : signed(31 downto 0) ;
signal rf_rx_last_sample : signed(11 downto 0) ;
signal rf_rx_sample_idx : signed(2 downto 0) ;
--- end RF rx FIFO
--- RF tx FIFO signals
signal rf_tx_fifo_clr : std_logic;
signal rf_tx_fifo_data : std_logic_vector(31 downto 0);
signal rf_tx_fifo_read : std_logic;
signal rf_tx_fifo_w : std_logic;
signal rf_tx_fifo_q : std_logic_vector(31 downto 0);
signal rf_tx_fifo_empty : std_logic;
signal rf_tx_fifo_cnt : std_logic_vector(11 downto 0);
signal rf_tx_fifo_enough : std_logic;
signal rf_tx_fifo_data_iq_r : std_logic_vector(31 downto 0);
signal rf_tx_fifo_data_iq_rr : std_logic_vector(31 downto 0);
signal tx_data : std_logic_vector(11 downto 0) ;
--- end RF tx FIFO
signal debug_line_speed : std_logic;
signal debug_line_speed_rx, debug_line_speed_tx : std_logic;
signal can_perform_rx, should_perform_rx : std_logic;
signal can_perform_tx, should_perform_tx : std_logic;
signal rf_tx_next_dma : std_logic;
signal rf_tx_dma_2 : std_logic;
signal rf_tx_dma_3 : std_logic;
signal rf_rx_next_dma : std_logic;
signal rf_rx_dma_0 : std_logic;
signal rf_rx_dma_1 : std_logic;
signal sys_rst : std_logic;
signal dma_idle : std_logic;
signal dma_rdy_0 : std_logic;
signal dma_rdy_1 : std_logic;
signal dma_rdy_2 : std_logic;
signal dma_rdy_3 : std_logic;
type dma_event is (DE_TX, DE_RX);
signal dma_last_event : dma_event;
signal dma_rx_en : std_logic;
signal dma_tx_en : std_logic;
signal dma_rx_en_r : std_logic;
signal dma_rx_en_rr : std_logic;
signal dma_tx_en_r : std_logic;
signal dma_tx_en_rr : std_logic;
signal rf_tx_en_iq_r : std_logic;
signal rf_tx_en_iq_rr : std_logic;
signal tx_iq_idx : std_logic;
signal gpif_buf_sz : unsigned(10 downto 0);
signal gpif_buf_sz_cond : signed(12 downto 0);
signal gpif_buf_sel_r, gpif_buf_sel_rr : std_logic;
type m_state is (M_IDLE, M_IDLE_RD, M_IDLE_WR, M_IDLE_WR_1, M_IDLE_WR_2, M_IDLE_WR_3, M_READ, M_WRITE);
signal current_state : m_state;
attribute keep: boolean;
attribute keep of dma_idle: signal is true;
attribute keep of rf_rx_fifo_cnt: signal is true;
attribute keep of rf_rx_fifo_enough: signal is true;
attribute keep of dma_rdy_0: signal is true;
attribute keep of dma_rdy_1: signal is true;
attribute keep of rf_rx_next_dma: signal is true;
attribute keep of sys_rst: signal is true;
attribute keep of rf_rx_fifo_full: signal is true;
attribute keep of rf_rx_fifo_clr: signal is true;
--attribute keep of lms_rx_clock: signal is true;
attribute keep of can_perform_rx: signal is true;
attribute keep of can_perform_tx: signal is true;
attribute keep of should_perform_rx: signal is true;
attribute keep of should_perform_tx: signal is true;
attribute keep of rf_tx_fifo_enough: signal is true;
attribute keep of rf_tx_fifo_cnt: signal is true;
attribute keep of rf_tx_fifo_w: signal is true;
attribute keep of \38.4MHz\: signal is true;
attribute keep of \76.8MHz\: signal is true;
attribute keep of rf_tx_fifo_data_iq_rr: signal is true;
attribute keep of rf_tx_fifo_q: signal is true;
attribute noprune of dma_idle: signal is true;
attribute noprune of rf_rx_fifo_cnt: signal is true;
attribute noprune of rf_rx_fifo_enough: signal is true;
attribute noprune of dma_rdy_0: signal is true;
attribute noprune of dma_rdy_1: signal is true;
attribute noprune of rf_rx_next_dma: signal is true;
attribute noprune of sys_rst: signal is true;
attribute noprune of rf_rx_fifo_full: signal is true;
attribute noprune of rf_rx_fifo_clr: signal is true;
--attribute noprune of lms_rx_clock: signal is true;
attribute noprune of \38.4MHz\: signal is true;
attribute noprune of \76.8MHz\: signal is true;
attribute noprune of rf_tx_fifo_data_iq_rr: signal is true;
attribute noprune of rf_tx_fifo_q: signal is true;
attribute noprune of can_perform_rx: signal is true;
attribute noprune of can_perform_tx: signal is true;
attribute noprune of should_perform_rx: signal is true;
attribute noprune of should_perform_tx: signal is true;
attribute noprune of rf_tx_fifo_enough: signal is true;
attribute noprune of rf_tx_fifo_cnt: signal is true;
attribute noprune of rf_tx_fifo_w: signal is true;
begin
qualifier <= qualifier + 1 when rising_edge(\38.4MHz\) ;
rx_i <= lms_rx_data when rising_edge(lms_rx_clock_out) and lms_rx_iq_select = '0' ;
rx_q <= lms_rx_data when rising_edge(lms_rx_clock_out) and lms_rx_iq_select = '1' ;
U_pll : entity work.pll
port map (
inclk0 => c4_tx_clock,
c0 => \76.8MHz\,
c1 => \38.4MHz\,
c2 => \76.8MHz@90\,
locked => open
) ;
U_serial_pll : entity work.serial_pll
port map (
inclk0 => c4_clock,
c0 => rs232_clock,
locked => rs232_locked
) ;
fx3_ctl(0) <= rf_rx_dma_0;
fx3_ctl(1) <= rf_rx_dma_1;
fx3_ctl(2) <= rf_tx_dma_2;
fx3_ctl(3) <= rf_tx_dma_3;
dma_rx_en <= fx3_ctl(4);
dma_tx_en <= fx3_ctl(5);
dma_idle <= fx3_ctl(6);
sys_rst <= fx3_ctl(7);
dma_rdy_0 <= fx3_ctl(8);
dma_rdy_1 <= fx3_ctl(12); -- 9 is DCLK, it is somewhat lost
dma_rdy_2 <= fx3_ctl(10);
dma_rdy_3 <= fx3_ctl(11);
gpif_buf_sz <= to_unsigned(512, gpif_buf_sz'length) when gpif_buf_sel_rr = '0' else to_unsigned(256, gpif_buf_sz'length);
gpif_buf_sz_cond <= to_signed(511, gpif_buf_sz_cond'length) when gpif_buf_sel_rr = '0' else to_signed(255, gpif_buf_sz_cond'length);
rf_tx_fifo : entity work.tx_fifo
port map (
aclr => rf_tx_fifo_clr,
data => rf_tx_fifo_data,
rdclk => c4_tx_clock,
rdreq => dma_tx_en_rr and lms_tx_iq_select,
wrclk => fx3_pclk,
wrreq => rf_tx_fifo_w,
q => rf_tx_fifo_q,
rdempty => rf_tx_fifo_empty,
rdfull => open,
rdusedw => open,
wrempty => open,
wrfull => open,
wrusedw => rf_tx_fifo_cnt
);
rf_tx_fifo_enough <= '1' when (unsigned(rf_tx_fifo_cnt) <= ((2**(rf_tx_fifo_cnt'length-1)) - gpif_buf_sz)) else '0';
rf_tx_fifo_clr <= '1' when (sys_rst = '1') else '0';
rf_tx_fifo_w <= '1' when (current_state = M_WRITE) else '0';
process(sys_rst, c4_tx_clock)
begin
if( sys_rst = '1' ) then
dma_tx_en_r <= '0';
dma_tx_en_rr <= '0';
elsif( rising_edge(c4_tx_clock) ) then
dma_tx_en_r <= dma_tx_en;
dma_tx_en_rr <= dma_tx_en_r;
end if;
end process;
process(sys_rst, c4_tx_clock)
begin
if( sys_rst = '1' ) then
rf_tx_en_iq_r <= '0';
rf_tx_en_iq_rr <= '0';
rf_tx_fifo_data_iq_r <= (others => '0');
rf_tx_fifo_data_iq_rr <= (others => '0');
elsif( rising_edge(c4_tx_clock) ) then
rf_tx_en_iq_r <= not rf_tx_fifo_empty;
rf_tx_en_iq_rr <= rf_tx_en_iq_r;
rf_tx_fifo_data_iq_r <= rf_tx_fifo_q;
rf_tx_fifo_data_iq_rr <= rf_tx_fifo_data_iq_r;
end if;
end process;
process(sys_rst, c4_tx_clock)
begin
if( sys_rst = '1' ) then
tx_iq_idx <= '0';
elsif( rising_edge(c4_tx_clock) ) then
if (rf_tx_en_iq_rr = '1') then
tx_iq_idx <= not tx_iq_idx;
elsif (rf_tx_en_iq_rr = '0') then
tx_iq_idx <= '0';
end if;
end if;
end process;
tx_data <= rf_tx_fifo_data_iq_rr(27 downto 16) when tx_iq_idx = '1' else rf_tx_fifo_data_iq_rr(11 downto 0);
lms_tx_data <= signed(tx_data) when rf_tx_en_iq_rr = '1' else (others => '0');
rf_rx_fifo : entity work.rx_fifo
port map (
aclr => rf_rx_fifo_clr,
data => std_logic_vector(rf_rx_fifo_sample),
rdclk => fx3_pclk,
rdreq => rf_rx_fifo_read,
wrclk => lms_rx_clock_out,
wrreq => rf_rx_fifo_w,
q => rf_rx_fifo_q,
rdempty => open,
rdfull => open,
rdusedw => rf_rx_fifo_cnt,
wrempty => open,
wrfull => rf_rx_fifo_full,
wrusedw => open
);
rf_rx_fifo_enough <= '1' when (unsigned(rf_rx_fifo_cnt) >= gpif_buf_sz ) else '0';
rf_rx_fifo_clr <= '1' when (sys_rst = '1' or (rf_rx_fifo_full = '1' and signed(rf_rx_sample_idx) = 0)) else '0';
rf_rx_fifo_read <= '1' when (current_state = M_READ) else '0';
process(all)
begin
if( current_state = M_READ or current_state = M_IDLE_RD) then
fx3_gpif <= rf_rx_fifo_q;
elsif( current_state = M_WRITE or current_state = M_IDLE_WR) then
rf_tx_fifo_data <= fx3_gpif;
else
fx3_gpif <= (others => 'Z');
end if;
end process;
--todo: readd debug_line_speed handling
--fx3_gpif <= rf_rx_fifo_q when (debug_line_speed_rx = '0' and (current_state = M_READ or current_state = M_IDLE_RD)) else (others => 'Z');
--gpif_var <= fx3_gpif;
--process(all)
--begin
-- if (debug_line_speed_rx = '0' and (current_state = M_READ or current_state = M_IDLE_RD)) then
-- fx3_gpif <= rf_rx_fifo_q;
-- elsif (current_state = M_WRITE ) then
-- gpif_var <= fx3_gpif;
-- else
-- fx3_gpif <= (others => 'Z');
-- end if;
--end process;
debug_line_speed <= '0';
debug_line_speed_rx <= debug_line_speed;
debug_line_speed_tx <= debug_line_speed;
can_perform_rx <= '1' when (dma_rx_en = '1' and (
debug_line_speed_rx = '1' or
(rf_rx_fifo_enough = '1' and (
(dma_rdy_0 = '0' and rf_rx_next_dma = '0') or
(dma_rdy_1 = '0' and rf_rx_next_dma = '1')
)
)
)) else '0';
can_perform_tx <= '1' when (dma_tx_en = '1' and (
debug_line_speed_tx = '1' or
(rf_tx_fifo_enough = '1' and (
(dma_rdy_2 = '0' and rf_tx_next_dma = '0') or
(dma_rdy_3 = '0' and rf_tx_next_dma = '1')
)
)
)) else '0';
should_perform_rx <= '1' when ( can_perform_rx = '1' and (can_perform_tx = '0' or (can_perform_tx = '1' and dma_last_event = DE_TX ) ) ) else '0';
should_perform_tx <= '1' when ( can_perform_tx = '1' and (can_perform_rx = '0' or (can_perform_rx = '1' and dma_last_event = DE_RX ) ) ) else '0';
process(sys_rst, fx3_pclk)
begin
if( sys_rst = '1' ) then
current_state <= M_IDLE;
rf_tx_next_dma <= '1';
rf_rx_next_dma <= '0';
rf_rx_dma_0 <= '0';
rf_rx_dma_1 <= '0';
rf_tx_dma_2 <= '0';
rf_tx_dma_3 <= '0';
rf_fifo_rcnt <= (others => '0');
dma_last_event <= DE_TX;
elsif( rising_edge(fx3_pclk) ) then
case current_state is
when M_IDLE =>
if( dma_idle = '1' ) then
if( should_perform_rx = '1' ) then
rf_fifo_rcnt <= gpif_buf_sz_cond;
if ( rf_rx_next_dma = '0') then
rf_rx_dma_0 <= '1';
rf_rx_dma_1 <= '0';
else
rf_rx_dma_0 <= '0';
rf_rx_dma_1 <= '1';
end if;
-- DMA thread 0 is always next
--rf_rx_next_dma <= not rf_rx_next_dma;
rf_rx_next_dma <= '0';
current_state <= M_IDLE_RD;
-- set this to DE_RX unconditionally so that no hangs occur
-- if there is an problem with RX
dma_last_event <= DE_RX;
elsif( should_perform_tx = '1' ) then
rf_fifo_rcnt <= gpif_buf_sz_cond;
if( rf_tx_next_dma = '0') then
rf_tx_dma_2 <= '1';
rf_tx_dma_3 <= '0';
else
rf_tx_dma_2 <= '0';
rf_tx_dma_3 <= '1';
end if;
--DMA thread 3 is always next
--rf_tx_next_dma <= not rf_tx_next_dma;
rf_tx_next_dma <= '1';
current_state <= M_IDLE_WR;
dma_last_event <= DE_TX;
end if;
end if;
when M_IDLE_WR =>
current_state <= M_IDLE_WR_1;
when M_IDLE_WR_1 =>
current_state <= M_IDLE_WR_2;
when M_IDLE_WR_2 =>
current_state <= M_IDLE_WR_3;
when M_IDLE_WR_3 =>
current_state <= M_WRITE;
when M_WRITE =>
rf_tx_dma_2 <= '0';
rf_tx_dma_3 <= '0';
if( unsigned(rf_fifo_rcnt) /= 0 ) then
rf_fifo_rcnt <= rf_fifo_rcnt - 1;
else
current_state <= M_IDLE;
end if;
when M_IDLE_RD =>
current_state <= M_READ;
when M_READ =>
rf_rx_dma_0 <= '0';
rf_rx_dma_1 <= '0';
if( unsigned(rf_fifo_rcnt) /= 0 ) then
rf_fifo_rcnt <= rf_fifo_rcnt - 1;
else
current_state <= M_IDLE;
end if;
end case;
end if;
end process;
-- | Byte 1 | Byte 2 Byte 3 Byte 4 |
-- | 0 0 0 0 0 0 0 0 | 0 0 0 0 1 1 1 1 | 1 1 1 1 1 1 1 1 | 2 2 2 2 2 2 2 2 |
-- | 2 2 2 2 3 3 3 3 | 3 3 3 3 3 3 3 3 | 4 4 4 4 4 4 4 4 | 4 4 4 4 5 5 5 5 |
-- | 5 5 5 5 5 5 5 5 | 6 6 6 6 6 6 6 6 | 6 6 6 6 7 7 7 7 | 7 7 7 7 7 7 7 7 |
--
-- Eight 12bit samples have to be collected to align data being fed into the FIFO
-- Enough data exists at the end of RF samples #2, #5, #7 to write data to the FIFO
process(sys_rst, lms_rx_clock_out)
begin
if( sys_rst = '1' ) then
dma_rx_en_r <= '0';
dma_rx_en_rr <= '0';
elsif( rising_edge(lms_rx_clock_out) ) then
dma_rx_en_r <= dma_rx_en;
dma_rx_en_rr <= dma_rx_en_r;
end if;
end process;
process(sys_rst, lms_rx_clock_out)
begin
if( sys_rst = '1' ) then
rf_rx_fifo_sample <= (others => '0');
rf_rx_last_sample <= (others => '0');
rf_rx_sample_idx <= (others => '0');
rf_rx_fifo_w <= '0';
elsif( rising_edge(lms_rx_clock_out) ) then
if( dma_rx_en_rr = '1' ) then
--rf_rx_last_sample <= upcnter;
--if( unsigned(rf_rx_sample_idx) = 2 or unsigned(rf_rx_sample_idx) = 5 or unsigned(rf_rx_sample_idx) = 7) then
-- rf_rx_fifo_w <= '1';
--else
-- rf_rx_fifo_w <= '0';
--end if;
rf_rx_fifo_sample(31 downto 0) <= "0011" & rx_q & "1011" & rx_i;
rf_rx_fifo_w <= not lms_rx_iq_select;
--if ( rf_rx_sample_idx(0) = '0')
--rf_rx_fifo_sample(11 downto 0) <= upcnter;
--if( unsigned(rf_rx_sample_idx) = 0 ) then
-- rf_rx_fifo_sample(11 downto 0) <= upcnter(11 downto 0);
--elsif( unsigned(rf_rx_sample_idx) = 1 ) then
-- rf_rx_fifo_sample(23 downto 12) <= upcnter(11 downto 0);
--elsif( unsigned(rf_rx_sample_idx) = 2 ) then
-- rf_rx_fifo_sample(31 downto 24) <= upcnter(7 downto 0);
--elsif( unsigned(rf_rx_sample_idx) = 3 ) then
-- rf_rx_fifo_sample(15 downto 0) <= upcnter(11 downto 0) & rf_rx_last_sample(11 downto 8);
--elsif( unsigned(rf_rx_sample_idx) = 4 ) then
-- rf_rx_fifo_sample(27 downto 16) <= upcnter(11 downto 0);
--elsif( unsigned(rf_rx_sample_idx) = 5 ) then
-- rf_rx_fifo_sample(31 downto 28) <= upcnter(3 downto 0);
--elsif( unsigned(rf_rx_sample_idx) = 6 ) then
-- rf_rx_fifo_sample(19 downto 0) <= upcnter(11 downto 0) & rf_rx_last_sample(11 downto 4);
--elsif( unsigned(rf_rx_sample_idx) = 7 ) then
-- rf_rx_fifo_sample(31 downto 20) <= upcnter(11 downto 0);
--end if;
rf_rx_sample_idx <= rf_rx_sample_idx + 1;
end if ;
end if ;
end process;
U_nios_system : nios_system
port map (
clk_clk => c4_clock,
reset_reset_n => '1',
dac_MISO => dac_sdo,
dac_MOSI => dac_sdi,
dac_SCLK => dac_sclk,
dac_SS_n => dac_csx,
spi_MISO => lms_sdo,
spi_MOSI => lms_sdio,
spi_SCLK => lms_sclk,
spi_SS_n => lms_sen,
uart_rxd => fx3_uart_txd,
uart_txd => fx3_uart_rxd,
gpio_export => nios_gpio,
oc_i2c_scl_pad_o => i2c_scl_out,
oc_i2c_scl_padoen_o => i2c_scl_oen,
oc_i2c_sda_pad_i => i2c_sda_in,
oc_i2c_sda_pad_o => i2c_sda_out,
oc_i2c_sda_padoen_o => i2c_sda_oen,
oc_i2c_arst_i => '0',
oc_i2c_scl_pad_i => i2c_scl_in
) ;
si_scl <= i2c_scl_out when i2c_scl_oen = '0' else 'Z' ;
si_sda <= i2c_sda_out when i2c_sda_oen = '0' else 'Z' ;
i2c_scl_in <= si_scl ;
i2c_sda_in <= si_sda ;
nios_uart_rxd <= demod_ssd(demod_ssd'high) when demod_valid = '1' ;
toggle_led1 : process(fx3_pclk)
variable count : natural range 0 to 100_000_000 := 100_000_000 ;
begin
if( rising_edge(fx3_pclk) ) then
count := count - 1 ;
if( count = 0 ) then
count := 100_000_00 ;
led(1) <= not led(1) ;
end if ;
end if ;
end process ;
toggle_led2 : process(lms_rx_clock_out)
variable count : natural range 0 to 38_400_00 := 38_400_00 ;
begin
if( rising_edge(lms_rx_clock_out) ) then
count := count - 1 ;
if( count = 0 ) then
count := 38_400_00 ;
led(2) <= not led(2) ;
end if ;
end if ;
end process ;
toggle_led3 : process(lms_rx_iq_select)
variable count : natural range 0 to 19_200_000 := 19_200_000 ;
begin
if( rising_edge(lms_rx_iq_select) ) then
count := count - 1 ;
if( count = 0 ) then
count := 19_200_000 ;
led(3) <= not led(3) ;
end if ;
end if ;
end process ;
lms_reset <= nios_gpio(0) ;
lms_rx_enable <= nios_gpio(1) ;
lms_tx_enable <= nios_gpio(2) ;
lms_tx_iq_select <= not lms_tx_iq_select when rising_edge(c4_tx_clock) ;
lms_tx_v <= nios_gpio(4 downto 3) ;
lms_rx_v <= nios_gpio(6 downto 5) ;
exp_spi_clock <= '0' ;
exp_spi_mosi <= '0' ;
exp_gpio <= (others =>'Z') ;
process(fx3_pclk)
begin
if( rising_edge(fx3_pclk)) then
gpif_buf_sel_r <= nios_gpio(7);
gpif_buf_sel_rr <= gpif_buf_sel_r;
end if;
end process;
end architecture ; -- arch
|
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram_dq_PHASE_m.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY ram_dq_PHASE_m IS
PORT
(
address : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END ram_dq_PHASE_m;
ARCHITECTURE SYN OF ram_dq_phase_m IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=PH_m",
lpm_type => "altsyncram",
numwords_a => 32,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 5,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "PH_m"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "5"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=PH_m"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL "address[4..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_m.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_m.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_m.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_m.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_m_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram_dq_PHASE_m.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY ram_dq_PHASE_m IS
PORT
(
address : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END ram_dq_PHASE_m;
ARCHITECTURE SYN OF ram_dq_phase_m IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=PH_m",
lpm_type => "altsyncram",
numwords_a => 32,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 5,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "PH_m"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "5"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=PH_m"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL "address[4..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_m.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_m.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_m.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_m.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_m_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk512_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(2 downto 0)
);
end dk512_rnd;
architecture behaviour of dk512_rnd is
constant state_1: std_logic_vector(3 downto 0) := "1101";
constant state_8: std_logic_vector(3 downto 0) := "0010";
constant state_2: std_logic_vector(3 downto 0) := "1011";
constant state_4: std_logic_vector(3 downto 0) := "1110";
constant state_3: std_logic_vector(3 downto 0) := "1111";
constant state_5: std_logic_vector(3 downto 0) := "0001";
constant state_6: std_logic_vector(3 downto 0) := "0110";
constant state_13: std_logic_vector(3 downto 0) := "0000";
constant state_7: std_logic_vector(3 downto 0) := "1010";
constant state_9: std_logic_vector(3 downto 0) := "1000";
constant state_10: std_logic_vector(3 downto 0) := "0100";
constant state_11: std_logic_vector(3 downto 0) := "1001";
constant state_12: std_logic_vector(3 downto 0) := "1100";
constant state_14: std_logic_vector(3 downto 0) := "0011";
constant state_15: std_logic_vector(3 downto 0) := "0111";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "---";
case current_state is
when state_1 =>
if std_match(input, "0") then next_state <= state_8; output <= "000";
elsif std_match(input, "1") then next_state <= state_9; output <= "000";
end if;
when state_2 =>
if std_match(input, "0") then next_state <= state_4; output <= "000";
elsif std_match(input, "1") then next_state <= state_3; output <= "000";
end if;
when state_3 =>
if std_match(input, "0") then next_state <= state_5; output <= "000";
elsif std_match(input, "1") then next_state <= state_6; output <= "000";
end if;
when state_4 =>
if std_match(input, "0") then next_state <= state_8; output <= "000";
elsif std_match(input, "1") then next_state <= state_11; output <= "000";
end if;
when state_5 =>
if std_match(input, "0") then next_state <= state_8; output <= "000";
elsif std_match(input, "1") then next_state <= state_12; output <= "000";
end if;
when state_6 =>
if std_match(input, "0") then next_state <= state_13; output <= "000";
elsif std_match(input, "1") then next_state <= state_14; output <= "000";
end if;
when state_7 =>
if std_match(input, "0") then next_state <= state_4; output <= "000";
elsif std_match(input, "1") then next_state <= state_15; output <= "000";
end if;
when state_8 =>
if std_match(input, "0") then next_state <= state_1; output <= "001";
elsif std_match(input, "1") then next_state <= state_2; output <= "001";
end if;
when state_9 =>
if std_match(input, "0") then next_state <= state_4; output <= "000";
elsif std_match(input, "1") then next_state <= state_3; output <= "001";
end if;
when state_10 =>
if std_match(input, "0") then next_state <= state_1; output <= "010";
elsif std_match(input, "1") then next_state <= state_2; output <= "010";
end if;
when state_11 =>
if std_match(input, "0") then next_state <= state_3; output <= "010";
elsif std_match(input, "1") then next_state <= state_4; output <= "010";
end if;
when state_12 =>
if std_match(input, "0") then next_state <= state_4; output <= "100";
elsif std_match(input, "1") then next_state <= state_3; output <= "001";
end if;
when state_13 =>
if std_match(input, "0") then next_state <= state_5; output <= "100";
elsif std_match(input, "1") then next_state <= state_6; output <= "100";
end if;
when state_14 =>
if std_match(input, "0") then next_state <= state_3; output <= "100";
elsif std_match(input, "1") then next_state <= state_7; output <= "100";
end if;
when state_15 =>
if std_match(input, "0") then next_state <= state_4; output <= "000";
elsif std_match(input, "1") then next_state <= state_6; output <= "000";
end if;
when others => next_state <= "----"; output <= "---";
end case;
end process;
end behaviour;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:12:10 03/30/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Poject_Lab01/ProjLab1/DCCTL_tb.vhd
-- Project Name: ProjLab1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: DC_CTL
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY DCCTL_tb IS
END DCCTL_tb;
ARCHITECTURE behavior OF DCCTL_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT DC_CTL
PORT(
CLK : IN std_logic;
RA : IN std_logic_vector(3 downto 0);
RB : IN std_logic_vector(3 downto 0);
RA0 : IN std_logic_vector(3 downto 0);
RA1 : IN std_logic_vector(3 downto 0);
RA2 : IN std_logic_vector(3 downto 0);
-- RB0 : IN std_logic_vector(3 downto 0);
-- RB1 : IN std_logic_vector(3 downto 0);
-- RB2 : IN std_logic_vector(3 downto 0);
OPC : IN std_logic_vector(3 downto 0);
OP1_SEL : OUT std_logic_vector(1 downto 0);
OP2_SEL : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RA : std_logic_vector(3 downto 0) := (others => '0');
signal RB : std_logic_vector(3 downto 0) := (others => '0');
signal RA0 : std_logic_vector(3 downto 0) := (others => '1');
signal RA1 : std_logic_vector(3 downto 0) := (others => '1');
signal RA2 : std_logic_vector(3 downto 0) := (others => '1');
-- signal RB0 : std_logic_vector(3 downto 0) := (others => '0');
-- signal RB1 : std_logic_vector(3 downto 0) := (others => '0');
-- signal RB2 : std_logic_vector(3 downto 0) := (others => '0');
signal OPC : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal OP1_SEL : std_logic_vector(1 downto 0);
signal OP2_SEL : std_logic_vector(1 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: DC_CTL PORT MAP (
CLK => CLK,
RA => RA,
RB => RB,
RA0 => RA0,
RA1 => RA1,
RA2 => RA2,
-- RB0 => RB0,
-- RB1 => RB1,
-- RB2 => RB2,
OPC => OPC,
OP1_SEL => OP1_SEL,
OP2_SEL => OP2_SEL
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for CLK_period*10;
wait for CLK_period/2;
RA2 <= "0000";
wait for CLK_period;
RA1 <= "0000";
wait for CLK_period;
RA0 <= "0000";
wait for CLK_period*10;
-- insert stimulus here
wait;
end process;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:12:10 03/30/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Poject_Lab01/ProjLab1/DCCTL_tb.vhd
-- Project Name: ProjLab1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: DC_CTL
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY DCCTL_tb IS
END DCCTL_tb;
ARCHITECTURE behavior OF DCCTL_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT DC_CTL
PORT(
CLK : IN std_logic;
RA : IN std_logic_vector(3 downto 0);
RB : IN std_logic_vector(3 downto 0);
RA0 : IN std_logic_vector(3 downto 0);
RA1 : IN std_logic_vector(3 downto 0);
RA2 : IN std_logic_vector(3 downto 0);
-- RB0 : IN std_logic_vector(3 downto 0);
-- RB1 : IN std_logic_vector(3 downto 0);
-- RB2 : IN std_logic_vector(3 downto 0);
OPC : IN std_logic_vector(3 downto 0);
OP1_SEL : OUT std_logic_vector(1 downto 0);
OP2_SEL : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RA : std_logic_vector(3 downto 0) := (others => '0');
signal RB : std_logic_vector(3 downto 0) := (others => '0');
signal RA0 : std_logic_vector(3 downto 0) := (others => '1');
signal RA1 : std_logic_vector(3 downto 0) := (others => '1');
signal RA2 : std_logic_vector(3 downto 0) := (others => '1');
-- signal RB0 : std_logic_vector(3 downto 0) := (others => '0');
-- signal RB1 : std_logic_vector(3 downto 0) := (others => '0');
-- signal RB2 : std_logic_vector(3 downto 0) := (others => '0');
signal OPC : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal OP1_SEL : std_logic_vector(1 downto 0);
signal OP2_SEL : std_logic_vector(1 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: DC_CTL PORT MAP (
CLK => CLK,
RA => RA,
RB => RB,
RA0 => RA0,
RA1 => RA1,
RA2 => RA2,
-- RB0 => RB0,
-- RB1 => RB1,
-- RB2 => RB2,
OPC => OPC,
OP1_SEL => OP1_SEL,
OP2_SEL => OP2_SEL
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for CLK_period*10;
wait for CLK_period/2;
RA2 <= "0000";
wait for CLK_period;
RA1 <= "0000";
wait for CLK_period;
RA0 <= "0000";
wait for CLK_period*10;
-- insert stimulus here
wait;
end process;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:12:10 03/30/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Poject_Lab01/ProjLab1/DCCTL_tb.vhd
-- Project Name: ProjLab1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: DC_CTL
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY DCCTL_tb IS
END DCCTL_tb;
ARCHITECTURE behavior OF DCCTL_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT DC_CTL
PORT(
CLK : IN std_logic;
RA : IN std_logic_vector(3 downto 0);
RB : IN std_logic_vector(3 downto 0);
RA0 : IN std_logic_vector(3 downto 0);
RA1 : IN std_logic_vector(3 downto 0);
RA2 : IN std_logic_vector(3 downto 0);
-- RB0 : IN std_logic_vector(3 downto 0);
-- RB1 : IN std_logic_vector(3 downto 0);
-- RB2 : IN std_logic_vector(3 downto 0);
OPC : IN std_logic_vector(3 downto 0);
OP1_SEL : OUT std_logic_vector(1 downto 0);
OP2_SEL : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RA : std_logic_vector(3 downto 0) := (others => '0');
signal RB : std_logic_vector(3 downto 0) := (others => '0');
signal RA0 : std_logic_vector(3 downto 0) := (others => '1');
signal RA1 : std_logic_vector(3 downto 0) := (others => '1');
signal RA2 : std_logic_vector(3 downto 0) := (others => '1');
-- signal RB0 : std_logic_vector(3 downto 0) := (others => '0');
-- signal RB1 : std_logic_vector(3 downto 0) := (others => '0');
-- signal RB2 : std_logic_vector(3 downto 0) := (others => '0');
signal OPC : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal OP1_SEL : std_logic_vector(1 downto 0);
signal OP2_SEL : std_logic_vector(1 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: DC_CTL PORT MAP (
CLK => CLK,
RA => RA,
RB => RB,
RA0 => RA0,
RA1 => RA1,
RA2 => RA2,
-- RB0 => RB0,
-- RB1 => RB1,
-- RB2 => RB2,
OPC => OPC,
OP1_SEL => OP1_SEL,
OP2_SEL => OP2_SEL
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for CLK_period*10;
wait for CLK_period/2;
RA2 <= "0000";
wait for CLK_period;
RA1 <= "0000";
wait for CLK_period;
RA0 <= "0000";
wait for CLK_period*10;
-- insert stimulus here
wait;
end process;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:12:10 03/30/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Poject_Lab01/ProjLab1/DCCTL_tb.vhd
-- Project Name: ProjLab1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: DC_CTL
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY DCCTL_tb IS
END DCCTL_tb;
ARCHITECTURE behavior OF DCCTL_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT DC_CTL
PORT(
CLK : IN std_logic;
RA : IN std_logic_vector(3 downto 0);
RB : IN std_logic_vector(3 downto 0);
RA0 : IN std_logic_vector(3 downto 0);
RA1 : IN std_logic_vector(3 downto 0);
RA2 : IN std_logic_vector(3 downto 0);
-- RB0 : IN std_logic_vector(3 downto 0);
-- RB1 : IN std_logic_vector(3 downto 0);
-- RB2 : IN std_logic_vector(3 downto 0);
OPC : IN std_logic_vector(3 downto 0);
OP1_SEL : OUT std_logic_vector(1 downto 0);
OP2_SEL : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RA : std_logic_vector(3 downto 0) := (others => '0');
signal RB : std_logic_vector(3 downto 0) := (others => '0');
signal RA0 : std_logic_vector(3 downto 0) := (others => '1');
signal RA1 : std_logic_vector(3 downto 0) := (others => '1');
signal RA2 : std_logic_vector(3 downto 0) := (others => '1');
-- signal RB0 : std_logic_vector(3 downto 0) := (others => '0');
-- signal RB1 : std_logic_vector(3 downto 0) := (others => '0');
-- signal RB2 : std_logic_vector(3 downto 0) := (others => '0');
signal OPC : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal OP1_SEL : std_logic_vector(1 downto 0);
signal OP2_SEL : std_logic_vector(1 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: DC_CTL PORT MAP (
CLK => CLK,
RA => RA,
RB => RB,
RA0 => RA0,
RA1 => RA1,
RA2 => RA2,
-- RB0 => RB0,
-- RB1 => RB1,
-- RB2 => RB2,
OPC => OPC,
OP1_SEL => OP1_SEL,
OP2_SEL => OP2_SEL
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for CLK_period*10;
wait for CLK_period/2;
RA2 <= "0000";
wait for CLK_period;
RA1 <= "0000";
wait for CLK_period;
RA0 <= "0000";
wait for CLK_period*10;
-- insert stimulus here
wait;
end process;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:12:10 03/30/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Poject_Lab01/ProjLab1/DCCTL_tb.vhd
-- Project Name: ProjLab1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: DC_CTL
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY DCCTL_tb IS
END DCCTL_tb;
ARCHITECTURE behavior OF DCCTL_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT DC_CTL
PORT(
CLK : IN std_logic;
RA : IN std_logic_vector(3 downto 0);
RB : IN std_logic_vector(3 downto 0);
RA0 : IN std_logic_vector(3 downto 0);
RA1 : IN std_logic_vector(3 downto 0);
RA2 : IN std_logic_vector(3 downto 0);
-- RB0 : IN std_logic_vector(3 downto 0);
-- RB1 : IN std_logic_vector(3 downto 0);
-- RB2 : IN std_logic_vector(3 downto 0);
OPC : IN std_logic_vector(3 downto 0);
OP1_SEL : OUT std_logic_vector(1 downto 0);
OP2_SEL : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RA : std_logic_vector(3 downto 0) := (others => '0');
signal RB : std_logic_vector(3 downto 0) := (others => '0');
signal RA0 : std_logic_vector(3 downto 0) := (others => '1');
signal RA1 : std_logic_vector(3 downto 0) := (others => '1');
signal RA2 : std_logic_vector(3 downto 0) := (others => '1');
-- signal RB0 : std_logic_vector(3 downto 0) := (others => '0');
-- signal RB1 : std_logic_vector(3 downto 0) := (others => '0');
-- signal RB2 : std_logic_vector(3 downto 0) := (others => '0');
signal OPC : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal OP1_SEL : std_logic_vector(1 downto 0);
signal OP2_SEL : std_logic_vector(1 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: DC_CTL PORT MAP (
CLK => CLK,
RA => RA,
RB => RB,
RA0 => RA0,
RA1 => RA1,
RA2 => RA2,
-- RB0 => RB0,
-- RB1 => RB1,
-- RB2 => RB2,
OPC => OPC,
OP1_SEL => OP1_SEL,
OP2_SEL => OP2_SEL
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for CLK_period*10;
wait for CLK_period/2;
RA2 <= "0000";
wait for CLK_period;
RA1 <= "0000";
wait for CLK_period;
RA0 <= "0000";
wait for CLK_period*10;
-- insert stimulus here
wait;
end process;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:12:10 03/30/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Poject_Lab01/ProjLab1/DCCTL_tb.vhd
-- Project Name: ProjLab1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: DC_CTL
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY DCCTL_tb IS
END DCCTL_tb;
ARCHITECTURE behavior OF DCCTL_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT DC_CTL
PORT(
CLK : IN std_logic;
RA : IN std_logic_vector(3 downto 0);
RB : IN std_logic_vector(3 downto 0);
RA0 : IN std_logic_vector(3 downto 0);
RA1 : IN std_logic_vector(3 downto 0);
RA2 : IN std_logic_vector(3 downto 0);
-- RB0 : IN std_logic_vector(3 downto 0);
-- RB1 : IN std_logic_vector(3 downto 0);
-- RB2 : IN std_logic_vector(3 downto 0);
OPC : IN std_logic_vector(3 downto 0);
OP1_SEL : OUT std_logic_vector(1 downto 0);
OP2_SEL : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RA : std_logic_vector(3 downto 0) := (others => '0');
signal RB : std_logic_vector(3 downto 0) := (others => '0');
signal RA0 : std_logic_vector(3 downto 0) := (others => '1');
signal RA1 : std_logic_vector(3 downto 0) := (others => '1');
signal RA2 : std_logic_vector(3 downto 0) := (others => '1');
-- signal RB0 : std_logic_vector(3 downto 0) := (others => '0');
-- signal RB1 : std_logic_vector(3 downto 0) := (others => '0');
-- signal RB2 : std_logic_vector(3 downto 0) := (others => '0');
signal OPC : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal OP1_SEL : std_logic_vector(1 downto 0);
signal OP2_SEL : std_logic_vector(1 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: DC_CTL PORT MAP (
CLK => CLK,
RA => RA,
RB => RB,
RA0 => RA0,
RA1 => RA1,
RA2 => RA2,
-- RB0 => RB0,
-- RB1 => RB1,
-- RB2 => RB2,
OPC => OPC,
OP1_SEL => OP1_SEL,
OP2_SEL => OP2_SEL
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for CLK_period*10;
wait for CLK_period/2;
RA2 <= "0000";
wait for CLK_period;
RA1 <= "0000";
wait for CLK_period;
RA0 <= "0000";
wait for CLK_period*10;
-- insert stimulus here
wait;
end process;
END;
|
entity sub1 is
port (i : bit_vector);
end;
entity notype1 is
end;
architecture behav of notype1 is
type counter_t is array (2 downto 0) of (31 downto 0);
signal cnts : counter_t;
begin
i : entity work.sub1
port map (i => cnts (0));
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fullAdder is (
Port(
A: in STD_LOGIC;
B: in STD_LOGIC;
Cin: in STD_LOGIC;
Cout: out STD_LOGIC;
Sum: out STD_LOGIC;
);
);
architecture FullAdderBehavioral is
begin
Sum <= A xor B xor Cin;
Cout <= (A and B) or (Cin and (A xor B));
end FullAdderBehavioral;
|
-------------------------------------------------------------------------------
--! @file atomicmodifyRtl.vhd
--
--! @brief Atomic modify
--
--! @details This component is used to modify memory atomically.
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2015
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity atomicmodify is
generic (
--! Address bus width
gAddrWidth : natural := 16
);
port (
--! Clock
iClk : in std_logic;
--! Reset
iRst : in std_logic;
-- Memory Mapped master
--! MM master address
oMst_address : out std_logic_vector(gAddrWidth-1 downto 0);
--! MM master byteenable
oMst_byteenable : out std_logic_vector(3 downto 0);
--! MM master read
oMst_read : out std_logic;
--! MM master readdata
iMst_readdata : in std_logic_vector(31 downto 0);
--! MM master write
oMst_write : out std_logic;
--! MM master writedata
oMst_writedata : out std_logic_vector(31 downto 0);
--! MM master waitrequest
iMst_waitrequest : in std_logic;
--! MM master lock
oMst_lock : out std_logic;
-- Memory mapped slave
--! Address
iSlv_address : in std_logic_vector(gAddrWidth-1 downto 2);
--! Byteenable
iSlv_byteenable : in std_logic_vector(3 downto 0);
--! Read strobe
iSlv_read : in std_logic;
--! Readdata
oSlv_readdata : out std_logic_vector(31 downto 0);
--! Write strobe
iSlv_write : in std_logic;
--! Writedata
iSlv_writedata : in std_logic_vector(31 downto 0);
--! Waitrequest
oSlv_waitrequest : out std_logic
);
end atomicmodify;
architecture rtl of atomicmodify is
-- fsm
type tFsm is (
sIdle,
sRead,
sWrite
);
-- register set
type tReg is record
address : std_logic_vector(oMst_address'range);
byteenable : std_logic_vector(oMst_byteenable'range);
writedata : std_logic_vector(oMst_writedata'range);
readdata : std_logic_vector(iMst_readdata'range);
fsm : tFsm;
ack : std_logic;
end record;
constant cRegInit : tReg := (
address => (others => cInactivated),
byteenable => (others => cInactivated),
writedata => (others => cInactivated),
readdata => (others => cInactivated),
fsm => sIdle,
ack => cInactivated
);
-- register set signals
signal reg : tReg;
signal reg_next : tReg;
begin
--! The process describes the register set.
regClk : process(iClk)
begin
if rising_edge(iClk) then
if iRst = cActivated then
reg <= cRegInit;
else
reg <= reg_next;
end if;
end if;
end process;
--! The process describes the combinational circuit for the register set.
regComb : process (
reg,
iSlv_address, iSlv_byteenable, iSlv_read, iSlv_write, iSlv_writedata,
iMst_waitrequest, iMst_readdata
)
begin
-- default
reg_next <= reg;
reg_next.ack <= cInactivated;
-- Master access state machine
case reg.fsm is
when sIdle =>
if iSlv_write = cActivated and reg.ack = cInactivated then
reg_next.fsm <= sRead;
reg_next.address <= iSlv_address & "00";
reg_next.byteenable <= iSlv_byteenable;
reg_next.writedata <= iSlv_writedata;
elsif iSlv_read = cActivated and reg.ack = cInactivated then
reg_next.fsm <= sIdle;
reg_next.ack <= cActivated;
end if;
when sRead =>
if iMst_waitrequest = cInactivated then
reg_next.fsm <= sWrite;
reg_next.readdata <= iMst_readdata;
end if;
when sWrite =>
if iMst_waitrequest = cInactivated then
reg_next.fsm <= sIdle;
reg_next.ack <= cActivated;
end if;
end case;
end process;
-- Assign ports to register set
oSlv_waitrequest <= not reg.ack;
oSlv_readdata <= reg.readdata;
oMst_address <= reg.address;
oMst_byteenable <= reg.byteenable;
oMst_writedata <= reg.writedata;
oMst_read <= cActivated when reg.fsm = sRead else cInactivated;
oMst_write <= cActivated when reg.fsm = sWrite else cInactivated;
oMst_lock <= cActivated when reg.fsm = sRead else cInactivated;
end rtl;
|
-- NEED RESULT: ARCH00075.P1: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075.P2: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075.P3: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075.P4: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075.P5: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075.P6: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075.P7: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075.P8: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075.P9: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075.P10: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075.P11: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075.P12: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075.P13: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075.P14: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075.P15: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075.P16: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075.P17: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: P17: Transport transactions entirely completed passed
-- NEED RESULT: P16: Transport transactions entirely completed passed
-- NEED RESULT: P15: Transport transactions entirely completed passed
-- NEED RESULT: P14: Transport transactions entirely completed passed
-- NEED RESULT: P13: Transport transactions entirely completed passed
-- NEED RESULT: P12: Transport transactions entirely completed passed
-- NEED RESULT: P11: Transport transactions entirely completed passed
-- NEED RESULT: P10: Transport transactions entirely completed passed
-- NEED RESULT: P9: Transport transactions entirely completed passed
-- NEED RESULT: P8: Transport transactions entirely completed passed
-- NEED RESULT: P7: Transport transactions entirely completed passed
-- NEED RESULT: P6: Transport transactions entirely completed passed
-- NEED RESULT: P5: Transport transactions entirely completed passed
-- NEED RESULT: P4: Transport transactions entirely completed passed
-- NEED RESULT: P3: Transport transactions entirely completed passed
-- NEED RESULT: P2: Transport transactions entirely completed passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00075
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00075(ARCH00075)
-- ENT00075_Test_Bench(ARCH00075_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00075 is
port (
s_boolean : inout boolean
; s_bit : inout bit
; s_severity_level : inout severity_level
; s_character : inout character
; s_st_enum1 : inout st_enum1
; s_integer : inout integer
; s_st_int1 : inout st_int1
; s_time : inout time
; s_st_phys1 : inout st_phys1
; s_real : inout real
; s_st_real1 : inout st_real1
; s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
; s_st_arr1 : inout st_arr1
; s_st_arr2 : inout st_arr2
; s_st_arr3 : inout st_arr3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_boolean : chk_sig_type := -1 ;
signal chk_bit : chk_sig_type := -1 ;
signal chk_severity_level : chk_sig_type := -1 ;
signal chk_character : chk_sig_type := -1 ;
signal chk_st_enum1 : chk_sig_type := -1 ;
signal chk_integer : chk_sig_type := -1 ;
signal chk_st_int1 : chk_sig_type := -1 ;
signal chk_time : chk_sig_type := -1 ;
signal chk_st_phys1 : chk_sig_type := -1 ;
signal chk_real : chk_sig_type := -1 ;
signal chk_st_real1 : chk_sig_type := -1 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
signal chk_st_arr1 : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
signal chk_st_arr3 : chk_sig_type := -1 ;
--
end ENT00075 ;
--
architecture ARCH00075 of ENT00075 is
begin
PGEN_CHKP_1 :
process ( chk_boolean )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_boolean = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_boolean )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_boolean <= transport
c_boolean_2 after 10 ns,
c_boolean_1 after 20 ns ;
--
when 1
=> correct :=
s_boolean = c_boolean_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_boolean = c_boolean_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00075.P1" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_boolean <= transport
c_boolean_2 after 10 ns ,
c_boolean_1 after 20 ns ,
c_boolean_2 after 30 ns ,
c_boolean_1 after 40 ns ;
--
when 3
=> correct :=
s_boolean = c_boolean_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_boolean <= transport c_boolean_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_boolean = c_boolean_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00075" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00075" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00075" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_boolean <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_bit )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_bit = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_bit )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_bit <= transport
c_bit_2 after 10 ns,
c_bit_1 after 20 ns ;
--
when 1
=> correct :=
s_bit = c_bit_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_bit = c_bit_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00075.P2" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_bit <= transport
c_bit_2 after 10 ns ,
c_bit_1 after 20 ns ,
c_bit_2 after 30 ns ,
c_bit_1 after 40 ns ;
--
when 3
=> correct :=
s_bit = c_bit_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_bit <= transport c_bit_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_bit = c_bit_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00075" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00075" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00075" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_bit <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_severity_level )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_severity_level = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process ( s_severity_level )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_severity_level <= transport
c_severity_level_2 after 10 ns,
c_severity_level_1 after 20 ns ;
--
when 1
=> correct :=
s_severity_level = c_severity_level_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_severity_level = c_severity_level_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00075.P3" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_severity_level <= transport
c_severity_level_2 after 10 ns ,
c_severity_level_1 after 20 ns ,
c_severity_level_2 after 30 ns ,
c_severity_level_1 after 40 ns ;
--
when 3
=> correct :=
s_severity_level = c_severity_level_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_severity_level <= transport c_severity_level_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_severity_level = c_severity_level_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00075" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00075" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00075" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_severity_level <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P3 ;
--
PGEN_CHKP_4 :
process ( chk_character )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Transport transactions entirely completed",
chk_character = 4 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
P4 :
process ( s_character )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_character <= transport
c_character_2 after 10 ns,
c_character_1 after 20 ns ;
--
when 1
=> correct :=
s_character = c_character_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_character = c_character_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00075.P4" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_character <= transport
c_character_2 after 10 ns ,
c_character_1 after 20 ns ,
c_character_2 after 30 ns ,
c_character_1 after 40 ns ;
--
when 3
=> correct :=
s_character = c_character_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_character <= transport c_character_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_character = c_character_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00075" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00075" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00075" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_character <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P4 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Transport transactions entirely completed",
chk_st_enum1 = 4 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
P5 :
process ( s_st_enum1 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_enum1 <= transport
c_st_enum1_2 after 10 ns,
c_st_enum1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_enum1 = c_st_enum1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1 = c_st_enum1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00075.P5" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_enum1 <= transport
c_st_enum1_2 after 10 ns ,
c_st_enum1_1 after 20 ns ,
c_st_enum1_2 after 30 ns ,
c_st_enum1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_enum1 = c_st_enum1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_enum1 <= transport c_st_enum1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1 = c_st_enum1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00075" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00075" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00075" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_enum1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P5 ;
--
PGEN_CHKP_6 :
process ( chk_integer )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Transport transactions entirely completed",
chk_integer = 4 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
P6 :
process ( s_integer )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_integer <= transport
c_integer_2 after 10 ns,
c_integer_1 after 20 ns ;
--
when 1
=> correct :=
s_integer = c_integer_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_integer = c_integer_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00075.P6" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_integer <= transport
c_integer_2 after 10 ns ,
c_integer_1 after 20 ns ,
c_integer_2 after 30 ns ,
c_integer_1 after 40 ns ;
--
when 3
=> correct :=
s_integer = c_integer_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_integer <= transport c_integer_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_integer = c_integer_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00075" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00075" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00075" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_integer <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P6 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Transport transactions entirely completed",
chk_st_int1 = 4 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
P7 :
process ( s_st_int1 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_int1 <= transport
c_st_int1_2 after 10 ns,
c_st_int1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_int1 = c_st_int1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1 = c_st_int1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00075.P7" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_int1 <= transport
c_st_int1_2 after 10 ns ,
c_st_int1_1 after 20 ns ,
c_st_int1_2 after 30 ns ,
c_st_int1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_int1 = c_st_int1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_int1 <= transport c_st_int1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1 = c_st_int1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00075" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00075" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00075" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_int1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P7 ;
--
PGEN_CHKP_8 :
process ( chk_time )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Transport transactions entirely completed",
chk_time = 4 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
P8 :
process ( s_time )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_time <= transport
c_time_2 after 10 ns,
c_time_1 after 20 ns ;
--
when 1
=> correct :=
s_time = c_time_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_time = c_time_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00075.P8" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_time <= transport
c_time_2 after 10 ns ,
c_time_1 after 20 ns ,
c_time_2 after 30 ns ,
c_time_1 after 40 ns ;
--
when 3
=> correct :=
s_time = c_time_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_time <= transport c_time_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_time = c_time_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00075" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00075" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00075" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_time <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P8 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Transport transactions entirely completed",
chk_st_phys1 = 4 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
P9 :
process ( s_st_phys1 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_phys1 <= transport
c_st_phys1_2 after 10 ns,
c_st_phys1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_phys1 = c_st_phys1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1 = c_st_phys1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00075.P9" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_phys1 <= transport
c_st_phys1_2 after 10 ns ,
c_st_phys1_1 after 20 ns ,
c_st_phys1_2 after 30 ns ,
c_st_phys1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_phys1 = c_st_phys1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_phys1 <= transport c_st_phys1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1 = c_st_phys1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00075" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00075" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00075" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_phys1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P9 ;
--
PGEN_CHKP_10 :
process ( chk_real )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Transport transactions entirely completed",
chk_real = 4 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
P10 :
process ( s_real )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_real <= transport
c_real_2 after 10 ns,
c_real_1 after 20 ns ;
--
when 1
=> correct :=
s_real = c_real_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_real = c_real_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00075.P10" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_real <= transport
c_real_2 after 10 ns ,
c_real_1 after 20 ns ,
c_real_2 after 30 ns ,
c_real_1 after 40 ns ;
--
when 3
=> correct :=
s_real = c_real_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_real <= transport c_real_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_real = c_real_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00075" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00075" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00075" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_real <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P10 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Transport transactions entirely completed",
chk_st_real1 = 4 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
P11 :
process ( s_st_real1 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_real1 <= transport
c_st_real1_2 after 10 ns,
c_st_real1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_real1 = c_st_real1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1 = c_st_real1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00075.P11" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_real1 <= transport
c_st_real1_2 after 10 ns ,
c_st_real1_1 after 20 ns ,
c_st_real1_2 after 30 ns ,
c_st_real1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_real1 = c_st_real1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_real1 <= transport c_st_real1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1 = c_st_real1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00075" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00075" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00075" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P11 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Transport transactions entirely completed",
chk_st_rec1 = 4 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
P12 :
process ( s_st_rec1 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_rec1 <= transport
c_st_rec1_2 after 10 ns,
c_st_rec1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1 = c_st_rec1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1 = c_st_rec1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00075.P12" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec1 <= transport
c_st_rec1_2 after 10 ns ,
c_st_rec1_1 after 20 ns ,
c_st_rec1_2 after 30 ns ,
c_st_rec1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1 = c_st_rec1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1 <= transport c_st_rec1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1 = c_st_rec1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00075" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00075" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00075" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P12 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Transport transactions entirely completed",
chk_st_rec2 = 4 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
P13 :
process ( s_st_rec2 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_rec2 <= transport
c_st_rec2_2 after 10 ns,
c_st_rec2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2 = c_st_rec2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2 = c_st_rec2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00075.P13" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec2 <= transport
c_st_rec2_2 after 10 ns ,
c_st_rec2_1 after 20 ns ,
c_st_rec2_2 after 30 ns ,
c_st_rec2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2 = c_st_rec2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2 <= transport c_st_rec2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2 = c_st_rec2_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00075" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00075" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00075" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P13 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Transport transactions entirely completed",
chk_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
P14 :
process ( s_st_rec3 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_rec3 <= transport
c_st_rec3_2 after 10 ns,
c_st_rec3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3 = c_st_rec3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3 = c_st_rec3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00075.P14" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec3 <= transport
c_st_rec3_2 after 10 ns ,
c_st_rec3_1 after 20 ns ,
c_st_rec3_2 after 30 ns ,
c_st_rec3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3 = c_st_rec3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3 <= transport c_st_rec3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3 = c_st_rec3_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00075" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00075" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00075" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P14 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Transport transactions entirely completed",
chk_st_arr1 = 4 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
P15 :
process ( s_st_arr1 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_arr1 <= transport
c_st_arr1_2 after 10 ns,
c_st_arr1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr1 = c_st_arr1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1 = c_st_arr1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00075.P15" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr1 <= transport
c_st_arr1_2 after 10 ns ,
c_st_arr1_1 after 20 ns ,
c_st_arr1_2 after 30 ns ,
c_st_arr1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr1 = c_st_arr1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1 <= transport c_st_arr1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1 = c_st_arr1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00075" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00075" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00075" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P15 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Transport transactions entirely completed",
chk_st_arr2 = 4 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
P16 :
process ( s_st_arr2 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_arr2 <= transport
c_st_arr2_2 after 10 ns,
c_st_arr2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr2 = c_st_arr2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2 = c_st_arr2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00075.P16" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr2 <= transport
c_st_arr2_2 after 10 ns ,
c_st_arr2_1 after 20 ns ,
c_st_arr2_2 after 30 ns ,
c_st_arr2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr2 = c_st_arr2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr2 <= transport c_st_arr2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2 = c_st_arr2_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00075" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00075" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00075" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P16 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Transport transactions entirely completed",
chk_st_arr3 = 4 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
P17 :
process ( s_st_arr3 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_arr3 <= transport
c_st_arr3_2 after 10 ns,
c_st_arr3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr3 = c_st_arr3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3 = c_st_arr3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00075.P17" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr3 <= transport
c_st_arr3_2 after 10 ns ,
c_st_arr3_1 after 20 ns ,
c_st_arr3_2 after 30 ns ,
c_st_arr3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr3 = c_st_arr3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr3 <= transport c_st_arr3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3 = c_st_arr3_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00075" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00075" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00075" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P17 ;
--
--
end ARCH00075 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00075_Test_Bench is
signal s_boolean : boolean
:= c_boolean_1 ;
signal s_bit : bit
:= c_bit_1 ;
signal s_severity_level : severity_level
:= c_severity_level_1 ;
signal s_character : character
:= c_character_1 ;
signal s_st_enum1 : st_enum1
:= c_st_enum1_1 ;
signal s_integer : integer
:= c_integer_1 ;
signal s_st_int1 : st_int1
:= c_st_int1_1 ;
signal s_time : time
:= c_time_1 ;
signal s_st_phys1 : st_phys1
:= c_st_phys1_1 ;
signal s_real : real
:= c_real_1 ;
signal s_st_real1 : st_real1
:= c_st_real1_1 ;
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
signal s_st_arr1 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3 : st_arr3
:= c_st_arr3_1 ;
--
end ENT00075_Test_Bench ;
--
architecture ARCH00075_Test_Bench of ENT00075_Test_Bench is
begin
L1:
block
component UUT
port (
s_boolean : inout boolean
; s_bit : inout bit
; s_severity_level : inout severity_level
; s_character : inout character
; s_st_enum1 : inout st_enum1
; s_integer : inout integer
; s_st_int1 : inout st_int1
; s_time : inout time
; s_st_phys1 : inout st_phys1
; s_real : inout real
; s_st_real1 : inout st_real1
; s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
; s_st_arr1 : inout st_arr1
; s_st_arr2 : inout st_arr2
; s_st_arr3 : inout st_arr3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00075 ( ARCH00075 ) ;
begin
CIS1 : UUT
port map (
s_boolean
, s_bit
, s_severity_level
, s_character
, s_st_enum1
, s_integer
, s_st_int1
, s_time
, s_st_phys1
, s_real
, s_st_real1
, s_st_rec1
, s_st_rec2
, s_st_rec3
, s_st_arr1
, s_st_arr2
, s_st_arr3
) ;
end block L1 ;
end ARCH00075_Test_Bench ;
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18432)
`protect data_block
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18432)
`protect data_block
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18432)
`protect data_block
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
entity concat is
end entity;
architecture arch of concat is
type int_array is array (integer range <>) of integer;
begin
process
variable w : int_array(1 to 4);
variable x, y : int_array(1 to 3);
variable z : int_array(1 to 6);
variable s : string(1 to 5);
variable t : int_array(1 to 2);
variable b : bit_vector(1 to 3);
variable c : bit_vector(1 to 4);
begin
x := ( 1, 2, 3 );
y := ( 4, 5, 6 );
z := x & y; -- OK
w := 1 & x; -- OK
w := y & 5; -- OK
s := 'h' & string'("ello"); -- OK
s := 1 & string'("ello"); -- Error
t := 6 & 7; -- OK
t := 7 & character'( 'x' ); -- Error
c := bit_vector(b & '1'); -- OK
assert "10" = ("1" & b(1)); -- OK
assert ("1" & b(1)) = "10"; -- OK
assert "10" = (b(1) & "0"); -- OK
wait;
end process;
process
type mem_type is array (1 to 128) of bit_vector(7 downto 0);
variable mem : mem_type;
variable byte : bit_vector(7 downto 0);
begin
mem := mem(1 to 127) & byte; -- OK
wait;
end process;
end architecture;
|
-- megafunction wizard: %ALTPLL_RECONFIG%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll_reconfig
-- ============================================================
-- File Name: PLL_RECONFIG.vhd
-- Megafunction Name(s):
-- altpll_reconfig
--
-- Simulation Library Files(s):
-- altera_mf;cycloneive;lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 16.1.2 Build 203 01/18/2017 SJ Lite Edition
-- ************************************************************
--Copyright (C) 2017 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Intel and sold by Intel or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
--altpll_reconfig CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone IV E" busy clock counter_param counter_type data_in data_out pll_areset pll_areset_in pll_configupdate pll_scanclk pll_scanclkena pll_scandata pll_scandataout pll_scandone read_param reconfig reset write_param
--VERSION_BEGIN 16.1 cbx_altera_syncram_nd_impl 2017:01:11:18:30:33:SJ cbx_altpll_reconfig 2017:01:11:18:30:33:SJ cbx_altsyncram 2017:01:11:18:30:33:SJ cbx_cycloneii 2017:01:11:18:30:33:SJ cbx_lpm_add_sub 2017:01:11:18:30:33:SJ cbx_lpm_compare 2017:01:11:18:30:33:SJ cbx_lpm_counter 2017:01:11:18:30:33:SJ cbx_lpm_decode 2017:01:11:18:30:33:SJ cbx_lpm_mux 2017:01:11:18:30:33:SJ cbx_mgl 2017:01:11:19:37:47:SJ cbx_nadder 2017:01:11:18:30:33:SJ cbx_stratix 2017:01:11:18:30:33:SJ cbx_stratixii 2017:01:11:18:30:33:SJ cbx_stratixiii 2017:01:11:18:30:33:SJ cbx_stratixv 2017:01:11:18:30:33:SJ cbx_util_mgl 2017:01:11:18:30:33:SJ VERSION_END
LIBRARY altera_mf;
USE altera_mf.all;
LIBRARY cycloneive;
USE cycloneive.all;
LIBRARY lpm;
USE lpm.all;
--synthesis_resources = altsyncram 1 lpm_add_sub 2 lpm_compare 1 lpm_counter 7 lpm_decode 1 lut 3 reg 80
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY PLL_RECONFIG_pllrcfg_66q IS
PORT
(
busy : OUT STD_LOGIC;
clock : IN STD_LOGIC;
counter_param : IN STD_LOGIC_VECTOR (2 DOWNTO 0) := (OTHERS => '0');
counter_type : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
data_in : IN STD_LOGIC_VECTOR (8 DOWNTO 0) := (OTHERS => '0');
data_out : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
pll_areset : OUT STD_LOGIC;
pll_areset_in : IN STD_LOGIC := '0';
pll_configupdate : OUT STD_LOGIC;
pll_scanclk : OUT STD_LOGIC;
pll_scanclkena : OUT STD_LOGIC;
pll_scandata : OUT STD_LOGIC;
pll_scandataout : IN STD_LOGIC := '0';
pll_scandone : IN STD_LOGIC := '0';
read_param : IN STD_LOGIC := '0';
reconfig : IN STD_LOGIC := '0';
reset : IN STD_LOGIC;
write_param : IN STD_LOGIC := '0'
);
END PLL_RECONFIG_pllrcfg_66q;
ARCHITECTURE RTL OF PLL_RECONFIG_pllrcfg_66q IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
ATTRIBUTE ALTERA_ATTRIBUTE : string;
ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "ADV_NETLIST_OPT_ALLOWED=""NEVER_ALLOW"";suppress_da_rule_internal=C106;{-to le_comb10} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=2;{-to le_comb8} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=0;{-to le_comb9} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=1";
SIGNAL wire_altsyncram4_data_a : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altsyncram4_q_a : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_le_comb10_combout : STD_LOGIC;
SIGNAL wire_le_comb8_combout : STD_LOGIC;
SIGNAL wire_le_comb9_combout : STD_LOGIC;
SIGNAL areset_init_state_1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL areset_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL C0_data_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL C0_ena_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL C1_data_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL C1_ena_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_C1_ena_state_w_lg_q1766w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL C2_data_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL C2_ena_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_C2_ena_state_w_lg_q1767w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL C3_data_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL C3_ena_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL C4_data_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL C4_ena_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL configupdate2_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL configupdate3_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_configupdate3_state_w_lg_q1842w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL configupdate_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL counter_param_latch_reg : STD_LOGIC_VECTOR(2 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL counter_type_latch_reg : STD_LOGIC_VECTOR(3 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL idle_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF idle_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
SIGNAL wire_idle_state_w_lg_w_lg_w_lg_w_lg_q1731w1732w1733w1734w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_idle_state_w_lg_w_lg_w_lg_q1731w1732w1733w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_idle_state_w_lg_w_lg_q1731w1732w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_idle_state_w_lg_q1731w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_idle_state_w_lg_q1672w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_idle_state_w1735w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_idle_state_w_lg_w1735w1736w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_idle_state_w_lg_w_lg_w1735w1736w1737w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_idle_state_w_lg_w_lg_w_lg_w1735w1736w1737w1738w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL nominal_data0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL nominal_data1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL nominal_data2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL nominal_data3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL nominal_data4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL nominal_data5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL nominal_data6 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL nominal_data7 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL nominal_data8 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL nominal_data9 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL nominal_data10 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL nominal_data11 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL nominal_data12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL nominal_data13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL nominal_data14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL nominal_data15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL nominal_data16 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL nominal_data17 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL read_data_nominal_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF read_data_nominal_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
SIGNAL wire_read_data_nominal_state_w_lg_q1752w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_read_data_nominal_state_w_lg_q1686w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL read_data_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF read_data_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
SIGNAL wire_read_data_state_w_lg_q1745w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_read_data_state_w_lg_q1678w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL read_first_nominal_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF read_first_nominal_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
SIGNAL wire_read_first_nominal_state_w_lg_q1753w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_read_first_nominal_state_w_lg_q1684w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL read_first_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF read_first_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
SIGNAL wire_read_first_state_w_lg_q1746w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_read_first_state_w_lg_q1676w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL read_init_nominal_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF read_init_nominal_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
SIGNAL wire_read_init_nominal_state_w_lg_q1682w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL read_init_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF read_init_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
SIGNAL wire_read_init_state_w_lg_q1674w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_read_init_state_w_lg_q1848w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL read_last_nominal_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF read_last_nominal_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
SIGNAL wire_read_last_nominal_state_w_lg_q1865w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_read_last_nominal_state_w_lg_q1688w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL read_last_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF read_last_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
SIGNAL wire_read_last_state_w_lg_q1680w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL reconfig_counter_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF reconfig_counter_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
SIGNAL wire_reconfig_counter_state_w_lg_q1700w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL reconfig_init_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF reconfig_init_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
SIGNAL wire_reconfig_init_state_w_lg_q1698w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL reconfig_post_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF reconfig_post_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
SIGNAL wire_reconfig_post_state_w_lg_q1829w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_reconfig_post_state_w_lg_q1706w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL reconfig_seq_data_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF reconfig_seq_data_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
SIGNAL wire_reconfig_seq_data_state_w_lg_q1704w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL reconfig_seq_ena_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF reconfig_seq_ena_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
SIGNAL wire_reconfig_seq_ena_state_w_lg_q1856w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_reconfig_seq_ena_state_w_lg_q1857w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_reconfig_seq_ena_state_w_lg_q1702w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL reconfig_wait_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF reconfig_wait_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
SIGNAL wire_reconfig_wait_state_w_lg_q1833w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_reconfig_wait_state_w_lg_q1708w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL reset_state : STD_LOGIC
-- synopsys translate_off
:= '1'
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF reset_state : SIGNAL IS "POWER_UP_LEVEL=HIGH";
SIGNAL wire_reset_state_w_lg_q1671w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL shift_reg0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_shift_reg_w_lg_q217w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_shift_reg_w_lg_w_lg_q217w218w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL shift_reg1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_shift_reg_w_lg_q223w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_shift_reg_w_lg_w_lg_q223w224w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL shift_reg2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_shift_reg_w_lg_q228w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_shift_reg_w_lg_w_lg_q228w229w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL shift_reg3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_shift_reg_w_lg_q233w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_shift_reg_w_lg_w_lg_q233w234w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL shift_reg4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_shift_reg_w_lg_q238w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_shift_reg_w_lg_w_lg_q238w239w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL shift_reg5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_shift_reg_w_lg_q243w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_shift_reg_w_lg_w_lg_q243w244w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL shift_reg6 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_shift_reg_w_lg_q248w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_shift_reg_w_lg_w_lg_q248w249w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL shift_reg7 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_shift_reg_w_lg_q253w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_shift_reg_w_lg_w_lg_q253w254w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL shift_reg8 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_shift_reg_w_lg_q258w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_shift_reg_w_lg_w_lg_q258w259w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL shift_reg9 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL shift_reg10 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL shift_reg11 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL shift_reg12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL shift_reg13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL shift_reg14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL shift_reg15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL shift_reg16 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL shift_reg17 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_shift_reg_w_lg_q262w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_shift_reg_w_lg_q264w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_shift_reg_w_lg_q267w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_shift_reg_w_lg_q270w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_shift_reg_w_lg_q273w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_shift_reg_w_lg_q276w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_shift_reg_w_lg_q279w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_shift_reg_w_lg_q282w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_shift_reg_ena : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL tmp_nominal_data_out_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL tmp_seq_ena_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL write_data_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF write_data_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
SIGNAL wire_write_data_state_w_lg_q1726w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_write_data_state_w_lg_q1692w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL write_init_nominal_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF write_init_nominal_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
SIGNAL wire_write_init_nominal_state_w_lg_q1694w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL write_init_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF write_init_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
SIGNAL wire_write_init_state_w_lg_q1690w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_write_init_state_w_lg_q1853w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL write_nominal_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF write_nominal_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
SIGNAL wire_write_nominal_state_w_lg_q1725w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_write_nominal_state_w_lg_q1696w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_add_sub5_w_lg_w_result_range214w215w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_add_sub5_w_lg_w_result_range221w222w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_add_sub5_w_lg_w_result_range226w227w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_add_sub5_w_lg_w_result_range231w232w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_add_sub5_w_lg_w_result_range236w237w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_add_sub5_w_lg_w_result_range241w242w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_add_sub5_w_lg_w_result_range246w247w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_add_sub5_w_lg_w_result_range251w252w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_add_sub5_w_lg_w_result_range256w257w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_gnd : STD_LOGIC;
SIGNAL wire_add_sub5_dataa : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub5_datab : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub5_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub5_w_result_range214w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_add_sub5_w_result_range221w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_add_sub5_w_result_range226w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_add_sub5_w_result_range231w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_add_sub5_w_result_range236w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_add_sub5_w_result_range241w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_add_sub5_w_result_range246w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_add_sub5_w_result_range251w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_add_sub5_w_result_range256w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_add_sub6_dataa : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_add_sub6_result : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_cmpr7_aeb : STD_LOGIC;
SIGNAL wire_cmpr7_dataa : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_cmpr7_datab : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_cntr1_q : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_cntr12_q : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_cntr13_q : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_cntr14_q : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_cntr15_q : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_cntr2_q : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_cntr3_q : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_decode11_eq : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w_lg_addr_counter_out1880w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_addr_decoder_out1854w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_c0_wire1808w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_c1_wire1806w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_c2_wire1804w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_c3_wire1802w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_c4_wire1800w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_read_addr_counter_out1879w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_read_addr_decoder_out1849w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_reconfig_addr_counter_out1877w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_rotate_addr_counter_out1878w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable187w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable179w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable171w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable163w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable155w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable147w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable139w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable131w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable123w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_counter_param_latch_range294w379w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_counter_type_latch_range284w710w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_dummy_scandataout1873w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_pll_scandone1875w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_nominal_out216w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_param1730w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_reconfig1728w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_reconfig_done1832w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_reconfig_post_done1828w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_reconfig_width_counter_done1825w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_reset1w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_rotate_width_counter_done1776w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_width_counter_done1744w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_write_from_rom1727w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_write_param1729w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_counter_param_latch_range296w297w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_counter_type_latch_range286w530w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1329w1392w1452w1516w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w1329w1392w1452w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1361w1422w1483w1550w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w1329w1392w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w1361w1422w1483w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1329w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w1361w1422w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w980w1055w1126w1195w1261w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1361w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w980w1055w1126w1195w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1016w1091w1160w1228w1294w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w980w1055w1126w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1016w1091w1160w1228w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w980w1055w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w1016w1091w1160w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w980w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w1016w1091w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w_lg_w423w570w637w749w817w920w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1016w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w63w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w423w570w637w749w817w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w571w672w784w850w951w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_shift_reg_load_enable60w61w62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w423w570w637w749w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w571w672w784w850w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable60w61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w423w570w637w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w571w672w784w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_dummy_scandataout1874w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w301w378w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w381w495w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w423w570w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w571w672w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w675w885w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL addr_counter_enable : STD_LOGIC;
SIGNAL addr_counter_out : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL addr_counter_sload : STD_LOGIC;
SIGNAL addr_counter_sload_value : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL addr_decoder_out : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL c0_wire : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL c1_wire : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL c2_wire : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL c3_wire : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL c4_wire : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL counter_param_latch : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL counter_type_latch : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL cuda_combout_wire : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL dummy_scandataout : STD_LOGIC;
SIGNAL encode_out : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL input_latch_enable : STD_LOGIC;
SIGNAL power_up : STD_LOGIC;
SIGNAL read_addr_counter_enable : STD_LOGIC;
SIGNAL read_addr_counter_out : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL read_addr_counter_sload : STD_LOGIC;
SIGNAL read_addr_counter_sload_value : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL read_addr_decoder_out : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL read_nominal_out : STD_LOGIC;
SIGNAL reconfig_addr_counter_enable : STD_LOGIC;
SIGNAL reconfig_addr_counter_out : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL reconfig_addr_counter_sload : STD_LOGIC;
SIGNAL reconfig_addr_counter_sload_value : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL reconfig_done : STD_LOGIC;
SIGNAL reconfig_post_done : STD_LOGIC;
SIGNAL reconfig_width_counter_done : STD_LOGIC;
SIGNAL reconfig_width_counter_enable : STD_LOGIC;
SIGNAL reconfig_width_counter_sload : STD_LOGIC;
SIGNAL reconfig_width_counter_sload_value : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL rotate_addr_counter_enable : STD_LOGIC;
SIGNAL rotate_addr_counter_out : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL rotate_addr_counter_sload : STD_LOGIC;
SIGNAL rotate_addr_counter_sload_value : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL rotate_decoder_wires : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rotate_width_counter_done : STD_LOGIC;
SIGNAL rotate_width_counter_enable : STD_LOGIC;
SIGNAL rotate_width_counter_sload : STD_LOGIC;
SIGNAL rotate_width_counter_sload_value : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL scan_cache_address : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL scan_cache_in : STD_LOGIC;
SIGNAL scan_cache_out : STD_LOGIC;
SIGNAL scan_cache_write_enable : STD_LOGIC;
SIGNAL sel_param_bypass_LF_unused : STD_LOGIC;
SIGNAL sel_param_c : STD_LOGIC;
SIGNAL sel_param_high_i_postscale : STD_LOGIC;
SIGNAL sel_param_low_r : STD_LOGIC;
SIGNAL sel_param_nominal_count : STD_LOGIC;
SIGNAL sel_param_odd_CP_unused : STD_LOGIC;
SIGNAL sel_type_c0 : STD_LOGIC;
SIGNAL sel_type_c1 : STD_LOGIC;
SIGNAL sel_type_c2 : STD_LOGIC;
SIGNAL sel_type_c3 : STD_LOGIC;
SIGNAL sel_type_c4 : STD_LOGIC;
SIGNAL sel_type_cplf : STD_LOGIC;
SIGNAL sel_type_m : STD_LOGIC;
SIGNAL sel_type_n : STD_LOGIC;
SIGNAL sel_type_vco : STD_LOGIC;
SIGNAL seq_addr_wire : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL seq_sload_value : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL shift_reg_clear : STD_LOGIC;
SIGNAL shift_reg_load_enable : STD_LOGIC;
SIGNAL shift_reg_load_nominal_enable : STD_LOGIC;
SIGNAL shift_reg_serial_in : STD_LOGIC;
SIGNAL shift_reg_serial_out : STD_LOGIC;
SIGNAL shift_reg_shift_enable : STD_LOGIC;
SIGNAL shift_reg_shift_nominal_enable : STD_LOGIC;
SIGNAL shift_reg_width_select : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL w1019w : STD_LOGIC;
SIGNAL w1056w : STD_LOGIC;
SIGNAL w1092w : STD_LOGIC;
SIGNAL w1127w : STD_LOGIC;
SIGNAL w1163w : STD_LOGIC;
SIGNAL w1196w : STD_LOGIC;
SIGNAL w1229w : STD_LOGIC;
SIGNAL w1262w : STD_LOGIC;
SIGNAL w1297w : STD_LOGIC;
SIGNAL w1330w : STD_LOGIC;
SIGNAL w1362w : STD_LOGIC;
SIGNAL w1393w : STD_LOGIC;
SIGNAL w1424w : STD_LOGIC;
SIGNAL w1453w : STD_LOGIC;
SIGNAL w1484w : STD_LOGIC;
SIGNAL w1517w : STD_LOGIC;
SIGNAL w1565w : STD_LOGIC;
SIGNAL w1592w : STD_LOGIC;
SIGNAL w301w : STD_LOGIC;
SIGNAL w341w : STD_LOGIC;
SIGNAL w381w : STD_LOGIC;
SIGNAL w423w : STD_LOGIC;
SIGNAL w460w : STD_LOGIC;
SIGNAL w496w : STD_LOGIC;
SIGNAL w534w : STD_LOGIC;
SIGNAL w571w : STD_LOGIC;
SIGNAL w605w : STD_LOGIC;
SIGNAL w638w : STD_LOGIC;
SIGNAL w64w : STD_LOGIC;
SIGNAL w675w : STD_LOGIC;
SIGNAL w713w : STD_LOGIC;
SIGNAL w750w : STD_LOGIC;
SIGNAL w785w : STD_LOGIC;
SIGNAL w818w : STD_LOGIC;
SIGNAL w851w : STD_LOGIC;
SIGNAL w888w : STD_LOGIC;
SIGNAL w921w : STD_LOGIC;
SIGNAL w952w : STD_LOGIC;
SIGNAL w981w : STD_LOGIC;
SIGNAL width_counter_done : STD_LOGIC;
SIGNAL width_counter_enable : STD_LOGIC;
SIGNAL width_counter_sload : STD_LOGIC;
SIGNAL width_counter_sload_value : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL width_decoder_out : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL width_decoder_select : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL write_from_rom : STD_LOGIC;
SIGNAL wire_w_counter_param_latch_range294w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_counter_param_latch_range296w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_counter_type_latch_range284w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_counter_type_latch_range286w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range186w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range178w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range170w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range162w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range154w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range146w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range138w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range130w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range122w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_rotate_decoder_wires_range1807w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_rotate_decoder_wires_range1805w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_rotate_decoder_wires_range1803w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_rotate_decoder_wires_range1801w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_rotate_decoder_wires_range1799w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_shift_reg_width_select_range261w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_shift_reg_width_select_range263w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_shift_reg_width_select_range266w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_shift_reg_width_select_range269w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_shift_reg_width_select_range272w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_shift_reg_width_select_range275w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_shift_reg_width_select_range278w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_shift_reg_width_select_range281w : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altsyncram
GENERIC
(
ADDRESS_ACLR_A : STRING := "UNUSED";
ADDRESS_ACLR_B : STRING := "NONE";
ADDRESS_REG_B : STRING := "CLOCK1";
BYTE_SIZE : NATURAL := 8;
BYTEENA_ACLR_A : STRING := "UNUSED";
BYTEENA_ACLR_B : STRING := "NONE";
BYTEENA_REG_B : STRING := "CLOCK1";
CLOCK_ENABLE_CORE_A : STRING := "USE_INPUT_CLKEN";
CLOCK_ENABLE_CORE_B : STRING := "USE_INPUT_CLKEN";
CLOCK_ENABLE_INPUT_A : STRING := "NORMAL";
CLOCK_ENABLE_INPUT_B : STRING := "NORMAL";
CLOCK_ENABLE_OUTPUT_A : STRING := "NORMAL";
CLOCK_ENABLE_OUTPUT_B : STRING := "NORMAL";
ECC_PIPELINE_STAGE_ENABLED : STRING := "FALSE";
ENABLE_ECC : STRING := "FALSE";
IMPLEMENT_IN_LES : STRING := "OFF";
INDATA_ACLR_A : STRING := "UNUSED";
INDATA_ACLR_B : STRING := "NONE";
INDATA_REG_B : STRING := "CLOCK1";
INIT_FILE : STRING := "UNUSED";
INIT_FILE_LAYOUT : STRING := "PORT_A";
MAXIMUM_DEPTH : NATURAL := 0;
NUMWORDS_A : NATURAL := 0;
NUMWORDS_B : NATURAL := 0;
OPERATION_MODE : STRING := "BIDIR_DUAL_PORT";
OUTDATA_ACLR_A : STRING := "NONE";
OUTDATA_ACLR_B : STRING := "NONE";
OUTDATA_REG_A : STRING := "UNREGISTERED";
OUTDATA_REG_B : STRING := "UNREGISTERED";
POWER_UP_UNINITIALIZED : STRING := "FALSE";
RAM_BLOCK_TYPE : STRING := "AUTO";
RDCONTROL_ACLR_B : STRING := "NONE";
RDCONTROL_REG_B : STRING := "CLOCK1";
READ_DURING_WRITE_MODE_MIXED_PORTS : STRING := "DONT_CARE";
read_during_write_mode_port_a : STRING := "NEW_DATA_NO_NBE_READ";
read_during_write_mode_port_b : STRING := "NEW_DATA_NO_NBE_READ";
WIDTH_A : NATURAL;
WIDTH_B : NATURAL := 1;
WIDTH_BYTEENA_A : NATURAL := 1;
WIDTH_BYTEENA_B : NATURAL := 1;
WIDTH_ECCSTATUS : NATURAL := 3;
WIDTHAD_A : NATURAL;
WIDTHAD_B : NATURAL := 1;
WRCONTROL_ACLR_A : STRING := "UNUSED";
WRCONTROL_ACLR_B : STRING := "NONE";
WRCONTROL_WRADDRESS_REG_B : STRING := "CLOCK1";
INTENDED_DEVICE_FAMILY : STRING := "Cyclone IV E";
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "altsyncram"
);
PORT
(
aclr0 : IN STD_LOGIC := '0';
aclr1 : IN STD_LOGIC := '0';
address_a : IN STD_LOGIC_VECTOR(WIDTHAD_A-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR(WIDTHAD_B-1 DOWNTO 0) := (OTHERS => '1');
addressstall_a : IN STD_LOGIC := '0';
addressstall_b : IN STD_LOGIC := '0';
byteena_a : IN STD_LOGIC_VECTOR(WIDTH_BYTEENA_A-1 DOWNTO 0) := (OTHERS => '1');
byteena_b : IN STD_LOGIC_VECTOR(WIDTH_BYTEENA_B-1 DOWNTO 0) := (OTHERS => '1');
clock0 : IN STD_LOGIC := '1';
clock1 : IN STD_LOGIC := '1';
clocken0 : IN STD_LOGIC := '1';
clocken1 : IN STD_LOGIC := '1';
clocken2 : IN STD_LOGIC := '1';
clocken3 : IN STD_LOGIC := '1';
data_a : IN STD_LOGIC_VECTOR(WIDTH_A-1 DOWNTO 0) := (OTHERS => '1');
data_b : IN STD_LOGIC_VECTOR(WIDTH_B-1 DOWNTO 0) := (OTHERS => '1');
eccstatus : OUT STD_LOGIC_VECTOR(WIDTH_ECCSTATUS-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR(WIDTH_A-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR(WIDTH_B-1 DOWNTO 0);
rden_a : IN STD_LOGIC := '1';
rden_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT cycloneive_lcell_comb
GENERIC
(
DONT_TOUCH : STRING := "off";
LUT_MASK : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0000000000000000";
SUM_LUTC_INPUT : STRING := "datac";
lpm_type : STRING := "cycloneive_lcell_comb"
);
PORT
(
cin : IN STD_LOGIC := '0';
combout : OUT STD_LOGIC;
cout : OUT STD_LOGIC;
dataa : IN STD_LOGIC := '0';
datab : IN STD_LOGIC := '0';
datac : IN STD_LOGIC := '0';
datad : IN STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT lpm_add_sub
GENERIC
(
LPM_DIRECTION : STRING := "DEFAULT";
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "SIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_add_sub"
);
PORT
(
aclr : IN STD_LOGIC := '0';
add_sub : IN STD_LOGIC := '1';
cin : IN STD_LOGIC := 'Z';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
cout : OUT STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
overflow : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_compare
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_compare"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aeb : OUT STD_LOGIC;
agb : OUT STD_LOGIC;
ageb : OUT STD_LOGIC;
alb : OUT STD_LOGIC;
aleb : OUT STD_LOGIC;
aneb : OUT STD_LOGIC;
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
COMPONENT lpm_counter
GENERIC
(
lpm_avalue : STRING := "0";
lpm_direction : STRING := "DEFAULT";
lpm_modulus : NATURAL := 0;
lpm_port_updown : STRING := "PORT_CONNECTIVITY";
lpm_pvalue : STRING := "0";
lpm_svalue : STRING := "0";
lpm_width : NATURAL;
lpm_type : STRING := "lpm_counter"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aload : IN STD_LOGIC := '0';
aset : IN STD_LOGIC := '0';
cin : IN STD_LOGIC := '1';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC;
cnt_en : IN STD_LOGIC := '1';
cout : OUT STD_LOGIC;
data : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
eq : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
sclr : IN STD_LOGIC := '0';
sload : IN STD_LOGIC := '0';
sset : IN STD_LOGIC := '0';
updown : IN STD_LOGIC := '1'
);
END COMPONENT;
COMPONENT lpm_decode
GENERIC
(
LPM_DECODES : NATURAL;
LPM_PIPELINE : NATURAL := 0;
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_decode"
);
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
enable : IN STD_LOGIC := '1';
eq : OUT STD_LOGIC_VECTOR(LPM_DECODES-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
wire_gnd <= '0';
loop0 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_addr_counter_out1880w(i) <= addr_counter_out(i) AND addr_counter_enable;
END GENERATE loop0;
loop1 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_addr_decoder_out1854w(i) <= addr_decoder_out(i) AND wire_write_init_state_w_lg_q1853w(0);
END GENERATE loop1;
loop2 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_c0_wire1808w(i) <= c0_wire(i) AND wire_w_rotate_decoder_wires_range1807w(0);
END GENERATE loop2;
loop3 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_c1_wire1806w(i) <= c1_wire(i) AND wire_w_rotate_decoder_wires_range1805w(0);
END GENERATE loop3;
loop4 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_c2_wire1804w(i) <= c2_wire(i) AND wire_w_rotate_decoder_wires_range1803w(0);
END GENERATE loop4;
loop5 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_c3_wire1802w(i) <= c3_wire(i) AND wire_w_rotate_decoder_wires_range1801w(0);
END GENERATE loop5;
loop6 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_c4_wire1800w(i) <= c4_wire(i) AND wire_w_rotate_decoder_wires_range1799w(0);
END GENERATE loop6;
loop7 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_read_addr_counter_out1879w(i) <= read_addr_counter_out(i) AND read_addr_counter_enable;
END GENERATE loop7;
loop8 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_read_addr_decoder_out1849w(i) <= read_addr_decoder_out(i) AND wire_read_init_state_w_lg_q1848w(0);
END GENERATE loop8;
loop9 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_reconfig_addr_counter_out1877w(i) <= reconfig_addr_counter_out(i) AND reconfig_addr_counter_enable;
END GENERATE loop9;
loop10 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_rotate_addr_counter_out1878w(i) <= rotate_addr_counter_out(i) AND rotate_addr_counter_enable;
END GENERATE loop10;
wire_w_lg_shift_reg_load_enable187w(0) <= shift_reg_load_enable AND wire_w_data_in_range186w(0);
wire_w_lg_shift_reg_load_enable179w(0) <= shift_reg_load_enable AND wire_w_data_in_range178w(0);
wire_w_lg_shift_reg_load_enable171w(0) <= shift_reg_load_enable AND wire_w_data_in_range170w(0);
wire_w_lg_shift_reg_load_enable163w(0) <= shift_reg_load_enable AND wire_w_data_in_range162w(0);
wire_w_lg_shift_reg_load_enable155w(0) <= shift_reg_load_enable AND wire_w_data_in_range154w(0);
wire_w_lg_shift_reg_load_enable147w(0) <= shift_reg_load_enable AND wire_w_data_in_range146w(0);
wire_w_lg_shift_reg_load_enable139w(0) <= shift_reg_load_enable AND wire_w_data_in_range138w(0);
wire_w_lg_shift_reg_load_enable131w(0) <= shift_reg_load_enable AND wire_w_data_in_range130w(0);
wire_w_lg_shift_reg_load_enable123w(0) <= shift_reg_load_enable AND wire_w_data_in_range122w(0);
wire_w_lg_w_counter_param_latch_range294w379w(0) <= wire_w_counter_param_latch_range294w(0) AND wire_w_lg_w_counter_param_latch_range296w297w(0);
wire_w_lg_w_counter_type_latch_range284w710w(0) <= wire_w_counter_type_latch_range284w(0) AND wire_w_lg_w_counter_type_latch_range286w530w(0);
wire_w_lg_dummy_scandataout1873w(0) <= NOT dummy_scandataout;
wire_w_lg_pll_scandone1875w(0) <= NOT pll_scandone;
wire_w_lg_read_nominal_out216w(0) <= NOT read_nominal_out;
wire_w_lg_read_param1730w(0) <= NOT read_param;
wire_w_lg_reconfig1728w(0) <= NOT reconfig;
wire_w_lg_reconfig_done1832w(0) <= NOT reconfig_done;
wire_w_lg_reconfig_post_done1828w(0) <= NOT reconfig_post_done;
wire_w_lg_reconfig_width_counter_done1825w(0) <= NOT reconfig_width_counter_done;
wire_w_lg_reset1w(0) <= NOT reset;
wire_w_lg_rotate_width_counter_done1776w(0) <= NOT rotate_width_counter_done;
wire_w_lg_width_counter_done1744w(0) <= NOT width_counter_done;
wire_w_lg_write_from_rom1727w(0) <= NOT write_from_rom;
wire_w_lg_write_param1729w(0) <= NOT write_param;
wire_w_lg_w_counter_param_latch_range296w297w(0) <= NOT wire_w_counter_param_latch_range296w(0);
wire_w_lg_w_counter_type_latch_range286w530w(0) <= NOT wire_w_counter_type_latch_range286w(0);
wire_w_lg_w_lg_w_lg_w1329w1392w1452w1516w(0) <= wire_w_lg_w_lg_w1329w1392w1452w(0) OR w1484w;
wire_w_lg_w_lg_w1329w1392w1452w(0) <= wire_w_lg_w1329w1392w(0) OR w1424w;
wire_w_lg_w_lg_w_lg_w1361w1422w1483w1550w(0) <= wire_w_lg_w_lg_w1361w1422w1483w(0) OR w1517w;
wire_w_lg_w1329w1392w(0) <= wire_w1329w(0) OR w1362w;
wire_w_lg_w_lg_w1361w1422w1483w(0) <= wire_w_lg_w1361w1422w(0) OR w1453w;
wire_w1329w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w980w1055w1126w1195w1261w(0) OR w1297w;
wire_w_lg_w1361w1422w(0) <= wire_w1361w(0) OR w1393w;
wire_w_lg_w_lg_w_lg_w_lg_w980w1055w1126w1195w1261w(0) <= wire_w_lg_w_lg_w_lg_w980w1055w1126w1195w(0) OR w1229w;
wire_w1361w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w1016w1091w1160w1228w1294w(0) OR w1330w;
wire_w_lg_w_lg_w_lg_w980w1055w1126w1195w(0) <= wire_w_lg_w_lg_w980w1055w1126w(0) OR w1163w;
wire_w_lg_w_lg_w_lg_w_lg_w1016w1091w1160w1228w1294w(0) <= wire_w_lg_w_lg_w_lg_w1016w1091w1160w1228w(0) OR w1262w;
wire_w_lg_w_lg_w980w1055w1126w(0) <= wire_w_lg_w980w1055w(0) OR w1092w;
wire_w_lg_w_lg_w_lg_w1016w1091w1160w1228w(0) <= wire_w_lg_w_lg_w1016w1091w1160w(0) OR w1196w;
wire_w_lg_w980w1055w(0) <= wire_w980w(0) OR w1019w;
wire_w_lg_w_lg_w1016w1091w1160w(0) <= wire_w_lg_w1016w1091w(0) OR w1127w;
wire_w980w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w_lg_w423w570w637w749w817w920w(0) OR w952w;
wire_w_lg_w1016w1091w(0) <= wire_w1016w(0) OR w1056w;
wire_w_lg_w_lg_w_lg_w_lg_w_lg_w423w570w637w749w817w920w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w423w570w637w749w817w(0) OR w888w;
wire_w1016w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w571w672w784w850w951w(0) OR w981w;
wire_w63w(0) <= wire_w_lg_w_lg_w_lg_shift_reg_load_enable60w61w62w(0) OR shift_reg_clear;
wire_w_lg_w_lg_w_lg_w_lg_w423w570w637w749w817w(0) <= wire_w_lg_w_lg_w_lg_w423w570w637w749w(0) OR w785w;
wire_w_lg_w_lg_w_lg_w_lg_w571w672w784w850w951w(0) <= wire_w_lg_w_lg_w_lg_w571w672w784w850w(0) OR w921w;
wire_w_lg_w_lg_w_lg_shift_reg_load_enable60w61w62w(0) <= wire_w_lg_w_lg_shift_reg_load_enable60w61w(0) OR shift_reg_shift_nominal_enable;
wire_w_lg_w_lg_w_lg_w423w570w637w749w(0) <= wire_w_lg_w_lg_w423w570w637w(0) OR w713w;
wire_w_lg_w_lg_w_lg_w571w672w784w850w(0) <= wire_w_lg_w_lg_w571w672w784w(0) OR w818w;
wire_w_lg_w_lg_shift_reg_load_enable60w61w(0) <= wire_w_lg_shift_reg_load_enable60w(0) OR shift_reg_load_nominal_enable;
wire_w_lg_w_lg_w423w570w637w(0) <= wire_w_lg_w423w570w(0) OR w605w;
wire_w_lg_w_lg_w571w672w784w(0) <= wire_w_lg_w571w672w(0) OR w750w;
wire_w_lg_dummy_scandataout1874w(0) <= dummy_scandataout OR wire_w_lg_dummy_scandataout1873w(0);
wire_w_lg_shift_reg_load_enable60w(0) <= shift_reg_load_enable OR shift_reg_shift_enable;
wire_w_lg_w301w378w(0) <= w301w OR w341w;
wire_w_lg_w381w495w(0) <= w381w OR w460w;
wire_w_lg_w423w570w(0) <= w423w OR w534w;
wire_w_lg_w571w672w(0) <= w571w OR w638w;
wire_w_lg_w675w885w(0) <= w675w OR w851w;
addr_counter_enable <= (write_data_state OR write_nominal_state);
addr_counter_out <= wire_cntr1_q;
addr_counter_sload <= wire_write_init_state_w_lg_q1853w(0);
addr_counter_sload_value <= wire_w_lg_addr_decoder_out1854w;
addr_decoder_out <= (((((((((((((((((((((((((((((((((((( "0" & "0" & "0" & "0" & "0" & "0" & "0" & w301w) OR ( "0" & "0" & "0" & "0" & "0" & "0" & w341w & w341w)) OR ( "0" & "0" & "0" & "0" & w381w & "0" & "0" & "0")) OR ( "0" & "0" & "0" & "0" & w423w & "0" & "0" & w423w)) OR ( "0" & "0" & "0" & "0" & w460w & w460w & w460w & "0")) OR ( "0" & "0" & "0" & w496w & "0" & "0" & "0" & w496w)) OR ( "0" & "0" & "0" & w534w & "0" & "0" & w534w & "0")) OR ( "0" & "0" & "0" & w571w & w571w & "0" & w571w & "0")) OR ( "0" & "0" & "0" & w605w & w605w & "0" & w605w & w605w)) OR ( "0" & "0" & w638w & "0" & "0" & "0" & w638w & w638w)) OR ( "0" & "0" & w675w & "0" & "0" & "0" & w675w & w675w)) OR ( "0" & "0" & w713w & "0" & "0" & w713w & "0" & "0")) OR ( "0" & "0" & w750w & "0" & w750w & w750w & "0" & "0")) OR ( "0" & "0" & w785w & "0" & w785w & w785w & "0" & w785w)) OR ( "0" & "0" & w818w & w818w & "0" & w818w & "0" & w818w)) OR ( "0" & "0" & w851w & w851w & "0" & w851w & "0" & w851w)) OR ( "0" & "0" & w888w & w888w & "0" & w888w & w888w & "0")) OR ( "0" & "0" & w921w & w921w & w921w & w921w & w921w & "0")) OR ( "0" & "0" & w952w & w952w & w952w & w952w & w952w & w952w)) OR ( "0" & w981w & "0" & "0" & "0" & w981w & w981w & w981w)) OR ( "0" & w1019w & "0" & "0" & w1019w & "0" & "0" & "0")) OR ( "0" & w1056w & "0" & w1056w & "0" & "0" & "0" & "0")) OR ( "0" & w1092w & "0" & w1092w & "0" & "0" & "0" & w1092w)) OR ( "0" & w1127w & "0" & w1127w & w1127w & "0" & "0" & w1127w)) OR ( "0" & w1163w & "0" & w1163w & w1163w & "0" & w1163w & "0")) OR ( "0" & w1196w & w1196w & "0" & "0" & "0" & w1196w & "0")) OR ( "0" & w1229w & w1229w & "0" & "0" & "0" & w1229w & w1229w)) OR ( "0" & w1262w & w1262w & "0" & w1262w & "0" & w1262w & w1262w)) OR ( "0" & w1297w & w1297w & "0" & w1297w & w1297w & "0" & "0")) OR ( "0" & w1330w & w1330w & w1330w & "0" & w1330w & "0" & "0")) OR ( "0" & w1362w & w1362w & w1362w & "0" & w1362w & "0" & w1362w)) OR ( "0" & w1393w & w1393w & w1393w & w1393w & w1393w & "0" & w1393w)) OR ( "0" & w1424w & w1424w & w1424w & w1424w
& w1424w & w1424w & "0")) OR ( w1453w & "0" & "0" & "0" & "0" & w1453w & w1453w & "0")) OR ( w1484w & "0" & "0" & "0" & "0" & w1484w & w1484w & w1484w)) OR ( w1517w & "0" & "0" & "0" & w1517w & w1517w & w1517w & w1517w));
busy <= (wire_idle_state_w_lg_q1672w(0) OR areset_state);
c0_wire <= "01000111";
c1_wire <= "01011001";
c2_wire <= "01101011";
c3_wire <= "01111101";
c4_wire <= "10001111";
counter_param_latch <= counter_param_latch_reg;
counter_type_latch <= counter_type_latch_reg;
cuda_combout_wire <= ( wire_le_comb10_combout & wire_le_comb9_combout & wire_le_comb8_combout);
data_out <= ( wire_shift_reg_w_lg_w_lg_q258w259w & wire_shift_reg_w_lg_w_lg_q253w254w & wire_shift_reg_w_lg_w_lg_q248w249w & wire_shift_reg_w_lg_w_lg_q243w244w & wire_shift_reg_w_lg_w_lg_q238w239w & wire_shift_reg_w_lg_w_lg_q233w234w & wire_shift_reg_w_lg_w_lg_q228w229w & wire_shift_reg_w_lg_w_lg_q223w224w & wire_shift_reg_w_lg_w_lg_q217w218w);
dummy_scandataout <= pll_scandataout;
encode_out <= ( C4_ena_state & wire_C2_ena_state_w_lg_q1767w & wire_C1_ena_state_w_lg_q1766w);
input_latch_enable <= (idle_state AND (write_param OR read_param));
pll_areset <= (pll_areset_in OR (areset_state AND reconfig_wait_state));
pll_configupdate <= (configupdate_state AND wire_configupdate3_state_w_lg_q1842w(0));
pll_scanclk <= clock;
pll_scanclkena <= ((rotate_width_counter_enable AND wire_w_lg_rotate_width_counter_done1776w(0)) OR reconfig_seq_data_state);
pll_scandata <= (scan_cache_out AND ((rotate_width_counter_enable OR reconfig_seq_data_state) OR reconfig_post_state));
power_up <= (((((((((((((((((((wire_reset_state_w_lg_q1671w(0) AND wire_idle_state_w_lg_q1672w(0)) AND wire_read_init_state_w_lg_q1674w(0)) AND wire_read_first_state_w_lg_q1676w(0)) AND wire_read_data_state_w_lg_q1678w(0)) AND wire_read_last_state_w_lg_q1680w(0)) AND wire_read_init_nominal_state_w_lg_q1682w(0)) AND wire_read_first_nominal_state_w_lg_q1684w(0)) AND wire_read_data_nominal_state_w_lg_q1686w(0)) AND wire_read_last_nominal_state_w_lg_q1688w(0)) AND wire_write_init_state_w_lg_q1690w(0)) AND wire_write_data_state_w_lg_q1692w(0)) AND wire_write_init_nominal_state_w_lg_q1694w(0)) AND wire_write_nominal_state_w_lg_q1696w(0)) AND wire_reconfig_init_state_w_lg_q1698w(0)) AND wire_reconfig_counter_state_w_lg_q1700w(0)) AND wire_reconfig_seq_ena_state_w_lg_q1702w(0)) AND wire_reconfig_seq_data_state_w_lg_q1704w(0)) AND wire_reconfig_post_state_w_lg_q1706w(0)) AND wire_reconfig_wait_state_w_lg_q1708w(0));
read_addr_counter_enable <= (((read_first_state OR read_data_state) OR read_first_nominal_state) OR read_data_nominal_state);
read_addr_counter_out <= wire_cntr2_q;
read_addr_counter_sload <= wire_read_init_state_w_lg_q1848w(0);
read_addr_counter_sload_value <= wire_w_lg_read_addr_decoder_out1849w;
read_addr_decoder_out <= (((((((((((((((((((((((((((((((((((( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0") OR ( "0" & "0" & "0" & "0" & "0" & "0" & w341w & "0")) OR ( "0" & "0" & "0" & "0" & "0" & w381w & "0" & "0")) OR ( "0" & "0" & "0" & "0" & w423w & "0" & "0" & w423w)) OR ( "0" & "0" & "0" & "0" & w460w & "0" & w460w & "0")) OR ( "0" & "0" & "0" & "0" & w496w & w496w & w496w & w496w)) OR ( "0" & "0" & "0" & w534w & "0" & "0" & w534w & "0")) OR ( "0" & "0" & "0" & w571w & "0" & "0" & w571w & w571w)) OR ( "0" & "0" & "0" & w605w & w605w & "0" & w605w & w605w)) OR ( "0" & "0" & "0" & w638w & w638w & w638w & "0" & "0")) OR ( "0" & "0" & "0" & w675w & "0" & "0" & w675w & "0")) OR ( "0" & "0" & w713w & "0" & "0" & w713w & "0" & "0")) OR ( "0" & "0" & w750w & "0" & "0" & w750w & "0" & w750w)) OR ( "0" & "0" & w785w & "0" & w785w & w785w & "0" & w785w)) OR ( "0" & "0" & w818w & "0" & w818w & w818w & w818w & "0")) OR ( "0" & "0" & w851w & "0" & "0" & w851w & "0" & "0")) OR ( "0" & "0" & w888w & w888w & "0" & w888w & w888w & "0")) OR ( "0" & "0" & w921w & w921w & "0" & w921w & w921w & w921w)) OR ( "0" & "0" & w952w & w952w & w952w & w952w & w952w & w952w)) OR ( "0" & w981w & "0" & "0" & "0" & "0" & "0" & "0")) OR ( "0" & w1019w & "0" & "0" & w1019w & "0" & "0" & "0")) OR ( "0" & w1056w & "0" & "0" & w1056w & "0" & "0" & w1056w)) OR ( "0" & w1092w & "0" & w1092w & "0" & "0" & "0" & w1092w)) OR ( "0" & w1127w & "0" & w1127w & "0" & "0" & w1127w & "0")) OR ( "0" & w1163w & "0" & w1163w & w1163w & "0" & w1163w & "0")) OR ( "0" & w1196w & "0" & w1196w & w1196w & "0" & w1196w & w1196w)) OR ( "0" & w1229w & w1229w & "0" & "0" & "0" & w1229w & w1229w)) OR ( "0" & w1262w & w1262w & "0" & "0" & w1262w & "0" & "0")) OR ( "0" & w1297w & w1297w & "0" & w1297w & w1297w & "0" & "0")) OR ( "0" & w1330w & w1330w & "0" & w1330w & w1330w & "0" & w1330w)) OR ( "0" & w1362w & w1362w & w1362w & "0" & w1362w & "0" & w1362w)) OR ( "0" & w1393w & w1393w & w1393w & "0" & w1393w & w1393w & "0")) OR ( "0" & w1424w & w1424w & w1424w & w1424w & w1424w
& w1424w & "0")) OR ( "0" & w1453w & w1453w & w1453w & w1453w & w1453w & w1453w & w1453w)) OR ( w1484w & "0" & "0" & "0" & "0" & w1484w & w1484w & w1484w)) OR ( w1517w & "0" & "0" & "0" & w1517w & "0" & "0" & "0"));
read_nominal_out <= tmp_nominal_data_out_state;
reconfig_addr_counter_enable <= reconfig_seq_data_state;
reconfig_addr_counter_out <= wire_cntr12_q;
reconfig_addr_counter_sload <= reconfig_seq_ena_state;
reconfig_addr_counter_sload_value <= wire_reconfig_seq_ena_state_w_lg_q1856w;
reconfig_done <= (wire_w_lg_pll_scandone1875w(0) AND wire_w_lg_dummy_scandataout1874w(0));
reconfig_post_done <= pll_scandone;
reconfig_width_counter_done <= ((((((NOT wire_cntr13_q(0)) AND (NOT wire_cntr13_q(1))) AND (NOT wire_cntr13_q(2))) AND (NOT wire_cntr13_q(3))) AND (NOT wire_cntr13_q(4))) AND (NOT wire_cntr13_q(5)));
reconfig_width_counter_enable <= reconfig_seq_data_state;
reconfig_width_counter_sload <= reconfig_seq_ena_state;
reconfig_width_counter_sload_value <= wire_reconfig_seq_ena_state_w_lg_q1857w;
rotate_addr_counter_enable <= ((((C0_data_state OR C1_data_state) OR C2_data_state) OR C3_data_state) OR C4_data_state);
rotate_addr_counter_out <= wire_cntr15_q;
rotate_addr_counter_sload <= ((((C0_ena_state OR C1_ena_state) OR C2_ena_state) OR C3_ena_state) OR C4_ena_state);
rotate_addr_counter_sload_value <= ((((wire_w_lg_c0_wire1808w OR wire_w_lg_c1_wire1806w) OR wire_w_lg_c2_wire1804w) OR wire_w_lg_c3_wire1802w) OR wire_w_lg_c4_wire1800w);
rotate_decoder_wires <= wire_decode11_eq;
rotate_width_counter_done <= (((((NOT wire_cntr14_q(0)) AND (NOT wire_cntr14_q(1))) AND (NOT wire_cntr14_q(2))) AND (NOT wire_cntr14_q(3))) AND (NOT wire_cntr14_q(4)));
rotate_width_counter_enable <= ((((C0_data_state OR C1_data_state) OR C2_data_state) OR C3_data_state) OR C4_data_state);
rotate_width_counter_sload <= ((((C0_ena_state OR C1_ena_state) OR C2_ena_state) OR C3_ena_state) OR C4_ena_state);
rotate_width_counter_sload_value <= "10010";
scan_cache_address <= (((wire_w_lg_addr_counter_out1880w OR wire_w_lg_read_addr_counter_out1879w) OR wire_w_lg_rotate_addr_counter_out1878w) OR wire_w_lg_reconfig_addr_counter_out1877w);
scan_cache_in <= shift_reg_serial_out;
scan_cache_out <= wire_altsyncram4_q_a(0);
scan_cache_write_enable <= (write_data_state OR write_nominal_state);
sel_param_bypass_LF_unused <= (((NOT counter_param_latch(0)) AND wire_w_lg_w_counter_param_latch_range296w297w(0)) AND counter_param_latch(2));
sel_param_c <= (((NOT counter_param_latch(0)) AND counter_param_latch(1)) AND (NOT counter_param_latch(2)));
sel_param_high_i_postscale <= (((NOT counter_param_latch(0)) AND wire_w_lg_w_counter_param_latch_range296w297w(0)) AND (NOT counter_param_latch(2)));
sel_param_low_r <= (wire_w_lg_w_counter_param_latch_range294w379w(0) AND (NOT counter_param_latch(2)));
sel_param_nominal_count <= ((counter_param_latch(0) AND counter_param_latch(1)) AND counter_param_latch(2));
sel_param_odd_CP_unused <= (wire_w_lg_w_counter_param_latch_range294w379w(0) AND counter_param_latch(2));
sel_type_c0 <= ((((NOT counter_type_latch(0)) AND wire_w_lg_w_counter_type_latch_range286w530w(0)) AND counter_type_latch(2)) AND (NOT counter_type_latch(3)));
sel_type_c1 <= ((wire_w_lg_w_counter_type_latch_range284w710w(0) AND counter_type_latch(2)) AND (NOT counter_type_latch(3)));
sel_type_c2 <= ((((NOT counter_type_latch(0)) AND counter_type_latch(1)) AND counter_type_latch(2)) AND (NOT counter_type_latch(3)));
sel_type_c3 <= (((counter_type_latch(0) AND counter_type_latch(1)) AND counter_type_latch(2)) AND (NOT counter_type_latch(3)));
sel_type_c4 <= ((((NOT counter_type_latch(0)) AND wire_w_lg_w_counter_type_latch_range286w530w(0)) AND (NOT counter_type_latch(2))) AND counter_type_latch(3));
sel_type_cplf <= ((((NOT counter_type_latch(0)) AND counter_type_latch(1)) AND (NOT counter_type_latch(2))) AND (NOT counter_type_latch(3)));
sel_type_m <= ((wire_w_lg_w_counter_type_latch_range284w710w(0) AND (NOT counter_type_latch(2))) AND (NOT counter_type_latch(3)));
sel_type_n <= ((((NOT counter_type_latch(0)) AND wire_w_lg_w_counter_type_latch_range286w530w(0)) AND (NOT counter_type_latch(2))) AND (NOT counter_type_latch(3)));
sel_type_vco <= (((counter_type_latch(0) AND counter_type_latch(1)) AND (NOT counter_type_latch(2))) AND (NOT counter_type_latch(3)));
seq_addr_wire <= "00110101";
seq_sload_value <= "110110";
shift_reg_clear <= wire_read_init_state_w_lg_q1848w(0);
shift_reg_load_enable <= ((idle_state AND write_param) AND (NOT ((((((NOT counter_type(3)) AND (NOT counter_type(2))) AND (NOT counter_type(1))) AND counter_param(2)) AND counter_param(1)) AND counter_param(0))));
shift_reg_load_nominal_enable <= ((idle_state AND write_param) AND ((((((NOT counter_type(3)) AND (NOT counter_type(2))) AND (NOT counter_type(1))) AND counter_param(2)) AND counter_param(1)) AND counter_param(0)));
shift_reg_serial_in <= scan_cache_out;
shift_reg_serial_out <= (((((((wire_shift_reg_w_lg_q262w(0) OR wire_shift_reg_w_lg_q264w(0)) OR wire_shift_reg_w_lg_q267w(0)) OR wire_shift_reg_w_lg_q270w(0)) OR wire_shift_reg_w_lg_q273w(0)) OR wire_shift_reg_w_lg_q276w(0)) OR wire_shift_reg_w_lg_q279w(0)) OR wire_shift_reg_w_lg_q282w(0));
shift_reg_shift_enable <= ((read_data_state OR read_last_state) OR write_data_state);
shift_reg_shift_nominal_enable <= ((read_data_nominal_state OR read_last_nominal_state) OR write_nominal_state);
shift_reg_width_select <= width_decoder_select;
w1019w <= (sel_type_c1 AND sel_param_bypass_LF_unused);
w1056w <= (sel_type_c1 AND sel_param_high_i_postscale);
w1092w <= (sel_type_c1 AND sel_param_odd_CP_unused);
w1127w <= (sel_type_c1 AND sel_param_low_r);
w1163w <= (sel_type_c2 AND sel_param_bypass_LF_unused);
w1196w <= (sel_type_c2 AND sel_param_high_i_postscale);
w1229w <= (sel_type_c2 AND sel_param_odd_CP_unused);
w1262w <= (sel_type_c2 AND sel_param_low_r);
w1297w <= (sel_type_c3 AND sel_param_bypass_LF_unused);
w1330w <= (sel_type_c3 AND sel_param_high_i_postscale);
w1362w <= (sel_type_c3 AND sel_param_odd_CP_unused);
w1393w <= (sel_type_c3 AND sel_param_low_r);
w1424w <= (sel_type_c4 AND sel_param_bypass_LF_unused);
w1453w <= (sel_type_c4 AND sel_param_high_i_postscale);
w1484w <= (sel_type_c4 AND sel_param_odd_CP_unused);
w1517w <= (sel_type_c4 AND sel_param_low_r);
w1565w <= '0';
w1592w <= '0';
w301w <= (sel_type_cplf AND sel_param_bypass_LF_unused);
w341w <= (sel_type_cplf AND sel_param_c);
w381w <= (sel_type_cplf AND sel_param_low_r);
w423w <= (sel_type_vco AND sel_param_high_i_postscale);
w460w <= (sel_type_cplf AND sel_param_odd_CP_unused);
w496w <= (sel_type_cplf AND sel_param_high_i_postscale);
w534w <= (sel_type_n AND sel_param_bypass_LF_unused);
w571w <= (sel_type_n AND sel_param_high_i_postscale);
w605w <= (sel_type_n AND sel_param_odd_CP_unused);
w638w <= (sel_type_n AND sel_param_low_r);
w64w <= '0';
w675w <= (sel_type_n AND sel_param_nominal_count);
w713w <= (sel_type_m AND sel_param_bypass_LF_unused);
w750w <= (sel_type_m AND sel_param_high_i_postscale);
w785w <= (sel_type_m AND sel_param_odd_CP_unused);
w818w <= (sel_type_m AND sel_param_low_r);
w851w <= (sel_type_m AND sel_param_nominal_count);
w888w <= (sel_type_c0 AND sel_param_bypass_LF_unused);
w921w <= (sel_type_c0 AND sel_param_high_i_postscale);
w952w <= (sel_type_c0 AND sel_param_odd_CP_unused);
w981w <= (sel_type_c0 AND sel_param_low_r);
width_counter_done <= (((((NOT wire_cntr3_q(0)) AND (NOT wire_cntr3_q(1))) AND (NOT wire_cntr3_q(2))) AND (NOT wire_cntr3_q(3))) AND (NOT wire_cntr3_q(4)));
width_counter_enable <= ((((read_first_state OR read_data_state) OR write_data_state) OR read_data_nominal_state) OR write_nominal_state);
width_counter_sload <= (((read_init_state OR write_init_state) OR read_init_nominal_state) OR write_init_nominal_state);
width_counter_sload_value <= width_decoder_out;
width_decoder_out <= (((((( "0" & "0" & "0" & "0" & "0") OR ( width_decoder_select(2) & "0" & "0" & "0" & width_decoder_select(2))) OR ( "0" & "0" & "0" & "0" & width_decoder_select(3))) OR ( "0" & "0" & width_decoder_select(5) & width_decoder_select(5) & width_decoder_select(5))) OR ( "0" & "0" & "0" & width_decoder_select(6) & "0")) OR ( "0" & "0" & width_decoder_select(7) & "0" & "0"));
width_decoder_select <= ( wire_w_lg_w381w495w & w496w & wire_w_lg_w_lg_w_lg_w1361w1422w1483w1550w & w1592w & wire_w_lg_w301w378w & wire_w_lg_w675w885w & w1565w & wire_w_lg_w_lg_w_lg_w1329w1392w1452w1516w);
write_from_rom <= '0';
wire_w_counter_param_latch_range294w(0) <= counter_param_latch(0);
wire_w_counter_param_latch_range296w(0) <= counter_param_latch(1);
wire_w_counter_type_latch_range284w(0) <= counter_type_latch(0);
wire_w_counter_type_latch_range286w(0) <= counter_type_latch(1);
wire_w_data_in_range186w(0) <= data_in(0);
wire_w_data_in_range178w(0) <= data_in(1);
wire_w_data_in_range170w(0) <= data_in(2);
wire_w_data_in_range162w(0) <= data_in(3);
wire_w_data_in_range154w(0) <= data_in(4);
wire_w_data_in_range146w(0) <= data_in(5);
wire_w_data_in_range138w(0) <= data_in(6);
wire_w_data_in_range130w(0) <= data_in(7);
wire_w_data_in_range122w(0) <= data_in(8);
wire_w_rotate_decoder_wires_range1807w(0) <= rotate_decoder_wires(0);
wire_w_rotate_decoder_wires_range1805w(0) <= rotate_decoder_wires(1);
wire_w_rotate_decoder_wires_range1803w(0) <= rotate_decoder_wires(2);
wire_w_rotate_decoder_wires_range1801w(0) <= rotate_decoder_wires(3);
wire_w_rotate_decoder_wires_range1799w(0) <= rotate_decoder_wires(4);
wire_w_shift_reg_width_select_range261w(0) <= shift_reg_width_select(0);
wire_w_shift_reg_width_select_range263w(0) <= shift_reg_width_select(1);
wire_w_shift_reg_width_select_range266w(0) <= shift_reg_width_select(2);
wire_w_shift_reg_width_select_range269w(0) <= shift_reg_width_select(3);
wire_w_shift_reg_width_select_range272w(0) <= shift_reg_width_select(4);
wire_w_shift_reg_width_select_range275w(0) <= shift_reg_width_select(5);
wire_w_shift_reg_width_select_range278w(0) <= shift_reg_width_select(6);
wire_w_shift_reg_width_select_range281w(0) <= shift_reg_width_select(7);
wire_altsyncram4_data_a(0) <= ( scan_cache_in);
altsyncram4 : altsyncram
GENERIC MAP (
NUMWORDS_A => 144,
OPERATION_MODE => "SINGLE_PORT",
WIDTH_A => 1,
WIDTH_BYTEENA_A => 1,
WIDTHAD_A => 8,
INTENDED_DEVICE_FAMILY => "Cyclone IV E"
)
PORT MAP (
address_a => scan_cache_address,
clock0 => clock,
data_a => wire_altsyncram4_data_a,
q_a => wire_altsyncram4_q_a,
wren_a => scan_cache_write_enable
);
le_comb10 : cycloneive_lcell_comb
GENERIC MAP (
DONT_TOUCH => "on",
LUT_MASK => "1111000011110000",
SUM_LUTC_INPUT => "datac"
)
PORT MAP (
combout => wire_le_comb10_combout,
dataa => encode_out(0),
datab => encode_out(1),
datac => encode_out(2)
);
le_comb8 : cycloneive_lcell_comb
GENERIC MAP (
DONT_TOUCH => "on",
LUT_MASK => "1010101010101010",
SUM_LUTC_INPUT => "datac"
)
PORT MAP (
combout => wire_le_comb8_combout,
dataa => encode_out(0),
datab => encode_out(1),
datac => encode_out(2)
);
le_comb9 : cycloneive_lcell_comb
GENERIC MAP (
DONT_TOUCH => "on",
LUT_MASK => "1100110011001100",
SUM_LUTC_INPUT => "datac"
)
PORT MAP (
combout => wire_le_comb9_combout,
dataa => encode_out(0),
datab => encode_out(1),
datac => encode_out(2)
);
PROCESS (clock)
BEGIN
IF (clock = '1' AND clock'event) THEN areset_init_state_1 <= pll_scandone;
END IF;
END PROCESS;
PROCESS (clock)
BEGIN
IF (clock = '1' AND clock'event) THEN areset_state <= (areset_init_state_1 AND wire_w_lg_reset1w(0));
END IF;
END PROCESS;
PROCESS (clock)
BEGIN
IF (clock = '1' AND clock'event) THEN C0_data_state <= (C0_ena_state OR (C0_data_state AND wire_w_lg_rotate_width_counter_done1776w(0)));
END IF;
END PROCESS;
PROCESS (clock)
BEGIN
IF (clock = '1' AND clock'event) THEN C0_ena_state <= (C1_data_state AND rotate_width_counter_done);
END IF;
END PROCESS;
PROCESS (clock)
BEGIN
IF (clock = '1' AND clock'event) THEN C1_data_state <= (C1_ena_state OR (C1_data_state AND wire_w_lg_rotate_width_counter_done1776w(0)));
END IF;
END PROCESS;
PROCESS (clock)
BEGIN
IF (clock = '1' AND clock'event) THEN C1_ena_state <= (C2_data_state AND rotate_width_counter_done);
END IF;
END PROCESS;
wire_C1_ena_state_w_lg_q1766w(0) <= C1_ena_state OR C3_ena_state;
PROCESS (clock)
BEGIN
IF (clock = '1' AND clock'event) THEN C2_data_state <= (C2_ena_state OR (C2_data_state AND wire_w_lg_rotate_width_counter_done1776w(0)));
END IF;
END PROCESS;
PROCESS (clock)
BEGIN
IF (clock = '1' AND clock'event) THEN C2_ena_state <= (C3_data_state AND rotate_width_counter_done);
END IF;
END PROCESS;
wire_C2_ena_state_w_lg_q1767w(0) <= C2_ena_state OR C3_ena_state;
PROCESS (clock)
BEGIN
IF (clock = '1' AND clock'event) THEN C3_data_state <= (C3_ena_state OR (C3_data_state AND wire_w_lg_rotate_width_counter_done1776w(0)));
END IF;
END PROCESS;
PROCESS (clock)
BEGIN
IF (clock = '1' AND clock'event) THEN C3_ena_state <= (C4_data_state AND rotate_width_counter_done);
END IF;
END PROCESS;
PROCESS (clock)
BEGIN
IF (clock = '1' AND clock'event) THEN C4_data_state <= (C4_ena_state OR (C4_data_state AND wire_w_lg_rotate_width_counter_done1776w(0)));
END IF;
END PROCESS;
PROCESS (clock)
BEGIN
IF (clock = '1' AND clock'event) THEN C4_ena_state <= reconfig_init_state;
END IF;
END PROCESS;
PROCESS (clock)
BEGIN
IF (clock = '1' AND clock'event) THEN configupdate2_state <= configupdate_state;
END IF;
END PROCESS;
PROCESS (clock)
BEGIN
IF (clock = '0' AND clock'event) THEN configupdate3_state <= configupdate2_state;
END IF;
END PROCESS;
wire_configupdate3_state_w_lg_q1842w(0) <= NOT configupdate3_state;
PROCESS (clock)
BEGIN
IF (clock = '1' AND clock'event) THEN configupdate_state <= reconfig_post_state;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN counter_param_latch_reg <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (input_latch_enable = '1') THEN counter_param_latch_reg <= counter_param;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN counter_type_latch_reg <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (input_latch_enable = '1') THEN counter_type_latch_reg <= counter_type;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN idle_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN idle_state <= ((wire_idle_state_w_lg_w_lg_w_lg_w1735w1736w1737w1738w(0) OR (reconfig_wait_state AND reconfig_done)) OR reset_state);
END IF;
END PROCESS;
wire_idle_state_w_lg_w_lg_w_lg_w_lg_q1731w1732w1733w1734w(0) <= wire_idle_state_w_lg_w_lg_w_lg_q1731w1732w1733w(0) AND wire_w_lg_write_from_rom1727w(0);
wire_idle_state_w_lg_w_lg_w_lg_q1731w1732w1733w(0) <= wire_idle_state_w_lg_w_lg_q1731w1732w(0) AND wire_w_lg_reconfig1728w(0);
wire_idle_state_w_lg_w_lg_q1731w1732w(0) <= wire_idle_state_w_lg_q1731w(0) AND wire_w_lg_write_param1729w(0);
wire_idle_state_w_lg_q1731w(0) <= idle_state AND wire_w_lg_read_param1730w(0);
wire_idle_state_w_lg_q1672w(0) <= NOT idle_state;
wire_idle_state_w1735w(0) <= wire_idle_state_w_lg_w_lg_w_lg_w_lg_q1731w1732w1733w1734w(0) OR read_last_state;
wire_idle_state_w_lg_w1735w1736w(0) <= wire_idle_state_w1735w(0) OR wire_write_data_state_w_lg_q1726w(0);
wire_idle_state_w_lg_w_lg_w1735w1736w1737w(0) <= wire_idle_state_w_lg_w1735w1736w(0) OR wire_write_nominal_state_w_lg_q1725w(0);
wire_idle_state_w_lg_w_lg_w_lg_w1735w1736w1737w1738w(0) <= wire_idle_state_w_lg_w_lg_w1735w1736w1737w(0) OR read_last_nominal_state;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN nominal_data0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN nominal_data0 <= wire_add_sub6_result(0);
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN nominal_data1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN nominal_data1 <= wire_add_sub6_result(1);
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN nominal_data2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN nominal_data2 <= wire_add_sub6_result(2);
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN nominal_data3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN nominal_data3 <= wire_add_sub6_result(3);
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN nominal_data4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN nominal_data4 <= wire_add_sub6_result(4);
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN nominal_data5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN nominal_data5 <= wire_add_sub6_result(5);
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN nominal_data6 <= '0';
ELSIF (clock = '1' AND clock'event) THEN nominal_data6 <= wire_add_sub6_result(6);
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN nominal_data7 <= '0';
ELSIF (clock = '1' AND clock'event) THEN nominal_data7 <= wire_add_sub6_result(7);
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN nominal_data8 <= '0';
ELSIF (clock = '1' AND clock'event) THEN nominal_data8 <= wire_w_data_in_range186w(0);
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN nominal_data9 <= '0';
ELSIF (clock = '1' AND clock'event) THEN nominal_data9 <= wire_w_data_in_range178w(0);
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN nominal_data10 <= '0';
ELSIF (clock = '1' AND clock'event) THEN nominal_data10 <= wire_w_data_in_range170w(0);
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN nominal_data11 <= '0';
ELSIF (clock = '1' AND clock'event) THEN nominal_data11 <= wire_w_data_in_range162w(0);
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN nominal_data12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN nominal_data12 <= wire_w_data_in_range154w(0);
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN nominal_data13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN nominal_data13 <= wire_w_data_in_range146w(0);
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN nominal_data14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN nominal_data14 <= wire_w_data_in_range138w(0);
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN nominal_data15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN nominal_data15 <= wire_w_data_in_range130w(0);
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN nominal_data16 <= '0';
ELSIF (clock = '1' AND clock'event) THEN nominal_data16 <= wire_w_data_in_range122w(0);
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN nominal_data17 <= '0';
ELSIF (clock = '1' AND clock'event) THEN nominal_data17 <= wire_cmpr7_aeb;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN read_data_nominal_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN read_data_nominal_state <= (wire_read_first_nominal_state_w_lg_q1753w(0) OR wire_read_data_nominal_state_w_lg_q1752w(0));
END IF;
END PROCESS;
wire_read_data_nominal_state_w_lg_q1752w(0) <= read_data_nominal_state AND wire_w_lg_width_counter_done1744w(0);
wire_read_data_nominal_state_w_lg_q1686w(0) <= NOT read_data_nominal_state;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN read_data_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN read_data_state <= (wire_read_first_state_w_lg_q1746w(0) OR wire_read_data_state_w_lg_q1745w(0));
END IF;
END PROCESS;
wire_read_data_state_w_lg_q1745w(0) <= read_data_state AND wire_w_lg_width_counter_done1744w(0);
wire_read_data_state_w_lg_q1678w(0) <= NOT read_data_state;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN read_first_nominal_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN read_first_nominal_state <= read_init_nominal_state;
END IF;
END PROCESS;
wire_read_first_nominal_state_w_lg_q1753w(0) <= read_first_nominal_state AND wire_w_lg_width_counter_done1744w(0);
wire_read_first_nominal_state_w_lg_q1684w(0) <= NOT read_first_nominal_state;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN read_first_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN read_first_state <= read_init_state;
END IF;
END PROCESS;
wire_read_first_state_w_lg_q1746w(0) <= read_first_state AND wire_w_lg_width_counter_done1744w(0);
wire_read_first_state_w_lg_q1676w(0) <= NOT read_first_state;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN read_init_nominal_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN read_init_nominal_state <= ((idle_state AND read_param) AND ((((((NOT counter_type(3)) AND (NOT counter_type(2))) AND (NOT counter_type(1))) AND counter_param(2)) AND counter_param(1)) AND counter_param(0)));
END IF;
END PROCESS;
wire_read_init_nominal_state_w_lg_q1682w(0) <= NOT read_init_nominal_state;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN read_init_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN read_init_state <= ((idle_state AND read_param) AND (NOT ((((((NOT counter_type(3)) AND (NOT counter_type(2))) AND (NOT counter_type(1))) AND counter_param(2)) AND counter_param(1)) AND counter_param(0))));
END IF;
END PROCESS;
wire_read_init_state_w_lg_q1674w(0) <= NOT read_init_state;
wire_read_init_state_w_lg_q1848w(0) <= read_init_state OR read_init_nominal_state;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN read_last_nominal_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN read_last_nominal_state <= ((read_first_nominal_state AND width_counter_done) OR (read_data_nominal_state AND width_counter_done));
END IF;
END PROCESS;
wire_read_last_nominal_state_w_lg_q1865w(0) <= read_last_nominal_state AND wire_idle_state_w_lg_q1672w(0);
wire_read_last_nominal_state_w_lg_q1688w(0) <= NOT read_last_nominal_state;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN read_last_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN read_last_state <= ((read_first_state AND width_counter_done) OR (read_data_state AND width_counter_done));
END IF;
END PROCESS;
wire_read_last_state_w_lg_q1680w(0) <= NOT read_last_state;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN reconfig_counter_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN reconfig_counter_state <= ((((((((((reconfig_init_state OR C0_data_state) OR C1_data_state) OR C2_data_state) OR C3_data_state) OR C4_data_state) OR C0_ena_state) OR C1_ena_state) OR C2_ena_state) OR C3_ena_state) OR C4_ena_state);
END IF;
END PROCESS;
wire_reconfig_counter_state_w_lg_q1700w(0) <= NOT reconfig_counter_state;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN reconfig_init_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN reconfig_init_state <= (idle_state AND reconfig);
END IF;
END PROCESS;
wire_reconfig_init_state_w_lg_q1698w(0) <= NOT reconfig_init_state;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN reconfig_post_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN reconfig_post_state <= ((reconfig_seq_data_state AND reconfig_width_counter_done) OR wire_reconfig_post_state_w_lg_q1829w(0));
END IF;
END PROCESS;
wire_reconfig_post_state_w_lg_q1829w(0) <= reconfig_post_state AND wire_w_lg_reconfig_post_done1828w(0);
wire_reconfig_post_state_w_lg_q1706w(0) <= NOT reconfig_post_state;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN reconfig_seq_data_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN reconfig_seq_data_state <= (reconfig_seq_ena_state OR (reconfig_seq_data_state AND wire_w_lg_reconfig_width_counter_done1825w(0)));
END IF;
END PROCESS;
wire_reconfig_seq_data_state_w_lg_q1704w(0) <= NOT reconfig_seq_data_state;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN reconfig_seq_ena_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN reconfig_seq_ena_state <= tmp_seq_ena_state;
END IF;
END PROCESS;
loop11 : FOR i IN 0 TO 7 GENERATE
wire_reconfig_seq_ena_state_w_lg_q1856w(i) <= reconfig_seq_ena_state AND seq_addr_wire(i);
END GENERATE loop11;
loop12 : FOR i IN 0 TO 5 GENERATE
wire_reconfig_seq_ena_state_w_lg_q1857w(i) <= reconfig_seq_ena_state AND seq_sload_value(i);
END GENERATE loop12;
wire_reconfig_seq_ena_state_w_lg_q1702w(0) <= NOT reconfig_seq_ena_state;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN reconfig_wait_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN reconfig_wait_state <= ((reconfig_post_state AND reconfig_post_done) OR wire_reconfig_wait_state_w_lg_q1833w(0));
END IF;
END PROCESS;
wire_reconfig_wait_state_w_lg_q1833w(0) <= reconfig_wait_state AND wire_w_lg_reconfig_done1832w(0);
wire_reconfig_wait_state_w_lg_q1708w(0) <= NOT reconfig_wait_state;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN reset_state <= '1';
ELSIF (clock = '1' AND clock'event) THEN reset_state <= power_up;
END IF;
END PROCESS;
wire_reset_state_w_lg_q1671w(0) <= NOT reset_state;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN shift_reg0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_shift_reg_ena(0) = '1') THEN
IF (shift_reg_clear = '1') THEN shift_reg0 <= '0';
ELSE shift_reg0 <= ((((shift_reg_load_nominal_enable AND nominal_data17) OR (shift_reg_load_enable AND w64w)) OR (shift_reg_shift_enable AND shift_reg_serial_in)) OR (shift_reg_shift_nominal_enable AND shift_reg_serial_in));
END IF;
END IF;
END IF;
END PROCESS;
wire_shift_reg_w_lg_q217w(0) <= shift_reg0 AND wire_w_lg_read_nominal_out216w(0);
wire_shift_reg_w_lg_w_lg_q217w218w(0) <= wire_shift_reg_w_lg_q217w(0) OR wire_add_sub5_w_lg_w_result_range214w215w(0);
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN shift_reg1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_shift_reg_ena(1) = '1') THEN
IF (shift_reg_clear = '1') THEN shift_reg1 <= '0';
ELSE shift_reg1 <= ((((shift_reg_load_nominal_enable AND nominal_data16) OR (shift_reg_load_enable AND w64w)) OR (shift_reg_shift_enable AND shift_reg0)) OR (shift_reg_shift_nominal_enable AND shift_reg0));
END IF;
END IF;
END IF;
END PROCESS;
wire_shift_reg_w_lg_q223w(0) <= shift_reg1 AND wire_w_lg_read_nominal_out216w(0);
wire_shift_reg_w_lg_w_lg_q223w224w(0) <= wire_shift_reg_w_lg_q223w(0) OR wire_add_sub5_w_lg_w_result_range221w222w(0);
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN shift_reg2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_shift_reg_ena(2) = '1') THEN
IF (shift_reg_clear = '1') THEN shift_reg2 <= '0';
ELSE shift_reg2 <= ((((shift_reg_load_nominal_enable AND nominal_data15) OR (shift_reg_load_enable AND w64w)) OR (shift_reg_shift_enable AND shift_reg1)) OR (shift_reg_shift_nominal_enable AND shift_reg1));
END IF;
END IF;
END IF;
END PROCESS;
wire_shift_reg_w_lg_q228w(0) <= shift_reg2 AND wire_w_lg_read_nominal_out216w(0);
wire_shift_reg_w_lg_w_lg_q228w229w(0) <= wire_shift_reg_w_lg_q228w(0) OR wire_add_sub5_w_lg_w_result_range226w227w(0);
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN shift_reg3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_shift_reg_ena(3) = '1') THEN
IF (shift_reg_clear = '1') THEN shift_reg3 <= '0';
ELSE shift_reg3 <= ((((shift_reg_load_nominal_enable AND nominal_data14) OR (shift_reg_load_enable AND w64w)) OR (shift_reg_shift_enable AND shift_reg2)) OR (shift_reg_shift_nominal_enable AND shift_reg2));
END IF;
END IF;
END IF;
END PROCESS;
wire_shift_reg_w_lg_q233w(0) <= shift_reg3 AND wire_w_lg_read_nominal_out216w(0);
wire_shift_reg_w_lg_w_lg_q233w234w(0) <= wire_shift_reg_w_lg_q233w(0) OR wire_add_sub5_w_lg_w_result_range231w232w(0);
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN shift_reg4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_shift_reg_ena(4) = '1') THEN
IF (shift_reg_clear = '1') THEN shift_reg4 <= '0';
ELSE shift_reg4 <= ((((shift_reg_load_nominal_enable AND nominal_data13) OR (shift_reg_load_enable AND w64w)) OR (shift_reg_shift_enable AND shift_reg3)) OR (shift_reg_shift_nominal_enable AND shift_reg3));
END IF;
END IF;
END IF;
END PROCESS;
wire_shift_reg_w_lg_q238w(0) <= shift_reg4 AND wire_w_lg_read_nominal_out216w(0);
wire_shift_reg_w_lg_w_lg_q238w239w(0) <= wire_shift_reg_w_lg_q238w(0) OR wire_add_sub5_w_lg_w_result_range236w237w(0);
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN shift_reg5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_shift_reg_ena(5) = '1') THEN
IF (shift_reg_clear = '1') THEN shift_reg5 <= '0';
ELSE shift_reg5 <= ((((shift_reg_load_nominal_enable AND nominal_data12) OR (shift_reg_load_enable AND w64w)) OR (shift_reg_shift_enable AND shift_reg4)) OR (shift_reg_shift_nominal_enable AND shift_reg4));
END IF;
END IF;
END IF;
END PROCESS;
wire_shift_reg_w_lg_q243w(0) <= shift_reg5 AND wire_w_lg_read_nominal_out216w(0);
wire_shift_reg_w_lg_w_lg_q243w244w(0) <= wire_shift_reg_w_lg_q243w(0) OR wire_add_sub5_w_lg_w_result_range241w242w(0);
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN shift_reg6 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_shift_reg_ena(6) = '1') THEN
IF (shift_reg_clear = '1') THEN shift_reg6 <= '0';
ELSE shift_reg6 <= ((((shift_reg_load_nominal_enable AND nominal_data11) OR (shift_reg_load_enable AND w64w)) OR (shift_reg_shift_enable AND shift_reg5)) OR (shift_reg_shift_nominal_enable AND shift_reg5));
END IF;
END IF;
END IF;
END PROCESS;
wire_shift_reg_w_lg_q248w(0) <= shift_reg6 AND wire_w_lg_read_nominal_out216w(0);
wire_shift_reg_w_lg_w_lg_q248w249w(0) <= wire_shift_reg_w_lg_q248w(0) OR wire_add_sub5_w_lg_w_result_range246w247w(0);
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN shift_reg7 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_shift_reg_ena(7) = '1') THEN
IF (shift_reg_clear = '1') THEN shift_reg7 <= '0';
ELSE shift_reg7 <= ((((shift_reg_load_nominal_enable AND nominal_data10) OR (shift_reg_load_enable AND w64w)) OR (shift_reg_shift_enable AND shift_reg6)) OR (shift_reg_shift_nominal_enable AND shift_reg6));
END IF;
END IF;
END IF;
END PROCESS;
wire_shift_reg_w_lg_q253w(0) <= shift_reg7 AND wire_w_lg_read_nominal_out216w(0);
wire_shift_reg_w_lg_w_lg_q253w254w(0) <= wire_shift_reg_w_lg_q253w(0) OR wire_add_sub5_w_lg_w_result_range251w252w(0);
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN shift_reg8 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_shift_reg_ena(8) = '1') THEN
IF (shift_reg_clear = '1') THEN shift_reg8 <= '0';
ELSE shift_reg8 <= ((((shift_reg_load_nominal_enable AND nominal_data9) OR (shift_reg_load_enable AND w64w)) OR (shift_reg_shift_enable AND shift_reg7)) OR (shift_reg_shift_nominal_enable AND shift_reg7));
END IF;
END IF;
END IF;
END PROCESS;
wire_shift_reg_w_lg_q258w(0) <= shift_reg8 AND wire_w_lg_read_nominal_out216w(0);
wire_shift_reg_w_lg_w_lg_q258w259w(0) <= wire_shift_reg_w_lg_q258w(0) OR wire_add_sub5_w_lg_w_result_range256w257w(0);
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN shift_reg9 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_shift_reg_ena(9) = '1') THEN
IF (shift_reg_clear = '1') THEN shift_reg9 <= '0';
ELSE shift_reg9 <= ((((shift_reg_load_nominal_enable AND nominal_data8) OR wire_w_lg_shift_reg_load_enable123w(0)) OR (shift_reg_shift_enable AND shift_reg8)) OR (shift_reg_shift_nominal_enable AND shift_reg8));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN shift_reg10 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_shift_reg_ena(10) = '1') THEN
IF (shift_reg_clear = '1') THEN shift_reg10 <= '0';
ELSE shift_reg10 <= ((((shift_reg_load_nominal_enable AND nominal_data7) OR wire_w_lg_shift_reg_load_enable131w(0)) OR (shift_reg_shift_enable AND shift_reg9)) OR (shift_reg_shift_nominal_enable AND shift_reg9));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN shift_reg11 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_shift_reg_ena(11) = '1') THEN
IF (shift_reg_clear = '1') THEN shift_reg11 <= '0';
ELSE shift_reg11 <= ((((shift_reg_load_nominal_enable AND nominal_data6) OR wire_w_lg_shift_reg_load_enable139w(0)) OR (shift_reg_shift_enable AND shift_reg10)) OR (shift_reg_shift_nominal_enable AND shift_reg10));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN shift_reg12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_shift_reg_ena(12) = '1') THEN
IF (shift_reg_clear = '1') THEN shift_reg12 <= '0';
ELSE shift_reg12 <= ((((shift_reg_load_nominal_enable AND nominal_data5) OR wire_w_lg_shift_reg_load_enable147w(0)) OR (shift_reg_shift_enable AND shift_reg11)) OR (shift_reg_shift_nominal_enable AND shift_reg11));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN shift_reg13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_shift_reg_ena(13) = '1') THEN
IF (shift_reg_clear = '1') THEN shift_reg13 <= '0';
ELSE shift_reg13 <= ((((shift_reg_load_nominal_enable AND nominal_data4) OR wire_w_lg_shift_reg_load_enable155w(0)) OR (shift_reg_shift_enable AND shift_reg12)) OR (shift_reg_shift_nominal_enable AND shift_reg12));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN shift_reg14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_shift_reg_ena(14) = '1') THEN
IF (shift_reg_clear = '1') THEN shift_reg14 <= '0';
ELSE shift_reg14 <= ((((shift_reg_load_nominal_enable AND nominal_data3) OR wire_w_lg_shift_reg_load_enable163w(0)) OR (shift_reg_shift_enable AND shift_reg13)) OR (shift_reg_shift_nominal_enable AND shift_reg13));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN shift_reg15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_shift_reg_ena(15) = '1') THEN
IF (shift_reg_clear = '1') THEN shift_reg15 <= '0';
ELSE shift_reg15 <= ((((shift_reg_load_nominal_enable AND nominal_data2) OR wire_w_lg_shift_reg_load_enable171w(0)) OR (shift_reg_shift_enable AND shift_reg14)) OR (shift_reg_shift_nominal_enable AND shift_reg14));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN shift_reg16 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_shift_reg_ena(16) = '1') THEN
IF (shift_reg_clear = '1') THEN shift_reg16 <= '0';
ELSE shift_reg16 <= ((((shift_reg_load_nominal_enable AND nominal_data1) OR wire_w_lg_shift_reg_load_enable179w(0)) OR (shift_reg_shift_enable AND shift_reg15)) OR (shift_reg_shift_nominal_enable AND shift_reg15));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN shift_reg17 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_shift_reg_ena(17) = '1') THEN
IF (shift_reg_clear = '1') THEN shift_reg17 <= '0';
ELSE shift_reg17 <= ((((shift_reg_load_nominal_enable AND nominal_data0) OR wire_w_lg_shift_reg_load_enable187w(0)) OR (shift_reg_shift_enable AND shift_reg16)) OR (shift_reg_shift_nominal_enable AND shift_reg16));
END IF;
END IF;
END IF;
END PROCESS;
wire_shift_reg_w_lg_q262w(0) <= shift_reg17 AND wire_w_shift_reg_width_select_range261w(0);
wire_shift_reg_w_lg_q264w(0) <= shift_reg17 AND wire_w_shift_reg_width_select_range263w(0);
wire_shift_reg_w_lg_q267w(0) <= shift_reg17 AND wire_w_shift_reg_width_select_range266w(0);
wire_shift_reg_w_lg_q270w(0) <= shift_reg17 AND wire_w_shift_reg_width_select_range269w(0);
wire_shift_reg_w_lg_q273w(0) <= shift_reg17 AND wire_w_shift_reg_width_select_range272w(0);
wire_shift_reg_w_lg_q276w(0) <= shift_reg17 AND wire_w_shift_reg_width_select_range275w(0);
wire_shift_reg_w_lg_q279w(0) <= shift_reg17 AND wire_w_shift_reg_width_select_range278w(0);
wire_shift_reg_w_lg_q282w(0) <= shift_reg17 AND wire_w_shift_reg_width_select_range281w(0);
loop13 : FOR i IN 0 TO 17 GENERATE
wire_shift_reg_ena(i) <= wire_w63w(0);
END GENERATE loop13;
PROCESS (clock)
BEGIN
IF (clock = '1' AND clock'event) THEN tmp_nominal_data_out_state <= (wire_read_last_nominal_state_w_lg_q1865w(0) OR (tmp_nominal_data_out_state AND idle_state));
END IF;
END PROCESS;
PROCESS (clock)
BEGIN
IF (clock = '1' AND clock'event) THEN tmp_seq_ena_state <= (reconfig_counter_state AND (C0_data_state AND rotate_width_counter_done));
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN write_data_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN write_data_state <= (write_init_state OR (write_data_state AND wire_w_lg_width_counter_done1744w(0)));
END IF;
END PROCESS;
wire_write_data_state_w_lg_q1726w(0) <= write_data_state AND width_counter_done;
wire_write_data_state_w_lg_q1692w(0) <= NOT write_data_state;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN write_init_nominal_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN write_init_nominal_state <= ((idle_state AND write_param) AND ((((((NOT counter_type(3)) AND (NOT counter_type(2))) AND (NOT counter_type(1))) AND counter_param(2)) AND counter_param(1)) AND counter_param(0)));
END IF;
END PROCESS;
wire_write_init_nominal_state_w_lg_q1694w(0) <= NOT write_init_nominal_state;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN write_init_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN write_init_state <= ((idle_state AND write_param) AND (NOT ((((((NOT counter_type(3)) AND (NOT counter_type(2))) AND (NOT counter_type(1))) AND counter_param(2)) AND counter_param(1)) AND counter_param(0))));
END IF;
END PROCESS;
wire_write_init_state_w_lg_q1690w(0) <= NOT write_init_state;
wire_write_init_state_w_lg_q1853w(0) <= write_init_state OR write_init_nominal_state;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN write_nominal_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN write_nominal_state <= (write_init_nominal_state OR (write_nominal_state AND wire_w_lg_width_counter_done1744w(0)));
END IF;
END PROCESS;
wire_write_nominal_state_w_lg_q1725w(0) <= write_nominal_state AND width_counter_done;
wire_write_nominal_state_w_lg_q1696w(0) <= NOT write_nominal_state;
wire_add_sub5_w_lg_w_result_range214w215w(0) <= wire_add_sub5_w_result_range214w(0) AND read_nominal_out;
wire_add_sub5_w_lg_w_result_range221w222w(0) <= wire_add_sub5_w_result_range221w(0) AND read_nominal_out;
wire_add_sub5_w_lg_w_result_range226w227w(0) <= wire_add_sub5_w_result_range226w(0) AND read_nominal_out;
wire_add_sub5_w_lg_w_result_range231w232w(0) <= wire_add_sub5_w_result_range231w(0) AND read_nominal_out;
wire_add_sub5_w_lg_w_result_range236w237w(0) <= wire_add_sub5_w_result_range236w(0) AND read_nominal_out;
wire_add_sub5_w_lg_w_result_range241w242w(0) <= wire_add_sub5_w_result_range241w(0) AND read_nominal_out;
wire_add_sub5_w_lg_w_result_range246w247w(0) <= wire_add_sub5_w_result_range246w(0) AND read_nominal_out;
wire_add_sub5_w_lg_w_result_range251w252w(0) <= wire_add_sub5_w_result_range251w(0) AND read_nominal_out;
wire_add_sub5_w_lg_w_result_range256w257w(0) <= wire_add_sub5_w_result_range256w(0) AND read_nominal_out;
wire_add_sub5_dataa <= ( "0" & shift_reg8 & shift_reg7 & shift_reg6 & shift_reg5 & shift_reg4 & shift_reg3 & shift_reg2 & shift_reg1);
wire_add_sub5_datab <= ( "0" & shift_reg17 & shift_reg16 & shift_reg15 & shift_reg14 & shift_reg13 & shift_reg12 & shift_reg11 & shift_reg10);
wire_add_sub5_w_result_range214w(0) <= wire_add_sub5_result(0);
wire_add_sub5_w_result_range221w(0) <= wire_add_sub5_result(1);
wire_add_sub5_w_result_range226w(0) <= wire_add_sub5_result(2);
wire_add_sub5_w_result_range231w(0) <= wire_add_sub5_result(3);
wire_add_sub5_w_result_range236w(0) <= wire_add_sub5_result(4);
wire_add_sub5_w_result_range241w(0) <= wire_add_sub5_result(5);
wire_add_sub5_w_result_range246w(0) <= wire_add_sub5_result(6);
wire_add_sub5_w_result_range251w(0) <= wire_add_sub5_result(7);
wire_add_sub5_w_result_range256w(0) <= wire_add_sub5_result(8);
add_sub5 : lpm_add_sub
GENERIC MAP (
LPM_WIDTH => 9
)
PORT MAP (
cin => wire_gnd,
dataa => wire_add_sub5_dataa,
datab => wire_add_sub5_datab,
result => wire_add_sub5_result
);
wire_add_sub6_dataa <= ( data_in(8 DOWNTO 1));
add_sub6 : lpm_add_sub
GENERIC MAP (
LPM_WIDTH => 8
)
PORT MAP (
cin => data_in(0),
dataa => wire_add_sub6_dataa,
result => wire_add_sub6_result
);
wire_cmpr7_dataa <= ( data_in(7 DOWNTO 0));
wire_cmpr7_datab <= "00000001";
cmpr7 : lpm_compare
GENERIC MAP (
LPM_WIDTH => 8
)
PORT MAP (
aeb => wire_cmpr7_aeb,
dataa => wire_cmpr7_dataa,
datab => wire_cmpr7_datab
);
cntr1 : lpm_counter
GENERIC MAP (
lpm_direction => "DOWN",
lpm_modulus => 144,
lpm_port_updown => "PORT_UNUSED",
lpm_width => 8
)
PORT MAP (
clock => clock,
cnt_en => addr_counter_enable,
data => addr_counter_sload_value,
q => wire_cntr1_q,
sload => addr_counter_sload
);
cntr12 : lpm_counter
GENERIC MAP (
lpm_direction => "DOWN",
lpm_modulus => 144,
lpm_port_updown => "PORT_UNUSED",
lpm_width => 8
)
PORT MAP (
clock => clock,
cnt_en => reconfig_addr_counter_enable,
data => reconfig_addr_counter_sload_value,
q => wire_cntr12_q,
sload => reconfig_addr_counter_sload
);
cntr13 : lpm_counter
GENERIC MAP (
lpm_direction => "DOWN",
lpm_port_updown => "PORT_UNUSED",
lpm_width => 6
)
PORT MAP (
clock => clock,
cnt_en => reconfig_width_counter_enable,
data => reconfig_width_counter_sload_value,
q => wire_cntr13_q,
sload => reconfig_width_counter_sload
);
cntr14 : lpm_counter
GENERIC MAP (
lpm_direction => "DOWN",
lpm_port_updown => "PORT_UNUSED",
lpm_width => 5
)
PORT MAP (
clock => clock,
cnt_en => rotate_width_counter_enable,
data => rotate_width_counter_sload_value,
q => wire_cntr14_q,
sload => rotate_width_counter_sload
);
cntr15 : lpm_counter
GENERIC MAP (
lpm_direction => "DOWN",
lpm_modulus => 144,
lpm_port_updown => "PORT_UNUSED",
lpm_width => 8
)
PORT MAP (
clock => clock,
cnt_en => rotate_addr_counter_enable,
data => rotate_addr_counter_sload_value,
q => wire_cntr15_q,
sload => rotate_addr_counter_sload
);
cntr2 : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_width => 8
)
PORT MAP (
clock => clock,
cnt_en => read_addr_counter_enable,
data => read_addr_counter_sload_value,
q => wire_cntr2_q,
sload => read_addr_counter_sload
);
cntr3 : lpm_counter
GENERIC MAP (
lpm_direction => "DOWN",
lpm_port_updown => "PORT_UNUSED",
lpm_width => 5
)
PORT MAP (
clock => clock,
cnt_en => width_counter_enable,
data => width_counter_sload_value,
q => wire_cntr3_q,
sload => width_counter_sload
);
decode11 : lpm_decode
GENERIC MAP (
LPM_DECODES => 5,
LPM_WIDTH => 3
)
PORT MAP (
data => cuda_combout_wire,
eq => wire_decode11_eq
);
END RTL; --PLL_RECONFIG_pllrcfg_66q
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY PLL_RECONFIG IS
PORT
(
clock : IN STD_LOGIC ;
counter_param : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
counter_type : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data_in : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
pll_areset_in : IN STD_LOGIC := '0';
pll_scandataout : IN STD_LOGIC ;
pll_scandone : IN STD_LOGIC ;
read_param : IN STD_LOGIC ;
reconfig : IN STD_LOGIC ;
reset : IN STD_LOGIC ;
write_param : IN STD_LOGIC ;
busy : OUT STD_LOGIC ;
data_out : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
pll_areset : OUT STD_LOGIC ;
pll_configupdate : OUT STD_LOGIC ;
pll_scanclk : OUT STD_LOGIC ;
pll_scanclkena : OUT STD_LOGIC ;
pll_scandata : OUT STD_LOGIC
);
END PLL_RECONFIG;
ARCHITECTURE RTL OF pll_reconfig IS
ATTRIBUTE synthesis_clearbox: natural;
ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS 2;
ATTRIBUTE clearbox_macroname: string;
ATTRIBUTE clearbox_macroname OF RTL: ARCHITECTURE IS "altpll_reconfig";
ATTRIBUTE clearbox_defparam: string;
ATTRIBUTE clearbox_defparam OF RTL: ARCHITECTURE IS "init_from_external_rom_checkbox_checked=NO;intended_device_family=Cyclone IV E;";
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
COMPONENT PLL_RECONFIG_pllrcfg_66q
PORT (
clock : IN STD_LOGIC ;
counter_param : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
counter_type : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data_in : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
pll_areset_in : IN STD_LOGIC ;
pll_scandataout : IN STD_LOGIC ;
pll_scandone : IN STD_LOGIC ;
read_param : IN STD_LOGIC ;
reconfig : IN STD_LOGIC ;
reset : IN STD_LOGIC ;
write_param : IN STD_LOGIC ;
busy : OUT STD_LOGIC ;
data_out : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
pll_areset : OUT STD_LOGIC ;
pll_configupdate : OUT STD_LOGIC ;
pll_scanclk : OUT STD_LOGIC ;
pll_scanclkena : OUT STD_LOGIC ;
pll_scandata : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
busy <= sub_wire0;
data_out <= sub_wire1(8 DOWNTO 0);
pll_areset <= sub_wire2;
pll_configupdate <= sub_wire3;
pll_scanclk <= sub_wire4;
pll_scanclkena <= sub_wire5;
pll_scandata <= sub_wire6;
PLL_RECONFIG_pllrcfg_66q_component : PLL_RECONFIG_pllrcfg_66q
PORT MAP (
clock => clock,
counter_param => counter_param,
counter_type => counter_type,
data_in => data_in,
pll_areset_in => pll_areset_in,
pll_scandataout => pll_scandataout,
pll_scandone => pll_scandone,
read_param => read_param,
reconfig => reconfig,
reset => reset,
write_param => write_param,
busy => sub_wire0,
data_out => sub_wire1,
pll_areset => sub_wire2,
pll_configupdate => sub_wire3,
pll_scanclk => sub_wire4,
pll_scanclkena => sub_wire5,
pll_scandata => sub_wire6
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: CHAIN_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_NAME STRING ""
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_INIT_FILE STRING "0"
-- Retrieval info: CONSTANT: INIT_FROM_EXTERNAL_ROM_CHECKBOX_CHECKED STRING "NO"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: counter_param 0 0 3 0 INPUT NODEFVAL "counter_param[2..0]"
-- Retrieval info: USED_PORT: counter_type 0 0 4 0 INPUT NODEFVAL "counter_type[3..0]"
-- Retrieval info: USED_PORT: data_in 0 0 9 0 INPUT NODEFVAL "data_in[8..0]"
-- Retrieval info: USED_PORT: data_out 0 0 9 0 OUTPUT NODEFVAL "data_out[8..0]"
-- Retrieval info: USED_PORT: pll_areset 0 0 0 0 OUTPUT NODEFVAL "pll_areset"
-- Retrieval info: USED_PORT: pll_areset_in 0 0 0 0 INPUT GND "pll_areset_in"
-- Retrieval info: USED_PORT: pll_configupdate 0 0 0 0 OUTPUT NODEFVAL "pll_configupdate"
-- Retrieval info: USED_PORT: pll_scanclk 0 0 0 0 OUTPUT NODEFVAL "pll_scanclk"
-- Retrieval info: USED_PORT: pll_scanclkena 0 0 0 0 OUTPUT NODEFVAL "pll_scanclkena"
-- Retrieval info: USED_PORT: pll_scandata 0 0 0 0 OUTPUT NODEFVAL "pll_scandata"
-- Retrieval info: USED_PORT: pll_scandataout 0 0 0 0 INPUT NODEFVAL "pll_scandataout"
-- Retrieval info: USED_PORT: pll_scandone 0 0 0 0 INPUT NODEFVAL "pll_scandone"
-- Retrieval info: USED_PORT: read_param 0 0 0 0 INPUT NODEFVAL "read_param"
-- Retrieval info: USED_PORT: reconfig 0 0 0 0 INPUT NODEFVAL "reconfig"
-- Retrieval info: USED_PORT: reset 0 0 0 0 INPUT NODEFVAL "reset"
-- Retrieval info: USED_PORT: write_param 0 0 0 0 INPUT NODEFVAL "write_param"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @counter_param 0 0 3 0 counter_param 0 0 3 0
-- Retrieval info: CONNECT: @counter_type 0 0 4 0 counter_type 0 0 4 0
-- Retrieval info: CONNECT: @data_in 0 0 9 0 data_in 0 0 9 0
-- Retrieval info: CONNECT: @pll_areset_in 0 0 0 0 pll_areset_in 0 0 0 0
-- Retrieval info: CONNECT: @pll_scandataout 0 0 0 0 pll_scandataout 0 0 0 0
-- Retrieval info: CONNECT: @pll_scandone 0 0 0 0 pll_scandone 0 0 0 0
-- Retrieval info: CONNECT: @read_param 0 0 0 0 read_param 0 0 0 0
-- Retrieval info: CONNECT: @reconfig 0 0 0 0 reconfig 0 0 0 0
-- Retrieval info: CONNECT: @reset 0 0 0 0 reset 0 0 0 0
-- Retrieval info: CONNECT: @write_param 0 0 0 0 write_param 0 0 0 0
-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
-- Retrieval info: CONNECT: data_out 0 0 9 0 @data_out 0 0 9 0
-- Retrieval info: CONNECT: pll_areset 0 0 0 0 @pll_areset 0 0 0 0
-- Retrieval info: CONNECT: pll_configupdate 0 0 0 0 @pll_configupdate 0 0 0 0
-- Retrieval info: CONNECT: pll_scanclk 0 0 0 0 @pll_scanclk 0 0 0 0
-- Retrieval info: CONNECT: pll_scanclkena 0 0 0 0 @pll_scanclkena 0 0 0 0
-- Retrieval info: CONNECT: pll_scandata 0 0 0 0 @pll_scandata 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL_RECONFIG.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL_RECONFIG.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL_RECONFIG.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL_RECONFIG.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL_RECONFIG_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: LIB_FILE: cycloneive
-- Retrieval info: LIB_FILE: lpm
|
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity ClkGen is
port (
CLK : out std_logic;
RST : out std_logic
);
end entity ClkGen;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture ClkGen_rtl of ClkGen is
constant CLOCK_PERIOD : time := 10 ns;
signal clk_s : std_logic := '0';
signal rst_s : std_logic := '0';
begin
-- Clock generator (50% duty cycle)
clk_gen: process
begin
clk_s <= '0';
wait for CLOCK_PERIOD/2;
clk_s <= '1';
wait for CLOCK_PERIOD/2;
end process clk_gen;
CLK <= clk_s;
reset_gen: process
begin
wait until rising_edge(clk_s);
rst_s <= '0';
wait until rising_edge(clk_s);
rst_s <= '1';
wait until rising_edge(clk_s);
rst_s <= '0';
wait;
end process reset_gen;
RST <= rst_s;
end architecture ClkGen_rtl; |
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity ClkGen is
port (
CLK : out std_logic;
RST : out std_logic
);
end entity ClkGen;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture ClkGen_rtl of ClkGen is
constant CLOCK_PERIOD : time := 10 ns;
signal clk_s : std_logic := '0';
signal rst_s : std_logic := '0';
begin
-- Clock generator (50% duty cycle)
clk_gen: process
begin
clk_s <= '0';
wait for CLOCK_PERIOD/2;
clk_s <= '1';
wait for CLOCK_PERIOD/2;
end process clk_gen;
CLK <= clk_s;
reset_gen: process
begin
wait until rising_edge(clk_s);
rst_s <= '0';
wait until rising_edge(clk_s);
rst_s <= '1';
wait until rising_edge(clk_s);
rst_s <= '0';
wait;
end process reset_gen;
RST <= rst_s;
end architecture ClkGen_rtl; |
----------------------------------------------------------------------------------
-- Company: Nameless2
-- Engineer: Ana María Martínez Gómez, Aitor Alonso Lorenzo, Víctor Adolfo Gallego Alcalá
--
-- Create Date: 12:15:23 11/18/2013
-- Design Name:
-- Module Name: conversor - Behavioral
-- Project Name: Representación gráfica de funciones
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
entity conversor is
port( caso : in std_logic_vector(1 downto 0);
numPuntos : in std_logic_vector(6 downto 0);
fin_pantalla: in std_logic;
avanza: in std_logic;
punto: in std_logic_vector(20 downto 0);
reset, clk: in std_logic;
punto1X, punto2X, punto1Y, punto2Y: out std_logic_vector(6 downto 0);
enable_pantalla, fin_conv, inf: out std_logic;
indice_o: out std_logic_vector(4 downto 0)); -- Para mostrarlo en la barra de LEDs
end conversor;
architecture Behavioral of conversor is
constant ENT : integer := 11;
constant DEC : integer := 10;
constant nB: integer := 6;
type matrizPuntos is array(0 to 31) of std_logic_vector(31 downto 0);
signal puntos, puntosAux: matrizPuntos;
signal indice, indice3: std_logic_vector(4 downto 0);
signal salida1Y, salida2Y: std_logic_vector(6 downto 0);
signal estado, estado_sig: std_logic_vector(6 downto 0);
signal estado2, estado2_sig: std_logic_vector(1 downto 0);
signal vAcc, vAccAux: std_logic_vector(DEC+ENT-1 downto 6);
type matrizX is array(0 to 32) of std_logic_vector(6 downto 0);
signal puntos1X: matrizX;
type matrizX2 is array(0 to 31) of std_logic_vector(6 downto 0);
signal puntos2X, puntos3X : matrizX2;
begin
puntos1X(0) <= "0000000";
puntos1X(1) <= "0000100";
puntos1X(2) <= "0001000";
puntos1X(3) <= "0001100";
puntos1X(4) <= "0010000";
puntos1X(5) <= "0010100";
puntos1X(6) <= "0011000";
puntos1X(7) <= "0011100";
puntos1X(8) <= "0100000";
puntos1X(9) <= "0100100";
puntos1X(10) <= "0101000";
puntos1X(11) <= "0101100";
puntos1X(12) <= "0110000";
puntos1X(13) <= "0110100";
puntos1X(14) <= "0111000";
puntos1X(15) <= "0111100";
puntos1X(16) <= "1000000";
puntos1X(17) <= "1000100";
puntos1X(18) <= "1001000";
puntos1X(19) <= "1001100";
puntos1X(20) <= "1010000";
puntos1X(21) <= "1010100";
puntos1X(22) <= "1011000";
puntos1X(23) <= "1011100";
puntos1X(24) <= "1100000";
puntos1X(25) <= "1100100";
puntos1X(26) <= "1101000";
puntos1X(27) <= "1101100";
puntos1X(28) <= "1110000";
puntos1X(29) <= "1110100";
puntos1X(30) <= "1111000";
puntos1X(31) <= "1111100";
puntos1X(32) <= "1111111";
puntos2X(0) <= "0000000";
puntos2X(1) <= "0001000";
puntos2X(2) <= "0001100";
puntos2X(3) <= "0010000";
puntos2X(4) <= "0010100";
puntos2X(5) <= "0011000";
puntos2X(6) <= "0011100";
puntos2X(7) <= "0100000";
puntos2X(8) <= "0100100";
puntos2X(9) <= "0101000";
puntos2X(10) <= "0101100";
puntos2X(11) <= "0110000";
puntos2X(12) <= "0110100";
puntos2X(13) <= "0111000";
puntos2X(14) <= "0111100";
puntos2X(15) <= "1000000";
puntos2X(16) <= "1000100";
puntos2X(17) <= "1001000";
puntos2X(18) <= "1001100";
puntos2X(19) <= "1010000";
puntos2X(20) <= "1010100";
puntos2X(21) <= "1011000";
puntos2X(22) <= "1011100";
puntos2X(23) <= "1100000";
puntos2X(24) <= "1100100";
puntos2X(25) <= "1101000";
puntos2X(26) <= "1101100";
puntos2X(27) <= "1110000";
puntos2X(28) <= "1110100";
puntos2X(29) <= "1111000";
puntos2X(30) <= "1111100";
puntos2X(31) <= "1111111";
puntos3X(0) <= "0000000";
puntos3X(1) <= "0000100";
puntos3X(2) <= "0001000";
puntos3X(3) <= "0001100";
puntos3X(4) <= "0010000";
puntos3X(5) <= "0010100";
puntos3X(6) <= "0011000";
puntos3X(7) <= "0011100";
puntos3X(8) <= "0100000";
puntos3X(9) <= "0100100";
puntos3X(10) <= "0101000";
puntos3X(11) <= "0101100";
puntos3X(12) <= "0110000";
puntos3X(13) <= "0110100";
puntos3X(14) <= "0111000";
puntos3X(15) <= "0111100";
puntos3X(16) <= "1000100";
puntos3X(17) <= "1001000";
puntos3X(18) <= "1001100";
puntos3X(19) <= "1010000";
puntos3X(20) <= "1010100";
puntos3X(21) <= "1011000";
puntos3X(22) <= "1011100";
puntos3X(23) <= "1100000";
puntos3X(24) <= "1100100";
puntos3X(25) <= "1101000";
puntos3X(26) <= "1101100";
puntos3X(27) <= "1110000";
puntos3X(28) <= "1110100";
puntos3X(29) <= "1111000";
puntos3X(30) <= "1111100";
puntos3X(31) <= "1111111";
index: process(vAcc, estado2)
begin
-- En función del bit más significativo a 1 (permanece en todo a 1 tras realizar las or(ver el estado "10"), una posición a la izquierda
-- de ese bit será el índice. La conversión a coordenadas de pantalla consiste en, a partir de ese bit y hacia
-- la derecha, tomar 7 bits (un punto de la pantalla)
indice <= "00110";
bucle1: for i in 6 to 20 loop
if estado2 = "01" or estado2 = "10" or estado2 = "11" then
if vAcc(i) = '1' then
indice <= conv_std_logic_vector(i+1, 5);
end if;
end if;
end loop bucle1;
end process index;
sincrono: process(clk, reset, estado2_sig, estado_sig)
begin
if reset = '1' then
estado2 <= ( others => '0');
estado <= ( others => '0');
elsif clk'event and clk = '1' then
estado2 <= estado2_sig;
estado <= estado_sig;
end if;
end process sincrono;
maquina: process(estado2, fin_pantalla, punto, avanza, puntos, estado, vAcc, numPuntos, caso)
begin
inf <= '0';
puntosAux <= puntos;
vAccAux <= vAcc;
salida1Y <= (others=>'0');
salida2Y <= (others=>'0');
case estado2 is
-- Estado de inicio
when "00" =>
vAccAux <= (others => '0');
fin_conv <= '1';
enable_pantalla <= '0';
estado_sig <= estado;
if avanza = '1' then
estado2_sig <= "01";
else
estado2_sig <= "00";
end if;
-- Estado 01: de guardado de puntos. Se guardan en puntos, y vAcc (en este último, como valor absoluto,
-- con el fin de poder obtener el índice necesario realizar el reescalado a coordenadas de pantalla, basándonos
-- en realizar sucesivas OR lógicas con el fin de obtener el índice (factor para la escala vertical).
when "01" =>
fin_conv <= '0';
enable_pantalla <= '0';
if punto(20)='1' then
puntosAux(conv_integer(unsigned(estado))) <= "11111111111" & punto;
vAccAux <= vAcc or ("000000000000" - punto(DEC+ENT-1 downto 6));
else
vAccAux <= vAcc or punto(DEC+ENT-1 downto 6);
puntosAux(conv_integer(unsigned(estado))) <= "00000000000" & punto;
end if;
estado_sig <= estado;
if avanza ='1' then
if estado = numPuntos-1 then
estado2_sig <= "10";
estado_sig <= (others => '0');
else
estado_sig <= estado +1;
estado2_sig <= "01";
end if;
else
estado_sig <= estado;
estado2_sig <= estado2;
end if;
-- En el siguiente estado se manda un par de puntos a la pantalla. Los puntos han sigo guardados en los estados
-- anteriores, por tanto la señal indice tiene el valor correcto con el fin de tomar el subvector para realizar
-- el reescalado.
-- Debido a las características de la algoritmia de la pantalla, estado 10 y 11 son iguales, salvo que en el primero
-- únicamente estamos un ciclo con enable_pantalla a 1.
when "10" =>
if estado = "0000000" and caso(1)='0' then
inf <= '1';
elsif estado = numPuntos(6 downto 1) -1 and caso = "10" then
inf <= '1';
else
inf <= '0';
end if;
enable_pantalla <= '1';
fin_conv <= '0';
salida1Y <= puntos(conv_integer(unsigned(estado)))(conv_integer(unsigned(indice)) downto conv_integer(unsigned(indice))-6);
salida2Y <= puntos(conv_integer(unsigned(estado))+1)(conv_integer(unsigned(indice)) downto conv_integer(unsigned(indice))-6);
estado2_sig <= "11";
estado_sig <= estado;
when "11" =>
if estado = "0000000" and caso(1)='0' then
inf <= '1';
elsif estado = numPuntos(6 downto 1) -1 and caso = "10" then
inf <= '1';
else
inf <= '0';
end if;
fin_conv <= '0';
salida1Y <= puntos(conv_integer(unsigned(estado)))(conv_integer(unsigned(indice)) downto conv_integer(unsigned(indice))-6);
salida2Y <= puntos(conv_integer(unsigned(estado))+1)(conv_integer(unsigned(indice)) downto conv_integer(unsigned(indice))-6);
enable_pantalla <= '0';
if fin_pantalla = '1' then
if estado = numPuntos-2 then
estado_sig <= (others => '0');
estado2_sig <= "00";
else
estado_sig <= estado +1;
estado2_sig <= "10";
end if;
else
estado2_sig <= estado2;
estado_sig <= estado;
end if;
-- Una vez hemos obtenido el subvector de longitud 7 usando el indice, hacemos 64 - eso, con el fin
-- de ajustar a las coordenadas en la pantalla.
--Ejemplo: las coordenadas verticales de la pantalla son de esta manera
--
-- 0 (lim. sup)
--
--
-- 64 (eje horizontal)
--
--
-- 127 (lim.inf).
-- Así, si por ejemplo tenemos los f(x) = 2, f(y) = 3, al tomar con el índice teniendo en cuenta las
-- or anteriores quedarían 0100000 (=32) (para el 2) y 0110000 (=48) (para el 3). Realizando 64 - lo anterior, quedarían
-- las coordenadas 32 y 16, respectivamente. De forma similar, si f(x) fuera negativo, su coordenada sería mayor
-- que 64, quedando por debajo del eje horizontal.
when others =>
end case;
end process maquina;
process(clk)
begin
if clk'event and clk = '1' then
if estado2 = "11" then
indice3 <= indice;
else
indice3 <= indice3;
end if;
end if;
end process;
p_outX: process(puntos1X, puntos2X, estado, estado2, caso, puntos3X)
begin
if estado2 = "10" or estado2 = "11" then
if caso = "00" then
punto1X <= puntos1X(conv_integer(unsigned(estado)));
punto2X <= puntos1X(conv_integer(unsigned(estado))+1);
elsif caso = "01" then
punto1X <= puntos2X(conv_integer(unsigned(estado)));
punto2X <= puntos2X(conv_integer(unsigned(estado))+1);
else
punto1X <= puntos3X(conv_integer(unsigned(estado)));
punto2X <= puntos3X(conv_integer(unsigned(estado))+1);
end if;
else
punto1X <= (others => '1');
punto2X <= (others => '1');
end if;
end process p_outX;
registros: process (clk, reset, vAccAux, puntosAux, estado2_sig, estado_sig)
begin
if reset = '1' then
puntos <= (others => "00000000000000000000000000000000");
vAcc <= (others => '0');
estado2 <= (others => '0');
estado <= (others => '0');
elsif clk'event and clk = '1' then
puntos <= puntosAux;
vAcc <= vAccAux;
estado <= estado_sig;
estado2 <= estado2_sig;
end if;
end process registros;
punto1Y <= 64 - salida1Y;
punto2Y <= 64 - salida2Y;
-- Escala y: 1 unidad equivale a 2^(indice-13), por lo que indice_o representará este exponente
indice_o <= unsigned(indice3)-13 ;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company: Nameless2
-- Engineer: Ana María Martínez Gómez, Aitor Alonso Lorenzo, Víctor Adolfo Gallego Alcalá
--
-- Create Date: 12:15:23 11/18/2013
-- Design Name:
-- Module Name: conversor - Behavioral
-- Project Name: Representación gráfica de funciones
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
entity conversor is
port( caso : in std_logic_vector(1 downto 0);
numPuntos : in std_logic_vector(6 downto 0);
fin_pantalla: in std_logic;
avanza: in std_logic;
punto: in std_logic_vector(20 downto 0);
reset, clk: in std_logic;
punto1X, punto2X, punto1Y, punto2Y: out std_logic_vector(6 downto 0);
enable_pantalla, fin_conv, inf: out std_logic;
indice_o: out std_logic_vector(4 downto 0)); -- Para mostrarlo en la barra de LEDs
end conversor;
architecture Behavioral of conversor is
constant ENT : integer := 11;
constant DEC : integer := 10;
constant nB: integer := 6;
type matrizPuntos is array(0 to 31) of std_logic_vector(31 downto 0);
signal puntos, puntosAux: matrizPuntos;
signal indice, indice3: std_logic_vector(4 downto 0);
signal salida1Y, salida2Y: std_logic_vector(6 downto 0);
signal estado, estado_sig: std_logic_vector(6 downto 0);
signal estado2, estado2_sig: std_logic_vector(1 downto 0);
signal vAcc, vAccAux: std_logic_vector(DEC+ENT-1 downto 6);
type matrizX is array(0 to 32) of std_logic_vector(6 downto 0);
signal puntos1X: matrizX;
type matrizX2 is array(0 to 31) of std_logic_vector(6 downto 0);
signal puntos2X, puntos3X : matrizX2;
begin
puntos1X(0) <= "0000000";
puntos1X(1) <= "0000100";
puntos1X(2) <= "0001000";
puntos1X(3) <= "0001100";
puntos1X(4) <= "0010000";
puntos1X(5) <= "0010100";
puntos1X(6) <= "0011000";
puntos1X(7) <= "0011100";
puntos1X(8) <= "0100000";
puntos1X(9) <= "0100100";
puntos1X(10) <= "0101000";
puntos1X(11) <= "0101100";
puntos1X(12) <= "0110000";
puntos1X(13) <= "0110100";
puntos1X(14) <= "0111000";
puntos1X(15) <= "0111100";
puntos1X(16) <= "1000000";
puntos1X(17) <= "1000100";
puntos1X(18) <= "1001000";
puntos1X(19) <= "1001100";
puntos1X(20) <= "1010000";
puntos1X(21) <= "1010100";
puntos1X(22) <= "1011000";
puntos1X(23) <= "1011100";
puntos1X(24) <= "1100000";
puntos1X(25) <= "1100100";
puntos1X(26) <= "1101000";
puntos1X(27) <= "1101100";
puntos1X(28) <= "1110000";
puntos1X(29) <= "1110100";
puntos1X(30) <= "1111000";
puntos1X(31) <= "1111100";
puntos1X(32) <= "1111111";
puntos2X(0) <= "0000000";
puntos2X(1) <= "0001000";
puntos2X(2) <= "0001100";
puntos2X(3) <= "0010000";
puntos2X(4) <= "0010100";
puntos2X(5) <= "0011000";
puntos2X(6) <= "0011100";
puntos2X(7) <= "0100000";
puntos2X(8) <= "0100100";
puntos2X(9) <= "0101000";
puntos2X(10) <= "0101100";
puntos2X(11) <= "0110000";
puntos2X(12) <= "0110100";
puntos2X(13) <= "0111000";
puntos2X(14) <= "0111100";
puntos2X(15) <= "1000000";
puntos2X(16) <= "1000100";
puntos2X(17) <= "1001000";
puntos2X(18) <= "1001100";
puntos2X(19) <= "1010000";
puntos2X(20) <= "1010100";
puntos2X(21) <= "1011000";
puntos2X(22) <= "1011100";
puntos2X(23) <= "1100000";
puntos2X(24) <= "1100100";
puntos2X(25) <= "1101000";
puntos2X(26) <= "1101100";
puntos2X(27) <= "1110000";
puntos2X(28) <= "1110100";
puntos2X(29) <= "1111000";
puntos2X(30) <= "1111100";
puntos2X(31) <= "1111111";
puntos3X(0) <= "0000000";
puntos3X(1) <= "0000100";
puntos3X(2) <= "0001000";
puntos3X(3) <= "0001100";
puntos3X(4) <= "0010000";
puntos3X(5) <= "0010100";
puntos3X(6) <= "0011000";
puntos3X(7) <= "0011100";
puntos3X(8) <= "0100000";
puntos3X(9) <= "0100100";
puntos3X(10) <= "0101000";
puntos3X(11) <= "0101100";
puntos3X(12) <= "0110000";
puntos3X(13) <= "0110100";
puntos3X(14) <= "0111000";
puntos3X(15) <= "0111100";
puntos3X(16) <= "1000100";
puntos3X(17) <= "1001000";
puntos3X(18) <= "1001100";
puntos3X(19) <= "1010000";
puntos3X(20) <= "1010100";
puntos3X(21) <= "1011000";
puntos3X(22) <= "1011100";
puntos3X(23) <= "1100000";
puntos3X(24) <= "1100100";
puntos3X(25) <= "1101000";
puntos3X(26) <= "1101100";
puntos3X(27) <= "1110000";
puntos3X(28) <= "1110100";
puntos3X(29) <= "1111000";
puntos3X(30) <= "1111100";
puntos3X(31) <= "1111111";
index: process(vAcc, estado2)
begin
-- En función del bit más significativo a 1 (permanece en todo a 1 tras realizar las or(ver el estado "10"), una posición a la izquierda
-- de ese bit será el índice. La conversión a coordenadas de pantalla consiste en, a partir de ese bit y hacia
-- la derecha, tomar 7 bits (un punto de la pantalla)
indice <= "00110";
bucle1: for i in 6 to 20 loop
if estado2 = "01" or estado2 = "10" or estado2 = "11" then
if vAcc(i) = '1' then
indice <= conv_std_logic_vector(i+1, 5);
end if;
end if;
end loop bucle1;
end process index;
sincrono: process(clk, reset, estado2_sig, estado_sig)
begin
if reset = '1' then
estado2 <= ( others => '0');
estado <= ( others => '0');
elsif clk'event and clk = '1' then
estado2 <= estado2_sig;
estado <= estado_sig;
end if;
end process sincrono;
maquina: process(estado2, fin_pantalla, punto, avanza, puntos, estado, vAcc, numPuntos, caso)
begin
inf <= '0';
puntosAux <= puntos;
vAccAux <= vAcc;
salida1Y <= (others=>'0');
salida2Y <= (others=>'0');
case estado2 is
-- Estado de inicio
when "00" =>
vAccAux <= (others => '0');
fin_conv <= '1';
enable_pantalla <= '0';
estado_sig <= estado;
if avanza = '1' then
estado2_sig <= "01";
else
estado2_sig <= "00";
end if;
-- Estado 01: de guardado de puntos. Se guardan en puntos, y vAcc (en este último, como valor absoluto,
-- con el fin de poder obtener el índice necesario realizar el reescalado a coordenadas de pantalla, basándonos
-- en realizar sucesivas OR lógicas con el fin de obtener el índice (factor para la escala vertical).
when "01" =>
fin_conv <= '0';
enable_pantalla <= '0';
if punto(20)='1' then
puntosAux(conv_integer(unsigned(estado))) <= "11111111111" & punto;
vAccAux <= vAcc or ("000000000000" - punto(DEC+ENT-1 downto 6));
else
vAccAux <= vAcc or punto(DEC+ENT-1 downto 6);
puntosAux(conv_integer(unsigned(estado))) <= "00000000000" & punto;
end if;
estado_sig <= estado;
if avanza ='1' then
if estado = numPuntos-1 then
estado2_sig <= "10";
estado_sig <= (others => '0');
else
estado_sig <= estado +1;
estado2_sig <= "01";
end if;
else
estado_sig <= estado;
estado2_sig <= estado2;
end if;
-- En el siguiente estado se manda un par de puntos a la pantalla. Los puntos han sigo guardados en los estados
-- anteriores, por tanto la señal indice tiene el valor correcto con el fin de tomar el subvector para realizar
-- el reescalado.
-- Debido a las características de la algoritmia de la pantalla, estado 10 y 11 son iguales, salvo que en el primero
-- únicamente estamos un ciclo con enable_pantalla a 1.
when "10" =>
if estado = "0000000" and caso(1)='0' then
inf <= '1';
elsif estado = numPuntos(6 downto 1) -1 and caso = "10" then
inf <= '1';
else
inf <= '0';
end if;
enable_pantalla <= '1';
fin_conv <= '0';
salida1Y <= puntos(conv_integer(unsigned(estado)))(conv_integer(unsigned(indice)) downto conv_integer(unsigned(indice))-6);
salida2Y <= puntos(conv_integer(unsigned(estado))+1)(conv_integer(unsigned(indice)) downto conv_integer(unsigned(indice))-6);
estado2_sig <= "11";
estado_sig <= estado;
when "11" =>
if estado = "0000000" and caso(1)='0' then
inf <= '1';
elsif estado = numPuntos(6 downto 1) -1 and caso = "10" then
inf <= '1';
else
inf <= '0';
end if;
fin_conv <= '0';
salida1Y <= puntos(conv_integer(unsigned(estado)))(conv_integer(unsigned(indice)) downto conv_integer(unsigned(indice))-6);
salida2Y <= puntos(conv_integer(unsigned(estado))+1)(conv_integer(unsigned(indice)) downto conv_integer(unsigned(indice))-6);
enable_pantalla <= '0';
if fin_pantalla = '1' then
if estado = numPuntos-2 then
estado_sig <= (others => '0');
estado2_sig <= "00";
else
estado_sig <= estado +1;
estado2_sig <= "10";
end if;
else
estado2_sig <= estado2;
estado_sig <= estado;
end if;
-- Una vez hemos obtenido el subvector de longitud 7 usando el indice, hacemos 64 - eso, con el fin
-- de ajustar a las coordenadas en la pantalla.
--Ejemplo: las coordenadas verticales de la pantalla son de esta manera
--
-- 0 (lim. sup)
--
--
-- 64 (eje horizontal)
--
--
-- 127 (lim.inf).
-- Así, si por ejemplo tenemos los f(x) = 2, f(y) = 3, al tomar con el índice teniendo en cuenta las
-- or anteriores quedarían 0100000 (=32) (para el 2) y 0110000 (=48) (para el 3). Realizando 64 - lo anterior, quedarían
-- las coordenadas 32 y 16, respectivamente. De forma similar, si f(x) fuera negativo, su coordenada sería mayor
-- que 64, quedando por debajo del eje horizontal.
when others =>
end case;
end process maquina;
process(clk)
begin
if clk'event and clk = '1' then
if estado2 = "11" then
indice3 <= indice;
else
indice3 <= indice3;
end if;
end if;
end process;
p_outX: process(puntos1X, puntos2X, estado, estado2, caso, puntos3X)
begin
if estado2 = "10" or estado2 = "11" then
if caso = "00" then
punto1X <= puntos1X(conv_integer(unsigned(estado)));
punto2X <= puntos1X(conv_integer(unsigned(estado))+1);
elsif caso = "01" then
punto1X <= puntos2X(conv_integer(unsigned(estado)));
punto2X <= puntos2X(conv_integer(unsigned(estado))+1);
else
punto1X <= puntos3X(conv_integer(unsigned(estado)));
punto2X <= puntos3X(conv_integer(unsigned(estado))+1);
end if;
else
punto1X <= (others => '1');
punto2X <= (others => '1');
end if;
end process p_outX;
registros: process (clk, reset, vAccAux, puntosAux, estado2_sig, estado_sig)
begin
if reset = '1' then
puntos <= (others => "00000000000000000000000000000000");
vAcc <= (others => '0');
estado2 <= (others => '0');
estado <= (others => '0');
elsif clk'event and clk = '1' then
puntos <= puntosAux;
vAcc <= vAccAux;
estado <= estado_sig;
estado2 <= estado2_sig;
end if;
end process registros;
punto1Y <= 64 - salida1Y;
punto2Y <= 64 - salida2Y;
-- Escala y: 1 unidad equivale a 2^(indice-13), por lo que indice_o representará este exponente
indice_o <= unsigned(indice3)-13 ;
end Behavioral;
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