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-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1194.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p05n01i01194ent IS
END c08s01b00x00p05n01i01194ent;
ARCHITECTURE c08s01b00x00p05n01i01194arch OF c08s01b00x00p05n01i01194ent IS
signal k : integer := 0;
BEGIN
TESTING: PROCESS
BEGIN
k <= 5 after 5 ns;
wait on k untli (k = 5);
assert FALSE
report "***FAILED TEST: c08s01b00x00p05n01i01194 - Reserved word 'until' is misspelled"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p05n01i01194arch;
|
package FIFO_PKG is
procedure AVERAGE_SAMPLES;
procedure AVERAGE_SAMPLES (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic);
-- Violations below this line
procedure AVERAGE_SAMPLES;
procedure AVERAGE_SAMPLES (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic);
end package FIFO_PKG;
package body FIFO_PKG is
procedure AVERAGE_SAMPLES (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
variable sig1 : std_logic;
file file1 : something;
constant var1 : integer;
alias alias1 is name;
begin
end procedure AVERAGE_SAMPLES;
procedure AVERAGE_SAMPLES (constant x : in integer;
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
variable sig1 : std_logic;
file file1 : something;
constant var1 : integer;
alias alias1 is name;
begin
end procedure AVERAGE_SAMPLES;
-- Variations on end of procedure parameter and is keyword
procedure AVERAGE_SAMPLES (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic)
is
variable sig1 : std_logic;
file file1 : something;
constant var1 : integer;
begin
end procedure AVERAGE_SAMPLES;
procedure AVERAGE_SAMPLES (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic
) is
variable sig1 : std_logic;
file file1 : something;
constant var1 : integer;
begin
end procedure AVERAGE_SAMPLES;
procedure AVERAGE_SAMPLES (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic
)
is
variable sig1 : std_logic;
file file1 : something;
constant var1 : integer;
begin
end procedure AVERAGE_SAMPLES;
end package body FIFO_PKG;
architecture RTL of ENT is
procedure AVERAGE_SAMPLES (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
variable sig1 : std_logic;
file file1 : something;
constant var1 : integer;
begin
end procedure AVERAGE_SAMPLES;
procedure AVERAGE_SAMPLES (constant x : in integer;
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
variable sig1 : std_logic;
file file1 : something;
constant var1 : integer;
begin
end procedure AVERAGE_SAMPLES;
function func_1 (a : integer) return integer is
constant c : integer;
variable v : integer;
file f : something;
begin
end function func1;
begin
TEST_PROCESS : process
procedure AVERAGE_SAMPLES (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
variable sig1 : std_logic;
file file1 : something;
constant var1 : integer;
begin
end procedure AVERAGE_SAMPLES;
begin
end process TEST_PROCESS;
TEST_PROCESS : process
procedure AVERAGE_SAMPLES (constant x : in integer;
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
variable sig1 : std_logic;
file file1 : something;
constant var1 : integer;
begin
end procedure AVERAGE_SAMPLES;
begin
end process TEST_PROCESS;
end architecture RTL;
|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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8DDz+334Ag==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 176256)
`protect data_block
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RE88OwwPvUIvS+ZGEuzEMqf6dmoShF9yTjWBkWXG6Er/ryql89BKNJIqvXK5HyIMx7z+uScmIPek
kwwma4lkQtY+4uCJowg0Q0j1pMp4mdWgpb4ou/xuqXO47ABvMReX4JX5Zhbn3lev2vHzY+9pPcNY
KVKRr/B7ptmbzXMiBOQuumthPcS0Jd99cIid5cRCJE9PBU4HUFDiyv/z2fFTlgbVhlUxAfm2xj7W
jW6ENwqah38dKyc7m+xxVke6/rvupATdsq/mPSHd2sLXw8dpS8uMJkBlZV91ZhYoWu3JmSSIQdYj
/ZkBrEY9PjGv39KMUJZrwBpWO+83Qn6F1HQbpIUAtEhOQL/FbPBY0wLSknOqoBl5P4tGZXMIMkwd
x0b86qFmvBVqJ5/5eFjU47C1rRbTI6D8LqWk6LRl+MVRSBoc5dGVjDBskufmP8hmYSVDDdHJNDHG
arXi30+TXVpaD41NQHi+OwwvQG9i/u5z18fu1k/XOsJW/bXmU01PKgQR7dk9+yo8J/WNcHcM5O6p
oknMXdlljhS+Ia37PkqFRMVgKnUCHswDBh1DydsifFa5gXvpC7itflcG6i5s+ZzMpjS78FzPEWVg
D4utfwUR8NvArhW0
`protect end_protected
|
entity tb_test2 is
end tb_test2;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_test2 is
signal clk : std_logic;
signal wr : std_logic;
signal rst : std_logic;
begin
dut: entity work.test2
port map (clk, wr, rst);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
wr <= '0';
rst <= '1';
pulse;
rst <= '0';
pulse;
rst <= '1';
wr <= '1';
pulse;
wait;
end process;
end behav;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 09/11/2014
--! Module Name: CRresetManager
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library work, ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.all;
--!
entity CRresetManager is
port (
clk40 : in std_logic;
rst_soft : in std_logic;
cr_rst : out std_logic;
cr_fifo_flush : out std_logic
);
end CRresetManager;
architecture Behavioral of CRresetManager is
--
constant fifoFLUSHcount_max : std_logic_vector (7 downto 0) := "10000000";
constant commonRSTcount_max : std_logic_vector (7 downto 0) := (others=>'1');
signal cr_rst_r,cr_rst_rr,fifoFLUSH : std_logic := '1';
signal rstTimerCount : std_logic_vector (7 downto 0) := (others=>'0');
--
begin
------------------------------------------------------------
-- clock domain crossing appreg_clk to clk40
------------------------------------------------------------
rst_cdc: process(clk40)
begin
if rising_edge(clk40) then
cr_rst_r <= rst_soft;
end if;
end process;
--
------------------------------------------------------------
--
------------------------------------------------------------
--
rstTimerCounter: process(clk40)
begin
if rising_edge(clk40) then
if cr_rst_r = '1' then
rstTimerCount <= (others=>'0');
else -- after cr_rst_r is deasserted:
if rstTimerCount = commonRSTcount_max then -- stop counting
rstTimerCount <= rstTimerCount; -- freese counter
else
rstTimerCount <= rstTimerCount + 1;
end if;
end if;
end if;
end process;
--
cr_rst_out: process(clk40)
begin
if rising_edge(clk40) then
if cr_rst_r = '1' then
cr_rst_rr <= '1';
else
if rstTimerCount = commonRSTcount_max then
cr_rst_rr <= '0';
else
cr_rst_rr <= cr_rst_rr;
end if;
end if;
end if;
end process;
--
crFifoFlush: process(clk40)
begin
if rising_edge(clk40) then
if cr_rst_r = '1' then
fifoFLUSH <= '1';
else
if rstTimerCount = fifoFLUSHcount_max then
fifoFLUSH <= '0';
else
fifoFLUSH <= fifoFLUSH;
end if;
end if;
end if;
end process;
--
cr_rst <= cr_rst_rr;
cr_fifo_flush <= fifoFLUSH;
--
end Behavioral;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 09/11/2014
--! Module Name: CRresetManager
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library work, ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.all;
--!
entity CRresetManager is
port (
clk40 : in std_logic;
rst_soft : in std_logic;
cr_rst : out std_logic;
cr_fifo_flush : out std_logic
);
end CRresetManager;
architecture Behavioral of CRresetManager is
--
constant fifoFLUSHcount_max : std_logic_vector (7 downto 0) := "10000000";
constant commonRSTcount_max : std_logic_vector (7 downto 0) := (others=>'1');
signal cr_rst_r,cr_rst_rr,fifoFLUSH : std_logic := '1';
signal rstTimerCount : std_logic_vector (7 downto 0) := (others=>'0');
--
begin
------------------------------------------------------------
-- clock domain crossing appreg_clk to clk40
------------------------------------------------------------
rst_cdc: process(clk40)
begin
if rising_edge(clk40) then
cr_rst_r <= rst_soft;
end if;
end process;
--
------------------------------------------------------------
--
------------------------------------------------------------
--
rstTimerCounter: process(clk40)
begin
if rising_edge(clk40) then
if cr_rst_r = '1' then
rstTimerCount <= (others=>'0');
else -- after cr_rst_r is deasserted:
if rstTimerCount = commonRSTcount_max then -- stop counting
rstTimerCount <= rstTimerCount; -- freese counter
else
rstTimerCount <= rstTimerCount + 1;
end if;
end if;
end if;
end process;
--
cr_rst_out: process(clk40)
begin
if rising_edge(clk40) then
if cr_rst_r = '1' then
cr_rst_rr <= '1';
else
if rstTimerCount = commonRSTcount_max then
cr_rst_rr <= '0';
else
cr_rst_rr <= cr_rst_rr;
end if;
end if;
end if;
end process;
--
crFifoFlush: process(clk40)
begin
if rising_edge(clk40) then
if cr_rst_r = '1' then
fifoFLUSH <= '1';
else
if rstTimerCount = fifoFLUSHcount_max then
fifoFLUSH <= '0';
else
fifoFLUSH <= fifoFLUSH;
end if;
end if;
end if;
end process;
--
cr_rst <= cr_rst_rr;
cr_fifo_flush <= fifoFLUSH;
--
end Behavioral;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 09/11/2014
--! Module Name: CRresetManager
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library work, ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.all;
--!
entity CRresetManager is
port (
clk40 : in std_logic;
rst_soft : in std_logic;
cr_rst : out std_logic;
cr_fifo_flush : out std_logic
);
end CRresetManager;
architecture Behavioral of CRresetManager is
--
constant fifoFLUSHcount_max : std_logic_vector (7 downto 0) := "10000000";
constant commonRSTcount_max : std_logic_vector (7 downto 0) := (others=>'1');
signal cr_rst_r,cr_rst_rr,fifoFLUSH : std_logic := '1';
signal rstTimerCount : std_logic_vector (7 downto 0) := (others=>'0');
--
begin
------------------------------------------------------------
-- clock domain crossing appreg_clk to clk40
------------------------------------------------------------
rst_cdc: process(clk40)
begin
if rising_edge(clk40) then
cr_rst_r <= rst_soft;
end if;
end process;
--
------------------------------------------------------------
--
------------------------------------------------------------
--
rstTimerCounter: process(clk40)
begin
if rising_edge(clk40) then
if cr_rst_r = '1' then
rstTimerCount <= (others=>'0');
else -- after cr_rst_r is deasserted:
if rstTimerCount = commonRSTcount_max then -- stop counting
rstTimerCount <= rstTimerCount; -- freese counter
else
rstTimerCount <= rstTimerCount + 1;
end if;
end if;
end if;
end process;
--
cr_rst_out: process(clk40)
begin
if rising_edge(clk40) then
if cr_rst_r = '1' then
cr_rst_rr <= '1';
else
if rstTimerCount = commonRSTcount_max then
cr_rst_rr <= '0';
else
cr_rst_rr <= cr_rst_rr;
end if;
end if;
end if;
end process;
--
crFifoFlush: process(clk40)
begin
if rising_edge(clk40) then
if cr_rst_r = '1' then
fifoFLUSH <= '1';
else
if rstTimerCount = fifoFLUSHcount_max then
fifoFLUSH <= '0';
else
fifoFLUSH <= fifoFLUSH;
end if;
end if;
end if;
end process;
--
cr_rst <= cr_rst_rr;
cr_fifo_flush <= fifoFLUSH;
--
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/28/2015 07:22:57 PM
-- Design Name:
-- Module Name: Sync - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Sync is
Generic (
kRstActiveHigh : boolean := true; --'1' if aRst (active-high) is in use, '0' if aRst_n (active_low)
kResetTo : std_logic := '0'; --the reset value of oOut when aRst/aRst_n is asserted
kRegisterInput : boolean := true; --should iIn be re-registered on the InClk domain
kStages : natural := 2); --how many synchronizer stages to use
Port (
aRst : in STD_LOGIC;
aRst_n : in STD_LOGIC;
iIn : in STD_LOGIC;
InClk :in STD_LOGIC;
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
end Sync;
architecture Behavioral of Sync is
signal aRst_int, iIn_q : std_logic;
begin
ResetActiveLow: if not kRstActiveHigh generate
aRst_int <= not aRst_n;
end generate ResetActiveLow;
ResetActiveHigh: if kRstActiveHigh generate
aRst_int <= aRst;
end generate ResetActiveHigh;
ReRegister: if kRegisterInput generate
--By re-registering iIn on its own domain, we make sure iIn_q is glitch-free
SyncSource: process(aRst_int, InClk)
begin
if (aRst_int = '1') then
iIn_q <= kResetTo;
elsif Rising_Edge(InClk) then
iIn_q <= iIn;
end if;
end process SyncSource;
end generate ReRegister;
DontRegister: if not kRegisterInput generate
iIn_q <= iIn;
end generate DontRegister;
--Crossing clock boundary here
SyncAsyncx: entity work.SyncAsync
generic map (
kResetTo => kResetTo,
kStages => kStages)
port map (
aReset => aRst_int,
aIn => iIn_q,
OutClk => OutClk,
oOut => oOut);
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/28/2015 07:22:57 PM
-- Design Name:
-- Module Name: Sync - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Sync is
Generic (
kRstActiveHigh : boolean := true; --'1' if aRst (active-high) is in use, '0' if aRst_n (active_low)
kResetTo : std_logic := '0'; --the reset value of oOut when aRst/aRst_n is asserted
kRegisterInput : boolean := true; --should iIn be re-registered on the InClk domain
kStages : natural := 2); --how many synchronizer stages to use
Port (
aRst : in STD_LOGIC;
aRst_n : in STD_LOGIC;
iIn : in STD_LOGIC;
InClk :in STD_LOGIC;
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
end Sync;
architecture Behavioral of Sync is
signal aRst_int, iIn_q : std_logic;
begin
ResetActiveLow: if not kRstActiveHigh generate
aRst_int <= not aRst_n;
end generate ResetActiveLow;
ResetActiveHigh: if kRstActiveHigh generate
aRst_int <= aRst;
end generate ResetActiveHigh;
ReRegister: if kRegisterInput generate
--By re-registering iIn on its own domain, we make sure iIn_q is glitch-free
SyncSource: process(aRst_int, InClk)
begin
if (aRst_int = '1') then
iIn_q <= kResetTo;
elsif Rising_Edge(InClk) then
iIn_q <= iIn;
end if;
end process SyncSource;
end generate ReRegister;
DontRegister: if not kRegisterInput generate
iIn_q <= iIn;
end generate DontRegister;
--Crossing clock boundary here
SyncAsyncx: entity work.SyncAsync
generic map (
kResetTo => kResetTo,
kStages => kStages)
port map (
aReset => aRst_int,
aIn => iIn_q,
OutClk => OutClk,
oOut => oOut);
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/28/2015 07:22:57 PM
-- Design Name:
-- Module Name: Sync - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Sync is
Generic (
kRstActiveHigh : boolean := true; --'1' if aRst (active-high) is in use, '0' if aRst_n (active_low)
kResetTo : std_logic := '0'; --the reset value of oOut when aRst/aRst_n is asserted
kRegisterInput : boolean := true; --should iIn be re-registered on the InClk domain
kStages : natural := 2); --how many synchronizer stages to use
Port (
aRst : in STD_LOGIC;
aRst_n : in STD_LOGIC;
iIn : in STD_LOGIC;
InClk :in STD_LOGIC;
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
end Sync;
architecture Behavioral of Sync is
signal aRst_int, iIn_q : std_logic;
begin
ResetActiveLow: if not kRstActiveHigh generate
aRst_int <= not aRst_n;
end generate ResetActiveLow;
ResetActiveHigh: if kRstActiveHigh generate
aRst_int <= aRst;
end generate ResetActiveHigh;
ReRegister: if kRegisterInput generate
--By re-registering iIn on its own domain, we make sure iIn_q is glitch-free
SyncSource: process(aRst_int, InClk)
begin
if (aRst_int = '1') then
iIn_q <= kResetTo;
elsif Rising_Edge(InClk) then
iIn_q <= iIn;
end if;
end process SyncSource;
end generate ReRegister;
DontRegister: if not kRegisterInput generate
iIn_q <= iIn;
end generate DontRegister;
--Crossing clock boundary here
SyncAsyncx: entity work.SyncAsync
generic map (
kResetTo => kResetTo,
kStages => kStages)
port map (
aReset => aRst_int,
aIn => iIn_q,
OutClk => OutClk,
oOut => oOut);
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/28/2015 07:22:57 PM
-- Design Name:
-- Module Name: Sync - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Sync is
Generic (
kRstActiveHigh : boolean := true; --'1' if aRst (active-high) is in use, '0' if aRst_n (active_low)
kResetTo : std_logic := '0'; --the reset value of oOut when aRst/aRst_n is asserted
kRegisterInput : boolean := true; --should iIn be re-registered on the InClk domain
kStages : natural := 2); --how many synchronizer stages to use
Port (
aRst : in STD_LOGIC;
aRst_n : in STD_LOGIC;
iIn : in STD_LOGIC;
InClk :in STD_LOGIC;
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
end Sync;
architecture Behavioral of Sync is
signal aRst_int, iIn_q : std_logic;
begin
ResetActiveLow: if not kRstActiveHigh generate
aRst_int <= not aRst_n;
end generate ResetActiveLow;
ResetActiveHigh: if kRstActiveHigh generate
aRst_int <= aRst;
end generate ResetActiveHigh;
ReRegister: if kRegisterInput generate
--By re-registering iIn on its own domain, we make sure iIn_q is glitch-free
SyncSource: process(aRst_int, InClk)
begin
if (aRst_int = '1') then
iIn_q <= kResetTo;
elsif Rising_Edge(InClk) then
iIn_q <= iIn;
end if;
end process SyncSource;
end generate ReRegister;
DontRegister: if not kRegisterInput generate
iIn_q <= iIn;
end generate DontRegister;
--Crossing clock boundary here
SyncAsyncx: entity work.SyncAsync
generic map (
kResetTo => kResetTo,
kStages => kStages)
port map (
aReset => aRst_int,
aIn => iIn_q,
OutClk => OutClk,
oOut => oOut);
end Behavioral;
|
-------------------------------------------------------------------------------
-- COPYRIGHT (c) SOLECTRIX GmbH, Germany, %TPL_YEAR% All rights reserved
--
-- The copyright to the document(s) herein is the property of SOLECTRIX GmbH
-- The document(s) may be used and/or copied only with the written permission
-- from SOLECTRIX GmbH or in accordance with the terms/conditions stipulated
-- in the agreement/contract under which the document(s) have been supplied
-------------------------------------------------------------------------------
-- Project : %TPL_PROJECT%
-- File : %TPL_VHDLFILE%
-- Created : %TPL_DATE%
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
--*
--* @short Wishbone register module
--* Auto-generated by '%TPL_SCRIPT%' based on '%TPL_TPLFILE%'
--*
--* Needed Libraries and Packages:
--* @li ieee.std_logic_1164 standard multi-value logic package
--* @li ieee.numeric_std
--*
--* @author %TPL_USER%
--* @date 30.06.2016
--* @internal
--/
-------------------------------------------------------------------------------
-- Modification history :
-- Date Author & Description
-- %TPL_DATE% %TPL_USER%: Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
%TPL_LIBRARY%
-------------------------------------------------------------------------------
ENTITY %TPL_MODULE% IS
GENERIC (
g_addr_bits : INTEGER := %TPL_WBSIZE%);
PORT (
-- Wishbone interface
clk : IN STD_LOGIC;
i_wb_cyc : IN STD_LOGIC;
i_wb_stb : IN STD_LOGIC;
i_wb_we : IN STD_LOGIC;
i_wb_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
i_wb_addr : IN STD_LOGIC_VECTOR(g_addr_bits-1 DOWNTO 0);
i_wb_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
o_wb_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
o_wb_ack : OUT STD_LOGIC;
o_wb_rty : OUT STD_LOGIC;
o_wb_err : OUT STD_LOGIC;
-- Custom ports
%TPL_PORTS%
);
END ENTITY %TPL_MODULE%;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF %TPL_MODULE% IS
-----------------------------------------------------------------------------
-- Procedures
-----------------------------------------------------------------------------
%TPL_PROCEDURES%
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
%TPL_CONSTANTS%
-----------------------------------------------------------------------------
-- WB interface signals
-----------------------------------------------------------------------------
SIGNAL s_wb_ack : STD_LOGIC;
SIGNAL s_wb_err : STD_LOGIC;
SIGNAL s_wb_addr : UNSIGNED(i_wb_addr'HIGH DOWNTO 0);
SIGNAL s_int_addr : UNSIGNED(i_wb_addr'HIGH DOWNTO 0);
SIGNAL s_int_data : STD_LOGIC_VECTOR(i_wb_data'RANGE);
SIGNAL s_int_we : STD_LOGIC_VECTOR(i_wb_sel'RANGE);
SIGNAL s_int_trd : STD_LOGIC;
SIGNAL s_int_twr : STD_LOGIC;
SIGNAL s_int_addr_valid : STD_LOGIC;
SIGNAL s_int_data_rb : STD_LOGIC_VECTOR(i_wb_data'RANGE);
SIGNAL s_wb_data : STD_LOGIC_VECTOR(o_wb_data'RANGE);
TYPE t_wb_state IS (e_idle, e_delay, e_ack);
SIGNAL s_wb_state : t_wb_state := e_idle;
-----------------------------------------------------------------------------
-- Custom registers
-----------------------------------------------------------------------------
%TPL_REGISTER_SIGNALS%
BEGIN -- ARCHITECTURE rtl
-----------------------------------------------------------------------------
--* purpose : Wishbone Bus Control
--* type : sequential, rising edge, no reset
wb_ctrl : PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
s_wb_ack <= '0';
s_wb_err <= '0';
s_int_data <= i_wb_data;
s_int_addr <= s_wb_addr;
s_int_we <= (OTHERS => '0');
s_int_trd <= '0';
s_int_twr <= '0';
CASE s_wb_state IS
WHEN e_idle =>
-- check if anyone requests access
IF (i_wb_cyc = '1' AND i_wb_stb = '1') THEN
-- ack is delayed because we need 3 cycles
IF (i_wb_we = '1') THEN
s_wb_ack <= s_int_addr_valid;
s_wb_err <= NOT s_int_addr_valid;
s_wb_state <= e_ack;
s_int_we <= i_wb_sel;
s_int_twr <= '1';
ELSE
IF c_has_read_notifies THEN
s_wb_state <= e_delay;
s_int_trd <= '1';
ELSE
s_wb_ack <= s_int_addr_valid;
s_wb_err <= NOT s_int_addr_valid;
s_wb_state <= e_ack;
END IF;
END IF;
END IF;
WHEN e_delay =>
s_wb_ack <= s_int_addr_valid;
s_wb_err <= NOT s_int_addr_valid;
s_wb_state <= e_ack;
WHEN e_ack =>
s_wb_state <= e_idle;
END CASE;
s_wb_data <= s_int_data_rb;
END IF;
END PROCESS wb_ctrl;
s_wb_addr <= UNSIGNED(i_wb_addr);
o_wb_data <= s_wb_data;
o_wb_ack <= s_wb_ack;
o_wb_err <= s_wb_err;
o_wb_rty <= '0';
-----------------------------------------------------------------------------
-- WB address validation
WITH to_integer(s_wb_addr) SELECT
s_int_addr_valid <=
%TPL_ADDR_VALIDATION%
'0' WHEN OTHERS;
-----------------------------------------------------------------------------
--* purpose : register access
--* type : sequential, rising edge, high active synchronous reset
reg_access : PROCESS (clk)
BEGIN -- PROCESS reg_access
IF rising_edge(clk) THEN
-- default values / clear trigger signals
%TPL_REG_DEFAULT%
-- WRITE registers
CASE to_integer(s_int_addr) IS
%TPL_SIG_WR%
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS reg_access;
-----------------------------------------------------------------------------
p_comb_read_mux : PROCESS(s_wb_addr, %TPL_SENS_LIST%)
%TPL_VAR_DEC%
-- helper to ease template generation
PROCEDURE set(
l_input : STD_LOGIC_VECTOR(31 DOWNTO 0);
l_mask : STD_LOGIC_VECTOR(31 DOWNTO 0)) IS
BEGIN
s_int_data_rb <= l_input AND l_mask;
END PROCEDURE;
BEGIN
-- READ registers assignments
%TPL_VAR_RD%
-- WB output data multiplexer
CASE to_integer(s_wb_addr) IS
%TPL_CASE_OUT%
WHEN OTHERS => set((OTHERS => '0'), (OTHERS => '1'));
END CASE;
END PROCESS p_comb_read_mux;
-----------------------------------------------------------------------------
-- output mappings
%TPL_PORT_SIG_OUT%
END ARCHITECTURE rtl;
|
-------------------------------------------------------------------------------
-- COPYRIGHT (c) SOLECTRIX GmbH, Germany, %TPL_YEAR% All rights reserved
--
-- The copyright to the document(s) herein is the property of SOLECTRIX GmbH
-- The document(s) may be used and/or copied only with the written permission
-- from SOLECTRIX GmbH or in accordance with the terms/conditions stipulated
-- in the agreement/contract under which the document(s) have been supplied
-------------------------------------------------------------------------------
-- Project : %TPL_PROJECT%
-- File : %TPL_VHDLFILE%
-- Created : %TPL_DATE%
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
--*
--* @short Wishbone register module
--* Auto-generated by '%TPL_SCRIPT%' based on '%TPL_TPLFILE%'
--*
--* Needed Libraries and Packages:
--* @li ieee.std_logic_1164 standard multi-value logic package
--* @li ieee.numeric_std
--*
--* @author %TPL_USER%
--* @date 30.06.2016
--* @internal
--/
-------------------------------------------------------------------------------
-- Modification history :
-- Date Author & Description
-- %TPL_DATE% %TPL_USER%: Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
%TPL_LIBRARY%
-------------------------------------------------------------------------------
ENTITY %TPL_MODULE% IS
GENERIC (
g_addr_bits : INTEGER := %TPL_WBSIZE%);
PORT (
-- Wishbone interface
clk : IN STD_LOGIC;
i_wb_cyc : IN STD_LOGIC;
i_wb_stb : IN STD_LOGIC;
i_wb_we : IN STD_LOGIC;
i_wb_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
i_wb_addr : IN STD_LOGIC_VECTOR(g_addr_bits-1 DOWNTO 0);
i_wb_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
o_wb_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
o_wb_ack : OUT STD_LOGIC;
o_wb_rty : OUT STD_LOGIC;
o_wb_err : OUT STD_LOGIC;
-- Custom ports
%TPL_PORTS%
);
END ENTITY %TPL_MODULE%;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF %TPL_MODULE% IS
-----------------------------------------------------------------------------
-- Procedures
-----------------------------------------------------------------------------
%TPL_PROCEDURES%
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
%TPL_CONSTANTS%
-----------------------------------------------------------------------------
-- WB interface signals
-----------------------------------------------------------------------------
SIGNAL s_wb_ack : STD_LOGIC;
SIGNAL s_wb_err : STD_LOGIC;
SIGNAL s_wb_addr : UNSIGNED(i_wb_addr'HIGH DOWNTO 0);
SIGNAL s_int_addr : UNSIGNED(i_wb_addr'HIGH DOWNTO 0);
SIGNAL s_int_data : STD_LOGIC_VECTOR(i_wb_data'RANGE);
SIGNAL s_int_we : STD_LOGIC_VECTOR(i_wb_sel'RANGE);
SIGNAL s_int_trd : STD_LOGIC;
SIGNAL s_int_twr : STD_LOGIC;
SIGNAL s_int_addr_valid : STD_LOGIC;
SIGNAL s_int_data_rb : STD_LOGIC_VECTOR(i_wb_data'RANGE);
SIGNAL s_wb_data : STD_LOGIC_VECTOR(o_wb_data'RANGE);
TYPE t_wb_state IS (e_idle, e_delay, e_ack);
SIGNAL s_wb_state : t_wb_state := e_idle;
-----------------------------------------------------------------------------
-- Custom registers
-----------------------------------------------------------------------------
%TPL_REGISTER_SIGNALS%
BEGIN -- ARCHITECTURE rtl
-----------------------------------------------------------------------------
--* purpose : Wishbone Bus Control
--* type : sequential, rising edge, no reset
wb_ctrl : PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
s_wb_ack <= '0';
s_wb_err <= '0';
s_int_data <= i_wb_data;
s_int_addr <= s_wb_addr;
s_int_we <= (OTHERS => '0');
s_int_trd <= '0';
s_int_twr <= '0';
CASE s_wb_state IS
WHEN e_idle =>
-- check if anyone requests access
IF (i_wb_cyc = '1' AND i_wb_stb = '1') THEN
-- ack is delayed because we need 3 cycles
IF (i_wb_we = '1') THEN
s_wb_ack <= s_int_addr_valid;
s_wb_err <= NOT s_int_addr_valid;
s_wb_state <= e_ack;
s_int_we <= i_wb_sel;
s_int_twr <= '1';
ELSE
IF c_has_read_notifies THEN
s_wb_state <= e_delay;
s_int_trd <= '1';
ELSE
s_wb_ack <= s_int_addr_valid;
s_wb_err <= NOT s_int_addr_valid;
s_wb_state <= e_ack;
END IF;
END IF;
END IF;
WHEN e_delay =>
s_wb_ack <= s_int_addr_valid;
s_wb_err <= NOT s_int_addr_valid;
s_wb_state <= e_ack;
WHEN e_ack =>
s_wb_state <= e_idle;
END CASE;
s_wb_data <= s_int_data_rb;
END IF;
END PROCESS wb_ctrl;
s_wb_addr <= UNSIGNED(i_wb_addr);
o_wb_data <= s_wb_data;
o_wb_ack <= s_wb_ack;
o_wb_err <= s_wb_err;
o_wb_rty <= '0';
-----------------------------------------------------------------------------
-- WB address validation
WITH to_integer(s_wb_addr) SELECT
s_int_addr_valid <=
%TPL_ADDR_VALIDATION%
'0' WHEN OTHERS;
-----------------------------------------------------------------------------
--* purpose : register access
--* type : sequential, rising edge, high active synchronous reset
reg_access : PROCESS (clk)
BEGIN -- PROCESS reg_access
IF rising_edge(clk) THEN
-- default values / clear trigger signals
%TPL_REG_DEFAULT%
-- WRITE registers
CASE to_integer(s_int_addr) IS
%TPL_SIG_WR%
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS reg_access;
-----------------------------------------------------------------------------
p_comb_read_mux : PROCESS(s_wb_addr, %TPL_SENS_LIST%)
%TPL_VAR_DEC%
-- helper to ease template generation
PROCEDURE set(
l_input : STD_LOGIC_VECTOR(31 DOWNTO 0);
l_mask : STD_LOGIC_VECTOR(31 DOWNTO 0)) IS
BEGIN
s_int_data_rb <= l_input AND l_mask;
END PROCEDURE;
BEGIN
-- READ registers assignments
%TPL_VAR_RD%
-- WB output data multiplexer
CASE to_integer(s_wb_addr) IS
%TPL_CASE_OUT%
WHEN OTHERS => set((OTHERS => '0'), (OTHERS => '1'));
END CASE;
END PROCESS p_comb_read_mux;
-----------------------------------------------------------------------------
-- output mappings
%TPL_PORT_SIG_OUT%
END ARCHITECTURE rtl;
|
-- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- enc.vhd: Generic encoder
-- Copyright (C) 2006 CESNET
-- Author(s): Martin Kosek <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use work.math_pack.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity GEN_ENC is
generic(
ITEMS : integer := 16
);
port(
DI : in std_logic_vector(ITEMS-1 downto 0);
ADDR : out std_logic_vector(log2(ITEMS)-1 downto 0)
);
end entity GEN_ENC;
-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
architecture behavioral of GEN_ENC is
begin
process(DI)
begin
ADDR <= (others => '0');
for i in 0 to (ITEMS-1) loop
if (DI(i) = '1') then
ADDR <= conv_std_logic_vector(i, log2(ITEMS));
end if;
end loop;
end process;
end architecture behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.eth_config.all;
entity eth is
generic(
MII_WIDTH : natural := 8;
RAM_RD_CYCLE : natural := 2;
RAM_WR_CYCLE : natural := 2;
RAM_RD_DELAY : natural := 1 ; --1
RAM_AWIDTH : natural := 32;
RAM_DWIDTH : natural := 32
);
port(
txclk : in std_logic;
txd : out std_logic_vector(MII_WIDTH-1 downto 0);
txen : out std_logic;
rxclk : in std_logic;
rxd : in std_logic_vector(MII_WIDTH-1 downto 0);
rxdv : in std_logic;
clk : in std_logic;
reset : in std_logic;
zcpsm_clk : in std_logic;
TxFIFO_W_Clk : in std_logic;
TxFIFO_Clr : in std_logic;
TxFIFO_W_Block : in std_logic;
TxFIFO_WE : in std_logic;
TxFIFO_WAddr : in std_logic_vector( TX_TASKFIFO_BLOCK_AWIDTH - 1 downto 0 );
TxFIFO_WData : in std_logic_vector( TASKFIFO_DWIDTH - 1 downto 0 );
TxFIFO_Full : out std_logic;
RxFIFO_R_Clk : in std_logic;
RxFIFO_R_Block : in std_logic;
RxFIFO_RAddr : in std_logic_vector( RX_TASKFIFO_BLOCK_AWIDTH - 1 downto 0 );
RxFIFO_RData : out std_logic_vector( TASKFIFO_DWIDTH - 1 downto 0 );
RxFIFO_Empty : out std_logic;
localtime : in std_logic_vector(31 downto 0);
recvtime : out std_logic_vector(31 downto 0);
recvtime_valid : out std_logic;
localtime_locked: out std_logic;
----------------------------------------------
debugIO_port_id : out std_logic_vector(15 downto 0);
debugIO_write_strobe: out std_logic;
debugIO_out_port : out std_logic_vector(15 downto 0);
debugIO_read_strobe : out std_logic;
debugIO_in_port : in std_logic_vector(15 downto 0);
progIO_id : out std_logic_vector(3 downto 0);
progIO_reset : out std_logic;
progIO_wren : out std_logic;
progIO_addr : out std_logic_vector(9 downto 0);
progIO_wdata : out std_logic_vector(15 downto 0);
progIO_rdata : in std_logic_vector(15 downto 0);
------------------------------------------------------------------------
ram_wren : out std_logic;
ram_waddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
ram_wdata : out std_logic_vector(RAM_DWIDTH-1 downto 0);
ram_raddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
ram_rdata : in std_logic_vector(RAM_DWIDTH-1 downto 0);
--
test : out std_logic_vector(1 downto 0);
s_HighPri_Tx_Req : in std_logic;
m48_HighPri_Tx_Req_DesMac : in std_logic_vector( 47 downto 0 );
m16_HighPri_Tx_Req_Addr : in std_logic_vector( 15 downto 0 );
m16_HighPri_Tx_Req_Data : in std_logic_vector( 15 downto 0 );
local_id_MAC0_Req : in std_logic_vector(7 downto 0);
local_id_MAC0_A : in std_logic_vector(7 downto 0);
local_id_MAC0_B : in std_logic_vector(7 downto 0);
local_id : in std_logic_vector(39 downto 0)
);
end entity;
architecture arch_eth of eth is
component ethrx
generic(
HEAD_AWIDTH : NATURAL := 5;
BUFF_AWIDTH : NATURAL := 12;
FIFO_AWIDTH : NATURAL := 2;
WR_CYCLE : NATURAL := 1;
RAM_AWIDTH : NATURAL :=32
);
port(
clk : in std_logic;
zcpsm_clk : in std_logic;
reset : in std_logic;
rxclk : in std_logic;
rxd : in std_logic_vector(3 downto 0);
rxdv : in std_logic;
db_ce : in std_logic;
db_port_id : in std_logic_vector(3 downto 0);
db_write_strobe : in std_logic;
db_out_port : in std_logic_vector(7 downto 0);
db_read_strobe : in std_logic;
db_in_port : out std_logic_vector(7 downto 0);
eth_ce : in std_logic;
eth_port_id : in std_logic_vector(3 downto 0);
eth_write_strobe : in std_logic;
eth_out_port : in std_logic_vector(7 downto 0);
eth_read_strobe : in std_logic;
eth_in_port : out std_logic_vector(7 downto 0);
eth_dma_ce : in std_logic;
ethrx_busy : out std_logic;
recvtime : out std_logic_vector(31 downto 0);
recvtime_valid : out std_logic;
localtime_locked : out std_logic;
lastframe_flag : out std_logic;
ram_wren : out std_logic;
ram_waddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
---------------
-- test : out std_logic_vector(3 downto 0);
ram_wdata : out std_logic_vector(15 downto 0));
end component;
component g_ethrx
generic(
HEAD_AWIDTH : NATURAL := 5;
BUFF_AWIDTH : NATURAL := 12;
FIFO_AWIDTH : NATURAL := 2;
WR_CYCLE : NATURAL := 1;
RAM_AWIDTH : NATURAL :=32
);
port(
clk : in std_logic;
zcpsm_clk : in std_logic;
reset : in std_logic;
rxclk : in std_logic;
rxd : in std_logic_vector(7 downto 0);
rxdv : in std_logic;
db_ce : in std_logic;
db_port_id : in std_logic_vector(3 downto 0);
db_write_strobe : in std_logic;
db_out_port : in std_logic_vector(7 downto 0);
db_read_strobe : in std_logic;
db_in_port : out std_logic_vector(7 downto 0);
eth_ce : in std_logic;
eth_port_id : in std_logic_vector(3 downto 0);
eth_write_strobe : in std_logic;
eth_out_port : in std_logic_vector(7 downto 0);
eth_read_strobe : in std_logic;
eth_in_port : out std_logic_vector(7 downto 0);
eth_dma_ce : in std_logic;
ethrx_busy : out std_logic;
recvtime : out std_logic_vector(31 downto 0);
recvtime_valid : out std_logic;
localtime_locked : out std_logic;
lastframe_flag : out std_logic;
ram_wren : out std_logic;
ram_waddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
---------------
-- test : out std_logic_vector(3 downto 0);
ram_wdata : out std_logic_vector(31 downto 0));
end component;
component ethrx_zcpsm
port(
reset : in std_logic;
clk : in std_logic;
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0)
);
end component;
component ethrx_task
generic(
TASKFIFO_DWIDTH : natural := 8;
TASKFIFO_BLOCK_DEPTH : natural := 8;
TASKFIFO_BLOCK_AWIDTH : natural := 3;
TASKFIFO_DEPTH : natural := 16;
TASKFIFO_AWIDTH : natural := 4;
TASKFIFO_RAM_TYPE : string := "DIS_RAM"
);
port(
reset : in std_logic;
-- Task Input
RxFIFO_R_Clk : in std_logic;
RxFIFO_R_Block : in std_logic;
RxFIFO_RAddr : in std_logic_vector( TASKFIFO_BLOCK_AWIDTH - 1 downto 0 );
RxFIFO_RData : out std_logic_vector( TASKFIFO_DWIDTH - 1 downto 0 );
RxFIFO_Full : out std_logic;
RxFIFO_Empty : out std_logic;
fifo_wr_block : in std_logic;
-- zcpsm
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0)
);
end component;
component dma2rxtask
port(
reset : in std_logic;
zcpsm_clk : in std_logic;
busy : in std_logic;
lastframe : in std_logic;
rxtask_wr_block : out std_logic
);
end component;
component asyncwrite
port(
reset : in std_logic;
async_clk : in std_logic;
sync_clk : in std_logic;
async_wren : in std_logic;
trigger : in std_logic;
sync_wren : out std_logic;
over : out std_logic;
flag : out std_logic);
end component;
component ethtx
generic(
HEAD_AWIDTH : NATURAL := 5;
BUFF_AWIDTH : NATURAL := 5;
FIFO_AWIDTH : NATURAL := 2;
RD_CYCLE : NATURAL := 1;
RD_DELAY : NATURAL := 1;
RAM_AWIDTH : NATURAL := 32
);
port(
clk : in std_logic;
zcpsm_clk : in std_logic;
reset : in std_logic;
txclk : in std_logic;
txd : out std_logic_vector(3 downto 0);
txen : out std_logic;
eth_ce : in std_logic;
eth_port_id : in std_logic_vector(3 downto 0);
eth_write_strobe : in std_logic;
eth_out_port : in std_logic_vector(7 downto 0);
eth_read_strobe : in std_logic;
eth_in_port : out std_logic_vector(7 downto 0);
db_ce : in std_logic;
db_port_id : in std_logic_vector(3 downto 0);
db_write_strobe : in std_logic;
db_out_port : in std_logic_vector(7 downto 0);
db_read_strobe : in std_logic;
db_in_port : out std_logic_vector(7 downto 0);
ram_raddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
ram_rdata : in std_logic_vector(15 downto 0);
-- localtime --
localtime : in std_logic_vector(31 downto 0)
);
end component;
component g_ethtx
generic(
HEAD_AWIDTH : NATURAL := 5;
BUFF_AWIDTH : NATURAL := 5;
FIFO_AWIDTH : NATURAL := 2;
RD_CYCLE : NATURAL := 1;
RD_DELAY : NATURAL := 1;
RAM_AWIDTH : NATURAL := 32
);
port(
clk : in std_logic;
zcpsm_clk : in std_logic;
reset : in std_logic;
txclk : in std_logic;
txd : out std_logic_vector(7 downto 0);
txen : out std_logic;
eth_ce : in std_logic;
eth_port_id : in std_logic_vector(3 downto 0);
eth_write_strobe : in std_logic;
eth_out_port : in std_logic_vector(7 downto 0);
eth_read_strobe : in std_logic;
eth_in_port : out std_logic_vector(7 downto 0);
db_ce : in std_logic;
db_port_id : in std_logic_vector(3 downto 0);
db_write_strobe : in std_logic;
db_out_port : in std_logic_vector(7 downto 0);
db_read_strobe : in std_logic;
db_in_port : out std_logic_vector(7 downto 0);
ram_raddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
ram_rdata : in std_logic_vector(31 downto 0);
-- localtime --
localtime : in std_logic_vector(31 downto 0)
);
end component;
component ethtx_zcpsm
port(
reset : in std_logic;
clk : in std_logic;
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0)
);
end component;
component ethtx_task
generic(
TASKFIFO_DWIDTH : natural := 8;
TASKFIFO_BLOCK_DEPTH : natural := 16;
TASKFIFO_BLOCK_AWIDTH : natural := 4;
TASKFIFO_DEPTH : natural := 16;
TASKFIFO_AWIDTH : natural := 4;
TASKFIFO_RAM_TYPE : string := "DIS_RAM"
);
port(
reset : in std_logic;
-- Task Input
TxFIFO_W_Clk : in std_logic;
TxFIFO_Clr : in std_logic;
TxFIFO_W_Block : in std_logic;
TxFIFO_WE : in std_logic;
TxFIFO_WAddr : in std_logic_vector( TASKFIFO_BLOCK_AWIDTH - 1 downto 0 );
TxFIFO_WData : in std_logic_vector( TASKFIFO_DWIDTH - 1 downto 0 );
TxFIFO_Full : out std_logic;
TxFIFO_Empty : out std_logic;
-- zcpsm
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0)
);
end component;
component Eth_Tx_HighPriority
port(
reset : in std_logic;
clk : in std_logic;
clk_zcpsm : in std_logic;
s_Tx_Req : in std_logic;
m48_Tx_Req_DesMac : in std_logic_vector( 47 downto 0 );
m16_Tx_Req_Addr : in std_logic_vector( 15 downto 0 );
m16_Tx_Req_Data : in std_logic_vector( 15 downto 0 );
port_id : in std_logic_vector(7 downto 0);
write_strobe : in std_logic;
out_port : in std_logic_vector(7 downto 0);
read_strobe : in std_logic;
in_port : out std_logic_vector(7 downto 0)
);
end component;
component db_zcpsm
port(
reset : in std_logic;
clk : in std_logic;
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0));
end component;
component zcpsmIO2bus16
port(
reset : in std_logic;
debug_port_id : out std_logic_vector(15 downto 0);
debug_write_strobe : out std_logic;
debug_out_port : out std_logic_vector(15 downto 0);
debug_read_strobe : out std_logic;
debug_in_port : in std_logic_vector(15 downto 0);
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0));
end component;
component zcpsmDecode
port (
port_id_H : in std_logic_vector(3 downto 0);
ce : out std_logic_vector(15 downto 0)
);
end component;
component macAddrConfig
port (
ethtx_port_id : in std_logic_vector(7 downto 0);
ethrx_port_id : in std_logic_vector(7 downto 0);
db_port_id : in std_logic_vector(7 downto 0);
local_id_MAC0_Req : in std_logic_vector(7 downto 0);
local_id_MAC0_A : in std_logic_vector(7 downto 0);
local_id_MAC0_B : in std_logic_vector(7 downto 0);
local_id : in std_logic_vector(39 downto 0);
ethtx_in_port : out std_logic_vector(7 downto 0);
ethrx_in_port : out std_logic_vector(7 downto 0);
db_in_port : out std_logic_vector(7 downto 0)
);
end component;
signal ethrx_port_id : std_logic_vector(7 downto 0);
signal ethrx_write_strobe : std_logic;
signal ethrx_out_port : std_logic_vector(7 downto 0);
signal ethrx_read_strobe : std_logic;
signal ethrx_in_port : std_logic_vector(7 downto 0);
signal ethtx_port_id : std_logic_vector(7 downto 0);
signal ethtx_write_strobe : std_logic;
signal ethtx_out_port : std_logic_vector(7 downto 0);
signal ethtx_read_strobe : std_logic;
signal ethtx_in_port : std_logic_vector(7 downto 0);
signal db_port_id : std_logic_vector(7 downto 0);
signal db_write_strobe : std_logic;
signal db_out_port : std_logic_vector(7 downto 0);
signal db_read_strobe : std_logic;
signal db_in_port : std_logic_vector(7 downto 0);
signal debug_port_id : std_logic_vector(15 downto 0);
signal debug_write_strobe : std_logic;
signal debug_out_port : std_logic_vector(15 downto 0);
signal debug_read_strobe : std_logic;
signal debug_in_port : std_logic_vector(15 downto 0);
signal debug_in_port_pro : std_logic_vector(15 downto 0);
signal lastframe_flag : std_logic;
signal ethrx_busy : std_logic;
signal rxtask_wr_block : std_logic;
signal rxtask_wr_block_Reg : std_logic;
signal ethtx_task_ce : std_logic;
signal eth_tx_ce : std_logic;
signal eth_rx_ce : std_logic;
signal eth_rxdma_ce : std_logic;
signal ethrx_task_ce : std_logic;
signal db_rx_ce : std_logic;
signal db_tx_ce : std_logic;
signal db_debug_ce : std_logic;
signal txen_buf : std_logic;
signal db_ce : std_logic_vector(15 downto 0);
signal ethtx_ce : std_logic_vector(15 downto 0);
signal ethrx_ce : std_logic_vector(15 downto 0);
begin
test(0) <= not rxdv;
test(1) <= not txen_buf;
------------------------------------------------------------------------------
-- RX
------------------------------------------------------------------------------
Eth100BaseRx : if MII_WIDTH = 4 generate
u_rx : ethrx
generic map(
HEAD_AWIDTH => ETHRX_HEAD_AWIDTH,
BUFF_AWIDTH => ETHRX_BUFF_AWIDTH,
FIFO_AWIDTH => ETHRX_FIFO_AWIDTH,
WR_CYCLE => RAM_WR_CYCLE,
RAM_AWIDTH => RAM_AWIDTH
)
port map(
clk => clk,
zcpsm_clk => zcpsm_clk,
reset => reset,
rxclk => rxclk,
rxd => rxd,
rxdv => rxdv,
db_ce => db_rx_ce,
db_port_id => db_port_id(3 downto 0),
db_write_strobe => db_write_strobe,
db_out_port => db_out_port,
db_read_strobe => db_read_strobe,
db_in_port => db_in_port,
eth_ce => eth_rx_ce,
eth_port_id => ethrx_port_id(3 downto 0),
eth_write_strobe => ethrx_write_strobe,
eth_out_port => ethrx_out_port,
eth_read_strobe => ethrx_read_strobe,
eth_in_port => ethrx_in_port,
eth_dma_ce => eth_rxdma_ce,
ethrx_busy => ethrx_busy,
recvtime => recvtime,
recvtime_valid => recvtime_valid,
localtime_locked => localtime_locked,
lastframe_flag => lastframe_flag,
ram_wren => ram_wren,
ram_waddr => ram_waddr,
-----
ram_wdata => ram_wdata
);
end generate Eth100BaseRx;
Eth1000BaseRx : if MII_WIDTH = 8 generate
u_rx : g_ethrx
generic map(
HEAD_AWIDTH => ETHRX_HEAD_AWIDTH,
BUFF_AWIDTH => ETHRX_BUFF_AWIDTH,
FIFO_AWIDTH => ETHRX_FIFO_AWIDTH,
WR_CYCLE => RAM_WR_CYCLE,
RAM_AWIDTH => RAM_AWIDTH
)
port map(
clk => clk,
zcpsm_clk => zcpsm_clk,
reset => reset,
rxclk => rxclk,
rxd => rxd,
rxdv => rxdv,
db_ce => db_rx_ce,
db_port_id => db_port_id(3 downto 0),
db_write_strobe => db_write_strobe,
db_out_port => db_out_port,
db_read_strobe => db_read_strobe,
db_in_port => db_in_port,
eth_ce => eth_rx_ce,
eth_port_id => ethrx_port_id(3 downto 0),
eth_write_strobe => ethrx_write_strobe,
eth_out_port => ethrx_out_port,
eth_read_strobe => ethrx_read_strobe,
eth_in_port => ethrx_in_port,
eth_dma_ce => eth_rxdma_ce,
ethrx_busy => ethrx_busy,
recvtime => recvtime,
recvtime_valid => recvtime_valid,
localtime_locked => localtime_locked,
lastframe_flag => lastframe_flag,
ram_wren => ram_wren,
ram_waddr => ram_waddr,
-----
ram_wdata => ram_wdata
);
end generate Eth1000BaseRx;
-- db_rx_ce <= '1' when db_port_id(7 downto 4) = PORTS_DB_RX else '0';
-- eth_rx_ce <= '1' when ethrx_port_id(7 downto 4) = PORTS_ETH_RX else '0';
-- eth_rxdma_ce <= '1' when ethrx_port_id(7 downto 4) = PORTS_ETH_RXDMA else '0';
db_rx_ce <= db_ce(conv_integer(PORTS_DB_RX));
eth_rx_ce <= ethrx_ce(conv_integer(PORTS_ETH_RX));
eth_rxdma_ce <= ethrx_ce(conv_integer(PORTS_ETH_RXDMA));
u_ethrx_zcpsm : ethrx_zcpsm
port map(
reset => reset,
clk => zcpsm_clk,
port_id => ethrx_port_id,
write_strobe => ethrx_write_strobe,
out_port => ethrx_out_port,
read_strobe => ethrx_read_strobe,
in_port => ethrx_in_port
);
u_ethrx_zcpsm_ce : zcpsmDecode
port map(
port_id_H => ethrx_port_id( 7 downto 4),
ce => ethrx_ce
);
u_ethrx_task : ethrx_task
generic map (
TASKFIFO_DWIDTH => TASKFIFO_DWIDTH,
TASKFIFO_BLOCK_DEPTH => RX_TASKFIFO_BLOCK_DEPTH,
TASKFIFO_BLOCK_AWIDTH => RX_TASKFIFO_BLOCK_AWIDTH,
TASKFIFO_DEPTH => RX_TASKFIFO_DEPTH,
TASKFIFO_AWIDTH => RX_TASKFIFO_AWIDTH,
TASKFIFO_RAM_TYPE => RX_TASKFIFO_RAM_TYPE
)
port map(
reset => reset,
-- Task Input
RxFIFO_R_Clk => RxFIFO_R_Clk,
RxFIFO_R_Block => RxFIFO_R_Block,
RxFIFO_RAddr => RxFIFO_RAddr,
RxFIFO_RData => RxFIFO_RData,
RxFIFO_Full => open,
-- RxFIFO_Full => RxFIFO_Full,
RxFIFO_Empty => RxFIFO_Empty,
fifo_wr_block => rxtask_wr_block,
-- zcpsm
zcpsm_clk => zcpsm_clk,
zcpsm_ce => ethrx_task_ce,
zcpsm_port_id => ethrx_port_id(3 downto 0),
zcpsm_write_strobe => ethrx_write_strobe,
zcpsm_out_port => ethrx_out_port,
zcpsm_read_strobe => ethrx_read_strobe,
zcpsm_in_port => ethrx_in_port
);
-- ethrx_task_ce <= '1' when ethrx_port_id(7 downto 4) = PORTS_ETH_RX_TASK else '0';
ethrx_task_ce <= ethrx_ce(conv_integer(PORTS_ETH_RX_TASK));
u_dma2rxtask: dma2rxtask
port map(
reset => reset,
zcpsm_clk => zcpsm_clk,
busy => ethrx_busy,
lastframe => lastframe_flag,
rxtask_wr_block => rxtask_wr_block_Reg
);
-- ethrx_in_port <= local_id_MAC0_A when ethrx_port_id = PORT_ETH_LOCAL_ID_0_A else
-- local_id_MAC0_B when ethrx_port_id = PORT_ETH_LOCAL_ID_0_B else
-- local_id( 39 downto 32 ) when ethrx_port_id = PORT_ETH_LOCAL_ID_1 else
-- local_id( 31 downto 24 ) when ethrx_port_id = PORT_ETH_LOCAL_ID_2 else
-- local_id( 23 downto 16 ) when ethrx_port_id = PORT_ETH_LOCAL_ID_3 else
-- local_id( 15 downto 8 ) when ethrx_port_id = PORT_ETH_LOCAL_ID_4 else
-- local_id( 7 downto 0 ) when ethrx_port_id = PORT_ETH_LOCAL_ID_5 else
-- (others => 'Z');
u_wr_block : asyncwrite -- rxtask_wr_block must be synchronized with clk
port map(
reset => reset,
async_clk => zcpsm_clk,
sync_clk => clk,
async_wren => rxtask_wr_block_Reg,
trigger => '1',
sync_wren => rxtask_wr_block,
over => open,
flag => open
);
------------------------------------------------------------------------------
-- TX
------------------------------------------------------------------------------
Eth100BaseTx : if MII_WIDTH = 4 generate
u_tx : ethtx
generic map(
HEAD_AWIDTH => ETHTX_HEAD_AWIDTH,
BUFF_AWIDTH => ETHTX_BUFF_AWIDTH,
FIFO_AWIDTH => ETHTX_FIFO_AWIDTH,
RD_CYCLE => RAM_RD_CYCLE,
RD_DELAY => RAM_RD_DELAY,
RAM_AWIDTH => RAM_AWIDTH
)
port map(
clk => clk,
zcpsm_clk => zcpsm_clk,
reset => reset,
txclk => txclk,
txd => txd,
txen => txen_buf,
db_ce => db_tx_ce,
db_port_id => db_port_id(3 downto 0),
db_write_strobe => db_write_strobe,
db_out_port => db_out_port,
db_read_strobe => db_read_strobe,
db_in_port => db_in_port,
eth_ce => eth_tx_ce,
eth_port_id => ethtx_port_id(3 downto 0),
eth_write_strobe => ethtx_write_strobe,
eth_out_port => ethtx_out_port,
eth_read_strobe => ethtx_read_strobe,
eth_in_port => ethtx_in_port,
ram_raddr => ram_raddr,
ram_rdata => ram_rdata,
-- local time--
localtime => localtime
);
end generate Eth100BaseTx;
Eth1000BaseTx : if MII_WIDTH = 8 generate
u_tx : g_ethtx
generic map(
HEAD_AWIDTH => ETHTX_HEAD_AWIDTH,
BUFF_AWIDTH => ETHTX_BUFF_AWIDTH,
FIFO_AWIDTH => ETHTX_FIFO_AWIDTH,
RD_CYCLE => RAM_RD_CYCLE,
RD_DELAY => RAM_RD_DELAY,
RAM_AWIDTH => RAM_AWIDTH
)
port map(
clk => clk,
zcpsm_clk => zcpsm_clk,
reset => reset,
txclk => txclk,
txd => txd,
txen => txen_buf,
db_ce => db_tx_ce,
db_port_id => db_port_id(3 downto 0),
db_write_strobe => db_write_strobe,
db_out_port => db_out_port,
db_read_strobe => db_read_strobe,
db_in_port => db_in_port,
eth_ce => eth_tx_ce,
eth_port_id => ethtx_port_id(3 downto 0),
eth_write_strobe => ethtx_write_strobe,
eth_out_port => ethtx_out_port,
eth_read_strobe => ethtx_read_strobe,
eth_in_port => ethtx_in_port,
ram_raddr => ram_raddr,
ram_rdata => ram_rdata,
-- local time--
localtime => localtime
);
end generate Eth1000BaseTx;
txen <= txen_buf;
-- db_tx_ce <= '1' when db_port_id(7 downto 4) = PORTS_DB_TX else '0';
-- eth_tx_ce <= '1' when ethtx_port_id(7 downto 4) = PORTS_ETH_TX else '0';
db_tx_ce <= db_ce(conv_integer(PORTS_DB_TX));
eth_tx_ce <= ethtx_ce(conv_integer(PORTS_ETH_TX));
-- eth tx zcpsm
u_ethtx_zcpsm : ethtx_zcpsm
port map(
reset => reset,
clk => zcpsm_clk,
port_id => ethtx_port_id,
write_strobe => ethtx_write_strobe,
out_port => ethtx_out_port,
read_strobe => ethtx_read_strobe,
in_port => ethtx_in_port
);
u_ethtx_zcpsm_ce : zcpsmDecode
port map(
port_id_H => ethtx_port_id( 7 downto 4),
ce => ethtx_ce
);
mo_Eth_Tx_HighPriority : Eth_Tx_HighPriority
port map(
reset => reset,
clk => clk,
clk_zcpsm => zcpsm_clk,
s_Tx_Req => s_HighPri_Tx_Req,
m48_Tx_Req_DesMac => m48_HighPri_Tx_Req_DesMac,
m16_Tx_Req_Addr => m16_HighPri_Tx_Req_Addr,
m16_Tx_Req_Data => m16_HighPri_Tx_Req_Data,
port_id => ethtx_port_id,
write_strobe => ethtx_write_strobe,
out_port => ethtx_out_port,
read_strobe => ethtx_read_strobe,
in_port => ethtx_in_port
);
u_ethtx_task : ethtx_task
generic map(
TASKFIFO_DWIDTH => TASKFIFO_DWIDTH,
TASKFIFO_BLOCK_DEPTH => TX_TASKFIFO_BLOCK_DEPTH,
TASKFIFO_BLOCK_AWIDTH => TX_TASKFIFO_BLOCK_AWIDTH,
TASKFIFO_DEPTH => TX_TASKFIFO_DEPTH,
TASKFIFO_AWIDTH => TX_TASKFIFO_AWIDTH,
TASKFIFO_RAM_TYPE => TX_TASKFIFO_RAM_TYPE
)
port map(
reset => reset,
-- Task Input
TxFIFO_W_Clk => TxFIFO_W_Clk,
TxFIFO_Clr => TxFIFO_Clr,
TxFIFO_W_Block => TxFIFO_W_Block,
TxFIFO_WE => TxFIFO_WE,
TxFIFO_WAddr => TxFIFO_WAddr,
TxFIFO_WData => TxFIFO_WData,
TxFIFO_Full => TxFIFO_Full,
-- TxFIFO_Empty => TxFIFO_Empty,
TxFIFO_Empty => open,
-- zcpsm
zcpsm_clk => zcpsm_clk,
zcpsm_ce => ethtx_task_ce,
zcpsm_port_id => ethtx_port_id(3 downto 0),
zcpsm_write_strobe => ethtx_write_strobe,
zcpsm_out_port => ethtx_out_port,
zcpsm_read_strobe => ethtx_read_strobe,
zcpsm_in_port => ethtx_in_port
);
-- ethtx_task_ce <= '1' when ethtx_port_id(7 downto 4) = PORTS_ETH_TX_TASK else '0';
ethtx_task_ce <= ethtx_ce(conv_integer(PORTS_ETH_TX_TASK));
-- ethtx_in_port <= local_id_MAC0_Req when ethtx_port_id = PORT_ETH_LOCAL_ID_0_REQ else
-- local_id_MAC0_A when ethtx_port_id = PORT_ETH_LOCAL_ID_0_A else
-- local_id_MAC0_B when ethtx_port_id = PORT_ETH_LOCAL_ID_0_B else
-- local_id( 39 downto 32 ) when ethtx_port_id = PORT_ETH_LOCAL_ID_1 else
-- local_id( 31 downto 24 ) when ethtx_port_id = PORT_ETH_LOCAL_ID_2 else
-- local_id( 23 downto 16 ) when ethtx_port_id = PORT_ETH_LOCAL_ID_3 else
-- local_id( 15 downto 8 ) when ethtx_port_id = PORT_ETH_LOCAL_ID_4 else
-- local_id( 7 downto 0 ) when ethtx_port_id = PORT_ETH_LOCAL_ID_5 else
-- (others => 'Z');
------------------------------------------------------------------------------
-- DB zcpsm
------------------------------------------------------------------------------
u_db_zcpsm : db_zcpsm
port map(
reset => reset,
clk => zcpsm_clk,
port_id => db_port_id,
write_strobe => db_write_strobe,
out_port => db_out_port,
read_strobe => db_read_strobe,
in_port => db_in_port
);
u_db_zcpsm_ce : zcpsmDecode
port map(
port_id_H => db_port_id( 7 downto 4),
ce => db_ce
);
------------------------------------------------------------------------------
-- DEBUG & PROG
------------------------------------------------------------------------------
u_zcpsmIO2bus16 : zcpsmIO2bus16
port map(
reset => reset,
zcpsm_clk => zcpsm_clk,
debug_port_id => debug_port_id,
debug_write_strobe => debug_write_strobe,
debug_out_port => debug_out_port,
debug_read_strobe => debug_read_strobe,
debug_in_port => debug_in_port,
zcpsm_ce => db_debug_ce,
zcpsm_port_id => db_port_id(3 downto 0),
zcpsm_write_strobe => db_write_strobe,
zcpsm_out_port => db_out_port,
zcpsm_read_strobe => db_read_strobe,
zcpsm_in_port => db_in_port
);
-- db_debug_ce <= '1' when db_port_id(7 downto 4) = PORTS_DB_DEBUG else '0';
db_debug_ce <= db_ce(conv_integer(PORTS_DB_DEBUG));
------------------------------------------------------------------------------
-- IO
------------------------------------------------------------------------------
debugIO_port_id <= debug_port_id;
debugIO_write_strobe<= debug_write_strobe;
debugIO_out_port <= debug_out_port;
debugIO_read_strobe <= debug_read_strobe;
debug_in_port <= debug_in_port_pro when debug_port_id(15 downto 12) = PORTS_DEBUG_PROG else
debugIO_in_port;
------------------------------------------------------------------------------
-- LOCAL ID
------------------------------------------------------------------------------
-- db_in_port <= local_id_MAC0_A when db_port_id = PORT_DB_LOCAL_ID_0_A else
-- local_id_MAC0_B when db_port_id = PORT_DB_LOCAL_ID_0_B else
-- local_id( 39 downto 32 ) when db_port_id = PORT_DB_LOCAL_ID_1 else
-- local_id( 31 downto 24 ) when db_port_id = PORT_DB_LOCAL_ID_2 else
-- local_id( 23 downto 16 ) when db_port_id = PORT_DB_LOCAL_ID_3 else
-- local_id( 15 downto 8 ) when db_port_id = PORT_DB_LOCAL_ID_4 else
-- local_id( 7 downto 0 ) when db_port_id = PORT_DB_LOCAL_ID_5 else
-- (others => 'Z');
u_macAddr : macAddrConfig
port map(
ethtx_port_id => ethtx_port_id,
ethrx_port_id => ethrx_port_id,
db_port_id => db_port_id,
local_id_MAC0_Req => local_id_MAC0_Req,
local_id_MAC0_A => local_id_MAC0_A,
local_id_MAC0_B => local_id_MAC0_B,
local_id => local_id,
ethtx_in_port => ethtx_in_port,
ethrx_in_port => ethrx_in_port,
db_in_port => db_in_port
);
end arch_eth;
|
---------------------------------------------------------------------------------------------
-- VIDEO DELAY - Hex to 7 Segment
--
-- Part of the Synkie Project: www.synkie.net
--
-- © 2013 Michael Egger, Licensed under GNU GPLv3
--
--------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity Bin_2_BCD is
port
(
bin : in std_logic_vector (8 downto 0); -- binary input
bcd : out std_logic_vector (9 downto 0); -- bcd output
);
end Hex_7_Seg;
architecture Bin_2_BCD_Arch of Bin_2_BCD is
begin
process(bin)
variable z : std_logic_vector (17 downto 0);
for i in o to 17 loop
z(i) := '0';
end loop;
z(10 downto 3) := bin;
for i in 0 to 4 loop
if z(11 downto 8) > 4 then
z(11 downto 8) := z(11 downto 8) + 3;
end if;
if z (15 downto 12) > 4 then
z (15 downto 12) := z (15 downto 12) + 3;
end if
z(17 downto 1) := z (16 downto 0);
end loop;
p <= z(17 downto 8);
end process;
end Bin_2_BCD;
|
architecture rtl of fifo is
begin
connect_ports(port_1 => data, port_2 => enable, port_3 => overflow, port_4 => underflow);
connect_ports(
port_1 => data, port_2 => enable, port_3 => overflow, port_4 => underflow);
connect_ports(port_1 => data,
port_2 => enable,
port_3 => overflow,
port_4 => underflow);
connect_ports(port_1 => data, port_2 => enable, port_3 => overflow, port_4 => underflow
);
connect_ports(
port_1 => data,
port_2 => enable,
port_3 => overflow,
port_4 => underflow
);
connect_ports(
port_1 => data
,
port_2 => enable,
port_3 => overflow
,
port_4 => underflow
);
process
begin
connect_ports(
port_1 => data,
port_2=> enable,
port_3 => overflow,
port_4 => underflow
);
end process;
end architecture;
|
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2014/04/24 17:41:30
-- Nombre del módulo: clk_rom - Behavioral
-- Comentarios adicionales:
-- Este divisor de frecuencia toma sus valores de una memoria ROM que contiene
-- los valores de los contadores. Por lo tanto, el rango de frecuencias depende
-- de la ROM.
--
-- Comentarios adicionales:
-- Se puede encontrar más información en la siguiente dirección:
-- http://www.estadofinito.com/metronomo-en-vhdl-2/
--
-- Revisión:
-- Revisión 0.02 - El tiempo en alto es constante, y corresponde a un periodo de
-- 10Hz (el sonido del metrónomo debe tener la misma duración
-- para todas las diversas frecuencias).
-- Dicha frecuencia debe ser mayor a la frecuencia mayor del
-- sistema, F > 512 BPM (u 8.53 Hz).
-- En este caso, la frecuencia o tiempo en alto es de 10Hz.
-- Revisión 0.01 - Archivo creado.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_1164.ALL;
entity clk_rom is
GENERIC (
NBITS : integer := 28 -- Cantidad de bits que tiene cada registro en la ROM.
);
PORT (
clk : in STD_LOGIC; -- Reloj de entrada de 3.125MHz.
reset : in STD_LOGIC;
escala : in STD_LOGIC_VECTOR(NBITS-1 downto 0);
clk_out : out STD_LOGIC -- Reloj de salida, dependiente del valor en memoria.
);
end clk_rom;
architecture Behavioral of clk_rom is
-- Señal utilizada para procesamiento interno de la señal de salida.
signal temporal : STD_LOGIC;
-- Señal que cubre el rango que puede alcanzar la ROM.
signal contador : integer range 0 to (2**(NBITS-4))-1 := 0;
-- Transformación de la escala de entrada a tipo numérico para el uso de operadores aritméticos.
signal escala_num : UNSIGNED(NBITS-1 downto 0) := (others => '0');
begin
-- Actualización de los datos de escala.
escala_num <= UNSIGNED(escala); -- Conversión de vector a número.
-- Procesamiento para el divisor de frecuencia.
divisor_frecuencia: process (clk, reset) begin
if (reset = '1') then
temporal <= '0';
contador <= 0;
elsif rising_edge(clk) then
if (contador = escala_num) then
contador <= 0;
else
if (contador < 312500) then
-- Tiempo de 10Hz en alto.
temporal <= '1';
else
-- Todo lo demás en bajo.
temporal <= '0';
end if;
contador <= contador + 1;
end if;
end if;
end process;
-- Asignación de la señal de salida.
clk_out <= temporal;
end Behavioral; |
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2014/04/24 17:41:30
-- Nombre del módulo: clk_rom - Behavioral
-- Comentarios adicionales:
-- Este divisor de frecuencia toma sus valores de una memoria ROM que contiene
-- los valores de los contadores. Por lo tanto, el rango de frecuencias depende
-- de la ROM.
--
-- Comentarios adicionales:
-- Se puede encontrar más información en la siguiente dirección:
-- http://www.estadofinito.com/metronomo-en-vhdl-2/
--
-- Revisión:
-- Revisión 0.02 - El tiempo en alto es constante, y corresponde a un periodo de
-- 10Hz (el sonido del metrónomo debe tener la misma duración
-- para todas las diversas frecuencias).
-- Dicha frecuencia debe ser mayor a la frecuencia mayor del
-- sistema, F > 512 BPM (u 8.53 Hz).
-- En este caso, la frecuencia o tiempo en alto es de 10Hz.
-- Revisión 0.01 - Archivo creado.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_1164.ALL;
entity clk_rom is
GENERIC (
NBITS : integer := 28 -- Cantidad de bits que tiene cada registro en la ROM.
);
PORT (
clk : in STD_LOGIC; -- Reloj de entrada de 3.125MHz.
reset : in STD_LOGIC;
escala : in STD_LOGIC_VECTOR(NBITS-1 downto 0);
clk_out : out STD_LOGIC -- Reloj de salida, dependiente del valor en memoria.
);
end clk_rom;
architecture Behavioral of clk_rom is
-- Señal utilizada para procesamiento interno de la señal de salida.
signal temporal : STD_LOGIC;
-- Señal que cubre el rango que puede alcanzar la ROM.
signal contador : integer range 0 to (2**(NBITS-4))-1 := 0;
-- Transformación de la escala de entrada a tipo numérico para el uso de operadores aritméticos.
signal escala_num : UNSIGNED(NBITS-1 downto 0) := (others => '0');
begin
-- Actualización de los datos de escala.
escala_num <= UNSIGNED(escala); -- Conversión de vector a número.
-- Procesamiento para el divisor de frecuencia.
divisor_frecuencia: process (clk, reset) begin
if (reset = '1') then
temporal <= '0';
contador <= 0;
elsif rising_edge(clk) then
if (contador = escala_num) then
contador <= 0;
else
if (contador < 312500) then
-- Tiempo de 10Hz en alto.
temporal <= '1';
else
-- Todo lo demás en bajo.
temporal <= '0';
end if;
contador <= contador + 1;
end if;
end if;
end process;
-- Asignación de la señal de salida.
clk_out <= temporal;
end Behavioral; |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package system_types is
-- code from book
type system_status is (idle, active, overloaded);
-- end code from book
end package system_types;
entity inline_05 is
end entity inline_05;
----------------------------------------------------------------
architecture test of inline_05 is
-- code from book
alias status_type is work.system_types.system_status;
-- end code from book
begin
process_2_b : process is
variable status : status_type := idle;
begin
wait for 10 ns;
status := active;
wait for 10 ns;
status := overloaded;
wait;
end process process_2_b;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package system_types is
-- code from book
type system_status is (idle, active, overloaded);
-- end code from book
end package system_types;
entity inline_05 is
end entity inline_05;
----------------------------------------------------------------
architecture test of inline_05 is
-- code from book
alias status_type is work.system_types.system_status;
-- end code from book
begin
process_2_b : process is
variable status : status_type := idle;
begin
wait for 10 ns;
status := active;
wait for 10 ns;
status := overloaded;
wait;
end process process_2_b;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package system_types is
-- code from book
type system_status is (idle, active, overloaded);
-- end code from book
end package system_types;
entity inline_05 is
end entity inline_05;
----------------------------------------------------------------
architecture test of inline_05 is
-- code from book
alias status_type is work.system_types.system_status;
-- end code from book
begin
process_2_b : process is
variable status : status_type := idle;
begin
wait for 10 ns;
status := active;
wait for 10 ns;
status := overloaded;
wait;
end process process_2_b;
end architecture test;
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-08 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_05000_bad.vhd
-- File Creation date : 2015-04-08
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Sensitivity list for synchronous processes: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity STD_05000_bad is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end STD_05000_bad;
architecture Behavioral of STD_05000_bad is
signal Q : std_logic; -- D Flip-Flop output
begin
--CODE
-- D FlipFlop process
P_FlipFlop : process(i_Clock, i_Reset_n, i_D)
begin
if (i_Reset_n = '0') then
Q <= '0';
elsif (rising_edge(i_Clock)) then
Q <= i_D;
end if;
end process;
--CODE
o_Q <= Q;
end Behavioral;
|
library verilog;
use verilog.vl_types.all;
entity LOG_Table is
port(
address : in vl_logic_vector(12 downto 0);
clock : in vl_logic;
q : out vl_logic_vector(7 downto 0)
);
end LOG_Table;
|
library verilog;
use verilog.vl_types.all;
entity LOG_Table is
port(
address : in vl_logic_vector(12 downto 0);
clock : in vl_logic;
q : out vl_logic_vector(7 downto 0)
);
end LOG_Table;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity p_bsf32_hw is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
bus_r : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (4 downto 0);
ap_ce : IN STD_LOGIC );
end;
architecture behav of p_bsf32_hw is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv5_1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_const_lv5_2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_const_lv5_3 : STD_LOGIC_VECTOR (4 downto 0) := "00011";
constant ap_const_lv5_4 : STD_LOGIC_VECTOR (4 downto 0) := "00100";
constant ap_const_lv5_5 : STD_LOGIC_VECTOR (4 downto 0) := "00101";
constant ap_const_lv5_6 : STD_LOGIC_VECTOR (4 downto 0) := "00110";
constant ap_const_lv5_7 : STD_LOGIC_VECTOR (4 downto 0) := "00111";
constant ap_const_lv5_8 : STD_LOGIC_VECTOR (4 downto 0) := "01000";
constant ap_const_lv5_9 : STD_LOGIC_VECTOR (4 downto 0) := "01001";
constant ap_const_lv5_A : STD_LOGIC_VECTOR (4 downto 0) := "01010";
constant ap_const_lv5_B : STD_LOGIC_VECTOR (4 downto 0) := "01011";
constant ap_const_lv5_C : STD_LOGIC_VECTOR (4 downto 0) := "01100";
constant ap_const_lv5_D : STD_LOGIC_VECTOR (4 downto 0) := "01101";
constant ap_const_lv5_E : STD_LOGIC_VECTOR (4 downto 0) := "01110";
constant ap_const_lv5_F : STD_LOGIC_VECTOR (4 downto 0) := "01111";
constant ap_const_lv5_10 : STD_LOGIC_VECTOR (4 downto 0) := "10000";
constant ap_const_lv5_11 : STD_LOGIC_VECTOR (4 downto 0) := "10001";
constant ap_const_lv5_12 : STD_LOGIC_VECTOR (4 downto 0) := "10010";
constant ap_const_lv5_13 : STD_LOGIC_VECTOR (4 downto 0) := "10011";
constant ap_const_lv5_14 : STD_LOGIC_VECTOR (4 downto 0) := "10100";
constant ap_const_lv5_15 : STD_LOGIC_VECTOR (4 downto 0) := "10101";
constant ap_const_lv5_16 : STD_LOGIC_VECTOR (4 downto 0) := "10110";
constant ap_const_lv5_17 : STD_LOGIC_VECTOR (4 downto 0) := "10111";
constant ap_const_lv5_18 : STD_LOGIC_VECTOR (4 downto 0) := "11000";
constant ap_const_lv5_19 : STD_LOGIC_VECTOR (4 downto 0) := "11001";
constant ap_const_lv5_1A : STD_LOGIC_VECTOR (4 downto 0) := "11010";
constant ap_const_lv5_1B : STD_LOGIC_VECTOR (4 downto 0) := "11011";
constant ap_const_lv5_1C : STD_LOGIC_VECTOR (4 downto 0) := "11100";
constant ap_const_lv5_1D : STD_LOGIC_VECTOR (4 downto 0) := "11101";
constant ap_const_lv5_1E : STD_LOGIC_VECTOR (4 downto 0) := "11110";
constant ap_const_lv5_1F : STD_LOGIC_VECTOR (4 downto 0) := "11111";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001";
constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010";
constant ap_const_lv32_1B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011011";
constant ap_const_lv32_1C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011100";
constant ap_const_lv32_1D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011101";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_true : BOOLEAN := true;
signal tmp_fu_278_p1 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_reg_522 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_7_fu_282_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_7_reg_526 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_fu_290_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_reg_530 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_9_fu_298_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_9_reg_534 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_10_fu_306_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_10_reg_538 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_fu_314_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_reg_542 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_12_fu_322_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_12_reg_546 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_13_fu_330_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_13_reg_550 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_14_fu_338_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_14_reg_554 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_15_fu_346_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_15_reg_558 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_16_fu_354_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_16_reg_562 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_17_fu_362_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_17_reg_566 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_18_fu_370_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_18_reg_570 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_19_fu_378_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_19_reg_574 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_20_fu_386_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_20_reg_578 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_21_fu_394_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_21_reg_582 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_22_fu_402_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_22_reg_586 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_23_fu_410_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_23_reg_590 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_24_fu_418_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_24_reg_594 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_25_fu_426_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_25_reg_598 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_26_fu_434_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_26_reg_602 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_27_fu_442_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_27_reg_606 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_28_fu_450_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_28_reg_610 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_29_fu_458_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_29_reg_614 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_30_fu_466_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_30_reg_618 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_fu_474_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_622 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_32_fu_482_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_32_reg_626 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_33_fu_490_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_33_reg_630 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_34_fu_498_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_34_reg_634 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_35_fu_506_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_35_reg_638 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_36_fu_514_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_36_reg_642 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_phiprechg_p_s_reg_136pp0_it0 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_phiprechg_p_s_reg_136pp0_it1 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_phiprechg_merge_reg_265pp0_it0 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_phiprechg_merge_reg_265pp0_it1 : STD_LOGIC_VECTOR (4 downto 0);
signal merge_phi_fu_269_p4 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_sig_bdd_764 : BOOLEAN;
signal ap_sig_bdd_178 : BOOLEAN;
signal ap_sig_bdd_183 : BOOLEAN;
signal ap_sig_bdd_189 : BOOLEAN;
signal ap_sig_bdd_196 : BOOLEAN;
signal ap_sig_bdd_204 : BOOLEAN;
signal ap_sig_bdd_213 : BOOLEAN;
signal ap_sig_bdd_223 : BOOLEAN;
signal ap_sig_bdd_234 : BOOLEAN;
signal ap_sig_bdd_246 : BOOLEAN;
signal ap_sig_bdd_259 : BOOLEAN;
signal ap_sig_bdd_273 : BOOLEAN;
signal ap_sig_bdd_288 : BOOLEAN;
signal ap_sig_bdd_304 : BOOLEAN;
signal ap_sig_bdd_321 : BOOLEAN;
signal ap_sig_bdd_339 : BOOLEAN;
signal ap_sig_bdd_358 : BOOLEAN;
signal ap_sig_bdd_378 : BOOLEAN;
signal ap_sig_bdd_399 : BOOLEAN;
signal ap_sig_bdd_421 : BOOLEAN;
signal ap_sig_bdd_444 : BOOLEAN;
signal ap_sig_bdd_468 : BOOLEAN;
signal ap_sig_bdd_493 : BOOLEAN;
signal ap_sig_bdd_519 : BOOLEAN;
signal ap_sig_bdd_546 : BOOLEAN;
signal ap_sig_bdd_574 : BOOLEAN;
signal ap_sig_bdd_603 : BOOLEAN;
signal ap_sig_bdd_633 : BOOLEAN;
signal ap_sig_bdd_664 : BOOLEAN;
signal ap_sig_bdd_696 : BOOLEAN;
signal ap_sig_bdd_730 : BOOLEAN;
begin
-- ap_reg_phiprechg_merge_reg_265pp0_it1 assign process. --
ap_reg_phiprechg_merge_reg_265pp0_it1_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_ce)) then
if (ap_sig_bdd_764) then
ap_reg_phiprechg_merge_reg_265pp0_it1(1) <= '1';
ap_reg_phiprechg_merge_reg_265pp0_it1(2) <= '1';
ap_reg_phiprechg_merge_reg_265pp0_it1(3) <= '1';
ap_reg_phiprechg_merge_reg_265pp0_it1(4) <= '1';
elsif ((ap_true = ap_true)) then
ap_reg_phiprechg_merge_reg_265pp0_it1(1) <= ap_reg_phiprechg_merge_reg_265pp0_it0(1);
ap_reg_phiprechg_merge_reg_265pp0_it1(2) <= ap_reg_phiprechg_merge_reg_265pp0_it0(2);
ap_reg_phiprechg_merge_reg_265pp0_it1(3) <= ap_reg_phiprechg_merge_reg_265pp0_it0(3);
ap_reg_phiprechg_merge_reg_265pp0_it1(4) <= ap_reg_phiprechg_merge_reg_265pp0_it0(4);
end if;
end if;
end if;
end process;
-- ap_reg_phiprechg_p_s_reg_136pp0_it1 assign process. --
ap_reg_phiprechg_p_s_reg_136pp0_it1_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_ce)) then
if (ap_sig_bdd_730) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1E;
elsif (ap_sig_bdd_696) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1D;
elsif (ap_sig_bdd_664) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1C;
elsif (ap_sig_bdd_633) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1B;
elsif (ap_sig_bdd_603) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1A;
elsif (ap_sig_bdd_574) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_19;
elsif (ap_sig_bdd_546) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_18;
elsif (ap_sig_bdd_519) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_17;
elsif (ap_sig_bdd_493) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_16;
elsif (ap_sig_bdd_468) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_15;
elsif (ap_sig_bdd_444) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_14;
elsif (ap_sig_bdd_421) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_13;
elsif (ap_sig_bdd_399) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_12;
elsif (ap_sig_bdd_378) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_11;
elsif (ap_sig_bdd_358) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_10;
elsif (ap_sig_bdd_339) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_F;
elsif (ap_sig_bdd_321) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_E;
elsif (ap_sig_bdd_304) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_D;
elsif (ap_sig_bdd_288) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_C;
elsif (ap_sig_bdd_273) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_B;
elsif (ap_sig_bdd_259) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_A;
elsif (ap_sig_bdd_246) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_9;
elsif (ap_sig_bdd_234) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_8;
elsif (ap_sig_bdd_223) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_7;
elsif (ap_sig_bdd_213) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_6;
elsif (ap_sig_bdd_204) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_5;
elsif (ap_sig_bdd_196) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_4;
elsif (ap_sig_bdd_189) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_3;
elsif (ap_sig_bdd_183) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_2;
elsif (ap_sig_bdd_178) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1;
elsif (not((tmp_fu_278_p1 = ap_const_lv1_0))) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_0;
elsif ((ap_true = ap_true)) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_reg_phiprechg_p_s_reg_136pp0_it0;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3))) then
tmp_10_reg_538 <= bus_r(4 downto 4);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3))) then
tmp_11_reg_542 <= bus_r(5 downto 5);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3))) then
tmp_12_reg_546 <= bus_r(6 downto 6);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3))) then
tmp_13_reg_550 <= bus_r(7 downto 7);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3))) then
tmp_14_reg_554 <= bus_r(8 downto 8);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3))) then
tmp_15_reg_558 <= bus_r(9 downto 9);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3))) then
tmp_16_reg_562 <= bus_r(10 downto 10);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3))) then
tmp_17_reg_566 <= bus_r(11 downto 11);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3))) then
tmp_18_reg_570 <= bus_r(12 downto 12);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3))) then
tmp_19_reg_574 <= bus_r(13 downto 13);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3))) then
tmp_20_reg_578 <= bus_r(14 downto 14);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3))) then
tmp_21_reg_582 <= bus_r(15 downto 15);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3))) then
tmp_22_reg_586 <= bus_r(16 downto 16);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3))) then
tmp_23_reg_590 <= bus_r(17 downto 17);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3))) then
tmp_24_reg_594 <= bus_r(18 downto 18);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3))) then
tmp_25_reg_598 <= bus_r(19 downto 19);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3))) then
tmp_26_reg_602 <= bus_r(20 downto 20);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3))) then
tmp_27_reg_606 <= bus_r(21 downto 21);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3))) then
tmp_28_reg_610 <= bus_r(22 downto 22);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3))) then
tmp_29_reg_614 <= bus_r(23 downto 23);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3))) then
tmp_30_reg_618 <= bus_r(24 downto 24);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3))) then
tmp_31_reg_622 <= bus_r(25 downto 25);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3))) then
tmp_32_reg_626 <= bus_r(26 downto 26);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3))) then
tmp_33_reg_630 <= bus_r(27 downto 27);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3) and (ap_const_lv1_0 = tmp_33_fu_490_p3))) then
tmp_34_reg_634 <= bus_r(28 downto 28);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3) and (ap_const_lv1_0 = tmp_33_fu_490_p3) and (ap_const_lv1_0 = tmp_34_fu_498_p3))) then
tmp_35_reg_638 <= bus_r(29 downto 29);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3) and (ap_const_lv1_0 = tmp_33_fu_490_p3) and (ap_const_lv1_0 = tmp_34_fu_498_p3) and (ap_const_lv1_0 = tmp_35_fu_506_p3))) then
tmp_36_reg_642 <= bus_r(30 downto 30);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0))) then
tmp_7_reg_526 <= bus_r(1 downto 1);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0))) then
tmp_8_reg_530 <= bus_r(2 downto 2);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3))) then
tmp_9_reg_534 <= bus_r(3 downto 3);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_ce)) then
tmp_reg_522 <= tmp_fu_278_p1;
end if;
end if;
end process;
ap_reg_phiprechg_merge_reg_265pp0_it1(0) <= '1';
ap_reg_phiprechg_merge_reg_265pp0_it0 <= ap_const_lv5_1;
ap_reg_phiprechg_p_s_reg_136pp0_it0 <= ap_const_lv5_1;
ap_return <= merge_phi_fu_269_p4;
-- ap_sig_bdd_178 assign process. --
ap_sig_bdd_178_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3)
begin
ap_sig_bdd_178 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and not((tmp_7_fu_282_p3 = ap_const_lv1_0)));
end process;
-- ap_sig_bdd_183 assign process. --
ap_sig_bdd_183_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3)
begin
ap_sig_bdd_183 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and not((ap_const_lv1_0 = tmp_8_fu_290_p3)));
end process;
-- ap_sig_bdd_189 assign process. --
ap_sig_bdd_189_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3)
begin
ap_sig_bdd_189 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and not((ap_const_lv1_0 = tmp_9_fu_298_p3)));
end process;
-- ap_sig_bdd_196 assign process. --
ap_sig_bdd_196_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3)
begin
ap_sig_bdd_196 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and not((ap_const_lv1_0 = tmp_10_fu_306_p3)));
end process;
-- ap_sig_bdd_204 assign process. --
ap_sig_bdd_204_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3)
begin
ap_sig_bdd_204 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and not((ap_const_lv1_0 = tmp_11_fu_314_p3)));
end process;
-- ap_sig_bdd_213 assign process. --
ap_sig_bdd_213_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3)
begin
ap_sig_bdd_213 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and not((ap_const_lv1_0 = tmp_12_fu_322_p3)));
end process;
-- ap_sig_bdd_223 assign process. --
ap_sig_bdd_223_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3)
begin
ap_sig_bdd_223 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and not((ap_const_lv1_0 = tmp_13_fu_330_p3)));
end process;
-- ap_sig_bdd_234 assign process. --
ap_sig_bdd_234_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3)
begin
ap_sig_bdd_234 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and not((ap_const_lv1_0 = tmp_14_fu_338_p3)));
end process;
-- ap_sig_bdd_246 assign process. --
ap_sig_bdd_246_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3)
begin
ap_sig_bdd_246 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and not((ap_const_lv1_0 = tmp_15_fu_346_p3)));
end process;
-- ap_sig_bdd_259 assign process. --
ap_sig_bdd_259_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3)
begin
ap_sig_bdd_259 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and not((ap_const_lv1_0 = tmp_16_fu_354_p3)));
end process;
-- ap_sig_bdd_273 assign process. --
ap_sig_bdd_273_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3)
begin
ap_sig_bdd_273 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and not((ap_const_lv1_0 = tmp_17_fu_362_p3)));
end process;
-- ap_sig_bdd_288 assign process. --
ap_sig_bdd_288_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3)
begin
ap_sig_bdd_288 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and not((ap_const_lv1_0 = tmp_18_fu_370_p3)));
end process;
-- ap_sig_bdd_304 assign process. --
ap_sig_bdd_304_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3)
begin
ap_sig_bdd_304 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and not((ap_const_lv1_0 = tmp_19_fu_378_p3)));
end process;
-- ap_sig_bdd_321 assign process. --
ap_sig_bdd_321_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3)
begin
ap_sig_bdd_321 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and not((ap_const_lv1_0 = tmp_20_fu_386_p3)));
end process;
-- ap_sig_bdd_339 assign process. --
ap_sig_bdd_339_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3)
begin
ap_sig_bdd_339 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and not((ap_const_lv1_0 = tmp_21_fu_394_p3)));
end process;
-- ap_sig_bdd_358 assign process. --
ap_sig_bdd_358_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3)
begin
ap_sig_bdd_358 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and not((ap_const_lv1_0 = tmp_22_fu_402_p3)));
end process;
-- ap_sig_bdd_378 assign process. --
ap_sig_bdd_378_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3)
begin
ap_sig_bdd_378 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and not((ap_const_lv1_0 = tmp_23_fu_410_p3)));
end process;
-- ap_sig_bdd_399 assign process. --
ap_sig_bdd_399_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3)
begin
ap_sig_bdd_399 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and not((ap_const_lv1_0 = tmp_24_fu_418_p3)));
end process;
-- ap_sig_bdd_421 assign process. --
ap_sig_bdd_421_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3)
begin
ap_sig_bdd_421 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and not((ap_const_lv1_0 = tmp_25_fu_426_p3)));
end process;
-- ap_sig_bdd_444 assign process. --
ap_sig_bdd_444_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3)
begin
ap_sig_bdd_444 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and not((ap_const_lv1_0 = tmp_26_fu_434_p3)));
end process;
-- ap_sig_bdd_468 assign process. --
ap_sig_bdd_468_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3)
begin
ap_sig_bdd_468 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and not((ap_const_lv1_0 = tmp_27_fu_442_p3)));
end process;
-- ap_sig_bdd_493 assign process. --
ap_sig_bdd_493_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3)
begin
ap_sig_bdd_493 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and not((ap_const_lv1_0 = tmp_28_fu_450_p3)));
end process;
-- ap_sig_bdd_519 assign process. --
ap_sig_bdd_519_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3)
begin
ap_sig_bdd_519 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and not((ap_const_lv1_0 = tmp_29_fu_458_p3)));
end process;
-- ap_sig_bdd_546 assign process. --
ap_sig_bdd_546_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3, tmp_30_fu_466_p3)
begin
ap_sig_bdd_546 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and not((ap_const_lv1_0 = tmp_30_fu_466_p3)));
end process;
-- ap_sig_bdd_574 assign process. --
ap_sig_bdd_574_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3, tmp_30_fu_466_p3, tmp_31_fu_474_p3)
begin
ap_sig_bdd_574 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and not((ap_const_lv1_0 = tmp_31_fu_474_p3)));
end process;
-- ap_sig_bdd_603 assign process. --
ap_sig_bdd_603_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3, tmp_30_fu_466_p3, tmp_31_fu_474_p3, tmp_32_fu_482_p3)
begin
ap_sig_bdd_603 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and not((ap_const_lv1_0 = tmp_32_fu_482_p3)));
end process;
-- ap_sig_bdd_633 assign process. --
ap_sig_bdd_633_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3, tmp_30_fu_466_p3, tmp_31_fu_474_p3, tmp_32_fu_482_p3, tmp_33_fu_490_p3)
begin
ap_sig_bdd_633 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3) and not((ap_const_lv1_0 = tmp_33_fu_490_p3)));
end process;
-- ap_sig_bdd_664 assign process. --
ap_sig_bdd_664_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3, tmp_30_fu_466_p3, tmp_31_fu_474_p3, tmp_32_fu_482_p3, tmp_33_fu_490_p3, tmp_34_fu_498_p3)
begin
ap_sig_bdd_664 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3) and (ap_const_lv1_0 = tmp_33_fu_490_p3) and not((ap_const_lv1_0 = tmp_34_fu_498_p3)));
end process;
-- ap_sig_bdd_696 assign process. --
ap_sig_bdd_696_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3, tmp_30_fu_466_p3, tmp_31_fu_474_p3, tmp_32_fu_482_p3, tmp_33_fu_490_p3, tmp_34_fu_498_p3, tmp_35_fu_506_p3)
begin
ap_sig_bdd_696 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3) and (ap_const_lv1_0 = tmp_33_fu_490_p3) and (ap_const_lv1_0 = tmp_34_fu_498_p3) and not((ap_const_lv1_0 = tmp_35_fu_506_p3)));
end process;
-- ap_sig_bdd_730 assign process. --
ap_sig_bdd_730_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3, tmp_30_fu_466_p3, tmp_31_fu_474_p3, tmp_32_fu_482_p3, tmp_33_fu_490_p3, tmp_34_fu_498_p3, tmp_35_fu_506_p3, tmp_36_fu_514_p3)
begin
ap_sig_bdd_730 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3) and (ap_const_lv1_0 = tmp_33_fu_490_p3) and (ap_const_lv1_0 = tmp_34_fu_498_p3) and (ap_const_lv1_0 = tmp_35_fu_506_p3) and not((ap_const_lv1_0 = tmp_36_fu_514_p3)));
end process;
-- ap_sig_bdd_764 assign process. --
ap_sig_bdd_764_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3, tmp_30_fu_466_p3, tmp_31_fu_474_p3, tmp_32_fu_482_p3, tmp_33_fu_490_p3, tmp_34_fu_498_p3, tmp_35_fu_506_p3, tmp_36_fu_514_p3)
begin
ap_sig_bdd_764 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3) and (ap_const_lv1_0 = tmp_33_fu_490_p3) and (ap_const_lv1_0 = tmp_34_fu_498_p3) and (ap_const_lv1_0 = tmp_35_fu_506_p3) and (ap_const_lv1_0 = tmp_36_fu_514_p3));
end process;
-- merge_phi_fu_269_p4 assign process. --
merge_phi_fu_269_p4_assign_proc : process(tmp_reg_522, tmp_7_reg_526, tmp_8_reg_530, tmp_9_reg_534, tmp_10_reg_538, tmp_11_reg_542, tmp_12_reg_546, tmp_13_reg_550, tmp_14_reg_554, tmp_15_reg_558, tmp_16_reg_562, tmp_17_reg_566, tmp_18_reg_570, tmp_19_reg_574, tmp_20_reg_578, tmp_21_reg_582, tmp_22_reg_586, tmp_23_reg_590, tmp_24_reg_594, tmp_25_reg_598, tmp_26_reg_602, tmp_27_reg_606, tmp_28_reg_610, tmp_29_reg_614, tmp_30_reg_618, tmp_31_reg_622, tmp_32_reg_626, tmp_33_reg_630, tmp_34_reg_634, tmp_35_reg_638, tmp_36_reg_642, ap_reg_phiprechg_p_s_reg_136pp0_it1, ap_reg_phiprechg_merge_reg_265pp0_it1)
begin
if ((not((tmp_reg_522 = ap_const_lv1_0)) or not((tmp_7_reg_526 = ap_const_lv1_0)) or not((ap_const_lv1_0 = tmp_8_reg_530)) or not((ap_const_lv1_0 = tmp_9_reg_534)) or not((ap_const_lv1_0 = tmp_10_reg_538)) or not((ap_const_lv1_0 = tmp_11_reg_542)) or not((ap_const_lv1_0 = tmp_12_reg_546)) or not((ap_const_lv1_0 = tmp_13_reg_550)) or not((ap_const_lv1_0 = tmp_14_reg_554)) or not((ap_const_lv1_0 = tmp_15_reg_558)) or not((ap_const_lv1_0 = tmp_16_reg_562)) or not((ap_const_lv1_0 = tmp_17_reg_566)) or not((ap_const_lv1_0 = tmp_18_reg_570)) or not((ap_const_lv1_0 = tmp_19_reg_574)) or not((ap_const_lv1_0 = tmp_20_reg_578)) or not((ap_const_lv1_0 = tmp_21_reg_582)) or not((ap_const_lv1_0 = tmp_22_reg_586)) or not((ap_const_lv1_0 = tmp_23_reg_590)) or not((ap_const_lv1_0 = tmp_24_reg_594)) or not((ap_const_lv1_0 = tmp_25_reg_598)) or not((ap_const_lv1_0 = tmp_26_reg_602)) or not((ap_const_lv1_0 = tmp_27_reg_606)) or not((ap_const_lv1_0 = tmp_28_reg_610)) or not((ap_const_lv1_0 = tmp_29_reg_614)) or not((ap_const_lv1_0 = tmp_30_reg_618)) or not((ap_const_lv1_0 = tmp_31_reg_622)) or not((ap_const_lv1_0 = tmp_32_reg_626)) or not((ap_const_lv1_0 = tmp_33_reg_630)) or not((ap_const_lv1_0 = tmp_34_reg_634)) or not((ap_const_lv1_0 = tmp_35_reg_638)) or not((ap_const_lv1_0 = tmp_36_reg_642)))) then
merge_phi_fu_269_p4 <= ap_reg_phiprechg_p_s_reg_136pp0_it1;
else
merge_phi_fu_269_p4 <= ap_reg_phiprechg_merge_reg_265pp0_it1;
end if;
end process;
tmp_10_fu_306_p3 <= bus_r(4 downto 4);
tmp_11_fu_314_p3 <= bus_r(5 downto 5);
tmp_12_fu_322_p3 <= bus_r(6 downto 6);
tmp_13_fu_330_p3 <= bus_r(7 downto 7);
tmp_14_fu_338_p3 <= bus_r(8 downto 8);
tmp_15_fu_346_p3 <= bus_r(9 downto 9);
tmp_16_fu_354_p3 <= bus_r(10 downto 10);
tmp_17_fu_362_p3 <= bus_r(11 downto 11);
tmp_18_fu_370_p3 <= bus_r(12 downto 12);
tmp_19_fu_378_p3 <= bus_r(13 downto 13);
tmp_20_fu_386_p3 <= bus_r(14 downto 14);
tmp_21_fu_394_p3 <= bus_r(15 downto 15);
tmp_22_fu_402_p3 <= bus_r(16 downto 16);
tmp_23_fu_410_p3 <= bus_r(17 downto 17);
tmp_24_fu_418_p3 <= bus_r(18 downto 18);
tmp_25_fu_426_p3 <= bus_r(19 downto 19);
tmp_26_fu_434_p3 <= bus_r(20 downto 20);
tmp_27_fu_442_p3 <= bus_r(21 downto 21);
tmp_28_fu_450_p3 <= bus_r(22 downto 22);
tmp_29_fu_458_p3 <= bus_r(23 downto 23);
tmp_30_fu_466_p3 <= bus_r(24 downto 24);
tmp_31_fu_474_p3 <= bus_r(25 downto 25);
tmp_32_fu_482_p3 <= bus_r(26 downto 26);
tmp_33_fu_490_p3 <= bus_r(27 downto 27);
tmp_34_fu_498_p3 <= bus_r(28 downto 28);
tmp_35_fu_506_p3 <= bus_r(29 downto 29);
tmp_36_fu_514_p3 <= bus_r(30 downto 30);
tmp_7_fu_282_p3 <= bus_r(1 downto 1);
tmp_8_fu_290_p3 <= bus_r(2 downto 2);
tmp_9_fu_298_p3 <= bus_r(3 downto 3);
tmp_fu_278_p1 <= bus_r(1 - 1 downto 0);
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity p_bsf32_hw is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
bus_r : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (4 downto 0);
ap_ce : IN STD_LOGIC );
end;
architecture behav of p_bsf32_hw is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv5_1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_const_lv5_2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_const_lv5_3 : STD_LOGIC_VECTOR (4 downto 0) := "00011";
constant ap_const_lv5_4 : STD_LOGIC_VECTOR (4 downto 0) := "00100";
constant ap_const_lv5_5 : STD_LOGIC_VECTOR (4 downto 0) := "00101";
constant ap_const_lv5_6 : STD_LOGIC_VECTOR (4 downto 0) := "00110";
constant ap_const_lv5_7 : STD_LOGIC_VECTOR (4 downto 0) := "00111";
constant ap_const_lv5_8 : STD_LOGIC_VECTOR (4 downto 0) := "01000";
constant ap_const_lv5_9 : STD_LOGIC_VECTOR (4 downto 0) := "01001";
constant ap_const_lv5_A : STD_LOGIC_VECTOR (4 downto 0) := "01010";
constant ap_const_lv5_B : STD_LOGIC_VECTOR (4 downto 0) := "01011";
constant ap_const_lv5_C : STD_LOGIC_VECTOR (4 downto 0) := "01100";
constant ap_const_lv5_D : STD_LOGIC_VECTOR (4 downto 0) := "01101";
constant ap_const_lv5_E : STD_LOGIC_VECTOR (4 downto 0) := "01110";
constant ap_const_lv5_F : STD_LOGIC_VECTOR (4 downto 0) := "01111";
constant ap_const_lv5_10 : STD_LOGIC_VECTOR (4 downto 0) := "10000";
constant ap_const_lv5_11 : STD_LOGIC_VECTOR (4 downto 0) := "10001";
constant ap_const_lv5_12 : STD_LOGIC_VECTOR (4 downto 0) := "10010";
constant ap_const_lv5_13 : STD_LOGIC_VECTOR (4 downto 0) := "10011";
constant ap_const_lv5_14 : STD_LOGIC_VECTOR (4 downto 0) := "10100";
constant ap_const_lv5_15 : STD_LOGIC_VECTOR (4 downto 0) := "10101";
constant ap_const_lv5_16 : STD_LOGIC_VECTOR (4 downto 0) := "10110";
constant ap_const_lv5_17 : STD_LOGIC_VECTOR (4 downto 0) := "10111";
constant ap_const_lv5_18 : STD_LOGIC_VECTOR (4 downto 0) := "11000";
constant ap_const_lv5_19 : STD_LOGIC_VECTOR (4 downto 0) := "11001";
constant ap_const_lv5_1A : STD_LOGIC_VECTOR (4 downto 0) := "11010";
constant ap_const_lv5_1B : STD_LOGIC_VECTOR (4 downto 0) := "11011";
constant ap_const_lv5_1C : STD_LOGIC_VECTOR (4 downto 0) := "11100";
constant ap_const_lv5_1D : STD_LOGIC_VECTOR (4 downto 0) := "11101";
constant ap_const_lv5_1E : STD_LOGIC_VECTOR (4 downto 0) := "11110";
constant ap_const_lv5_1F : STD_LOGIC_VECTOR (4 downto 0) := "11111";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001";
constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010";
constant ap_const_lv32_1B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011011";
constant ap_const_lv32_1C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011100";
constant ap_const_lv32_1D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011101";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_true : BOOLEAN := true;
signal tmp_fu_278_p1 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_reg_522 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_7_fu_282_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_7_reg_526 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_fu_290_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_reg_530 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_9_fu_298_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_9_reg_534 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_10_fu_306_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_10_reg_538 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_fu_314_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_reg_542 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_12_fu_322_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_12_reg_546 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_13_fu_330_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_13_reg_550 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_14_fu_338_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_14_reg_554 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_15_fu_346_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_15_reg_558 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_16_fu_354_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_16_reg_562 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_17_fu_362_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_17_reg_566 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_18_fu_370_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_18_reg_570 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_19_fu_378_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_19_reg_574 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_20_fu_386_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_20_reg_578 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_21_fu_394_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_21_reg_582 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_22_fu_402_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_22_reg_586 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_23_fu_410_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_23_reg_590 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_24_fu_418_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_24_reg_594 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_25_fu_426_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_25_reg_598 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_26_fu_434_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_26_reg_602 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_27_fu_442_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_27_reg_606 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_28_fu_450_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_28_reg_610 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_29_fu_458_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_29_reg_614 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_30_fu_466_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_30_reg_618 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_fu_474_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_622 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_32_fu_482_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_32_reg_626 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_33_fu_490_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_33_reg_630 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_34_fu_498_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_34_reg_634 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_35_fu_506_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_35_reg_638 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_36_fu_514_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_36_reg_642 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_phiprechg_p_s_reg_136pp0_it0 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_phiprechg_p_s_reg_136pp0_it1 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_phiprechg_merge_reg_265pp0_it0 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_phiprechg_merge_reg_265pp0_it1 : STD_LOGIC_VECTOR (4 downto 0);
signal merge_phi_fu_269_p4 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_sig_bdd_764 : BOOLEAN;
signal ap_sig_bdd_178 : BOOLEAN;
signal ap_sig_bdd_183 : BOOLEAN;
signal ap_sig_bdd_189 : BOOLEAN;
signal ap_sig_bdd_196 : BOOLEAN;
signal ap_sig_bdd_204 : BOOLEAN;
signal ap_sig_bdd_213 : BOOLEAN;
signal ap_sig_bdd_223 : BOOLEAN;
signal ap_sig_bdd_234 : BOOLEAN;
signal ap_sig_bdd_246 : BOOLEAN;
signal ap_sig_bdd_259 : BOOLEAN;
signal ap_sig_bdd_273 : BOOLEAN;
signal ap_sig_bdd_288 : BOOLEAN;
signal ap_sig_bdd_304 : BOOLEAN;
signal ap_sig_bdd_321 : BOOLEAN;
signal ap_sig_bdd_339 : BOOLEAN;
signal ap_sig_bdd_358 : BOOLEAN;
signal ap_sig_bdd_378 : BOOLEAN;
signal ap_sig_bdd_399 : BOOLEAN;
signal ap_sig_bdd_421 : BOOLEAN;
signal ap_sig_bdd_444 : BOOLEAN;
signal ap_sig_bdd_468 : BOOLEAN;
signal ap_sig_bdd_493 : BOOLEAN;
signal ap_sig_bdd_519 : BOOLEAN;
signal ap_sig_bdd_546 : BOOLEAN;
signal ap_sig_bdd_574 : BOOLEAN;
signal ap_sig_bdd_603 : BOOLEAN;
signal ap_sig_bdd_633 : BOOLEAN;
signal ap_sig_bdd_664 : BOOLEAN;
signal ap_sig_bdd_696 : BOOLEAN;
signal ap_sig_bdd_730 : BOOLEAN;
begin
-- ap_reg_phiprechg_merge_reg_265pp0_it1 assign process. --
ap_reg_phiprechg_merge_reg_265pp0_it1_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_ce)) then
if (ap_sig_bdd_764) then
ap_reg_phiprechg_merge_reg_265pp0_it1(1) <= '1';
ap_reg_phiprechg_merge_reg_265pp0_it1(2) <= '1';
ap_reg_phiprechg_merge_reg_265pp0_it1(3) <= '1';
ap_reg_phiprechg_merge_reg_265pp0_it1(4) <= '1';
elsif ((ap_true = ap_true)) then
ap_reg_phiprechg_merge_reg_265pp0_it1(1) <= ap_reg_phiprechg_merge_reg_265pp0_it0(1);
ap_reg_phiprechg_merge_reg_265pp0_it1(2) <= ap_reg_phiprechg_merge_reg_265pp0_it0(2);
ap_reg_phiprechg_merge_reg_265pp0_it1(3) <= ap_reg_phiprechg_merge_reg_265pp0_it0(3);
ap_reg_phiprechg_merge_reg_265pp0_it1(4) <= ap_reg_phiprechg_merge_reg_265pp0_it0(4);
end if;
end if;
end if;
end process;
-- ap_reg_phiprechg_p_s_reg_136pp0_it1 assign process. --
ap_reg_phiprechg_p_s_reg_136pp0_it1_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_ce)) then
if (ap_sig_bdd_730) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1E;
elsif (ap_sig_bdd_696) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1D;
elsif (ap_sig_bdd_664) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1C;
elsif (ap_sig_bdd_633) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1B;
elsif (ap_sig_bdd_603) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1A;
elsif (ap_sig_bdd_574) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_19;
elsif (ap_sig_bdd_546) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_18;
elsif (ap_sig_bdd_519) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_17;
elsif (ap_sig_bdd_493) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_16;
elsif (ap_sig_bdd_468) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_15;
elsif (ap_sig_bdd_444) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_14;
elsif (ap_sig_bdd_421) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_13;
elsif (ap_sig_bdd_399) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_12;
elsif (ap_sig_bdd_378) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_11;
elsif (ap_sig_bdd_358) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_10;
elsif (ap_sig_bdd_339) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_F;
elsif (ap_sig_bdd_321) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_E;
elsif (ap_sig_bdd_304) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_D;
elsif (ap_sig_bdd_288) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_C;
elsif (ap_sig_bdd_273) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_B;
elsif (ap_sig_bdd_259) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_A;
elsif (ap_sig_bdd_246) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_9;
elsif (ap_sig_bdd_234) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_8;
elsif (ap_sig_bdd_223) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_7;
elsif (ap_sig_bdd_213) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_6;
elsif (ap_sig_bdd_204) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_5;
elsif (ap_sig_bdd_196) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_4;
elsif (ap_sig_bdd_189) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_3;
elsif (ap_sig_bdd_183) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_2;
elsif (ap_sig_bdd_178) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1;
elsif (not((tmp_fu_278_p1 = ap_const_lv1_0))) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_0;
elsif ((ap_true = ap_true)) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_reg_phiprechg_p_s_reg_136pp0_it0;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3))) then
tmp_10_reg_538 <= bus_r(4 downto 4);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3))) then
tmp_11_reg_542 <= bus_r(5 downto 5);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3))) then
tmp_12_reg_546 <= bus_r(6 downto 6);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3))) then
tmp_13_reg_550 <= bus_r(7 downto 7);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3))) then
tmp_14_reg_554 <= bus_r(8 downto 8);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3))) then
tmp_15_reg_558 <= bus_r(9 downto 9);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3))) then
tmp_16_reg_562 <= bus_r(10 downto 10);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3))) then
tmp_17_reg_566 <= bus_r(11 downto 11);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3))) then
tmp_18_reg_570 <= bus_r(12 downto 12);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3))) then
tmp_19_reg_574 <= bus_r(13 downto 13);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3))) then
tmp_20_reg_578 <= bus_r(14 downto 14);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3))) then
tmp_21_reg_582 <= bus_r(15 downto 15);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3))) then
tmp_22_reg_586 <= bus_r(16 downto 16);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3))) then
tmp_23_reg_590 <= bus_r(17 downto 17);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3))) then
tmp_24_reg_594 <= bus_r(18 downto 18);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3))) then
tmp_25_reg_598 <= bus_r(19 downto 19);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3))) then
tmp_26_reg_602 <= bus_r(20 downto 20);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3))) then
tmp_27_reg_606 <= bus_r(21 downto 21);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3))) then
tmp_28_reg_610 <= bus_r(22 downto 22);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3))) then
tmp_29_reg_614 <= bus_r(23 downto 23);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3))) then
tmp_30_reg_618 <= bus_r(24 downto 24);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3))) then
tmp_31_reg_622 <= bus_r(25 downto 25);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3))) then
tmp_32_reg_626 <= bus_r(26 downto 26);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3))) then
tmp_33_reg_630 <= bus_r(27 downto 27);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3) and (ap_const_lv1_0 = tmp_33_fu_490_p3))) then
tmp_34_reg_634 <= bus_r(28 downto 28);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3) and (ap_const_lv1_0 = tmp_33_fu_490_p3) and (ap_const_lv1_0 = tmp_34_fu_498_p3))) then
tmp_35_reg_638 <= bus_r(29 downto 29);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3) and (ap_const_lv1_0 = tmp_33_fu_490_p3) and (ap_const_lv1_0 = tmp_34_fu_498_p3) and (ap_const_lv1_0 = tmp_35_fu_506_p3))) then
tmp_36_reg_642 <= bus_r(30 downto 30);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0))) then
tmp_7_reg_526 <= bus_r(1 downto 1);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0))) then
tmp_8_reg_530 <= bus_r(2 downto 2);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3))) then
tmp_9_reg_534 <= bus_r(3 downto 3);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_ce)) then
tmp_reg_522 <= tmp_fu_278_p1;
end if;
end if;
end process;
ap_reg_phiprechg_merge_reg_265pp0_it1(0) <= '1';
ap_reg_phiprechg_merge_reg_265pp0_it0 <= ap_const_lv5_1;
ap_reg_phiprechg_p_s_reg_136pp0_it0 <= ap_const_lv5_1;
ap_return <= merge_phi_fu_269_p4;
-- ap_sig_bdd_178 assign process. --
ap_sig_bdd_178_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3)
begin
ap_sig_bdd_178 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and not((tmp_7_fu_282_p3 = ap_const_lv1_0)));
end process;
-- ap_sig_bdd_183 assign process. --
ap_sig_bdd_183_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3)
begin
ap_sig_bdd_183 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and not((ap_const_lv1_0 = tmp_8_fu_290_p3)));
end process;
-- ap_sig_bdd_189 assign process. --
ap_sig_bdd_189_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3)
begin
ap_sig_bdd_189 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and not((ap_const_lv1_0 = tmp_9_fu_298_p3)));
end process;
-- ap_sig_bdd_196 assign process. --
ap_sig_bdd_196_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3)
begin
ap_sig_bdd_196 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and not((ap_const_lv1_0 = tmp_10_fu_306_p3)));
end process;
-- ap_sig_bdd_204 assign process. --
ap_sig_bdd_204_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3)
begin
ap_sig_bdd_204 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and not((ap_const_lv1_0 = tmp_11_fu_314_p3)));
end process;
-- ap_sig_bdd_213 assign process. --
ap_sig_bdd_213_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3)
begin
ap_sig_bdd_213 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and not((ap_const_lv1_0 = tmp_12_fu_322_p3)));
end process;
-- ap_sig_bdd_223 assign process. --
ap_sig_bdd_223_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3)
begin
ap_sig_bdd_223 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and not((ap_const_lv1_0 = tmp_13_fu_330_p3)));
end process;
-- ap_sig_bdd_234 assign process. --
ap_sig_bdd_234_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3)
begin
ap_sig_bdd_234 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and not((ap_const_lv1_0 = tmp_14_fu_338_p3)));
end process;
-- ap_sig_bdd_246 assign process. --
ap_sig_bdd_246_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3)
begin
ap_sig_bdd_246 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and not((ap_const_lv1_0 = tmp_15_fu_346_p3)));
end process;
-- ap_sig_bdd_259 assign process. --
ap_sig_bdd_259_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3)
begin
ap_sig_bdd_259 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and not((ap_const_lv1_0 = tmp_16_fu_354_p3)));
end process;
-- ap_sig_bdd_273 assign process. --
ap_sig_bdd_273_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3)
begin
ap_sig_bdd_273 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and not((ap_const_lv1_0 = tmp_17_fu_362_p3)));
end process;
-- ap_sig_bdd_288 assign process. --
ap_sig_bdd_288_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3)
begin
ap_sig_bdd_288 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and not((ap_const_lv1_0 = tmp_18_fu_370_p3)));
end process;
-- ap_sig_bdd_304 assign process. --
ap_sig_bdd_304_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3)
begin
ap_sig_bdd_304 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and not((ap_const_lv1_0 = tmp_19_fu_378_p3)));
end process;
-- ap_sig_bdd_321 assign process. --
ap_sig_bdd_321_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3)
begin
ap_sig_bdd_321 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and not((ap_const_lv1_0 = tmp_20_fu_386_p3)));
end process;
-- ap_sig_bdd_339 assign process. --
ap_sig_bdd_339_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3)
begin
ap_sig_bdd_339 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and not((ap_const_lv1_0 = tmp_21_fu_394_p3)));
end process;
-- ap_sig_bdd_358 assign process. --
ap_sig_bdd_358_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3)
begin
ap_sig_bdd_358 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and not((ap_const_lv1_0 = tmp_22_fu_402_p3)));
end process;
-- ap_sig_bdd_378 assign process. --
ap_sig_bdd_378_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3)
begin
ap_sig_bdd_378 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and not((ap_const_lv1_0 = tmp_23_fu_410_p3)));
end process;
-- ap_sig_bdd_399 assign process. --
ap_sig_bdd_399_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3)
begin
ap_sig_bdd_399 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and not((ap_const_lv1_0 = tmp_24_fu_418_p3)));
end process;
-- ap_sig_bdd_421 assign process. --
ap_sig_bdd_421_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3)
begin
ap_sig_bdd_421 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and not((ap_const_lv1_0 = tmp_25_fu_426_p3)));
end process;
-- ap_sig_bdd_444 assign process. --
ap_sig_bdd_444_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3)
begin
ap_sig_bdd_444 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and not((ap_const_lv1_0 = tmp_26_fu_434_p3)));
end process;
-- ap_sig_bdd_468 assign process. --
ap_sig_bdd_468_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3)
begin
ap_sig_bdd_468 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and not((ap_const_lv1_0 = tmp_27_fu_442_p3)));
end process;
-- ap_sig_bdd_493 assign process. --
ap_sig_bdd_493_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3)
begin
ap_sig_bdd_493 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and not((ap_const_lv1_0 = tmp_28_fu_450_p3)));
end process;
-- ap_sig_bdd_519 assign process. --
ap_sig_bdd_519_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3)
begin
ap_sig_bdd_519 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and not((ap_const_lv1_0 = tmp_29_fu_458_p3)));
end process;
-- ap_sig_bdd_546 assign process. --
ap_sig_bdd_546_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3, tmp_30_fu_466_p3)
begin
ap_sig_bdd_546 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and not((ap_const_lv1_0 = tmp_30_fu_466_p3)));
end process;
-- ap_sig_bdd_574 assign process. --
ap_sig_bdd_574_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3, tmp_30_fu_466_p3, tmp_31_fu_474_p3)
begin
ap_sig_bdd_574 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and not((ap_const_lv1_0 = tmp_31_fu_474_p3)));
end process;
-- ap_sig_bdd_603 assign process. --
ap_sig_bdd_603_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3, tmp_30_fu_466_p3, tmp_31_fu_474_p3, tmp_32_fu_482_p3)
begin
ap_sig_bdd_603 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and not((ap_const_lv1_0 = tmp_32_fu_482_p3)));
end process;
-- ap_sig_bdd_633 assign process. --
ap_sig_bdd_633_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3, tmp_30_fu_466_p3, tmp_31_fu_474_p3, tmp_32_fu_482_p3, tmp_33_fu_490_p3)
begin
ap_sig_bdd_633 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3) and not((ap_const_lv1_0 = tmp_33_fu_490_p3)));
end process;
-- ap_sig_bdd_664 assign process. --
ap_sig_bdd_664_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3, tmp_30_fu_466_p3, tmp_31_fu_474_p3, tmp_32_fu_482_p3, tmp_33_fu_490_p3, tmp_34_fu_498_p3)
begin
ap_sig_bdd_664 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3) and (ap_const_lv1_0 = tmp_33_fu_490_p3) and not((ap_const_lv1_0 = tmp_34_fu_498_p3)));
end process;
-- ap_sig_bdd_696 assign process. --
ap_sig_bdd_696_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3, tmp_30_fu_466_p3, tmp_31_fu_474_p3, tmp_32_fu_482_p3, tmp_33_fu_490_p3, tmp_34_fu_498_p3, tmp_35_fu_506_p3)
begin
ap_sig_bdd_696 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3) and (ap_const_lv1_0 = tmp_33_fu_490_p3) and (ap_const_lv1_0 = tmp_34_fu_498_p3) and not((ap_const_lv1_0 = tmp_35_fu_506_p3)));
end process;
-- ap_sig_bdd_730 assign process. --
ap_sig_bdd_730_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3, tmp_30_fu_466_p3, tmp_31_fu_474_p3, tmp_32_fu_482_p3, tmp_33_fu_490_p3, tmp_34_fu_498_p3, tmp_35_fu_506_p3, tmp_36_fu_514_p3)
begin
ap_sig_bdd_730 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3) and (ap_const_lv1_0 = tmp_33_fu_490_p3) and (ap_const_lv1_0 = tmp_34_fu_498_p3) and (ap_const_lv1_0 = tmp_35_fu_506_p3) and not((ap_const_lv1_0 = tmp_36_fu_514_p3)));
end process;
-- ap_sig_bdd_764 assign process. --
ap_sig_bdd_764_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3, tmp_30_fu_466_p3, tmp_31_fu_474_p3, tmp_32_fu_482_p3, tmp_33_fu_490_p3, tmp_34_fu_498_p3, tmp_35_fu_506_p3, tmp_36_fu_514_p3)
begin
ap_sig_bdd_764 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3) and (ap_const_lv1_0 = tmp_33_fu_490_p3) and (ap_const_lv1_0 = tmp_34_fu_498_p3) and (ap_const_lv1_0 = tmp_35_fu_506_p3) and (ap_const_lv1_0 = tmp_36_fu_514_p3));
end process;
-- merge_phi_fu_269_p4 assign process. --
merge_phi_fu_269_p4_assign_proc : process(tmp_reg_522, tmp_7_reg_526, tmp_8_reg_530, tmp_9_reg_534, tmp_10_reg_538, tmp_11_reg_542, tmp_12_reg_546, tmp_13_reg_550, tmp_14_reg_554, tmp_15_reg_558, tmp_16_reg_562, tmp_17_reg_566, tmp_18_reg_570, tmp_19_reg_574, tmp_20_reg_578, tmp_21_reg_582, tmp_22_reg_586, tmp_23_reg_590, tmp_24_reg_594, tmp_25_reg_598, tmp_26_reg_602, tmp_27_reg_606, tmp_28_reg_610, tmp_29_reg_614, tmp_30_reg_618, tmp_31_reg_622, tmp_32_reg_626, tmp_33_reg_630, tmp_34_reg_634, tmp_35_reg_638, tmp_36_reg_642, ap_reg_phiprechg_p_s_reg_136pp0_it1, ap_reg_phiprechg_merge_reg_265pp0_it1)
begin
if ((not((tmp_reg_522 = ap_const_lv1_0)) or not((tmp_7_reg_526 = ap_const_lv1_0)) or not((ap_const_lv1_0 = tmp_8_reg_530)) or not((ap_const_lv1_0 = tmp_9_reg_534)) or not((ap_const_lv1_0 = tmp_10_reg_538)) or not((ap_const_lv1_0 = tmp_11_reg_542)) or not((ap_const_lv1_0 = tmp_12_reg_546)) or not((ap_const_lv1_0 = tmp_13_reg_550)) or not((ap_const_lv1_0 = tmp_14_reg_554)) or not((ap_const_lv1_0 = tmp_15_reg_558)) or not((ap_const_lv1_0 = tmp_16_reg_562)) or not((ap_const_lv1_0 = tmp_17_reg_566)) or not((ap_const_lv1_0 = tmp_18_reg_570)) or not((ap_const_lv1_0 = tmp_19_reg_574)) or not((ap_const_lv1_0 = tmp_20_reg_578)) or not((ap_const_lv1_0 = tmp_21_reg_582)) or not((ap_const_lv1_0 = tmp_22_reg_586)) or not((ap_const_lv1_0 = tmp_23_reg_590)) or not((ap_const_lv1_0 = tmp_24_reg_594)) or not((ap_const_lv1_0 = tmp_25_reg_598)) or not((ap_const_lv1_0 = tmp_26_reg_602)) or not((ap_const_lv1_0 = tmp_27_reg_606)) or not((ap_const_lv1_0 = tmp_28_reg_610)) or not((ap_const_lv1_0 = tmp_29_reg_614)) or not((ap_const_lv1_0 = tmp_30_reg_618)) or not((ap_const_lv1_0 = tmp_31_reg_622)) or not((ap_const_lv1_0 = tmp_32_reg_626)) or not((ap_const_lv1_0 = tmp_33_reg_630)) or not((ap_const_lv1_0 = tmp_34_reg_634)) or not((ap_const_lv1_0 = tmp_35_reg_638)) or not((ap_const_lv1_0 = tmp_36_reg_642)))) then
merge_phi_fu_269_p4 <= ap_reg_phiprechg_p_s_reg_136pp0_it1;
else
merge_phi_fu_269_p4 <= ap_reg_phiprechg_merge_reg_265pp0_it1;
end if;
end process;
tmp_10_fu_306_p3 <= bus_r(4 downto 4);
tmp_11_fu_314_p3 <= bus_r(5 downto 5);
tmp_12_fu_322_p3 <= bus_r(6 downto 6);
tmp_13_fu_330_p3 <= bus_r(7 downto 7);
tmp_14_fu_338_p3 <= bus_r(8 downto 8);
tmp_15_fu_346_p3 <= bus_r(9 downto 9);
tmp_16_fu_354_p3 <= bus_r(10 downto 10);
tmp_17_fu_362_p3 <= bus_r(11 downto 11);
tmp_18_fu_370_p3 <= bus_r(12 downto 12);
tmp_19_fu_378_p3 <= bus_r(13 downto 13);
tmp_20_fu_386_p3 <= bus_r(14 downto 14);
tmp_21_fu_394_p3 <= bus_r(15 downto 15);
tmp_22_fu_402_p3 <= bus_r(16 downto 16);
tmp_23_fu_410_p3 <= bus_r(17 downto 17);
tmp_24_fu_418_p3 <= bus_r(18 downto 18);
tmp_25_fu_426_p3 <= bus_r(19 downto 19);
tmp_26_fu_434_p3 <= bus_r(20 downto 20);
tmp_27_fu_442_p3 <= bus_r(21 downto 21);
tmp_28_fu_450_p3 <= bus_r(22 downto 22);
tmp_29_fu_458_p3 <= bus_r(23 downto 23);
tmp_30_fu_466_p3 <= bus_r(24 downto 24);
tmp_31_fu_474_p3 <= bus_r(25 downto 25);
tmp_32_fu_482_p3 <= bus_r(26 downto 26);
tmp_33_fu_490_p3 <= bus_r(27 downto 27);
tmp_34_fu_498_p3 <= bus_r(28 downto 28);
tmp_35_fu_506_p3 <= bus_r(29 downto 29);
tmp_36_fu_514_p3 <= bus_r(30 downto 30);
tmp_7_fu_282_p3 <= bus_r(1 downto 1);
tmp_8_fu_290_p3 <= bus_r(2 downto 2);
tmp_9_fu_298_p3 <= bus_r(3 downto 3);
tmp_fu_278_p1 <= bus_r(1 - 1 downto 0);
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity p_bsf32_hw is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
bus_r : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (4 downto 0);
ap_ce : IN STD_LOGIC );
end;
architecture behav of p_bsf32_hw is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv5_1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_const_lv5_2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_const_lv5_3 : STD_LOGIC_VECTOR (4 downto 0) := "00011";
constant ap_const_lv5_4 : STD_LOGIC_VECTOR (4 downto 0) := "00100";
constant ap_const_lv5_5 : STD_LOGIC_VECTOR (4 downto 0) := "00101";
constant ap_const_lv5_6 : STD_LOGIC_VECTOR (4 downto 0) := "00110";
constant ap_const_lv5_7 : STD_LOGIC_VECTOR (4 downto 0) := "00111";
constant ap_const_lv5_8 : STD_LOGIC_VECTOR (4 downto 0) := "01000";
constant ap_const_lv5_9 : STD_LOGIC_VECTOR (4 downto 0) := "01001";
constant ap_const_lv5_A : STD_LOGIC_VECTOR (4 downto 0) := "01010";
constant ap_const_lv5_B : STD_LOGIC_VECTOR (4 downto 0) := "01011";
constant ap_const_lv5_C : STD_LOGIC_VECTOR (4 downto 0) := "01100";
constant ap_const_lv5_D : STD_LOGIC_VECTOR (4 downto 0) := "01101";
constant ap_const_lv5_E : STD_LOGIC_VECTOR (4 downto 0) := "01110";
constant ap_const_lv5_F : STD_LOGIC_VECTOR (4 downto 0) := "01111";
constant ap_const_lv5_10 : STD_LOGIC_VECTOR (4 downto 0) := "10000";
constant ap_const_lv5_11 : STD_LOGIC_VECTOR (4 downto 0) := "10001";
constant ap_const_lv5_12 : STD_LOGIC_VECTOR (4 downto 0) := "10010";
constant ap_const_lv5_13 : STD_LOGIC_VECTOR (4 downto 0) := "10011";
constant ap_const_lv5_14 : STD_LOGIC_VECTOR (4 downto 0) := "10100";
constant ap_const_lv5_15 : STD_LOGIC_VECTOR (4 downto 0) := "10101";
constant ap_const_lv5_16 : STD_LOGIC_VECTOR (4 downto 0) := "10110";
constant ap_const_lv5_17 : STD_LOGIC_VECTOR (4 downto 0) := "10111";
constant ap_const_lv5_18 : STD_LOGIC_VECTOR (4 downto 0) := "11000";
constant ap_const_lv5_19 : STD_LOGIC_VECTOR (4 downto 0) := "11001";
constant ap_const_lv5_1A : STD_LOGIC_VECTOR (4 downto 0) := "11010";
constant ap_const_lv5_1B : STD_LOGIC_VECTOR (4 downto 0) := "11011";
constant ap_const_lv5_1C : STD_LOGIC_VECTOR (4 downto 0) := "11100";
constant ap_const_lv5_1D : STD_LOGIC_VECTOR (4 downto 0) := "11101";
constant ap_const_lv5_1E : STD_LOGIC_VECTOR (4 downto 0) := "11110";
constant ap_const_lv5_1F : STD_LOGIC_VECTOR (4 downto 0) := "11111";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001";
constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010";
constant ap_const_lv32_1B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011011";
constant ap_const_lv32_1C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011100";
constant ap_const_lv32_1D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011101";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_true : BOOLEAN := true;
signal tmp_fu_278_p1 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_reg_522 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_7_fu_282_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_7_reg_526 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_fu_290_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_reg_530 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_9_fu_298_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_9_reg_534 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_10_fu_306_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_10_reg_538 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_fu_314_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_reg_542 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_12_fu_322_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_12_reg_546 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_13_fu_330_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_13_reg_550 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_14_fu_338_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_14_reg_554 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_15_fu_346_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_15_reg_558 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_16_fu_354_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_16_reg_562 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_17_fu_362_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_17_reg_566 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_18_fu_370_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_18_reg_570 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_19_fu_378_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_19_reg_574 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_20_fu_386_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_20_reg_578 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_21_fu_394_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_21_reg_582 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_22_fu_402_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_22_reg_586 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_23_fu_410_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_23_reg_590 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_24_fu_418_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_24_reg_594 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_25_fu_426_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_25_reg_598 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_26_fu_434_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_26_reg_602 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_27_fu_442_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_27_reg_606 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_28_fu_450_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_28_reg_610 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_29_fu_458_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_29_reg_614 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_30_fu_466_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_30_reg_618 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_fu_474_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_622 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_32_fu_482_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_32_reg_626 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_33_fu_490_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_33_reg_630 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_34_fu_498_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_34_reg_634 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_35_fu_506_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_35_reg_638 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_36_fu_514_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_36_reg_642 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_phiprechg_p_s_reg_136pp0_it0 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_phiprechg_p_s_reg_136pp0_it1 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_phiprechg_merge_reg_265pp0_it0 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_phiprechg_merge_reg_265pp0_it1 : STD_LOGIC_VECTOR (4 downto 0);
signal merge_phi_fu_269_p4 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_sig_bdd_764 : BOOLEAN;
signal ap_sig_bdd_178 : BOOLEAN;
signal ap_sig_bdd_183 : BOOLEAN;
signal ap_sig_bdd_189 : BOOLEAN;
signal ap_sig_bdd_196 : BOOLEAN;
signal ap_sig_bdd_204 : BOOLEAN;
signal ap_sig_bdd_213 : BOOLEAN;
signal ap_sig_bdd_223 : BOOLEAN;
signal ap_sig_bdd_234 : BOOLEAN;
signal ap_sig_bdd_246 : BOOLEAN;
signal ap_sig_bdd_259 : BOOLEAN;
signal ap_sig_bdd_273 : BOOLEAN;
signal ap_sig_bdd_288 : BOOLEAN;
signal ap_sig_bdd_304 : BOOLEAN;
signal ap_sig_bdd_321 : BOOLEAN;
signal ap_sig_bdd_339 : BOOLEAN;
signal ap_sig_bdd_358 : BOOLEAN;
signal ap_sig_bdd_378 : BOOLEAN;
signal ap_sig_bdd_399 : BOOLEAN;
signal ap_sig_bdd_421 : BOOLEAN;
signal ap_sig_bdd_444 : BOOLEAN;
signal ap_sig_bdd_468 : BOOLEAN;
signal ap_sig_bdd_493 : BOOLEAN;
signal ap_sig_bdd_519 : BOOLEAN;
signal ap_sig_bdd_546 : BOOLEAN;
signal ap_sig_bdd_574 : BOOLEAN;
signal ap_sig_bdd_603 : BOOLEAN;
signal ap_sig_bdd_633 : BOOLEAN;
signal ap_sig_bdd_664 : BOOLEAN;
signal ap_sig_bdd_696 : BOOLEAN;
signal ap_sig_bdd_730 : BOOLEAN;
begin
-- ap_reg_phiprechg_merge_reg_265pp0_it1 assign process. --
ap_reg_phiprechg_merge_reg_265pp0_it1_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_ce)) then
if (ap_sig_bdd_764) then
ap_reg_phiprechg_merge_reg_265pp0_it1(1) <= '1';
ap_reg_phiprechg_merge_reg_265pp0_it1(2) <= '1';
ap_reg_phiprechg_merge_reg_265pp0_it1(3) <= '1';
ap_reg_phiprechg_merge_reg_265pp0_it1(4) <= '1';
elsif ((ap_true = ap_true)) then
ap_reg_phiprechg_merge_reg_265pp0_it1(1) <= ap_reg_phiprechg_merge_reg_265pp0_it0(1);
ap_reg_phiprechg_merge_reg_265pp0_it1(2) <= ap_reg_phiprechg_merge_reg_265pp0_it0(2);
ap_reg_phiprechg_merge_reg_265pp0_it1(3) <= ap_reg_phiprechg_merge_reg_265pp0_it0(3);
ap_reg_phiprechg_merge_reg_265pp0_it1(4) <= ap_reg_phiprechg_merge_reg_265pp0_it0(4);
end if;
end if;
end if;
end process;
-- ap_reg_phiprechg_p_s_reg_136pp0_it1 assign process. --
ap_reg_phiprechg_p_s_reg_136pp0_it1_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_ce)) then
if (ap_sig_bdd_730) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1E;
elsif (ap_sig_bdd_696) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1D;
elsif (ap_sig_bdd_664) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1C;
elsif (ap_sig_bdd_633) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1B;
elsif (ap_sig_bdd_603) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1A;
elsif (ap_sig_bdd_574) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_19;
elsif (ap_sig_bdd_546) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_18;
elsif (ap_sig_bdd_519) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_17;
elsif (ap_sig_bdd_493) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_16;
elsif (ap_sig_bdd_468) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_15;
elsif (ap_sig_bdd_444) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_14;
elsif (ap_sig_bdd_421) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_13;
elsif (ap_sig_bdd_399) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_12;
elsif (ap_sig_bdd_378) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_11;
elsif (ap_sig_bdd_358) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_10;
elsif (ap_sig_bdd_339) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_F;
elsif (ap_sig_bdd_321) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_E;
elsif (ap_sig_bdd_304) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_D;
elsif (ap_sig_bdd_288) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_C;
elsif (ap_sig_bdd_273) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_B;
elsif (ap_sig_bdd_259) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_A;
elsif (ap_sig_bdd_246) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_9;
elsif (ap_sig_bdd_234) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_8;
elsif (ap_sig_bdd_223) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_7;
elsif (ap_sig_bdd_213) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_6;
elsif (ap_sig_bdd_204) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_5;
elsif (ap_sig_bdd_196) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_4;
elsif (ap_sig_bdd_189) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_3;
elsif (ap_sig_bdd_183) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_2;
elsif (ap_sig_bdd_178) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1;
elsif (not((tmp_fu_278_p1 = ap_const_lv1_0))) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_0;
elsif ((ap_true = ap_true)) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_reg_phiprechg_p_s_reg_136pp0_it0;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3))) then
tmp_10_reg_538 <= bus_r(4 downto 4);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3))) then
tmp_11_reg_542 <= bus_r(5 downto 5);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3))) then
tmp_12_reg_546 <= bus_r(6 downto 6);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3))) then
tmp_13_reg_550 <= bus_r(7 downto 7);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3))) then
tmp_14_reg_554 <= bus_r(8 downto 8);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3))) then
tmp_15_reg_558 <= bus_r(9 downto 9);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3))) then
tmp_16_reg_562 <= bus_r(10 downto 10);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3))) then
tmp_17_reg_566 <= bus_r(11 downto 11);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3))) then
tmp_18_reg_570 <= bus_r(12 downto 12);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3))) then
tmp_19_reg_574 <= bus_r(13 downto 13);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3))) then
tmp_20_reg_578 <= bus_r(14 downto 14);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3))) then
tmp_21_reg_582 <= bus_r(15 downto 15);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3))) then
tmp_22_reg_586 <= bus_r(16 downto 16);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3))) then
tmp_23_reg_590 <= bus_r(17 downto 17);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3))) then
tmp_24_reg_594 <= bus_r(18 downto 18);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3))) then
tmp_25_reg_598 <= bus_r(19 downto 19);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3))) then
tmp_26_reg_602 <= bus_r(20 downto 20);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3))) then
tmp_27_reg_606 <= bus_r(21 downto 21);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3))) then
tmp_28_reg_610 <= bus_r(22 downto 22);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3))) then
tmp_29_reg_614 <= bus_r(23 downto 23);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3))) then
tmp_30_reg_618 <= bus_r(24 downto 24);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3))) then
tmp_31_reg_622 <= bus_r(25 downto 25);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3))) then
tmp_32_reg_626 <= bus_r(26 downto 26);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3))) then
tmp_33_reg_630 <= bus_r(27 downto 27);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3) and (ap_const_lv1_0 = tmp_33_fu_490_p3))) then
tmp_34_reg_634 <= bus_r(28 downto 28);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3) and (ap_const_lv1_0 = tmp_33_fu_490_p3) and (ap_const_lv1_0 = tmp_34_fu_498_p3))) then
tmp_35_reg_638 <= bus_r(29 downto 29);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3) and (ap_const_lv1_0 = tmp_33_fu_490_p3) and (ap_const_lv1_0 = tmp_34_fu_498_p3) and (ap_const_lv1_0 = tmp_35_fu_506_p3))) then
tmp_36_reg_642 <= bus_r(30 downto 30);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0))) then
tmp_7_reg_526 <= bus_r(1 downto 1);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0))) then
tmp_8_reg_530 <= bus_r(2 downto 2);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3))) then
tmp_9_reg_534 <= bus_r(3 downto 3);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_ce)) then
tmp_reg_522 <= tmp_fu_278_p1;
end if;
end if;
end process;
ap_reg_phiprechg_merge_reg_265pp0_it1(0) <= '1';
ap_reg_phiprechg_merge_reg_265pp0_it0 <= ap_const_lv5_1;
ap_reg_phiprechg_p_s_reg_136pp0_it0 <= ap_const_lv5_1;
ap_return <= merge_phi_fu_269_p4;
-- ap_sig_bdd_178 assign process. --
ap_sig_bdd_178_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3)
begin
ap_sig_bdd_178 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and not((tmp_7_fu_282_p3 = ap_const_lv1_0)));
end process;
-- ap_sig_bdd_183 assign process. --
ap_sig_bdd_183_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3)
begin
ap_sig_bdd_183 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and not((ap_const_lv1_0 = tmp_8_fu_290_p3)));
end process;
-- ap_sig_bdd_189 assign process. --
ap_sig_bdd_189_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3)
begin
ap_sig_bdd_189 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and not((ap_const_lv1_0 = tmp_9_fu_298_p3)));
end process;
-- ap_sig_bdd_196 assign process. --
ap_sig_bdd_196_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3)
begin
ap_sig_bdd_196 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and not((ap_const_lv1_0 = tmp_10_fu_306_p3)));
end process;
-- ap_sig_bdd_204 assign process. --
ap_sig_bdd_204_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3)
begin
ap_sig_bdd_204 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and not((ap_const_lv1_0 = tmp_11_fu_314_p3)));
end process;
-- ap_sig_bdd_213 assign process. --
ap_sig_bdd_213_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3)
begin
ap_sig_bdd_213 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and not((ap_const_lv1_0 = tmp_12_fu_322_p3)));
end process;
-- ap_sig_bdd_223 assign process. --
ap_sig_bdd_223_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3)
begin
ap_sig_bdd_223 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and not((ap_const_lv1_0 = tmp_13_fu_330_p3)));
end process;
-- ap_sig_bdd_234 assign process. --
ap_sig_bdd_234_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3)
begin
ap_sig_bdd_234 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and not((ap_const_lv1_0 = tmp_14_fu_338_p3)));
end process;
-- ap_sig_bdd_246 assign process. --
ap_sig_bdd_246_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3)
begin
ap_sig_bdd_246 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and not((ap_const_lv1_0 = tmp_15_fu_346_p3)));
end process;
-- ap_sig_bdd_259 assign process. --
ap_sig_bdd_259_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3)
begin
ap_sig_bdd_259 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and not((ap_const_lv1_0 = tmp_16_fu_354_p3)));
end process;
-- ap_sig_bdd_273 assign process. --
ap_sig_bdd_273_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3)
begin
ap_sig_bdd_273 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and not((ap_const_lv1_0 = tmp_17_fu_362_p3)));
end process;
-- ap_sig_bdd_288 assign process. --
ap_sig_bdd_288_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3)
begin
ap_sig_bdd_288 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and not((ap_const_lv1_0 = tmp_18_fu_370_p3)));
end process;
-- ap_sig_bdd_304 assign process. --
ap_sig_bdd_304_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3)
begin
ap_sig_bdd_304 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and not((ap_const_lv1_0 = tmp_19_fu_378_p3)));
end process;
-- ap_sig_bdd_321 assign process. --
ap_sig_bdd_321_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3)
begin
ap_sig_bdd_321 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and not((ap_const_lv1_0 = tmp_20_fu_386_p3)));
end process;
-- ap_sig_bdd_339 assign process. --
ap_sig_bdd_339_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3)
begin
ap_sig_bdd_339 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and not((ap_const_lv1_0 = tmp_21_fu_394_p3)));
end process;
-- ap_sig_bdd_358 assign process. --
ap_sig_bdd_358_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3)
begin
ap_sig_bdd_358 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and not((ap_const_lv1_0 = tmp_22_fu_402_p3)));
end process;
-- ap_sig_bdd_378 assign process. --
ap_sig_bdd_378_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3)
begin
ap_sig_bdd_378 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and not((ap_const_lv1_0 = tmp_23_fu_410_p3)));
end process;
-- ap_sig_bdd_399 assign process. --
ap_sig_bdd_399_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3)
begin
ap_sig_bdd_399 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and not((ap_const_lv1_0 = tmp_24_fu_418_p3)));
end process;
-- ap_sig_bdd_421 assign process. --
ap_sig_bdd_421_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3)
begin
ap_sig_bdd_421 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and not((ap_const_lv1_0 = tmp_25_fu_426_p3)));
end process;
-- ap_sig_bdd_444 assign process. --
ap_sig_bdd_444_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3)
begin
ap_sig_bdd_444 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and not((ap_const_lv1_0 = tmp_26_fu_434_p3)));
end process;
-- ap_sig_bdd_468 assign process. --
ap_sig_bdd_468_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3)
begin
ap_sig_bdd_468 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and not((ap_const_lv1_0 = tmp_27_fu_442_p3)));
end process;
-- ap_sig_bdd_493 assign process. --
ap_sig_bdd_493_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3)
begin
ap_sig_bdd_493 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and not((ap_const_lv1_0 = tmp_28_fu_450_p3)));
end process;
-- ap_sig_bdd_519 assign process. --
ap_sig_bdd_519_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3)
begin
ap_sig_bdd_519 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and not((ap_const_lv1_0 = tmp_29_fu_458_p3)));
end process;
-- ap_sig_bdd_546 assign process. --
ap_sig_bdd_546_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3, tmp_30_fu_466_p3)
begin
ap_sig_bdd_546 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and not((ap_const_lv1_0 = tmp_30_fu_466_p3)));
end process;
-- ap_sig_bdd_574 assign process. --
ap_sig_bdd_574_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3, tmp_30_fu_466_p3, tmp_31_fu_474_p3)
begin
ap_sig_bdd_574 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and not((ap_const_lv1_0 = tmp_31_fu_474_p3)));
end process;
-- ap_sig_bdd_603 assign process. --
ap_sig_bdd_603_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3, tmp_30_fu_466_p3, tmp_31_fu_474_p3, tmp_32_fu_482_p3)
begin
ap_sig_bdd_603 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and not((ap_const_lv1_0 = tmp_32_fu_482_p3)));
end process;
-- ap_sig_bdd_633 assign process. --
ap_sig_bdd_633_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3, tmp_30_fu_466_p3, tmp_31_fu_474_p3, tmp_32_fu_482_p3, tmp_33_fu_490_p3)
begin
ap_sig_bdd_633 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3) and not((ap_const_lv1_0 = tmp_33_fu_490_p3)));
end process;
-- ap_sig_bdd_664 assign process. --
ap_sig_bdd_664_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3, tmp_30_fu_466_p3, tmp_31_fu_474_p3, tmp_32_fu_482_p3, tmp_33_fu_490_p3, tmp_34_fu_498_p3)
begin
ap_sig_bdd_664 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3) and (ap_const_lv1_0 = tmp_33_fu_490_p3) and not((ap_const_lv1_0 = tmp_34_fu_498_p3)));
end process;
-- ap_sig_bdd_696 assign process. --
ap_sig_bdd_696_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3, tmp_30_fu_466_p3, tmp_31_fu_474_p3, tmp_32_fu_482_p3, tmp_33_fu_490_p3, tmp_34_fu_498_p3, tmp_35_fu_506_p3)
begin
ap_sig_bdd_696 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3) and (ap_const_lv1_0 = tmp_33_fu_490_p3) and (ap_const_lv1_0 = tmp_34_fu_498_p3) and not((ap_const_lv1_0 = tmp_35_fu_506_p3)));
end process;
-- ap_sig_bdd_730 assign process. --
ap_sig_bdd_730_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3, tmp_30_fu_466_p3, tmp_31_fu_474_p3, tmp_32_fu_482_p3, tmp_33_fu_490_p3, tmp_34_fu_498_p3, tmp_35_fu_506_p3, tmp_36_fu_514_p3)
begin
ap_sig_bdd_730 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3) and (ap_const_lv1_0 = tmp_33_fu_490_p3) and (ap_const_lv1_0 = tmp_34_fu_498_p3) and (ap_const_lv1_0 = tmp_35_fu_506_p3) and not((ap_const_lv1_0 = tmp_36_fu_514_p3)));
end process;
-- ap_sig_bdd_764 assign process. --
ap_sig_bdd_764_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3, tmp_30_fu_466_p3, tmp_31_fu_474_p3, tmp_32_fu_482_p3, tmp_33_fu_490_p3, tmp_34_fu_498_p3, tmp_35_fu_506_p3, tmp_36_fu_514_p3)
begin
ap_sig_bdd_764 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3) and (ap_const_lv1_0 = tmp_33_fu_490_p3) and (ap_const_lv1_0 = tmp_34_fu_498_p3) and (ap_const_lv1_0 = tmp_35_fu_506_p3) and (ap_const_lv1_0 = tmp_36_fu_514_p3));
end process;
-- merge_phi_fu_269_p4 assign process. --
merge_phi_fu_269_p4_assign_proc : process(tmp_reg_522, tmp_7_reg_526, tmp_8_reg_530, tmp_9_reg_534, tmp_10_reg_538, tmp_11_reg_542, tmp_12_reg_546, tmp_13_reg_550, tmp_14_reg_554, tmp_15_reg_558, tmp_16_reg_562, tmp_17_reg_566, tmp_18_reg_570, tmp_19_reg_574, tmp_20_reg_578, tmp_21_reg_582, tmp_22_reg_586, tmp_23_reg_590, tmp_24_reg_594, tmp_25_reg_598, tmp_26_reg_602, tmp_27_reg_606, tmp_28_reg_610, tmp_29_reg_614, tmp_30_reg_618, tmp_31_reg_622, tmp_32_reg_626, tmp_33_reg_630, tmp_34_reg_634, tmp_35_reg_638, tmp_36_reg_642, ap_reg_phiprechg_p_s_reg_136pp0_it1, ap_reg_phiprechg_merge_reg_265pp0_it1)
begin
if ((not((tmp_reg_522 = ap_const_lv1_0)) or not((tmp_7_reg_526 = ap_const_lv1_0)) or not((ap_const_lv1_0 = tmp_8_reg_530)) or not((ap_const_lv1_0 = tmp_9_reg_534)) or not((ap_const_lv1_0 = tmp_10_reg_538)) or not((ap_const_lv1_0 = tmp_11_reg_542)) or not((ap_const_lv1_0 = tmp_12_reg_546)) or not((ap_const_lv1_0 = tmp_13_reg_550)) or not((ap_const_lv1_0 = tmp_14_reg_554)) or not((ap_const_lv1_0 = tmp_15_reg_558)) or not((ap_const_lv1_0 = tmp_16_reg_562)) or not((ap_const_lv1_0 = tmp_17_reg_566)) or not((ap_const_lv1_0 = tmp_18_reg_570)) or not((ap_const_lv1_0 = tmp_19_reg_574)) or not((ap_const_lv1_0 = tmp_20_reg_578)) or not((ap_const_lv1_0 = tmp_21_reg_582)) or not((ap_const_lv1_0 = tmp_22_reg_586)) or not((ap_const_lv1_0 = tmp_23_reg_590)) or not((ap_const_lv1_0 = tmp_24_reg_594)) or not((ap_const_lv1_0 = tmp_25_reg_598)) or not((ap_const_lv1_0 = tmp_26_reg_602)) or not((ap_const_lv1_0 = tmp_27_reg_606)) or not((ap_const_lv1_0 = tmp_28_reg_610)) or not((ap_const_lv1_0 = tmp_29_reg_614)) or not((ap_const_lv1_0 = tmp_30_reg_618)) or not((ap_const_lv1_0 = tmp_31_reg_622)) or not((ap_const_lv1_0 = tmp_32_reg_626)) or not((ap_const_lv1_0 = tmp_33_reg_630)) or not((ap_const_lv1_0 = tmp_34_reg_634)) or not((ap_const_lv1_0 = tmp_35_reg_638)) or not((ap_const_lv1_0 = tmp_36_reg_642)))) then
merge_phi_fu_269_p4 <= ap_reg_phiprechg_p_s_reg_136pp0_it1;
else
merge_phi_fu_269_p4 <= ap_reg_phiprechg_merge_reg_265pp0_it1;
end if;
end process;
tmp_10_fu_306_p3 <= bus_r(4 downto 4);
tmp_11_fu_314_p3 <= bus_r(5 downto 5);
tmp_12_fu_322_p3 <= bus_r(6 downto 6);
tmp_13_fu_330_p3 <= bus_r(7 downto 7);
tmp_14_fu_338_p3 <= bus_r(8 downto 8);
tmp_15_fu_346_p3 <= bus_r(9 downto 9);
tmp_16_fu_354_p3 <= bus_r(10 downto 10);
tmp_17_fu_362_p3 <= bus_r(11 downto 11);
tmp_18_fu_370_p3 <= bus_r(12 downto 12);
tmp_19_fu_378_p3 <= bus_r(13 downto 13);
tmp_20_fu_386_p3 <= bus_r(14 downto 14);
tmp_21_fu_394_p3 <= bus_r(15 downto 15);
tmp_22_fu_402_p3 <= bus_r(16 downto 16);
tmp_23_fu_410_p3 <= bus_r(17 downto 17);
tmp_24_fu_418_p3 <= bus_r(18 downto 18);
tmp_25_fu_426_p3 <= bus_r(19 downto 19);
tmp_26_fu_434_p3 <= bus_r(20 downto 20);
tmp_27_fu_442_p3 <= bus_r(21 downto 21);
tmp_28_fu_450_p3 <= bus_r(22 downto 22);
tmp_29_fu_458_p3 <= bus_r(23 downto 23);
tmp_30_fu_466_p3 <= bus_r(24 downto 24);
tmp_31_fu_474_p3 <= bus_r(25 downto 25);
tmp_32_fu_482_p3 <= bus_r(26 downto 26);
tmp_33_fu_490_p3 <= bus_r(27 downto 27);
tmp_34_fu_498_p3 <= bus_r(28 downto 28);
tmp_35_fu_506_p3 <= bus_r(29 downto 29);
tmp_36_fu_514_p3 <= bus_r(30 downto 30);
tmp_7_fu_282_p3 <= bus_r(1 downto 1);
tmp_8_fu_290_p3 <= bus_r(2 downto 2);
tmp_9_fu_298_p3 <= bus_r(3 downto 3);
tmp_fu_278_p1 <= bus_r(1 - 1 downto 0);
end behav;
|
--
-- PhaseGenerator.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity PhaseGenerator is port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
rhythm : in std_logic;
pm : in PM_TYPE;
ml : in ML_TYPE;
blk : in BLK_TYPE;
fnum : in FNUM_TYPE;
key : in std_logic;
noise : out std_logic;
pgout : out PGOUT_TYPE
);
end PhaseGenerator;
architecture RTL of PhaseGenerator is
component PhaseMemory is port (
clk : in std_logic;
reset : in std_logic;
slot : in SLOT_TYPE;
memwr : in std_logic;
memout : out PHASE_TYPE;
memin : in PHASE_TYPE
);
end component;
type ML_TABLE is array (0 to 15) of std_logic_vector(4 downto 0);
constant mltbl : ML_TABLE := (
"00001","00010","00100","00110","01000","01010","01100","01110",
"10000","10010","10100","10100","11000","11000","11110","11110"
);
constant noise14_tbl : std_logic_vector(63 downto 0) :=
"1000100010001000100010001000100100010001000100010001000100010000";
constant noise17_tbl : std_logic_vector(7 downto 0) :=
"00001010";
-- Signals connected to the phase memory.
signal memwr : std_logic;
signal memout, memin : PHASE_TYPE;
-- Counter for pitch modulation;
signal pmcount : std_logic_vector(12 downto 0);
function CONV_PGOUT ( pv : PHASE_TYPE ) return PGOUT_TYPE is
begin
return pv(PHASE_TYPE'high downto PHASE_TYPE'high - PGOUT_TYPE'high);
end;
begin
process(clk, reset)
variable lastkey : std_logic_vector(MAXSLOT-1 downto 0);
variable dphase : PHASE_TYPE;
variable noise14 : std_logic;
variable noise17 : std_logic;
variable pgout_buf : PGOUT_TYPE;
begin
if reset = '1' then
pmcount <= (others=>'0');
memwr <= '0';
lastkey := (others=>'0');
dphase := (others=>'0');
noise14 := '0';
noise17 := '0';
elsif clk'event and clk='1' then if clkena = '1' then
noise <= noise14 xor noise17;
if stage = 0 then
memwr <= '0';
elsif stage = 1 then
-- Wait for memory
elsif stage = 2 then
-- Update pitch LFO counter when slot = 0 and stage = 0 (i.e. increment per 72 clocks)
if slot = 0 then
pmcount <= pmcount + '1';
end if;
-- Delta phase
dphase := (SHL("00000000"&(fnum*mltbl(CONV_INTEGER(ml))),blk)(19 downto 2));
if pm ='1' then
case pmcount(pmcount'high downto pmcount'high-1) is
when "01" =>
dphase := dphase + SHR(dphase,"111");
when "11" =>
dphase := dphase - SHR(dphase,"111");
when others => null;
end case;
end if;
-- Update Phase
if lastkey(slot) = '0' and key = '1' and (rhythm = '0' or (slot /= 14 and slot /= 17)) then
memin <= (others=>'0');
else
memin <= memout + dphase;
end if;
lastkey(slot) := key;
-- Update noise
if slot = 14 then
noise14 := noise14_tbl(CONV_INTEGER(memout(15 downto 10)));
elsif slot = 17 then
noise17 := noise17_tbl(CONV_INTEGER(memout(13 downto 11)));
end if;
pgout_buf := CONV_PGOUT(memout);
pgout <= pgout_buf;
memwr <= '1';
elsif stage = 3 then
memwr <= '0';
end if;
end if; end if;
end process;
MEM : PhaseMemory port map(clk,reset,slot,memwr,memout,memin);
end RTL;
|
--
-- PhaseGenerator.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity PhaseGenerator is port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
rhythm : in std_logic;
pm : in PM_TYPE;
ml : in ML_TYPE;
blk : in BLK_TYPE;
fnum : in FNUM_TYPE;
key : in std_logic;
noise : out std_logic;
pgout : out PGOUT_TYPE
);
end PhaseGenerator;
architecture RTL of PhaseGenerator is
component PhaseMemory is port (
clk : in std_logic;
reset : in std_logic;
slot : in SLOT_TYPE;
memwr : in std_logic;
memout : out PHASE_TYPE;
memin : in PHASE_TYPE
);
end component;
type ML_TABLE is array (0 to 15) of std_logic_vector(4 downto 0);
constant mltbl : ML_TABLE := (
"00001","00010","00100","00110","01000","01010","01100","01110",
"10000","10010","10100","10100","11000","11000","11110","11110"
);
constant noise14_tbl : std_logic_vector(63 downto 0) :=
"1000100010001000100010001000100100010001000100010001000100010000";
constant noise17_tbl : std_logic_vector(7 downto 0) :=
"00001010";
-- Signals connected to the phase memory.
signal memwr : std_logic;
signal memout, memin : PHASE_TYPE;
-- Counter for pitch modulation;
signal pmcount : std_logic_vector(12 downto 0);
function CONV_PGOUT ( pv : PHASE_TYPE ) return PGOUT_TYPE is
begin
return pv(PHASE_TYPE'high downto PHASE_TYPE'high - PGOUT_TYPE'high);
end;
begin
process(clk, reset)
variable lastkey : std_logic_vector(MAXSLOT-1 downto 0);
variable dphase : PHASE_TYPE;
variable noise14 : std_logic;
variable noise17 : std_logic;
variable pgout_buf : PGOUT_TYPE;
begin
if reset = '1' then
pmcount <= (others=>'0');
memwr <= '0';
lastkey := (others=>'0');
dphase := (others=>'0');
noise14 := '0';
noise17 := '0';
elsif clk'event and clk='1' then if clkena = '1' then
noise <= noise14 xor noise17;
if stage = 0 then
memwr <= '0';
elsif stage = 1 then
-- Wait for memory
elsif stage = 2 then
-- Update pitch LFO counter when slot = 0 and stage = 0 (i.e. increment per 72 clocks)
if slot = 0 then
pmcount <= pmcount + '1';
end if;
-- Delta phase
dphase := (SHL("00000000"&(fnum*mltbl(CONV_INTEGER(ml))),blk)(19 downto 2));
if pm ='1' then
case pmcount(pmcount'high downto pmcount'high-1) is
when "01" =>
dphase := dphase + SHR(dphase,"111");
when "11" =>
dphase := dphase - SHR(dphase,"111");
when others => null;
end case;
end if;
-- Update Phase
if lastkey(slot) = '0' and key = '1' and (rhythm = '0' or (slot /= 14 and slot /= 17)) then
memin <= (others=>'0');
else
memin <= memout + dphase;
end if;
lastkey(slot) := key;
-- Update noise
if slot = 14 then
noise14 := noise14_tbl(CONV_INTEGER(memout(15 downto 10)));
elsif slot = 17 then
noise17 := noise17_tbl(CONV_INTEGER(memout(13 downto 11)));
end if;
pgout_buf := CONV_PGOUT(memout);
pgout <= pgout_buf;
memwr <= '1';
elsif stage = 3 then
memwr <= '0';
end if;
end if; end if;
end process;
MEM : PhaseMemory port map(clk,reset,slot,memwr,memout,memin);
end RTL;
|
entity t87 is
end;
architecture behav of t87 is
constant t1 : time := 1 ns;
constant t2 : natural := time'pos (t1);
begin
assert t1 = 1000 ps;
process
variable v : natural;
begin
-- Time resolution must be ps
v := time'pos(ps);
assert v = 1 severity failure;
wait;
end process;
end behav;
|
entity t87 is
end;
architecture behav of t87 is
constant t1 : time := 1 ns;
constant t2 : natural := time'pos (t1);
begin
assert t1 = 1000 ps;
process
variable v : natural;
begin
-- Time resolution must be ps
v := time'pos(ps);
assert v = 1 severity failure;
wait;
end process;
end behav;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity SEMI_MIPS is
port (
clk : in std_logic;
external_reset : in std_logic;
we : out std_logic;
re : out std_logic;
address : out std_logic_vector(7 downto 0);
memory_in : in std_logic_vector(15 downto 0);
memory_out : out std_logic_vector(15 downto 0)
);
end entity;
architecture DATA_PATH of SEMI_MIPS is
component ALU is
port(
CARRY_IN : in std_logic;
INPUT1 : in std_logic_vector(16 - 1 downto 0);
INPUT2 : in std_logic_vector(16 - 1 downto 0);
OPERATION : in std_logic_vector(3 downto 0);
OUTPUT : out std_logic_vector(16 - 1 downto 0);
CARRY_OUT : out std_logic;
ZERO_OUT : out std_logic
);
end component;
component STATUS_REGISTER is
PORT (
carryIn, overflowIn : IN std_logic;
data : IN std_logic_vector (15 DOWNTO 0);
carry, zero, sign, parity, borrow, overflow : OUT std_logic
);
end component;
component registerFile is
port (
CLK : in std_logic;
W_EN : in std_logic;
INPUT : in std_logic_vector(15 downto 0);
IN_ADR : in std_logic_vector(3 downto 0);
OUT1_ADR: in std_logic_vector(3 downto 0);
OUT2_ADR: in std_logic_vector(3 downto 0);
OUTPUT1 : out std_logic_vector(15 downto 0);
OUTPUT2 : out std_logic_vector(15 downto 0);
REG0_OUT: out std_logic_vector(15 downto 0)
);
end component;
component ADDRESS_UNIT is
PORT (
Iside : IN std_logic_vector (7 DOWNTO 0);
Address : OUT std_logic_vector (7 DOWNTO 0);
clk, ResetPC, Im, PCplus1 : IN std_logic;
EnablePC : IN std_logic
);
end component;
component reg16b is
port(clk, load, reset : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000"
);
end component;
component CU is
port (
clk, ExternalReset,
carry, zero, sign, parity, borrow, overflow -- status register
: in STD_LOGIC;
IRout : in STD_LOGIC_VECTOR(15 downto 0); -- IR
reg0 : in STD_LOGIC_VECTOR(15 downto 0); -- Register(0)
ALUout_on_Databus, -- Data Bus
IRload, -- IR
ResetPC, Im, PCplus1, EnablePC, -- Address Unit
W_EN, -- register file
we, re, -- memory
itype
: out STD_LOGIC;
-- ALU's bits
alu_operation : out std_logic_vector(3 downto 0);
databus : inout std_logic_vector(15 downto 0)
);
end component;
signal DATABUS : std_logic_vector(15 downto 0);
signal S1 , S2 , reg2 , d : std_logic_vector(2 downto 0);
signal REG_IN_ADR, REG_OUT1_ADR, REG_OUT2_ADR : std_logic_vector(3 downto 0);
signal ALU_OP : std_logic_vector(3 downto 0);
signal ALUoutput, ALU_INPUT2 : std_logic_vector(15 downto 0);
signal ALU_Zero : std_logic;
signal ALUout_on_Databus : std_logic;
signal ResetPC : std_logic;
signal carryIn, overflowIn, carry, zero, sign, parity, borrow, overflow : std_logic;
signal REG0_OUT ,REG_FILE_SRC1 , REG_FILE_SRC2 , IRout : std_logic_vector (15 downto 0);
signal W_EN : std_logic;
signal itype : std_logic;
signal IRLoad, IRReset : std_logic;
signal Im : std_logic;
signal PCplus1, EnablePC : std_logic;
constant STORE_INSTRUCTION_CODE : std_logic_vector(3 downto 0) := "1101";
begin
DATABUS <= memory_in;
memory_out <= DATABUS;
IR : component reg16b
port map(
clk => clk,
load => IRLoad,
reset => IRReset,
input => DATABUS,
output => IRout
);
ADDRESS_UNIT_inst : component ADDRESS_UNIT
port map(
Iside => IRout(7 downto 0),
Address => Address,
clk => clk,
ResetPC => external_reset,
Im => Im,
PCplus1 => PCplus1,
EnablePC => EnablePC
);
ALU_inst : component ALU
port map(
CARRY_IN => carry,
INPUT1 => REG_FILE_SRC1,
INPUT2 => ALU_INPUT2,
OPERATION => ALU_OP,
OUTPUT => ALUoutput,
CARRY_OUT => carryIn,
ZERO_OUT => ALU_Zero
);
STATUS_REGISTER_inst : component STATUS_REGISTER
port map(
carryIn => carryIn,
overflowIn => overflowIn,
data => ALUoutput,
carry => carry,
zero => zero,
sign => sign,
parity => parity,
borrow => borrow,
overflow => overflow
);
REGFILE_INPUT_ADDRESS : with IRout(15 downto 12) select
REG_IN_ADR <=
IRout(11 downto 8) when STORE_INSTRUCTION_CODE,
IRout(7 downto 4) when others;
registerFile_inst : component registerFile
port map(
CLK => CLK,
W_EN => W_EN,
INPUT => DATABUS,
IN_ADR => REG_IN_ADR,
OUT1_ADR => REG_OUT1_ADR,
OUT2_ADR => REG_OUT2_ADR,
OUTPUT1 => REG_FILE_SRC1,
OUTPUT2 => REG_FILE_SRC2,
REG0_OUT => REG0_OUT
);
CU_inst : component CU
port map(
clk => clk,
ExternalReset => external_reset,
carry => carry,
zero => zero,
sign => sign,
parity => parity,
borrow => borrow,
overflow => overflow,
IRout => IRout,
reg0 => REG0_OUT,
ALUout_on_Databus => ALUout_on_Databus,
IRload => IRload,
ResetPC => ResetPC,
Im => Im,
PCplus1 => PCplus1,
EnablePC => EnablePC,
W_EN => W_EN,
we => we,
re => re,
itype => itype,
alu_operation => ALU_OP,
databus => DATABUS
);
ALU_INPUT2_MUX : with itype select
ALU_INPUT2 <=
REG_FILE_SRC2 when '0',
"00000000" & Im when '1',
REG_FILE_SRC2 when others;
ALU_OUT_MUX : with ALUout_on_Databus select
DATABUS <=
ALUoutput when '1',
"ZZZZZZZZZZZZZZZZ" when others;
end architecture; |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- <UUT NAME> T E S T B E N C H (<uut_name>_tb.vhd)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
ENTITY <uut_name>_tb is
-------------------------------------------------------------------------------
begin
end <uut_name>_tb;
-------------------------------------------------------------------------------
ARCHITECTURE simulation of <uut_name>_tb is
-------------------------------------------------------------------------------
-- constants
constant CLK_PERIOD : time := 10 ns;
-- signals
signal clk : std_logic;
signal rst : std_logic;
begin
-------------------------------------------------
STIMULI_PROC :
-------------------------------------------------
process begin
-- hold reset for 100 ns and 10 clock cycles
rst <= '1';
wait for 100 ns;
wait for CLK_PERIOD*10;
-- place stimuli here:
wait; -- forever
end process STIMULI_PROC;
-------------------------------------------------
-- UUT instantiation
-------------------------------------------------
UUT : soc_bridge
port map (
clk_i => clk,
rst_i => rst
);
-------------------------------------------------
CLK_GENERATOR :
-------------------------------------------------
process begin
clk <= '0';
wait for CLK_PERIOD/2;
clk <= '1';
wait for CLK_PERIOD/2;
end process CLK_GENERATOR;
end simulation;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01.03.2016 12:10:07
-- Design Name:
-- Module Name: VRAM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity VRAM is
-- Port ( );
end VRAM;
architecture Behavioral of VRAM is
begin
end Behavioral;
|
-- NEED RESULT: ARCH00181.P1: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00181.P2: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00181.P3: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00181.P4: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00181.P5: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00181.P6: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Old transactions were removed on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Old transactions were removed on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Old transactions were removed on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Old transactions were removed on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Old transactions were removed on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Old transactions were removed on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: P6: Inertial transactions entirely completed failed
-- NEED RESULT: P5: Inertial transactions entirely completed failed
-- NEED RESULT: P4: Inertial transactions entirely completed failed
-- NEED RESULT: P3: Inertial transactions entirely completed failed
-- NEED RESULT: P2: Inertial transactions entirely completed failed
-- NEED RESULT: P1: Inertial transactions entirely completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00181
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00181
-- PKG00181/BODY
-- ENT00181(ARCH00181)
-- ENT00181_Test_Bench(ARCH00181_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
package PKG00181 is
type r_st_arr1_vector is record
f1 : integer ;
f2 : st_arr1_vector ;
end record ;
function c_r_st_arr1_vector_1 return r_st_arr1_vector ;
-- (c_integer_1, c_st_arr1_vector_1) ;
function c_r_st_arr1_vector_2 return r_st_arr1_vector ;
-- (c_integer_2, c_st_arr1_vector_2) ;
--
type r_st_arr2_vector is record
f1 : integer ;
f2 : st_arr2_vector ;
end record ;
function c_r_st_arr2_vector_1 return r_st_arr2_vector ;
-- (c_integer_1, c_st_arr2_vector_1) ;
function c_r_st_arr2_vector_2 return r_st_arr2_vector ;
-- (c_integer_2, c_st_arr2_vector_2) ;
--
type r_st_arr3_vector is record
f1 : integer ;
f2 : st_arr3_vector ;
end record ;
function c_r_st_arr3_vector_1 return r_st_arr3_vector ;
-- (c_integer_1, c_st_arr3_vector_1) ;
function c_r_st_arr3_vector_2 return r_st_arr3_vector ;
-- (c_integer_2, c_st_arr3_vector_2) ;
--
type r_st_rec1_vector is record
f1 : integer ;
f2 : st_rec1_vector ;
end record ;
function c_r_st_rec1_vector_1 return r_st_rec1_vector ;
-- (c_integer_1, c_st_rec1_vector_1) ;
function c_r_st_rec1_vector_2 return r_st_rec1_vector ;
-- (c_integer_2, c_st_rec1_vector_2) ;
--
type r_st_rec2_vector is record
f1 : integer ;
f2 : st_rec2_vector ;
end record ;
function c_r_st_rec2_vector_1 return r_st_rec2_vector ;
-- (c_integer_1, c_st_rec2_vector_1) ;
function c_r_st_rec2_vector_2 return r_st_rec2_vector ;
-- (c_integer_2, c_st_rec2_vector_2) ;
--
type r_st_rec3_vector is record
f1 : integer ;
f2 : st_rec3_vector ;
end record ;
function c_r_st_rec3_vector_1 return r_st_rec3_vector ;
-- (c_integer_1, c_st_rec3_vector_1) ;
function c_r_st_rec3_vector_2 return r_st_rec3_vector ;
-- (c_integer_2, c_st_rec3_vector_2) ;
--
--
end PKG00181 ;
--
package body PKG00181 is
function c_r_st_arr1_vector_1 return r_st_arr1_vector
is begin
return (c_integer_1, c_st_arr1_vector_1) ;
end c_r_st_arr1_vector_1 ;
--
function c_r_st_arr1_vector_2 return r_st_arr1_vector
is begin
return (c_integer_2, c_st_arr1_vector_2) ;
end c_r_st_arr1_vector_2 ;
--
--
function c_r_st_arr2_vector_1 return r_st_arr2_vector
is begin
return (c_integer_1, c_st_arr2_vector_1) ;
end c_r_st_arr2_vector_1 ;
--
function c_r_st_arr2_vector_2 return r_st_arr2_vector
is begin
return (c_integer_2, c_st_arr2_vector_2) ;
end c_r_st_arr2_vector_2 ;
--
--
function c_r_st_arr3_vector_1 return r_st_arr3_vector
is begin
return (c_integer_1, c_st_arr3_vector_1) ;
end c_r_st_arr3_vector_1 ;
--
function c_r_st_arr3_vector_2 return r_st_arr3_vector
is begin
return (c_integer_2, c_st_arr3_vector_2) ;
end c_r_st_arr3_vector_2 ;
--
--
function c_r_st_rec1_vector_1 return r_st_rec1_vector
is begin
return (c_integer_1, c_st_rec1_vector_1) ;
end c_r_st_rec1_vector_1 ;
--
function c_r_st_rec1_vector_2 return r_st_rec1_vector
is begin
return (c_integer_2, c_st_rec1_vector_2) ;
end c_r_st_rec1_vector_2 ;
--
--
function c_r_st_rec2_vector_1 return r_st_rec2_vector
is begin
return (c_integer_1, c_st_rec2_vector_1) ;
end c_r_st_rec2_vector_1 ;
--
function c_r_st_rec2_vector_2 return r_st_rec2_vector
is begin
return (c_integer_2, c_st_rec2_vector_2) ;
end c_r_st_rec2_vector_2 ;
--
--
function c_r_st_rec3_vector_1 return r_st_rec3_vector
is begin
return (c_integer_1, c_st_rec3_vector_1) ;
end c_r_st_rec3_vector_1 ;
--
function c_r_st_rec3_vector_2 return r_st_rec3_vector
is begin
return (c_integer_2, c_st_rec3_vector_2) ;
end c_r_st_rec3_vector_2 ;
--
--
--
end PKG00181 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00181.all ;
entity ENT00181 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_r_st_arr1_vector : chk_sig_type := -1 ;
signal chk_r_st_arr2_vector : chk_sig_type := -1 ;
signal chk_r_st_arr3_vector : chk_sig_type := -1 ;
signal chk_r_st_rec1_vector : chk_sig_type := -1 ;
signal chk_r_st_rec2_vector : chk_sig_type := -1 ;
signal chk_r_st_rec3_vector : chk_sig_type := -1 ;
--
procedure Proc1 (
signal s_r_st_arr1_vector : inout r_st_arr1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_arr1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
procedure Proc2 (
signal s_r_st_arr2_vector : inout r_st_arr2_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_arr2_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_arr2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc2 ;
--
procedure Proc3 (
signal s_r_st_arr3_vector : inout r_st_arr3_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_arr3_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_arr3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc3 ;
--
procedure Proc4 (
signal s_r_st_rec1_vector : inout r_st_rec1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_rec1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181.P4" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc4 ;
--
procedure Proc5 (
signal s_r_st_rec2_vector : inout r_st_rec2_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_rec2_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181.P5" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc5 ;
--
procedure Proc6 (
signal s_r_st_rec3_vector : inout r_st_rec3_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_rec3_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181.P6" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc6 ;
--
--
end ENT00181 ;
--
architecture ARCH00181 of ENT00181 is
signal s_r_st_arr1_vector : r_st_arr1_vector
:= c_r_st_arr1_vector_1 ;
signal s_r_st_arr2_vector : r_st_arr2_vector
:= c_r_st_arr2_vector_1 ;
signal s_r_st_arr3_vector : r_st_arr3_vector
:= c_r_st_arr3_vector_1 ;
signal s_r_st_rec1_vector : r_st_rec1_vector
:= c_r_st_rec1_vector_1 ;
signal s_r_st_rec2_vector : r_st_rec2_vector
:= c_r_st_rec2_vector_1 ;
signal s_r_st_rec3_vector : r_st_rec3_vector
:= c_r_st_rec3_vector_1 ;
--
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc1 (
s_r_st_arr1_vector,
counter,
correct,
savtime,
chk_r_st_arr1_vector
) ;
wait until (not s_r_st_arr1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_r_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_r_st_arr1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
P2 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc2 (
s_r_st_arr2_vector,
counter,
correct,
savtime,
chk_r_st_arr2_vector
) ;
wait until (not s_r_st_arr2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_r_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_r_st_arr2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
P3 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc3 (
s_r_st_arr3_vector,
counter,
correct,
savtime,
chk_r_st_arr3_vector
) ;
wait until (not s_r_st_arr3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_r_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_r_st_arr3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
P4 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc4 (
s_r_st_rec1_vector,
counter,
correct,
savtime,
chk_r_st_rec1_vector
) ;
wait until (not s_r_st_rec1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P4 ;
--
PGEN_CHKP_4 :
process ( chk_r_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions entirely completed",
chk_r_st_rec1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
P5 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc5 (
s_r_st_rec2_vector,
counter,
correct,
savtime,
chk_r_st_rec2_vector
) ;
wait until (not s_r_st_rec2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P5 ;
--
PGEN_CHKP_5 :
process ( chk_r_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions entirely completed",
chk_r_st_rec2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
P6 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc6 (
s_r_st_rec3_vector,
counter,
correct,
savtime,
chk_r_st_rec3_vector
) ;
wait until (not s_r_st_rec3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P6 ;
--
PGEN_CHKP_6 :
process ( chk_r_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions entirely completed",
chk_r_st_rec3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
--
end ARCH00181 ;
--
entity ENT00181_Test_Bench is
end ENT00181_Test_Bench ;
--
architecture ARCH00181_Test_Bench of ENT00181_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00181 ( ARCH00181 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00181_Test_Bench ;
|
-------------------------------------------------------------------------------
-- Title : TIE-50206, Exercise 06
-- Project :
-------------------------------------------------------------------------------
-- File : wave_gen_bonus.vhd
-- Author : Tuomas Huuki
-- Company : TUT
-- Created : 23.11.2015
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Sixth excercise (bonus).
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 25.11.2015 1.0 tuhu Created
-- 09.12.2015 1.1 nikulaj Tweak bonus
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.fixed_float_types.all;
use ieee.fixed_pkg.all;
entity wave_gen is -- Wave generator entity.
generic
(
width_g : integer := 16; -- Width of the generated wave in bits.
step_g : integer -- Width of one step.
);
port
(
clk : in std_logic; -- Clock signal.
rst_n : in std_logic; -- Reset, actove low.
sync_clear_in : in std_logic; -- Sync bit input to clear the counter.
value_out : out std_logic_vector(width_g - 1 downto 0) -- Counter value out.
);
end wave_gen;
architecture rtl of wave_gen is
constant maxval_c : integer := (2**(width_g - 2) - 1); -- Maximum value for output.
constant minval_c : integer := -maxval_c; -- Minimun value for output.
constant decimals_c : integer := -width_g;
constant d_c : sfixed(width_g-1 downto decimals_c) := resize((2 * to_sfixed(3.141593, width_g-1, decimals_c)) / maxval_c, width_g-1, decimals_c);
signal count_r : sfixed(width_g-1 downto decimals_c);
signal sin_r : sfixed(width_g-1 downto decimals_c);
signal cos_r : sfixed(width_g-1 downto decimals_c);
signal result_r : sfixed(width_g-1 downto decimals_c);
begin -- rtl
value_out <= std_logic_vector(to_signed(result_r, width_g)); -- Assign register to output.
count : process (clk, rst_n) -- Process to increment or decrement counter value.
begin
if(rst_n = '0') then
count_r <= (others => '0'); -- Clear the output on reset ...
sin_r <= (others => '0');
cos_r <= to_sfixed(1.0, cos_r);
elsif(clk'event and clk = '1') then
sin_r <= resize(sin_r + cos_r * d_c, sin_r'high, sin_r'low);
cos_r <= resize(cos_r - sin_r * d_c, cos_r'high, cos_r'low);
result_r <= resize(sin_r * maxval_c, result_r'high, result_r'low);
count_r <= resize(count_r + to_sfixed(1.0, count_r), count_r'high, count_r'low);
if(count_r = maxval_c) then
count_r <= (others => '0');
sin_r <= (others => '0');
cos_r <= to_sfixed(1.0, cos_r);
end if;
end if; -- clk'event ...
end process count;
end rtl;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_18_fg_18_11.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_18_11 is
end entity fg_18_11;
architecture test of fg_18_11 is
subtype byte is bit_vector(7 downto 0);
type byte_array is array (natural range <>) of byte;
function resolve_bytes ( drivers : in byte_array ) return byte is
begin
return drivers(drivers'left);
end function resolve_bytes;
function resolve_bits ( drivers : in bit_vector ) return bit is
begin
return drivers(drivers'left);
end function resolve_bits;
-- code from book (in text)
signal address : bit_vector(15 downto 0);
signal data : resolve_bytes byte;
signal rd, wr, io : bit; -- read, write, io/mem select
signal ready : resolve_bits bit;
-- end code from book
begin
-- code from book
bus_monitor : process is
constant header : string(1 to 44)
:= FF & " Time R/W I/M Address Data";
use std.textio.all;
file log : text open write_mode is "buslog";
variable trace_line : line;
variable line_count : natural := 0;
begin
if line_count mod 60 = 0 then
write ( trace_line, header );
writeline ( log, trace_line );
writeline ( log, trace_line ); -- empty line
end if;
wait until (rd = '1' or wr = '1') and ready = '1';
write ( trace_line, now, justified => right, field => 10, unit => us );
write ( trace_line, string'(" ") );
if rd = '1' then
write ( trace_line, 'R' );
else
write ( trace_line, 'W' );
end if;
write ( trace_line, string'(" ") );
if io = '1' then
write ( trace_line, 'I' );
else
write ( trace_line, 'M' );
end if;
write ( trace_line, string'(" ") );
write ( trace_line, address );
write ( trace_line, ' ');
write ( trace_line, data );
writeline ( log, trace_line );
line_count := line_count + 1;
end process bus_monitor;
-- end code from book
stimulus : process is
begin
wait for 0.4 us - now;
rd <= '1', '0' after 10 ns;
address <= X"0000";
data <= B"10011110";
ready <= '1', '0' after 10 ns;
wait for 0.9 us - now;
rd <= '1', '0' after 10 ns;
address <= X"0001";
data <= B"00010010";
ready <= '1', '0' after 10 ns;
wait for 2.0 us - now;
rd <= '1', '0' after 10 ns;
address <= X"0014";
data <= B"11100111";
ready <= '1', '0' after 10 ns;
wait for 2.7 us - now;
wr <= '1', '0' after 10 ns;
io <= '1', '0' after 10 ns;
address <= X"0007";
data <= X"00";
ready <= '1', '0' after 10 ns;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_18_fg_18_11.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_18_11 is
end entity fg_18_11;
architecture test of fg_18_11 is
subtype byte is bit_vector(7 downto 0);
type byte_array is array (natural range <>) of byte;
function resolve_bytes ( drivers : in byte_array ) return byte is
begin
return drivers(drivers'left);
end function resolve_bytes;
function resolve_bits ( drivers : in bit_vector ) return bit is
begin
return drivers(drivers'left);
end function resolve_bits;
-- code from book (in text)
signal address : bit_vector(15 downto 0);
signal data : resolve_bytes byte;
signal rd, wr, io : bit; -- read, write, io/mem select
signal ready : resolve_bits bit;
-- end code from book
begin
-- code from book
bus_monitor : process is
constant header : string(1 to 44)
:= FF & " Time R/W I/M Address Data";
use std.textio.all;
file log : text open write_mode is "buslog";
variable trace_line : line;
variable line_count : natural := 0;
begin
if line_count mod 60 = 0 then
write ( trace_line, header );
writeline ( log, trace_line );
writeline ( log, trace_line ); -- empty line
end if;
wait until (rd = '1' or wr = '1') and ready = '1';
write ( trace_line, now, justified => right, field => 10, unit => us );
write ( trace_line, string'(" ") );
if rd = '1' then
write ( trace_line, 'R' );
else
write ( trace_line, 'W' );
end if;
write ( trace_line, string'(" ") );
if io = '1' then
write ( trace_line, 'I' );
else
write ( trace_line, 'M' );
end if;
write ( trace_line, string'(" ") );
write ( trace_line, address );
write ( trace_line, ' ');
write ( trace_line, data );
writeline ( log, trace_line );
line_count := line_count + 1;
end process bus_monitor;
-- end code from book
stimulus : process is
begin
wait for 0.4 us - now;
rd <= '1', '0' after 10 ns;
address <= X"0000";
data <= B"10011110";
ready <= '1', '0' after 10 ns;
wait for 0.9 us - now;
rd <= '1', '0' after 10 ns;
address <= X"0001";
data <= B"00010010";
ready <= '1', '0' after 10 ns;
wait for 2.0 us - now;
rd <= '1', '0' after 10 ns;
address <= X"0014";
data <= B"11100111";
ready <= '1', '0' after 10 ns;
wait for 2.7 us - now;
wr <= '1', '0' after 10 ns;
io <= '1', '0' after 10 ns;
address <= X"0007";
data <= X"00";
ready <= '1', '0' after 10 ns;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_18_fg_18_11.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_18_11 is
end entity fg_18_11;
architecture test of fg_18_11 is
subtype byte is bit_vector(7 downto 0);
type byte_array is array (natural range <>) of byte;
function resolve_bytes ( drivers : in byte_array ) return byte is
begin
return drivers(drivers'left);
end function resolve_bytes;
function resolve_bits ( drivers : in bit_vector ) return bit is
begin
return drivers(drivers'left);
end function resolve_bits;
-- code from book (in text)
signal address : bit_vector(15 downto 0);
signal data : resolve_bytes byte;
signal rd, wr, io : bit; -- read, write, io/mem select
signal ready : resolve_bits bit;
-- end code from book
begin
-- code from book
bus_monitor : process is
constant header : string(1 to 44)
:= FF & " Time R/W I/M Address Data";
use std.textio.all;
file log : text open write_mode is "buslog";
variable trace_line : line;
variable line_count : natural := 0;
begin
if line_count mod 60 = 0 then
write ( trace_line, header );
writeline ( log, trace_line );
writeline ( log, trace_line ); -- empty line
end if;
wait until (rd = '1' or wr = '1') and ready = '1';
write ( trace_line, now, justified => right, field => 10, unit => us );
write ( trace_line, string'(" ") );
if rd = '1' then
write ( trace_line, 'R' );
else
write ( trace_line, 'W' );
end if;
write ( trace_line, string'(" ") );
if io = '1' then
write ( trace_line, 'I' );
else
write ( trace_line, 'M' );
end if;
write ( trace_line, string'(" ") );
write ( trace_line, address );
write ( trace_line, ' ');
write ( trace_line, data );
writeline ( log, trace_line );
line_count := line_count + 1;
end process bus_monitor;
-- end code from book
stimulus : process is
begin
wait for 0.4 us - now;
rd <= '1', '0' after 10 ns;
address <= X"0000";
data <= B"10011110";
ready <= '1', '0' after 10 ns;
wait for 0.9 us - now;
rd <= '1', '0' after 10 ns;
address <= X"0001";
data <= B"00010010";
ready <= '1', '0' after 10 ns;
wait for 2.0 us - now;
rd <= '1', '0' after 10 ns;
address <= X"0014";
data <= B"11100111";
ready <= '1', '0' after 10 ns;
wait for 2.7 us - now;
wr <= '1', '0' after 10 ns;
io <= '1', '0' after 10 ns;
address <= X"0007";
data <= X"00";
ready <= '1', '0' after 10 ns;
wait;
end process stimulus;
end architecture test;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity BlockRamScore is
Port (
Clock : in STD_LOGIC;
Texture : in STD_LOGIC_VECTOR (3 downto 0);
Row : in STD_LOGIC_VECTOR (4 downto 0);
Column : in STD_LOGIC_VECTOR (4 downto 0);
DataOutPixel : out STD_LOGIC
);
end BlockRamScore;
architecture Behavioral of BlockRamScore is
component ScoreAndRowToAddr
Port (
Texture : in STD_LOGIC_VECTOR (3 downto 0);
Row : in STD_LOGIC_VECTOR (4 downto 0);
AddressOut : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component MemScore
PORT (
a : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clk : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
end component;
component Reg5
Port (
Clock : in STD_LOGIC;
ColumnIn : in STD_LOGIC_VECTOR (4 downto 0);
ColumnOut : out STD_LOGIC_VECTOR (4 downto 0)
);
end component;
component ToPixelScore
Port (
DataIn : in STD_LOGIC_VECTOR (11 downto 0);
Column : in STD_LOGIC_VECTOR (4 downto 0);
PixelOut : out STD_LOGIC
);
end component;
signal AddressOut_signal : std_logic_vector(7 downto 0);
signal MemOut_signal : std_logic_vector(11 downto 0);
signal ColumnOut_signal : std_logic_vector(4 downto 0);
begin
ScoreToAddr:ScoreAndRowToAddr
port map(Texture => Texture,
Row => Row,
AddressOut => AddressOut_signal);
CoreScore:MemScore
port map(a => AddressOut_signal,
clk => Clock,
spo => MemOut_signal);
Register5:Reg5
port map(Clock => Clock,
ColumnIn => Column,
ColumnOut => ColumnOut_signal);
ToPixel:ToPixelScore
port map(DataIn => MemOut_signal,
Column => ColumnOut_signal,
PixelOut => DataOutPixel);
end Behavioral;
|
library ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY boothmul_pipelined IS
generic (N : integer := 8);
PORT(
Clock : in std_logic;
Reset : in std_logic;
sign : in std_logic;
A : IN std_logic_vector (N-1 downto 0);
B : IN std_logic_vector (N-1 downto 0);
P : OUT std_logic_vector (2*N-1 downto 0)
);
END boothmul_pipelined;
architecture BEHAVIOR of boothmul_pipelined is
component booth_encoder
PORT(
B_in : IN std_logic_vector (2 downto 0);
A_out : OUT std_logic_vector (2 downto 0)
);
end component;
component mux8to1_gen
generic ( M : integer := 64);
PORT(
A : IN std_logic_vector (M-1 downto 0);
B : IN std_logic_vector (M-1 downto 0);
C : IN std_logic_vector (M-1 downto 0);
D : IN std_logic_vector (M-1 downto 0);
E : IN std_logic_vector (M-1 downto 0);
F : IN std_logic_vector (M-1 downto 0);
G : IN std_logic_vector (M-1 downto 0);
H : IN std_logic_vector (M-1 downto 0);
S : IN std_logic_vector (2 downto 0);
Y : OUT std_logic_vector (M-1 downto 0)
);
end component;
component RCA
generic (M : integer := 64
);
Port ( A : In std_logic_vector(M-1 downto 0);
B : In std_logic_vector(M-1 downto 0);
S : Out std_logic_vector(M-1 downto 0)
);
end component;
signal b_enc : std_logic_vector(N downto 0);
signal last_enc : std_logic_vector(2 downto 0);
signal zeros : std_logic_vector(2*N-1 downto 0);
type mux_select is array (N/2 downto 0) of std_logic_vector(2 downto 0);
type mux_in is array (4 downto 0) of std_logic_vector (2*N-1 downto 0);
type tot_in is array (N/2 downto 0) of mux_in;
type tot_out is array (N/2 downto 0) of std_logic_vector (2*N-1 downto 0);
type tot_out_reg is array (N/2 downto 0) of tot_out;
type tot_sum is array (N/2 downto 0) of std_logic_vector (2*N-1 downto 0);
signal tot_mux_in : tot_in;
signal tot_mux_out : tot_out;
signal tot_mux_out_reg : tot_out_reg;
signal tot_select : mux_select;
signal mux_ini : mux_in;
signal mux_out0 : std_logic_vector (2*N-1 downto 0);
signal mux_outi : std_logic_vector (2*N-1 downto 0);
signal sum : tot_sum;
signal next_sum : tot_sum;
signal extend : std_logic;
signal Cin : std_logic;
signal Cout : std_logic;
type not_type is array (N/2 downto 0) of std_logic_vector ( 2*N-1 downto 0);
signal notmuxA : not_type;
signal notmux2A : not_type;
BEGIN
--TODO: add comments
b_enc <= B &'0';
zeros <= (others => '0');
extend <= sign;
last_enc <= sign&sign&B(N-1);
Cin <= '0';
P <= sum(N/2-1);
encod_loop: for i in 0 to N/2 generate
en_level0 : IF i = 0 generate
encod_0 : booth_encoder port map(b_enc(2 downto 0), tot_select(i));
end generate en_level0;
en_levelN : IF i = N/2 generate
encod_i : booth_encoder port map(last_enc, tot_select(i));
end generate en_levelN;
en_leveli : IF i > 0 and i < N/2 generate
encod_i : booth_encoder port map(B(2*i+1 downto 2*i-1), tot_select(i));
end generate en_leveli;
end generate encod_loop;
in_mu : for i in 0 to N/2 generate
mlevel_0 : IF i = 0 generate
tot_mux_in(i)(0) <= (others => '0' );
tot_mux_in(i)(1)(2*N-1 downto N) <= (others => ('0'OR A(N-1)) and extend); -- take sign of A (last bit and extend)
tot_mux_in(i)(1)(N-1 downto 0) <= A; --lowest 16 bits are A
--notmuxA is A flipped (twos complement)
notmuxA(i)(2*N-1 downto N) <= (others => ('0'OR A(N-1)) and extend);
notmuxA(i)(N-1 downto 0) <= A;
tot_mux_in(i)(2) <= std_logic_vector(signed(NOT(notmuxA(i))) + 1);
tot_mux_in(i)(3)(2*N-1 downto N+1) <= (others => ('0'OR A(N-1)) and extend);
tot_mux_in(i)(3)(N downto 1) <= A;
tot_mux_in(i)(3)(0 downto 0) <= (others => '0');
notmux2A(i)(2*N-1 downto N+1) <= (others => ('0'OR A(N-1)) and extend);
notmux2A(i)(N downto 1) <= A;
notmux2A(i)(0 downto 0) <= (others => '0');
tot_mux_in(i)(4) <= std_logic_vector(signed(NOT(notmux2A(i))) + 1);
end generate mlevel_0;
mlevel_N : IF i = N/2 generate
tot_mux_in(i)(0) <= (others => '0');
tot_mux_in(i)(1)(2*N-1 downto N+2*i) <= (others => ('0'OR A(N-1)) and extend);
tot_mux_in(i)(1)(N+2*i-1 downto 2*i) <= A;
tot_mux_in(i)(1)(2*i-1 downto 0) <= (others => '0');
end generate mlevel_N;
mlevel_i : IF i > 0 and i < N/2 generate
tot_mux_in(i)(0) <= (others => '0');
tot_mux_in(i)(1)(2*N-1 downto N+2*i) <= (others => ('0'OR A(N-1)) and extend);
tot_mux_in(i)(1)(N+2*i-1 downto 2*i) <= A;
tot_mux_in(i)(1)(2*i-1 downto 0) <= (others => '0');
notmuxA(i)(2*N-1 downto N+2*i) <= (others => ('0'OR A(N-1)) and extend);
notmuxA(i)(N+2*i-1 downto 2*i) <= A;
notmuxA(i)(2*i-1 downto 0) <= (others => '0');
tot_mux_in(i)(2) <= std_logic_vector(signed(NOT(notmuxA(i))) + 1);
tot_mux_in(i)(3)(2*N-1 downto N+1+2*i) <= (others => ('0'OR A(N-1)) and extend);
tot_mux_in(i)(3)(N+2*i downto 2*i+1) <= A;
tot_mux_in(i)(3)(2*i downto 0) <= (others => '0');
notmux2A(i)(2*N-1 downto N+1+2*i) <= (others => ('0'OR A(N-1)) and extend);
notmux2A(i)(N+2*i downto 2*i+1) <= A;
notmux2A(i)(2*i downto 0) <= (others => '0');
tot_mux_in(i)(4) <= std_logic_vector(signed(NOT(notmux2A(i))) + 1);
end generate mlevel_i;
end generate in_mu;
mux_loop: for i in 0 to N/2 generate
mux_i : mux8to1_gen
generic map (M => 2*N)
-- TODO:fix this with a proper port map
port map (tot_mux_in(i)(0), tot_mux_in(i)(1), tot_mux_in(i)(2), tot_mux_in(i)(3), tot_mux_in(i)(4), zeros, zeros, zeros, tot_select(i), tot_mux_out_reg(0)(i));
end generate mux_loop;
sum_loop: for i in 0 to N/2-1 generate
level_0 : IF i = 0 generate
sum1 : rca
generic map (M => 2*N)
port map(tot_mux_out_reg(0)(0),tot_mux_out_reg(0)(1), next_sum(i));
end generate level_0;
level_i : IF i > 0 generate
sum_i : rca
generic map (M => 2*N)
port map(sum(i-1), tot_mux_out_reg(i)(i+1), next_sum(i));
end generate level_i;
end generate sum_loop;
process(Reset,Clock)
begin
if Reset = '1' then
for i in 0 to N/2 loop
sum(i) <= (others => '0');
-- tot_mux_out_reg(0)(i) <= (others => '0');
end loop;
else
if Clock = '1' and Clock'event then
for i in 0 to N/2 loop
sum(i) <= next_sum(i);
end loop;
tot_mux_out_reg(1) <= tot_mux_out_reg(0);
tot_mux_out_reg(2) <= tot_mux_out_reg(1);
tot_mux_out_reg(3) <= tot_mux_out_reg(2);
tot_mux_out_reg(4) <= tot_mux_out_reg(3);
tot_mux_out_reg(5) <= tot_mux_out_reg(4);
tot_mux_out_reg(6) <= tot_mux_out_reg(5);
tot_mux_out_reg(7) <= tot_mux_out_reg(6);
tot_mux_out_reg(8) <= tot_mux_out_reg(7);
end if;
end if;
end process;
end BEHAVIOR;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
use work.iface.all;
use work.amba.all;
-- Version with stereo and 16 bits on each channel
-- Record function disabled
-- 20.02.02 LA
entity ddm is
port (
rst : in std_logic;
clk : in clk_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ddmi : in ddm_in_type;
ddmo : out ddm_out_type;
irq : out std_logic
);
end;
architecture rtl of ddm is
type ddmregs is record
-- ***********************
-- memory mapped registers
-- bit 0 of 0x80000200
audioenreq : std_logic; -- audio function enabled active
-- bit 1 of 0x80000200
recorden : std_logic; -- audio record '1' or playback '1'
-- bit 2 of 0x80000200
loopen : std_logic; -- enable loop mode;
-- bit 3 of 0x80000200
irqen : std_logic; -- enable interrupt
-- bit 4 of 0x80000200
irq : std_logic; -- irq request
-- 32 bit at 0x80000204
startaddr : std_logic_vector(31 downto 0); -- dma transfer start address
-- 32 bit at 0x80000208
stopaddr : std_logic_vector(31 downto 0); -- dma transfer stop address
-- 14 bit at 0x8000020c
scalerup : std_logic_vector(13 downto 0); -- scaler update register value
-- masterclock / (sampling frequenz * 20*2)
-- lowest 8 bit of 0x80000210
display : std_logic_vector(7 downto 0); -- value to be displayed on the 2
-- digit display
-- bit 9 of 0x80000210
dispen : std_logic; -- enable display on board
-- bit 0-4 of 0x80000214
button0 : std_logic; -- status of the buttons
button1 : std_logic;
button2 : std_logic;
button3 : std_logic;
-- 0x80000218
memoryadr : std_logic_vector(31 downto 0); -- actual dma address /read only
-- memory mapped registers end
-- ***************************
-- internal registers
audioen : std_logic;
dmatransfreq : std_logic;
audiobuffer : std_logic_vector(31 downto 0); -- audio data buffer for
-- memory transfers
shiftcounter : std_logic_vector(4 downto 0); -- counter for 16 bit shiftregister in this version LA
audioshifter : std_logic_vector(15 downto 0); -- serial shift register for
-- audio a/d and d/a converter
instopaddr: std_logic_vector(31 downto 0); -- Internal stop address. It is
-- write each time the function
-- is enabled.
-- changed for 16 bits LA
shifttick : std_logic; -- tick from serial 5 bit (from 20 bit shift
-- register) counter
readaudio_clk: std_logic;
shiftstop : std_logic; -- set for the 12 bit not shifted
lrsel : std_logic; -- left/right output selector
masterclk : std_logic;
sclk : std_logic;
audioout : std_logic; -- 1 bit audio output to d/a converter
digit0 : std_logic_vector(6 downto 0);
digit1 : std_logic_vector(6 downto 0);
-- amba status registers
busact : std_logic;
busown : std_logic;
busgrant : std_logic;
busown2cyc : std_logic;
end record;
type timer is record
scaler : std_logic_vector(13 downto 0);
masterclk : std_logic;
sclkscaler : std_logic_vector(1 downto 0); -- shiftclk generator
sclk : std_logic; -- shiftclk output
sclk_old : std_logic; -- old status of shiftclk for signal
-- change recognition
end record;
signal r,rin : ddmregs;
signal timerout,timerin : timer;
begin
ddmtop : process(rst,r, apbi, ahbi, ddmi, timerout)
variable rdata : std_logic_vector(31 downto 0);
variable tmp: ddmregs;
variable regaddr : std_logic_vector(4 downto 0):="10000";
-- amba ahb variables
variable haddr : std_logic_vector(31 downto 0):=(others => '0'); -- address bus
variable htrans : std_logic_vector(1 downto 0):="00"; -- transfer type
variable hwrite : std_logic:='0'; -- read/write
variable hsize : std_logic_vector(2 downto 0):="000"; -- transfer size
variable hburst : std_logic_vector(2 downto 0):="000"; -- burst type
variable hwdata : std_logic_vector(31 downto 0):=(others => '0'); -- write data
variable hbusreq : std_logic:='0'; -- bus request
begin
-- init
tmp:=r;
hbusreq := '0';
-- read/write memory mapped registers witch amba apb bus
rdata := (others => '0'); -- init
case apbi.paddr(4 downto 2) is
when "000" =>
rdata(0) := r.audioen or r.audioenreq;
rdata(1) := r.recorden;
rdata(2) := r.loopen;
rdata(3) := r.irqen;
rdata(4) := r.irq;
when "001" =>
rdata := r.startaddr;
when "010" =>
rdata := r.stopaddr;
when "011" =>
rdata(13 downto 0) := r.scalerup;
when "100" =>
rdata(7 downto 0) := r.display;
rdata(8) := r.dispen;
when "101" =>
rdata(0) := r.button0;
rdata(1) := r.button1;
rdata(2) := r.button2;
rdata(3) := r.button3;
when "110" =>
rdata := r.memoryadr;
when others => null;
end case;
if (apbi.psel and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(4 downto 2) is
when "000" =>
tmp.audioenreq := apbi.pwdata(0);
tmp.recorden := apbi.pwdata(1);
tmp.loopen := apbi.pwdata(2);
tmp.irqen := apbi.pwdata(3);
if apbi.pwdata(4)='0' then -- allow only interrupt reset
tmp.irq := '0';
end if;
if tmp.audioenreq = '1' and r.audioenreq = '0' then -- init audio transaction
tmp.memoryadr := r.startaddr;
tmp.instopaddr := r.stopaddr;
if tmp.recorden = '0' then -- load first audio data when play back
tmp.dmatransfreq := '1';
end if;
end if;
when "001" =>
tmp.startaddr := apbi.pwdata;
when "010" =>
tmp.stopaddr := apbi.pwdata;
when "011" =>
tmp.scalerup := apbi.pwdata(13 downto 0);
when "100" =>
tmp.display := apbi.pwdata(7 downto 0);
tmp.dispen := apbi.pwdata(8);
when others => null;
end case;
end if;
-- update buttonreg
tmp.button0 := ddmi.button0;
tmp.button1 := ddmi.button1;
tmp.button2 := ddmi.button2;
tmp.button3 := ddmi.button3;
-- decode display input to digits
case r.display(3 downto 0) is
when "0000" =>
tmp.digit0 := "1110111";
when "0001" =>
tmp.digit0 := "0100100";
when "0010" =>
tmp.digit0 := "1011101";
when "0011" =>
tmp.digit0 := "1101101";
when "0100" =>
tmp.digit0 := "0101110";
when "0101" =>
tmp.digit0 := "1101011";
when "0110" =>
tmp.digit0 := "1111011";
when "0111" =>
tmp.digit0 := "0100111";
when "1000" =>
tmp.digit0 := "1111111";
when "1001" =>
tmp.digit0 := "1101111";
when "1010" =>
tmp.digit0 := "0111111";
when "1011" =>
tmp.digit0 := "1111010";
when "1100" =>
tmp.digit0 := "1010011";
when "1101" =>
tmp.digit0 := "1111100";
when "1110" =>
tmp.digit0 := "1011011";
when "1111" =>
tmp.digit0 := "0011011";
when others => null;
end case;
case r.display(7 downto 4) is
when "0000" =>
tmp.digit1 := "1110111";
when "0001" =>
tmp.digit1 := "0100100";
when "0010" =>
tmp.digit1 := "1011101";
when "0011" =>
tmp.digit1 := "1101101";
when "0100" =>
tmp.digit1 := "0101110";
when "0101" =>
tmp.digit1 := "1101011";
when "0110" =>
tmp.digit1 := "1111011";
when "0111" =>
tmp.digit1 := "0100111";
when "1000" =>
tmp.digit1 := "1111111";
when "1001" =>
tmp.digit1 := "1101111";
when "1010" =>
tmp.digit1 := "0111111";
when "1011" =>
tmp.digit1 := "1111010";
when "1100" =>
tmp.digit1 := "1010011";
when "1101" =>
tmp.digit1 := "1111100";
when "1110" =>
tmp.digit1 := "1011011";
when "1111" =>
tmp.digit1 := "0011011";
when others => null;
end case;
-- audio in/out
tmp.masterclk:=timerout.masterclk;
tmp.sclk :=timerout.sclk;
-- audio shifter out/in
if (timerout.sclk='1') and (timerout.sclk_old='0') then
tmp.shiftcounter := tmp.shiftcounter+1;
tmp.shifttick := r.shiftcounter(4) and not tmp.shiftcounter(4);
-- if tmp.shiftcounter="10100" then -- stop shifting after 20 bit
if tmp.shiftcounter="10000" then -- stop shifting after 16 bit LA
tmp.shiftstop :='1';
end if;
-- audio shifregister to buffer update and vice versa
if (tmp.shifttick ='1') and (r.shifttick= '0') then -- all 32 data bits
tmp.lrsel:=not r.lrsel; -- change left/right channel
-- if tmp.lrsel = '1' then -- only transmit data to or from memory when audio is on for one phase
-- ^this line was disabled. The difference between left and right channels is inner,
-- when audioshifter is assigned
if r.audioen='1' then
if r.recorden = '1' then -- if record shiftreg to buffer
-- saving data from audioshifter for two channels LA
if tmp.lrsel='1' then -- LA
tmp.audiobuffer(15 downto 0) := tmp.audioshifter; -- save record
end if; -- data from
if tmp.lrsel='0' then -- LA
tmp.audiobuffer(31 downto 16) := tmp.audioshifter; -- save record
end if; -- data from
-- shiftregister
-- in buffer
tmp.dmatransfreq := '1'; -- start dma transfer action for
-- recording
else
-- tmp.audioshifter := r.audiobuffer(19 downto 0); -- else load new audio data
if tmp.lrsel='1' then -- LA
tmp.audioshifter := r.audiobuffer(15 downto 0); -- else load new audio data for 16 bits
end if;
if tmp.lrsel='0' then -- LA
tmp.audioshifter := r.audiobuffer(31 downto 16); -- else load new audio data for 16 bits
end if;
end if;
end if;
tmp.audioen:=tmp.audioenreq; -- enable audio if requested
if tmp.audioen='1' and tmp.recorden='0'and tmp.lrsel = '1' then -- loads only a word per clock LA
tmp.dmatransfreq:='1'; -- load data for playback from memory
end if;
-- else
tmp.shiftstop:='0'; -- start shifting
-- end if;
end if;
if r.audioen ='1' then
hburst := HBURST_SINGLE;
hsize := HSIZE_WORD;
if r.recorden = '1' then
if tmp.shiftstop='0' then
tmp.readaudio_clk:='1';
else
tmp.audioout := '0';
end if;
else
if tmp.shiftstop='0' then
-- tmp.audioout := tmp.audioshifter(19);
-- tmp.audioshifter := tmp.audioshifter(18 downto 0) & '0';
tmp.audioout := tmp.audioshifter(15); -- 16 bits version LA
tmp.audioshifter := tmp.audioshifter(14 downto 0) & '0';
else
tmp.audioout:='0';
end if;
end if;
else
tmp.audioout:='0';
tmp.audioshifter := (others => '0');
tmp.busown:='0';
tmp.busown2cyc:='0';
end if;
end if;
-- audio data must be read one clk later as mclk is generated
if r.readaudio_clk='1' then
tmp.readaudio_clk:='0';
tmp.audioshifter := tmp.audioshifter(14 downto 0) & ddmi.audioin; -- 16 bits LA
tmp.audioout:=ddmi.audioin;
end if;
-- audio shifregister to buffer update and vice versa
-- dma/amba ahb activity (master)
-- start ahb action
if r.dmatransfreq = '1' then -- request bus for action
hbusreq := '1';
end if;
-- check for bus ownership
tmp.busgrant := ahbi.hgrant;
if tmp.busgrant = '1' and r.dmatransfreq = '1' then
tmp.busact := '1'; -- bus granted and requested
htrans := HTRANS_NONSEQ;
else
tmp.busact := '0'; -- bus granted but not requested
htrans := HTRANS_IDLE; -- do nothing if granted without request
end if;
if (tmp.busact = '1') and (ahbi.hready= '1') then -- bus active
tmp.busown:='1'; -- bus owner at next clock
tmp.dmatransfreq := '0';
end if;
-- control and address cycle of ahb transfer
if r.busown='1' then
htrans := HTRANS_NONSEQ;
haddr := r.memoryadr;
if r.recorden = '1'then
hwrite := '1';
else
hwrite := '0';
end if;
if ahbi.hready='1' then -- check for data cycle
tmp.busown:='0';
tmp.busown2cyc:='1';
end if;
end if;
-- data cycle of ahb transfer
if r.busown2cyc='1' then
if r.recorden = '1'then
hwdata:=r.audiobuffer;
end if;
if ahbi.hready='1' then
tmp.busown:='0';
tmp.busown2cyc:='0';
htrans := HTRANS_IDLE;
tmp.memoryadr := r.memoryadr+4; -- next memory address
if r.recorden='0' then
tmp.audiobuffer := ahbi.hrdata;
end if;
end if;
end if;
-- check for audio action end
if tmp.memoryadr = r.instopaddr then -- stop address reached ?
if r.loopen = '1' then -- if loopmode activated
tmp.memoryadr := r.startaddr; -- loop mode; begin again at start
tmp.instopaddr := r.stopaddr; -- store actual stop address
else
tmp.audioen := '0'; -- audio task finished , in output
-- mode last sample gets lost
tmp.audioenreq := '0';
tmp.audiobuffer:= (others => '0');
end if;
tmp.irq := r.irqen; -- request interrupt when enabled
end if;
-- reset operation of ddm-module
if rst = '0' then
tmp.audiobuffer := (others => '0');
tmp.audioshifter := (others => '0');
tmp.startaddr := (others => '0');
tmp.stopaddr := (others => '0');
tmp.instopaddr := (others => '0');
tmp.memoryadr := (others => '0');
tmp.scalerup := "00000000000001";
tmp.shiftcounter := (others => '0');
tmp.shiftstop := '0';
tmp.shifttick := '0';
tmp.audioen := '0';
tmp.recorden := '0';
tmp.loopen := '0';
tmp.irqen := '0';
tmp.irq := '0';
tmp.display := (others => '0');
tmp.dmatransfreq := '0';
tmp.lrsel := '0';
tmp.dispen := '0';
tmp.busown := '0';
tmp.busown2cyc := '0';
tmp.busact := '0';
tmp.readaudio_clk:='0';
tmp.audioout:='0';
end if;
-- update registers
rin <= tmp;
-- output from ddm to ambabus and outworld
ddmo.digit0 <= r.digit0;
ddmo.digit1 <= r.digit1;
ddmo.audioout <= r.audioout;
ddmo.lr_out <= r.lrsel;
ddmo.shift_clk <= not r.sclk;
ddmo.dispen <= r.dispen;
ddmo.mclk <= r.masterclk;
irq <= r.irq;
apbo.prdata <= rdata;
ahbo.haddr <= haddr;
ahbo.htrans <= htrans;
ahbo.hbusreq <= hbusreq;
ahbo.hwdata <= hwdata;
ahbo.hlock <= '0';
ahbo.hwrite <= hwrite;
ahbo.hsize <= hsize;
ahbo.hburst <= hburst;
ahbo.hprot <= (others => '0');
end process;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
timerout <= timerin;
end if;
end process;
timerpr : process(timerout, rst)
variable scaler : std_logic_vector(13 downto 0);
variable masterclk : std_logic;
variable tick : std_logic;
variable rscaler : std_logic_vector(1 downto 0);
variable sclk: std_logic;
-- scaler update
begin
if rst = '1' then
sclk:= timerout.sclk;
scaler := timerout.scaler-1;
masterclk := timerout.masterclk;
tick := scaler(13) and not timerout.scaler(13);
rscaler := timerout.sclkscaler;
if tick = '1' then
scaler := r.scalerup;
masterclk := not timerout.masterclk;
rscaler := rscaler+1; -- generating shiftclk
if ((not rscaler(0)) and (not rscaler(1)))='1' then
sclk := not sclk;
end if;
end if;
-- audio shiftclk generation
timerin.sclkscaler <= rscaler;
timerin.sclk_old <= timerout.sclk;
timerin.scaler <= scaler;
timerin.masterclk <= masterclk;
timerin.sclk <= sclk;
else
timerin.sclkscaler <= "00"; --reset
timerin.sclk_old <= '0';
timerin.sclk <= '0';
timerin.scaler <= "00000000000001";
timerin.masterclk <= '0';
end if;
end process;
end;
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 26-04-2016
-- Module Name: p12.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity drawstring is
port (p1, p2 : in std_logic;
clk, reset : in std_logic;
led : out std_logic_vector (9 downto 1));
end entity;
architecture rtl of drawstring is
type state is (led1, led2, led3, led4, led5, led6, led7, led8, led9);
signal current_state, next_state : state := led5;
begin
process (clk, reset)
begin
if reset = '1' then
current_state <= led5;
elsif clk'event and clk = '1' then
current_state <= next_state;
end if;
end process;
process (current_state, p1, p2)
begin
case current_state is
when led1 =>
if p1'event and p1 = '1' then
next_state <= led2;
elsif p2'event and p2 = '1' then
next_state <= led1;
end if;
when led2 =>
if p1'event and p1 = '1' then
next_state <= led3;
elsif p2'event and p2 = '1' then
next_state <= led1;
end if;
when led3 =>
if p1'event and p1 = '1' then
next_state <= led4;
elsif p2'event and p2 = '1' then
next_state <= led2;
end if;
when led4 =>
if p1'event and p1 = '1' then
next_state <= led5;
elsif p2'event and p2 = '1' then
next_state <= led3;
end if;
when led5 =>
if p1'event and p1 = '1' then
next_state <= led6;
elsif p2'event and p2 = '1' then
next_state <= led4;
end if;
when led6 =>
if p1'event and p1 = '1' then
next_state <= led7;
elsif p2'event and p2 = '1' then
next_state <= led5;
end if;
when led7 =>
if p1'event and p1 = '1' then
next_state <= led8;
elsif p2'event and p2 = '1' then
next_state <= led6;
end if;
when led8 =>
if p1'event and p1 = '1' then
next_state <= led9;
elsif p2'event and p2 = '1' then
next_state <= led7;
end if;
when led9 =>
if p1'event and p1 = '1' then
next_state <= led9;
elsif p2'event and p2 = '1' then
next_state <= led8;
end if;
end case;
end process;
process (current_state)
begin
case current_state is
when led1 => led <= (1 => '1', others => '0');
when led2 => led <= (2 => '1', others => '0');
when led3 => led <= (3 => '1', others => '0');
when led4 => led <= (4 => '1', others => '0');
when led5 => led <= (5 => '1', others => '0');
when led6 => led <= (6 => '1', others => '0');
when led7 => led <= (7 => '1', others => '0');
when led8 => led <= (8 => '1', others => '0');
when led9 => led <= (9 => '1', others => '0');
end case;
end process;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity blockPHfinding is
port (clk_i : in std_logic;
reset_i : in std_logic;
framing_i : in std_logic;
block_o : out std_logic);
end blockPHfinding;
architecture rtl of blockPHfinding is
type t_state is (waiting,
tick1,
tick2,
tick3,
tick4);
signal s_state : t_state;
begin
p_monoflop: process (clk_i, reset_i)
begin -- process p_serin
if (reset_i = '1') then -- asynchronous reset
block_o <= '0';
s_state <= waiting;
elsif rising_edge(clk_i) then -- rising clock edge
case s_state is
-------------------------------------------------------------------------
when tick1 =>
block_o <= '1';
s_state <= tick2 ;
-------------------------------------------------------------------------
when tick2 =>
block_o <= '1';
s_state <= tick3 ;
-------------------------------------------------------------------------
when tick3 =>
block_o <= '1';
s_state <= tick4 ;
-------------------------------------------------------------------------
when tick4 =>
block_o <= '1';
s_state <= waiting ;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
when others =>
if framing_i = '1' then
s_state <= tick1;
else
block_o <= '0';
s_state <= waiting;
end if;
end case;
end if;
end process p_monoflop;
end rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity blockPHfinding is
port (clk_i : in std_logic;
reset_i : in std_logic;
framing_i : in std_logic;
block_o : out std_logic);
end blockPHfinding;
architecture rtl of blockPHfinding is
type t_state is (waiting,
tick1,
tick2,
tick3,
tick4);
signal s_state : t_state;
begin
p_monoflop: process (clk_i, reset_i)
begin -- process p_serin
if (reset_i = '1') then -- asynchronous reset
block_o <= '0';
s_state <= waiting;
elsif rising_edge(clk_i) then -- rising clock edge
case s_state is
-------------------------------------------------------------------------
when tick1 =>
block_o <= '1';
s_state <= tick2 ;
-------------------------------------------------------------------------
when tick2 =>
block_o <= '1';
s_state <= tick3 ;
-------------------------------------------------------------------------
when tick3 =>
block_o <= '1';
s_state <= tick4 ;
-------------------------------------------------------------------------
when tick4 =>
block_o <= '1';
s_state <= waiting ;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
when others =>
if framing_i = '1' then
s_state <= tick1;
else
block_o <= '0';
s_state <= waiting;
end if;
end case;
end if;
end process p_monoflop;
end rtl;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Uy+/bAvDW2ToQF5miV8H9GwSL+PQ6TS8muqM9gHVNDlSpfz75P/vOGkhPJrDbUaPwDByMk3k3JW3
myuGSoygBw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
e1EemWqX9CWadook2ifd/61jXvbyF3yTOqC/mN/QysJdnZdoVBcGh5HZH+uQuR+LBK1jFI+sVkoH
xfWgMH/fhkTKG4zcQ1Zy0Ueg6Vp/xrtL4I3VGcxcIP2l/JBAOL5TxY2el2Ty56j3B0jGzlZzmYQf
2+l07yoeGygtKP6QBjk=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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482YnfM+dHFYlcS8o6yrgzLsFVv8O/L5GJ789A==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
QHbSWkv9TEL02YdHjUSVOS3T1I2yEWF7BIyIfTd1hJ5trJ6V6UsqCi1p1RMhfY0hxQfDbNraBna+
H3A3llmi/8BjAsXtY4s6ZyzbFm5RL6DIdqfEw4weiOjkzBJXXfyekA58E4msFUsA37NrlAms0J2q
l8VSXmATW7oZq9aYiss=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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pa8v4aWmLB4zxY6BpaR9GOllTUV8lirakEkr4Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4992)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Uy+/bAvDW2ToQF5miV8H9GwSL+PQ6TS8muqM9gHVNDlSpfz75P/vOGkhPJrDbUaPwDByMk3k3JW3
myuGSoygBw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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2+l07yoeGygtKP6QBjk=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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l8VSXmATW7oZq9aYiss=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
XkVsXlpUckKM9S3I7MZ8m+mkvml+IMF1LrgShoCiNuRh1b5UdLKBOxq3UtErV3Al3WXt+vkFwVBZ
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pa8v4aWmLB4zxY6BpaR9GOllTUV8lirakEkr4Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4992)
`protect data_block
224gadEcRed2Ta56vYjUjudKgAN87QAKph+56WWOBBeqvYG1d0GsBHKHpspuELx/tuHaSKVcKg9S
5K97ohvTnmUGC+Bw/h1nPjrXdEdExNVUeE3y5DEfZcaRDX3PqMSaoZ2GIoi3BKszi+vwdgCq9Wbd
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|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Core_tb is
end Core_tb;
architecture behavior of Core_tb is
component Core
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
LFXT_Clk_i : in std_logic;
Cpu_En_i : in std_logic;
Dbg_En_i : in std_logic;
-- Dbg_UART_RxD_i : in std_logic;
-- Dbg_UART_TxD_o : out std_logic;
Dbg_SCL_i : in std_logic;
Dbg_SDA_Out_o : out std_logic;
Dbg_SDA_In_i : in std_logic;
P1_DOut_o : out std_logic_vector(7 downto 0);
P1_En_o : out std_logic_vector(7 downto 0);
P1_DIn_i : in std_logic_vector(7 downto 0);
P2_DOut_o : out std_logic_vector(7 downto 0);
P2_En_o : out std_logic_vector(7 downto 0);
P2_DIn_i : in std_logic_vector(7 downto 0);
UartRxD_i : in std_logic;
UartTxD_o : out std_logic;
SCK_o : out std_logic;
MOSI_o : out std_logic;
MISO_i : in std_logic;
Inputs_i : in std_logic_vector(7 downto 0);
Outputs_o : out std_logic_vector(7 downto 0);
SPIMISO_i : in std_logic;
SPIMOSI_o : out std_logic;
SPISCK_o : out std_logic;
I2CSCL_o : out std_logic;
I2CSDA_i : in std_logic;
I2CSDA_o : out std_logic;
-- OneWire_i : in std_logic;
-- OneWire_o : out std_logic;
-- PWMInput_i : in std_logic;
-- SENTInput_i : in std_logic;
-- SPCInput_i : in std_logic;
-- SPCTrigger_o : out std_logic;
AdcConvComplete_i : in std_logic;
AdcDoConvert_o : out std_logic;
AdcValue_i : in std_logic_vector(9 downto 0));
end component;
component MAX6682_Model
port (
ChipSelect_n_i : in std_logic;
SCLK_i : in std_logic;
SO_o : out std_logic;
Value_i : in std_logic_vector(10 downto 0)
);
end component;
component ExtNames
port (
SPIFSM_Done : out std_logic;
CpuIntr : out std_logic;
SensorValue : out std_logic_vector(15 downto 0);
Enable : out std_logic
);
end component;
-- Reset
signal Reset_n_i : std_logic := '0';
-- Clock
signal Clk_i : std_logic := '1';
signal LFXT_Clk_i : std_logic;
signal Cpu_En_i : std_logic := '1';
signal Dbg_En_i : std_logic;
-- signal Dbg_UART_RxD_i : std_logic;
-- signal Dbg_UART_TxD_o : std_logic;
signal Dbg_SCL_i : std_logic;
signal Dbg_SDA_Out_o : std_logic;
signal Dbg_SDA_In_i : std_logic;
signal P1_DOut_o : std_logic_vector(7 downto 0);
signal P1_En_o : std_logic_vector(7 downto 0);
signal P1_DIn_i : std_logic_vector(7 downto 0);
signal P2_DOut_o : std_logic_vector(7 downto 0);
signal P2_En_o : std_logic_vector(7 downto 0);
signal P2_DIn_i : std_logic_vector(7 downto 0);
signal UartRxD_i : std_logic;
signal UartTxD_o : std_logic;
signal SCK_o : std_logic;
signal MOSI_o : std_logic;
signal MISO_i : std_logic := '0';
signal Inputs_i : std_logic_vector(7 downto 0);
signal Outputs_o : std_logic_vector(7 downto 0);
signal SPIMISO_i : std_logic;
signal SPIMOSI_o : std_logic;
signal SPISCK_o : std_logic;
signal I2CSCL_o : std_logic;
signal I2CSDA_i : std_logic;
signal I2CSDA_o : std_logic;
-- signal OneWire_i : std_logic;
-- signal OneWire_o : std_logic;
-- signal PWMInput_i : std_logic;
-- signal SENTInput_i : std_logic;
-- signal SPCInput_i : std_logic;
-- signal SPCTrigger_o : std_logic;
signal AdcConvComplete_i : std_logic;
signal AdcDoConvert_o : std_logic;
signal AdcValue_i : std_logic_vector(9 downto 0);
-- look into the ADT7310 app
-- alias SPIFSM_Done_i is << signal .adt7310_tb.DUT.SPIFSM_Done_s : std_logic >>;
-- ModelSim complains here, that the references signal is not a VHDL object.
-- True, this is a Verilog object. As a workaround the module ExtNames is created
-- which uses Verilog hierarchical names to reference the wire and assigns it to
-- an output. This module is instantiated (and it seems ModelSim only adds
-- Verilog<->VHDL signal converters on instance boundaries) and this output is
-- connected with the SPIFSM_Done_i signal.
signal SPIFSM_Done_e : std_logic; -- directly from inside SPI_FSM
signal CpuIntr_e : std_logic; -- directly from inside SPI_FSM
signal SensorValue_e : std_logic_vector(15 downto 0);
signal Enable_e : std_logic; -- directly from inside
-- Using the extracted Yosys FSM we get delta cycles and a glitch on
-- SPIFSM_Done_i. Therefore we generate a slightly delayed version and wait
-- on the ANDed value.
signal SPIFSM_Done_d : std_logic; -- sightly delayed
signal CpuIntr_o : std_logic; -- sightly delayed
signal SensorValue_o : std_logic_vector(15 downto 0); -- sightly delayed
signal Enable_i : std_logic; -- directly from inside
-- MAX6682 component ports
signal MAX6682CS_n_o : std_logic;
constant ClkPeriode : time := 10 ns;
-- MAX6682 simulation
signal MAX6682Value : unsigned(10 downto 0);
begin
DUT: Core
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
LFXT_Clk_i => LFXT_Clk_i,
Cpu_En_i => Cpu_En_i,
Dbg_En_i => Dbg_En_i,
-- Dbg_UART_RxD_i => Dbg_UART_RxD_i,
-- Dbg_UART_TxD_o => Dbg_UART_TxD_o,
Dbg_SCL_i => Dbg_SCL_i,
Dbg_SDA_Out_o => Dbg_SDA_Out_o,
Dbg_SDA_In_i => Dbg_SDA_In_i,
P1_DOut_o => P1_DOut_o,
P1_En_o => P1_En_o,
P1_DIn_i => P1_DIn_i,
P2_DOut_o => P2_DOut_o,
P2_En_o => P2_En_o,
P2_DIn_i => P2_DIn_i,
UartRxD_i => UartRxD_i,
UartTxD_o => UartTxD_o,
SCK_o => SCK_o,
MOSI_o => MOSI_o,
MISO_i => MISO_i,
Inputs_i => Inputs_i,
Outputs_o => Outputs_o,
SPIMISO_i => SPIMISO_i,
SPIMOSI_o => SPIMOSI_o,
SPISCK_o => SPISCK_o,
I2CSCL_o => I2CSCL_o,
I2CSDA_i => I2CSDA_i,
I2CSDA_o => I2CSDA_o,
-- OneWire_i => OneWire_i,
-- OneWire_o => OneWire_o,
-- PWMInput_i => PWMInput_i,
-- SENTInput_i => SENTInput_i,
-- SPCInput_i => SPCInput_i,
-- SPCTrigger_o => SPCTrigger_o,
AdcConvComplete_i => AdcConvComplete_i,
AdcDoConvert_o => AdcDoConvert_o,
AdcValue_i => AdcValue_i
);
MAX6682CS_n_o <= Outputs_o(0);
Inputs_i <= (others => '0');
P1_DIn_i <= (others => '0');
P2_DIn_i <= (others => '0');
ExtNames_1: ExtNames
port map (
SPIFSM_Done => SPIFSM_Done_e,
CpuIntr => CpuIntr_e,
SensorValue => SensorValue_e,
Enable => Enable_e
);
SPIFSM_Done_d <= SPIFSM_Done_e after 1.0 ns;
CpuIntr_o <= CpuIntr_e after 1.0 ns;
SensorValue_o <= SensorValue_e after 1.0 ns;
Enable_i <= Enable_e after 1.0 ns;
SPIMISO_i <= 'H';
MAX6682_1: MAX6682_Model
port map (
ChipSelect_n_i => MAX6682CS_n_o,
SCLK_i => SPISCK_o,
SO_o => SPIMISO_i,
Value_i => std_logic_vector(MAX6682Value));
-- Generate clock signal
Clk_i <= not Clk_i after ClkPeriode*0.5;
StimulusProc: process
begin
MAX6682Value <= (others => '0');
wait for 2.2*ClkPeriode;
-- deassert Reset
Reset_n_i <= '1';
-- three cycles with disabled SensorFSM
wait for 3*ClkPeriode;
-- enable SensorFSM
wait until Enable_i = '1';
wait for 9*ClkPeriode; -- 9 cycles
assert MAX6682CS_n_o = '1' report "CS_n should be '1'" severity error;
wait for 1*ClkPeriode; -- 1 cycle
assert MAX6682CS_n_o = '0' report "CS_n should be '0' after 10 cycles" severity error;
wait for 35*ClkPeriode; -- 35 cycles
assert MAX6682CS_n_o = '0' report "CS_n should still be '0'" severity error;
wait for 1*ClkPeriode; -- 1 cycle
assert MAX6682CS_n_o = '1' report "CS_n should be '1' after 16 SPI bits" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
wait for 1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(0,16)) report "SensorValue_o should be 0" severity error;
-- new sensor value: 38 -> large difference -> notify required
wait for 3*ClkPeriode; -- 3 cycle
MAX6682Value <= to_unsigned(38,11);
wait for 43*ClkPeriode; -- 43 cycle
assert MAX6682CS_n_o = '1' report "CS_n should be '1' after 16 SPI bits" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
wait for 1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(38,16)) report "SensorValue_o should be 38" severity error;
wait for 1*ClkPeriode; -- 1 more cycle if notification happened
-- new sensor value: 30 -> small difference -> no notification
wait for 3*ClkPeriode; -- 3 cycle
MAX6682Value <= to_unsigned(30,11);
wait for 43*ClkPeriode; -- 43 cycle
assert MAX6682CS_n_o = '1' report "CS_n should be '1' after 16 SPI bits" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
wait for 1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(38,16)) report "SensorValue_o should be 38" severity error;
-- new sensor value: 28 -> small difference -> no notification
wait for 3*ClkPeriode; -- 3 cycle
MAX6682Value <= to_unsigned(28,11);
wait for 43*ClkPeriode; -- 43 cycle
assert MAX6682CS_n_o = '1' report "CS_n should be '1' after 16 SPI bits" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
wait for 1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(38,16)) report "SensorValue_o should be 38" severity error;
-- new sensor value: 27 -> large difference -> notify required
wait for 3*ClkPeriode; -- 3 cycle
MAX6682Value <= to_unsigned(27,11);
wait for 43*ClkPeriode; -- 43 cycle
assert MAX6682CS_n_o = '1' report "CS_n should be '1' after 16 SPI bits" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
wait for 1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(27,16)) report "SensorValue_o should be 27" severity error;
wait for 1*ClkPeriode; -- 1 more cycle if notification happened
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
wait for 10*ClkPeriode;
-- End of simulation
report "### Simulation Finished ###" severity failure;
wait;
end process StimulusProc;
end behavior;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Core_tb is
end Core_tb;
architecture behavior of Core_tb is
component Core
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
LFXT_Clk_i : in std_logic;
Cpu_En_i : in std_logic;
Dbg_En_i : in std_logic;
-- Dbg_UART_RxD_i : in std_logic;
-- Dbg_UART_TxD_o : out std_logic;
Dbg_SCL_i : in std_logic;
Dbg_SDA_Out_o : out std_logic;
Dbg_SDA_In_i : in std_logic;
P1_DOut_o : out std_logic_vector(7 downto 0);
P1_En_o : out std_logic_vector(7 downto 0);
P1_DIn_i : in std_logic_vector(7 downto 0);
P2_DOut_o : out std_logic_vector(7 downto 0);
P2_En_o : out std_logic_vector(7 downto 0);
P2_DIn_i : in std_logic_vector(7 downto 0);
UartRxD_i : in std_logic;
UartTxD_o : out std_logic;
SCK_o : out std_logic;
MOSI_o : out std_logic;
MISO_i : in std_logic;
Inputs_i : in std_logic_vector(7 downto 0);
Outputs_o : out std_logic_vector(7 downto 0);
SPIMISO_i : in std_logic;
SPIMOSI_o : out std_logic;
SPISCK_o : out std_logic;
I2CSCL_o : out std_logic;
I2CSDA_i : in std_logic;
I2CSDA_o : out std_logic;
-- OneWire_i : in std_logic;
-- OneWire_o : out std_logic;
-- PWMInput_i : in std_logic;
-- SENTInput_i : in std_logic;
-- SPCInput_i : in std_logic;
-- SPCTrigger_o : out std_logic;
AdcConvComplete_i : in std_logic;
AdcDoConvert_o : out std_logic;
AdcValue_i : in std_logic_vector(9 downto 0));
end component;
component MAX6682_Model
port (
ChipSelect_n_i : in std_logic;
SCLK_i : in std_logic;
SO_o : out std_logic;
Value_i : in std_logic_vector(10 downto 0)
);
end component;
component ExtNames
port (
SPIFSM_Done : out std_logic;
CpuIntr : out std_logic;
SensorValue : out std_logic_vector(15 downto 0);
Enable : out std_logic
);
end component;
-- Reset
signal Reset_n_i : std_logic := '0';
-- Clock
signal Clk_i : std_logic := '1';
signal LFXT_Clk_i : std_logic;
signal Cpu_En_i : std_logic := '1';
signal Dbg_En_i : std_logic;
-- signal Dbg_UART_RxD_i : std_logic;
-- signal Dbg_UART_TxD_o : std_logic;
signal Dbg_SCL_i : std_logic;
signal Dbg_SDA_Out_o : std_logic;
signal Dbg_SDA_In_i : std_logic;
signal P1_DOut_o : std_logic_vector(7 downto 0);
signal P1_En_o : std_logic_vector(7 downto 0);
signal P1_DIn_i : std_logic_vector(7 downto 0);
signal P2_DOut_o : std_logic_vector(7 downto 0);
signal P2_En_o : std_logic_vector(7 downto 0);
signal P2_DIn_i : std_logic_vector(7 downto 0);
signal UartRxD_i : std_logic;
signal UartTxD_o : std_logic;
signal SCK_o : std_logic;
signal MOSI_o : std_logic;
signal MISO_i : std_logic := '0';
signal Inputs_i : std_logic_vector(7 downto 0);
signal Outputs_o : std_logic_vector(7 downto 0);
signal SPIMISO_i : std_logic;
signal SPIMOSI_o : std_logic;
signal SPISCK_o : std_logic;
signal I2CSCL_o : std_logic;
signal I2CSDA_i : std_logic;
signal I2CSDA_o : std_logic;
-- signal OneWire_i : std_logic;
-- signal OneWire_o : std_logic;
-- signal PWMInput_i : std_logic;
-- signal SENTInput_i : std_logic;
-- signal SPCInput_i : std_logic;
-- signal SPCTrigger_o : std_logic;
signal AdcConvComplete_i : std_logic;
signal AdcDoConvert_o : std_logic;
signal AdcValue_i : std_logic_vector(9 downto 0);
-- look into the ADT7310 app
-- alias SPIFSM_Done_i is << signal .adt7310_tb.DUT.SPIFSM_Done_s : std_logic >>;
-- ModelSim complains here, that the references signal is not a VHDL object.
-- True, this is a Verilog object. As a workaround the module ExtNames is created
-- which uses Verilog hierarchical names to reference the wire and assigns it to
-- an output. This module is instantiated (and it seems ModelSim only adds
-- Verilog<->VHDL signal converters on instance boundaries) and this output is
-- connected with the SPIFSM_Done_i signal.
signal SPIFSM_Done_e : std_logic; -- directly from inside SPI_FSM
signal CpuIntr_e : std_logic; -- directly from inside SPI_FSM
signal SensorValue_e : std_logic_vector(15 downto 0);
signal Enable_e : std_logic; -- directly from inside
-- Using the extracted Yosys FSM we get delta cycles and a glitch on
-- SPIFSM_Done_i. Therefore we generate a slightly delayed version and wait
-- on the ANDed value.
signal SPIFSM_Done_d : std_logic; -- sightly delayed
signal CpuIntr_o : std_logic; -- sightly delayed
signal SensorValue_o : std_logic_vector(15 downto 0); -- sightly delayed
signal Enable_i : std_logic; -- directly from inside
-- MAX6682 component ports
signal MAX6682CS_n_o : std_logic;
constant ClkPeriode : time := 10 ns;
-- MAX6682 simulation
signal MAX6682Value : unsigned(10 downto 0);
begin
DUT: Core
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
LFXT_Clk_i => LFXT_Clk_i,
Cpu_En_i => Cpu_En_i,
Dbg_En_i => Dbg_En_i,
-- Dbg_UART_RxD_i => Dbg_UART_RxD_i,
-- Dbg_UART_TxD_o => Dbg_UART_TxD_o,
Dbg_SCL_i => Dbg_SCL_i,
Dbg_SDA_Out_o => Dbg_SDA_Out_o,
Dbg_SDA_In_i => Dbg_SDA_In_i,
P1_DOut_o => P1_DOut_o,
P1_En_o => P1_En_o,
P1_DIn_i => P1_DIn_i,
P2_DOut_o => P2_DOut_o,
P2_En_o => P2_En_o,
P2_DIn_i => P2_DIn_i,
UartRxD_i => UartRxD_i,
UartTxD_o => UartTxD_o,
SCK_o => SCK_o,
MOSI_o => MOSI_o,
MISO_i => MISO_i,
Inputs_i => Inputs_i,
Outputs_o => Outputs_o,
SPIMISO_i => SPIMISO_i,
SPIMOSI_o => SPIMOSI_o,
SPISCK_o => SPISCK_o,
I2CSCL_o => I2CSCL_o,
I2CSDA_i => I2CSDA_i,
I2CSDA_o => I2CSDA_o,
-- OneWire_i => OneWire_i,
-- OneWire_o => OneWire_o,
-- PWMInput_i => PWMInput_i,
-- SENTInput_i => SENTInput_i,
-- SPCInput_i => SPCInput_i,
-- SPCTrigger_o => SPCTrigger_o,
AdcConvComplete_i => AdcConvComplete_i,
AdcDoConvert_o => AdcDoConvert_o,
AdcValue_i => AdcValue_i
);
MAX6682CS_n_o <= Outputs_o(0);
Inputs_i <= (others => '0');
P1_DIn_i <= (others => '0');
P2_DIn_i <= (others => '0');
ExtNames_1: ExtNames
port map (
SPIFSM_Done => SPIFSM_Done_e,
CpuIntr => CpuIntr_e,
SensorValue => SensorValue_e,
Enable => Enable_e
);
SPIFSM_Done_d <= SPIFSM_Done_e after 1.0 ns;
CpuIntr_o <= CpuIntr_e after 1.0 ns;
SensorValue_o <= SensorValue_e after 1.0 ns;
Enable_i <= Enable_e after 1.0 ns;
SPIMISO_i <= 'H';
MAX6682_1: MAX6682_Model
port map (
ChipSelect_n_i => MAX6682CS_n_o,
SCLK_i => SPISCK_o,
SO_o => SPIMISO_i,
Value_i => std_logic_vector(MAX6682Value));
-- Generate clock signal
Clk_i <= not Clk_i after ClkPeriode*0.5;
StimulusProc: process
begin
MAX6682Value <= (others => '0');
wait for 2.2*ClkPeriode;
-- deassert Reset
Reset_n_i <= '1';
-- three cycles with disabled SensorFSM
wait for 3*ClkPeriode;
-- enable SensorFSM
wait until Enable_i = '1';
wait for 9*ClkPeriode; -- 9 cycles
assert MAX6682CS_n_o = '1' report "CS_n should be '1'" severity error;
wait for 1*ClkPeriode; -- 1 cycle
assert MAX6682CS_n_o = '0' report "CS_n should be '0' after 10 cycles" severity error;
wait for 35*ClkPeriode; -- 35 cycles
assert MAX6682CS_n_o = '0' report "CS_n should still be '0'" severity error;
wait for 1*ClkPeriode; -- 1 cycle
assert MAX6682CS_n_o = '1' report "CS_n should be '1' after 16 SPI bits" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
wait for 1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(0,16)) report "SensorValue_o should be 0" severity error;
-- new sensor value: 38 -> large difference -> notify required
wait for 3*ClkPeriode; -- 3 cycle
MAX6682Value <= to_unsigned(38,11);
wait for 43*ClkPeriode; -- 43 cycle
assert MAX6682CS_n_o = '1' report "CS_n should be '1' after 16 SPI bits" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
wait for 1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(38,16)) report "SensorValue_o should be 38" severity error;
wait for 1*ClkPeriode; -- 1 more cycle if notification happened
-- new sensor value: 30 -> small difference -> no notification
wait for 3*ClkPeriode; -- 3 cycle
MAX6682Value <= to_unsigned(30,11);
wait for 43*ClkPeriode; -- 43 cycle
assert MAX6682CS_n_o = '1' report "CS_n should be '1' after 16 SPI bits" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
wait for 1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(38,16)) report "SensorValue_o should be 38" severity error;
-- new sensor value: 28 -> small difference -> no notification
wait for 3*ClkPeriode; -- 3 cycle
MAX6682Value <= to_unsigned(28,11);
wait for 43*ClkPeriode; -- 43 cycle
assert MAX6682CS_n_o = '1' report "CS_n should be '1' after 16 SPI bits" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
wait for 1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(38,16)) report "SensorValue_o should be 38" severity error;
-- new sensor value: 27 -> large difference -> notify required
wait for 3*ClkPeriode; -- 3 cycle
MAX6682Value <= to_unsigned(27,11);
wait for 43*ClkPeriode; -- 43 cycle
assert MAX6682CS_n_o = '1' report "CS_n should be '1' after 16 SPI bits" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
wait for 1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(27,16)) report "SensorValue_o should be 27" severity error;
wait for 1*ClkPeriode; -- 1 more cycle if notification happened
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
wait for 10*ClkPeriode;
-- End of simulation
report "### Simulation Finished ###" severity failure;
wait;
end process StimulusProc;
end behavior;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 18/03/2015
--! Module Name: EPROC_OUT8
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee,work;
use ieee.std_logic_1164.all;
use work.all;
--! E-link processor, 8bit output
entity EPROC_OUT8 is
generic (
do_generate : boolean := true;
includeNoEncodingCase : boolean := true
);
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
ENA : in std_logic;
getDataTrig : out std_logic; -- @ bitCLKx4
ENCODING : in std_logic_vector (3 downto 0);
EDATA_OUT : out std_logic_vector (7 downto 0);
TTCin : in std_logic_vector (8 downto 0);
DATA_IN : in std_logic_vector (9 downto 0);
DATA_RDY : in std_logic
);
end EPROC_OUT8;
architecture Behavioral of EPROC_OUT8 is
constant zeros8bit : std_logic_vector (7 downto 0) := (others=>'0');
signal EdataOUT_ENC8b10b_case, EdataOUT_direct_case, EdataOUT_HDLC_case, EdataOUT_TTC3_case, EdataOUT_TTC4_case : std_logic_vector (7 downto 0);
signal rst_s, rst_case000, rst_case001, rst_case010, rst_case011 : std_logic;
signal getDataTrig_ENC8b10b_case, getDataTrig_direct_case, getDataTrig_HDLC_case, getDataTrig_TTC_cases : std_logic;
begin
gen_enabled: if do_generate = true generate
rst_s <= rst or (not ENA);
-------------------------------------------------------------------------------------------
-- case 0: direct data, no delimeter...
-------------------------------------------------------------------------------------------
direct_data_enabled: if includeNoEncodingCase = true generate
rst_case000 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "000")) else '1';
getDataTrig_direct_case <= '1' when (ENCODING(2 downto 0) = "000") else '0';
EdataOUT_direct_case <= DATA_IN(7 downto 0);
end generate direct_data_enabled;
--
direct_data_disabled: if includeNoEncodingCase = false generate
EdataOUT_direct_case <= (others=>'0');
end generate direct_data_disabled;
--
-------------------------------------------------------------------------------------------
-- case 1: DEC8b10b
-------------------------------------------------------------------------------------------
rst_case001 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "001")) else '1';
--
ENC8b10b_case: entity work.EPROC_OUT8_ENC8b10b
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case001,
getDataTrig => getDataTrig_ENC8b10b_case,
edataIN => DATA_IN,
edataINrdy => DATA_RDY,
EdataOUT => EdataOUT_ENC8b10b_case
);
--
-------------------------------------------------------------------------------------------
-- case 2: HDLC
-------------------------------------------------------------------------------------------
rst_case010 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "010")) else '1';
--
getDataTrig_HDLC_case <= '0'; --'1' when (ENCODING(2 downto 0) = "010") else '0';
EdataOUT_HDLC_case <= (others=>'0'); --<---TBD
--
-------------------------------------------------------------------------------------------
-- case 3&4: TTC-3 & TTC-4
-------------------------------------------------------------------------------------------
rst_case011 <= '0' when ((rst_s = '0') and ((ENCODING(2 downto 0) = "011") or (ENCODING(2 downto 0) = "100"))) else '1';
--
getDataTrig_TTC_cases <= '0'; --'1' when ((ENCODING(2 downto 0) = "011") or (ENCODING(2 downto 0) = "100")) else '0';
--
ttc_r: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if rst_case011 = '1' then
EdataOUT_TTC3_case <= zeros8bit;
EdataOUT_TTC4_case <= zeros8bit;
else
EdataOUT_TTC3_case <= TTCin(1) & TTCin(7 downto 2) & TTCin(0);
EdataOUT_TTC4_case <= TTCin(8 downto 2) & TTCin(0);
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- output data and busy according to the encoding settings
-------------------------------------------------------------------------------------------
dataOUTmux: entity work.MUX8_Nbit
generic map (N=>8)
port map(
data0 => EdataOUT_direct_case,
data1 => EdataOUT_ENC8b10b_case,
data2 => EdataOUT_HDLC_case,
data3 => EdataOUT_TTC3_case,
data4 => EdataOUT_TTC4_case,
data5 => zeros8bit,
data6 => zeros8bit,
data7 => zeros8bit,
sel => ENCODING(2 downto 0),
data_out => EDATA_OUT
);
--
getDataTrig <= ENA and (getDataTrig_TTC_cases or getDataTrig_HDLC_case or getDataTrig_ENC8b10b_case or getDataTrig_direct_case);
--
end generate gen_enabled;
--
--
gen_disabled: if do_generate = false generate
EDATA_OUT <= (others=>'0');
getDataTrig <= '0';
end generate gen_disabled;
end Behavioral;
|
entity e is end entity;
architecture a of e is
signal x : bit_vector(1 to 3);
signal y : bit;
begin
-- Test corner case in lexer
-- http://www.eda-stds.org/isac/IRs-VHDL-93/IR1045.txt
x <= bit_vector'('1','0','1');
y <= bit'('1');
end architecture;
|
-- VHDL Entity my_project1_lib.fifo_test.symbol
--
-- Created:
-- by - mg147.bin (srge00.ecn.purdue.edu)
-- at - 18:18:44 04/10/12
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2010.2a (Build 7)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY fifo_test IS
generic(
gregLength : integer := 16;
gregWidth : integer := 8;
srWidth : integer :=8;
addrSize : integer := 4 -- 2^addrSize = gregLength
);
PORT(
clk : IN std_logic;
rEnable : IN std_logic;
resetN : IN std_logic;
shiftCtrl : IN std_logic;
tsrEnable : IN std_logic;
wData : IN std_logic_vector (gregWidth-1 DOWNTO 0);
wEnable : IN std_logic;
tsrLoad : IN std_logic;
dataOut : OUT std_logic;
fifoEmpty : OUT std_logic;
fifoFull : OUT std_logic
);
-- Declarations
END fifo_test ;
--
-- VHDL Architecture my_project1_lib.fifo_test.struct
--
-- Created:
-- by - mg147.bin (srge00.ecn.purdue.edu)
-- at - 18:18:44 04/10/12
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2010.2a (Build 7)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ARCHITECTURE struct OF fifo_test IS
-- Architecture declarations
-- Internal signal declarations
SIGNAL tsrData : std_logic_vector(srWidth-1 DOWNTO 0);
-- Component Declarations
COMPONENT FifoTop
GENERIC (
gregLength : integer := 16;
gregWidth : integer := 8;
addrSize : integer := 4 -- 2^addrSize = gregLength
);
PORT (
clk : IN std_logic;
rEnable : IN std_logic;
resetN : IN std_logic;
wData : IN std_logic_vector (gregWidth-1 DOWNTO 0);
wEnable : IN std_logic;
fifoEmpty : OUT std_logic;
fifoFull : OUT std_logic;
rData : OUT std_logic_vector (gregWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT SpiXmitSR
GENERIC (
srWidth : integer := 8
);
PORT (
clk : IN std_logic;
resetN : IN std_logic;
shiftCtrl : IN std_logic;
tsrData : IN std_logic_vector (srWidth-1 DOWNTO 0);
tsrEnable : IN std_logic;
tsrLoad : IN std_logic;
dataOut : OUT std_logic
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
-- pragma synthesis_on
BEGIN
-- Instance port mappings.
U_0 : FifoTop
GENERIC MAP (
gregLength => 16,
gregWidth => 8,
addrSize => 4 -- 2^addrSize = gregLength
)
PORT MAP (
clk => clk,
rEnable => rEnable,
resetN => resetN,
wData => wData,
wEnable => wEnable,
fifoEmpty => fifoEmpty,
fifoFull => fifoFull,
rData => tsrData
);
U_1 : SpiXmitSR
GENERIC MAP (
srWidth => 8
)
PORT MAP (
clk => clk,
resetN => resetN,
tsrEnable => tsrEnable,
shiftCtrl => shiftCtrl,
tsrLoad => rEnable,
tsrData => tsrData,
dataOut => dataOut
);
END struct;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2509.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b04x00p03n01i02509ent IS
generic ( G_BOOL : boolean ) ;
port ( OUT_BIT : out bit ) ;
ENTITY c07s03b04x00p03n01i02509ent IS
BEGIN
TESTING: PROCESS
OUT_BIT <= bit'(G_BOOL); -- Failure_here
-- SEMANTIC ERROR: type of expression does not match type mark.
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b04x00p03n01i02509 - Expression type does not match type mark."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b04x00p03n01i02509arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2509.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b04x00p03n01i02509ent IS
generic ( G_BOOL : boolean ) ;
port ( OUT_BIT : out bit ) ;
ENTITY c07s03b04x00p03n01i02509ent IS
BEGIN
TESTING: PROCESS
OUT_BIT <= bit'(G_BOOL); -- Failure_here
-- SEMANTIC ERROR: type of expression does not match type mark.
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b04x00p03n01i02509 - Expression type does not match type mark."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b04x00p03n01i02509arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2509.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b04x00p03n01i02509ent IS
generic ( G_BOOL : boolean ) ;
port ( OUT_BIT : out bit ) ;
ENTITY c07s03b04x00p03n01i02509ent IS
BEGIN
TESTING: PROCESS
OUT_BIT <= bit'(G_BOOL); -- Failure_here
-- SEMANTIC ERROR: type of expression does not match type mark.
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b04x00p03n01i02509 - Expression type does not match type mark."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b04x00p03n01i02509arch;
|
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.all;
entity pll_125 is
port(
inclk0 : in std_logic := '0';
c0 : out std_logic
);
end pll_125;
architecture syn of pll_125 is
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
clk4_divide_by : NATURAL;
clk4_duty_cycle : NATURAL;
clk4_multiply_by : NATURAL;
clk4_phase_shift : STRING;
clk5_divide_by : NATURAL;
clk5_duty_cycle : NATURAL;
clk5_multiply_by : NATURAL;
clk5_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_fbout : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clk6 : STRING;
port_clk7 : STRING;
port_clk8 : STRING;
port_clk9 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
self_reset_on_loss_lock : STRING;
using_fbmimicbidir_port : STRING;
width_clock : NATURAL
);
PORT (
phasestep : IN STD_LOGIC ;
phaseupdown : IN STD_LOGIC ;
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
phasecounterselect : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
locked : OUT STD_LOGIC ;
phasedone : OUT STD_LOGIC ;
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
scanclk : IN STD_LOGIC
);
END COMPONENT;
signal sub_wire3 : std_logic_vector(1 downto 0);
signal sub_wire0 : std_logic_vector(9 downto 0);
begin
sub_wire3 <= '0' & inclk0;
c0 <= sub_wire0(0);
altpll_component : altpll
generic map (
bandwidth_type => "AUTO",
clk0_divide_by => 2,
clk0_duty_cycle => 50,
clk0_multiply_by => 5,
clk0_phase_shift => "0",
clk1_divide_by => 2,
clk1_duty_cycle => 50,
clk1_multiply_by => 5,
clk1_phase_shift => "0",
clk2_divide_by => 2,
clk2_duty_cycle => 50,
clk2_multiply_by => 5,
clk2_phase_shift => "0",
clk3_divide_by => 2,
clk3_duty_cycle => 50,
clk3_multiply_by => 5,
clk3_phase_shift => "0",
clk4_divide_by => 2,
clk4_duty_cycle => 50,
clk4_multiply_by => 5,
clk4_phase_shift => "0",
clk5_divide_by => 2,
clk5_duty_cycle => 50,
clk5_multiply_by => 5,
clk5_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Stratix IV",
lpm_hint => "CBX_MODULE_PREFIX=pll_125",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_fbout => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clk6 => "PORT_UNUSED",
port_clk7 => "PORT_UNUSED",
port_clk8 => "PORT_UNUSED",
port_clk9 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
using_fbmimicbidir_port => "OFF",
self_reset_on_loss_lock => "OFF",
width_clock => 10
)
port map (
inclk => sub_wire3,
clk => sub_wire0,
areset => '0',
phasecounterselect => "1111",
phasestep => '1',
phaseupdown => '1',
scanclk => '0'
);
end architecture syn; |
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.all;
entity pll_125 is
port(
inclk0 : in std_logic := '0';
c0 : out std_logic
);
end pll_125;
architecture syn of pll_125 is
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
clk4_divide_by : NATURAL;
clk4_duty_cycle : NATURAL;
clk4_multiply_by : NATURAL;
clk4_phase_shift : STRING;
clk5_divide_by : NATURAL;
clk5_duty_cycle : NATURAL;
clk5_multiply_by : NATURAL;
clk5_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_fbout : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clk6 : STRING;
port_clk7 : STRING;
port_clk8 : STRING;
port_clk9 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
self_reset_on_loss_lock : STRING;
using_fbmimicbidir_port : STRING;
width_clock : NATURAL
);
PORT (
phasestep : IN STD_LOGIC ;
phaseupdown : IN STD_LOGIC ;
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
phasecounterselect : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
locked : OUT STD_LOGIC ;
phasedone : OUT STD_LOGIC ;
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
scanclk : IN STD_LOGIC
);
END COMPONENT;
signal sub_wire3 : std_logic_vector(1 downto 0);
signal sub_wire0 : std_logic_vector(9 downto 0);
begin
sub_wire3 <= '0' & inclk0;
c0 <= sub_wire0(0);
altpll_component : altpll
generic map (
bandwidth_type => "AUTO",
clk0_divide_by => 2,
clk0_duty_cycle => 50,
clk0_multiply_by => 5,
clk0_phase_shift => "0",
clk1_divide_by => 2,
clk1_duty_cycle => 50,
clk1_multiply_by => 5,
clk1_phase_shift => "0",
clk2_divide_by => 2,
clk2_duty_cycle => 50,
clk2_multiply_by => 5,
clk2_phase_shift => "0",
clk3_divide_by => 2,
clk3_duty_cycle => 50,
clk3_multiply_by => 5,
clk3_phase_shift => "0",
clk4_divide_by => 2,
clk4_duty_cycle => 50,
clk4_multiply_by => 5,
clk4_phase_shift => "0",
clk5_divide_by => 2,
clk5_duty_cycle => 50,
clk5_multiply_by => 5,
clk5_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Stratix IV",
lpm_hint => "CBX_MODULE_PREFIX=pll_125",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_fbout => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clk6 => "PORT_UNUSED",
port_clk7 => "PORT_UNUSED",
port_clk8 => "PORT_UNUSED",
port_clk9 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
using_fbmimicbidir_port => "OFF",
self_reset_on_loss_lock => "OFF",
width_clock => 10
)
port map (
inclk => sub_wire3,
clk => sub_wire0,
areset => '0',
phasecounterselect => "1111",
phasestep => '1',
phaseupdown => '1',
scanclk => '0'
);
end architecture syn; |
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.all;
entity pll_125 is
port(
inclk0 : in std_logic := '0';
c0 : out std_logic
);
end pll_125;
architecture syn of pll_125 is
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
clk4_divide_by : NATURAL;
clk4_duty_cycle : NATURAL;
clk4_multiply_by : NATURAL;
clk4_phase_shift : STRING;
clk5_divide_by : NATURAL;
clk5_duty_cycle : NATURAL;
clk5_multiply_by : NATURAL;
clk5_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_fbout : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clk6 : STRING;
port_clk7 : STRING;
port_clk8 : STRING;
port_clk9 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
self_reset_on_loss_lock : STRING;
using_fbmimicbidir_port : STRING;
width_clock : NATURAL
);
PORT (
phasestep : IN STD_LOGIC ;
phaseupdown : IN STD_LOGIC ;
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
phasecounterselect : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
locked : OUT STD_LOGIC ;
phasedone : OUT STD_LOGIC ;
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
scanclk : IN STD_LOGIC
);
END COMPONENT;
signal sub_wire3 : std_logic_vector(1 downto 0);
signal sub_wire0 : std_logic_vector(9 downto 0);
begin
sub_wire3 <= '0' & inclk0;
c0 <= sub_wire0(0);
altpll_component : altpll
generic map (
bandwidth_type => "AUTO",
clk0_divide_by => 2,
clk0_duty_cycle => 50,
clk0_multiply_by => 5,
clk0_phase_shift => "0",
clk1_divide_by => 2,
clk1_duty_cycle => 50,
clk1_multiply_by => 5,
clk1_phase_shift => "0",
clk2_divide_by => 2,
clk2_duty_cycle => 50,
clk2_multiply_by => 5,
clk2_phase_shift => "0",
clk3_divide_by => 2,
clk3_duty_cycle => 50,
clk3_multiply_by => 5,
clk3_phase_shift => "0",
clk4_divide_by => 2,
clk4_duty_cycle => 50,
clk4_multiply_by => 5,
clk4_phase_shift => "0",
clk5_divide_by => 2,
clk5_duty_cycle => 50,
clk5_multiply_by => 5,
clk5_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Stratix IV",
lpm_hint => "CBX_MODULE_PREFIX=pll_125",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_fbout => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clk6 => "PORT_UNUSED",
port_clk7 => "PORT_UNUSED",
port_clk8 => "PORT_UNUSED",
port_clk9 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
using_fbmimicbidir_port => "OFF",
self_reset_on_loss_lock => "OFF",
width_clock => 10
)
port map (
inclk => sub_wire3,
clk => sub_wire0,
areset => '0',
phasecounterselect => "1111",
phasestep => '1',
phaseupdown => '1',
scanclk => '0'
);
end architecture syn; |
--! @file reset_sequencer_tb.vhd
--! @brief Test Bench for Reset Sequencer
--! @author Scott Teal ([email protected])
--! @date 2013-09-30
--! @copyright
--! Copyright 2013 Richard Scott Teal, Jr.
--!
--! Licensed under the Apache License, Version 2.0 (the "License"); you may not
--! use this file except in compliance with the License. You may obtain a copy
--! of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
--! WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
--! License for the specific language governing permissions and limitations
--! under the License.
--! Standard IEEE library
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
--! Testbench for an entity in boostlogic library
library boostlogic;
--! reset_sequencer Testbench
entity reset_sequencer_tb is
end entity;
--! Simulation of reset_sequencer
architecture sim of reset_sequencer_tb is
constant clk_period : time := 2 ns;
-- Test Signals to UUT
signal clk : std_logic;
signal rst : std_logic;
signal rst_vector : std_logic_vector(4 downto 0);
signal done : std_logic;
begin
uut : entity boostlogic.reset_sequencer
generic map (
clk_period => clk_period,
wait_times => (10 ns, 20 ns, 30 ns, 40 ns, 50 ns),
retry_time => 60 ns,
move_fast => "00000",
debounce_time => 200 ns
)
port map (
clk => clk,
rst => rst,
check_good => "11111",
rst_vector => rst_vector,
done => done
);
clk_proc : process
begin
clk <= '0';
wait for clk_period / 2;
clk <= '1';
wait for clk_period / 2;
end process;
rst_proc : process
begin
rst <= '1';
wait for clk_period * 4;
rst <= '0';
wait;
end process;
end sim;
|
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------
entity testbench is
--generic declarations
end entity testbench;
--------------------------------------
architecture circuit of testbench is
signal clk: std_logic := '0';
signal rst: std_logic := '0';
begin
-- generation of clk with after (concurrent)
clk <= not clk after 10 ns;
-- generation of rst with wait for (sequential)
process
begin
wait for 10 ns;
rst <= '1';
wait for 10 ns;
rst <= '0';
wait;
end process;
-- generation of rst with after (concurrent)
-- rst <= '1' after 10 ns, '0' after 20 ns;
end architecture circuit;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity vga_node is
generic(
data_width : integer := 64;
addr_width : integer := 4;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic;
-- vga connections
clk27 : in std_logic;
rst27 : in std_logic;
vga_red : out std_logic_vector(5 downto 0);
vga_blue : out std_logic_vector(5 downto 0);
vga_green : out std_logic_vector(5 downto 0);
vga_v_sync : out std_logic;
vga_h_sync : out std_logic
);
end entity vga_node;
architecture fsmd of vga_node is
--- Components ------------------------------------------------------------
component priority_encoder is
generic(
encoded_word_size : integer := 3
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end component priority_encoder;
component vga_controller is
generic(
h_pulse : integer := 208; --horiztonal sync pulse width in pixels
h_bp : integer := 336; --horiztonal back porch width in pixels
h_pixels : integer := 1920; --horiztonal display width in pixels
h_fp : integer := 128; --horiztonal front porch width in pixels
h_pol : std_logic := '0'; --horizontal sync pulse polarity (1 = positive, 0 = negative)
v_pulse : integer := 3; --vertical sync pulse width in rows
v_bp : integer := 38; --vertical back porch width in rows
v_pixels : integer := 1200; --vertical display width in rows
v_fp : integer := 1; --vertical front porch width in rows
v_pol : std_logic := '1'); --vertical sync pulse polarity (1 = positive, 0 = negative)
port(
pixel_clk : in std_logic; --pixel clock at frequency of vga mode being used
reset_n : in std_logic; --active low asycnchronous reset
h_sync : out std_logic; --horiztonal sync pulse
v_sync : out std_logic; --vertical sync pulse
disp_ena : out std_logic; --display enable ('1' = display time, '0' = blanking time)
column : out integer; --horizontal pixel coordinate
row : out integer; --vertical pixel coordinate
n_blank : out std_logic; --direct blacking output to dac
n_sync : out std_logic); --sync-on-green output to dac
end component vga_controller;
component ram_dual is
generic
(
ram_width : integer := 24;
ram_depth : integer := 65536
);
port
(
clock1 : in std_logic;
clock2 : in std_logic;
data : in std_logic_vector(ram_width-1 downto 0);
write_address : in integer;
read_address : in integer;
we : in std_logic;
q : out std_logic_vector(ram_width-1 downto 0)
);
end component ram_dual;
component ycbcr_to_rgb is
port(
clk : in std_logic;
y : in std_logic_vector(7 downto 0);
cb : in std_logic_vector(7 downto 0);
cr : in std_logic_vector(7 downto 0);
red : out std_logic_vector(7 downto 0);
green : out std_logic_vector(7 downto 0);
blue : out std_logic_vector(7 downto 0)
);
end component ycbcr_to_rgb;
--- Constants -------------------------------------------------------------
constant rgb_size : integer := 6;
constant horizontal : integer := 320;
constant vertical : integer := 200;
constant addr_size : integer := 19;
--- Types -----------------------------------------------------------------
type vga_node_states is (idle,
sel_vc,
rx,
convert_0,
wr_rgb_0,
convert_1,
wr_rgb_1,
dequeue_flit
);
--- signals and registers -------------------------------------------------
signal state : vga_node_states;
signal next_state : vga_node_states;
signal convert_counter_d : unsigned(7 downto 0);
signal convert_counter_q : unsigned(7 downto 0);
signal red_in : std_logic_vector(rgb_size-1 downto 0);
signal green_in : std_logic_vector(rgb_size-1 downto 0);
signal blue_in : std_logic_vector(rgb_size-1 downto 0);
signal wr_addr : integer;
signal wr_enable : std_logic;
signal red_out : std_logic_vector(rgb_size-1 downto 0);
signal green_out : std_logic_vector(rgb_size-1 downto 0);
signal blue_out : std_logic_vector(rgb_size-1 downto 0);
signal rd_addr : integer;
signal y : std_logic_vector(7 downto 0);
signal cb : std_logic_vector(7 downto 0);
signal cr : std_logic_vector(7 downto 0);
signal red : std_logic_vector(7 downto 0);
signal green : std_logic_vector(7 downto 0);
signal blue : std_logic_vector(7 downto 0);
signal r : std_logic_vector(9 downto 0);
signal g : std_logic_vector(9 downto 0);
signal b : std_logic_vector(9 downto 0);
signal current_x : integer;
signal current_y : integer;
signal request : std_logic;
signal vga_r : std_logic_vector(9 downto 0);
signal vga_g : std_logic_vector(9 downto 0);
signal vga_b : std_logic_vector(9 downto 0);
signal vga_hs : std_logic;
signal vga_vs : std_logic;
signal vga_blank : std_logic;
signal vga_clock : std_logic;
signal rd_addr_32 : std_logic_vector(31 downto 0);
signal sel_vc_d : std_logic_vector(vc_sel_width-1 downto 0);
signal sel_vc_q : std_logic_vector(vc_sel_width-1 downto 0);
signal sel_vc_enc : std_logic_vector(vc_sel_width-1 downto 0);
signal sel_vc_one_hot : std_logic_vector(num_vc-1 downto 0);
signal rgb_read : std_logic_vector(3*rgb_size-1 downto 0);
signal disp_ena : std_logic;
begin
---------------------------------------------------------------------------
--- DATAPATH --------------------------------------------------------------
---------------------------------------------------------------------------
--components
u0: component priority_encoder
generic map(
encoded_word_size => vc_sel_width
)
Port map(
input => data_in_buffer,
output => sel_vc_enc
);
red_ram: component ram_dual
generic map
(
ram_width => 6,
ram_depth => horizontal*vertical
)
port map
(
clock1 => clk,
clock2 => clk27,
data => red_in,
write_address => wr_addr,
read_address => rd_addr,
we => wr_enable,
q => red_out
);
blue_ram: component ram_dual
generic map
(
ram_width => 6,
ram_depth => horizontal*vertical
)
port map
(
clock1 => clk,
clock2 => clk27,
data => blue_in,
write_address => wr_addr,
read_address => rd_addr,
we => wr_enable,
q => blue_out
);
green_ram: component ram_dual
generic map
(
ram_width => 6,
ram_depth => horizontal*vertical
)
port map
(
clock1 => clk,
clock2 => clk27,
data => green_in,
write_address => wr_addr,
read_address => rd_addr,
we => wr_enable,
q => green_out
);
u2: component ycbcr_to_rgb
port map(
clk => clk ,
y => y ,
cb => cb ,
cr => cr ,
red => red ,
green => green,
blue => blue
);
u3: component vga_controller
generic map(
h_pulse => 96,
h_bp => 48,
h_pixels => 640,
h_fp => 16,
h_pol => '0',
v_pulse => 2,
v_bp => 35,
v_pixels => 400,
v_fp => 12,
v_pol => '1'
)
port map(
pixel_clk => clk27,
reset_n => not rst27,
h_sync => vga_hs,
v_sync => vga_vs,
column => current_x,
row => current_y,
disp_ena => disp_ena
);
rd_addr <= (current_x mod horizontal) +
(current_y mod vertical ) * horizontal;
vga_red <= red_out when disp_ena = '1' else "000000"; --red_out;
vga_blue <= blue_out when disp_ena = '1' else "000000"; --green_out;
vga_green <= green_out when disp_ena = '1' else "000000"; --blue_out;
vga_v_sync <= vga_vs;
vga_h_sync <= vga_hs;
y <= recv_data(63 downto 56) when state = convert_0 else recv_data(39 downto 32);
cb <= recv_data(55 downto 48) when state = convert_0 else recv_data(31 downto 24);
cr <= recv_data(47 downto 40) when state = convert_0 else recv_data(23 downto 16);
red_in <= red(7 downto 2);
green_in <= green(7 downto 2);
blue_in <= blue(7 downto 2);
wr_addr <= to_integer(unsigned(recv_data(15 downto 0))) when state = wr_rgb_0 or state = convert_0 else
to_integer(unsigned(recv_data(15 downto 0))) + 1;
wr_enable <= '1' when state = wr_rgb_0 else
'1' when state = wr_rgb_1 else
'0';
--counter for coversion wait states
convert_counter_d <= convert_counter_q + to_unsigned(1, 8) when state = convert_0 else
convert_counter_q + to_unsigned(1, 8) when state = convert_1 else
to_unsigned(0, 8);
process(clk, rst)
begin
if rst = '1' then
sel_vc_q <= (others => '0');
convert_counter_q <= (others => '0');
elsif rising_edge(clk) then
convert_counter_q <= convert_counter_d;
sel_vc_q <= sel_vc_d;
end if;
end process;
--packet generation
send_data <= (others => '0');
dest_addr <= (others => '0');
set_tail_flit <= '0';
send_flit <= '0';
--rx controls
sel_vc_d <= sel_vc_enc when state = sel_vc else sel_vc_q;
dequeue <= sel_vc_one_hot when state = dequeue_flit else "00";
select_vc_read <= sel_vc_q;
sel_vc_one_hot <= "01" when sel_vc_q = "0" else "10";
---------------------------------------------------------------------------
--- STATE MACHINE ---------------------------------------------------------
---------------------------------------------------------------------------
process(clk, rst)
begin
if rst = '1' then
state <= idle;
elsif rising_edge(clk) then
state <= next_state;
end if;
end process;
process(state, data_in_buffer, is_tail_flit, sel_vc_one_hot, ready_to_send, convert_counter_q)
begin
next_state <= state;
if state = idle and or_reduce(data_in_buffer) = '1' then
next_state <= sel_vc;
end if;
if state = sel_vc then
next_state <= rx;
end if;
if state = rx then
next_state <= convert_0;
end if;
if state = convert_0 and convert_counter_q > to_unsigned(2, 8) then
next_state <= wr_rgb_0;
end if;
if state = wr_rgb_0 then
next_state <= convert_1;
end if;
if state = convert_1 and convert_counter_q > to_unsigned(2, 8) then
next_state <= wr_rgb_1;
end if;
if state = wr_rgb_1 then
next_state <= dequeue_flit;
end if;
if state = dequeue_flit then
next_state <= idle;
end if;
end process;
end architecture;
|
entity bounds24 is
end entity;
architecture test of bounds24 is
function func (n : natural) return bit is
variable r : bit_vector(1 to 3) := (1 to n => '1');
begin
return r(1) xor r(2) xor r(3);
end function;
signal n : integer := 3;
begin
main: process is
begin
assert func(3) = '1'; -- OK
assert func(n) = '1'; -- OK
n <= 1000;
wait for 1 ns;
assert func(n) = '1'; -- Error
wait;
end process;
end architecture;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
library ieee; use ieee.math_real.all;
entity v_source is
port ( terminal p, m : electrical );
end entity v_source;
----------------------------------------------------------------
architecture source_sine of v_source is
constant ampl : real := 1.0;
constant freq : real := 60.0;
quantity v across i through p to m;
begin
v == ampl * sin(2.0 * math_pi * freq * now);
end architecture source_sine;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
library ieee; use ieee.math_real.all;
entity v_source is
port ( terminal p, m : electrical );
end entity v_source;
----------------------------------------------------------------
architecture source_sine of v_source is
constant ampl : real := 1.0;
constant freq : real := 60.0;
quantity v across i through p to m;
begin
v == ampl * sin(2.0 * math_pi * freq * now);
end architecture source_sine;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
library ieee; use ieee.math_real.all;
entity v_source is
port ( terminal p, m : electrical );
end entity v_source;
----------------------------------------------------------------
architecture source_sine of v_source is
constant ampl : real := 1.0;
constant freq : real := 60.0;
quantity v across i through p to m;
begin
v == ampl * sin(2.0 * math_pi * freq * now);
end architecture source_sine;
|
-- The processor --
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.processor_functions.all;
ENTITY processor IS
PORT (clk, nrst, WAKE_signal: IN std_logic;
-- Switches
switches: IN std_logic_vector(17 downto 0);
-- Leds vermelhos
red_leds: OUT std_logic_vector(17 downto 0);
-- Leds verdes
green_leds: OUT std_logic_vector(8 downto 0);
-- 7 Seg
hex7: OUT std_logic_vector(0 TO 7);
hex6: OUT std_logic_vector(0 TO 7);
hex5: OUT std_logic_vector(0 TO 7);
hex4: OUT std_logic_vector(0 TO 7);
hex3: OUT std_logic_vector(0 TO 7);
hex2: OUT std_logic_vector(0 TO 7);
hex1: OUT std_logic_vector(0 TO 7);
hex0: OUT std_logic_vector(0 TO 7));
END ENTITY processor;
ARCHITECTURE processor OF processor IS
SIGNAL CONTROL_bus: std_logic_vector(n-1 DOWNTO 0);
SIGNAL clk_out: std_logic;
-- IR
SIGNAL IR_opcode: opcode;
SIGNAL IR_load: std_logic;
SIGNAL IR_valid: std_logic;
SIGNAL IR_opcode_leds: std_logic_vector(3 DOWNTO 0);
-- PC
SIGNAL PC_inc: std_logic;
SIGNAL PC_load: std_logic;
SIGNAL PC_valid: std_logic;
SIGNAL PC_7seg: std_logic_vector(0 TO 15);
-- Memory
SIGNAL MDR_load: std_logic;
SIGNAL MAR_load: std_logic;
SIGNAL MEM_valid: std_logic;
SIGNAL MEM_en: std_logic;
SIGNAL MEM_rw: std_logic;
-- ALU
SIGNAL ALU_zero: std_logic;
SIGNAL ALU_slt: std_logic;
SIGNAL ALU_valid: std_logic;
SIGNAL ALU_enable: std_logic;
SIGNAL ALU_cmd: std_logic_vector(3 DOWNTO 0);
-- IO
SIGNAL IODR_load: std_logic;
SIGNAL IOAR_load: std_logic;
SIGNAL IO_valid: std_logic;
SIGNAL IO_en: std_logic;
SIGNAL IO_rw: std_logic;
BEGIN
-- Para visualizacao
green_leds(0) <= not nrst;
green_leds(7) <= not WAKE_signal;
red_leds(17) <= clk_out;
red_leds(11 DOWNTO 0) <= CONTROL_bus;
red_leds(16 DOWNTO 13) <= IR_opcode_leds;
hex7 <= "01100001";
hex5 <= PC_7seg(8 TO 15);
hex4 <= PC_7seg(0 TO 7);
-- Divisor de clock
clock_divisor : entity work.clock_divisor port map(clk, nrst, clk_out);
-- Entidades internas
controller : entity work.controller port map(clk_out, nrst, CONTROL_bus, hex6, IR_opcode, IR_load, IR_valid, PC_inc, PC_load, PC_valid, MDR_load, MAR_load, MEM_valid, MEM_en, MEM_rw, ALU_zero, ALU_valid, ALU_slt, ALU_enable, ALU_cmd, IODR_load, IOAR_load, IO_valid, IO_en, IO_rw, WAKE_signal, green_leds(8));
memory : entity work.memory port map(clk_out, nrst, MDR_load, MAR_load, MEM_valid, MEM_en, MEM_rw, CONTROL_bus);
alu : entity work.alu port map(clk_out, nrst, ALU_cmd, ALU_zero, ALU_slt, ALU_valid, ALU_enable, CONTROL_bus);
ir : entity work.ir port map(clk_out, nrst, IR_load, IR_valid, IR_opcode, CONTROL_bus, IR_opcode_leds);
pc : entity work.pc port map(clk_out, nrst, PC_inc, PC_load, PC_valid, CONTROL_bus, PC_7seg);
io : entity work.io port map(clk_out, nrst, IODR_load, IOAR_load, IO_valid, IO_en, IO_rw, CONTROL_bus, switches, hex3, hex2, hex1, hex0);
END ARCHITECTURE; |
-- file: Interface_Master_BD_clk_wiz_0_0_clk_wiz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1____71.602______0.000______50.0______245.835____242.683
-- CLK_OUT2_____7.202______0.000______50.0______392.994____242.683
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity Interface_Master_BD_clk_wiz_0_0_clk_wiz is
port
(-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk_out1 : out std_logic;
clk_out2 : out std_logic;
-- Status and control signals
resetn : in std_logic;
locked : out std_logic
);
end Interface_Master_BD_clk_wiz_0_0_clk_wiz;
architecture xilinx of Interface_Master_BD_clk_wiz_0_0_clk_wiz is
-- Input clock buffering / unused connectors
signal clk_in1_Interface_Master_BD_clk_wiz_0_0 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout_Interface_Master_BD_clk_wiz_0_0 : std_logic;
signal clkfbout_buf_Interface_Master_BD_clk_wiz_0_0 : std_logic;
signal clkfboutb_unused : std_logic;
signal clk_out1_Interface_Master_BD_clk_wiz_0_0 : std_logic;
signal clk_out1_Interface_Master_BD_clk_wiz_0_0_en_clk : std_logic;
signal clkout0b_unused : std_logic;
signal clk_out2_Interface_Master_BD_clk_wiz_0_0 : std_logic;
signal clk_out2_Interface_Master_BD_clk_wiz_0_0_en_clk : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
signal locked_int : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
signal reset_high : std_logic;
signal seq_reg1 : std_logic_vector(7 downto 0) := (others => '0');
signal seq_reg2 : std_logic_vector(7 downto 0) := (others => '0');
attribute ASYNC_REG : string;
attribute ASYNC_REG of seq_reg1: signal is "TRUE";
attribute keep: boolean;
attribute keep of seq_reg1: signal is true;
attribute ASYNC_REG of seq_reg2: signal is "TRUE";
attribute keep of seq_reg2: signal is true;
begin
-- Input buffering
--------------------------------------
clkin1_ibufg : IBUF
port map
(O => clk_in1_Interface_Master_BD_clk_wiz_0_0,
I => clk_in1);
-- Clocking PRIMITIVE
--------------------------------------
-- Instantiation of the MMCM PRIMITIVE
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "HIGH",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 4,
CLKFBOUT_MULT_F => 36.875,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 12.875,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => 128,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 10.0)
port map
-- Output clocks
(
CLKFBOUT => clkfbout_Interface_Master_BD_clk_wiz_0_0,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clk_out1_Interface_Master_BD_clk_wiz_0_0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clk_out2_Interface_Master_BD_clk_wiz_0_0,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_buf_Interface_Master_BD_clk_wiz_0_0,
CLKIN1 => clk_in1_Interface_Master_BD_clk_wiz_0_0,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => locked_int,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => reset_high);
reset_high <= not resetn;
locked <= locked_int;
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf_Interface_Master_BD_clk_wiz_0_0,
I => clkfbout_Interface_Master_BD_clk_wiz_0_0);
clkout1_buf : BUFGCE
port map
(O => clk_out1,
CE => seq_reg1(7),
I => clk_out1_Interface_Master_BD_clk_wiz_0_0);
clkout1_buf_en : BUFH
port map
(O => clk_out1_Interface_Master_BD_clk_wiz_0_0_en_clk,
I => clk_out1_Interface_Master_BD_clk_wiz_0_0);
process(clk_out1_Interface_Master_BD_clk_wiz_0_0_en_clk)
begin
if clk_out1_Interface_Master_BD_clk_wiz_0_0_en_clk'event and clk_out1_Interface_Master_BD_clk_wiz_0_0_en_clk = '1' then
seq_reg1 <= seq_reg1(6 downto 0) & locked_int;
end if;
end process;
clkout2_buf : BUFGCE
port map
(O => clk_out2,
CE => seq_reg2(7),
I => clk_out2_Interface_Master_BD_clk_wiz_0_0);
clkout2_buf_en : BUFH
port map
(O => clk_out2_Interface_Master_BD_clk_wiz_0_0_en_clk,
I => clk_out2_Interface_Master_BD_clk_wiz_0_0);
process(clk_out2_Interface_Master_BD_clk_wiz_0_0_en_clk)
begin
if clk_out2_Interface_Master_BD_clk_wiz_0_0_en_clk'event and clk_out2_Interface_Master_BD_clk_wiz_0_0_en_clk = '1' then
seq_reg2 <= seq_reg2(6 downto 0) & locked_int;
end if;
end process;
end xilinx;
|
-- EULER module for Betty SDR
-- implements a rectangle to polar conversion
-- file: euler.vhd
-- author: Sebastian Weiss DL3YC <[email protected]>
-- version: 1.0
-- depends on: vcordic.vhd
--
-- change log:
-- - release implementation 1.0
-- - buggy phase in vcordic
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity euler is
generic
(
A : natural;
P : natural;
N : natural
);
port
(
clk : in std_logic;
i : in signed(A-1 downto 0);
q : in signed(A-1 downto 0);
amp : out unsigned(A-1 downto 0);
phi : out signed(P-1 downto 0)
);
end entity;
architecture behavioral of euler is
signal cordic_i : signed(A-1 downto 0) := (others => '0');
signal cordic_q : signed(A-1 downto 0) := (others => '0');
signal cordic_phi : signed(P-1 downto 0) := (others => '0');
signal cordic_amp : unsigned(A-1 downto 0) := (others => '0');
alias i_sign : std_logic is i(i'high);
alias q_sign : std_logic is q(q'high);
type quadrant_t is array(N+3 downto 0) of bit_vector(1 downto 0);
signal quadrant : quadrant_t;
alias actual_quadrant : bit_vector(1 downto 0) is quadrant(0);
alias last_quadrant : bit_vector(1 downto 0) is quadrant(N+3);
begin
cordic : entity work.vcordic
generic map(
A => A,
P => P,
N => N
)
port map(
clk => clk,
i => cordic_i,
q => cordic_q,
amp => cordic_amp,
phi => cordic_phi
);
process
begin
wait until rising_edge(clk);
quadrant(N+3 downto 1) <= quadrant(N+2 downto 0);
end process;
quadrant(0) <= to_bit(i_sign) & to_bit(q_sign);
process
begin
wait until rising_edge(clk);
case actual_quadrant is
when "00" => -- 1st quadrant
cordic_i <= i;
cordic_q <= q;
when "01" => -- 2nd quadrant
cordic_i <= i;
cordic_q <= -q;
when "11" => -- 3rd quadrant
cordic_i <= -i;
cordic_q <= -q;
when "10" => -- 4th quadrant
cordic_i <= -i;
cordic_q <= q;
end case;
end process;
process
begin
wait until rising_edge(clk);
case last_quadrant is
when "00" => phi <= cordic_phi; -- 1st quadrant
when "01" => phi <= 2**(P-1) - cordic_phi; -- 2nd quadrant
when "11" => phi <= 2**(P-1) + cordic_phi; -- 3rd quadrant
when "10" => phi <= -cordic_phi; -- 4th quadrant
end case;
amp <= cordic_amp;
end process;
end behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sampling_pkg.all;
package tdc_sample_prep_pkg is
constant TDC_EVENT_POS_BITS: natural := 2;
type tdc_event_t is
record
valid: std_logic;
pos: unsigned(1 downto 0);
end record;
function to_std_logic_vector(x: tdc_event_t) return std_logic_vector;
function to_tdc_event_t(x: std_logic_vector) return tdc_event_t;
-- convert vector to a single event encoded as valid flag + position. extract first event only.
function flat_events_to_event_t(flat: std_logic_vector(3 downto 0)) return tdc_event_t;
type tdc_events_t is
record
d1_rising: tdc_event_t;
d1_falling: tdc_event_t;
d2_rising: tdc_event_t;
d2_falling: tdc_event_t;
a_maxfound: tdc_event_t;
a_maxvalue: a_sample_t;
end record;
component tdc_sample_prep is
generic (
CNT_BITS: natural := 16
);
port (
clk: in std_logic;
samples_d_in: in din_samples_t(0 to 3);
samples_a_in: in adc_samples_t(0 to 1);
a_threshold: in a_sample_t;
a_invert: in std_logic;
a_average: in std_logic_vector(1 downto 0);
--
samples_d_out: out din_samples_t(0 to 3);
samples_a_out: out a_samples_t(0 to 1);
cnt: out unsigned(CNT_BITS-1 downto 0);
tdc_events: out tdc_events_t
);
end component;
end tdc_sample_prep_pkg;
package body tdc_sample_prep_pkg is
function to_std_logic_vector(x: tdc_event_t) return std_logic_vector is
variable result: std_logic_vector(1+TDC_EVENT_POS_BITS-1 downto 0);
begin
result(TDC_EVENT_POS_BITS) := x.valid;
result(TDC_EVENT_POS_BITS-1 downto 0) := std_logic_vector(x.pos);
return result;
end to_std_logic_vector;
function to_tdc_event_t(x: std_logic_vector) return tdc_event_t is
variable result: tdc_event_t;
begin
result.valid := x(x'low + TDC_EVENT_POS_BITS);
result.pos := unsigned(x(x'low + TDC_EVENT_POS_BITS-1 downto x'low));
return result;
end to_tdc_event_t;
function flat_events_to_event_t(flat: std_logic_vector(3 downto 0)) return tdc_event_t is
variable result: tdc_event_t := (valid => '0', pos => (others => '-'));
begin
for I in 0 to 3 loop
if flat(I) = '1' then
result.valid := '1';
result.pos := to_unsigned(3-I, 2);
end if;
end loop;
return result;
end flat_events_to_event_t;
end tdc_sample_prep_pkg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1567.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p03n01i01567ent IS
END c08s10b00x00p03n01i01567ent;
ARCHITECTURE c08s10b00x00p03n01i01567arch OF c08s10b00x00p03n01i01567ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
variable m : integer := 0;
BEGIN
L1: for i in boolean loop
k := 5;
L2: for j in 1 to 3 loop
next L2;
k := 3;
end loop L2;
m := m + 1;
end loop L1;
assert NOT(( k=5 ) and (m= boolean'Pos(boolean'High) - boolean'Pos(boolean'Low) + 1))
report "***PASSED TEST: c08s10b00x00p03n01i01567"
severity NOTE;
assert (( k=5 ) and (m= boolean'Pos(boolean'High) - boolean'Pos(boolean'Low) + 1))
report "***FAILED TEST: c08s10b00x00p03n01i01567 - A next statement with a loop label is only allowed within the labeled loop, and applies to that loop."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p03n01i01567arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1567.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p03n01i01567ent IS
END c08s10b00x00p03n01i01567ent;
ARCHITECTURE c08s10b00x00p03n01i01567arch OF c08s10b00x00p03n01i01567ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
variable m : integer := 0;
BEGIN
L1: for i in boolean loop
k := 5;
L2: for j in 1 to 3 loop
next L2;
k := 3;
end loop L2;
m := m + 1;
end loop L1;
assert NOT(( k=5 ) and (m= boolean'Pos(boolean'High) - boolean'Pos(boolean'Low) + 1))
report "***PASSED TEST: c08s10b00x00p03n01i01567"
severity NOTE;
assert (( k=5 ) and (m= boolean'Pos(boolean'High) - boolean'Pos(boolean'Low) + 1))
report "***FAILED TEST: c08s10b00x00p03n01i01567 - A next statement with a loop label is only allowed within the labeled loop, and applies to that loop."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p03n01i01567arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1567.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p03n01i01567ent IS
END c08s10b00x00p03n01i01567ent;
ARCHITECTURE c08s10b00x00p03n01i01567arch OF c08s10b00x00p03n01i01567ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
variable m : integer := 0;
BEGIN
L1: for i in boolean loop
k := 5;
L2: for j in 1 to 3 loop
next L2;
k := 3;
end loop L2;
m := m + 1;
end loop L1;
assert NOT(( k=5 ) and (m= boolean'Pos(boolean'High) - boolean'Pos(boolean'Low) + 1))
report "***PASSED TEST: c08s10b00x00p03n01i01567"
severity NOTE;
assert (( k=5 ) and (m= boolean'Pos(boolean'High) - boolean'Pos(boolean'Low) + 1))
report "***FAILED TEST: c08s10b00x00p03n01i01567 - A next statement with a loop label is only allowed within the labeled loop, and applies to that loop."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p03n01i01567arch;
|
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 14, 2017
--! @brief Contains the entity and architecture of the
--! Single Port Block RAM needed to load either the boot
--! loader, jumper loader, or the main application.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.main_pack.all;
use work.jump_pack.all;
use work.boot_pack.all;
--! The Single Port BRAM is effectively defined as an array the
--! compiler can infer as Block RAM. This methodology is useful for verification
--! purposes since the contents of the array can be observed while in simulation.
--! Moreover, binary can be loaded into the BRAM during static elaboration prior
--! to synthesis, allowing the BRAM to be initialized with a bootloader application
--! for hardware deployment.
--!
--! One out of three types of binary can be statically loaded into the BRAM. The first
--! of which is the Jump binary, whose purpose is to make the Plasma-SoC's CPU jump
--! to a particular place in memory. The Jump binary was made so that the Bootloader
--! binary can be bypassed in simulation, allowing the Main binary to begin its execution
--! faster. The second binary is the Bootloader. The purpose of the Bootloader is to load
--! the Main application into memory and then cause the CPU to jump to the starting address
--! of the Main application. Finally, the Main binary is the application under test. Unlike
--! the Jump and Boot binaries, the Main binary can be located at an address other than 0 if
--! compiled and linked correctly. The Jump and Bootloader binaries need to be built such that
--! they are aware where the Main binary is located and needs to go, respectively.
--!
--! Alternatively, the BRAM can be initialized to zero; in other words, without any binary.
--!
--! It is recommended to read over the documentation presented in the corresponding C sources
--! to learn more about these applications.
entity bram is
generic (
select_app : string := "none"; --! Selects the binary to statically load. "none" refers to no binary. "jump" refers to the Jump binary. "boot" refers to the Bootloader binary. "main" refers to the Main application.
address_width : integer := 18; --! Defines the address width.
data_width : integer := 32; --! Defines the data width.
bram_depth : integer := 65536 --! Defines the size of the BRAM in the number of words.
);
port(
bram_rst_a : in std_logic; --! High reset. Since the binary is loaded statically, this reset effectively behaves like another bram_en_a.
bram_clk_a : in std_logic; --! Clock that synchronizes the BRAM's operation.
bram_en_a : in std_logic; --! Enables the BRAM when high.
bram_we_a : in std_logic_vector(data_width/8-1 downto 0); --! Each high bit allows the respective byte in bram_wrdata_a to be written into the BRAM.
bram_addr_a : in std_logic_vector(address_width-1 downto 0); --! Specifies the BRAM's location where the memory access operation will occur on the next positive edge clock cycle. Should be a multiple of (2**address_width)/(data_width/8) and less than bram_depth*(data_width/8).
bram_wrdata_a : in std_logic_vector(data_width-1 downto 0); --! The data that will be written on the next positive edge clock cycle provided that bram_rst_a is low, bram_en_a is high, and at least one bit in bram_we_a is high.
bram_rddata_a : out std_logic_vector(data_width-1 downto 0) := (others=>'0') --! The data that will be read on the next positive edge clock cycle provided that bram_rst_a is low and bram_en_a is high.
);
end bram;
architecture Behavioral of bram is
constant bytes_per_word : integer := data_width/8;
type bram_buff_type is array (0 to bram_depth-1) of std_logic_vector(data_width-1 downto 0);
function load_selected_app return bram_buff_type is
variable bram_buff : bram_buff_type := (others=>(others=>'0'));
variable boot_buff : work.boot_pack.ram_type;
variable jump_buff : work.jump_pack.ram_type;
variable main_buff : work.main_pack.ram_type;
begin
case select_app is
when "none"=>
when "main"=>
main_buff := work.main_pack.load_hex;
for each_word in 0 to work.main_pack.ram_size-1 loop
bram_buff(each_word) := main_buff(each_word);
end loop;
when "jump"=>
jump_buff := work.jump_pack.load_hex;
for each_word in 0 to work.jump_pack.ram_size-1 loop
bram_buff(each_word) := jump_buff(each_word);
end loop;
when "boot"=>
boot_buff := work.boot_pack.load_hex;
for each_word in 0 to work.boot_pack.ram_size-1 loop
bram_buff(each_word) := boot_buff(each_word);
end loop;
when others=>
assert false report "Incorrect option for select_app" severity error;
end case;
return bram_buff;
end;
signal bram_buff : bram_buff_type := load_selected_app;
begin
process (bram_clk_a)
variable base_index : integer;
begin
if rising_edge(bram_clk_a) then
if bram_rst_a='0' then
if bram_en_a='1' then
base_index := to_integer(unsigned(bram_addr_a))/bytes_per_word;
for each_byte in 0 to bytes_per_word-1 loop
if bram_we_a(each_byte)='1' then
bram_buff(base_index)(each_byte*8+7 downto each_byte*8) <=
bram_wrdata_a(each_byte*8+7 downto each_byte*8);
end if;
end loop;
bram_rddata_a <= bram_buff(base_index);
end if;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 14, 2017
--! @brief Contains the entity and architecture of the
--! Single Port Block RAM needed to load either the boot
--! loader, jumper loader, or the main application.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.main_pack.all;
use work.jump_pack.all;
use work.boot_pack.all;
--! The Single Port BRAM is effectively defined as an array the
--! compiler can infer as Block RAM. This methodology is useful for verification
--! purposes since the contents of the array can be observed while in simulation.
--! Moreover, binary can be loaded into the BRAM during static elaboration prior
--! to synthesis, allowing the BRAM to be initialized with a bootloader application
--! for hardware deployment.
--!
--! One out of three types of binary can be statically loaded into the BRAM. The first
--! of which is the Jump binary, whose purpose is to make the Plasma-SoC's CPU jump
--! to a particular place in memory. The Jump binary was made so that the Bootloader
--! binary can be bypassed in simulation, allowing the Main binary to begin its execution
--! faster. The second binary is the Bootloader. The purpose of the Bootloader is to load
--! the Main application into memory and then cause the CPU to jump to the starting address
--! of the Main application. Finally, the Main binary is the application under test. Unlike
--! the Jump and Boot binaries, the Main binary can be located at an address other than 0 if
--! compiled and linked correctly. The Jump and Bootloader binaries need to be built such that
--! they are aware where the Main binary is located and needs to go, respectively.
--!
--! Alternatively, the BRAM can be initialized to zero; in other words, without any binary.
--!
--! It is recommended to read over the documentation presented in the corresponding C sources
--! to learn more about these applications.
entity bram is
generic (
select_app : string := "none"; --! Selects the binary to statically load. "none" refers to no binary. "jump" refers to the Jump binary. "boot" refers to the Bootloader binary. "main" refers to the Main application.
address_width : integer := 18; --! Defines the address width.
data_width : integer := 32; --! Defines the data width.
bram_depth : integer := 65536 --! Defines the size of the BRAM in the number of words.
);
port(
bram_rst_a : in std_logic; --! High reset. Since the binary is loaded statically, this reset effectively behaves like another bram_en_a.
bram_clk_a : in std_logic; --! Clock that synchronizes the BRAM's operation.
bram_en_a : in std_logic; --! Enables the BRAM when high.
bram_we_a : in std_logic_vector(data_width/8-1 downto 0); --! Each high bit allows the respective byte in bram_wrdata_a to be written into the BRAM.
bram_addr_a : in std_logic_vector(address_width-1 downto 0); --! Specifies the BRAM's location where the memory access operation will occur on the next positive edge clock cycle. Should be a multiple of (2**address_width)/(data_width/8) and less than bram_depth*(data_width/8).
bram_wrdata_a : in std_logic_vector(data_width-1 downto 0); --! The data that will be written on the next positive edge clock cycle provided that bram_rst_a is low, bram_en_a is high, and at least one bit in bram_we_a is high.
bram_rddata_a : out std_logic_vector(data_width-1 downto 0) := (others=>'0') --! The data that will be read on the next positive edge clock cycle provided that bram_rst_a is low and bram_en_a is high.
);
end bram;
architecture Behavioral of bram is
constant bytes_per_word : integer := data_width/8;
type bram_buff_type is array (0 to bram_depth-1) of std_logic_vector(data_width-1 downto 0);
function load_selected_app return bram_buff_type is
variable bram_buff : bram_buff_type := (others=>(others=>'0'));
variable boot_buff : work.boot_pack.ram_type;
variable jump_buff : work.jump_pack.ram_type;
variable main_buff : work.main_pack.ram_type;
begin
case select_app is
when "none"=>
when "main"=>
main_buff := work.main_pack.load_hex;
for each_word in 0 to work.main_pack.ram_size-1 loop
bram_buff(each_word) := main_buff(each_word);
end loop;
when "jump"=>
jump_buff := work.jump_pack.load_hex;
for each_word in 0 to work.jump_pack.ram_size-1 loop
bram_buff(each_word) := jump_buff(each_word);
end loop;
when "boot"=>
boot_buff := work.boot_pack.load_hex;
for each_word in 0 to work.boot_pack.ram_size-1 loop
bram_buff(each_word) := boot_buff(each_word);
end loop;
when others=>
assert false report "Incorrect option for select_app" severity error;
end case;
return bram_buff;
end;
signal bram_buff : bram_buff_type := load_selected_app;
begin
process (bram_clk_a)
variable base_index : integer;
begin
if rising_edge(bram_clk_a) then
if bram_rst_a='0' then
if bram_en_a='1' then
base_index := to_integer(unsigned(bram_addr_a))/bytes_per_word;
for each_byte in 0 to bytes_per_word-1 loop
if bram_we_a(each_byte)='1' then
bram_buff(base_index)(each_byte*8+7 downto each_byte*8) <=
bram_wrdata_a(each_byte*8+7 downto each_byte*8);
end if;
end loop;
bram_rddata_a <= bram_buff(base_index);
end if;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 14, 2017
--! @brief Contains the entity and architecture of the
--! Single Port Block RAM needed to load either the boot
--! loader, jumper loader, or the main application.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.main_pack.all;
use work.jump_pack.all;
use work.boot_pack.all;
--! The Single Port BRAM is effectively defined as an array the
--! compiler can infer as Block RAM. This methodology is useful for verification
--! purposes since the contents of the array can be observed while in simulation.
--! Moreover, binary can be loaded into the BRAM during static elaboration prior
--! to synthesis, allowing the BRAM to be initialized with a bootloader application
--! for hardware deployment.
--!
--! One out of three types of binary can be statically loaded into the BRAM. The first
--! of which is the Jump binary, whose purpose is to make the Plasma-SoC's CPU jump
--! to a particular place in memory. The Jump binary was made so that the Bootloader
--! binary can be bypassed in simulation, allowing the Main binary to begin its execution
--! faster. The second binary is the Bootloader. The purpose of the Bootloader is to load
--! the Main application into memory and then cause the CPU to jump to the starting address
--! of the Main application. Finally, the Main binary is the application under test. Unlike
--! the Jump and Boot binaries, the Main binary can be located at an address other than 0 if
--! compiled and linked correctly. The Jump and Bootloader binaries need to be built such that
--! they are aware where the Main binary is located and needs to go, respectively.
--!
--! Alternatively, the BRAM can be initialized to zero; in other words, without any binary.
--!
--! It is recommended to read over the documentation presented in the corresponding C sources
--! to learn more about these applications.
entity bram is
generic (
select_app : string := "none"; --! Selects the binary to statically load. "none" refers to no binary. "jump" refers to the Jump binary. "boot" refers to the Bootloader binary. "main" refers to the Main application.
address_width : integer := 18; --! Defines the address width.
data_width : integer := 32; --! Defines the data width.
bram_depth : integer := 65536 --! Defines the size of the BRAM in the number of words.
);
port(
bram_rst_a : in std_logic; --! High reset. Since the binary is loaded statically, this reset effectively behaves like another bram_en_a.
bram_clk_a : in std_logic; --! Clock that synchronizes the BRAM's operation.
bram_en_a : in std_logic; --! Enables the BRAM when high.
bram_we_a : in std_logic_vector(data_width/8-1 downto 0); --! Each high bit allows the respective byte in bram_wrdata_a to be written into the BRAM.
bram_addr_a : in std_logic_vector(address_width-1 downto 0); --! Specifies the BRAM's location where the memory access operation will occur on the next positive edge clock cycle. Should be a multiple of (2**address_width)/(data_width/8) and less than bram_depth*(data_width/8).
bram_wrdata_a : in std_logic_vector(data_width-1 downto 0); --! The data that will be written on the next positive edge clock cycle provided that bram_rst_a is low, bram_en_a is high, and at least one bit in bram_we_a is high.
bram_rddata_a : out std_logic_vector(data_width-1 downto 0) := (others=>'0') --! The data that will be read on the next positive edge clock cycle provided that bram_rst_a is low and bram_en_a is high.
);
end bram;
architecture Behavioral of bram is
constant bytes_per_word : integer := data_width/8;
type bram_buff_type is array (0 to bram_depth-1) of std_logic_vector(data_width-1 downto 0);
function load_selected_app return bram_buff_type is
variable bram_buff : bram_buff_type := (others=>(others=>'0'));
variable boot_buff : work.boot_pack.ram_type;
variable jump_buff : work.jump_pack.ram_type;
variable main_buff : work.main_pack.ram_type;
begin
case select_app is
when "none"=>
when "main"=>
main_buff := work.main_pack.load_hex;
for each_word in 0 to work.main_pack.ram_size-1 loop
bram_buff(each_word) := main_buff(each_word);
end loop;
when "jump"=>
jump_buff := work.jump_pack.load_hex;
for each_word in 0 to work.jump_pack.ram_size-1 loop
bram_buff(each_word) := jump_buff(each_word);
end loop;
when "boot"=>
boot_buff := work.boot_pack.load_hex;
for each_word in 0 to work.boot_pack.ram_size-1 loop
bram_buff(each_word) := boot_buff(each_word);
end loop;
when others=>
assert false report "Incorrect option for select_app" severity error;
end case;
return bram_buff;
end;
signal bram_buff : bram_buff_type := load_selected_app;
begin
process (bram_clk_a)
variable base_index : integer;
begin
if rising_edge(bram_clk_a) then
if bram_rst_a='0' then
if bram_en_a='1' then
base_index := to_integer(unsigned(bram_addr_a))/bytes_per_word;
for each_byte in 0 to bytes_per_word-1 loop
if bram_we_a(each_byte)='1' then
bram_buff(base_index)(each_byte*8+7 downto each_byte*8) <=
bram_wrdata_a(each_byte*8+7 downto each_byte*8);
end if;
end loop;
bram_rddata_a <= bram_buff(base_index);
end if;
end if;
end if;
end process;
end Behavioral;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Oct 27 14:51:03 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/RATCPU/Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_prog_rom_0_0/RAT_prog_rom_0_0_stub.vhdl
-- Design : RAT_prog_rom_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RAT_prog_rom_0_0 is
Port (
ADDRESS : in STD_LOGIC_VECTOR ( 9 downto 0 );
INSTRUCTION : out STD_LOGIC_VECTOR ( 17 downto 0 );
CLK : in STD_LOGIC
);
end RAT_prog_rom_0_0;
architecture stub of RAT_prog_rom_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "ADDRESS[9:0],INSTRUCTION[17:0],CLK";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "prog_rom,Vivado 2016.4";
begin
end;
|
-- ----------------------------------------------------------------------------
-- Entity for implementation of SINDHU PRASANA NFA
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity SINDHU_PRASANA_NFA is
generic(
DATA_WIDTH : integer := %$%;
RULES : integer := %$%
);
port(
CLK : in std_logic;
RESET : in std_logic;
-- input data interface
DATA : in std_logic_vector(DATA_WIDTH - 1 downto 0);
SOF : in std_logic;
EOF : in std_logic;
SRC_RDY : in std_logic;
DST_RDY : out std_logic;
-- output data interface
BITMAP : out std_logic_vector(RULES - 1 downto 0);
VLD : out std_logic;
ACK : in std_logic
);
end entity SINDHU_PRASANA_NFA;
-- ----------------------------------------------------------------------------
-- Architecture: full
-- ----------------------------------------------------------------------------
architecture full of SINDHU_PRASANA_NFA is
signal local_reset : std_logic;
signal local_reset_fsm : std_logic;
signal we : std_logic;
-- signal rdy : std_logic;
-- signal vld_internal : std_logic;
-- signal set : std_logic;
%$%
begin
-- local_reset <= RESET or ACK;
-- we <= SRC_RDY and rdy;
-- DST_RDY <= rdy;
-- VLD <= vld_internal;
-- set <= SRC_RDY and EOF and rdy;
-- rdy <= not vld_internal;
--
-- end_reg: process(CLK)
-- begin
-- if (CLK'event and CLK = '1') then
-- if (local_reset = '1') then
-- vld_internal <= '0';
-- else
-- if set = '1' then
-- vld_internal <= '1';
-- end if;
-- end if;
-- end if;
-- end process end_reg;
local_reset <= RESET or local_reset_fsm;
ctrl_fsm: entity work.CONTROL_FSM
port map(
CLK => CLK,
RESET => RESET,
-- input interface
EOF => EOF,
SRC_RDY => SRC_RDY,
DST_RDY => DST_RDY,
-- output interface
WE => we,
LOCAL_RESET => local_reset_fsm,
-- inner interface
VLD => VLD,
ACK => ACK
);
%$%
final_bitmap_u: entity work.FINAL_BITMAP
generic map(
DATA_WIDTH => RULES
)
port map(
CLK => CLK,
RESET => local_reset,
-- input data interface
SET => bitmap_in,
-- output data interface
BITMAP => BITMAP
);
end architecture full;
|
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.dspalu_pac.all;
use work.bit_manipulation.all;
-------------------------------------------------------------------------------
package dspunit_pac is
constant sig_width : positive := 16;
constant cmdreg_addr_width : natural := 4;
constant cmdreg_data_width : positive := 16;
constant cmdreg_width : positive := 16;
constant cmdregs_length : positive := 16;
constant acc_width : positive := 40;
constant acc_reduce_width : positive := 30;
constant lut_in_width : positive := 13;
constant lut_sel_width : positive := 4;
constant lut_out_width : positive := sig_width;
constant angle_width : positive := 13;
constant c_dsp_pipe_length : positive := 4;
constant div_pipe_length : positive := sig_width + 1;
function sig_cst_init(realval : real) return std_logic_vector;
function module(a : signed; b : signed) return integer;
procedure dispsig(name : string; ind : integer; val : integer);
--type t_dsp_cmdregs is array (0 to ((2**cmdreg_addr_width) - 1)) of std_logic_vector((cmdreg_width - 1) downto 0);
type t_dsp_cmdregs is array (0 to cmdregs_length - 1) of std_logic_vector((cmdreg_width - 1) downto 0);
type t_dsp_bus is
record
op_done : std_logic;
-- memory 0
data_out_m0 : std_logic_vector((sig_width - 1) downto 0);
addr_r_m0 : unsigned((cmdreg_width - 1) downto 0);
addr_w_m0 : unsigned((cmdreg_width - 1) downto 0);
wr_en_m0 : std_logic;
c_en_m0 : std_logic;
-- memory 1
data_out_m1 : std_logic_vector((sig_width - 1) downto 0);
addr_m1 : unsigned((cmdreg_width - 1) downto 0);
wr_en_m1 : std_logic;
c_en_m1 : std_logic;
-- memory 2
data_out_m2 : std_logic_vector((sig_width - 1) downto 0);
addr_m2 : unsigned((cmdreg_width - 1) downto 0);
wr_en_m2 : std_logic;
c_en_m2 : std_logic;
-- alu
mul_in_a1 : std_logic_vector((sig_width - 1) downto 0);
mul_in_b1 : std_logic_vector((sig_width - 1) downto 0);
mul_in_a2 : std_logic_vector((sig_width - 1) downto 0);
mul_in_b2 : std_logic_vector((sig_width - 1) downto 0);
acc_mode1 : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
acc_mode2 : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
alu_select : std_logic_vector((alu_select_width - 1) downto 0); -- t_alu_select;
cmp_mode : std_logic_vector((cmp_mode_width - 1) downto 0); -- t_cmp_mode;
cmp_pol : std_logic;
cmp_store : std_logic;
-- divider
div_num : std_logic_vector((2*sig_width - 1) downto 0);
div_den : std_logic_vector((sig_width - 1) downto 0);
-- global counter
gcounter_reset : std_logic;
-- shared lut
lut_in : std_logic_vector((lut_in_width - 1) downto 0);
lut_select : std_logic_vector((lut_sel_width - 1) downto 0);
end record;
constant c_dsp_bus_init : t_dsp_bus := (
op_done => '0',
-- memory 0
data_out_m0 => (others => '0'),
addr_r_m0 => (others => '0'),
addr_w_m0 => (others => '0'),
wr_en_m0 => '0',
c_en_m0 => '0',
-- memory 1
data_out_m1 => (others => '0'),
addr_m1 => (others => '0'),
wr_en_m1 => '0',
c_en_m1 => '0',
-- memory 2
data_out_m2 => (others => '0'),
addr_m2 => (others => '0'),
wr_en_m2 => '0',
c_en_m2 => '0',
-- alu
mul_in_a1 => (others => '0'),
mul_in_b1 => (others => '0'),
mul_in_a2 => (others => '0'),
mul_in_b2 => (others => '0'),
acc_mode1 => acc_none,
acc_mode2 => acc_none,
alu_select => alu_none,
cmp_mode => cmp_none,
cmp_pol => '0',
cmp_store => '0',
-- divider
div_num => (others => '0'),
div_den => (others => '0'),
-- global counter
gcounter_reset => '0',
-- shared lut
lut_in => (others => '0'),
lut_select => (others => '0')
);
function "or" (a, b : t_dsp_bus) return t_dsp_bus;
function "and" (a : std_logic_vector; b : std_logic) return std_logic_vector;
function dsp_cmdregs_init return t_dsp_cmdregs;
-------------------------------------------------------------------------------
-- General params
-------------------------------------------------------------------------------
constant c_dspmem_pipe_depth : integer := 2;
-------------------------------------------------------------------------------
-- Register address
-------------------------------------------------------------------------------
-- registers offsets of dspunit
constant DSPADDR_STARTADDR0 : positive := 1;
constant DSPADDR_LENGTH0 : positive := 2;
constant DSPADDR_STARTADDR1 : positive := 3;
constant DSPADDR_LENGTH1 : positive := 4;
constant DSPADDR_STARTADDR2 : positive := 5;
constant DSPADDR_LENGTH2 : positive := 6;
constant DSPADDR_OPCODE : positive := 7;
constant DSPADDR_SR : positive := 8;
-- Bits of status register
constant DSP_SRBIT_DONE : natural := 0;
constant DSP_SRBIT_RUN : natural := 1;
constant DSP_SRBIT_LOADED : natural := 2;
constant DSP_SRBIT_DONE_IE : natural := 3;
constant DSP_SRBIT_EMPTY_IE : natural := 4;
constant DSP_SRBIT_DONE_IF : natural := 5;
constant DSP_SRBIT_EMPTY_IF : natural := 6;
constant DSP_SRBIT_UNUSED : natural := 7;
-- opcodes of availables processings
constant opcode_width : positive := 4;
constant opcode_cpflip : std_logic_vector((opcode_width - 1) downto 0) := "0010";
constant opcode_cpmem : std_logic_vector((opcode_width - 1) downto 0) := "0100";
constant opcode_setmem : std_logic_vector((opcode_width - 1) downto 0) := "0101";
constant opcode_dotopnorm : std_logic_vector((opcode_width - 1) downto 0) := "0111";
constant opcode_dotdiv : std_logic_vector((opcode_width - 1) downto 0) := "1000";
constant opcode_fft : std_logic_vector((opcode_width - 1) downto 0) := "1100";
constant opcode_dotcmul : std_logic_vector((opcode_width - 1) downto 0) := "1101";
-- opflags (options related to each operation)
constant opflag_width : positive := 8;
constant opflag_ifft : std_logic_vector((opflag_width - 1) downto 0) := "00000001";
constant opflagbit_ifft : natural := 0;
constant opflag_bitrev : std_logic_vector((opflag_width - 1) downto 0) := "00000010";
constant opflagbit_bitrev : natural := 1;
constant opflag_mainmem : std_logic_vector((opflag_width - 1) downto 0) := "00000010";
constant opflagbit_mainmem : natural := 1;
constant opflag_savestep : std_logic_vector((opflag_width - 1) downto 0) := "00001000";
constant opflagbit_savestep : natural := 3;
constant opflag_muladd : std_logic_vector((opflag_width - 1) downto 0) := "00000001";
constant opflagbit_muladd : natural := 0;
constant opflag_l1norm : std_logic_vector((opflag_width - 1) downto 0) := "00000010";
constant opflagbit_l1norm : natural := 1;
constant opflag_tocomplex : std_logic_vector((opflag_width - 1) downto 0) := "00000001";
constant opflagbit_tocomplex : natural := 0;
constant opflag_fromcomplex : std_logic_vector((opflag_width - 1) downto 0) := "00000010";
constant opflagbit_fromcomplex : natural := 1;
constant opflag_m0 : std_logic_vector((opflag_width - 1) downto 0) := "00100000";
constant opflagbit_m0 : natural := 5;
constant opflag_m1 : std_logic_vector((opflag_width - 1) downto 0) := "01000000";
constant opflagbit_m1 : natural := 6;
constant opflag_m2 : std_logic_vector((opflag_width - 1) downto 0) := "10000000";
constant opflagbit_m2 : natural := 7;
constant opflag_srcm0 : std_logic_vector((opflag_width - 1) downto 0) := "00000100";
constant opflagbit_srcm0 : natural := 2;
constant opflag_srcm1 : std_logic_vector((opflag_width - 1) downto 0) := "00001000";
constant opflagbit_srcm1 : natural := 3;
constant opflag_srcm2 : std_logic_vector((opflag_width - 1) downto 0) := "00010000";
constant opflagbit_srcm2 : natural := 4;
constant opflag_srcswap : std_logic_vector((opflag_width - 1) downto 0) := "00000010";
constant opflagbit_srcswap : natural := 1;
-- selection of math lut
constant lutsel_none : std_logic_vector((lut_sel_width - 1) downto 0) := "0000";
constant lutsel_cos : std_logic_vector((lut_sel_width - 1) downto 0) := "0001";
constant lutsel_sin : std_logic_vector((lut_sel_width - 1) downto 0) := "0010";
end dspunit_pac;
package body dspunit_pac is
function sig_cst_init(realval : real) return std_logic_vector
is
variable fracval : real;
variable fracint : integer;
begin
fracval := realval * real(2 ** (sig_width - 1));
fracint := integer(floor(fracval));
return std_logic_vector(to_signed(fracint, sig_width));
end sig_cst_init;
function module(a : signed; b : signed) return integer
is
variable res : real;
begin
res := sqrt(real(to_integer(a))**2 + real(to_integer(b))**2);
return integer(res);
end module;
procedure dispsig(name : string; ind : integer; val : integer)
is
variable msg : line;
begin
write(msg, string'("dispsig : "));
write(msg, name);
write(msg, string'("("));
write(msg, ind);
write(msg, string'(") = "));
write(msg, val);
report msg.all;
end dispsig;
function "or" (a, b : t_dsp_bus) return t_dsp_bus is
variable y : t_dsp_bus;
begin
-- y <= a or b;
y.op_done := a.op_done or b.op_done ;
y.data_out_m0 := a.data_out_m0 or b.data_out_m0 ;
y.addr_r_m0 := a.addr_r_m0 or b.addr_r_m0 ;
y.addr_w_m0 := a.addr_w_m0 or b.addr_w_m0 ;
y.wr_en_m0 := a.wr_en_m0 or b.wr_en_m0 ;
y.c_en_m0 := a.c_en_m0 or b.c_en_m0 ;
y.data_out_m1 := a.data_out_m1 or b.data_out_m1 ;
y.addr_m1 := a.addr_m1 or b.addr_m1 ;
y.wr_en_m1 := a.wr_en_m1 or b.wr_en_m1 ;
y.c_en_m1 := a.c_en_m1 or b.c_en_m1 ;
y.data_out_m2 := a.data_out_m2 or b.data_out_m2 ;
y.addr_m2 := a.addr_m2 or b.addr_m2 ;
y.wr_en_m2 := a.wr_en_m2 or b.wr_en_m2 ;
y.c_en_m2 := a.c_en_m2 or b.c_en_m2 ;
y.mul_in_a1 := a.mul_in_a1 or b.mul_in_a1 ;
y.mul_in_b1 := a.mul_in_b1 or b.mul_in_b1 ;
y.mul_in_a2 := a.mul_in_a2 or b.mul_in_a2 ;
y.mul_in_b2 := a.mul_in_b2 or b.mul_in_b2 ;
y.acc_mode1 := a.acc_mode1 or b.acc_mode1 ;
y.acc_mode2 := a.acc_mode2 or b.acc_mode2 ;
y.alu_select := a.alu_select or b.alu_select ;
y.cmp_mode := a.cmp_mode or b.cmp_mode ;
y.cmp_pol := a.cmp_pol or b.cmp_pol ;
y.cmp_store := a.cmp_store or b.cmp_store ;
y.div_num := a.div_num or b.div_num ;
y.div_den := a.div_den or b.div_den ;
y.gcounter_reset := a.gcounter_reset or b.gcounter_reset;
y.lut_in := a.lut_in or b.lut_in ;
y.lut_select := a.lut_select or b.lut_select ;
return y;
end "or";
function "and" (a : std_logic_vector; b : std_logic) return std_logic_vector is
constant L : natural := a'length;
alias aa : std_logic_vector((L - 1) downto 0) is A;
variable yy : std_logic_vector((L - 1) downto 0);
begin
for i in L-1 downto 0 loop
yy(i) := aa(i) and b;
end loop;
return yy;
end "and";
function dsp_cmdregs_init return t_dsp_cmdregs is
variable regs : t_dsp_cmdregs;
begin
for i in 0 to cmdregs_length - 1 loop
regs(i) := (others => '0');
end loop;
return regs;
end dsp_cmdregs_init;
end dspunit_pac;
|
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.dspalu_pac.all;
use work.bit_manipulation.all;
-------------------------------------------------------------------------------
package dspunit_pac is
constant sig_width : positive := 16;
constant cmdreg_addr_width : natural := 4;
constant cmdreg_data_width : positive := 16;
constant cmdreg_width : positive := 16;
constant cmdregs_length : positive := 16;
constant acc_width : positive := 40;
constant acc_reduce_width : positive := 30;
constant lut_in_width : positive := 13;
constant lut_sel_width : positive := 4;
constant lut_out_width : positive := sig_width;
constant angle_width : positive := 13;
constant c_dsp_pipe_length : positive := 4;
constant div_pipe_length : positive := sig_width + 1;
function sig_cst_init(realval : real) return std_logic_vector;
function module(a : signed; b : signed) return integer;
procedure dispsig(name : string; ind : integer; val : integer);
--type t_dsp_cmdregs is array (0 to ((2**cmdreg_addr_width) - 1)) of std_logic_vector((cmdreg_width - 1) downto 0);
type t_dsp_cmdregs is array (0 to cmdregs_length - 1) of std_logic_vector((cmdreg_width - 1) downto 0);
type t_dsp_bus is
record
op_done : std_logic;
-- memory 0
data_out_m0 : std_logic_vector((sig_width - 1) downto 0);
addr_r_m0 : unsigned((cmdreg_width - 1) downto 0);
addr_w_m0 : unsigned((cmdreg_width - 1) downto 0);
wr_en_m0 : std_logic;
c_en_m0 : std_logic;
-- memory 1
data_out_m1 : std_logic_vector((sig_width - 1) downto 0);
addr_m1 : unsigned((cmdreg_width - 1) downto 0);
wr_en_m1 : std_logic;
c_en_m1 : std_logic;
-- memory 2
data_out_m2 : std_logic_vector((sig_width - 1) downto 0);
addr_m2 : unsigned((cmdreg_width - 1) downto 0);
wr_en_m2 : std_logic;
c_en_m2 : std_logic;
-- alu
mul_in_a1 : std_logic_vector((sig_width - 1) downto 0);
mul_in_b1 : std_logic_vector((sig_width - 1) downto 0);
mul_in_a2 : std_logic_vector((sig_width - 1) downto 0);
mul_in_b2 : std_logic_vector((sig_width - 1) downto 0);
acc_mode1 : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
acc_mode2 : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
alu_select : std_logic_vector((alu_select_width - 1) downto 0); -- t_alu_select;
cmp_mode : std_logic_vector((cmp_mode_width - 1) downto 0); -- t_cmp_mode;
cmp_pol : std_logic;
cmp_store : std_logic;
-- divider
div_num : std_logic_vector((2*sig_width - 1) downto 0);
div_den : std_logic_vector((sig_width - 1) downto 0);
-- global counter
gcounter_reset : std_logic;
-- shared lut
lut_in : std_logic_vector((lut_in_width - 1) downto 0);
lut_select : std_logic_vector((lut_sel_width - 1) downto 0);
end record;
constant c_dsp_bus_init : t_dsp_bus := (
op_done => '0',
-- memory 0
data_out_m0 => (others => '0'),
addr_r_m0 => (others => '0'),
addr_w_m0 => (others => '0'),
wr_en_m0 => '0',
c_en_m0 => '0',
-- memory 1
data_out_m1 => (others => '0'),
addr_m1 => (others => '0'),
wr_en_m1 => '0',
c_en_m1 => '0',
-- memory 2
data_out_m2 => (others => '0'),
addr_m2 => (others => '0'),
wr_en_m2 => '0',
c_en_m2 => '0',
-- alu
mul_in_a1 => (others => '0'),
mul_in_b1 => (others => '0'),
mul_in_a2 => (others => '0'),
mul_in_b2 => (others => '0'),
acc_mode1 => acc_none,
acc_mode2 => acc_none,
alu_select => alu_none,
cmp_mode => cmp_none,
cmp_pol => '0',
cmp_store => '0',
-- divider
div_num => (others => '0'),
div_den => (others => '0'),
-- global counter
gcounter_reset => '0',
-- shared lut
lut_in => (others => '0'),
lut_select => (others => '0')
);
function "or" (a, b : t_dsp_bus) return t_dsp_bus;
function "and" (a : std_logic_vector; b : std_logic) return std_logic_vector;
function dsp_cmdregs_init return t_dsp_cmdregs;
-------------------------------------------------------------------------------
-- General params
-------------------------------------------------------------------------------
constant c_dspmem_pipe_depth : integer := 2;
-------------------------------------------------------------------------------
-- Register address
-------------------------------------------------------------------------------
-- registers offsets of dspunit
constant DSPADDR_STARTADDR0 : positive := 1;
constant DSPADDR_LENGTH0 : positive := 2;
constant DSPADDR_STARTADDR1 : positive := 3;
constant DSPADDR_LENGTH1 : positive := 4;
constant DSPADDR_STARTADDR2 : positive := 5;
constant DSPADDR_LENGTH2 : positive := 6;
constant DSPADDR_OPCODE : positive := 7;
constant DSPADDR_SR : positive := 8;
-- Bits of status register
constant DSP_SRBIT_DONE : natural := 0;
constant DSP_SRBIT_RUN : natural := 1;
constant DSP_SRBIT_LOADED : natural := 2;
constant DSP_SRBIT_DONE_IE : natural := 3;
constant DSP_SRBIT_EMPTY_IE : natural := 4;
constant DSP_SRBIT_DONE_IF : natural := 5;
constant DSP_SRBIT_EMPTY_IF : natural := 6;
constant DSP_SRBIT_UNUSED : natural := 7;
-- opcodes of availables processings
constant opcode_width : positive := 4;
constant opcode_cpflip : std_logic_vector((opcode_width - 1) downto 0) := "0010";
constant opcode_cpmem : std_logic_vector((opcode_width - 1) downto 0) := "0100";
constant opcode_setmem : std_logic_vector((opcode_width - 1) downto 0) := "0101";
constant opcode_dotopnorm : std_logic_vector((opcode_width - 1) downto 0) := "0111";
constant opcode_dotdiv : std_logic_vector((opcode_width - 1) downto 0) := "1000";
constant opcode_fft : std_logic_vector((opcode_width - 1) downto 0) := "1100";
constant opcode_dotcmul : std_logic_vector((opcode_width - 1) downto 0) := "1101";
-- opflags (options related to each operation)
constant opflag_width : positive := 8;
constant opflag_ifft : std_logic_vector((opflag_width - 1) downto 0) := "00000001";
constant opflagbit_ifft : natural := 0;
constant opflag_bitrev : std_logic_vector((opflag_width - 1) downto 0) := "00000010";
constant opflagbit_bitrev : natural := 1;
constant opflag_mainmem : std_logic_vector((opflag_width - 1) downto 0) := "00000010";
constant opflagbit_mainmem : natural := 1;
constant opflag_savestep : std_logic_vector((opflag_width - 1) downto 0) := "00001000";
constant opflagbit_savestep : natural := 3;
constant opflag_muladd : std_logic_vector((opflag_width - 1) downto 0) := "00000001";
constant opflagbit_muladd : natural := 0;
constant opflag_l1norm : std_logic_vector((opflag_width - 1) downto 0) := "00000010";
constant opflagbit_l1norm : natural := 1;
constant opflag_tocomplex : std_logic_vector((opflag_width - 1) downto 0) := "00000001";
constant opflagbit_tocomplex : natural := 0;
constant opflag_fromcomplex : std_logic_vector((opflag_width - 1) downto 0) := "00000010";
constant opflagbit_fromcomplex : natural := 1;
constant opflag_m0 : std_logic_vector((opflag_width - 1) downto 0) := "00100000";
constant opflagbit_m0 : natural := 5;
constant opflag_m1 : std_logic_vector((opflag_width - 1) downto 0) := "01000000";
constant opflagbit_m1 : natural := 6;
constant opflag_m2 : std_logic_vector((opflag_width - 1) downto 0) := "10000000";
constant opflagbit_m2 : natural := 7;
constant opflag_srcm0 : std_logic_vector((opflag_width - 1) downto 0) := "00000100";
constant opflagbit_srcm0 : natural := 2;
constant opflag_srcm1 : std_logic_vector((opflag_width - 1) downto 0) := "00001000";
constant opflagbit_srcm1 : natural := 3;
constant opflag_srcm2 : std_logic_vector((opflag_width - 1) downto 0) := "00010000";
constant opflagbit_srcm2 : natural := 4;
constant opflag_srcswap : std_logic_vector((opflag_width - 1) downto 0) := "00000010";
constant opflagbit_srcswap : natural := 1;
-- selection of math lut
constant lutsel_none : std_logic_vector((lut_sel_width - 1) downto 0) := "0000";
constant lutsel_cos : std_logic_vector((lut_sel_width - 1) downto 0) := "0001";
constant lutsel_sin : std_logic_vector((lut_sel_width - 1) downto 0) := "0010";
end dspunit_pac;
package body dspunit_pac is
function sig_cst_init(realval : real) return std_logic_vector
is
variable fracval : real;
variable fracint : integer;
begin
fracval := realval * real(2 ** (sig_width - 1));
fracint := integer(floor(fracval));
return std_logic_vector(to_signed(fracint, sig_width));
end sig_cst_init;
function module(a : signed; b : signed) return integer
is
variable res : real;
begin
res := sqrt(real(to_integer(a))**2 + real(to_integer(b))**2);
return integer(res);
end module;
procedure dispsig(name : string; ind : integer; val : integer)
is
variable msg : line;
begin
write(msg, string'("dispsig : "));
write(msg, name);
write(msg, string'("("));
write(msg, ind);
write(msg, string'(") = "));
write(msg, val);
report msg.all;
end dispsig;
function "or" (a, b : t_dsp_bus) return t_dsp_bus is
variable y : t_dsp_bus;
begin
-- y <= a or b;
y.op_done := a.op_done or b.op_done ;
y.data_out_m0 := a.data_out_m0 or b.data_out_m0 ;
y.addr_r_m0 := a.addr_r_m0 or b.addr_r_m0 ;
y.addr_w_m0 := a.addr_w_m0 or b.addr_w_m0 ;
y.wr_en_m0 := a.wr_en_m0 or b.wr_en_m0 ;
y.c_en_m0 := a.c_en_m0 or b.c_en_m0 ;
y.data_out_m1 := a.data_out_m1 or b.data_out_m1 ;
y.addr_m1 := a.addr_m1 or b.addr_m1 ;
y.wr_en_m1 := a.wr_en_m1 or b.wr_en_m1 ;
y.c_en_m1 := a.c_en_m1 or b.c_en_m1 ;
y.data_out_m2 := a.data_out_m2 or b.data_out_m2 ;
y.addr_m2 := a.addr_m2 or b.addr_m2 ;
y.wr_en_m2 := a.wr_en_m2 or b.wr_en_m2 ;
y.c_en_m2 := a.c_en_m2 or b.c_en_m2 ;
y.mul_in_a1 := a.mul_in_a1 or b.mul_in_a1 ;
y.mul_in_b1 := a.mul_in_b1 or b.mul_in_b1 ;
y.mul_in_a2 := a.mul_in_a2 or b.mul_in_a2 ;
y.mul_in_b2 := a.mul_in_b2 or b.mul_in_b2 ;
y.acc_mode1 := a.acc_mode1 or b.acc_mode1 ;
y.acc_mode2 := a.acc_mode2 or b.acc_mode2 ;
y.alu_select := a.alu_select or b.alu_select ;
y.cmp_mode := a.cmp_mode or b.cmp_mode ;
y.cmp_pol := a.cmp_pol or b.cmp_pol ;
y.cmp_store := a.cmp_store or b.cmp_store ;
y.div_num := a.div_num or b.div_num ;
y.div_den := a.div_den or b.div_den ;
y.gcounter_reset := a.gcounter_reset or b.gcounter_reset;
y.lut_in := a.lut_in or b.lut_in ;
y.lut_select := a.lut_select or b.lut_select ;
return y;
end "or";
function "and" (a : std_logic_vector; b : std_logic) return std_logic_vector is
constant L : natural := a'length;
alias aa : std_logic_vector((L - 1) downto 0) is A;
variable yy : std_logic_vector((L - 1) downto 0);
begin
for i in L-1 downto 0 loop
yy(i) := aa(i) and b;
end loop;
return yy;
end "and";
function dsp_cmdregs_init return t_dsp_cmdregs is
variable regs : t_dsp_cmdregs;
begin
for i in 0 to cmdregs_length - 1 loop
regs(i) := (others => '0');
end loop;
return regs;
end dsp_cmdregs_init;
end dspunit_pac;
|
-- file: my_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___320.000______0.000______50.0______262.500____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________32____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity my_dcm is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end my_dcm;
architecture xilinx of my_dcm is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "my_dcm,clk_wiz_v3_6,{component_name=my_dcm,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 10,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfb,
I => clk0);
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkfx);
end xilinx;
|
-- NEED RESULT: ARCH00147.P1: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00147.P2: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00147.P3: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00147.P4: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00147.P5: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00147.P6: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00147.P7: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00147.P8: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00147.P9: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00147.P10: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00147.P11: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00147.P12: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00147.P13: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00147.P14: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00147.P15: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00147.P16: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00147.P17: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00147: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00147: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00147: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00147: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00147: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00147: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00147: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00147: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00147: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00147: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00147: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00147: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00147: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00147: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00147: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00147: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00147: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: P17: Inertial transactions entirely completed failed
-- NEED RESULT: P16: Inertial transactions entirely completed failed
-- NEED RESULT: P15: Inertial transactions entirely completed failed
-- NEED RESULT: P14: Inertial transactions entirely completed failed
-- NEED RESULT: P13: Inertial transactions entirely completed failed
-- NEED RESULT: P12: Inertial transactions entirely completed failed
-- NEED RESULT: P11: Inertial transactions entirely completed failed
-- NEED RESULT: P10: Inertial transactions entirely completed failed
-- NEED RESULT: P9: Inertial transactions entirely completed failed
-- NEED RESULT: P8: Inertial transactions entirely completed failed
-- NEED RESULT: P7: Inertial transactions entirely completed failed
-- NEED RESULT: P6: Inertial transactions entirely completed failed
-- NEED RESULT: P5: Inertial transactions entirely completed failed
-- NEED RESULT: P4: Inertial transactions entirely completed failed
-- NEED RESULT: P3: Inertial transactions entirely completed failed
-- NEED RESULT: P2: Inertial transactions entirely completed failed
-- NEED RESULT: P1: Inertial transactions entirely completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00147
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00147(ARCH00147)
-- ENT00147_Test_Bench(ARCH00147_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00147 is
port (
s_st_boolean_vector : inout st_boolean_vector
; s_st_bit_vector : inout st_bit_vector
; s_st_severity_level_vector : inout st_severity_level_vector
; s_st_string : inout st_string
; s_st_enum1_vector : inout st_enum1_vector
; s_st_integer_vector : inout st_integer_vector
; s_st_int1_vector : inout st_int1_vector
; s_st_time_vector : inout st_time_vector
; s_st_phys1_vector : inout st_phys1_vector
; s_st_real_vector : inout st_real_vector
; s_st_real1_vector : inout st_real1_vector
; s_st_rec1_vector : inout st_rec1_vector
; s_st_rec2_vector : inout st_rec2_vector
; s_st_rec3_vector : inout st_rec3_vector
; s_st_arr1_vector : inout st_arr1_vector
; s_st_arr2_vector : inout st_arr2_vector
; s_st_arr3_vector : inout st_arr3_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_boolean_vector : chk_sig_type := -1 ;
signal chk_st_bit_vector : chk_sig_type := -1 ;
signal chk_st_severity_level_vector : chk_sig_type := -1 ;
signal chk_st_string : chk_sig_type := -1 ;
signal chk_st_enum1_vector : chk_sig_type := -1 ;
signal chk_st_integer_vector : chk_sig_type := -1 ;
signal chk_st_int1_vector : chk_sig_type := -1 ;
signal chk_st_time_vector : chk_sig_type := -1 ;
signal chk_st_phys1_vector : chk_sig_type := -1 ;
signal chk_st_real_vector : chk_sig_type := -1 ;
signal chk_st_real1_vector : chk_sig_type := -1 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_rec2_vector : chk_sig_type := -1 ;
signal chk_st_rec3_vector : chk_sig_type := -1 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr3_vector : chk_sig_type := -1 ;
--
end ENT00147 ;
--
architecture ARCH00147 of ENT00147 is
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_boolean_vector (lowb+1 to lowb+3) <=
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_boolean_vector (lowb+1 to lowb+3) <=
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_boolean_vector (lowb+1 to lowb+3) <=
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_boolean_vector (lowb+1 to lowb+3) <= transport
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_boolean_vector (lowb+1 to lowb+3) <=
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_boolean_vector (lowb+1 to lowb+3) <=
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00147" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_boolean_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_boolean_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_boolean_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_st_boolean_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P2 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_bit_vector (lowb+1 to lowb+3) <=
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_bit_vector (lowb+1 to lowb+3) <=
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_bit_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_bit_vector (lowb+1 to lowb+3) <=
c_st_bit_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_bit_vector (lowb+1 to lowb+3) <= transport
c_st_bit_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_bit_vector (lowb+1 to lowb+3) <=
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_bit_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_bit_vector (lowb+1 to lowb+3) <=
c_st_bit_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00147" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_bit_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_bit_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_st_bit_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_st_bit_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P3 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_severity_level_vector (lowb+1 to lowb+3) <=
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_severity_level_vector (lowb+1 to lowb+3) <=
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_severity_level_vector (lowb+1 to lowb+3) <=
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_severity_level_vector (lowb+1 to lowb+3) <= transport
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_severity_level_vector (lowb+1 to lowb+3) <=
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_severity_level_vector (lowb+1 to lowb+3) <=
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00147" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_severity_level_vector <= transport counter after (1 us - savtime
) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_severity_level_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_st_severity_level_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_st_severity_level_vector = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P4 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_string (lowb+1 to lowb+3) <=
c_st_string_2 (lowb+1 to lowb+3) after 10 ns,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147.P4" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_string (lowb+1 to lowb+3) <=
c_st_string_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_string_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_string (lowb+1 to lowb+3) <=
c_st_string_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_string (lowb+1 to lowb+3) <= transport
c_st_string_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_string (lowb+1 to lowb+3) <=
c_st_string_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_string_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_string (lowb+1 to lowb+3) <=
c_st_string_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00147" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_string <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_string'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P4 ;
--
PGEN_CHKP_4 :
process ( chk_st_string )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions entirely completed",
chk_st_string = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
P5 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_enum1_vector (lowb+1 to lowb+3) <=
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147.P5" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_enum1_vector (lowb+1 to lowb+3) <=
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_enum1_vector (lowb+1 to lowb+3) <=
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_enum1_vector (lowb+1 to lowb+3) <= transport
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_enum1_vector (lowb+1 to lowb+3) <=
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_enum1_vector (lowb+1 to lowb+3) <=
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00147" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_enum1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_enum1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P5 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions entirely completed",
chk_st_enum1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
P6 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_integer_vector (lowb+1 to lowb+3) <=
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147.P6" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_integer_vector (lowb+1 to lowb+3) <=
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_integer_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_integer_vector (lowb+1 to lowb+3) <=
c_st_integer_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_integer_vector (lowb+1 to lowb+3) <= transport
c_st_integer_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_integer_vector (lowb+1 to lowb+3) <=
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_integer_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_integer_vector (lowb+1 to lowb+3) <=
c_st_integer_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00147" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_integer_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_integer_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P6 ;
--
PGEN_CHKP_6 :
process ( chk_st_integer_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions entirely completed",
chk_st_integer_vector = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
P7 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_int1_vector (lowb+1 to lowb+3) <=
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147.P7" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_int1_vector (lowb+1 to lowb+3) <=
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_int1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_int1_vector (lowb+1 to lowb+3) <=
c_st_int1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_int1_vector (lowb+1 to lowb+3) <= transport
c_st_int1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_int1_vector (lowb+1 to lowb+3) <=
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_int1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_int1_vector (lowb+1 to lowb+3) <=
c_st_int1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00147" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_int1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_int1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P7 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Inertial transactions entirely completed",
chk_st_int1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
P8 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_time_vector (lowb+1 to lowb+3) <=
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147.P8" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_time_vector (lowb+1 to lowb+3) <=
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_time_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_time_vector (lowb+1 to lowb+3) <=
c_st_time_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_time_vector (lowb+1 to lowb+3) <= transport
c_st_time_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_time_vector (lowb+1 to lowb+3) <=
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_time_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_time_vector (lowb+1 to lowb+3) <=
c_st_time_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00147" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_time_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_time_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P8 ;
--
PGEN_CHKP_8 :
process ( chk_st_time_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Inertial transactions entirely completed",
chk_st_time_vector = 8 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
P9 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_phys1_vector (lowb+1 to lowb+3) <=
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147.P9" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_phys1_vector (lowb+1 to lowb+3) <=
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_phys1_vector (lowb+1 to lowb+3) <=
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_phys1_vector (lowb+1 to lowb+3) <= transport
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_phys1_vector (lowb+1 to lowb+3) <=
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_phys1_vector (lowb+1 to lowb+3) <=
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00147" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_phys1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_phys1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P9 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Inertial transactions entirely completed",
chk_st_phys1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
P10 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_real_vector (lowb+1 to lowb+3) <=
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147.P10" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real_vector (lowb+1 to lowb+3) <=
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_real_vector (lowb+1 to lowb+3) <=
c_st_real_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real_vector (lowb+1 to lowb+3) <= transport
c_st_real_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real_vector (lowb+1 to lowb+3) <=
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_real_vector (lowb+1 to lowb+3) <=
c_st_real_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00147" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_real_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P10 ;
--
PGEN_CHKP_10 :
process ( chk_st_real_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Inertial transactions entirely completed",
chk_st_real_vector = 8 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
P11 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_real1_vector (lowb+1 to lowb+3) <=
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147.P11" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real1_vector (lowb+1 to lowb+3) <=
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_real1_vector (lowb+1 to lowb+3) <=
c_st_real1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real1_vector (lowb+1 to lowb+3) <= transport
c_st_real1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real1_vector (lowb+1 to lowb+3) <=
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_real1_vector (lowb+1 to lowb+3) <=
c_st_real1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00147" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_real1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P11 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Inertial transactions entirely completed",
chk_st_real1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
P12 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_rec1_vector (lowb+1 to lowb+3) <=
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147.P12" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec1_vector (lowb+1 to lowb+3) <=
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1_vector (lowb+1 to lowb+3) <=
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec1_vector (lowb+1 to lowb+3) <= transport
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec1_vector (lowb+1 to lowb+3) <=
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_rec1_vector (lowb+1 to lowb+3) <=
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00147" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_rec1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P12 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Inertial transactions entirely completed",
chk_st_rec1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
P13 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_rec2_vector (lowb+1 to lowb+3) <=
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147.P13" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec2_vector (lowb+1 to lowb+3) <=
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2_vector (lowb+1 to lowb+3) <=
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec2_vector (lowb+1 to lowb+3) <= transport
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec2_vector (lowb+1 to lowb+3) <=
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_rec2_vector (lowb+1 to lowb+3) <=
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00147" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_rec2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P13 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Inertial transactions entirely completed",
chk_st_rec2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
P14 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_rec3_vector (lowb+1 to lowb+3) <=
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147.P14" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec3_vector (lowb+1 to lowb+3) <=
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3_vector (lowb+1 to lowb+3) <=
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec3_vector (lowb+1 to lowb+3) <= transport
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec3_vector (lowb+1 to lowb+3) <=
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_rec3_vector (lowb+1 to lowb+3) <=
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00147" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_rec3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P14 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Inertial transactions entirely completed",
chk_st_rec3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
P15 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_arr1_vector (lowb+1 to lowb+3) <=
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147.P15" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr1_vector (lowb+1 to lowb+3) <=
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1_vector (lowb+1 to lowb+3) <=
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr1_vector (lowb+1 to lowb+3) <= transport
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr1_vector (lowb+1 to lowb+3) <=
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_arr1_vector (lowb+1 to lowb+3) <=
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00147" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_arr1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P15 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Inertial transactions entirely completed",
chk_st_arr1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
P16 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_arr2_vector (lowb+1 to lowb+3) <=
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147.P16" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr2_vector (lowb+1 to lowb+3) <=
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr2_vector (lowb+1 to lowb+3) <=
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr2_vector (lowb+1 to lowb+3) <= transport
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr2_vector (lowb+1 to lowb+3) <=
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_arr2_vector (lowb+1 to lowb+3) <=
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00147" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_arr2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P16 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Inertial transactions entirely completed",
chk_st_arr2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
P17 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_arr3_vector (lowb+1 to lowb+3) <=
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147.P17" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr3_vector (lowb+1 to lowb+3) <=
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr3_vector (lowb+1 to lowb+3) <=
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr3_vector (lowb+1 to lowb+3) <= transport
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr3_vector (lowb+1 to lowb+3) <=
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_arr3_vector (lowb+1 to lowb+3) <=
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00147" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00147" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_arr3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P17 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Inertial transactions entirely completed",
chk_st_arr3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
--
end ARCH00147 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00147_Test_Bench is
signal s_st_boolean_vector : st_boolean_vector
:= c_st_boolean_vector_1 ;
signal s_st_bit_vector : st_bit_vector
:= c_st_bit_vector_1 ;
signal s_st_severity_level_vector : st_severity_level_vector
:= c_st_severity_level_vector_1 ;
signal s_st_string : st_string
:= c_st_string_1 ;
signal s_st_enum1_vector : st_enum1_vector
:= c_st_enum1_vector_1 ;
signal s_st_integer_vector : st_integer_vector
:= c_st_integer_vector_1 ;
signal s_st_int1_vector : st_int1_vector
:= c_st_int1_vector_1 ;
signal s_st_time_vector : st_time_vector
:= c_st_time_vector_1 ;
signal s_st_phys1_vector : st_phys1_vector
:= c_st_phys1_vector_1 ;
signal s_st_real_vector : st_real_vector
:= c_st_real_vector_1 ;
signal s_st_real1_vector : st_real1_vector
:= c_st_real1_vector_1 ;
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_rec2_vector : st_rec2_vector
:= c_st_rec2_vector_1 ;
signal s_st_rec3_vector : st_rec3_vector
:= c_st_rec3_vector_1 ;
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr3_vector : st_arr3_vector
:= c_st_arr3_vector_1 ;
--
end ENT00147_Test_Bench ;
--
architecture ARCH00147_Test_Bench of ENT00147_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_boolean_vector : inout st_boolean_vector
; s_st_bit_vector : inout st_bit_vector
; s_st_severity_level_vector : inout st_severity_level_vector
; s_st_string : inout st_string
; s_st_enum1_vector : inout st_enum1_vector
; s_st_integer_vector : inout st_integer_vector
; s_st_int1_vector : inout st_int1_vector
; s_st_time_vector : inout st_time_vector
; s_st_phys1_vector : inout st_phys1_vector
; s_st_real_vector : inout st_real_vector
; s_st_real1_vector : inout st_real1_vector
; s_st_rec1_vector : inout st_rec1_vector
; s_st_rec2_vector : inout st_rec2_vector
; s_st_rec3_vector : inout st_rec3_vector
; s_st_arr1_vector : inout st_arr1_vector
; s_st_arr2_vector : inout st_arr2_vector
; s_st_arr3_vector : inout st_arr3_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00147 ( ARCH00147 ) ;
begin
CIS1 : UUT
port map (
s_st_boolean_vector
, s_st_bit_vector
, s_st_severity_level_vector
, s_st_string
, s_st_enum1_vector
, s_st_integer_vector
, s_st_int1_vector
, s_st_time_vector
, s_st_phys1_vector
, s_st_real_vector
, s_st_real1_vector
, s_st_rec1_vector
, s_st_rec2_vector
, s_st_rec3_vector
, s_st_arr1_vector
, s_st_arr2_vector
, s_st_arr3_vector
) ;
end block L1 ;
end ARCH00147_Test_Bench ;
|
--
-- Copyright 2012 Jared Boone
-- Copyright 2013 Benjamin Vernoux
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity top is
Port(
HOST_DATA : inout std_logic_vector(7 downto 0);
HOST_CAPTURE : out std_logic;
HOST_SYNC_EN : in std_logic;
HOST_SYNC_CMD : out std_logic;
HOST_SYNC : in std_logic;
HOST_DISABLE : in std_logic;
HOST_DIRECTION : in std_logic;
HOST_Q_INVERT : in std_logic;
DA : in std_logic_vector(7 downto 0);
DD : out std_logic_vector(9 downto 0);
CODEC_CLK : in std_logic;
CODEC_X2_CLK : in std_logic
);
end top;
architecture Behavioral of top is
signal codec_clk_rx_i : std_logic;
signal codec_clk_tx_i : std_logic;
signal adc_data_i : std_logic_vector(7 downto 0);
signal dac_data_o : std_logic_vector(9 downto 0);
signal host_clk_i : std_logic;
type transfer_direction is (from_adc, to_dac);
signal transfer_direction_i : transfer_direction;
signal host_data_enable_i : std_logic;
signal host_data_capture_o : std_logic;
signal host_sync_enable : std_logic := '0';
signal host_sync_o : std_logic := '0';
signal host_sync_i : std_logic := '0';
signal host_sync_latched : std_logic := '0';
signal data_from_host_i : std_logic_vector(7 downto 0);
signal data_to_host_o : std_logic_vector(7 downto 0);
signal q_invert : std_logic;
signal rx_q_invert_mask : std_logic_vector(7 downto 0);
signal tx_q_invert_mask : std_logic_vector(7 downto 0);
begin
------------------------------------------------
-- Codec interface
DD(9 downto 0) <= dac_data_o;
------------------------------------------------
-- Clocks
BUFG_host : BUFG
port map (
O => host_clk_i,
I => CODEC_X2_CLK
);
------------------------------------------------
-- SGPIO interface
HOST_DATA <= data_to_host_o when transfer_direction_i = from_adc
else (others => 'Z');
HOST_CAPTURE <= host_data_capture_o;
host_sync_enable <= HOST_SYNC_EN;
host_sync_i <= HOST_SYNC;
HOST_SYNC_CMD <= host_sync_o;
host_data_enable_i <= not HOST_DISABLE;
transfer_direction_i <= to_dac when HOST_DIRECTION = '1'
else from_adc;
------------------------------------------------
q_invert <= HOST_Q_INVERT;
rx_q_invert_mask <= X"80" when q_invert = '1' else X"7f";
tx_q_invert_mask <= X"7f" when q_invert = '1' else X"80";
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
codec_clk_rx_i <= CODEC_CLK;
adc_data_i <= DA(7 downto 0);
if (transfer_direction_i = from_adc) then
if codec_clk_rx_i = '1' then
-- I: non-inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor X"80";
else
-- Q: inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor rx_q_invert_mask;
end if;
end if;
end if;
end process;
process(host_clk_i)
begin
if falling_edge(host_clk_i) then
codec_clk_tx_i <= CODEC_CLK;
data_from_host_i <= HOST_DATA;
if transfer_direction_i = to_dac then
if codec_clk_tx_i = '1' then
dac_data_o <= (data_from_host_i xor tx_q_invert_mask) & tx_q_invert_mask(0) & tx_q_invert_mask(0);
else
dac_data_o <= (data_from_host_i xor X"80") & "00";
end if;
else
dac_data_o <= (dac_data_o'high => '0', others => '1');
end if;
end if;
end process;
process (host_data_enable_i, host_sync_i)
begin
host_sync_o <= host_data_enable_i;
if host_data_enable_i = '1' then
if rising_edge(host_sync_i) then
host_sync_latched <= host_sync_i;
end if;
else
host_sync_latched <= '0';
end if;
end process;
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if transfer_direction_i = to_dac then
if codec_clk_tx_i = '1' then
host_data_capture_o <= host_data_enable_i and (host_sync_latched or not host_sync_enable);
end if;
else
if codec_clk_rx_i = '1' then
host_data_capture_o <= host_data_enable_i and (host_sync_latched or not host_sync_enable);
end if;
end if;
end if;
end process;
end Behavioral;
|
--
-- Copyright 2012 Jared Boone
-- Copyright 2013 Benjamin Vernoux
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity top is
Port(
HOST_DATA : inout std_logic_vector(7 downto 0);
HOST_CAPTURE : out std_logic;
HOST_SYNC_EN : in std_logic;
HOST_SYNC_CMD : out std_logic;
HOST_SYNC : in std_logic;
HOST_DISABLE : in std_logic;
HOST_DIRECTION : in std_logic;
HOST_Q_INVERT : in std_logic;
DA : in std_logic_vector(7 downto 0);
DD : out std_logic_vector(9 downto 0);
CODEC_CLK : in std_logic;
CODEC_X2_CLK : in std_logic
);
end top;
architecture Behavioral of top is
signal codec_clk_rx_i : std_logic;
signal codec_clk_tx_i : std_logic;
signal adc_data_i : std_logic_vector(7 downto 0);
signal dac_data_o : std_logic_vector(9 downto 0);
signal host_clk_i : std_logic;
type transfer_direction is (from_adc, to_dac);
signal transfer_direction_i : transfer_direction;
signal host_data_enable_i : std_logic;
signal host_data_capture_o : std_logic;
signal host_sync_enable : std_logic := '0';
signal host_sync_o : std_logic := '0';
signal host_sync_i : std_logic := '0';
signal host_sync_latched : std_logic := '0';
signal data_from_host_i : std_logic_vector(7 downto 0);
signal data_to_host_o : std_logic_vector(7 downto 0);
signal q_invert : std_logic;
signal rx_q_invert_mask : std_logic_vector(7 downto 0);
signal tx_q_invert_mask : std_logic_vector(7 downto 0);
begin
------------------------------------------------
-- Codec interface
DD(9 downto 0) <= dac_data_o;
------------------------------------------------
-- Clocks
BUFG_host : BUFG
port map (
O => host_clk_i,
I => CODEC_X2_CLK
);
------------------------------------------------
-- SGPIO interface
HOST_DATA <= data_to_host_o when transfer_direction_i = from_adc
else (others => 'Z');
HOST_CAPTURE <= host_data_capture_o;
host_sync_enable <= HOST_SYNC_EN;
host_sync_i <= HOST_SYNC;
HOST_SYNC_CMD <= host_sync_o;
host_data_enable_i <= not HOST_DISABLE;
transfer_direction_i <= to_dac when HOST_DIRECTION = '1'
else from_adc;
------------------------------------------------
q_invert <= HOST_Q_INVERT;
rx_q_invert_mask <= X"80" when q_invert = '1' else X"7f";
tx_q_invert_mask <= X"7f" when q_invert = '1' else X"80";
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
codec_clk_rx_i <= CODEC_CLK;
adc_data_i <= DA(7 downto 0);
if (transfer_direction_i = from_adc) then
if codec_clk_rx_i = '1' then
-- I: non-inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor X"80";
else
-- Q: inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor rx_q_invert_mask;
end if;
end if;
end if;
end process;
process(host_clk_i)
begin
if falling_edge(host_clk_i) then
codec_clk_tx_i <= CODEC_CLK;
data_from_host_i <= HOST_DATA;
if transfer_direction_i = to_dac then
if codec_clk_tx_i = '1' then
dac_data_o <= (data_from_host_i xor tx_q_invert_mask) & tx_q_invert_mask(0) & tx_q_invert_mask(0);
else
dac_data_o <= (data_from_host_i xor X"80") & "00";
end if;
else
dac_data_o <= (dac_data_o'high => '0', others => '1');
end if;
end if;
end process;
process (host_data_enable_i, host_sync_i)
begin
host_sync_o <= host_data_enable_i;
if host_data_enable_i = '1' then
if rising_edge(host_sync_i) then
host_sync_latched <= host_sync_i;
end if;
else
host_sync_latched <= '0';
end if;
end process;
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if transfer_direction_i = to_dac then
if codec_clk_tx_i = '1' then
host_data_capture_o <= host_data_enable_i and (host_sync_latched or not host_sync_enable);
end if;
else
if codec_clk_rx_i = '1' then
host_data_capture_o <= host_data_enable_i and (host_sync_latched or not host_sync_enable);
end if;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
-- Company : HSLU
-- Engineer : Gai, Waj
--
-- Create Date: 26-May-11
-- Project : RT Video Lab 1: Exercise 3
-- Description: Components for 2D 5x5-FIR filter
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Multiplier
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
entity MULT is
generic(
DW_IN_1 : integer;
DW_IN_2 : integer;
DELAY : integer
);
port(
ce_1 : in std_logic;
clk_1 : in std_logic;
FACTOR_IN_1 : in std_logic_vector(DW_IN_1-1 downto 0);
FACTOR_IN_2 : in std_logic_vector(DW_IN_2-1 downto 0);
PRODUCT_OUT : out std_logic_vector((DW_IN_1 + DW_IN_2 - 1) downto 0)
);
end MULT;
architecture structural of MULT is
type DELAY_TYPE is array(DELAY-1 downto 0) of std_logic_vector((DW_IN_1 + DW_IN_2 - 1) downto 0);
signal FACTOR_1_BUF : unsigned(DW_IN_1-1 downto 0);
signal FACTOR_2_BUF : unsigned(DW_IN_2-1 downto 0);
signal DelayLine : DELAY_TYPE := (others => (others => '0'));
begin
FACTOR_1_BUF <= unsigned(FACTOR_IN_1);
FACTOR_2_BUF <= unsigned(FACTOR_IN_2);
x0_multiply : process(clk_1)
begin
if clk_1'event and clk_1 = '1' then
if ce_1 = '1' then
DelayLine(DELAY-1) <= std_logic_vector(FACTOR_1_BUF * FACTOR_2_BUF);
DelayLine(DELAY-2 downto 0) <= DelayLine(DELAY-1 downto 1);
PRODUCT_OUT <= DelayLine(0);
end if;
end if;
end process x0_multiply;
end structural;
-------------------------------------------------------------------------------
-- Adder
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
entity ADDER is
generic(
DW_IN : integer
);
port(
ce_1 : in std_logic;
clk_1 : in std_logic;
S_IN_1 : in std_logic_vector(DW_IN-1 downto 0);
S_IN_2 : in std_logic_vector(DW_IN-1 downto 0);
SUM_OUT : out std_logic_vector(DW_IN downto 0)
);
end ADDER;
architecture structural of ADDER is
signal IN_Sign1 : signed(DW_IN downto 0);
signal IN_Sign2 : signed(DW_IN downto 0);
begin
-- sign-extension of inputs
IN_Sign1 <= signed(S_IN_1(DW_IN-1) & '1' & S_IN_1(DW_IN-2 downto 0)) when S_IN_1(DW_IN-1) = '1' else
signed(S_IN_1(DW_IN-1) & '0' & S_IN_1(DW_IN-2 downto 0));
IN_Sign2 <= signed(S_IN_2(DW_IN-1) & '1' & S_IN_2(DW_IN-2 downto 0)) when S_IN_2(DW_IN-1) = '1' else
signed(S_IN_2(DW_IN-1) & '0' & S_IN_2(DW_IN-2 downto 0));
x0_ADD : process(clk_1)
begin
if clk_1'event and clk_1 = '1' then
if ce_1 = '1' then
SUM_OUT <= std_logic_vector(signed(IN_Sign1 + IN_Sign2));
end if;
end if;
end process x0_ADD;
end structural;
-------------------------------------------------------------------------------
-- absolute Value
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
entity ABS_VAL is
generic(
DW: integer
);
port(
ce_1 : in std_logic;
clk_1 : in std_logic;
VAL_IN : in std_logic_vector(DW-1 downto 0);
VAL_OUT : out std_logic_vector(DW-1 downto 0)
);
end ABS_VAL;
architecture structural of ABS_VAL is
signal OutReg : std_logic_vector(DW-1 downto 0);
begin
x0_abs : process(clk_1)
begin
if clk_1'event and clk_1 = '1' then
if ce_1 = '1' then
-- :ToDo: ------------------------------------------------------------
-- Implement logic to generate absolute value of VAL_IN
-----------------------------------------------------------------------
OutReg <= .....
-- additional output register
VAL_OUT <= OutReg;
end if;
end if;
end process x0_abs;
end structural;
-------------------------------------------------------------------------------
-- Pipeline register
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
entity Pipeline_Reg is
generic(
DW_IN : integer
);
port(
clk_1 : in std_logic;
en : in std_logic;
D : in std_logic_vector(DW_IN-1 downto 0);
Q : out std_logic_vector(DW_IN-1 downto 0)
);
end Pipeline_Reg;
architecture structural of Pipeline_Reg is
begin
p_reg : process(clk_1)
begin
if clk_1'event and clk_1 = '1' then
if en = '1' then
Q <= D;
end if;
end if;
end process p_reg;
end structural;
-------------------------------------------------------------------------------
-- Truncation/Saturation unit
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
entity CONVERT is
generic(
DW_IN : integer;
DW_OUT : integer;
BIN_PNT : integer
);
port(
clk_1 : in std_logic;
ce_1 : in std_logic;
din : in std_logic_vector(DW_IN-1 downto 0);
dout : out std_logic_vector(DW_OUT-1 downto 0)
);
end CONVERT;
architecture structural of CONVERT is
begin
x0_CONV : process(clk_1)
begin
if clk_1'event and clk_1 = '1' then
if ce_1 = '1' then
-- :ToDo: ------------------------------------------------------------
-- Implement logic to scale the unsigned value din, which has a total
-- number of DW_IN bits and BIN_PNT fractional bits, such that
-- a) dout has a total number of DW_OUT bits and zero fractional bits
-- b) saturation is applied if the value of din exceeds the maximum
-- unsigned value of dout
-----------------------------------------------------------------------
dout <= .....
end if;
end if;
end process;
end structural;
|
--!
--! @file: exercise5_13.vhd
--! @brief: barrel shifter with std_logic_vector
--! @author: Antonio Gutierrez
--! @date: 2013-10-23
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity barrel_shifter is
generic (N: integer := 8;
M: integer := 3);
port (
x: in std_logic(N-1 downto 0);
shift: in std_logic_vector(M-1 downto 0);
y: out std_logic_vector(N-1 downto 0));
end entity barrel_shifter;
--------------------------------------
architecture circuit of barrel_shifter is
signal shift_uns: unsigned;
begin
shift_uns <= unsigned(shift);
with shift_uns select
y <= x when 0,
x rol shift_uns when others;
end architecture circuit;
--------------------------------------
|
library verilog;
use verilog.vl_types.all;
entity finalproject_mm_interconnect_0_router_003 is
port(
clk : in vl_logic;
reset : in vl_logic;
sink_valid : in vl_logic;
sink_data : in vl_logic_vector(104 downto 0);
sink_startofpacket: in vl_logic;
sink_endofpacket: in vl_logic;
sink_ready : out vl_logic;
src_valid : out vl_logic;
src_data : out vl_logic_vector(104 downto 0);
src_channel : out vl_logic_vector(5 downto 0);
src_startofpacket: out vl_logic;
src_endofpacket : out vl_logic;
src_ready : in vl_logic
);
end finalproject_mm_interconnect_0_router_003;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_10;
USE proc_sys_reset_v5_0_10.proc_sys_reset;
ENTITY mig_wrap_proc_sys_reset_1_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END mig_wrap_proc_sys_reset_1_0;
ARCHITECTURE mig_wrap_proc_sys_reset_1_0_arch OF mig_wrap_proc_sys_reset_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF mig_wrap_proc_sys_reset_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "virtex7",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '1',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END mig_wrap_proc_sys_reset_1_0_arch;
|
--8线-3线优先编码器。A的编码等级最低
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY ENCODER IS
PORT(A,B,C,D,E,F,G,H:IN STD_LOGIC;
Y0,Y1,Y2:OUT STD_LOGIC);
END ENTITY ENCODER;
--使用条件赋值语句
ARCHITECTURE ART1 OF ENCODER IS
SIGNAL SY:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
--优先级在此处体现，哈哈
SY(2 DOWNTO 0)<="111" WHEN H='1' ELSE
"110" WHEN G='1' ELSE
"101" WHEN F='1' ELSE
"100" WHEN E='1' ELSE
"011" WHEN D='1' ELSE
"010" WHEN C='1' ELSE
"001" WHEN B='1' ELSE
"000" WHEN A='1' ELSE
"XXX";
Y0<=SY(0);
Y1<=SY(1);
Y2<=SY(2);
END ARCHITECTURE ART1;
--使用LOOP语句
ARCHITECTURE ART2 OF ENCODER IS
BEGIN
PROCESS(A,B,C,D,E,F,G) IS
VARIABLE VSR:STD_LOGIC_VECTOR(7 DOWNTO 0);
VARIABLE I:INTEGER;
BEGIN
VSR:=(H,G,F,E,D,C,B,A);
I:=7;
--不等号是/=,你敢信？
WHILE I>=0 AND VSR(I)/='1' LOOP
I:=I-1;
END LOOP;
(Y2,Y1,Y0)<=CONV_STD_LOGIC_VECTOR(I,3);
END PROCESS;
END ARCHITECTURE ART2;
--使用IF条件语句
ARCHITECTURE ART3 OF ENCODER IS
SIGNAL SY:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
PROCESS(H,G,F,E,D,C,B,A) IS
BEGIN
IF H='1' THEN SY<="111";
ELSIF G='1' THEN SY<="110";
ELSIF F='1' THEN SY<="101";
ELSIF E='1' THEN SY<="100";
ELSIF D='1' THEN SY<="011";
ELSIF C='1' THEN SY<="010";
ELSIF B='1' THEN SY<="001";
ELSIF A='1' THEN SY<="000";
ELSE SY<="XXX";
END IF;
END PROCESS;
Y0<=SY(0);
Y1<=SY(1);
Y2<=SY(2);
END ARCHITECTURE ART3;
|
-- Transmitter, part of UART.
--
-- Part of MARK II project. For informations about license, please
-- see file /LICENSE .
--
-- author: Vladislav Mlejnecký
-- email: [email protected]
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity transmitter is
port(
en: in std_logic;
clk: in std_logic;
res: in std_logic;
baud16_clk_en: in std_logic;
tx_data: in unsigned(7 downto 0);
tx: out std_logic;
tx_dcfifo_rdreq: out std_logic;
tx_dcfifo_rdusedw: in std_logic_vector(5 downto 0);
tx_sended: out std_logic
);
end entity transmitter;
architecture transmitter_arch of transmitter is
signal count: unsigned(3 downto 0);
signal baud_clk_en: std_logic;
type tx_state_type is (idle,sample_data_0, sample_data_1, set_startbit, wait_startbit, set_b0, wait_b0, set_b1, wait_b1,
set_b2, wait_b2, set_b3, wait_b3, set_b4, wait_b4, set_b5, wait_b5,
set_b6, wait_b6, set_b7, wait_b7, set_stopbit, wait_stopbit, set_flags);
signal state: tx_state_type;
signal send_reg, send_started: std_logic;
signal shift_data, load_data: std_logic;
signal sync_counter: std_logic;
begin
txcounter:
process(clk, res) is
variable counter: unsigned(3 downto 0);
begin
if rising_edge(clk) then
if res = '1' then
counter := (others => '0');
elsif sync_counter = '1' then
counter := (others => '0');
elsif baud16_clk_en = '1' then
counter := counter + 1;
end if;
end if;
count <= counter;
end process;
process(count, baud16_clk_en) is
begin
if count = x"F" then
baud_clk_en <= baud16_clk_en;
else
baud_clk_en <= '0';
end if;
end process;
process(clk, res, baud_clk_en, tx_dcfifo_rdusedw) is begin
if rising_edge(clk) then
if res = '1' then
state <= idle;
else
case state is
when idle =>
if ((tx_dcfifo_rdusedw /= "000000") and (en = '1')) then
state <= sample_data_0;
else
state <= idle;
end if;
when sample_data_0 => state <= sample_data_1;
when sample_data_1 => state <= set_startbit;
when set_startbit => state <= wait_startbit;
when wait_startbit =>
if baud_clk_en = '1' then
state <= set_b0;
else
state <= wait_startbit;
end if;
when set_b0 => state <= wait_b0;
when wait_b0 =>
if baud_clk_en = '1' then
state <= set_b1;
else
state <= wait_b0;
end if;
when set_b1 => state <= wait_b1;
when wait_b1 =>
if baud_clk_en = '1' then
state <= set_b2;
else
state <= wait_b1;
end if;
when set_b2 => state <= wait_b2;
when wait_b2 =>
if baud_clk_en = '1' then
state <= set_b3;
else
state <= wait_b2;
end if;
when set_b3 => state <= wait_b3;
when wait_b3 =>
if baud_clk_en = '1' then
state <= set_b4;
else
state <= wait_b3;
end if;
when set_b4 => state <= wait_b4;
when wait_b4 =>
if baud_clk_en = '1' then
state <= set_b5;
else
state <= wait_b4;
end if;
when set_b5 => state <= wait_b5;
when wait_b5 =>
if baud_clk_en = '1' then
state <= set_b6;
else
state <= wait_b5;
end if;
when set_b6 => state <= wait_b6;
when wait_b6 =>
if baud_clk_en = '1' then
state <= set_b7;
else
state <= wait_b6;
end if;
when set_b7 => state <= wait_b7;
when wait_b7 =>
if baud_clk_en = '1' then
state <= set_stopbit;
else
state <= wait_b7;
end if;
when set_stopbit => state <= wait_stopbit;
when wait_stopbit =>
if baud_clk_en = '1' then
state <= set_flags;
else
state <= wait_stopbit;
end if;
when set_flags => state <= idle;
end case;
end if;
end if;
end process;
process(state) is begin
case state is
when idle =>
shift_data <= '0'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when sample_data_0 =>
shift_data <= '0'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '1'; tx_sended <= '0';
when sample_data_1 =>
shift_data <= '0'; load_data <= '1'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when set_startbit =>
shift_data <= '1'; load_data <= '0'; sync_counter <= '1'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when wait_startbit =>
shift_data <= '0'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when set_b0 =>
shift_data <= '1'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when wait_b0 =>
shift_data <= '0'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when set_b1 =>
shift_data <= '1'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when wait_b1 =>
shift_data <= '0'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when set_b2 =>
shift_data <= '1'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when wait_b2 =>
shift_data <= '0'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when set_b3 =>
shift_data <= '1'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when wait_b3 =>
shift_data <= '0'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when set_b4 =>
shift_data <= '1'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when wait_b4 =>
shift_data <= '0'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when set_b5 =>
shift_data <= '1'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when wait_b5 =>
shift_data <= '0'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when set_b6 =>
shift_data <= '1'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when wait_b6 =>
shift_data <= '0'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when set_b7 =>
shift_data <= '1'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when wait_b7 =>
shift_data <= '0'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when set_stopbit =>
shift_data <= '1'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when wait_stopbit =>
shift_data <= '0'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when set_flags =>
shift_data <= '0'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '1';
end case;
end process;
process(clk, res, shift_data, load_data) is
variable data: std_logic_vector(10 downto 0);
begin
if rising_edge(clk) then
if res = '1' then
data := (others => '1');
elsif load_data = '1' then
data := '1' & std_logic_vector(tx_data) & '0' & '1';
elsif shift_data = '1' then
data(9 downto 0) := data(10 downto 1);
data(10) := '1';
end if;
end if;
tx <= data(0);
end process;
end architecture transmitter_arch;
|
library ieee;
use ieee.std_logic_1164.all;
-- Add your library and packages declaration here ...
entity rslatch_tb is
end rslatch_tb;
architecture TB_ARCHITECTURE of rslatch_tb is
-- Component declaration of the tested unit
component rs_latch_param
port(
S : in STD_LOGIC;
R : in STD_LOGIC;
Q : out STD_LOGIC;
nQ : out STD_LOGIC );
end component;
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal S : STD_LOGIC;
signal R : STD_LOGIC;
-- Observed signals - signals mapped to the output ports of tested entity
signal Q : STD_LOGIC;
signal nQ : STD_LOGIC;
-- Add your code here ...
begin
-- Unit Under Test port map
UUT : rs_latch_param
port map (
S => S,
R => R,
Q => Q,
nQ => nQ
);
process
begin
S <= '0';
wait for 10ns;
S <= '1';
wait for 10ns;
end process;
process
begin
R <= '0';
wait for 20ns;
R <= '1';
wait for 20ns;
end process;
-- Add your stimulus here ...
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_rslatch of rslatch_tb is
for TB_ARCHITECTURE
for UUT : rs_latch_param
use entity work.rs_latch_param(struct);
end for;
end for;
end TESTBENCH_FOR_rslatch;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Package: tech_leonardo
-- File: tech_leonardo.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: Library of ram generators for inference by Leonardo
--
------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.std_logic_1164.all;
package tech_leonardo is
-- sync ram
component leonardo_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
address : in std_logic_vector((abits -1) downto 0);
clk : in std_logic;
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_logic;
write : in std_logic
);
end component;
-- regfile generators
component leonardo_regfile_ss -- sync read, sync write
generic (
abits : integer := 8; dbits : integer := 32; words : integer := 128
);
port (
clk : in std_logic;
datain : in std_logic_vector (dbits -1 downto 0);
raddr1 : in std_logic_vector (abits -1 downto 0);
raddr2 : in std_logic_vector (abits -1 downto 0);
waddr : in std_logic_vector (abits -1 downto 0);
enable : in std_logic;
write : in std_logic;
dataout1 : out std_logic_vector (dbits -1 downto 0);
dataout2 : out std_logic_vector (dbits -1 downto 0));
end component;
component leonardo_regfile_as -- async read, sync write
generic (
abits : integer := 8; dbits : integer := 32; words : integer := 128
);
port (
clk : in std_logic;
datain : in std_logic_vector (dbits -1 downto 0);
raddr1 : in std_logic_vector (abits -1 downto 0);
raddr2 : in std_logic_vector (abits -1 downto 0);
waddr : in std_logic_vector (abits -1 downto 0);
enable : in std_logic;
write : in std_logic;
dataout1 : out std_logic_vector (dbits -1 downto 0);
dataout2 : out std_logic_vector (dbits -1 downto 0));
end component;
end tech_leonardo;
-- async dpram for leonardo
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity leonardo_dpram_as is
generic (
abits : integer := 8;
dbits : integer := 32;
words : integer := 256
);
port (
clk : in std_logic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_logic;
q: out std_logic_vector (dbits -1 downto 0)
);
end;
architecture behav of leonardo_dpram_as is
subtype dword is std_logic_vector(dbits -1 downto 0);
type dregtype is array (0 to words - 1) of DWord;
signal rfd : dregtype;
begin
rp : process(clk, rdaddress, rfd)
begin
if rising_edge(clk) then
if wren = '1' then
-- pragma translate_off
if not ( is_x(wraddress) or
(conv_integer(unsigned(wraddress)) >= words))
then
-- pragma translate_on
rfd(conv_integer(unsigned(wraddress))) <= data;
-- pragma translate_off
end if;
-- pragma translate_on
end if;
end if;
-- pragma translate_off
if not ( is_x(rdaddress) or
(conv_integer(unsigned(rdaddress)) >= words))
then
-- pragma translate_on
q <= rfd(conv_integer(unsigned(rdaddress)));
-- pragma translate_off
else
q <= (others => 'X');
end if;
-- pragma translate_on
end process;
end;
-- sync dpram for leonardo
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity leonardo_dpram_ss is
generic (
abits : integer := 8;
dbits : integer := 32;
words : integer := 256
);
port (
clk : in std_logic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_logic;
q: out std_logic_vector (dbits -1 downto 0)
);
end;
architecture behav of leonardo_dpram_ss is
subtype dword is std_logic_vector(dbits -1 downto 0);
type dregtype is array (0 to words - 1) of DWord;
signal rfd : dregtype;
begin
rp : process(clk, rdaddress, rfd)
begin
if rising_edge(clk) then
if wren = '1' then
-- pragma translate_off
if not ( is_x(wraddress) or
(conv_integer(unsigned(wraddress)) >= words))
then
-- pragma translate_on
rfd(conv_integer(unsigned(wraddress))) <= data;
-- pragma translate_off
end if;
-- pragma translate_on
end if;
-- pragma translate_off
if not ( is_x(rdaddress) or
(conv_integer(unsigned(rdaddress)) >= words) or
((wren = '1') and (wraddress = rdaddress)))
then
-- pragma translate_on
q <= rfd(conv_integer(unsigned(rdaddress)));
-- pragma translate_off
else
q <= (others => 'X');
end if;
-- pragma translate_on
end if;
end process;
end;
-- synchronous ram for leonardo
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity leonardo_syncram is
generic (
abits : integer := 10;
dbits : integer := 8
);
port (
address : in std_logic_vector((abits -1) downto 0);
clk : in std_logic;
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_logic;
write : in std_logic
);
end;
architecture behavioral of leonardo_syncram is
subtype word is std_logic_vector((dbits -1) downto 0);
type mem is array(0 to (2**abits -1)) of word;
signal memarr : mem;
signal ra : std_logic_vector((abits -1) downto 0);
begin
main : process(clk, memarr, ra)
begin
if rising_edge(clk) then
ra <= address;
if write = '1' then
-- pragma translate_off
if not is_x(address) then
-- pragma translate_on
memarr(conv_integer(unsigned(address))) <= datain;
-- pragma translate_off
end if;
-- pragma translate_on
end if;
end if;
-- pragma translate_off
if not is_x(ra) then
-- pragma translate_on
dataout <= memarr(conv_integer(unsigned(ra)));
-- pragma translate_off
end if;
-- pragma translate_on
end process;
end;
--------------------------------------------------------------------
-- regfile generators
--------------------------------------------------------------------
LIBRARY ieee;
use IEEE.std_logic_1164.all;
entity leonardo_regfile_ss is
generic (
abits : integer := 8; dbits : integer := 32; words : integer := 128
);
port (
clk : in std_logic;
datain : in std_logic_vector (dbits -1 downto 0);
raddr1 : in std_logic_vector (abits -1 downto 0);
raddr2 : in std_logic_vector (abits -1 downto 0);
waddr : in std_logic_vector (abits -1 downto 0);
enable : in std_logic;
write : in std_logic;
dataout1 : out std_logic_vector (dbits -1 downto 0);
dataout2 : out std_logic_vector (dbits -1 downto 0));
end;
architecture rtl of leonardo_regfile_ss is
component leonardo_dpram_ss
generic (
abits : integer := 8;
dbits : integer := 32;
words : integer := 256
);
port (
clk : in std_logic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_logic;
q: out std_logic_vector (dbits -1 downto 0)
);
end component;
begin
u0 : leonardo_dpram_ss
generic map (abits => abits, dbits => dbits, words => words)
port map (clk => clk, rdaddress => raddr1, wraddress => waddr,
data => datain, wren => write, q => dataout1);
u1 : leonardo_dpram_ss
generic map (abits => abits, dbits => dbits, words => words)
port map (clk => clk, rdaddress => raddr2, wraddress => waddr,
data => datain, wren => write, q => dataout2);
end;
LIBRARY ieee;
use IEEE.std_logic_1164.all;
entity leonardo_regfile_as is
generic (
abits : integer := 8; dbits : integer := 32; words : integer := 128
);
port (
clk : in std_logic;
datain : in std_logic_vector (dbits -1 downto 0);
raddr1 : in std_logic_vector (abits -1 downto 0);
raddr2 : in std_logic_vector (abits -1 downto 0);
waddr : in std_logic_vector (abits -1 downto 0);
enable : in std_logic;
write : in std_logic;
dataout1 : out std_logic_vector (dbits -1 downto 0);
dataout2 : out std_logic_vector (dbits -1 downto 0));
end;
architecture rtl of leonardo_regfile_as is
component leonardo_dpram_as
generic (
abits : integer := 8;
dbits : integer := 32;
words : integer := 256
);
port (
clk : in std_logic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_logic;
q: out std_logic_vector (dbits -1 downto 0)
);
end component;
begin
u0 : leonardo_dpram_as
generic map (abits => abits, dbits => dbits, words => words)
port map (clk => clk, rdaddress => raddr1, wraddress => waddr,
data => datain, wren => write, q => dataout1);
u1 : leonardo_dpram_as
generic map (abits => abits, dbits => dbits, words => words)
port map (clk => clk, rdaddress => raddr2, wraddress => waddr,
data => datain, wren => write, q => dataout2);
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:40:27 04/09/2017
-- Design Name:
-- Module Name: anode_fsm - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity anode_fsm is
Port ( clk : in STD_LOGIC;
anode_o : out STD_LOGIC_VECTOR (3 downto 0);
reset : in STD_LOGIC);
end anode_fsm;
architecture Behavioral of anode_fsm is
type control is (an3,an2,an1,an0);
signal next_state :control;
begin
process(clk, next_state)
begin
if (clk' event and clk='1') then
case next_state is
when an3 =>
if reset ='1' then
next_state <=an3;
else
anode_o <= "0111";
next_state <= an2;
end if;
when an2 =>
if reset ='1' then
next_state <=an3;
else
anode_o <= "1011";
next_state <= an1;
end if;
when an1 =>
if reset ='1' then
next_state <=an3;
else
anode_o <= "1101";
next_state <= an0;
end if;
when an0 =>
if reset ='1' then
next_state <= an3;
else
anode_o <= "1110";
next_state <= an3;
end if;
end case;
end if;
end process;
end Behavioral;
|
-- Module Name: InputGate - Behavioral
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
entity test is
port (
a : in std_logic;
b : in std_logic;
c : out std_logic );
end test;
architecture Behavioral of test is
begin
c <= a and b;
end Behavioral;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:51:15 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top ip_design_auto_pc_0 -prefix
-- ip_design_auto_pc_0_ ip_design_auto_pc_0_stub.vhdl
-- Design : ip_design_auto_pc_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ip_design_auto_pc_0 is
Port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end ip_design_auto_pc_0;
architecture stub of ip_design_auto_pc_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "axi_protocol_converter_v2_1_14_axi_protocol_converter,Vivado 2017.3";
begin
end;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ov7670_controller:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_ov7670_controller_0_0 IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END system_ov7670_controller_0_0;
ARCHITECTURE system_ov7670_controller_0_0_arch OF system_ov7670_controller_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ov7670_controller_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT ov7670_controller IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END COMPONENT ov7670_controller;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_ov7670_controller_0_0_arch: ARCHITECTURE IS "ov7670_controller,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_ov7670_controller_0_0_arch : ARCHITECTURE IS "system_ov7670_controller_0_0,ov7670_controller,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_ov7670_controller_0_0_arch: ARCHITECTURE IS "system_ov7670_controller_0_0,ov7670_controller,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=ov7670_controller,x_ipVersion=1.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
BEGIN
U0 : ov7670_controller
PORT MAP (
clk => clk,
resend => resend,
config_finished => config_finished,
sioc => sioc,
siod => siod,
reset => reset,
pwdn => pwdn,
xclk => xclk
);
END system_ov7670_controller_0_0_arch;
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