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// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
Test #(16,2) test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hf9b3a5000165ed38
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
input clk;
input [31:0] in;
output [31:0] out;
parameter N = 0;
parameter PASSDOWN = 1;
add #(PASSDOWN) add (.in (in[(2*N)-1:(0*N)]),
.out (out));
endmodule
module add (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
parameter PASSDOWN = 9999;
input [31:0] in;
output [31:0] out;
wire out = in + PASSDOWN;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
parameter PAR = 3;
input clk;
defparam i.L00 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L01 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L02 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L03 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L04 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L05 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L06 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L07 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L08 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L09 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L0A = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L0B = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L0C = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L0D = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L0E = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L0F = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L10 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L11 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L12 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L13 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L14 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L15 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L16 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L17 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L18 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L19 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L1A = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L1B = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L1C = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L1D = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L1E = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L1F = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L20 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L21 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L22 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L23 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L24 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L25 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L26 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L27 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L28 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L29 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L2A = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L2B = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L2C = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L2D = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L2E = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L2F = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L30 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L31 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L32 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L33 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L34 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L35 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L36 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L37 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L38 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L39 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L3A = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L3B = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L3C = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L3D = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L3E = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L3F = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.A0 = "HELLO_WORLD_BOY_THIS_IS_LONG";
defparam i.A1 = "HELLO_WORLD_BOY_THIS_IS_LONG";
defparam i.A2 = "HELLO_WORLD_BOY_THIS_IS_LONG";
i i (.clk(clk));
integer cyc=1;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==1) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module i
(/*AUTOARG*/
// Inputs
clk
);
// verilator public_module
input clk;
parameter [255:0] L00 = 256'h0;
parameter [255:0] L01 = 256'h0;
parameter [255:0] L02 = 256'h0;
parameter [255:0] L03 = 256'h0;
parameter [255:0] L04 = 256'h0;
parameter [255:0] L05 = 256'h0;
parameter [255:0] L06 = 256'h0;
parameter [255:0] L07 = 256'h0;
parameter [255:0] L08 = 256'h0;
parameter [255:0] L09 = 256'h0;
parameter [255:0] L0A = 256'h0;
parameter [255:0] L0B = 256'h0;
parameter [255:0] L0C = 256'h0;
parameter [255:0] L0D = 256'h0;
parameter [255:0] L0E = 256'h0;
parameter [255:0] L0F = 256'h0;
parameter [255:0] L10 = 256'h0;
parameter [255:0] L11 = 256'h0;
parameter [255:0] L12 = 256'h0;
parameter [255:0] L13 = 256'h0;
parameter [255:0] L14 = 256'h0;
parameter [255:0] L15 = 256'h0;
parameter [255:0] L16 = 256'h0;
parameter [255:0] L17 = 256'h0;
parameter [255:0] L18 = 256'h0;
parameter [255:0] L19 = 256'h0;
parameter [255:0] L1A = 256'h0;
parameter [255:0] L1B = 256'h0;
parameter [255:0] L1C = 256'h0;
parameter [255:0] L1D = 256'h0;
parameter [255:0] L1E = 256'h0;
parameter [255:0] L1F = 256'h0;
parameter [255:0] L20 = 256'h0;
parameter [255:0] L21 = 256'h0;
parameter [255:0] L22 = 256'h0;
parameter [255:0] L23 = 256'h0;
parameter [255:0] L24 = 256'h0;
parameter [255:0] L25 = 256'h0;
parameter [255:0] L26 = 256'h0;
parameter [255:0] L27 = 256'h0;
parameter [255:0] L28 = 256'h0;
parameter [255:0] L29 = 256'h0;
parameter [255:0] L2A = 256'h0;
parameter [255:0] L2B = 256'h0;
parameter [255:0] L2C = 256'h0;
parameter [255:0] L2D = 256'h0;
parameter [255:0] L2E = 256'h0;
parameter [255:0] L2F = 256'h0;
parameter [255:0] L30 = 256'h0;
parameter [255:0] L31 = 256'h0;
parameter [255:0] L32 = 256'h0;
parameter [255:0] L33 = 256'h0;
parameter [255:0] L34 = 256'h0;
parameter [255:0] L35 = 256'h0;
parameter [255:0] L36 = 256'h0;
parameter [255:0] L37 = 256'h0;
parameter [255:0] L38 = 256'h0;
parameter [255:0] L39 = 256'h0;
parameter [255:0] L3A = 256'h0;
parameter [255:0] L3B = 256'h0;
parameter [255:0] L3C = 256'h0;
parameter [255:0] L3D = 256'h0;
parameter [255:0] L3E = 256'h0;
parameter [255:0] L3F = 256'h0;
parameter [255:0] A0 = 256'h0;
parameter [255:0] A1 = 256'h0;
parameter [255:0] A2 = 256'h0;
always @ (posedge clk) begin
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
parameter PAR = 3;
input clk;
defparam i.L00 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L01 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L02 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L03 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L04 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L05 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L06 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L07 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L08 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L09 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L0A = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L0B = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L0C = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L0D = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L0E = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L0F = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L10 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L11 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L12 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L13 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L14 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L15 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L16 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L17 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L18 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L19 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L1A = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L1B = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L1C = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L1D = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L1E = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L1F = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L20 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L21 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L22 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L23 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L24 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L25 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L26 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L27 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L28 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L29 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L2A = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L2B = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L2C = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L2D = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L2E = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L2F = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L30 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L31 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L32 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L33 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L34 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L35 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L36 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L37 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L38 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L39 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L3A = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L3B = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L3C = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L3D = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L3E = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L3F = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.A0 = "HELLO_WORLD_BOY_THIS_IS_LONG";
defparam i.A1 = "HELLO_WORLD_BOY_THIS_IS_LONG";
defparam i.A2 = "HELLO_WORLD_BOY_THIS_IS_LONG";
i i (.clk(clk));
integer cyc=1;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==1) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module i
(/*AUTOARG*/
// Inputs
clk
);
// verilator public_module
input clk;
parameter [255:0] L00 = 256'h0;
parameter [255:0] L01 = 256'h0;
parameter [255:0] L02 = 256'h0;
parameter [255:0] L03 = 256'h0;
parameter [255:0] L04 = 256'h0;
parameter [255:0] L05 = 256'h0;
parameter [255:0] L06 = 256'h0;
parameter [255:0] L07 = 256'h0;
parameter [255:0] L08 = 256'h0;
parameter [255:0] L09 = 256'h0;
parameter [255:0] L0A = 256'h0;
parameter [255:0] L0B = 256'h0;
parameter [255:0] L0C = 256'h0;
parameter [255:0] L0D = 256'h0;
parameter [255:0] L0E = 256'h0;
parameter [255:0] L0F = 256'h0;
parameter [255:0] L10 = 256'h0;
parameter [255:0] L11 = 256'h0;
parameter [255:0] L12 = 256'h0;
parameter [255:0] L13 = 256'h0;
parameter [255:0] L14 = 256'h0;
parameter [255:0] L15 = 256'h0;
parameter [255:0] L16 = 256'h0;
parameter [255:0] L17 = 256'h0;
parameter [255:0] L18 = 256'h0;
parameter [255:0] L19 = 256'h0;
parameter [255:0] L1A = 256'h0;
parameter [255:0] L1B = 256'h0;
parameter [255:0] L1C = 256'h0;
parameter [255:0] L1D = 256'h0;
parameter [255:0] L1E = 256'h0;
parameter [255:0] L1F = 256'h0;
parameter [255:0] L20 = 256'h0;
parameter [255:0] L21 = 256'h0;
parameter [255:0] L22 = 256'h0;
parameter [255:0] L23 = 256'h0;
parameter [255:0] L24 = 256'h0;
parameter [255:0] L25 = 256'h0;
parameter [255:0] L26 = 256'h0;
parameter [255:0] L27 = 256'h0;
parameter [255:0] L28 = 256'h0;
parameter [255:0] L29 = 256'h0;
parameter [255:0] L2A = 256'h0;
parameter [255:0] L2B = 256'h0;
parameter [255:0] L2C = 256'h0;
parameter [255:0] L2D = 256'h0;
parameter [255:0] L2E = 256'h0;
parameter [255:0] L2F = 256'h0;
parameter [255:0] L30 = 256'h0;
parameter [255:0] L31 = 256'h0;
parameter [255:0] L32 = 256'h0;
parameter [255:0] L33 = 256'h0;
parameter [255:0] L34 = 256'h0;
parameter [255:0] L35 = 256'h0;
parameter [255:0] L36 = 256'h0;
parameter [255:0] L37 = 256'h0;
parameter [255:0] L38 = 256'h0;
parameter [255:0] L39 = 256'h0;
parameter [255:0] L3A = 256'h0;
parameter [255:0] L3B = 256'h0;
parameter [255:0] L3C = 256'h0;
parameter [255:0] L3D = 256'h0;
parameter [255:0] L3E = 256'h0;
parameter [255:0] L3F = 256'h0;
parameter [255:0] A0 = 256'h0;
parameter [255:0] A1 = 256'h0;
parameter [255:0] A2 = 256'h0;
always @ (posedge clk) begin
end
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/15.1/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_clock_crosser.v $
// $Revision: #1 $
// $Date: 2015/08/09 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_clock_crosser(
in_clk,
in_reset,
in_ready,
in_valid,
in_data,
out_clk,
out_reset,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter FORWARD_SYNC_DEPTH = 2;
parameter BACKWARD_SYNC_DEPTH = 2;
parameter USE_OUTPUT_PIPELINE = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input in_clk;
input in_reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_clk;
input out_reset;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
// Data is guaranteed valid by control signal clock crossing. Cut data
// buffer false path.
(* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\""} *) reg [DATA_WIDTH-1:0] in_data_buffer;
reg [DATA_WIDTH-1:0] out_data_buffer;
reg in_data_toggle;
wire in_data_toggle_returned;
wire out_data_toggle;
reg out_data_toggle_flopped;
wire take_in_data;
wire out_data_taken;
wire out_valid_internal;
wire out_ready_internal;
assign in_ready = ~(in_data_toggle_returned ^ in_data_toggle);
assign take_in_data = in_valid & in_ready;
assign out_valid_internal = out_data_toggle ^ out_data_toggle_flopped;
assign out_data_taken = out_ready_internal & out_valid_internal;
always @(posedge in_clk or posedge in_reset) begin
if (in_reset) begin
in_data_buffer <= {DATA_WIDTH{1'b0}};
in_data_toggle <= 1'b0;
end else begin
if (take_in_data) begin
in_data_toggle <= ~in_data_toggle;
in_data_buffer <= in_data;
end
end //in_reset
end //in_clk always block
always @(posedge out_clk or posedge out_reset) begin
if (out_reset) begin
out_data_toggle_flopped <= 1'b0;
out_data_buffer <= {DATA_WIDTH{1'b0}};
end else begin
out_data_buffer <= in_data_buffer;
if (out_data_taken) begin
out_data_toggle_flopped <= out_data_toggle;
end
end //end if
end //out_clk always block
altera_std_synchronizer_nocut #(.depth(FORWARD_SYNC_DEPTH)) in_to_out_synchronizer (
.clk(out_clk),
.reset_n(~out_reset),
.din(in_data_toggle),
.dout(out_data_toggle)
);
altera_std_synchronizer_nocut #(.depth(BACKWARD_SYNC_DEPTH)) out_to_in_synchronizer (
.clk(in_clk),
.reset_n(~in_reset),
.din(out_data_toggle_flopped),
.dout(in_data_toggle_returned)
);
generate if (USE_OUTPUT_PIPELINE == 1) begin
altera_avalon_st_pipeline_base
#(
.BITS_PER_SYMBOL(BITS_PER_SYMBOL),
.SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT)
) output_stage (
.clk(out_clk),
.reset(out_reset),
.in_ready(out_ready_internal),
.in_valid(out_valid_internal),
.in_data(out_data_buffer),
.out_ready(out_ready),
.out_valid(out_valid),
.out_data(out_data)
);
end else begin
assign out_valid = out_valid_internal;
assign out_ready_internal = out_ready;
assign out_data = out_data_buffer;
end
endgenerate
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/15.1/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_clock_crosser.v $
// $Revision: #1 $
// $Date: 2015/08/09 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_clock_crosser(
in_clk,
in_reset,
in_ready,
in_valid,
in_data,
out_clk,
out_reset,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter FORWARD_SYNC_DEPTH = 2;
parameter BACKWARD_SYNC_DEPTH = 2;
parameter USE_OUTPUT_PIPELINE = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input in_clk;
input in_reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_clk;
input out_reset;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
// Data is guaranteed valid by control signal clock crossing. Cut data
// buffer false path.
(* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\""} *) reg [DATA_WIDTH-1:0] in_data_buffer;
reg [DATA_WIDTH-1:0] out_data_buffer;
reg in_data_toggle;
wire in_data_toggle_returned;
wire out_data_toggle;
reg out_data_toggle_flopped;
wire take_in_data;
wire out_data_taken;
wire out_valid_internal;
wire out_ready_internal;
assign in_ready = ~(in_data_toggle_returned ^ in_data_toggle);
assign take_in_data = in_valid & in_ready;
assign out_valid_internal = out_data_toggle ^ out_data_toggle_flopped;
assign out_data_taken = out_ready_internal & out_valid_internal;
always @(posedge in_clk or posedge in_reset) begin
if (in_reset) begin
in_data_buffer <= {DATA_WIDTH{1'b0}};
in_data_toggle <= 1'b0;
end else begin
if (take_in_data) begin
in_data_toggle <= ~in_data_toggle;
in_data_buffer <= in_data;
end
end //in_reset
end //in_clk always block
always @(posedge out_clk or posedge out_reset) begin
if (out_reset) begin
out_data_toggle_flopped <= 1'b0;
out_data_buffer <= {DATA_WIDTH{1'b0}};
end else begin
out_data_buffer <= in_data_buffer;
if (out_data_taken) begin
out_data_toggle_flopped <= out_data_toggle;
end
end //end if
end //out_clk always block
altera_std_synchronizer_nocut #(.depth(FORWARD_SYNC_DEPTH)) in_to_out_synchronizer (
.clk(out_clk),
.reset_n(~out_reset),
.din(in_data_toggle),
.dout(out_data_toggle)
);
altera_std_synchronizer_nocut #(.depth(BACKWARD_SYNC_DEPTH)) out_to_in_synchronizer (
.clk(in_clk),
.reset_n(~in_reset),
.din(out_data_toggle_flopped),
.dout(in_data_toggle_returned)
);
generate if (USE_OUTPUT_PIPELINE == 1) begin
altera_avalon_st_pipeline_base
#(
.BITS_PER_SYMBOL(BITS_PER_SYMBOL),
.SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT)
) output_stage (
.clk(out_clk),
.reset(out_reset),
.in_ready(out_ready_internal),
.in_valid(out_valid_internal),
.in_data(out_data_buffer),
.out_ready(out_ready),
.out_valid(out_valid),
.out_data(out_data)
);
end else begin
assign out_valid = out_valid_internal;
assign out_ready_internal = out_ready;
assign out_data = out_data_buffer;
end
endgenerate
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/15.1/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_clock_crosser.v $
// $Revision: #1 $
// $Date: 2015/08/09 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_clock_crosser(
in_clk,
in_reset,
in_ready,
in_valid,
in_data,
out_clk,
out_reset,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter FORWARD_SYNC_DEPTH = 2;
parameter BACKWARD_SYNC_DEPTH = 2;
parameter USE_OUTPUT_PIPELINE = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input in_clk;
input in_reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_clk;
input out_reset;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
// Data is guaranteed valid by control signal clock crossing. Cut data
// buffer false path.
(* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\""} *) reg [DATA_WIDTH-1:0] in_data_buffer;
reg [DATA_WIDTH-1:0] out_data_buffer;
reg in_data_toggle;
wire in_data_toggle_returned;
wire out_data_toggle;
reg out_data_toggle_flopped;
wire take_in_data;
wire out_data_taken;
wire out_valid_internal;
wire out_ready_internal;
assign in_ready = ~(in_data_toggle_returned ^ in_data_toggle);
assign take_in_data = in_valid & in_ready;
assign out_valid_internal = out_data_toggle ^ out_data_toggle_flopped;
assign out_data_taken = out_ready_internal & out_valid_internal;
always @(posedge in_clk or posedge in_reset) begin
if (in_reset) begin
in_data_buffer <= {DATA_WIDTH{1'b0}};
in_data_toggle <= 1'b0;
end else begin
if (take_in_data) begin
in_data_toggle <= ~in_data_toggle;
in_data_buffer <= in_data;
end
end //in_reset
end //in_clk always block
always @(posedge out_clk or posedge out_reset) begin
if (out_reset) begin
out_data_toggle_flopped <= 1'b0;
out_data_buffer <= {DATA_WIDTH{1'b0}};
end else begin
out_data_buffer <= in_data_buffer;
if (out_data_taken) begin
out_data_toggle_flopped <= out_data_toggle;
end
end //end if
end //out_clk always block
altera_std_synchronizer_nocut #(.depth(FORWARD_SYNC_DEPTH)) in_to_out_synchronizer (
.clk(out_clk),
.reset_n(~out_reset),
.din(in_data_toggle),
.dout(out_data_toggle)
);
altera_std_synchronizer_nocut #(.depth(BACKWARD_SYNC_DEPTH)) out_to_in_synchronizer (
.clk(in_clk),
.reset_n(~in_reset),
.din(out_data_toggle_flopped),
.dout(in_data_toggle_returned)
);
generate if (USE_OUTPUT_PIPELINE == 1) begin
altera_avalon_st_pipeline_base
#(
.BITS_PER_SYMBOL(BITS_PER_SYMBOL),
.SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT)
) output_stage (
.clk(out_clk),
.reset(out_reset),
.in_ready(out_ready_internal),
.in_valid(out_valid_internal),
.in_data(out_data_buffer),
.out_ready(out_ready),
.out_valid(out_valid),
.out_data(out_data)
);
end else begin
assign out_valid = out_valid_internal;
assign out_ready_internal = out_ready;
assign out_data = out_data_buffer;
end
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
`ifdef verilator
`define CLOG2 $clog2
`else
`define CLOG2 clog2_emulate
`endif
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Need temp wires as function has different width rules than $clog2
wire [127:0] pows = 128'h1<<crc[7:0];
wire [127:0] npows = ~pows;
wire [31:0] out = `CLOG2(crc[7:0]);
wire [31:0] out2 = `CLOG2(crc);
wire [31:0] out3 = `CLOG2(pows);
wire [31:0] out4 = `CLOG2(npows);
// Aggregate outputs into a single result vector
wire [63:0] result = {out4[15:0], out3[15:0], out2[15:0], out[15:0]};
`define EXPECTED_SUM 64'h73c48afee4f0cb57
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
crc <= 64'h0;
if (`CLOG2(32'h0) != 0) $stop;
if (`CLOG2(32'h1) != 0) $stop;
if (`CLOG2(32'h4) != 2) $stop;
if (`CLOG2(32'h7) != 3) $stop;
if (`CLOG2(32'h8) != 3) $stop;
if (`CLOG2(32'h9) != 4) $stop;
if (`CLOG2({32{1'b1}}) != 32) $stop;
if (`CLOG2({1'b1,32'b0}) != 32) $stop;
if (`CLOG2({64{1'b1}}) != 64) $stop;
if (`CLOG2({1'b1,64'b0}) != 64) $stop;
if (`CLOG2({128{1'b1}}) != 128) $stop;
if (`CLOG2({1'b1,128'b0}) != 128) $stop;
if (`CLOG2({2'b10,128'b0}) != 129) $stop;
end
else if (cyc==1) begin
crc <= 64'h1;
if (result[31:0] != {16'd0, 16'd0}) $stop;
end
else if (cyc==2) begin
crc <= 64'h3;
if (result[31:0] != {16'd0, 16'd0}) $stop;
end
else if (cyc==3) begin
crc <= {64{1'b1}};
if (result[31:0] != {16'd2, 16'd2}) $stop;
end
else if (cyc==4) begin
if (result[31:0] != {16'd64, 16'd8}) $stop;
end
else if (cyc==8) begin
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hcbc77bb9b3784ea0) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
function integer clog2_emulate(input [130:0] arg);
begin
if (arg!=0) arg = arg - 1;
for (clog2_emulate=0; arg!=0; clog2_emulate=clog2_emulate+1)
arg = (arg >> 1);
end
endfunction
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2008 by Wilson Snyder.
module t (clk);
input clk;
integer cyc; initial cyc=1;
integer sum;
integer cpre;
always @ (posedge clk) begin
if (cyc!=0) begin
cpre = cyc;
cyc <= cyc + 1;
if (cyc==1) begin
if (mlog2(32'd0) != 32'd0) $stop;
if (mlog2(32'd1) != 32'd0) $stop;
if (mlog2(32'd3) != 32'd2) $stop;
sum <= 32'd0;
end
else if (cyc<90) begin
// (cyc) so if we trash the variable things will get upset.
sum <= mlog2(cyc) + sum * 32'd42;
if (cpre != cyc) $stop;
end
else if (cyc==90) begin
if (sum !== 32'h0f12bb51) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
function integer mlog2;
input [31:0] value;
integer i;
begin
if(value < 32'd1) begin
mlog2 = 0;
end
else begin
value = value - 32'd1;
mlog2 = 0;
for(i=0;i<32;i=i+1) begin
if(value > 32'd0) begin
mlog2 = mlog2 + 1;
end
value = value >> 1;
end
end
end
endfunction
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// What checksum will we end up with
`define EXPECTED_SUM 64'h966e272fd829e672
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
input clk;
input [31:0] in;
output [31:0] out;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [31:0] out;
// End of automatics
`ifdef verilator
`define dontOptimize $c1("1")
`else
`define dontOptimize 1'b1
`endif
always @(posedge clk) begin
out <= in;
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
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if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
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if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (in[0])
out <= ~in;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// What checksum will we end up with
`define EXPECTED_SUM 64'h966e272fd829e672
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
input clk;
input [31:0] in;
output [31:0] out;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [31:0] out;
// End of automatics
`ifdef verilator
`define dontOptimize $c1("1")
`else
`define dontOptimize 1'b1
`endif
always @(posedge clk) begin
out <= in;
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
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if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (in[0])
out <= ~in;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// What checksum will we end up with
`define EXPECTED_SUM 64'h966e272fd829e672
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
input clk;
input [31:0] in;
output [31:0] out;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [31:0] out;
// End of automatics
`ifdef verilator
`define dontOptimize $c1("1")
`else
`define dontOptimize 1'b1
`endif
always @(posedge clk) begin
out <= in;
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (in[0])
out <= ~in;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Some inputs we'll set to random values
reg [6:0] addr;
reg [6:0] e0;
reg [5:0] e1;
reg [5:0] e2;
wire [7:0] data;
reg [2:0] wrapcheck_a;
reg [2:0] wrapcheck_b;
test test (/*AUTOINST*/
// Outputs
.data (data[7:0]),
// Inputs
.addr (addr[6:0]),
.e0 (e0[6:0]),
.e1 (e1[5:0]),
.e2 (e2[5:0]));
always @(/*AS*/addr) begin
case(addr[2:0])
3'd0+3'd0: wrapcheck_a = 3'h0;
3'd0+3'd1: wrapcheck_a = 3'h1;
3'd0+3'd2: wrapcheck_a = 3'h2;
3'd0+3'd3: wrapcheck_a = 3'h3;
default: wrapcheck_a = 3'h4;
endcase
case(addr[2:0])
3'd0+0: wrapcheck_b = 3'h0;
3'd1+1: wrapcheck_b = 3'h1;
3'd2+2: wrapcheck_b = 3'h2;
3'd3+3: wrapcheck_b = 3'h3;
default: wrapcheck_b = 3'h4;
endcase
end
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b);
if (cyc==1) begin
addr <= 7'h28;
e0 <= 7'h11;
e1 <= 6'h02;
e2 <= 6'h03;
end
if (cyc==2) begin
addr <= 7'h2b;
if (data != 8'h11) $stop;
end
if (cyc==3) begin
addr <= 7'h2c;
if (data != 8'h03) $stop;
if (wrapcheck_a != 3'h3) $stop;
if (wrapcheck_b != 3'h4) $stop;
end
if (cyc==4) begin
addr <= 7'h0;
if (data != 8'h00) $stop;
if (wrapcheck_a != 3'h4) $stop;
if (wrapcheck_b != 3'h2) $stop;
end
if (cyc==5) begin
if (data != 8'h00) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
/* verilator lint_off WIDTH */
`define AI 7'h28
module test (/*AUTOARG*/
// Outputs
data,
// Inputs
addr, e0, e1, e2
);
output [7:0] data;
input [6:0] addr;
input [6:0] e0;
input [5:0] e1, e2;
reg [7:0] data;
always @(/*AS*/addr or e0 or e1 or e2)
begin
case (addr)
`AI: data = {e0[6], 1'b0, e0[5:0]};
`AI+1: data = e1;
`AI+2,
`AI+3: data = e2;
default: data = 0;
endcase
end
endmodule
// Local Variables:
// eval:(verilog-read-defines)
// verilog-auto-sense-defines-constant: t
// End:
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Some inputs we'll set to random values
reg [6:0] addr;
reg [6:0] e0;
reg [5:0] e1;
reg [5:0] e2;
wire [7:0] data;
reg [2:0] wrapcheck_a;
reg [2:0] wrapcheck_b;
test test (/*AUTOINST*/
// Outputs
.data (data[7:0]),
// Inputs
.addr (addr[6:0]),
.e0 (e0[6:0]),
.e1 (e1[5:0]),
.e2 (e2[5:0]));
always @(/*AS*/addr) begin
case(addr[2:0])
3'd0+3'd0: wrapcheck_a = 3'h0;
3'd0+3'd1: wrapcheck_a = 3'h1;
3'd0+3'd2: wrapcheck_a = 3'h2;
3'd0+3'd3: wrapcheck_a = 3'h3;
default: wrapcheck_a = 3'h4;
endcase
case(addr[2:0])
3'd0+0: wrapcheck_b = 3'h0;
3'd1+1: wrapcheck_b = 3'h1;
3'd2+2: wrapcheck_b = 3'h2;
3'd3+3: wrapcheck_b = 3'h3;
default: wrapcheck_b = 3'h4;
endcase
end
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b);
if (cyc==1) begin
addr <= 7'h28;
e0 <= 7'h11;
e1 <= 6'h02;
e2 <= 6'h03;
end
if (cyc==2) begin
addr <= 7'h2b;
if (data != 8'h11) $stop;
end
if (cyc==3) begin
addr <= 7'h2c;
if (data != 8'h03) $stop;
if (wrapcheck_a != 3'h3) $stop;
if (wrapcheck_b != 3'h4) $stop;
end
if (cyc==4) begin
addr <= 7'h0;
if (data != 8'h00) $stop;
if (wrapcheck_a != 3'h4) $stop;
if (wrapcheck_b != 3'h2) $stop;
end
if (cyc==5) begin
if (data != 8'h00) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
/* verilator lint_off WIDTH */
`define AI 7'h28
module test (/*AUTOARG*/
// Outputs
data,
// Inputs
addr, e0, e1, e2
);
output [7:0] data;
input [6:0] addr;
input [6:0] e0;
input [5:0] e1, e2;
reg [7:0] data;
always @(/*AS*/addr or e0 or e1 or e2)
begin
case (addr)
`AI: data = {e0[6], 1'b0, e0[5:0]};
`AI+1: data = e1;
`AI+2,
`AI+3: data = e2;
default: data = 0;
endcase
end
endmodule
// Local Variables:
// eval:(verilog-read-defines)
// verilog-auto-sense-defines-constant: t
// End:
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Some inputs we'll set to random values
reg [6:0] addr;
reg [6:0] e0;
reg [5:0] e1;
reg [5:0] e2;
wire [7:0] data;
reg [2:0] wrapcheck_a;
reg [2:0] wrapcheck_b;
test test (/*AUTOINST*/
// Outputs
.data (data[7:0]),
// Inputs
.addr (addr[6:0]),
.e0 (e0[6:0]),
.e1 (e1[5:0]),
.e2 (e2[5:0]));
always @(/*AS*/addr) begin
case(addr[2:0])
3'd0+3'd0: wrapcheck_a = 3'h0;
3'd0+3'd1: wrapcheck_a = 3'h1;
3'd0+3'd2: wrapcheck_a = 3'h2;
3'd0+3'd3: wrapcheck_a = 3'h3;
default: wrapcheck_a = 3'h4;
endcase
case(addr[2:0])
3'd0+0: wrapcheck_b = 3'h0;
3'd1+1: wrapcheck_b = 3'h1;
3'd2+2: wrapcheck_b = 3'h2;
3'd3+3: wrapcheck_b = 3'h3;
default: wrapcheck_b = 3'h4;
endcase
end
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b);
if (cyc==1) begin
addr <= 7'h28;
e0 <= 7'h11;
e1 <= 6'h02;
e2 <= 6'h03;
end
if (cyc==2) begin
addr <= 7'h2b;
if (data != 8'h11) $stop;
end
if (cyc==3) begin
addr <= 7'h2c;
if (data != 8'h03) $stop;
if (wrapcheck_a != 3'h3) $stop;
if (wrapcheck_b != 3'h4) $stop;
end
if (cyc==4) begin
addr <= 7'h0;
if (data != 8'h00) $stop;
if (wrapcheck_a != 3'h4) $stop;
if (wrapcheck_b != 3'h2) $stop;
end
if (cyc==5) begin
if (data != 8'h00) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
/* verilator lint_off WIDTH */
`define AI 7'h28
module test (/*AUTOARG*/
// Outputs
data,
// Inputs
addr, e0, e1, e2
);
output [7:0] data;
input [6:0] addr;
input [6:0] e0;
input [5:0] e1, e2;
reg [7:0] data;
always @(/*AS*/addr or e0 or e1 or e2)
begin
case (addr)
`AI: data = {e0[6], 1'b0, e0[5:0]};
`AI+1: data = e1;
`AI+2,
`AI+3: data = e2;
default: data = 0;
endcase
end
endmodule
// Local Variables:
// eval:(verilog-read-defines)
// verilog-auto-sense-defines-constant: t
// End:
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Some inputs we'll set to random values
reg [6:0] addr;
reg [6:0] e0;
reg [5:0] e1;
reg [5:0] e2;
wire [7:0] data;
reg [2:0] wrapcheck_a;
reg [2:0] wrapcheck_b;
test test (/*AUTOINST*/
// Outputs
.data (data[7:0]),
// Inputs
.addr (addr[6:0]),
.e0 (e0[6:0]),
.e1 (e1[5:0]),
.e2 (e2[5:0]));
always @(/*AS*/addr) begin
case(addr[2:0])
3'd0+3'd0: wrapcheck_a = 3'h0;
3'd0+3'd1: wrapcheck_a = 3'h1;
3'd0+3'd2: wrapcheck_a = 3'h2;
3'd0+3'd3: wrapcheck_a = 3'h3;
default: wrapcheck_a = 3'h4;
endcase
case(addr[2:0])
3'd0+0: wrapcheck_b = 3'h0;
3'd1+1: wrapcheck_b = 3'h1;
3'd2+2: wrapcheck_b = 3'h2;
3'd3+3: wrapcheck_b = 3'h3;
default: wrapcheck_b = 3'h4;
endcase
end
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b);
if (cyc==1) begin
addr <= 7'h28;
e0 <= 7'h11;
e1 <= 6'h02;
e2 <= 6'h03;
end
if (cyc==2) begin
addr <= 7'h2b;
if (data != 8'h11) $stop;
end
if (cyc==3) begin
addr <= 7'h2c;
if (data != 8'h03) $stop;
if (wrapcheck_a != 3'h3) $stop;
if (wrapcheck_b != 3'h4) $stop;
end
if (cyc==4) begin
addr <= 7'h0;
if (data != 8'h00) $stop;
if (wrapcheck_a != 3'h4) $stop;
if (wrapcheck_b != 3'h2) $stop;
end
if (cyc==5) begin
if (data != 8'h00) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
/* verilator lint_off WIDTH */
`define AI 7'h28
module test (/*AUTOARG*/
// Outputs
data,
// Inputs
addr, e0, e1, e2
);
output [7:0] data;
input [6:0] addr;
input [6:0] e0;
input [5:0] e1, e2;
reg [7:0] data;
always @(/*AS*/addr or e0 or e1 or e2)
begin
case (addr)
`AI: data = {e0[6], 1'b0, e0[5:0]};
`AI+1: data = e1;
`AI+2,
`AI+3: data = e2;
default: data = 0;
endcase
end
endmodule
// Local Variables:
// eval:(verilog-read-defines)
// verilog-auto-sense-defines-constant: t
// End:
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [15:0] l;
reg [49:0] q;
reg [79:0] w;
reg [4:0] lc;
reg lo;
reg l0;
reg [5:0] qc;
reg qo;
reg q0;
reg [6:0] wc;
reg wo;
reg w0;
always @* begin
lc = $countones(l);
lo = $onehot(l);
l0 = $onehot0(l);
wc = $countones(w);
wo = $onehot(w);
w0 = $onehot0(w);
qc = $countones(q);
qo = $onehot(q);
q0 = $onehot0(q);
end
integer cyc; initial cyc=1;
integer cyc_com;
always_comb begin
cyc_com = cyc;
end
integer cyc_d1;
always_ff @ (posedge clk) begin
cyc_d1 <= cyc_com;
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x %d %x %x %x %d %x %x %x %d %x %x\n",
// cyc, l, lc, lo, l0, q,qc,qo,q0, w,wc,wo,w0);
if (cyc_com != cyc_com) $stop;
if (cyc_d1 != cyc-1) $stop;
if (cyc==0) begin
// Constification check
if ($countones(32'b11001011101) != 7) $stop;
if ($countones(32'b0) != 0) $stop;
if ($isunknown(32'b11101x11111) != 1) $stop;
if ($isunknown(32'b11101011111) != 0) $stop;
if ($isunknown(32'b10zzzzzzzzz) != 0) $stop;
if ($bits(0) != 32'd32) $stop;
if ($bits(lc) != 5) $stop;
if ($onehot(32'b00000001000000) != 1'b1) $stop;
if ($onehot(32'b00001001000000) != 1'b0) $stop;
if ($onehot(32'b0) != 1'b0) $stop;
if ($onehot0(32'b00000001000000) != 1'b1) $stop;
if ($onehot0(32'b00001001000000) != 1'b0) $stop;
if ($onehot0(32'b0) != 1'b1) $stop;
end
if (cyc==1) begin
l <= 16'b0;
q <= 50'h0;
w <= 80'h0;
end
if (cyc==2) begin
l <= ~16'b0;
q <= ~50'h0;
w <= ~80'h0;
//
if ({lc,lo,l0} != {5'd0,1'b0,1'b1}) $stop;
if ({qc,qo,q0} != {6'd0,1'b0,1'b1}) $stop;
if ({wc,wo,w0} != {7'd0,1'b0,1'b1}) $stop;
end
if (cyc==3) begin
l <= 16'b0010110010110111;
q <= 50'h01_1111_0001;
w <= 80'h0100_0000_0f00_00f0_0000;
//
if ({lc,lo,l0} != {5'd16,1'b0,1'b0}) $stop;
if ({qc,qo,q0} != {6'd50,1'b0,1'b0}) $stop;
if ({wc,wo,w0} != {7'd80,1'b0,1'b0}) $stop;
end
if (cyc==4) begin
l <= 16'b0000010000000000;
q <= 50'h1_0000_0000;
w <= 80'h010_00000000_00000000;
//
if ({lc,lo,l0} != {5'd9,1'b0,1'b0}) $stop;
if ({qc,qo,q0} != {6'd6,1'b0,1'b0}) $stop;
if ({wc,wo,w0} != {7'd9,1'b0,1'b0}) $stop;
end
if (cyc==5) begin
l <= 16'b0000000100000000;
q <= 50'h8000_0000_0000;
w <= 80'h10_00000000_00000000;
//
if ({lc,lo,l0} != {5'd1,1'b1,1'b1}) $stop;
if ({qc,qo,q0} != {6'd1,1'b1,1'b1}) $stop;
if ({wc,wo,w0} != {7'd1,1'b1,1'b1}) $stop;
end
if (cyc==6) begin
l <= 16'b0000100100000000;
q <= 50'h01_00000100;
w <= 80'h01_00000100_00000000;
//
if ({lc,lo,l0} != {5'd1,1'b1,1'b1}) $stop;
if ({qc,qo,q0} != {6'd1,1'b1,1'b1}) $stop;
if ({wc,wo,w0} != {7'd1,1'b1,1'b1}) $stop;
end
if (cyc==7) begin
//
if ({lc,lo,l0} != {5'd2,1'b0,1'b0}) $stop;
if ({qc,qo,q0} != {6'd2,1'b0,1'b0}) $stop;
if ({wc,wo,w0} != {7'd2,1'b0,1'b0}) $stop;
end
if (cyc==8) begin
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
final begin
$write("Goodbye world, at cycle %0d\n", cyc);
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [15:0] l;
reg [49:0] q;
reg [79:0] w;
reg [4:0] lc;
reg lo;
reg l0;
reg [5:0] qc;
reg qo;
reg q0;
reg [6:0] wc;
reg wo;
reg w0;
always @* begin
lc = $countones(l);
lo = $onehot(l);
l0 = $onehot0(l);
wc = $countones(w);
wo = $onehot(w);
w0 = $onehot0(w);
qc = $countones(q);
qo = $onehot(q);
q0 = $onehot0(q);
end
integer cyc; initial cyc=1;
integer cyc_com;
always_comb begin
cyc_com = cyc;
end
integer cyc_d1;
always_ff @ (posedge clk) begin
cyc_d1 <= cyc_com;
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x %d %x %x %x %d %x %x %x %d %x %x\n",
// cyc, l, lc, lo, l0, q,qc,qo,q0, w,wc,wo,w0);
if (cyc_com != cyc_com) $stop;
if (cyc_d1 != cyc-1) $stop;
if (cyc==0) begin
// Constification check
if ($countones(32'b11001011101) != 7) $stop;
if ($countones(32'b0) != 0) $stop;
if ($isunknown(32'b11101x11111) != 1) $stop;
if ($isunknown(32'b11101011111) != 0) $stop;
if ($isunknown(32'b10zzzzzzzzz) != 0) $stop;
if ($bits(0) != 32'd32) $stop;
if ($bits(lc) != 5) $stop;
if ($onehot(32'b00000001000000) != 1'b1) $stop;
if ($onehot(32'b00001001000000) != 1'b0) $stop;
if ($onehot(32'b0) != 1'b0) $stop;
if ($onehot0(32'b00000001000000) != 1'b1) $stop;
if ($onehot0(32'b00001001000000) != 1'b0) $stop;
if ($onehot0(32'b0) != 1'b1) $stop;
end
if (cyc==1) begin
l <= 16'b0;
q <= 50'h0;
w <= 80'h0;
end
if (cyc==2) begin
l <= ~16'b0;
q <= ~50'h0;
w <= ~80'h0;
//
if ({lc,lo,l0} != {5'd0,1'b0,1'b1}) $stop;
if ({qc,qo,q0} != {6'd0,1'b0,1'b1}) $stop;
if ({wc,wo,w0} != {7'd0,1'b0,1'b1}) $stop;
end
if (cyc==3) begin
l <= 16'b0010110010110111;
q <= 50'h01_1111_0001;
w <= 80'h0100_0000_0f00_00f0_0000;
//
if ({lc,lo,l0} != {5'd16,1'b0,1'b0}) $stop;
if ({qc,qo,q0} != {6'd50,1'b0,1'b0}) $stop;
if ({wc,wo,w0} != {7'd80,1'b0,1'b0}) $stop;
end
if (cyc==4) begin
l <= 16'b0000010000000000;
q <= 50'h1_0000_0000;
w <= 80'h010_00000000_00000000;
//
if ({lc,lo,l0} != {5'd9,1'b0,1'b0}) $stop;
if ({qc,qo,q0} != {6'd6,1'b0,1'b0}) $stop;
if ({wc,wo,w0} != {7'd9,1'b0,1'b0}) $stop;
end
if (cyc==5) begin
l <= 16'b0000000100000000;
q <= 50'h8000_0000_0000;
w <= 80'h10_00000000_00000000;
//
if ({lc,lo,l0} != {5'd1,1'b1,1'b1}) $stop;
if ({qc,qo,q0} != {6'd1,1'b1,1'b1}) $stop;
if ({wc,wo,w0} != {7'd1,1'b1,1'b1}) $stop;
end
if (cyc==6) begin
l <= 16'b0000100100000000;
q <= 50'h01_00000100;
w <= 80'h01_00000100_00000000;
//
if ({lc,lo,l0} != {5'd1,1'b1,1'b1}) $stop;
if ({qc,qo,q0} != {6'd1,1'b1,1'b1}) $stop;
if ({wc,wo,w0} != {7'd1,1'b1,1'b1}) $stop;
end
if (cyc==7) begin
//
if ({lc,lo,l0} != {5'd2,1'b0,1'b0}) $stop;
if ({qc,qo,q0} != {6'd2,1'b0,1'b0}) $stop;
if ({wc,wo,w0} != {7'd2,1'b0,1'b0}) $stop;
end
if (cyc==8) begin
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
final begin
$write("Goodbye world, at cycle %0d\n", cyc);
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [15:0] l;
reg [49:0] q;
reg [79:0] w;
reg [4:0] lc;
reg lo;
reg l0;
reg [5:0] qc;
reg qo;
reg q0;
reg [6:0] wc;
reg wo;
reg w0;
always @* begin
lc = $countones(l);
lo = $onehot(l);
l0 = $onehot0(l);
wc = $countones(w);
wo = $onehot(w);
w0 = $onehot0(w);
qc = $countones(q);
qo = $onehot(q);
q0 = $onehot0(q);
end
integer cyc; initial cyc=1;
integer cyc_com;
always_comb begin
cyc_com = cyc;
end
integer cyc_d1;
always_ff @ (posedge clk) begin
cyc_d1 <= cyc_com;
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x %d %x %x %x %d %x %x %x %d %x %x\n",
// cyc, l, lc, lo, l0, q,qc,qo,q0, w,wc,wo,w0);
if (cyc_com != cyc_com) $stop;
if (cyc_d1 != cyc-1) $stop;
if (cyc==0) begin
// Constification check
if ($countones(32'b11001011101) != 7) $stop;
if ($countones(32'b0) != 0) $stop;
if ($isunknown(32'b11101x11111) != 1) $stop;
if ($isunknown(32'b11101011111) != 0) $stop;
if ($isunknown(32'b10zzzzzzzzz) != 0) $stop;
if ($bits(0) != 32'd32) $stop;
if ($bits(lc) != 5) $stop;
if ($onehot(32'b00000001000000) != 1'b1) $stop;
if ($onehot(32'b00001001000000) != 1'b0) $stop;
if ($onehot(32'b0) != 1'b0) $stop;
if ($onehot0(32'b00000001000000) != 1'b1) $stop;
if ($onehot0(32'b00001001000000) != 1'b0) $stop;
if ($onehot0(32'b0) != 1'b1) $stop;
end
if (cyc==1) begin
l <= 16'b0;
q <= 50'h0;
w <= 80'h0;
end
if (cyc==2) begin
l <= ~16'b0;
q <= ~50'h0;
w <= ~80'h0;
//
if ({lc,lo,l0} != {5'd0,1'b0,1'b1}) $stop;
if ({qc,qo,q0} != {6'd0,1'b0,1'b1}) $stop;
if ({wc,wo,w0} != {7'd0,1'b0,1'b1}) $stop;
end
if (cyc==3) begin
l <= 16'b0010110010110111;
q <= 50'h01_1111_0001;
w <= 80'h0100_0000_0f00_00f0_0000;
//
if ({lc,lo,l0} != {5'd16,1'b0,1'b0}) $stop;
if ({qc,qo,q0} != {6'd50,1'b0,1'b0}) $stop;
if ({wc,wo,w0} != {7'd80,1'b0,1'b0}) $stop;
end
if (cyc==4) begin
l <= 16'b0000010000000000;
q <= 50'h1_0000_0000;
w <= 80'h010_00000000_00000000;
//
if ({lc,lo,l0} != {5'd9,1'b0,1'b0}) $stop;
if ({qc,qo,q0} != {6'd6,1'b0,1'b0}) $stop;
if ({wc,wo,w0} != {7'd9,1'b0,1'b0}) $stop;
end
if (cyc==5) begin
l <= 16'b0000000100000000;
q <= 50'h8000_0000_0000;
w <= 80'h10_00000000_00000000;
//
if ({lc,lo,l0} != {5'd1,1'b1,1'b1}) $stop;
if ({qc,qo,q0} != {6'd1,1'b1,1'b1}) $stop;
if ({wc,wo,w0} != {7'd1,1'b1,1'b1}) $stop;
end
if (cyc==6) begin
l <= 16'b0000100100000000;
q <= 50'h01_00000100;
w <= 80'h01_00000100_00000000;
//
if ({lc,lo,l0} != {5'd1,1'b1,1'b1}) $stop;
if ({qc,qo,q0} != {6'd1,1'b1,1'b1}) $stop;
if ({wc,wo,w0} != {7'd1,1'b1,1'b1}) $stop;
end
if (cyc==7) begin
//
if ({lc,lo,l0} != {5'd2,1'b0,1'b0}) $stop;
if ({qc,qo,q0} != {6'd2,1'b0,1'b0}) $stop;
if ({wc,wo,w0} != {7'd2,1'b0,1'b0}) $stop;
end
if (cyc==8) begin
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
final begin
$write("Goodbye world, at cycle %0d\n", cyc);
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// Life analysis checks
reg [15:0] life;
// Ding case
reg [7:0] din;
reg [15:0] fixin;
always @* begin
fixin = {din[7:0],din[7:0]};
case (din[1:0])
2'b00: begin
fixin = {fixin[14:0], 1'b1};
if (cyc==101) $display("Prevent ?: optimization a");
end
2'b01: begin
fixin = {fixin[13:0], 2'b11};
if (cyc==101) $display("Prevent ?: optimization b");
end
2'b10: begin
fixin = {fixin[12:0], 3'b111};
if (cyc==101) $display("Prevent ?: optimization c");
end
2'b11: begin
fixin = {fixin[11:0], 4'b1111};
if (cyc==101) $display("Prevent ?: optimization d");
end
endcase
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc<=cyc+1;
if (cyc==1) begin
life = 16'h8000; // Dropped
life = 16'h0010; // Used below
if (life != 16'h0010) $stop;
//
life = 16'h0020; // Used below
if ($time < 10000)
if (life != 16'h0020) $stop;
//
life = 16'h8000; // Dropped
if ($time > 100000) begin
if ($time != 0) $stop; // Prevent conversion to ?:
life = 16'h1030;
end
else
life = 16'h0030;
if (life != 16'h0030) $stop;
//
life = 16'h0040; // Not dropped, no else below
if ($time > 100000)
life = 16'h1040;
if (life != 16'h0040) $stop;
//
life = 16'h8000; // Dropped
if ($time > 100000) begin
life = 16'h1050;
if (life != 0) $stop; // Ignored, as set is first
end
else begin
if ($time > 100010)
life = 16'h1050;
else life = 16'h0050;
end
if (life != 16'h0050) $stop;
end
if (cyc==2) begin
din <= 8'haa;
end
if (cyc==3) begin
din <= 8'hfb;
if (fixin != 16'h5557) $stop;
end
if (cyc==4) begin
din <= 8'h5c;
if (fixin != 16'hbfbf) $stop;
end
if (cyc==5) begin
din <= 8'hed;
if (fixin != 16'hb8b9) $stop;
end
if (cyc==6) begin
if (fixin != 16'hb7b7) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// Life analysis checks
reg [15:0] life;
// Ding case
reg [7:0] din;
reg [15:0] fixin;
always @* begin
fixin = {din[7:0],din[7:0]};
case (din[1:0])
2'b00: begin
fixin = {fixin[14:0], 1'b1};
if (cyc==101) $display("Prevent ?: optimization a");
end
2'b01: begin
fixin = {fixin[13:0], 2'b11};
if (cyc==101) $display("Prevent ?: optimization b");
end
2'b10: begin
fixin = {fixin[12:0], 3'b111};
if (cyc==101) $display("Prevent ?: optimization c");
end
2'b11: begin
fixin = {fixin[11:0], 4'b1111};
if (cyc==101) $display("Prevent ?: optimization d");
end
endcase
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc<=cyc+1;
if (cyc==1) begin
life = 16'h8000; // Dropped
life = 16'h0010; // Used below
if (life != 16'h0010) $stop;
//
life = 16'h0020; // Used below
if ($time < 10000)
if (life != 16'h0020) $stop;
//
life = 16'h8000; // Dropped
if ($time > 100000) begin
if ($time != 0) $stop; // Prevent conversion to ?:
life = 16'h1030;
end
else
life = 16'h0030;
if (life != 16'h0030) $stop;
//
life = 16'h0040; // Not dropped, no else below
if ($time > 100000)
life = 16'h1040;
if (life != 16'h0040) $stop;
//
life = 16'h8000; // Dropped
if ($time > 100000) begin
life = 16'h1050;
if (life != 0) $stop; // Ignored, as set is first
end
else begin
if ($time > 100010)
life = 16'h1050;
else life = 16'h0050;
end
if (life != 16'h0050) $stop;
end
if (cyc==2) begin
din <= 8'haa;
end
if (cyc==3) begin
din <= 8'hfb;
if (fixin != 16'h5557) $stop;
end
if (cyc==4) begin
din <= 8'h5c;
if (fixin != 16'hbfbf) $stop;
end
if (cyc==5) begin
din <= 8'hed;
if (fixin != 16'hb8b9) $stop;
end
if (cyc==6) begin
if (fixin != 16'hb7b7) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
(** * UseAuto: Theory and Practice of Automation in Coq Proofs *)
(* $Date: 2013-07-17 16:19:11 -0400 (Wed, 17 Jul 2013) $ *)
(* Chapter maintained by Arthur Chargueraud *)
(** In a machine-checked proof, every single detail has to be
justified. This can result in huge proof scripts. Fortunately,
Coq comes with a proof-search mechanism and with several decision
procedures that enable the system to automatically synthesize
simple pieces of proof. Automation is very powerful when set up
appropriately. The purpose of this chapter is to explain the
basics of working of automation.
The chapter is organized in two parts. The first part focuses on a
general mechanism called "proof search." In short, proof search
consists in naively trying to apply lemmas and assumptions in all
possible ways. The second part describes "decision procedures",
which are tactics that are very good at solving proof obligations
that fall in some particular fragment of the logic of Coq.
Many of the examples used in this chapter consist of small lemmas
that have been made up to illustrate particular aspects of automation.
These examples are completely independent from the rest of the Software
Foundations course. This chapter also contains some bigger examples
which are used to explain how to use automation in realistic proofs.
These examples are taken from other chapters of the course (mostly
from STLC), and the proofs that we present make use of the tactics
from the library [LibTactics.v], which is presented in the chapter
[UseTactics]. *)
Require Import LibTactics.
(* ####################################################### *)
(** * Basic Features of Proof Search *)
(** The idea of proof search is to replace a sequence of tactics
applying lemmas and assumptions with a call to a single tactic,
for example [auto]. This form of proof automation saves a lot of
effort. It typically leads to much shorter proof scripts, and to
scripts that are typically more robust to change. If one makes a
little change to a definition, a proof that exploits automation
probably won't need to be modified at all. Of course, using too
much automation is a bad idea. When a proof script no longer
records the main arguments of a proof, it becomes difficult to fix
it when it gets broken after a change in a definition. Overall, a
reasonable use of automation is generally a big win, as it saves a
lot of time both in building proof scripts and in subsequently
maintaining those proof scripts. *)
(* ####################################################### *)
(** ** Strength of Proof Search *)
(** We are going to study four proof-search tactics: [auto], [eauto],
[iauto] and [jauto]. The tactics [auto] and [eauto] are builtin
in Coq. The tactic [iauto] is a shorthand for the builtin tactic
[try solve [intuition eauto]]. The tactic [jauto] is defined in
the library [LibTactics], and simply performs some preprocessing
of the goal before calling [eauto]. The goal of this chapter is
to explain the general principles of proof search and to give
rule of thumbs for guessing which of the four tactics mentioned
above is best suited for solving a given goal.
Proof search is a compromise between efficiency and
expressiveness, that is, a tradeoff between how complex goals the
tactic can solve and how much time the tactic requires for
terminating. The tactic [auto] builds proofs only by using the
basic tactics [reflexivity], [assumption], and [apply]. The tactic
[eauto] can also exploit [eapply]. The tactic [jauto] extends
[eauto] by being able to open conjunctions and existentials that
occur in the context. The tactic [iauto] is able to deal with
conjunctions, disjunctions, and negation in a quite clever way;
however it is not able to open existentials from the context.
Also, [iauto] usually becomes very slow when the goal involves
several disjunctions.
Note that proof search tactics never perform any rewriting
step (tactics [rewrite], [subst]), nor any case analysis on an
arbitrary data structure or predicate (tactics [destruct] and
[inversion]), nor any proof by induction (tactic [induction]). So,
proof search is really intended to automate the final steps from
the various branches of a proof. It is not able to discover the
overall structure of a proof. *)
(* ####################################################### *)
(** ** Basics *)
(** The tactic [auto] is able to solve a goal that can be proved
using a sequence of [intros], [apply], [assumption], and [reflexivity].
Two examples follow. The first one shows the ability for
[auto] to call [reflexivity] at any time. In fact, calling
[reflexivity] is always the first thing that [auto] tries to do. *)
Lemma solving_by_reflexivity :
2 + 3 = 5.
Proof. auto. Qed.
(** The second example illustrates a proof where a sequence of
two calls to [apply] are needed. The goal is to prove that
if [Q n] implies [P n] for any [n] and if [Q n] holds for any [n],
then [P 2] holds. *)
Lemma solving_by_apply : forall (P Q : nat->Prop),
(forall n, Q n -> P n) ->
(forall n, Q n) ->
P 2.
Proof. auto. Qed.
(** We can ask [auto] to tell us what proof it came up with,
by invoking [info_auto] in place of [auto]. *)
Lemma solving_by_apply' : forall (P Q : nat->Prop),
(forall n, Q n -> P n) ->
(forall n, Q n) ->
P 2.
Proof. info_auto. Qed.
(* The output is: [intro P; intro Q; intro H;] *)
(* followed with [intro H0; simple apply H; simple apply H0]. *)
(* i.e., the sequence [intros P Q H H0; apply H; apply H0]. *)
(** The tactic [auto] can invoke [apply] but not [eapply]. So, [auto]
cannot exploit lemmas whose instantiation cannot be directly
deduced from the proof goal. To exploit such lemmas, one needs to
invoke the tactic [eauto], which is able to call [eapply].
In the following example, the first hypothesis asserts that [P n]
is true when [Q m] is true for some [m], and the goal is to prove
that [Q 1] implies [P 2]. This implication follows direction from
the hypothesis by instantiating [m] as the value [1]. The
following proof script shows that [eauto] successfully solves the
goal, whereas [auto] is not able to do so. *)
Lemma solving_by_eapply : forall (P Q : nat->Prop),
(forall n m, Q m -> P n) ->
Q 1 -> P 2.
Proof. auto. eauto. Qed.
(** Remark: Again, we can use [info_eauto] to see what proof [eauto]
comes up with. *)
(* ####################################################### *)
(** ** Conjunctions *)
(** So far, we've seen that [eauto] is stronger than [auto] in the
sense that it can deal with [eapply]. In the same way, we are going
to see how [jauto] and [iauto] are stronger than [auto] and [eauto]
in the sense that they provide better support for conjunctions. *)
(** The tactics [auto] and [eauto] can prove a goal of the form
[F /\ F'], where [F] and [F'] are two propositions, as soon as
both [F] and [F'] can be proved in the current context.
An example follows. *)
Lemma solving_conj_goal : forall (P : nat->Prop) (F : Prop),
(forall n, P n) -> F -> F /\ P 2.
Proof. auto. Qed.
(** However, when an assumption is a conjunction, [auto] and [eauto]
are not able to exploit this conjunction. It can be quite
surprising at first that [eauto] can prove very complex goals but
that it fails to prove that [F /\ F'] implies [F]. The tactics
[iauto] and [jauto] are able to decompose conjunctions from the context.
Here is an example. *)
Lemma solving_conj_hyp : forall (F F' : Prop),
F /\ F' -> F.
Proof. auto. eauto. jauto. (* or [iauto] *) Qed.
(** The tactic [jauto] is implemented by first calling a
pre-processing tactic called [jauto_set], and then calling
[eauto]. So, to understand how [jauto] works, one can directly
call the tactic [jauto_set]. *)
Lemma solving_conj_hyp' : forall (F F' : Prop),
F /\ F' -> F.
Proof. intros. jauto_set. eauto. Qed.
(** Next is a more involved goal that can be solved by [iauto] and
[jauto]. *)
Lemma solving_conj_more : forall (P Q R : nat->Prop) (F : Prop),
(F /\ (forall n m, (Q m /\ R n) -> P n)) ->
(F -> R 2) ->
Q 1 ->
P 2 /\ F.
Proof. jauto. (* or [iauto] *) Qed.
(** The strategy of [iauto] and [jauto] is to run a global analysis of
the top-level conjunctions, and then call [eauto]. For this
reason, those tactics are not good at dealing with conjunctions
that occur as the conclusion of some universally quantified
hypothesis. The following example illustrates a general weakness
of Coq proof search mechanisms. *)
Lemma solving_conj_hyp_forall : forall (P Q : nat->Prop),
(forall n, P n /\ Q n) -> P 2.
Proof.
auto. eauto. iauto. jauto.
(* Nothing works, so we have to do some of the work by hand *)
intros. destruct (H 2). auto.
Qed.
(** This situation is slightly disappointing, since automation is
able to prove the following goal, which is very similar. The
only difference is that the universal quantification has been
distributed over the conjunction. *)
Lemma solved_by_jauto : forall (P Q : nat->Prop) (F : Prop),
(forall n, P n) /\ (forall n, Q n) -> P 2.
Proof. jauto. (* or [iauto] *) Qed.
(* ####################################################### *)
(** ** Disjunctions *)
(** The tactics [auto] and [eauto] can handle disjunctions that
occur in the goal. *)
Lemma solving_disj_goal : forall (F F' : Prop),
F -> F \/ F'.
Proof. auto. Qed.
(** However, only [iauto] is able to automate reasoning on the
disjunctions that appear in the context. For example, [iauto] can
prove that [F \/ F'] entails [F' \/ F]. *)
Lemma solving_disj_hyp : forall (F F' : Prop),
F \/ F' -> F' \/ F.
Proof. auto. eauto. jauto. iauto. Qed.
(** More generally, [iauto] can deal with complex combinations of
conjunctions, disjunctions, and negations. Here is an example. *)
Lemma solving_tauto : forall (F1 F2 F3 : Prop),
((~F1 /\ F3) \/ (F2 /\ ~F3)) ->
(F2 -> F1) ->
(F2 -> F3) ->
~F2.
Proof. iauto. Qed.
(** However, the ability of [iauto] to automatically perform a case
analysis on disjunctions comes with a downside: [iauto] may be
very slow. If the context involves several hypotheses with
disjunctions, [iauto] typically generates an exponential number of
subgoals on which [eauto] is called. One major advantage of [jauto]
compared with [iauto] is that it never spends time performing this
kind of case analyses. *)
(* ####################################################### *)
(** ** Existentials *)
(** The tactics [eauto], [iauto], and [jauto] can prove goals whose
conclusion is an existential. For example, if the goal is [exists
x, f x], the tactic [eauto] introduces an existential variable,
say [?25], in place of [x]. The remaining goal is [f ?25], and
[eauto] tries to solve this goal, allowing itself to instantiate
[?25] with any appropriate value. For example, if an assumption [f
2] is available, then the variable [?25] gets instantiated with
[2] and the goal is solved, as shown below. *)
Lemma solving_exists_goal : forall (f : nat->Prop),
f 2 -> exists x, f x.
Proof.
auto. (* observe that [auto] does not deal with existentials, *)
eauto. (* whereas [eauto], [iauto] and [jauto] solve the goal *)
Qed.
(** A major strength of [jauto] over the other proof search tactics is
that it is able to exploit the existentially-quantified
hypotheses, i.e., those of the form [exists x, P]. *)
Lemma solving_exists_hyp : forall (f g : nat->Prop),
(forall x, f x -> g x) ->
(exists a, f a) ->
(exists a, g a).
Proof.
auto. eauto. iauto. (* All of these tactics fail, *)
jauto. (* whereas [jauto] succeeds. *)
(* For the details, run [intros. jauto_set. eauto] *)
Qed.
(* ####################################################### *)
(** ** Negation *)
(** The tactics [auto] and [eauto] suffer from some limitations with
respect to the manipulation of negations, mostly related to the
fact that negation, written [~ P], is defined as [P -> False] but
that the unfolding of this definition is not performed
automatically. Consider the following example. *)
Lemma negation_study_1 : forall (P : nat->Prop),
P 0 -> (forall x, ~ P x) -> False.
Proof.
intros P H0 HX.
eauto. (* It fails to see that [HX] applies *)
unfold not in *. eauto.
Qed.
(** For this reason, the tactics [iauto] and [jauto] systematically
invoke [unfold not in *] as part of their pre-processing. So,
they are able to solve the previous goal right away. *)
Lemma negation_study_2 : forall (P : nat->Prop),
P 0 -> (forall x, ~ P x) -> False.
Proof. jauto. (* or [iauto] *) Qed.
(** We will come back later on to the behavior of proof search with
respect to the unfolding of definitions. *)
(* ####################################################### *)
(** ** Equalities *)
(** Coq's proof-search feature is not good at exploiting equalities.
It can do very basic operations, like exploiting reflexivity
and symmetry, but that's about it. Here is a simple example
that [auto] can solve, by first calling [symmetry] and then
applying the hypothesis. *)
Lemma equality_by_auto : forall (f g : nat->Prop),
(forall x, f x = g x) -> g 2 = f 2.
Proof. auto. Qed.
(** To automate more advanced reasoning on equalities, one should
rather try to use the tactic [congruence], which is presented at
the end of this chapter in the "Decision Procedures" section. *)
(* ####################################################### *)
(** * How Proof Search Works *)
(* ####################################################### *)
(** ** Search Depth *)
(** The tactic [auto] works as follows. It first tries to call
[reflexivity] and [assumption]. If one of these calls solves the
goal, the job is done. Otherwise [auto] tries to apply the most
recently introduced assumption that can be applied to the goal
without producing and error. This application produces
subgoals. There are two possible cases. If the sugboals produced
can be solved by a recursive call to [auto], then the job is done.
Otherwise, if this application produces at least one subgoal that
[auto] cannot solve, then [auto] starts over by trying to apply
the second most recently introduced assumption. It continues in a
similar fashion until it finds a proof or until no assumption
remains to be tried.
It is very important to have a clear idea of the backtracking
process involved in the execution of the [auto] tactic; otherwise
its behavior can be quite puzzling. For example, [auto] is not
able to solve the following triviality. *)
Lemma search_depth_0 :
True /\ True /\ True /\ True /\ True /\ True.
Proof.
auto.
Abort.
(** The reason [auto] fails to solve the goal is because there are
too many conjunctions. If there had been only five of them, [auto]
would have successfully solved the proof, but six is too many.
The tactic [auto] limits the number of lemmas and hypotheses
that can be applied in a proof, so as to ensure that the proof
search eventually terminates. By default, the maximal number
of steps is five. One can specify a different bound, writing
for example [auto 6] to search for a proof involving at most
six steps. For example, [auto 6] would solve the previous lemma.
(Similarly, one can invoke [eauto 6] or [intuition eauto 6].)
The argument [n] of [auto n] is called the "search depth."
The tactic [auto] is simply defined as a shorthand for [auto 5].
The behavior of [auto n] can be summarized as follows. It first
tries to solve the goal using [reflexivity] and [assumption]. If
this fails, it tries to apply a hypothesis (or a lemma that has
been registered in the hint database), and this application
produces a number of sugoals. The tactic [auto (n-1)] is then
called on each of those subgoals. If all the subgoals are solved,
the job is completed, otherwise [auto n] tries to apply a
different hypothesis.
During the process, [auto n] calls [auto (n-1)], which in turn
might call [auto (n-2)], and so on. The tactic [auto 0] only
tries [reflexivity] and [assumption], and does not try to apply
any lemma. Overall, this means that when the maximal number of
steps allowed has been exceeded, the [auto] tactic stops searching
and backtracks to try and investigate other paths. *)
(** The following lemma admits a unique proof that involves exactly
three steps. So, [auto n] proves this goal iff [n] is greater than
three. *)
Lemma search_depth_1 : forall (P : nat->Prop),
P 0 ->
(P 0 -> P 1) ->
(P 1 -> P 2) ->
(P 2).
Proof.
auto 0. (* does not find the proof *)
auto 1. (* does not find the proof *)
auto 2. (* does not find the proof *)
auto 3. (* finds the proof *)
(* more generally, [auto n] solves the goal if [n >= 3] *)
Qed.
(** We can generalize the example by introducing an assumption
asserting that [P k] is derivable from [P (k-1)] for all [k],
and keep the assumption [P 0]. The tactic [auto], which is the
same as [auto 5], is able to derive [P k] for all values of [k]
less than 5. For example, it can prove [P 4]. *)
Lemma search_depth_3 : forall (P : nat->Prop),
(* Hypothesis H1: *) (P 0) ->
(* Hypothesis H2: *) (forall k, P (k-1) -> P k) ->
(* Goal: *) (P 4).
Proof. auto. Qed.
(** However, to prove [P 5], one needs to call at least [auto 6]. *)
Lemma search_depth_4 : forall (P : nat->Prop),
(* Hypothesis H1: *) (P 0) ->
(* Hypothesis H2: *) (forall k, P (k-1) -> P k) ->
(* Goal: *) (P 5).
Proof. auto. auto 6. Qed.
(** Because [auto] looks for proofs at a limited depth, there are
cases where [auto] can prove a goal [F] and can prove a goal
[F'] but cannot prove [F /\ F']. In the following example,
[auto] can prove [P 4] but it is not able to prove [P 4 /\ P 4],
because the splitting of the conjunction consumes one proof step.
To prove the conjunction, one needs to increase the search depth,
using at least [auto 6]. *)
Lemma search_depth_5 : forall (P : nat->Prop),
(* Hypothesis H1: *) (P 0) ->
(* Hypothesis H2: *) (forall k, P (k-1) -> P k) ->
(* Goal: *) (P 4 /\ P 4).
Proof. auto. auto 6. Qed.
(* ####################################################### *)
(** ** Backtracking *)
(** In the previous section, we have considered proofs where
at each step there was a unique assumption that [auto]
could apply. In general, [auto] can have several choices
at every step. The strategy of [auto] consists of trying all
of the possibilities (using a depth-first search exploration).
To illustrate how automation works, we are going to extend the
previous example with an additional assumption asserting that
[P k] is also derivable from [P (k+1)]. Adding this hypothesis
offers a new possibility that [auto] could consider at every step.
There exists a special command that one can use for tracing
all the steps that proof-search considers. To view such a
trace, one should write [debug eauto]. (For some reason, the
command [debug auto] does not exist, so we have to use the
command [debug eauto] instead.) *)
Lemma working_of_auto_1 : forall (P : nat->Prop),
(* Hypothesis H1: *) (P 0) ->
(* Hypothesis H2: *) (forall k, P (k+1) -> P k) ->
(* Hypothesis H3: *) (forall k, P (k-1) -> P k) ->
(* Goal: *) (P 2).
(* Uncomment "debug" in the following line to see the debug trace: *)
Proof. intros P H1 H2 H3. (* debug *) eauto. Qed.
(** The output message produced by [debug eauto] is as follows.
<<
depth=5
depth=4 apply H3
depth=3 apply H3
depth=3 exact H1
>>
The depth indicates the value of [n] with which [eauto n] is
called. The tactics shown in the message indicate that the first
thing that [eauto] has tried to do is to apply [H3]. The effect of
applying [H3] is to replace the goal [P 2] with the goal [P 1].
Then, again, [H3] has been applied, changing the goal [P 1] into
[P 0]. At that point, the goal was exactly the hypothesis [H1].
It seems that [eauto] was quite lucky there, as it never even
tried to use the hypothesis [H2] at any time. The reason is that
[auto] always tries to use the most recently introduced hypothesis
first, and [H3] is a more recent hypothesis than [H2] in the goal.
So, let's permute the hypotheses [H2] and [H3] and see what
happens. *)
Lemma working_of_auto_2 : forall (P : nat->Prop),
(* Hypothesis H1: *) (P 0) ->
(* Hypothesis H3: *) (forall k, P (k-1) -> P k) ->
(* Hypothesis H2: *) (forall k, P (k+1) -> P k) ->
(* Goal: *) (P 2).
Proof. intros P H1 H3 H2. (* debug *) eauto. Qed.
(** This time, the output message suggests that the proof search
investigates many possibilities. Replacing [debug eauto] with
[info_eauto], we observe that the proof that [eauto] comes up
with is actually not the simplest one.
[apply H2; apply H3; apply H3; apply H3; exact H1]
This proof goes through the proof obligation [P 3], even though
it is not any useful. The following tree drawing describes
all the goals that automation has been through.
<<
|5||4||3||2||1||0| -- below, tabulation indicates the depth
[P 2]
-> [P 3]
-> [P 4]
-> [P 5]
-> [P 6]
-> [P 7]
-> [P 5]
-> [P 4]
-> [P 5]
-> [P 3]
--> [P 3]
-> [P 4]
-> [P 5]
-> [P 3]
-> [P 2]
-> [P 3]
-> [P 1]
-> [P 2]
-> [P 3]
-> [P 4]
-> [P 5]
-> [P 3]
-> [P 2]
-> [P 3]
-> [P 1]
-> [P 1]
-> [P 2]
-> [P 3]
-> [P 1]
-> [P 0]
-> !! Done !!
>>
The first few lines read as follows. To prove [P 2], [eauto 5]
has first tried to apply [H2], producing the subgoal [P 3].
To solve it, [eauto 4] has tried again to apply [H2], producing
the goal [P 4]. Similarly, the search goes through [P 5], [P 6]
and [P 7]. When reaching [P 7], the tactic [eauto 0] is called
but as it is not allowed to try and apply any lemma, it fails.
So, we come back to the goal [P 6], and try this time to apply
hypothesis [H3], producing the subgoal [P 5]. Here again,
[eauto 0] fails to solve this goal.
The process goes on and on, until backtracking to [P 3] and trying
to apply [H2] three times in a row, going through [P 2] and [P 1]
and [P 0]. This search tree explains why [eauto] came up with a
proof starting with [apply H2]. *)
(* ####################################################### *)
(** ** Adding Hints *)
(** By default, [auto] (and [eauto]) only tries to apply the
hypotheses that appear in the proof context. There are two
possibilities for telling [auto] to exploit a lemma that have
been proved previously: either adding the lemma as an assumption
just before calling [auto], or adding the lemma as a hint, so
that it can be used by every calls to [auto].
The first possibility is useful to have [auto] exploit a lemma
that only serves at this particular point. To add the lemma as
hypothesis, one can type [generalize mylemma; intros], or simply
[lets: mylemma] (the latter requires [LibTactics.v]).
The second possibility is useful for lemmas that need to be
exploited several times. The syntax for adding a lemma as a hint
is [Hint Resolve mylemma]. For example, the lemma asserting than
any number is less than or equal to itself, [forall x, x <= x],
called [Le.le_refl] in the Coq standard library, can be added as a
hint as follows. *)
Hint Resolve Le.le_refl.
(** A convenient shorthand for adding all the constructors of an
inductive datatype as hints is the command [Hint Constructors
mydatatype].
Warning: some lemmas, such as transitivity results, should
not be added as hints as they would very badly affect the
performance of proof search. The description of this problem
and the presentation of a general work-around for transitivity
lemmas appear further on. *)
(* ####################################################### *)
(** ** Integration of Automation in Tactics *)
(** The library "LibTactics" introduces a convenient feature for
invoking automation after calling a tactic. In short, it suffices
to add the symbol star ([*]) to the name of a tactic. For example,
[apply* H] is equivalent to [apply H; auto_star], where [auto_star]
is a tactic that can be defined as needed. By default, [auto_star]
first tries to solve the goal using [auto], and if this does not
succeed then it tries to call [jauto]. Even though [jauto] is
strictly stronger than [auto], it makes sense to call [auto] first:
when [auto] succeeds it may save a lot of time, and when [auto]
fails to prove the goal, it fails very quickly.
The definition of [auto_star], which determines the meaning of the
star symbol, can be modified whenever needed. Simply write:
Ltac auto_star ::= a_new_definition.
]]
Observe the use of [::=] instead of [:=], which indicates that the
tactic is being rebound to a new definition. So, the default
definition is as follows. *)
Ltac auto_star ::= try solve [ auto | jauto ].
(** Nearly all standard Coq tactics and all the tactics from
"LibTactics" can be called with a star symbol. For example, one
can invoke [subst*], [destruct* H], [inverts* H], [lets* I: H x],
[specializes* H x], and so on... There are two notable exceptions.
The tactic [auto*] is just another name for the tactic
[auto_star]. And the tactic [apply* H] calls [eapply H] (or the
more powerful [applys H] if needed), and then calls [auto_star].
Note that there is no [eapply* H] tactic, use [apply* H]
instead. *)
(** In large developments, it can be convenient to use two degrees of
automation. Typically, one would use a fast tactic, like [auto],
and a slower but more powerful tactic, like [jauto]. To allow for
a smooth coexistence of the two form of automation, [LibTactics.v]
also defines a "tilde" version of tactics, like [apply~ H],
[destruct~ H], [subst~], [auto~] and so on. The meaning of the
tilde symbol is described by the [auto_tilde] tactic, whose
default implementation is [auto]. *)
Ltac auto_tilde ::= auto.
(** In the examples that follow, only [auto_star] is needed. *)
(* ####################################################### *)
(** * Examples of Use of Automation *)
(** Let's see how to use proof search in practice on the main theorems
of the "Software Foundations" course, proving in particular
results such as determinism, preservation and progress. *)
(* ####################################################### *)
(** ** Determinism *)
Module DeterministicImp.
Require Import Imp.
(** Recall the original proof of the determinism lemma for the IMP
language, shown below. *)
Theorem ceval_deterministic: forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2.
generalize dependent st2.
(ceval_cases (induction E1) Case); intros st2 E2; inversion E2; subst.
Case "E_Skip". reflexivity.
Case "E_Ass". reflexivity.
Case "E_Seq".
assert (st' = st'0) as EQ1.
SCase "Proof of assertion". apply IHE1_1; assumption.
subst st'0.
apply IHE1_2. assumption.
Case "E_IfTrue".
SCase "b1 evaluates to true".
apply IHE1. assumption.
SCase "b1 evaluates to false (contradiction)".
rewrite H in H5. inversion H5.
Case "E_IfFalse".
SCase "b1 evaluates to true (contradiction)".
rewrite H in H5. inversion H5.
SCase "b1 evaluates to false".
apply IHE1. assumption.
Case "E_WhileEnd".
SCase "b1 evaluates to true".
reflexivity.
SCase "b1 evaluates to false (contradiction)".
rewrite H in H2. inversion H2.
Case "E_WhileLoop".
SCase "b1 evaluates to true (contradiction)".
rewrite H in H4. inversion H4.
SCase "b1 evaluates to false".
assert (st' = st'0) as EQ1.
SSCase "Proof of assertion". apply IHE1_1; assumption.
subst st'0.
apply IHE1_2. assumption.
Qed.
(** Exercise: rewrite this proof using [auto] whenever possible.
(The solution uses [auto] 9 times.) *)
Theorem ceval_deterministic': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
(* FILL IN HERE *) admit.
Qed.
(** In fact, using automation is not just a matter of calling [auto]
in place of one or two other tactics. Using automation is about
rethinking the organization of sequences of tactics so as to
minimize the effort involved in writing and maintaining the proof.
This process is eased by the use of the tactics from
[LibTactics.v]. So, before trying to optimize the way automation
is used, let's first rewrite the proof of determinism:
- use [introv H] instead of [intros x H],
- use [gen x] instead of [generalize dependent x],
- use [inverts H] instead of [inversion H; subst],
- use [tryfalse] to handle contradictions, and get rid of
the cases where [beval st b1 = true] and [beval st b1 = false]
both appear in the context,
- stop using [ceval_cases] to label subcases. *)
Theorem ceval_deterministic'': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
introv E1 E2. gen st2.
induction E1; intros; inverts E2; tryfalse.
auto.
auto.
assert (st' = st'0). auto. subst. auto.
auto.
auto.
auto.
assert (st' = st'0). auto. subst. auto.
Qed.
(** To obtain a nice clean proof script, we have to remove the calls
[assert (st' = st'0)]. Such a tactic invokation is not nice
because it refers to some variables whose name has been
automatically generated. This kind of tactics tend to be very
brittle. The tactic [assert (st' = st'0)] is used to assert the
conclusion that we want to derive from the induction
hypothesis. So, rather than stating this conclusion explicitly, we
are going to ask Coq to instantiate the induction hypothesis,
using automation to figure out how to instantiate it. The tactic
[forwards], described in [LibTactics.v] precisely helps with
instantiating a fact. So, let's see how it works out on our
example. *)
Theorem ceval_deterministic''': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
(* Let's replay the proof up to the [assert] tactic. *)
introv E1 E2. gen st2.
induction E1; intros; inverts E2; tryfalse.
auto. auto.
(* We duplicate the goal for comparing different proofs. *)
dup 4.
(* The old proof: *)
assert (st' = st'0). apply IHE1_1. apply H1.
(* produces [H: st' = st'0]. *) skip.
(* The new proof, without automation: *)
forwards: IHE1_1. apply H1.
(* produces [H: st' = st'0]. *) skip.
(* The new proof, with automation: *)
forwards: IHE1_1. eauto.
(* produces [H: st' = st'0]. *) skip.
(* The new proof, with integrated automation: *)
forwards*: IHE1_1.
(* produces [H: st' = st'0]. *) skip.
Abort.
(** To polish the proof script, it remains to factorize the calls
to [auto], using the star symbol. The proof of determinism can then
be rewritten in only four lines, including no more than 10 tactics. *)
Theorem ceval_deterministic'''': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
introv E1 E2. gen st2.
induction E1; intros; inverts* E2; tryfalse.
forwards*: IHE1_1. subst*.
forwards*: IHE1_1. subst*.
Qed.
End DeterministicImp.
(* ####################################################### *)
(** ** Preservation for STLC *)
Module PreservationProgressStlc.
Require Import StlcProp.
Import STLC.
Import STLCProp.
(** Consider the proof of perservation of STLC, shown below.
This proof already uses [eauto] through the triple-dot
mechanism. *)
Theorem preservation : forall t t' T,
has_type empty t T ->
t ==> t' ->
has_type empty t' T.
Proof with eauto.
remember (@empty ty) as Gamma.
intros t t' T HT. generalize dependent t'.
(has_type_cases (induction HT) Case); intros t' HE; subst Gamma.
Case "T_Var".
inversion HE.
Case "T_Abs".
inversion HE.
Case "T_App".
inversion HE; subst...
(* (step_cases (inversion HE) SCase); subst...*)
(* The ST_App1 and ST_App2 cases are immediate by induction, and
auto takes care of them *)
SCase "ST_AppAbs".
apply substitution_preserves_typing with T11...
inversion HT1...
Case "T_True".
inversion HE.
Case "T_False".
inversion HE.
Case "T_If".
inversion HE; subst...
Qed.
(** Exercise: rewrite this proof using tactics from [LibTactics]
and calling automation using the star symbol rather than the
triple-dot notation. More precisely, make use of the tactics
[inverts*] and [applys*] to call [auto*] after a call to
[inverts] or to [applys]. The solution is three lines long.*)
Theorem preservation' : forall t t' T,
has_type empty t T ->
t ==> t' ->
has_type empty t' T.
Proof.
(* FILL IN HERE *) admit.
Qed.
(* ####################################################### *)
(** ** Progress for STLC *)
(** Consider the proof of the progress theorem. *)
Theorem progress : forall t T,
has_type empty t T ->
value t \/ exists t', t ==> t'.
Proof with eauto.
intros t T Ht.
remember (@empty ty) as Gamma.
(has_type_cases (induction Ht) Case); subst Gamma...
Case "T_Var".
inversion H.
Case "T_App".
right. destruct IHHt1...
SCase "t1 is a value".
destruct IHHt2...
SSCase "t2 is a value".
inversion H; subst; try solve by inversion.
exists ([x0:=t2]t)...
SSCase "t2 steps".
destruct H0 as [t2' Hstp]. exists (tapp t1 t2')...
SCase "t1 steps".
destruct H as [t1' Hstp]. exists (tapp t1' t2)...
Case "T_If".
right. destruct IHHt1...
destruct t1; try solve by inversion...
inversion H. exists (tif x0 t2 t3)...
Qed.
(** Exercise: optimize the above proof.
Hint: make use of [destruct*] and [inverts*].
The solution consists of 10 short lines. *)
Theorem progress' : forall t T,
has_type empty t T ->
value t \/ exists t', t ==> t'.
Proof.
(* FILL IN HERE *) admit.
Qed.
End PreservationProgressStlc.
(* ####################################################### *)
(** ** BigStep and SmallStep *)
Module Semantics.
Require Import Smallstep.
(** Consider the proof relating a small-step reduction judgment
to a big-step reduction judgment. *)
Theorem multistep__eval : forall t v,
normal_form_of t v -> exists n, v = C n /\ t || n.
Proof.
intros t v Hnorm.
unfold normal_form_of in Hnorm.
inversion Hnorm as [Hs Hnf]; clear Hnorm.
rewrite nf_same_as_value in Hnf. inversion Hnf. clear Hnf.
exists n. split. reflexivity.
multi_cases (induction Hs) Case; subst.
Case "multi_refl".
apply E_Const.
Case "multi_step".
eapply step__eval. eassumption. apply IHHs. reflexivity.
Qed.
(** Our goal is to optimize the above proof. It is generally
easier to isolate inductions into separate lemmas. So,
we are going to first prove an intermediate result
that consists of the judgment over which the induction
is being performed. *)
(** Exercise: prove the following result, using tactics
[introv], [induction] and [subst], and [apply*].
The solution is 3 lines long. *)
Theorem multistep_eval_ind : forall t v,
t ==>* v -> forall n, C n = v -> t || n.
Proof.
(* FILL IN HERE *) admit.
Qed.
(** Exercise: using the lemma above, simplify the proof of
the result [multistep__eval]. You should use the tactics
[introv], [inverts], [split*] and [apply*].
The solution is 2 lines long. *)
Theorem multistep__eval' : forall t v,
normal_form_of t v -> exists n, v = C n /\ t || n.
Proof.
(* FILL IN HERE *) admit.
Qed.
(** If we try to combine the two proofs into a single one,
we will likely fail, because of a limitation of the
[induction] tactic. Indeed, this tactic looses
information when applied to a predicate whose arguments
are not reduced to variables, such as [t ==>* (C n)].
You will thus need to use the more powerful tactic called
[dependent induction]. This tactic is available only after
importing the [Program] library, as shown below. *)
Require Import Program.
(** Exercise: prove the lemma [multistep__eval] without invoking
the lemma [multistep_eval_ind], that is, by inlining the proof
by induction involved in [multistep_eval_ind], using the
tactic [dependent induction] instead of [induction].
The solution is 5 lines long. *)
Theorem multistep__eval'' : forall t v,
normal_form_of t v -> exists n, v = C n /\ t || n.
Proof.
(* FILL IN HERE *) admit.
Qed.
End Semantics.
(* ####################################################### *)
(** ** Preservation for STLCRef *)
Module PreservationProgressReferences.
Require Import References.
Import STLCRef.
Hint Resolve store_weakening extends_refl.
(** The proof of preservation for [STLCRef] can be found in chapter
[References]. It contains 58 lines (not counting the labelling of
cases). The optimized proof script is more than twice shorter. The
following material explains how to build the optimized proof
script. The resulting optimized proof script for the preservation
theorem appears afterwards. *)
Theorem preservation : forall ST t t' T st st',
has_type empty ST t T ->
store_well_typed ST st ->
t / st ==> t' / st' ->
exists ST',
(extends ST' ST /\
has_type empty ST' t' T /\
store_well_typed ST' st').
Proof.
(* old: [Proof. with eauto using store_weakening, extends_refl.]
new: [Proof.], and the two lemmas are registered as hints
before the proof of the lemma, possibly inside a section in
order to restrict the scope of the hints. *)
remember (@empty ty) as Gamma. introv Ht. gen t'.
(has_type_cases (induction Ht) Case); introv HST Hstep;
(* old: [subst; try (solve by inversion); inversion Hstep; subst;
try (eauto using store_weakening, extends_refl)]
new: [subst Gamma; inverts Hstep; eauto.]
We want to be more precise on what exactly we substitute,
and we do not want to call [try (solve by inversion)] which
is way to slow. *)
subst Gamma; inverts Hstep; eauto.
Case "T_App".
SCase "ST_AppAbs".
(* old:
exists ST. inversion Ht1; subst.
split; try split... eapply substitution_preserves_typing... *)
(* new: we use [inverts] in place of [inversion] and [splits] to
split the conjunction, and [applys*] in place of [eapply...] *)
exists ST. inverts Ht1. splits*. applys* substitution_preserves_typing.
SCase "ST_App1".
(* old:
eapply IHHt1 in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'... *)
(* new: The tactic [eapply IHHt1 in H0...] applies [IHHt1] to [H0].
But [H0] is only thing that [IHHt1] could be applied to, so
there [eauto] can figure this out on its own. The tactic
[forwards] is used to instantiate all the arguments of [IHHt1],
producing existential variables and subgoals when needed. *)
forwards: IHHt1. eauto. eauto. eauto.
(* At this point, we need to decompose the hypothesis [H] that has
just been created by [forwards]. This is done by the first part
of the preprocessing phase of [jauto]. *)
jauto_set_hyps; intros.
(* It remains to decompose the goal, which is done by the second
part of the preprocessing phase of [jauto]. *)
jauto_set_goal; intros.
(* All the subgoals produced can then be solved by [eauto]. *)
eauto. eauto. eauto.
SCase "ST_App2".
(* old:
eapply IHHt2 in H5...
inversion H5 as [ST' [Hext [Hty Hsty]]].
exists ST'... *)
(* new: this time, we need to call [forwards] on [IHHt2],
and we call [jauto] right away, by writing [forwards*],
proving the goal in a single tactic! *)
forwards*: IHHt2.
(* The same trick works for many of the other subgoals. *)
forwards*: IHHt.
forwards*: IHHt.
forwards*: IHHt1.
forwards*: IHHt2.
forwards*: IHHt1.
Case "T_Ref".
SCase "ST_RefValue".
(* old:
exists (snoc ST T1).
inversion HST; subst.
split.
apply extends_snoc.
split.
replace (TRef T1)
with (TRef (store_Tlookup (length st) (snoc ST T1))).
apply T_Loc.
rewrite <- H. rewrite length_snoc. omega.
unfold store_Tlookup. rewrite <- H. rewrite nth_eq_snoc...
apply store_well_typed_snoc; assumption. *)
(* new: in this proof case, we need to perform an inversion
without removing the hypothesis. The tactic [inverts keep]
serves exactly this purpose. *)
exists (snoc ST T1). inverts keep HST. splits.
(* The proof of the first subgoal needs not be changed *)
apply extends_snoc.
(* For the second subgoal, we use the tactic [applys_eq] to avoid
a manual [replace] before [T_loc] can be applied. *)
applys_eq T_Loc 1.
(* To justify the inequality, there is no need to call [rewrite <- H],
because the tactic [omega] is able to exploit [H] on its own.
So, only the rewriting of [lenght_snoc] and the call to the
tactic [omega] remain. *)
rewrite length_snoc. omega.
(* The next proof case is hard to polish because it relies on the
lemma [nth_eq_snoc] whose statement is not automation-friendly.
We'll come back to this proof case further on. *)
unfold store_Tlookup. rewrite <- H. rewrite* nth_eq_snoc.
(* Last, we replace [apply ..; assumption] with [apply* ..] *)
apply* store_well_typed_snoc.
forwards*: IHHt.
Case "T_Deref".
SCase "ST_DerefLoc".
(* old:
exists ST. split; try split...
destruct HST as [_ Hsty].
replace T11 with (store_Tlookup l ST).
apply Hsty...
inversion Ht; subst... *)
(* new: we start by calling [exists ST] and [splits*]. *)
exists ST. splits*.
(* new: we replace [destruct HST as [_ Hsty]] by the following *)
lets [_ Hsty]: HST.
(* new: then we use the tactic [applys_eq] to avoid the need to
perform a manual [replace] before applying [Hsty]. *)
applys_eq* Hsty 1.
(* new: we then can call [inverts] in place of [inversion;subst] *)
inverts* Ht.
forwards*: IHHt.
Case "T_Assign".
SCase "ST_Assign".
(* old:
exists ST. split; try split...
eapply assign_pres_store_typing...
inversion Ht1; subst... *)
(* new: simply using nicer tactics *)
exists ST. splits*. applys* assign_pres_store_typing. inverts* Ht1.
forwards*: IHHt1.
forwards*: IHHt2.
Qed.
(** Let's come back to the proof case that was hard to optimize.
The difficulty comes from the statement of [nth_eq_snoc], which
takes the form [nth (length l) (snoc l x) d = x]. This lemma is
hard to exploit because its first argument, [length l], mentions
a list [l] that has to be exactly the same as the [l] occuring in
[snoc l x]. In practice, the first argument is often a natural
number [n] that is provably equal to [length l] yet that is not
syntactically equal to [length l]. There is a simple fix for
making [nth_eq_snoc] easy to apply: introduce the intermediate
variable [n] explicitly, so that the goal becomes
[nth n (snoc l x) d = x], with a premise asserting [n = length l]. *)
Lemma nth_eq_snoc' : forall (A : Type) (l : list A) (x d : A) (n : nat),
n = length l -> nth n (snoc l x) d = x.
Proof. intros. subst. apply nth_eq_snoc. Qed.
(** The proof case for [ref] from the preservation theorem then
becomes much easier to prove, because [rewrite nth_eq_snoc']
now succeeds. *)
Lemma preservation_ref : forall (st:store) (ST : store_ty) T1,
length ST = length st ->
TRef T1 = TRef (store_Tlookup (length st) (snoc ST T1)).
Proof.
intros. dup.
(* A first proof, with an explicit [unfold] *)
unfold store_Tlookup. rewrite* nth_eq_snoc'.
(* A second proof, with a call to [fequal] *)
fequal. symmetry. apply* nth_eq_snoc'.
Qed.
(** The optimized proof of preservation is summarized next. *)
Theorem preservation' : forall ST t t' T st st',
has_type empty ST t T ->
store_well_typed ST st ->
t / st ==> t' / st' ->
exists ST',
(extends ST' ST /\
has_type empty ST' t' T /\
store_well_typed ST' st').
Proof.
remember (@empty ty) as Gamma. introv Ht. gen t'.
induction Ht; introv HST Hstep; subst Gamma; inverts Hstep; eauto.
exists ST. inverts Ht1. splits*. applys* substitution_preserves_typing.
forwards*: IHHt1.
forwards*: IHHt2.
forwards*: IHHt.
forwards*: IHHt.
forwards*: IHHt1.
forwards*: IHHt2.
forwards*: IHHt1.
exists (snoc ST T1). inverts keep HST. splits.
apply extends_snoc.
applys_eq T_Loc 1.
rewrite length_snoc. omega.
unfold store_Tlookup. rewrite* nth_eq_snoc'.
apply* store_well_typed_snoc.
forwards*: IHHt.
exists ST. splits*. lets [_ Hsty]: HST.
applys_eq* Hsty 1. inverts* Ht.
forwards*: IHHt.
exists ST. splits*. applys* assign_pres_store_typing. inverts* Ht1.
forwards*: IHHt1.
forwards*: IHHt2.
Qed.
(* ####################################################### *)
(** ** Progress for STLCRef *)
(** The proof of progress for [STLCRef] can be found in chapter
[References]. It contains 53 lines and the optimized proof script
is, here again, half the length. *)
Theorem progress : forall ST t T st,
has_type empty ST t T ->
store_well_typed ST st ->
(value t \/ exists t', exists st', t / st ==> t' / st').
Proof.
introv Ht HST. remember (@empty ty) as Gamma.
induction Ht; subst Gamma; tryfalse; try solve [left*].
right. destruct* IHHt1 as [K|].
inverts K; inverts Ht1.
destruct* IHHt2.
right. destruct* IHHt as [K|].
inverts K; try solve [inverts Ht]. eauto.
right. destruct* IHHt as [K|].
inverts K; try solve [inverts Ht]. eauto.
right. destruct* IHHt1 as [K|].
inverts K; try solve [inverts Ht1].
destruct* IHHt2 as [M|].
inverts M; try solve [inverts Ht2]. eauto.
right. destruct* IHHt1 as [K|].
inverts K; try solve [inverts Ht1]. destruct* n.
right. destruct* IHHt.
right. destruct* IHHt as [K|].
inverts K; inverts Ht as M.
inverts HST as N. rewrite* N in M.
right. destruct* IHHt1 as [K|].
destruct* IHHt2.
inverts K; inverts Ht1 as M.
inverts HST as N. rewrite* N in M.
Qed.
End PreservationProgressReferences.
(* ####################################################### *)
(** ** Subtyping *)
Module SubtypingInversion.
Require Import Sub.
(** Consider the inversion lemma for typing judgment
of abstractions in a type system with subtyping. *)
Lemma abs_arrow : forall x S1 s2 T1 T2,
has_type empty (tabs x S1 s2) (TArrow T1 T2) ->
subtype T1 S1
/\ has_type (extend empty x S1) s2 T2.
Proof with eauto.
intros x S1 s2 T1 T2 Hty.
apply typing_inversion_abs in Hty.
destruct Hty as [S2 [Hsub Hty]].
apply sub_inversion_arrow in Hsub.
destruct Hsub as [U1 [U2 [Heq [Hsub1 Hsub2]]]].
inversion Heq; subst...
Qed.
(** Exercise: optimize the proof script, using
[introv], [lets] and [inverts*]. In particular,
you will find it useful to replace the pattern
[apply K in H. destruct H as I] with [lets I: K H].
The solution is 4 lines. *)
Lemma abs_arrow' : forall x S1 s2 T1 T2,
has_type empty (tabs x S1 s2) (TArrow T1 T2) ->
subtype T1 S1
/\ has_type (extend empty x S1) s2 T2.
Proof.
(* FILL IN HERE *) admit.
Qed.
(** The lemma [substitution_preserves_typing] has already been used to
illustrate the working of [lets] and [applys] in chapter
[UseTactics]. Optimize further this proof using automation (with
the star symbol), and using the tactic [cases_if']. The solution
is 33 lines, including the [Case] instructions (21 lines without
them). *)
Lemma substitution_preserves_typing : forall Gamma x U v t S,
has_type (extend Gamma x U) t S ->
has_type empty v U ->
has_type Gamma ([x:=v]t) S.
Proof.
(* FILL IN HERE *) admit.
Qed.
End SubtypingInversion.
(* ####################################################### *)
(** * Advanced Topics in Proof Search *)
(* ####################################################### *)
(** ** Stating Lemmas in the Right Way *)
(** Due to its depth-first strategy, [eauto] can get exponentially
slower as the depth search increases, even when a short proof
exists. In general, to make proof search run reasonably fast, one
should avoid using a depth search greater than 5 or 6. Moreover,
one should try to minimize the number of applicable lemmas, and
usually put first the hypotheses whose proof usefully instantiates
the existential variables.
In fact, the ability for [eauto] to solve certain goals actually
depends on the order in which the hypotheses are stated. This point
is illustrated through the following example, in which [P] is
a predicate on natural numbers. This predicate is such that
[P n] holds for any [n] as soon as [P m] holds for at least one [m]
different from zero. The goal is to prove that [P 2] implies [P 1].
When the hypothesis about [P] is stated in the form
[forall n m, P m -> m <> 0 -> P n], then [eauto] works. However, with
[forall n m, m <> 0 -> P m -> P n], the tactic [eauto] fails. *)
Lemma order_matters_1 : forall (P : nat->Prop),
(forall n m, P m -> m <> 0 -> P n) -> P 2 -> P 1.
Proof.
eauto. (* Success *)
(* The proof: [intros P H K. eapply H. apply K. auto.] *)
Qed.
Lemma order_matters_2 : forall (P : nat->Prop),
(forall n m, m <> 0 -> P m -> P n) -> P 5 -> P 1.
Proof.
eauto. (* Failure *)
(* To understand why, let us replay the previous proof *)
intros P H K.
eapply H.
(* The application of [eapply] has left two subgoals,
[?X <> 0] and [P ?X], where [?X] is an existential variable. *)
(* Solving the first subgoal is easy for [eauto]: it suffices
to instantiate [?X] as the value [1], which is the simplest
value that satisfies [?X <> 0]. *)
eauto.
(* But then the second goal becomes [P 1], which is where we
started from. So, [eauto] gets stuck at this point. *)
Abort.
(** It is very important to understand that the hypothesis [forall n
m, P m -> m <> 0 -> P n] is eauto-friendly, whereas [forall n m, m
<> 0 -> P m -> P n] really isn't. Guessing a value of [m] for
which [P m] holds and then checking that [m <> 0] holds works well
because there are few values of [m] for which [P m] holds. So, it
is likely that [eauto] comes up with the right one. On the other
hand, guessing a value of [m] for which [m <> 0] and then checking
that [P m] holds does not work well, because there are many values
of [m] that satisfy [m <> 0] but not [P m]. *)
(* ####################################################### *)
(** ** Unfolding of Definitions During Proof-Search *)
(** The use of intermediate definitions is generally encouraged in a
formal development as it usually leads to more concise and more
readable statements. Yet, definitions can make it a little harder
to automate proofs. The problem is that it is not obvious for a
proof search mechanism to know when definitions need to be
unfolded. Note that a naive strategy that consists in unfolding
all definitions before calling proof search does not scale up to
large proofs, so we avoid it. This section introduces a few
techniques for avoiding to manually unfold definitions before
calling proof search. *)
(** To illustrate the treatment of definitions, let [P] be an abstract
predicate on natural numbers, and let [myFact] be a definition
denoting the proposition [P x] holds for any [x] less than or
equal to 3. *)
Axiom P : nat -> Prop.
Definition myFact := forall x, x <= 3 -> P x.
(** Proving that [myFact] under the assumption that [P x] holds for
any [x] should be trivial. Yet, [auto] fails to prove it unless we
unfold the definition of [myFact] explicitly. *)
Lemma demo_hint_unfold_goal_1 :
(forall x, P x) -> myFact.
Proof.
auto. (* Proof search doesn't know what to do, *)
unfold myFact. auto. (* unless we unfold the definition. *)
Qed.
(** To automate the unfolding of definitions that appear as proof
obligation, one can use the command [Hint Unfold myFact] to tell
Coq that it should always try to unfold [myFact] when [myFact]
appears in the goal. *)
Hint Unfold myFact.
(** This time, automation is able to see through the definition
of [myFact]. *)
Lemma demo_hint_unfold_goal_2 :
(forall x, P x) -> myFact.
Proof. auto. Qed.
(** However, the [Hint Unfold] mechanism only works for unfolding
definitions that appear in the goal. In general, proof search does
not unfold definitions from the context. For example, assume we
want to prove that [P 3] holds under the assumption that [True ->
myFact]. *)
Lemma demo_hint_unfold_context_1 :
(True -> myFact) -> P 3.
Proof.
intros.
auto. (* fails *)
unfold myFact in *. auto. (* succeeds *)
Qed.
(** There is actually one exception to the previous rule: a constant
occuring in an hypothesis is automatically unfolded if the
hypothesis can be directly applied to the current goal. For example,
[auto] can prove [myFact -> P 3], as illustrated below. *)
Lemma demo_hint_unfold_context_2 :
myFact -> P 3.
Proof. auto. Qed.
(* ####################################################### *)
(** ** Automation for Proving Absurd Goals *)
(** In this section, we'll see that lemmas concluding on a negation
are generally not useful as hints, and that lemmas whose
conclusion is [False] can be useful hints but having too many of
them makes proof search inefficient. We'll also see a practical
work-around to the efficiency issue. *)
(** Consider the following lemma, which asserts that a number
less than or equal to 3 is not greater than 3. *)
Parameter le_not_gt : forall x,
(x <= 3) -> ~ (x > 3).
(** Equivalently, one could state that a number greater than three is
not less than or equal to 3. *)
Parameter gt_not_le : forall x,
(x > 3) -> ~ (x <= 3).
(** In fact, both statements are equivalent to a third one stating
that [x <= 3] and [x > 3] are contradictory, in the sense that
they imply [False]. *)
Parameter le_gt_false : forall x,
(x <= 3) -> (x > 3) -> False.
(** The following investigation aim at figuring out which of the three
statments is the most convenient with respect to proof
automation. The following material is enclosed inside a [Section],
so as to restrict the scope of the hints that we are adding. In
other words, after the end of the section, the hints added within
the section will no longer be active.*)
Section DemoAbsurd1.
(** Let's try to add the first lemma, [le_not_gt], as hint,
and see whether we can prove that the proposition
[exists x, x <= 3 /\ x > 3] is absurd. *)
Hint Resolve le_not_gt.
Lemma demo_auto_absurd_1 :
(exists x, x <= 3 /\ x > 3) -> False.
Proof.
intros. jauto_set. (* decomposes the assumption *)
(* debug *) eauto. (* does not see that [le_not_gt] could apply *)
eapply le_not_gt. eauto. eauto.
Qed.
(** The lemma [gt_not_le] is symmetric to [le_not_gt], so it will not
be any better. The third lemma, [le_gt_false], is a more useful
hint, because it concludes on [False], so proof search will try to
apply it when the current goal is [False]. *)
Hint Resolve le_gt_false.
Lemma demo_auto_absurd_2 :
(exists x, x <= 3 /\ x > 3) -> False.
Proof.
dup.
(* detailed version: *)
intros. jauto_set. (* debug *) eauto.
(* short version: *)
jauto.
Qed.
(** In summary, a lemma of the form [H1 -> H2 -> False] is a much more
effective hint than [H1 -> ~ H2], even though the two statments
are equivalent up to the definition of the negation symbol [~]. *)
(** That said, one should be careful with adding lemmas whose
conclusion is [False] as hint. The reason is that whenever
reaching the goal [False], the proof search mechanism will
potentially try to apply all the hints whose conclusion is [False]
before applying the appropriate one. *)
End DemoAbsurd1.
(** Adding lemmas whose conclusion is [False] as hint can be, locally,
a very effective solution. However, this approach does not scale
up for global hints. For most practical applications, it is
reasonable to give the name of the lemmas to be exploited for
deriving a contradiction. The tactic [false H], provided by
[LibTactics] serves that purpose: [false H] replaces the goal
with [False] and calls [eapply H]. Its behavior is described next.
Observe that any of the three statements [le_not_gt], [gt_not_le]
or [le_gt_false] can be used. *)
Lemma demo_false : forall x,
(x <= 3) -> (x > 3) -> 4 = 5.
Proof.
intros. dup 4.
(* A failed proof: *)
false. eapply le_gt_false.
auto. (* here, [auto] does not prove [?x <= 3] by using [H] but
by using the lemma [le_refl : forall x, x <= x]. *)
(* The second subgoal becomes [3 > 3], which is not provable. *)
skip.
(* A correct proof: *)
false. eapply le_gt_false.
eauto. (* here, [eauto] uses [H], as expected, to prove [?x <= 3] *)
eauto. (* so the second subgoal becomes [x > 3] *)
(* The same proof using [false]: *)
false le_gt_false. eauto. eauto.
(* The lemmas [le_not_gt] and [gt_not_le] work as well *)
false le_not_gt. eauto. eauto.
Qed.
(** In the above example, [false le_gt_false; eauto] proves the goal,
but [false le_gt_false; auto] does not, because [auto] does not
correctly instantiate the existential variable. Note that [false*
le_gt_false] would not work either, because the star symbol tries
to call [auto] first. So, there are two possibilities for
completing the proof: either call [false le_gt_false; eauto], or
call [false* (le_gt_false 3)]. *)
(* ####################################################### *)
(** ** Automation for Transitivity Lemmas *)
(** Some lemmas should never be added as hints, because they would
very badly slow down proof search. The typical example is that of
transitivity results. This section describes the problem and
presents a general workaround.
Consider a subtyping relation, written [subtype S T], that relates
two object [S] and [T] of type [typ]. Assume that this relation
has been proved reflexive and transitive. The corresponding lemmas
are named [subtype_refl] and [subtype_trans]. *)
Parameter typ : Type.
Parameter subtype : typ -> typ -> Prop.
Parameter subtype_refl : forall T,
subtype T T.
Parameter subtype_trans : forall S T U,
subtype S T -> subtype T U -> subtype S U.
(** Adding reflexivity as hint is generally a good idea,
so let's add reflexivity of subtyping as hint. *)
Hint Resolve subtype_refl.
(** Adding transitivity as hint is generally a bad idea. To
understand why, let's add it as hint and see what happens.
Because we cannot remove hints once we've added them, we are going
to open a "Section," so as to restrict the scope of the
transitivity hint to that section. *)
Section HintsTransitivity.
Hint Resolve subtype_trans.
(** Now, consider the goal [forall S T, subtype S T], which clearly has
no hope of being solved. Let's call [eauto] on this goal. *)
Lemma transitivity_bad_hint_1 : forall S T,
subtype S T.
Proof.
intros. (* debug *) eauto. (* Investigates 106 applications... *)
Abort.
(** Note that after closing the section, the hint [subtype_trans]
is no longer active. *)
End HintsTransitivity.
(** In the previous example, the proof search has spent a lot of time
trying to apply transitivity and reflexivity in every possible
way. Its process can be summarized as follows. The first goal is
[subtype S T]. Since reflexivity does not apply, [eauto] invokes
transitivity, which produces two subgoals, [subtype S ?X] and
[subtype ?X T]. Solving the first subgoal, [subtype S ?X], is
straightforward, it suffices to apply reflexivity. This unifies
[?X] with [S]. So, the second sugoal, [subtype ?X T],
becomes [subtype S T], which is exactly what we started from...
The problem with the transitivity lemma is that it is applicable
to any goal concluding on a subtyping relation. Because of this,
[eauto] keeps trying to apply it even though it most often doesn't
help to solve the goal. So, one should never add a transitivity
lemma as a hint for proof search. *)
(** There is a general workaround for having automation to exploit
transitivity lemmas without giving up on efficiency. This workaround
relies on a powerful mechanism called "external hint." This
mechanism allows to manually describe the condition under which
a particular lemma should be tried out during proof search.
For the case of transitivity of subtyping, we are going to tell
Coq to try and apply the transitivity lemma on a goal of the form
[subtype S U] only when the proof context already contains an
assumption either of the form [subtype S T] or of the form
[subtype T U]. In other words, we only apply the transitivity
lemma when there is some evidence that this application might
help. To set up this "external hint," one has to write the
following. *)
Hint Extern 1 (subtype ?S ?U) =>
match goal with
| H: subtype S ?T |- _ => apply (@subtype_trans S T U)
| H: subtype ?T U |- _ => apply (@subtype_trans S T U)
end.
(** This hint declaration can be understood as follows.
- "Hint Extern" introduces the hint.
- The number "1" corresponds to a priority for proof search.
It doesn't matter so much what priority is used in practice.
- The pattern [subtype ?S ?U] describes the kind of goal on
which the pattern should apply. The question marks are used
to indicate that the variables [?S] and [?U] should be bound
to some value in the rest of the hint description.
- The construction [match goal with ... end] tries to recognize
patterns in the goal, or in the proof context, or both.
- The first pattern is [H: subtype S ?T |- _]. It indices that
the context should contain an hypothesis [H] of type
[subtype S ?T], where [S] has to be the same as in the goal,
and where [?T] can have any value.
- The symbol [|- _] at the end of [H: subtype S ?T |- _] indicates
that we do not impose further condition on how the proof
obligation has to look like.
- The branch [=> apply (@subtype_trans S T U)] that follows
indicates that if the goal has the form [subtype S U] and if
there exists an hypothesis of the form [subtype S T], then
we should try and apply transitivity lemma instantiated on
the arguments [S], [T] and [U]. (Note: the symbol [@] in front of
[subtype_trans] is only actually needed when the "Implicit Arguments"
feature is activated.)
- The other branch, which corresponds to an hypothesis of the form
[H: subtype ?T U] is symmetrical.
Note: the same external hint can be reused for any other transitive
relation, simply by renaming [subtype] into the name of that relation. *)
(** Let us see an example illustrating how the hint works. *)
Lemma transitivity_workaround_1 : forall T1 T2 T3 T4,
subtype T1 T2 -> subtype T2 T3 -> subtype T3 T4 -> subtype T1 T4.
Proof.
intros. (* debug *) eauto. (* The trace shows the external hint being used *)
Qed.
(** We may also check that the new external hint does not suffer from the
complexity blow up. *)
Lemma transitivity_workaround_2 : forall S T,
subtype S T.
Proof.
intros. (* debug *) eauto. (* Investigates 0 applications *)
Abort.
(* ####################################################### *)
(** * Decision Procedures *)
(** A decision procedure is able to solve proof obligations whose
statement admits a particular form. This section describes three
useful decision procedures. The tactic [omega] handles goals
involving arithmetic and inequalities, but not general
multiplications. The tactic [ring] handles goals involving
arithmetic, including multiplications, but does not support
inequalities. The tactic [congruence] is able to prove equalities
and inequalities by exploiting equalities available in the proof
context. *)
(* ####################################################### *)
(** ** Omega *)
(** The tactic [omega] supports natural numbers (type [nat]) as well as
integers (type [Z], available by including the module [ZArith]).
It supports addition, substraction, equalities and inequalities.
Before using [omega], one needs to import the module [Omega],
as follows. *)
Require Import Omega.
(** Here is an example. Let [x] and [y] be two natural numbers
(they cannot be negative). Assume [y] is less than 4, assume
[x+x+1] is less than [y], and assume [x] is not zero. Then,
it must be the case that [x] is equal to one. *)
Lemma omega_demo_1 : forall (x y : nat),
(y <= 4) -> (x + x + 1 <= y) -> (x <> 0) -> (x = 1).
Proof. intros. omega. Qed.
(** Another example: if [z] is the mean of [x] and [y], and if the
difference between [x] and [y] is at most [4], then the difference
between [x] and [z] is at most 2. *)
Lemma omega_demo_2 : forall (x y z : nat),
(x + y = z + z) -> (x - y <= 4) -> (x - z <= 2).
Proof. intros. omega. Qed.
(** One can proof [False] using [omega] if the mathematical facts
from the context are contradictory. In the following example,
the constraints on the values [x] and [y] cannot be all
satisfied in the same time. *)
Lemma omega_demo_3 : forall (x y : nat),
(x + 5 <= y) -> (y - x < 3) -> False.
Proof. intros. omega. Qed.
(** Note: [omega] can prove a goal by contradiction only if its
conclusion is reduced [False]. The tactic [omega] always fails
when the conclusion is an arbitrary proposition [P], even though
[False] implies any proposition [P] (by [ex_falso_quodlibet]). *)
Lemma omega_demo_4 : forall (x y : nat) (P : Prop),
(x + 5 <= y) -> (y - x < 3) -> P.
Proof.
intros.
(* Calling [omega] at this point fails with the message:
"Omega: Can't solve a goal with proposition variables" *)
(* So, one needs to replace the goal by [False] first. *)
false. omega.
Qed.
(* ####################################################### *)
(** ** Ring *)
(** Compared with [omega], the tactic [ring] adds support for
multiplications, however it gives up the ability to reason on
inequations. Moreover, it supports only integers (type [Z]) and
not natural numbers (type [nat]). Here is an example showing how
to use [ring]. *)
Module RingDemo.
Require Import ZArith.
Open Scope Z_scope.
(* Arithmetic symbols are now interpreted in [Z] *)
Lemma ring_demo : forall (x y z : Z),
x * (y + z) - z * 3 * x
= x * y - 2 * x * z.
Proof. intros. ring. Qed.
End RingDemo.
(* ####################################################### *)
(** ** Congruence *)
(** The tactic [congruence] is able to exploit equalities from the
proof context in order to automatically perform the rewriting
operations necessary to establish a goal. It is slightly more
powerful than the tactic [subst], which can only handle equalities
of the form [x = e] where [x] is a variable and [e] an
expression. *)
Lemma congruence_demo_1 :
forall (f : nat->nat->nat) (g h : nat->nat) (x y z : nat),
f (g x) (g y) = z ->
2 = g x ->
g y = h z ->
f 2 (h z) = z.
Proof. intros. congruence. Qed.
(** Moreover, [congruence] is able to exploit universally quantified
equalities, for example [forall a, g a = h a]. *)
Lemma congruence_demo_2 :
forall (f : nat->nat->nat) (g h : nat->nat) (x y z : nat),
(forall a, g a = h a) ->
f (g x) (g y) = z ->
g x = 2 ->
f 2 (h y) = z.
Proof. congruence. Qed.
(** Next is an example where [congruence] is very useful. *)
Lemma congruence_demo_4 : forall (f g : nat->nat),
(forall a, f a = g a) ->
f (g (g 2)) = g (f (f 2)).
Proof. congruence. Qed.
(** The tactic [congruence] is able to prove a contradiction if the
goal entails an equality that contradicts an inequality available
in the proof context. *)
Lemma congruence_demo_3 :
forall (f g h : nat->nat) (x : nat),
(forall a, f a = h a) ->
g x = f x ->
g x <> h x ->
False.
Proof. congruence. Qed.
(** One of the strengths of [congruence] is that it is a very fast
tactic. So, one should not hesitate to invoke it wherever it might
help. *)
(* ####################################################### *)
(** * Summary *)
(** Let us summarize the main automation tactics available.
- [auto] automatically applies [reflexivity], [assumption], and [apply].
- [eauto] moreover tries [eapply], and in particular can instantiate
existentials in the conclusion.
- [iauto] extends [eauto] with support for negation, conjunctions, and
disjunctions. However, its support for disjunction can make it
exponentially slow.
- [jauto] extends [eauto] with support for negation, conjunctions, and
existential at the head of hypothesis.
- [congruence] helps reasoning about equalities and inequalities.
- [omega] proves arithmetic goals with equalities and inequalities,
but it does not support multiplication.
- [ring] proves arithmetic goals with multiplications, but does not
support inequalities.
In order to set up automation appropriately, keep in mind the following
rule of thumbs:
- automation is all about balance: not enough automation makes proofs
not very robust on change, whereas too much automation makes proofs
very hard to fix when they break.
- if a lemma is not goal directed (i.e., some of its variables do not
occur in its conclusion), then the premises need to be ordered in
such a way that proving the first premises maximizes the chances of
correctly instantiating the variables that do not occur in the conclusion.
- a lemma whose conclusion is [False] should only be added as a local
hint, i.e., as a hint within the current section.
- a transitivity lemma should never be considered as hint; if automation
of transitivity reasoning is really necessary, an [Extern Hint] needs
to be set up.
- a definition usually needs to be accompanied with a [Hint Unfold].
Becoming a master in the black art of automation certainly requires
some investment, however this investment will pay off very quickly.
*)
|
(** * UseAuto: Theory and Practice of Automation in Coq Proofs *)
(* $Date: 2013-07-17 16:19:11 -0400 (Wed, 17 Jul 2013) $ *)
(* Chapter maintained by Arthur Chargueraud *)
(** In a machine-checked proof, every single detail has to be
justified. This can result in huge proof scripts. Fortunately,
Coq comes with a proof-search mechanism and with several decision
procedures that enable the system to automatically synthesize
simple pieces of proof. Automation is very powerful when set up
appropriately. The purpose of this chapter is to explain the
basics of working of automation.
The chapter is organized in two parts. The first part focuses on a
general mechanism called "proof search." In short, proof search
consists in naively trying to apply lemmas and assumptions in all
possible ways. The second part describes "decision procedures",
which are tactics that are very good at solving proof obligations
that fall in some particular fragment of the logic of Coq.
Many of the examples used in this chapter consist of small lemmas
that have been made up to illustrate particular aspects of automation.
These examples are completely independent from the rest of the Software
Foundations course. This chapter also contains some bigger examples
which are used to explain how to use automation in realistic proofs.
These examples are taken from other chapters of the course (mostly
from STLC), and the proofs that we present make use of the tactics
from the library [LibTactics.v], which is presented in the chapter
[UseTactics]. *)
Require Import LibTactics.
(* ####################################################### *)
(** * Basic Features of Proof Search *)
(** The idea of proof search is to replace a sequence of tactics
applying lemmas and assumptions with a call to a single tactic,
for example [auto]. This form of proof automation saves a lot of
effort. It typically leads to much shorter proof scripts, and to
scripts that are typically more robust to change. If one makes a
little change to a definition, a proof that exploits automation
probably won't need to be modified at all. Of course, using too
much automation is a bad idea. When a proof script no longer
records the main arguments of a proof, it becomes difficult to fix
it when it gets broken after a change in a definition. Overall, a
reasonable use of automation is generally a big win, as it saves a
lot of time both in building proof scripts and in subsequently
maintaining those proof scripts. *)
(* ####################################################### *)
(** ** Strength of Proof Search *)
(** We are going to study four proof-search tactics: [auto], [eauto],
[iauto] and [jauto]. The tactics [auto] and [eauto] are builtin
in Coq. The tactic [iauto] is a shorthand for the builtin tactic
[try solve [intuition eauto]]. The tactic [jauto] is defined in
the library [LibTactics], and simply performs some preprocessing
of the goal before calling [eauto]. The goal of this chapter is
to explain the general principles of proof search and to give
rule of thumbs for guessing which of the four tactics mentioned
above is best suited for solving a given goal.
Proof search is a compromise between efficiency and
expressiveness, that is, a tradeoff between how complex goals the
tactic can solve and how much time the tactic requires for
terminating. The tactic [auto] builds proofs only by using the
basic tactics [reflexivity], [assumption], and [apply]. The tactic
[eauto] can also exploit [eapply]. The tactic [jauto] extends
[eauto] by being able to open conjunctions and existentials that
occur in the context. The tactic [iauto] is able to deal with
conjunctions, disjunctions, and negation in a quite clever way;
however it is not able to open existentials from the context.
Also, [iauto] usually becomes very slow when the goal involves
several disjunctions.
Note that proof search tactics never perform any rewriting
step (tactics [rewrite], [subst]), nor any case analysis on an
arbitrary data structure or predicate (tactics [destruct] and
[inversion]), nor any proof by induction (tactic [induction]). So,
proof search is really intended to automate the final steps from
the various branches of a proof. It is not able to discover the
overall structure of a proof. *)
(* ####################################################### *)
(** ** Basics *)
(** The tactic [auto] is able to solve a goal that can be proved
using a sequence of [intros], [apply], [assumption], and [reflexivity].
Two examples follow. The first one shows the ability for
[auto] to call [reflexivity] at any time. In fact, calling
[reflexivity] is always the first thing that [auto] tries to do. *)
Lemma solving_by_reflexivity :
2 + 3 = 5.
Proof. auto. Qed.
(** The second example illustrates a proof where a sequence of
two calls to [apply] are needed. The goal is to prove that
if [Q n] implies [P n] for any [n] and if [Q n] holds for any [n],
then [P 2] holds. *)
Lemma solving_by_apply : forall (P Q : nat->Prop),
(forall n, Q n -> P n) ->
(forall n, Q n) ->
P 2.
Proof. auto. Qed.
(** We can ask [auto] to tell us what proof it came up with,
by invoking [info_auto] in place of [auto]. *)
Lemma solving_by_apply' : forall (P Q : nat->Prop),
(forall n, Q n -> P n) ->
(forall n, Q n) ->
P 2.
Proof. info_auto. Qed.
(* The output is: [intro P; intro Q; intro H;] *)
(* followed with [intro H0; simple apply H; simple apply H0]. *)
(* i.e., the sequence [intros P Q H H0; apply H; apply H0]. *)
(** The tactic [auto] can invoke [apply] but not [eapply]. So, [auto]
cannot exploit lemmas whose instantiation cannot be directly
deduced from the proof goal. To exploit such lemmas, one needs to
invoke the tactic [eauto], which is able to call [eapply].
In the following example, the first hypothesis asserts that [P n]
is true when [Q m] is true for some [m], and the goal is to prove
that [Q 1] implies [P 2]. This implication follows direction from
the hypothesis by instantiating [m] as the value [1]. The
following proof script shows that [eauto] successfully solves the
goal, whereas [auto] is not able to do so. *)
Lemma solving_by_eapply : forall (P Q : nat->Prop),
(forall n m, Q m -> P n) ->
Q 1 -> P 2.
Proof. auto. eauto. Qed.
(** Remark: Again, we can use [info_eauto] to see what proof [eauto]
comes up with. *)
(* ####################################################### *)
(** ** Conjunctions *)
(** So far, we've seen that [eauto] is stronger than [auto] in the
sense that it can deal with [eapply]. In the same way, we are going
to see how [jauto] and [iauto] are stronger than [auto] and [eauto]
in the sense that they provide better support for conjunctions. *)
(** The tactics [auto] and [eauto] can prove a goal of the form
[F /\ F'], where [F] and [F'] are two propositions, as soon as
both [F] and [F'] can be proved in the current context.
An example follows. *)
Lemma solving_conj_goal : forall (P : nat->Prop) (F : Prop),
(forall n, P n) -> F -> F /\ P 2.
Proof. auto. Qed.
(** However, when an assumption is a conjunction, [auto] and [eauto]
are not able to exploit this conjunction. It can be quite
surprising at first that [eauto] can prove very complex goals but
that it fails to prove that [F /\ F'] implies [F]. The tactics
[iauto] and [jauto] are able to decompose conjunctions from the context.
Here is an example. *)
Lemma solving_conj_hyp : forall (F F' : Prop),
F /\ F' -> F.
Proof. auto. eauto. jauto. (* or [iauto] *) Qed.
(** The tactic [jauto] is implemented by first calling a
pre-processing tactic called [jauto_set], and then calling
[eauto]. So, to understand how [jauto] works, one can directly
call the tactic [jauto_set]. *)
Lemma solving_conj_hyp' : forall (F F' : Prop),
F /\ F' -> F.
Proof. intros. jauto_set. eauto. Qed.
(** Next is a more involved goal that can be solved by [iauto] and
[jauto]. *)
Lemma solving_conj_more : forall (P Q R : nat->Prop) (F : Prop),
(F /\ (forall n m, (Q m /\ R n) -> P n)) ->
(F -> R 2) ->
Q 1 ->
P 2 /\ F.
Proof. jauto. (* or [iauto] *) Qed.
(** The strategy of [iauto] and [jauto] is to run a global analysis of
the top-level conjunctions, and then call [eauto]. For this
reason, those tactics are not good at dealing with conjunctions
that occur as the conclusion of some universally quantified
hypothesis. The following example illustrates a general weakness
of Coq proof search mechanisms. *)
Lemma solving_conj_hyp_forall : forall (P Q : nat->Prop),
(forall n, P n /\ Q n) -> P 2.
Proof.
auto. eauto. iauto. jauto.
(* Nothing works, so we have to do some of the work by hand *)
intros. destruct (H 2). auto.
Qed.
(** This situation is slightly disappointing, since automation is
able to prove the following goal, which is very similar. The
only difference is that the universal quantification has been
distributed over the conjunction. *)
Lemma solved_by_jauto : forall (P Q : nat->Prop) (F : Prop),
(forall n, P n) /\ (forall n, Q n) -> P 2.
Proof. jauto. (* or [iauto] *) Qed.
(* ####################################################### *)
(** ** Disjunctions *)
(** The tactics [auto] and [eauto] can handle disjunctions that
occur in the goal. *)
Lemma solving_disj_goal : forall (F F' : Prop),
F -> F \/ F'.
Proof. auto. Qed.
(** However, only [iauto] is able to automate reasoning on the
disjunctions that appear in the context. For example, [iauto] can
prove that [F \/ F'] entails [F' \/ F]. *)
Lemma solving_disj_hyp : forall (F F' : Prop),
F \/ F' -> F' \/ F.
Proof. auto. eauto. jauto. iauto. Qed.
(** More generally, [iauto] can deal with complex combinations of
conjunctions, disjunctions, and negations. Here is an example. *)
Lemma solving_tauto : forall (F1 F2 F3 : Prop),
((~F1 /\ F3) \/ (F2 /\ ~F3)) ->
(F2 -> F1) ->
(F2 -> F3) ->
~F2.
Proof. iauto. Qed.
(** However, the ability of [iauto] to automatically perform a case
analysis on disjunctions comes with a downside: [iauto] may be
very slow. If the context involves several hypotheses with
disjunctions, [iauto] typically generates an exponential number of
subgoals on which [eauto] is called. One major advantage of [jauto]
compared with [iauto] is that it never spends time performing this
kind of case analyses. *)
(* ####################################################### *)
(** ** Existentials *)
(** The tactics [eauto], [iauto], and [jauto] can prove goals whose
conclusion is an existential. For example, if the goal is [exists
x, f x], the tactic [eauto] introduces an existential variable,
say [?25], in place of [x]. The remaining goal is [f ?25], and
[eauto] tries to solve this goal, allowing itself to instantiate
[?25] with any appropriate value. For example, if an assumption [f
2] is available, then the variable [?25] gets instantiated with
[2] and the goal is solved, as shown below. *)
Lemma solving_exists_goal : forall (f : nat->Prop),
f 2 -> exists x, f x.
Proof.
auto. (* observe that [auto] does not deal with existentials, *)
eauto. (* whereas [eauto], [iauto] and [jauto] solve the goal *)
Qed.
(** A major strength of [jauto] over the other proof search tactics is
that it is able to exploit the existentially-quantified
hypotheses, i.e., those of the form [exists x, P]. *)
Lemma solving_exists_hyp : forall (f g : nat->Prop),
(forall x, f x -> g x) ->
(exists a, f a) ->
(exists a, g a).
Proof.
auto. eauto. iauto. (* All of these tactics fail, *)
jauto. (* whereas [jauto] succeeds. *)
(* For the details, run [intros. jauto_set. eauto] *)
Qed.
(* ####################################################### *)
(** ** Negation *)
(** The tactics [auto] and [eauto] suffer from some limitations with
respect to the manipulation of negations, mostly related to the
fact that negation, written [~ P], is defined as [P -> False] but
that the unfolding of this definition is not performed
automatically. Consider the following example. *)
Lemma negation_study_1 : forall (P : nat->Prop),
P 0 -> (forall x, ~ P x) -> False.
Proof.
intros P H0 HX.
eauto. (* It fails to see that [HX] applies *)
unfold not in *. eauto.
Qed.
(** For this reason, the tactics [iauto] and [jauto] systematically
invoke [unfold not in *] as part of their pre-processing. So,
they are able to solve the previous goal right away. *)
Lemma negation_study_2 : forall (P : nat->Prop),
P 0 -> (forall x, ~ P x) -> False.
Proof. jauto. (* or [iauto] *) Qed.
(** We will come back later on to the behavior of proof search with
respect to the unfolding of definitions. *)
(* ####################################################### *)
(** ** Equalities *)
(** Coq's proof-search feature is not good at exploiting equalities.
It can do very basic operations, like exploiting reflexivity
and symmetry, but that's about it. Here is a simple example
that [auto] can solve, by first calling [symmetry] and then
applying the hypothesis. *)
Lemma equality_by_auto : forall (f g : nat->Prop),
(forall x, f x = g x) -> g 2 = f 2.
Proof. auto. Qed.
(** To automate more advanced reasoning on equalities, one should
rather try to use the tactic [congruence], which is presented at
the end of this chapter in the "Decision Procedures" section. *)
(* ####################################################### *)
(** * How Proof Search Works *)
(* ####################################################### *)
(** ** Search Depth *)
(** The tactic [auto] works as follows. It first tries to call
[reflexivity] and [assumption]. If one of these calls solves the
goal, the job is done. Otherwise [auto] tries to apply the most
recently introduced assumption that can be applied to the goal
without producing and error. This application produces
subgoals. There are two possible cases. If the sugboals produced
can be solved by a recursive call to [auto], then the job is done.
Otherwise, if this application produces at least one subgoal that
[auto] cannot solve, then [auto] starts over by trying to apply
the second most recently introduced assumption. It continues in a
similar fashion until it finds a proof or until no assumption
remains to be tried.
It is very important to have a clear idea of the backtracking
process involved in the execution of the [auto] tactic; otherwise
its behavior can be quite puzzling. For example, [auto] is not
able to solve the following triviality. *)
Lemma search_depth_0 :
True /\ True /\ True /\ True /\ True /\ True.
Proof.
auto.
Abort.
(** The reason [auto] fails to solve the goal is because there are
too many conjunctions. If there had been only five of them, [auto]
would have successfully solved the proof, but six is too many.
The tactic [auto] limits the number of lemmas and hypotheses
that can be applied in a proof, so as to ensure that the proof
search eventually terminates. By default, the maximal number
of steps is five. One can specify a different bound, writing
for example [auto 6] to search for a proof involving at most
six steps. For example, [auto 6] would solve the previous lemma.
(Similarly, one can invoke [eauto 6] or [intuition eauto 6].)
The argument [n] of [auto n] is called the "search depth."
The tactic [auto] is simply defined as a shorthand for [auto 5].
The behavior of [auto n] can be summarized as follows. It first
tries to solve the goal using [reflexivity] and [assumption]. If
this fails, it tries to apply a hypothesis (or a lemma that has
been registered in the hint database), and this application
produces a number of sugoals. The tactic [auto (n-1)] is then
called on each of those subgoals. If all the subgoals are solved,
the job is completed, otherwise [auto n] tries to apply a
different hypothesis.
During the process, [auto n] calls [auto (n-1)], which in turn
might call [auto (n-2)], and so on. The tactic [auto 0] only
tries [reflexivity] and [assumption], and does not try to apply
any lemma. Overall, this means that when the maximal number of
steps allowed has been exceeded, the [auto] tactic stops searching
and backtracks to try and investigate other paths. *)
(** The following lemma admits a unique proof that involves exactly
three steps. So, [auto n] proves this goal iff [n] is greater than
three. *)
Lemma search_depth_1 : forall (P : nat->Prop),
P 0 ->
(P 0 -> P 1) ->
(P 1 -> P 2) ->
(P 2).
Proof.
auto 0. (* does not find the proof *)
auto 1. (* does not find the proof *)
auto 2. (* does not find the proof *)
auto 3. (* finds the proof *)
(* more generally, [auto n] solves the goal if [n >= 3] *)
Qed.
(** We can generalize the example by introducing an assumption
asserting that [P k] is derivable from [P (k-1)] for all [k],
and keep the assumption [P 0]. The tactic [auto], which is the
same as [auto 5], is able to derive [P k] for all values of [k]
less than 5. For example, it can prove [P 4]. *)
Lemma search_depth_3 : forall (P : nat->Prop),
(* Hypothesis H1: *) (P 0) ->
(* Hypothesis H2: *) (forall k, P (k-1) -> P k) ->
(* Goal: *) (P 4).
Proof. auto. Qed.
(** However, to prove [P 5], one needs to call at least [auto 6]. *)
Lemma search_depth_4 : forall (P : nat->Prop),
(* Hypothesis H1: *) (P 0) ->
(* Hypothesis H2: *) (forall k, P (k-1) -> P k) ->
(* Goal: *) (P 5).
Proof. auto. auto 6. Qed.
(** Because [auto] looks for proofs at a limited depth, there are
cases where [auto] can prove a goal [F] and can prove a goal
[F'] but cannot prove [F /\ F']. In the following example,
[auto] can prove [P 4] but it is not able to prove [P 4 /\ P 4],
because the splitting of the conjunction consumes one proof step.
To prove the conjunction, one needs to increase the search depth,
using at least [auto 6]. *)
Lemma search_depth_5 : forall (P : nat->Prop),
(* Hypothesis H1: *) (P 0) ->
(* Hypothesis H2: *) (forall k, P (k-1) -> P k) ->
(* Goal: *) (P 4 /\ P 4).
Proof. auto. auto 6. Qed.
(* ####################################################### *)
(** ** Backtracking *)
(** In the previous section, we have considered proofs where
at each step there was a unique assumption that [auto]
could apply. In general, [auto] can have several choices
at every step. The strategy of [auto] consists of trying all
of the possibilities (using a depth-first search exploration).
To illustrate how automation works, we are going to extend the
previous example with an additional assumption asserting that
[P k] is also derivable from [P (k+1)]. Adding this hypothesis
offers a new possibility that [auto] could consider at every step.
There exists a special command that one can use for tracing
all the steps that proof-search considers. To view such a
trace, one should write [debug eauto]. (For some reason, the
command [debug auto] does not exist, so we have to use the
command [debug eauto] instead.) *)
Lemma working_of_auto_1 : forall (P : nat->Prop),
(* Hypothesis H1: *) (P 0) ->
(* Hypothesis H2: *) (forall k, P (k+1) -> P k) ->
(* Hypothesis H3: *) (forall k, P (k-1) -> P k) ->
(* Goal: *) (P 2).
(* Uncomment "debug" in the following line to see the debug trace: *)
Proof. intros P H1 H2 H3. (* debug *) eauto. Qed.
(** The output message produced by [debug eauto] is as follows.
<<
depth=5
depth=4 apply H3
depth=3 apply H3
depth=3 exact H1
>>
The depth indicates the value of [n] with which [eauto n] is
called. The tactics shown in the message indicate that the first
thing that [eauto] has tried to do is to apply [H3]. The effect of
applying [H3] is to replace the goal [P 2] with the goal [P 1].
Then, again, [H3] has been applied, changing the goal [P 1] into
[P 0]. At that point, the goal was exactly the hypothesis [H1].
It seems that [eauto] was quite lucky there, as it never even
tried to use the hypothesis [H2] at any time. The reason is that
[auto] always tries to use the most recently introduced hypothesis
first, and [H3] is a more recent hypothesis than [H2] in the goal.
So, let's permute the hypotheses [H2] and [H3] and see what
happens. *)
Lemma working_of_auto_2 : forall (P : nat->Prop),
(* Hypothesis H1: *) (P 0) ->
(* Hypothesis H3: *) (forall k, P (k-1) -> P k) ->
(* Hypothesis H2: *) (forall k, P (k+1) -> P k) ->
(* Goal: *) (P 2).
Proof. intros P H1 H3 H2. (* debug *) eauto. Qed.
(** This time, the output message suggests that the proof search
investigates many possibilities. Replacing [debug eauto] with
[info_eauto], we observe that the proof that [eauto] comes up
with is actually not the simplest one.
[apply H2; apply H3; apply H3; apply H3; exact H1]
This proof goes through the proof obligation [P 3], even though
it is not any useful. The following tree drawing describes
all the goals that automation has been through.
<<
|5||4||3||2||1||0| -- below, tabulation indicates the depth
[P 2]
-> [P 3]
-> [P 4]
-> [P 5]
-> [P 6]
-> [P 7]
-> [P 5]
-> [P 4]
-> [P 5]
-> [P 3]
--> [P 3]
-> [P 4]
-> [P 5]
-> [P 3]
-> [P 2]
-> [P 3]
-> [P 1]
-> [P 2]
-> [P 3]
-> [P 4]
-> [P 5]
-> [P 3]
-> [P 2]
-> [P 3]
-> [P 1]
-> [P 1]
-> [P 2]
-> [P 3]
-> [P 1]
-> [P 0]
-> !! Done !!
>>
The first few lines read as follows. To prove [P 2], [eauto 5]
has first tried to apply [H2], producing the subgoal [P 3].
To solve it, [eauto 4] has tried again to apply [H2], producing
the goal [P 4]. Similarly, the search goes through [P 5], [P 6]
and [P 7]. When reaching [P 7], the tactic [eauto 0] is called
but as it is not allowed to try and apply any lemma, it fails.
So, we come back to the goal [P 6], and try this time to apply
hypothesis [H3], producing the subgoal [P 5]. Here again,
[eauto 0] fails to solve this goal.
The process goes on and on, until backtracking to [P 3] and trying
to apply [H2] three times in a row, going through [P 2] and [P 1]
and [P 0]. This search tree explains why [eauto] came up with a
proof starting with [apply H2]. *)
(* ####################################################### *)
(** ** Adding Hints *)
(** By default, [auto] (and [eauto]) only tries to apply the
hypotheses that appear in the proof context. There are two
possibilities for telling [auto] to exploit a lemma that have
been proved previously: either adding the lemma as an assumption
just before calling [auto], or adding the lemma as a hint, so
that it can be used by every calls to [auto].
The first possibility is useful to have [auto] exploit a lemma
that only serves at this particular point. To add the lemma as
hypothesis, one can type [generalize mylemma; intros], or simply
[lets: mylemma] (the latter requires [LibTactics.v]).
The second possibility is useful for lemmas that need to be
exploited several times. The syntax for adding a lemma as a hint
is [Hint Resolve mylemma]. For example, the lemma asserting than
any number is less than or equal to itself, [forall x, x <= x],
called [Le.le_refl] in the Coq standard library, can be added as a
hint as follows. *)
Hint Resolve Le.le_refl.
(** A convenient shorthand for adding all the constructors of an
inductive datatype as hints is the command [Hint Constructors
mydatatype].
Warning: some lemmas, such as transitivity results, should
not be added as hints as they would very badly affect the
performance of proof search. The description of this problem
and the presentation of a general work-around for transitivity
lemmas appear further on. *)
(* ####################################################### *)
(** ** Integration of Automation in Tactics *)
(** The library "LibTactics" introduces a convenient feature for
invoking automation after calling a tactic. In short, it suffices
to add the symbol star ([*]) to the name of a tactic. For example,
[apply* H] is equivalent to [apply H; auto_star], where [auto_star]
is a tactic that can be defined as needed. By default, [auto_star]
first tries to solve the goal using [auto], and if this does not
succeed then it tries to call [jauto]. Even though [jauto] is
strictly stronger than [auto], it makes sense to call [auto] first:
when [auto] succeeds it may save a lot of time, and when [auto]
fails to prove the goal, it fails very quickly.
The definition of [auto_star], which determines the meaning of the
star symbol, can be modified whenever needed. Simply write:
Ltac auto_star ::= a_new_definition.
]]
Observe the use of [::=] instead of [:=], which indicates that the
tactic is being rebound to a new definition. So, the default
definition is as follows. *)
Ltac auto_star ::= try solve [ auto | jauto ].
(** Nearly all standard Coq tactics and all the tactics from
"LibTactics" can be called with a star symbol. For example, one
can invoke [subst*], [destruct* H], [inverts* H], [lets* I: H x],
[specializes* H x], and so on... There are two notable exceptions.
The tactic [auto*] is just another name for the tactic
[auto_star]. And the tactic [apply* H] calls [eapply H] (or the
more powerful [applys H] if needed), and then calls [auto_star].
Note that there is no [eapply* H] tactic, use [apply* H]
instead. *)
(** In large developments, it can be convenient to use two degrees of
automation. Typically, one would use a fast tactic, like [auto],
and a slower but more powerful tactic, like [jauto]. To allow for
a smooth coexistence of the two form of automation, [LibTactics.v]
also defines a "tilde" version of tactics, like [apply~ H],
[destruct~ H], [subst~], [auto~] and so on. The meaning of the
tilde symbol is described by the [auto_tilde] tactic, whose
default implementation is [auto]. *)
Ltac auto_tilde ::= auto.
(** In the examples that follow, only [auto_star] is needed. *)
(* ####################################################### *)
(** * Examples of Use of Automation *)
(** Let's see how to use proof search in practice on the main theorems
of the "Software Foundations" course, proving in particular
results such as determinism, preservation and progress. *)
(* ####################################################### *)
(** ** Determinism *)
Module DeterministicImp.
Require Import Imp.
(** Recall the original proof of the determinism lemma for the IMP
language, shown below. *)
Theorem ceval_deterministic: forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2.
generalize dependent st2.
(ceval_cases (induction E1) Case); intros st2 E2; inversion E2; subst.
Case "E_Skip". reflexivity.
Case "E_Ass". reflexivity.
Case "E_Seq".
assert (st' = st'0) as EQ1.
SCase "Proof of assertion". apply IHE1_1; assumption.
subst st'0.
apply IHE1_2. assumption.
Case "E_IfTrue".
SCase "b1 evaluates to true".
apply IHE1. assumption.
SCase "b1 evaluates to false (contradiction)".
rewrite H in H5. inversion H5.
Case "E_IfFalse".
SCase "b1 evaluates to true (contradiction)".
rewrite H in H5. inversion H5.
SCase "b1 evaluates to false".
apply IHE1. assumption.
Case "E_WhileEnd".
SCase "b1 evaluates to true".
reflexivity.
SCase "b1 evaluates to false (contradiction)".
rewrite H in H2. inversion H2.
Case "E_WhileLoop".
SCase "b1 evaluates to true (contradiction)".
rewrite H in H4. inversion H4.
SCase "b1 evaluates to false".
assert (st' = st'0) as EQ1.
SSCase "Proof of assertion". apply IHE1_1; assumption.
subst st'0.
apply IHE1_2. assumption.
Qed.
(** Exercise: rewrite this proof using [auto] whenever possible.
(The solution uses [auto] 9 times.) *)
Theorem ceval_deterministic': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
(* FILL IN HERE *) admit.
Qed.
(** In fact, using automation is not just a matter of calling [auto]
in place of one or two other tactics. Using automation is about
rethinking the organization of sequences of tactics so as to
minimize the effort involved in writing and maintaining the proof.
This process is eased by the use of the tactics from
[LibTactics.v]. So, before trying to optimize the way automation
is used, let's first rewrite the proof of determinism:
- use [introv H] instead of [intros x H],
- use [gen x] instead of [generalize dependent x],
- use [inverts H] instead of [inversion H; subst],
- use [tryfalse] to handle contradictions, and get rid of
the cases where [beval st b1 = true] and [beval st b1 = false]
both appear in the context,
- stop using [ceval_cases] to label subcases. *)
Theorem ceval_deterministic'': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
introv E1 E2. gen st2.
induction E1; intros; inverts E2; tryfalse.
auto.
auto.
assert (st' = st'0). auto. subst. auto.
auto.
auto.
auto.
assert (st' = st'0). auto. subst. auto.
Qed.
(** To obtain a nice clean proof script, we have to remove the calls
[assert (st' = st'0)]. Such a tactic invokation is not nice
because it refers to some variables whose name has been
automatically generated. This kind of tactics tend to be very
brittle. The tactic [assert (st' = st'0)] is used to assert the
conclusion that we want to derive from the induction
hypothesis. So, rather than stating this conclusion explicitly, we
are going to ask Coq to instantiate the induction hypothesis,
using automation to figure out how to instantiate it. The tactic
[forwards], described in [LibTactics.v] precisely helps with
instantiating a fact. So, let's see how it works out on our
example. *)
Theorem ceval_deterministic''': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
(* Let's replay the proof up to the [assert] tactic. *)
introv E1 E2. gen st2.
induction E1; intros; inverts E2; tryfalse.
auto. auto.
(* We duplicate the goal for comparing different proofs. *)
dup 4.
(* The old proof: *)
assert (st' = st'0). apply IHE1_1. apply H1.
(* produces [H: st' = st'0]. *) skip.
(* The new proof, without automation: *)
forwards: IHE1_1. apply H1.
(* produces [H: st' = st'0]. *) skip.
(* The new proof, with automation: *)
forwards: IHE1_1. eauto.
(* produces [H: st' = st'0]. *) skip.
(* The new proof, with integrated automation: *)
forwards*: IHE1_1.
(* produces [H: st' = st'0]. *) skip.
Abort.
(** To polish the proof script, it remains to factorize the calls
to [auto], using the star symbol. The proof of determinism can then
be rewritten in only four lines, including no more than 10 tactics. *)
Theorem ceval_deterministic'''': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
introv E1 E2. gen st2.
induction E1; intros; inverts* E2; tryfalse.
forwards*: IHE1_1. subst*.
forwards*: IHE1_1. subst*.
Qed.
End DeterministicImp.
(* ####################################################### *)
(** ** Preservation for STLC *)
Module PreservationProgressStlc.
Require Import StlcProp.
Import STLC.
Import STLCProp.
(** Consider the proof of perservation of STLC, shown below.
This proof already uses [eauto] through the triple-dot
mechanism. *)
Theorem preservation : forall t t' T,
has_type empty t T ->
t ==> t' ->
has_type empty t' T.
Proof with eauto.
remember (@empty ty) as Gamma.
intros t t' T HT. generalize dependent t'.
(has_type_cases (induction HT) Case); intros t' HE; subst Gamma.
Case "T_Var".
inversion HE.
Case "T_Abs".
inversion HE.
Case "T_App".
inversion HE; subst...
(* (step_cases (inversion HE) SCase); subst...*)
(* The ST_App1 and ST_App2 cases are immediate by induction, and
auto takes care of them *)
SCase "ST_AppAbs".
apply substitution_preserves_typing with T11...
inversion HT1...
Case "T_True".
inversion HE.
Case "T_False".
inversion HE.
Case "T_If".
inversion HE; subst...
Qed.
(** Exercise: rewrite this proof using tactics from [LibTactics]
and calling automation using the star symbol rather than the
triple-dot notation. More precisely, make use of the tactics
[inverts*] and [applys*] to call [auto*] after a call to
[inverts] or to [applys]. The solution is three lines long.*)
Theorem preservation' : forall t t' T,
has_type empty t T ->
t ==> t' ->
has_type empty t' T.
Proof.
(* FILL IN HERE *) admit.
Qed.
(* ####################################################### *)
(** ** Progress for STLC *)
(** Consider the proof of the progress theorem. *)
Theorem progress : forall t T,
has_type empty t T ->
value t \/ exists t', t ==> t'.
Proof with eauto.
intros t T Ht.
remember (@empty ty) as Gamma.
(has_type_cases (induction Ht) Case); subst Gamma...
Case "T_Var".
inversion H.
Case "T_App".
right. destruct IHHt1...
SCase "t1 is a value".
destruct IHHt2...
SSCase "t2 is a value".
inversion H; subst; try solve by inversion.
exists ([x0:=t2]t)...
SSCase "t2 steps".
destruct H0 as [t2' Hstp]. exists (tapp t1 t2')...
SCase "t1 steps".
destruct H as [t1' Hstp]. exists (tapp t1' t2)...
Case "T_If".
right. destruct IHHt1...
destruct t1; try solve by inversion...
inversion H. exists (tif x0 t2 t3)...
Qed.
(** Exercise: optimize the above proof.
Hint: make use of [destruct*] and [inverts*].
The solution consists of 10 short lines. *)
Theorem progress' : forall t T,
has_type empty t T ->
value t \/ exists t', t ==> t'.
Proof.
(* FILL IN HERE *) admit.
Qed.
End PreservationProgressStlc.
(* ####################################################### *)
(** ** BigStep and SmallStep *)
Module Semantics.
Require Import Smallstep.
(** Consider the proof relating a small-step reduction judgment
to a big-step reduction judgment. *)
Theorem multistep__eval : forall t v,
normal_form_of t v -> exists n, v = C n /\ t || n.
Proof.
intros t v Hnorm.
unfold normal_form_of in Hnorm.
inversion Hnorm as [Hs Hnf]; clear Hnorm.
rewrite nf_same_as_value in Hnf. inversion Hnf. clear Hnf.
exists n. split. reflexivity.
multi_cases (induction Hs) Case; subst.
Case "multi_refl".
apply E_Const.
Case "multi_step".
eapply step__eval. eassumption. apply IHHs. reflexivity.
Qed.
(** Our goal is to optimize the above proof. It is generally
easier to isolate inductions into separate lemmas. So,
we are going to first prove an intermediate result
that consists of the judgment over which the induction
is being performed. *)
(** Exercise: prove the following result, using tactics
[introv], [induction] and [subst], and [apply*].
The solution is 3 lines long. *)
Theorem multistep_eval_ind : forall t v,
t ==>* v -> forall n, C n = v -> t || n.
Proof.
(* FILL IN HERE *) admit.
Qed.
(** Exercise: using the lemma above, simplify the proof of
the result [multistep__eval]. You should use the tactics
[introv], [inverts], [split*] and [apply*].
The solution is 2 lines long. *)
Theorem multistep__eval' : forall t v,
normal_form_of t v -> exists n, v = C n /\ t || n.
Proof.
(* FILL IN HERE *) admit.
Qed.
(** If we try to combine the two proofs into a single one,
we will likely fail, because of a limitation of the
[induction] tactic. Indeed, this tactic looses
information when applied to a predicate whose arguments
are not reduced to variables, such as [t ==>* (C n)].
You will thus need to use the more powerful tactic called
[dependent induction]. This tactic is available only after
importing the [Program] library, as shown below. *)
Require Import Program.
(** Exercise: prove the lemma [multistep__eval] without invoking
the lemma [multistep_eval_ind], that is, by inlining the proof
by induction involved in [multistep_eval_ind], using the
tactic [dependent induction] instead of [induction].
The solution is 5 lines long. *)
Theorem multistep__eval'' : forall t v,
normal_form_of t v -> exists n, v = C n /\ t || n.
Proof.
(* FILL IN HERE *) admit.
Qed.
End Semantics.
(* ####################################################### *)
(** ** Preservation for STLCRef *)
Module PreservationProgressReferences.
Require Import References.
Import STLCRef.
Hint Resolve store_weakening extends_refl.
(** The proof of preservation for [STLCRef] can be found in chapter
[References]. It contains 58 lines (not counting the labelling of
cases). The optimized proof script is more than twice shorter. The
following material explains how to build the optimized proof
script. The resulting optimized proof script for the preservation
theorem appears afterwards. *)
Theorem preservation : forall ST t t' T st st',
has_type empty ST t T ->
store_well_typed ST st ->
t / st ==> t' / st' ->
exists ST',
(extends ST' ST /\
has_type empty ST' t' T /\
store_well_typed ST' st').
Proof.
(* old: [Proof. with eauto using store_weakening, extends_refl.]
new: [Proof.], and the two lemmas are registered as hints
before the proof of the lemma, possibly inside a section in
order to restrict the scope of the hints. *)
remember (@empty ty) as Gamma. introv Ht. gen t'.
(has_type_cases (induction Ht) Case); introv HST Hstep;
(* old: [subst; try (solve by inversion); inversion Hstep; subst;
try (eauto using store_weakening, extends_refl)]
new: [subst Gamma; inverts Hstep; eauto.]
We want to be more precise on what exactly we substitute,
and we do not want to call [try (solve by inversion)] which
is way to slow. *)
subst Gamma; inverts Hstep; eauto.
Case "T_App".
SCase "ST_AppAbs".
(* old:
exists ST. inversion Ht1; subst.
split; try split... eapply substitution_preserves_typing... *)
(* new: we use [inverts] in place of [inversion] and [splits] to
split the conjunction, and [applys*] in place of [eapply...] *)
exists ST. inverts Ht1. splits*. applys* substitution_preserves_typing.
SCase "ST_App1".
(* old:
eapply IHHt1 in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'... *)
(* new: The tactic [eapply IHHt1 in H0...] applies [IHHt1] to [H0].
But [H0] is only thing that [IHHt1] could be applied to, so
there [eauto] can figure this out on its own. The tactic
[forwards] is used to instantiate all the arguments of [IHHt1],
producing existential variables and subgoals when needed. *)
forwards: IHHt1. eauto. eauto. eauto.
(* At this point, we need to decompose the hypothesis [H] that has
just been created by [forwards]. This is done by the first part
of the preprocessing phase of [jauto]. *)
jauto_set_hyps; intros.
(* It remains to decompose the goal, which is done by the second
part of the preprocessing phase of [jauto]. *)
jauto_set_goal; intros.
(* All the subgoals produced can then be solved by [eauto]. *)
eauto. eauto. eauto.
SCase "ST_App2".
(* old:
eapply IHHt2 in H5...
inversion H5 as [ST' [Hext [Hty Hsty]]].
exists ST'... *)
(* new: this time, we need to call [forwards] on [IHHt2],
and we call [jauto] right away, by writing [forwards*],
proving the goal in a single tactic! *)
forwards*: IHHt2.
(* The same trick works for many of the other subgoals. *)
forwards*: IHHt.
forwards*: IHHt.
forwards*: IHHt1.
forwards*: IHHt2.
forwards*: IHHt1.
Case "T_Ref".
SCase "ST_RefValue".
(* old:
exists (snoc ST T1).
inversion HST; subst.
split.
apply extends_snoc.
split.
replace (TRef T1)
with (TRef (store_Tlookup (length st) (snoc ST T1))).
apply T_Loc.
rewrite <- H. rewrite length_snoc. omega.
unfold store_Tlookup. rewrite <- H. rewrite nth_eq_snoc...
apply store_well_typed_snoc; assumption. *)
(* new: in this proof case, we need to perform an inversion
without removing the hypothesis. The tactic [inverts keep]
serves exactly this purpose. *)
exists (snoc ST T1). inverts keep HST. splits.
(* The proof of the first subgoal needs not be changed *)
apply extends_snoc.
(* For the second subgoal, we use the tactic [applys_eq] to avoid
a manual [replace] before [T_loc] can be applied. *)
applys_eq T_Loc 1.
(* To justify the inequality, there is no need to call [rewrite <- H],
because the tactic [omega] is able to exploit [H] on its own.
So, only the rewriting of [lenght_snoc] and the call to the
tactic [omega] remain. *)
rewrite length_snoc. omega.
(* The next proof case is hard to polish because it relies on the
lemma [nth_eq_snoc] whose statement is not automation-friendly.
We'll come back to this proof case further on. *)
unfold store_Tlookup. rewrite <- H. rewrite* nth_eq_snoc.
(* Last, we replace [apply ..; assumption] with [apply* ..] *)
apply* store_well_typed_snoc.
forwards*: IHHt.
Case "T_Deref".
SCase "ST_DerefLoc".
(* old:
exists ST. split; try split...
destruct HST as [_ Hsty].
replace T11 with (store_Tlookup l ST).
apply Hsty...
inversion Ht; subst... *)
(* new: we start by calling [exists ST] and [splits*]. *)
exists ST. splits*.
(* new: we replace [destruct HST as [_ Hsty]] by the following *)
lets [_ Hsty]: HST.
(* new: then we use the tactic [applys_eq] to avoid the need to
perform a manual [replace] before applying [Hsty]. *)
applys_eq* Hsty 1.
(* new: we then can call [inverts] in place of [inversion;subst] *)
inverts* Ht.
forwards*: IHHt.
Case "T_Assign".
SCase "ST_Assign".
(* old:
exists ST. split; try split...
eapply assign_pres_store_typing...
inversion Ht1; subst... *)
(* new: simply using nicer tactics *)
exists ST. splits*. applys* assign_pres_store_typing. inverts* Ht1.
forwards*: IHHt1.
forwards*: IHHt2.
Qed.
(** Let's come back to the proof case that was hard to optimize.
The difficulty comes from the statement of [nth_eq_snoc], which
takes the form [nth (length l) (snoc l x) d = x]. This lemma is
hard to exploit because its first argument, [length l], mentions
a list [l] that has to be exactly the same as the [l] occuring in
[snoc l x]. In practice, the first argument is often a natural
number [n] that is provably equal to [length l] yet that is not
syntactically equal to [length l]. There is a simple fix for
making [nth_eq_snoc] easy to apply: introduce the intermediate
variable [n] explicitly, so that the goal becomes
[nth n (snoc l x) d = x], with a premise asserting [n = length l]. *)
Lemma nth_eq_snoc' : forall (A : Type) (l : list A) (x d : A) (n : nat),
n = length l -> nth n (snoc l x) d = x.
Proof. intros. subst. apply nth_eq_snoc. Qed.
(** The proof case for [ref] from the preservation theorem then
becomes much easier to prove, because [rewrite nth_eq_snoc']
now succeeds. *)
Lemma preservation_ref : forall (st:store) (ST : store_ty) T1,
length ST = length st ->
TRef T1 = TRef (store_Tlookup (length st) (snoc ST T1)).
Proof.
intros. dup.
(* A first proof, with an explicit [unfold] *)
unfold store_Tlookup. rewrite* nth_eq_snoc'.
(* A second proof, with a call to [fequal] *)
fequal. symmetry. apply* nth_eq_snoc'.
Qed.
(** The optimized proof of preservation is summarized next. *)
Theorem preservation' : forall ST t t' T st st',
has_type empty ST t T ->
store_well_typed ST st ->
t / st ==> t' / st' ->
exists ST',
(extends ST' ST /\
has_type empty ST' t' T /\
store_well_typed ST' st').
Proof.
remember (@empty ty) as Gamma. introv Ht. gen t'.
induction Ht; introv HST Hstep; subst Gamma; inverts Hstep; eauto.
exists ST. inverts Ht1. splits*. applys* substitution_preserves_typing.
forwards*: IHHt1.
forwards*: IHHt2.
forwards*: IHHt.
forwards*: IHHt.
forwards*: IHHt1.
forwards*: IHHt2.
forwards*: IHHt1.
exists (snoc ST T1). inverts keep HST. splits.
apply extends_snoc.
applys_eq T_Loc 1.
rewrite length_snoc. omega.
unfold store_Tlookup. rewrite* nth_eq_snoc'.
apply* store_well_typed_snoc.
forwards*: IHHt.
exists ST. splits*. lets [_ Hsty]: HST.
applys_eq* Hsty 1. inverts* Ht.
forwards*: IHHt.
exists ST. splits*. applys* assign_pres_store_typing. inverts* Ht1.
forwards*: IHHt1.
forwards*: IHHt2.
Qed.
(* ####################################################### *)
(** ** Progress for STLCRef *)
(** The proof of progress for [STLCRef] can be found in chapter
[References]. It contains 53 lines and the optimized proof script
is, here again, half the length. *)
Theorem progress : forall ST t T st,
has_type empty ST t T ->
store_well_typed ST st ->
(value t \/ exists t', exists st', t / st ==> t' / st').
Proof.
introv Ht HST. remember (@empty ty) as Gamma.
induction Ht; subst Gamma; tryfalse; try solve [left*].
right. destruct* IHHt1 as [K|].
inverts K; inverts Ht1.
destruct* IHHt2.
right. destruct* IHHt as [K|].
inverts K; try solve [inverts Ht]. eauto.
right. destruct* IHHt as [K|].
inverts K; try solve [inverts Ht]. eauto.
right. destruct* IHHt1 as [K|].
inverts K; try solve [inverts Ht1].
destruct* IHHt2 as [M|].
inverts M; try solve [inverts Ht2]. eauto.
right. destruct* IHHt1 as [K|].
inverts K; try solve [inverts Ht1]. destruct* n.
right. destruct* IHHt.
right. destruct* IHHt as [K|].
inverts K; inverts Ht as M.
inverts HST as N. rewrite* N in M.
right. destruct* IHHt1 as [K|].
destruct* IHHt2.
inverts K; inverts Ht1 as M.
inverts HST as N. rewrite* N in M.
Qed.
End PreservationProgressReferences.
(* ####################################################### *)
(** ** Subtyping *)
Module SubtypingInversion.
Require Import Sub.
(** Consider the inversion lemma for typing judgment
of abstractions in a type system with subtyping. *)
Lemma abs_arrow : forall x S1 s2 T1 T2,
has_type empty (tabs x S1 s2) (TArrow T1 T2) ->
subtype T1 S1
/\ has_type (extend empty x S1) s2 T2.
Proof with eauto.
intros x S1 s2 T1 T2 Hty.
apply typing_inversion_abs in Hty.
destruct Hty as [S2 [Hsub Hty]].
apply sub_inversion_arrow in Hsub.
destruct Hsub as [U1 [U2 [Heq [Hsub1 Hsub2]]]].
inversion Heq; subst...
Qed.
(** Exercise: optimize the proof script, using
[introv], [lets] and [inverts*]. In particular,
you will find it useful to replace the pattern
[apply K in H. destruct H as I] with [lets I: K H].
The solution is 4 lines. *)
Lemma abs_arrow' : forall x S1 s2 T1 T2,
has_type empty (tabs x S1 s2) (TArrow T1 T2) ->
subtype T1 S1
/\ has_type (extend empty x S1) s2 T2.
Proof.
(* FILL IN HERE *) admit.
Qed.
(** The lemma [substitution_preserves_typing] has already been used to
illustrate the working of [lets] and [applys] in chapter
[UseTactics]. Optimize further this proof using automation (with
the star symbol), and using the tactic [cases_if']. The solution
is 33 lines, including the [Case] instructions (21 lines without
them). *)
Lemma substitution_preserves_typing : forall Gamma x U v t S,
has_type (extend Gamma x U) t S ->
has_type empty v U ->
has_type Gamma ([x:=v]t) S.
Proof.
(* FILL IN HERE *) admit.
Qed.
End SubtypingInversion.
(* ####################################################### *)
(** * Advanced Topics in Proof Search *)
(* ####################################################### *)
(** ** Stating Lemmas in the Right Way *)
(** Due to its depth-first strategy, [eauto] can get exponentially
slower as the depth search increases, even when a short proof
exists. In general, to make proof search run reasonably fast, one
should avoid using a depth search greater than 5 or 6. Moreover,
one should try to minimize the number of applicable lemmas, and
usually put first the hypotheses whose proof usefully instantiates
the existential variables.
In fact, the ability for [eauto] to solve certain goals actually
depends on the order in which the hypotheses are stated. This point
is illustrated through the following example, in which [P] is
a predicate on natural numbers. This predicate is such that
[P n] holds for any [n] as soon as [P m] holds for at least one [m]
different from zero. The goal is to prove that [P 2] implies [P 1].
When the hypothesis about [P] is stated in the form
[forall n m, P m -> m <> 0 -> P n], then [eauto] works. However, with
[forall n m, m <> 0 -> P m -> P n], the tactic [eauto] fails. *)
Lemma order_matters_1 : forall (P : nat->Prop),
(forall n m, P m -> m <> 0 -> P n) -> P 2 -> P 1.
Proof.
eauto. (* Success *)
(* The proof: [intros P H K. eapply H. apply K. auto.] *)
Qed.
Lemma order_matters_2 : forall (P : nat->Prop),
(forall n m, m <> 0 -> P m -> P n) -> P 5 -> P 1.
Proof.
eauto. (* Failure *)
(* To understand why, let us replay the previous proof *)
intros P H K.
eapply H.
(* The application of [eapply] has left two subgoals,
[?X <> 0] and [P ?X], where [?X] is an existential variable. *)
(* Solving the first subgoal is easy for [eauto]: it suffices
to instantiate [?X] as the value [1], which is the simplest
value that satisfies [?X <> 0]. *)
eauto.
(* But then the second goal becomes [P 1], which is where we
started from. So, [eauto] gets stuck at this point. *)
Abort.
(** It is very important to understand that the hypothesis [forall n
m, P m -> m <> 0 -> P n] is eauto-friendly, whereas [forall n m, m
<> 0 -> P m -> P n] really isn't. Guessing a value of [m] for
which [P m] holds and then checking that [m <> 0] holds works well
because there are few values of [m] for which [P m] holds. So, it
is likely that [eauto] comes up with the right one. On the other
hand, guessing a value of [m] for which [m <> 0] and then checking
that [P m] holds does not work well, because there are many values
of [m] that satisfy [m <> 0] but not [P m]. *)
(* ####################################################### *)
(** ** Unfolding of Definitions During Proof-Search *)
(** The use of intermediate definitions is generally encouraged in a
formal development as it usually leads to more concise and more
readable statements. Yet, definitions can make it a little harder
to automate proofs. The problem is that it is not obvious for a
proof search mechanism to know when definitions need to be
unfolded. Note that a naive strategy that consists in unfolding
all definitions before calling proof search does not scale up to
large proofs, so we avoid it. This section introduces a few
techniques for avoiding to manually unfold definitions before
calling proof search. *)
(** To illustrate the treatment of definitions, let [P] be an abstract
predicate on natural numbers, and let [myFact] be a definition
denoting the proposition [P x] holds for any [x] less than or
equal to 3. *)
Axiom P : nat -> Prop.
Definition myFact := forall x, x <= 3 -> P x.
(** Proving that [myFact] under the assumption that [P x] holds for
any [x] should be trivial. Yet, [auto] fails to prove it unless we
unfold the definition of [myFact] explicitly. *)
Lemma demo_hint_unfold_goal_1 :
(forall x, P x) -> myFact.
Proof.
auto. (* Proof search doesn't know what to do, *)
unfold myFact. auto. (* unless we unfold the definition. *)
Qed.
(** To automate the unfolding of definitions that appear as proof
obligation, one can use the command [Hint Unfold myFact] to tell
Coq that it should always try to unfold [myFact] when [myFact]
appears in the goal. *)
Hint Unfold myFact.
(** This time, automation is able to see through the definition
of [myFact]. *)
Lemma demo_hint_unfold_goal_2 :
(forall x, P x) -> myFact.
Proof. auto. Qed.
(** However, the [Hint Unfold] mechanism only works for unfolding
definitions that appear in the goal. In general, proof search does
not unfold definitions from the context. For example, assume we
want to prove that [P 3] holds under the assumption that [True ->
myFact]. *)
Lemma demo_hint_unfold_context_1 :
(True -> myFact) -> P 3.
Proof.
intros.
auto. (* fails *)
unfold myFact in *. auto. (* succeeds *)
Qed.
(** There is actually one exception to the previous rule: a constant
occuring in an hypothesis is automatically unfolded if the
hypothesis can be directly applied to the current goal. For example,
[auto] can prove [myFact -> P 3], as illustrated below. *)
Lemma demo_hint_unfold_context_2 :
myFact -> P 3.
Proof. auto. Qed.
(* ####################################################### *)
(** ** Automation for Proving Absurd Goals *)
(** In this section, we'll see that lemmas concluding on a negation
are generally not useful as hints, and that lemmas whose
conclusion is [False] can be useful hints but having too many of
them makes proof search inefficient. We'll also see a practical
work-around to the efficiency issue. *)
(** Consider the following lemma, which asserts that a number
less than or equal to 3 is not greater than 3. *)
Parameter le_not_gt : forall x,
(x <= 3) -> ~ (x > 3).
(** Equivalently, one could state that a number greater than three is
not less than or equal to 3. *)
Parameter gt_not_le : forall x,
(x > 3) -> ~ (x <= 3).
(** In fact, both statements are equivalent to a third one stating
that [x <= 3] and [x > 3] are contradictory, in the sense that
they imply [False]. *)
Parameter le_gt_false : forall x,
(x <= 3) -> (x > 3) -> False.
(** The following investigation aim at figuring out which of the three
statments is the most convenient with respect to proof
automation. The following material is enclosed inside a [Section],
so as to restrict the scope of the hints that we are adding. In
other words, after the end of the section, the hints added within
the section will no longer be active.*)
Section DemoAbsurd1.
(** Let's try to add the first lemma, [le_not_gt], as hint,
and see whether we can prove that the proposition
[exists x, x <= 3 /\ x > 3] is absurd. *)
Hint Resolve le_not_gt.
Lemma demo_auto_absurd_1 :
(exists x, x <= 3 /\ x > 3) -> False.
Proof.
intros. jauto_set. (* decomposes the assumption *)
(* debug *) eauto. (* does not see that [le_not_gt] could apply *)
eapply le_not_gt. eauto. eauto.
Qed.
(** The lemma [gt_not_le] is symmetric to [le_not_gt], so it will not
be any better. The third lemma, [le_gt_false], is a more useful
hint, because it concludes on [False], so proof search will try to
apply it when the current goal is [False]. *)
Hint Resolve le_gt_false.
Lemma demo_auto_absurd_2 :
(exists x, x <= 3 /\ x > 3) -> False.
Proof.
dup.
(* detailed version: *)
intros. jauto_set. (* debug *) eauto.
(* short version: *)
jauto.
Qed.
(** In summary, a lemma of the form [H1 -> H2 -> False] is a much more
effective hint than [H1 -> ~ H2], even though the two statments
are equivalent up to the definition of the negation symbol [~]. *)
(** That said, one should be careful with adding lemmas whose
conclusion is [False] as hint. The reason is that whenever
reaching the goal [False], the proof search mechanism will
potentially try to apply all the hints whose conclusion is [False]
before applying the appropriate one. *)
End DemoAbsurd1.
(** Adding lemmas whose conclusion is [False] as hint can be, locally,
a very effective solution. However, this approach does not scale
up for global hints. For most practical applications, it is
reasonable to give the name of the lemmas to be exploited for
deriving a contradiction. The tactic [false H], provided by
[LibTactics] serves that purpose: [false H] replaces the goal
with [False] and calls [eapply H]. Its behavior is described next.
Observe that any of the three statements [le_not_gt], [gt_not_le]
or [le_gt_false] can be used. *)
Lemma demo_false : forall x,
(x <= 3) -> (x > 3) -> 4 = 5.
Proof.
intros. dup 4.
(* A failed proof: *)
false. eapply le_gt_false.
auto. (* here, [auto] does not prove [?x <= 3] by using [H] but
by using the lemma [le_refl : forall x, x <= x]. *)
(* The second subgoal becomes [3 > 3], which is not provable. *)
skip.
(* A correct proof: *)
false. eapply le_gt_false.
eauto. (* here, [eauto] uses [H], as expected, to prove [?x <= 3] *)
eauto. (* so the second subgoal becomes [x > 3] *)
(* The same proof using [false]: *)
false le_gt_false. eauto. eauto.
(* The lemmas [le_not_gt] and [gt_not_le] work as well *)
false le_not_gt. eauto. eauto.
Qed.
(** In the above example, [false le_gt_false; eauto] proves the goal,
but [false le_gt_false; auto] does not, because [auto] does not
correctly instantiate the existential variable. Note that [false*
le_gt_false] would not work either, because the star symbol tries
to call [auto] first. So, there are two possibilities for
completing the proof: either call [false le_gt_false; eauto], or
call [false* (le_gt_false 3)]. *)
(* ####################################################### *)
(** ** Automation for Transitivity Lemmas *)
(** Some lemmas should never be added as hints, because they would
very badly slow down proof search. The typical example is that of
transitivity results. This section describes the problem and
presents a general workaround.
Consider a subtyping relation, written [subtype S T], that relates
two object [S] and [T] of type [typ]. Assume that this relation
has been proved reflexive and transitive. The corresponding lemmas
are named [subtype_refl] and [subtype_trans]. *)
Parameter typ : Type.
Parameter subtype : typ -> typ -> Prop.
Parameter subtype_refl : forall T,
subtype T T.
Parameter subtype_trans : forall S T U,
subtype S T -> subtype T U -> subtype S U.
(** Adding reflexivity as hint is generally a good idea,
so let's add reflexivity of subtyping as hint. *)
Hint Resolve subtype_refl.
(** Adding transitivity as hint is generally a bad idea. To
understand why, let's add it as hint and see what happens.
Because we cannot remove hints once we've added them, we are going
to open a "Section," so as to restrict the scope of the
transitivity hint to that section. *)
Section HintsTransitivity.
Hint Resolve subtype_trans.
(** Now, consider the goal [forall S T, subtype S T], which clearly has
no hope of being solved. Let's call [eauto] on this goal. *)
Lemma transitivity_bad_hint_1 : forall S T,
subtype S T.
Proof.
intros. (* debug *) eauto. (* Investigates 106 applications... *)
Abort.
(** Note that after closing the section, the hint [subtype_trans]
is no longer active. *)
End HintsTransitivity.
(** In the previous example, the proof search has spent a lot of time
trying to apply transitivity and reflexivity in every possible
way. Its process can be summarized as follows. The first goal is
[subtype S T]. Since reflexivity does not apply, [eauto] invokes
transitivity, which produces two subgoals, [subtype S ?X] and
[subtype ?X T]. Solving the first subgoal, [subtype S ?X], is
straightforward, it suffices to apply reflexivity. This unifies
[?X] with [S]. So, the second sugoal, [subtype ?X T],
becomes [subtype S T], which is exactly what we started from...
The problem with the transitivity lemma is that it is applicable
to any goal concluding on a subtyping relation. Because of this,
[eauto] keeps trying to apply it even though it most often doesn't
help to solve the goal. So, one should never add a transitivity
lemma as a hint for proof search. *)
(** There is a general workaround for having automation to exploit
transitivity lemmas without giving up on efficiency. This workaround
relies on a powerful mechanism called "external hint." This
mechanism allows to manually describe the condition under which
a particular lemma should be tried out during proof search.
For the case of transitivity of subtyping, we are going to tell
Coq to try and apply the transitivity lemma on a goal of the form
[subtype S U] only when the proof context already contains an
assumption either of the form [subtype S T] or of the form
[subtype T U]. In other words, we only apply the transitivity
lemma when there is some evidence that this application might
help. To set up this "external hint," one has to write the
following. *)
Hint Extern 1 (subtype ?S ?U) =>
match goal with
| H: subtype S ?T |- _ => apply (@subtype_trans S T U)
| H: subtype ?T U |- _ => apply (@subtype_trans S T U)
end.
(** This hint declaration can be understood as follows.
- "Hint Extern" introduces the hint.
- The number "1" corresponds to a priority for proof search.
It doesn't matter so much what priority is used in practice.
- The pattern [subtype ?S ?U] describes the kind of goal on
which the pattern should apply. The question marks are used
to indicate that the variables [?S] and [?U] should be bound
to some value in the rest of the hint description.
- The construction [match goal with ... end] tries to recognize
patterns in the goal, or in the proof context, or both.
- The first pattern is [H: subtype S ?T |- _]. It indices that
the context should contain an hypothesis [H] of type
[subtype S ?T], where [S] has to be the same as in the goal,
and where [?T] can have any value.
- The symbol [|- _] at the end of [H: subtype S ?T |- _] indicates
that we do not impose further condition on how the proof
obligation has to look like.
- The branch [=> apply (@subtype_trans S T U)] that follows
indicates that if the goal has the form [subtype S U] and if
there exists an hypothesis of the form [subtype S T], then
we should try and apply transitivity lemma instantiated on
the arguments [S], [T] and [U]. (Note: the symbol [@] in front of
[subtype_trans] is only actually needed when the "Implicit Arguments"
feature is activated.)
- The other branch, which corresponds to an hypothesis of the form
[H: subtype ?T U] is symmetrical.
Note: the same external hint can be reused for any other transitive
relation, simply by renaming [subtype] into the name of that relation. *)
(** Let us see an example illustrating how the hint works. *)
Lemma transitivity_workaround_1 : forall T1 T2 T3 T4,
subtype T1 T2 -> subtype T2 T3 -> subtype T3 T4 -> subtype T1 T4.
Proof.
intros. (* debug *) eauto. (* The trace shows the external hint being used *)
Qed.
(** We may also check that the new external hint does not suffer from the
complexity blow up. *)
Lemma transitivity_workaround_2 : forall S T,
subtype S T.
Proof.
intros. (* debug *) eauto. (* Investigates 0 applications *)
Abort.
(* ####################################################### *)
(** * Decision Procedures *)
(** A decision procedure is able to solve proof obligations whose
statement admits a particular form. This section describes three
useful decision procedures. The tactic [omega] handles goals
involving arithmetic and inequalities, but not general
multiplications. The tactic [ring] handles goals involving
arithmetic, including multiplications, but does not support
inequalities. The tactic [congruence] is able to prove equalities
and inequalities by exploiting equalities available in the proof
context. *)
(* ####################################################### *)
(** ** Omega *)
(** The tactic [omega] supports natural numbers (type [nat]) as well as
integers (type [Z], available by including the module [ZArith]).
It supports addition, substraction, equalities and inequalities.
Before using [omega], one needs to import the module [Omega],
as follows. *)
Require Import Omega.
(** Here is an example. Let [x] and [y] be two natural numbers
(they cannot be negative). Assume [y] is less than 4, assume
[x+x+1] is less than [y], and assume [x] is not zero. Then,
it must be the case that [x] is equal to one. *)
Lemma omega_demo_1 : forall (x y : nat),
(y <= 4) -> (x + x + 1 <= y) -> (x <> 0) -> (x = 1).
Proof. intros. omega. Qed.
(** Another example: if [z] is the mean of [x] and [y], and if the
difference between [x] and [y] is at most [4], then the difference
between [x] and [z] is at most 2. *)
Lemma omega_demo_2 : forall (x y z : nat),
(x + y = z + z) -> (x - y <= 4) -> (x - z <= 2).
Proof. intros. omega. Qed.
(** One can proof [False] using [omega] if the mathematical facts
from the context are contradictory. In the following example,
the constraints on the values [x] and [y] cannot be all
satisfied in the same time. *)
Lemma omega_demo_3 : forall (x y : nat),
(x + 5 <= y) -> (y - x < 3) -> False.
Proof. intros. omega. Qed.
(** Note: [omega] can prove a goal by contradiction only if its
conclusion is reduced [False]. The tactic [omega] always fails
when the conclusion is an arbitrary proposition [P], even though
[False] implies any proposition [P] (by [ex_falso_quodlibet]). *)
Lemma omega_demo_4 : forall (x y : nat) (P : Prop),
(x + 5 <= y) -> (y - x < 3) -> P.
Proof.
intros.
(* Calling [omega] at this point fails with the message:
"Omega: Can't solve a goal with proposition variables" *)
(* So, one needs to replace the goal by [False] first. *)
false. omega.
Qed.
(* ####################################################### *)
(** ** Ring *)
(** Compared with [omega], the tactic [ring] adds support for
multiplications, however it gives up the ability to reason on
inequations. Moreover, it supports only integers (type [Z]) and
not natural numbers (type [nat]). Here is an example showing how
to use [ring]. *)
Module RingDemo.
Require Import ZArith.
Open Scope Z_scope.
(* Arithmetic symbols are now interpreted in [Z] *)
Lemma ring_demo : forall (x y z : Z),
x * (y + z) - z * 3 * x
= x * y - 2 * x * z.
Proof. intros. ring. Qed.
End RingDemo.
(* ####################################################### *)
(** ** Congruence *)
(** The tactic [congruence] is able to exploit equalities from the
proof context in order to automatically perform the rewriting
operations necessary to establish a goal. It is slightly more
powerful than the tactic [subst], which can only handle equalities
of the form [x = e] where [x] is a variable and [e] an
expression. *)
Lemma congruence_demo_1 :
forall (f : nat->nat->nat) (g h : nat->nat) (x y z : nat),
f (g x) (g y) = z ->
2 = g x ->
g y = h z ->
f 2 (h z) = z.
Proof. intros. congruence. Qed.
(** Moreover, [congruence] is able to exploit universally quantified
equalities, for example [forall a, g a = h a]. *)
Lemma congruence_demo_2 :
forall (f : nat->nat->nat) (g h : nat->nat) (x y z : nat),
(forall a, g a = h a) ->
f (g x) (g y) = z ->
g x = 2 ->
f 2 (h y) = z.
Proof. congruence. Qed.
(** Next is an example where [congruence] is very useful. *)
Lemma congruence_demo_4 : forall (f g : nat->nat),
(forall a, f a = g a) ->
f (g (g 2)) = g (f (f 2)).
Proof. congruence. Qed.
(** The tactic [congruence] is able to prove a contradiction if the
goal entails an equality that contradicts an inequality available
in the proof context. *)
Lemma congruence_demo_3 :
forall (f g h : nat->nat) (x : nat),
(forall a, f a = h a) ->
g x = f x ->
g x <> h x ->
False.
Proof. congruence. Qed.
(** One of the strengths of [congruence] is that it is a very fast
tactic. So, one should not hesitate to invoke it wherever it might
help. *)
(* ####################################################### *)
(** * Summary *)
(** Let us summarize the main automation tactics available.
- [auto] automatically applies [reflexivity], [assumption], and [apply].
- [eauto] moreover tries [eapply], and in particular can instantiate
existentials in the conclusion.
- [iauto] extends [eauto] with support for negation, conjunctions, and
disjunctions. However, its support for disjunction can make it
exponentially slow.
- [jauto] extends [eauto] with support for negation, conjunctions, and
existential at the head of hypothesis.
- [congruence] helps reasoning about equalities and inequalities.
- [omega] proves arithmetic goals with equalities and inequalities,
but it does not support multiplication.
- [ring] proves arithmetic goals with multiplications, but does not
support inequalities.
In order to set up automation appropriately, keep in mind the following
rule of thumbs:
- automation is all about balance: not enough automation makes proofs
not very robust on change, whereas too much automation makes proofs
very hard to fix when they break.
- if a lemma is not goal directed (i.e., some of its variables do not
occur in its conclusion), then the premises need to be ordered in
such a way that proving the first premises maximizes the chances of
correctly instantiating the variables that do not occur in the conclusion.
- a lemma whose conclusion is [False] should only be added as a local
hint, i.e., as a hint within the current section.
- a transitivity lemma should never be considered as hint; if automation
of transitivity reasoning is really necessary, an [Extern Hint] needs
to be set up.
- a definition usually needs to be accompanied with a [Hint Unfold].
Becoming a master in the black art of automation certainly requires
some investment, however this investment will pay off very quickly.
*)
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
`define INT_RANGE 31:0
`define INT_RANGE 31:0 // Duplicate identical defs are OK
`define INT_RANGE_MAX 31
`define VECTOR_RANGE 511:0
module t (clk);
// verilator lint_off WIDTH
parameter WIDTH = 16; // Must be a power of 2
parameter WIDTH_LOG2 = 4; // set to log2(WIDTH)
parameter USE_BS = 1; // set to 1 for enable
input clk;
function [`VECTOR_RANGE] func_tree_left;
input [`VECTOR_RANGE] x; // x[width-1:0] is the input vector
reg [`VECTOR_RANGE] flip;
begin
flip = 'd0;
func_tree_left = flip;
end
endfunction
reg [WIDTH-1:0] a; // value to be shifted
reg [WIDTH-1:0] tree_left;
always @(a) begin : barrel_shift
tree_left = func_tree_left (a);
end // barrel_shift
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a = 5;
end
if (cyc==2) begin
$display ("%x\n",tree_left);
//if (tree_left != 'd15) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
`define INT_RANGE 31:0
`define INT_RANGE 31:0 // Duplicate identical defs are OK
`define INT_RANGE_MAX 31
`define VECTOR_RANGE 511:0
module t (clk);
// verilator lint_off WIDTH
parameter WIDTH = 16; // Must be a power of 2
parameter WIDTH_LOG2 = 4; // set to log2(WIDTH)
parameter USE_BS = 1; // set to 1 for enable
input clk;
function [`VECTOR_RANGE] func_tree_left;
input [`VECTOR_RANGE] x; // x[width-1:0] is the input vector
reg [`VECTOR_RANGE] flip;
begin
flip = 'd0;
func_tree_left = flip;
end
endfunction
reg [WIDTH-1:0] a; // value to be shifted
reg [WIDTH-1:0] tree_left;
always @(a) begin : barrel_shift
tree_left = func_tree_left (a);
end // barrel_shift
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a = 5;
end
if (cyc==2) begin
$display ("%x\n",tree_left);
//if (tree_left != 'd15) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t_case_huge_sub2 (/*AUTOARG*/
// Outputs
outa,
// Inputs
index
);
input [9:0] index;
output [9:0] outa;
// =============================
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [9:0] outa;
// End of automatics
// =============================
// Created from perl
// for $i (0..1023) { printf "\t10'h%03x: begin outa = 10'h%03x; outb = 2'b%02b; outc = 1'b%d; end\n", $i, rand(1024),rand(4),rand(2); };
always @(/*AS*/index) begin
case (index[7:0])
`ifdef VERILATOR // Harder test
8'h00: begin outa = $c("0"); end // Makes whole table non-optimizable
`else
8'h00: begin outa = 10'h0; end
`endif
8'h01: begin outa = 10'h318; end
8'h02: begin outa = 10'h29f; end
8'h03: begin outa = 10'h392; end
8'h04: begin outa = 10'h1ef; end
8'h05: begin outa = 10'h06c; end
8'h06: begin outa = 10'h29f; end
8'h07: begin outa = 10'h29a; end
8'h08: begin outa = 10'h3ce; end
8'h09: begin outa = 10'h37c; end
8'h0a: begin outa = 10'h058; end
8'h0b: begin outa = 10'h3b2; end
8'h0c: begin outa = 10'h36f; end
8'h0d: begin outa = 10'h2c5; end
8'h0e: begin outa = 10'h23a; end
8'h0f: begin outa = 10'h222; end
8'h10: begin outa = 10'h328; end
8'h11: begin outa = 10'h3c3; end
8'h12: begin outa = 10'h12c; end
8'h13: begin outa = 10'h1d0; end
8'h14: begin outa = 10'h3ff; end
8'h15: begin outa = 10'h115; end
8'h16: begin outa = 10'h3ba; end
8'h17: begin outa = 10'h3ba; end
8'h18: begin outa = 10'h10d; end
8'h19: begin outa = 10'h13b; end
8'h1a: begin outa = 10'h0a0; end
8'h1b: begin outa = 10'h264; end
8'h1c: begin outa = 10'h3a2; end
8'h1d: begin outa = 10'h07c; end
8'h1e: begin outa = 10'h291; end
8'h1f: begin outa = 10'h1d1; end
8'h20: begin outa = 10'h354; end
8'h21: begin outa = 10'h0c0; end
8'h22: begin outa = 10'h191; end
8'h23: begin outa = 10'h379; end
8'h24: begin outa = 10'h073; end
8'h25: begin outa = 10'h2fd; end
8'h26: begin outa = 10'h2e0; end
8'h27: begin outa = 10'h337; end
8'h28: begin outa = 10'h2c7; end
8'h29: begin outa = 10'h19e; end
8'h2a: begin outa = 10'h107; end
8'h2b: begin outa = 10'h06a; end
8'h2c: begin outa = 10'h1c7; end
8'h2d: begin outa = 10'h107; end
8'h2e: begin outa = 10'h0cf; end
8'h2f: begin outa = 10'h009; end
8'h30: begin outa = 10'h09d; end
8'h31: begin outa = 10'h28e; end
8'h32: begin outa = 10'h010; end
8'h33: begin outa = 10'h1e0; end
8'h34: begin outa = 10'h079; end
8'h35: begin outa = 10'h13e; end
8'h36: begin outa = 10'h282; end
8'h37: begin outa = 10'h21c; end
8'h38: begin outa = 10'h148; end
8'h39: begin outa = 10'h3c0; end
8'h3a: begin outa = 10'h176; end
8'h3b: begin outa = 10'h3fc; end
8'h3c: begin outa = 10'h295; end
8'h3d: begin outa = 10'h113; end
8'h3e: begin outa = 10'h354; end
8'h3f: begin outa = 10'h0db; end
8'h40: begin outa = 10'h238; end
8'h41: begin outa = 10'h12b; end
8'h42: begin outa = 10'h1dc; end
8'h43: begin outa = 10'h137; end
8'h44: begin outa = 10'h1e2; end
8'h45: begin outa = 10'h3d5; end
8'h46: begin outa = 10'h30c; end
8'h47: begin outa = 10'h298; end
8'h48: begin outa = 10'h080; end
8'h49: begin outa = 10'h35a; end
8'h4a: begin outa = 10'h01b; end
8'h4b: begin outa = 10'h0a3; end
8'h4c: begin outa = 10'h0b3; end
8'h4d: begin outa = 10'h17a; end
8'h4e: begin outa = 10'h3ae; end
8'h4f: begin outa = 10'h078; end
8'h50: begin outa = 10'h322; end
8'h51: begin outa = 10'h213; end
8'h52: begin outa = 10'h11a; end
8'h53: begin outa = 10'h1a7; end
8'h54: begin outa = 10'h35a; end
8'h55: begin outa = 10'h233; end
8'h56: begin outa = 10'h01d; end
8'h57: begin outa = 10'h2d5; end
8'h58: begin outa = 10'h1a0; end
8'h59: begin outa = 10'h3d0; end
8'h5a: begin outa = 10'h181; end
8'h5b: begin outa = 10'h219; end
8'h5c: begin outa = 10'h26a; end
8'h5d: begin outa = 10'h050; end
8'h5e: begin outa = 10'h189; end
8'h5f: begin outa = 10'h1eb; end
8'h60: begin outa = 10'h224; end
8'h61: begin outa = 10'h2fe; end
8'h62: begin outa = 10'h0ae; end
8'h63: begin outa = 10'h1cd; end
8'h64: begin outa = 10'h273; end
8'h65: begin outa = 10'h268; end
8'h66: begin outa = 10'h111; end
8'h67: begin outa = 10'h1f9; end
8'h68: begin outa = 10'h232; end
8'h69: begin outa = 10'h255; end
8'h6a: begin outa = 10'h34c; end
8'h6b: begin outa = 10'h049; end
8'h6c: begin outa = 10'h197; end
8'h6d: begin outa = 10'h0fe; end
8'h6e: begin outa = 10'h253; end
8'h6f: begin outa = 10'h2de; end
8'h70: begin outa = 10'h13b; end
8'h71: begin outa = 10'h040; end
8'h72: begin outa = 10'h0b4; end
8'h73: begin outa = 10'h233; end
8'h74: begin outa = 10'h198; end
8'h75: begin outa = 10'h018; end
8'h76: begin outa = 10'h2f7; end
8'h77: begin outa = 10'h134; end
8'h78: begin outa = 10'h1ca; end
8'h79: begin outa = 10'h286; end
8'h7a: begin outa = 10'h0e6; end
8'h7b: begin outa = 10'h064; end
8'h7c: begin outa = 10'h257; end
8'h7d: begin outa = 10'h31a; end
8'h7e: begin outa = 10'h247; end
8'h7f: begin outa = 10'h299; end
8'h80: begin outa = 10'h02c; end
8'h81: begin outa = 10'h2bb; end
8'h82: begin outa = 10'h180; end
8'h83: begin outa = 10'h245; end
8'h84: begin outa = 10'h0da; end
8'h85: begin outa = 10'h367; end
8'h86: begin outa = 10'h304; end
8'h87: begin outa = 10'h38b; end
8'h88: begin outa = 10'h09f; end
8'h89: begin outa = 10'h1f0; end
8'h8a: begin outa = 10'h281; end
8'h8b: begin outa = 10'h019; end
8'h8c: begin outa = 10'h1f2; end
8'h8d: begin outa = 10'h0b1; end
8'h8e: begin outa = 10'h058; end
8'h8f: begin outa = 10'h39b; end
8'h90: begin outa = 10'h2ec; end
8'h91: begin outa = 10'h250; end
8'h92: begin outa = 10'h3f4; end
8'h93: begin outa = 10'h057; end
8'h94: begin outa = 10'h18f; end
8'h95: begin outa = 10'h105; end
8'h96: begin outa = 10'h1ae; end
8'h97: begin outa = 10'h04e; end
8'h98: begin outa = 10'h240; end
8'h99: begin outa = 10'h3e4; end
8'h9a: begin outa = 10'h3c6; end
8'h9b: begin outa = 10'h109; end
8'h9c: begin outa = 10'h073; end
8'h9d: begin outa = 10'h19f; end
8'h9e: begin outa = 10'h3b8; end
8'h9f: begin outa = 10'h00e; end
8'ha0: begin outa = 10'h1b3; end
8'ha1: begin outa = 10'h2bd; end
8'ha2: begin outa = 10'h324; end
8'ha3: begin outa = 10'h343; end
8'ha4: begin outa = 10'h1c9; end
8'ha5: begin outa = 10'h185; end
8'ha6: begin outa = 10'h37a; end
8'ha7: begin outa = 10'h0e0; end
8'ha8: begin outa = 10'h0a3; end
8'ha9: begin outa = 10'h019; end
8'haa: begin outa = 10'h099; end
8'hab: begin outa = 10'h376; end
8'hac: begin outa = 10'h077; end
8'had: begin outa = 10'h2b1; end
8'hae: begin outa = 10'h27f; end
8'haf: begin outa = 10'h265; end
8'hb0: begin outa = 10'h156; end
8'hb1: begin outa = 10'h1ce; end
8'hb2: begin outa = 10'h008; end
8'hb3: begin outa = 10'h12e; end
8'hb4: begin outa = 10'h199; end
8'hb5: begin outa = 10'h330; end
8'hb6: begin outa = 10'h1ab; end
8'hb7: begin outa = 10'h3bd; end
8'hb8: begin outa = 10'h0ca; end
8'hb9: begin outa = 10'h367; end
8'hba: begin outa = 10'h334; end
8'hbb: begin outa = 10'h040; end
8'hbc: begin outa = 10'h1a7; end
8'hbd: begin outa = 10'h036; end
8'hbe: begin outa = 10'h223; end
8'hbf: begin outa = 10'h075; end
8'hc0: begin outa = 10'h3c4; end
8'hc1: begin outa = 10'h2cc; end
8'hc2: begin outa = 10'h123; end
8'hc3: begin outa = 10'h3fd; end
8'hc4: begin outa = 10'h11e; end
8'hc5: begin outa = 10'h27c; end
8'hc6: begin outa = 10'h1e2; end
8'hc7: begin outa = 10'h377; end
8'hc8: begin outa = 10'h33a; end
8'hc9: begin outa = 10'h32d; end
8'hca: begin outa = 10'h014; end
8'hcb: begin outa = 10'h332; end
8'hcc: begin outa = 10'h359; end
8'hcd: begin outa = 10'h0a4; end
8'hce: begin outa = 10'h348; end
8'hcf: begin outa = 10'h04b; end
8'hd0: begin outa = 10'h147; end
8'hd1: begin outa = 10'h026; end
8'hd2: begin outa = 10'h103; end
8'hd3: begin outa = 10'h106; end
8'hd4: begin outa = 10'h35a; end
8'hd5: begin outa = 10'h254; end
8'hd6: begin outa = 10'h0cd; end
8'hd7: begin outa = 10'h17c; end
8'hd8: begin outa = 10'h37e; end
8'hd9: begin outa = 10'h0a9; end
8'hda: begin outa = 10'h0fe; end
8'hdb: begin outa = 10'h3c0; end
8'hdc: begin outa = 10'h1d9; end
8'hdd: begin outa = 10'h10e; end
8'hde: begin outa = 10'h394; end
8'hdf: begin outa = 10'h316; end
8'he0: begin outa = 10'h05b; end
8'he1: begin outa = 10'h126; end
8'he2: begin outa = 10'h369; end
8'he3: begin outa = 10'h291; end
8'he4: begin outa = 10'h2ca; end
8'he5: begin outa = 10'h25b; end
8'he6: begin outa = 10'h106; end
8'he7: begin outa = 10'h172; end
8'he8: begin outa = 10'h2f7; end
8'he9: begin outa = 10'h2d3; end
8'hea: begin outa = 10'h182; end
8'heb: begin outa = 10'h327; end
8'hec: begin outa = 10'h1d0; end
8'hed: begin outa = 10'h204; end
8'hee: begin outa = 10'h11f; end
8'hef: begin outa = 10'h365; end
8'hf0: begin outa = 10'h2c2; end
8'hf1: begin outa = 10'h2b5; end
8'hf2: begin outa = 10'h1f8; end
8'hf3: begin outa = 10'h2a7; end
8'hf4: begin outa = 10'h1be; end
8'hf5: begin outa = 10'h25e; end
8'hf6: begin outa = 10'h032; end
8'hf7: begin outa = 10'h2ef; end
8'hf8: begin outa = 10'h02f; end
8'hf9: begin outa = 10'h201; end
8'hfa: begin outa = 10'h054; end
8'hfb: begin outa = 10'h013; end
8'hfc: begin outa = 10'h249; end
8'hfd: begin outa = 10'h09a; end
8'hfe: begin outa = 10'h012; end
8'hff: begin outa = 10'h114; end
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t_case_huge_sub2 (/*AUTOARG*/
// Outputs
outa,
// Inputs
index
);
input [9:0] index;
output [9:0] outa;
// =============================
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [9:0] outa;
// End of automatics
// =============================
// Created from perl
// for $i (0..1023) { printf "\t10'h%03x: begin outa = 10'h%03x; outb = 2'b%02b; outc = 1'b%d; end\n", $i, rand(1024),rand(4),rand(2); };
always @(/*AS*/index) begin
case (index[7:0])
`ifdef VERILATOR // Harder test
8'h00: begin outa = $c("0"); end // Makes whole table non-optimizable
`else
8'h00: begin outa = 10'h0; end
`endif
8'h01: begin outa = 10'h318; end
8'h02: begin outa = 10'h29f; end
8'h03: begin outa = 10'h392; end
8'h04: begin outa = 10'h1ef; end
8'h05: begin outa = 10'h06c; end
8'h06: begin outa = 10'h29f; end
8'h07: begin outa = 10'h29a; end
8'h08: begin outa = 10'h3ce; end
8'h09: begin outa = 10'h37c; end
8'h0a: begin outa = 10'h058; end
8'h0b: begin outa = 10'h3b2; end
8'h0c: begin outa = 10'h36f; end
8'h0d: begin outa = 10'h2c5; end
8'h0e: begin outa = 10'h23a; end
8'h0f: begin outa = 10'h222; end
8'h10: begin outa = 10'h328; end
8'h11: begin outa = 10'h3c3; end
8'h12: begin outa = 10'h12c; end
8'h13: begin outa = 10'h1d0; end
8'h14: begin outa = 10'h3ff; end
8'h15: begin outa = 10'h115; end
8'h16: begin outa = 10'h3ba; end
8'h17: begin outa = 10'h3ba; end
8'h18: begin outa = 10'h10d; end
8'h19: begin outa = 10'h13b; end
8'h1a: begin outa = 10'h0a0; end
8'h1b: begin outa = 10'h264; end
8'h1c: begin outa = 10'h3a2; end
8'h1d: begin outa = 10'h07c; end
8'h1e: begin outa = 10'h291; end
8'h1f: begin outa = 10'h1d1; end
8'h20: begin outa = 10'h354; end
8'h21: begin outa = 10'h0c0; end
8'h22: begin outa = 10'h191; end
8'h23: begin outa = 10'h379; end
8'h24: begin outa = 10'h073; end
8'h25: begin outa = 10'h2fd; end
8'h26: begin outa = 10'h2e0; end
8'h27: begin outa = 10'h337; end
8'h28: begin outa = 10'h2c7; end
8'h29: begin outa = 10'h19e; end
8'h2a: begin outa = 10'h107; end
8'h2b: begin outa = 10'h06a; end
8'h2c: begin outa = 10'h1c7; end
8'h2d: begin outa = 10'h107; end
8'h2e: begin outa = 10'h0cf; end
8'h2f: begin outa = 10'h009; end
8'h30: begin outa = 10'h09d; end
8'h31: begin outa = 10'h28e; end
8'h32: begin outa = 10'h010; end
8'h33: begin outa = 10'h1e0; end
8'h34: begin outa = 10'h079; end
8'h35: begin outa = 10'h13e; end
8'h36: begin outa = 10'h282; end
8'h37: begin outa = 10'h21c; end
8'h38: begin outa = 10'h148; end
8'h39: begin outa = 10'h3c0; end
8'h3a: begin outa = 10'h176; end
8'h3b: begin outa = 10'h3fc; end
8'h3c: begin outa = 10'h295; end
8'h3d: begin outa = 10'h113; end
8'h3e: begin outa = 10'h354; end
8'h3f: begin outa = 10'h0db; end
8'h40: begin outa = 10'h238; end
8'h41: begin outa = 10'h12b; end
8'h42: begin outa = 10'h1dc; end
8'h43: begin outa = 10'h137; end
8'h44: begin outa = 10'h1e2; end
8'h45: begin outa = 10'h3d5; end
8'h46: begin outa = 10'h30c; end
8'h47: begin outa = 10'h298; end
8'h48: begin outa = 10'h080; end
8'h49: begin outa = 10'h35a; end
8'h4a: begin outa = 10'h01b; end
8'h4b: begin outa = 10'h0a3; end
8'h4c: begin outa = 10'h0b3; end
8'h4d: begin outa = 10'h17a; end
8'h4e: begin outa = 10'h3ae; end
8'h4f: begin outa = 10'h078; end
8'h50: begin outa = 10'h322; end
8'h51: begin outa = 10'h213; end
8'h52: begin outa = 10'h11a; end
8'h53: begin outa = 10'h1a7; end
8'h54: begin outa = 10'h35a; end
8'h55: begin outa = 10'h233; end
8'h56: begin outa = 10'h01d; end
8'h57: begin outa = 10'h2d5; end
8'h58: begin outa = 10'h1a0; end
8'h59: begin outa = 10'h3d0; end
8'h5a: begin outa = 10'h181; end
8'h5b: begin outa = 10'h219; end
8'h5c: begin outa = 10'h26a; end
8'h5d: begin outa = 10'h050; end
8'h5e: begin outa = 10'h189; end
8'h5f: begin outa = 10'h1eb; end
8'h60: begin outa = 10'h224; end
8'h61: begin outa = 10'h2fe; end
8'h62: begin outa = 10'h0ae; end
8'h63: begin outa = 10'h1cd; end
8'h64: begin outa = 10'h273; end
8'h65: begin outa = 10'h268; end
8'h66: begin outa = 10'h111; end
8'h67: begin outa = 10'h1f9; end
8'h68: begin outa = 10'h232; end
8'h69: begin outa = 10'h255; end
8'h6a: begin outa = 10'h34c; end
8'h6b: begin outa = 10'h049; end
8'h6c: begin outa = 10'h197; end
8'h6d: begin outa = 10'h0fe; end
8'h6e: begin outa = 10'h253; end
8'h6f: begin outa = 10'h2de; end
8'h70: begin outa = 10'h13b; end
8'h71: begin outa = 10'h040; end
8'h72: begin outa = 10'h0b4; end
8'h73: begin outa = 10'h233; end
8'h74: begin outa = 10'h198; end
8'h75: begin outa = 10'h018; end
8'h76: begin outa = 10'h2f7; end
8'h77: begin outa = 10'h134; end
8'h78: begin outa = 10'h1ca; end
8'h79: begin outa = 10'h286; end
8'h7a: begin outa = 10'h0e6; end
8'h7b: begin outa = 10'h064; end
8'h7c: begin outa = 10'h257; end
8'h7d: begin outa = 10'h31a; end
8'h7e: begin outa = 10'h247; end
8'h7f: begin outa = 10'h299; end
8'h80: begin outa = 10'h02c; end
8'h81: begin outa = 10'h2bb; end
8'h82: begin outa = 10'h180; end
8'h83: begin outa = 10'h245; end
8'h84: begin outa = 10'h0da; end
8'h85: begin outa = 10'h367; end
8'h86: begin outa = 10'h304; end
8'h87: begin outa = 10'h38b; end
8'h88: begin outa = 10'h09f; end
8'h89: begin outa = 10'h1f0; end
8'h8a: begin outa = 10'h281; end
8'h8b: begin outa = 10'h019; end
8'h8c: begin outa = 10'h1f2; end
8'h8d: begin outa = 10'h0b1; end
8'h8e: begin outa = 10'h058; end
8'h8f: begin outa = 10'h39b; end
8'h90: begin outa = 10'h2ec; end
8'h91: begin outa = 10'h250; end
8'h92: begin outa = 10'h3f4; end
8'h93: begin outa = 10'h057; end
8'h94: begin outa = 10'h18f; end
8'h95: begin outa = 10'h105; end
8'h96: begin outa = 10'h1ae; end
8'h97: begin outa = 10'h04e; end
8'h98: begin outa = 10'h240; end
8'h99: begin outa = 10'h3e4; end
8'h9a: begin outa = 10'h3c6; end
8'h9b: begin outa = 10'h109; end
8'h9c: begin outa = 10'h073; end
8'h9d: begin outa = 10'h19f; end
8'h9e: begin outa = 10'h3b8; end
8'h9f: begin outa = 10'h00e; end
8'ha0: begin outa = 10'h1b3; end
8'ha1: begin outa = 10'h2bd; end
8'ha2: begin outa = 10'h324; end
8'ha3: begin outa = 10'h343; end
8'ha4: begin outa = 10'h1c9; end
8'ha5: begin outa = 10'h185; end
8'ha6: begin outa = 10'h37a; end
8'ha7: begin outa = 10'h0e0; end
8'ha8: begin outa = 10'h0a3; end
8'ha9: begin outa = 10'h019; end
8'haa: begin outa = 10'h099; end
8'hab: begin outa = 10'h376; end
8'hac: begin outa = 10'h077; end
8'had: begin outa = 10'h2b1; end
8'hae: begin outa = 10'h27f; end
8'haf: begin outa = 10'h265; end
8'hb0: begin outa = 10'h156; end
8'hb1: begin outa = 10'h1ce; end
8'hb2: begin outa = 10'h008; end
8'hb3: begin outa = 10'h12e; end
8'hb4: begin outa = 10'h199; end
8'hb5: begin outa = 10'h330; end
8'hb6: begin outa = 10'h1ab; end
8'hb7: begin outa = 10'h3bd; end
8'hb8: begin outa = 10'h0ca; end
8'hb9: begin outa = 10'h367; end
8'hba: begin outa = 10'h334; end
8'hbb: begin outa = 10'h040; end
8'hbc: begin outa = 10'h1a7; end
8'hbd: begin outa = 10'h036; end
8'hbe: begin outa = 10'h223; end
8'hbf: begin outa = 10'h075; end
8'hc0: begin outa = 10'h3c4; end
8'hc1: begin outa = 10'h2cc; end
8'hc2: begin outa = 10'h123; end
8'hc3: begin outa = 10'h3fd; end
8'hc4: begin outa = 10'h11e; end
8'hc5: begin outa = 10'h27c; end
8'hc6: begin outa = 10'h1e2; end
8'hc7: begin outa = 10'h377; end
8'hc8: begin outa = 10'h33a; end
8'hc9: begin outa = 10'h32d; end
8'hca: begin outa = 10'h014; end
8'hcb: begin outa = 10'h332; end
8'hcc: begin outa = 10'h359; end
8'hcd: begin outa = 10'h0a4; end
8'hce: begin outa = 10'h348; end
8'hcf: begin outa = 10'h04b; end
8'hd0: begin outa = 10'h147; end
8'hd1: begin outa = 10'h026; end
8'hd2: begin outa = 10'h103; end
8'hd3: begin outa = 10'h106; end
8'hd4: begin outa = 10'h35a; end
8'hd5: begin outa = 10'h254; end
8'hd6: begin outa = 10'h0cd; end
8'hd7: begin outa = 10'h17c; end
8'hd8: begin outa = 10'h37e; end
8'hd9: begin outa = 10'h0a9; end
8'hda: begin outa = 10'h0fe; end
8'hdb: begin outa = 10'h3c0; end
8'hdc: begin outa = 10'h1d9; end
8'hdd: begin outa = 10'h10e; end
8'hde: begin outa = 10'h394; end
8'hdf: begin outa = 10'h316; end
8'he0: begin outa = 10'h05b; end
8'he1: begin outa = 10'h126; end
8'he2: begin outa = 10'h369; end
8'he3: begin outa = 10'h291; end
8'he4: begin outa = 10'h2ca; end
8'he5: begin outa = 10'h25b; end
8'he6: begin outa = 10'h106; end
8'he7: begin outa = 10'h172; end
8'he8: begin outa = 10'h2f7; end
8'he9: begin outa = 10'h2d3; end
8'hea: begin outa = 10'h182; end
8'heb: begin outa = 10'h327; end
8'hec: begin outa = 10'h1d0; end
8'hed: begin outa = 10'h204; end
8'hee: begin outa = 10'h11f; end
8'hef: begin outa = 10'h365; end
8'hf0: begin outa = 10'h2c2; end
8'hf1: begin outa = 10'h2b5; end
8'hf2: begin outa = 10'h1f8; end
8'hf3: begin outa = 10'h2a7; end
8'hf4: begin outa = 10'h1be; end
8'hf5: begin outa = 10'h25e; end
8'hf6: begin outa = 10'h032; end
8'hf7: begin outa = 10'h2ef; end
8'hf8: begin outa = 10'h02f; end
8'hf9: begin outa = 10'h201; end
8'hfa: begin outa = 10'h054; end
8'hfb: begin outa = 10'h013; end
8'hfc: begin outa = 10'h249; end
8'hfd: begin outa = 10'h09a; end
8'hfe: begin outa = 10'h012; end
8'hff: begin outa = 10'h114; end
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t_case_huge_sub2 (/*AUTOARG*/
// Outputs
outa,
// Inputs
index
);
input [9:0] index;
output [9:0] outa;
// =============================
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [9:0] outa;
// End of automatics
// =============================
// Created from perl
// for $i (0..1023) { printf "\t10'h%03x: begin outa = 10'h%03x; outb = 2'b%02b; outc = 1'b%d; end\n", $i, rand(1024),rand(4),rand(2); };
always @(/*AS*/index) begin
case (index[7:0])
`ifdef VERILATOR // Harder test
8'h00: begin outa = $c("0"); end // Makes whole table non-optimizable
`else
8'h00: begin outa = 10'h0; end
`endif
8'h01: begin outa = 10'h318; end
8'h02: begin outa = 10'h29f; end
8'h03: begin outa = 10'h392; end
8'h04: begin outa = 10'h1ef; end
8'h05: begin outa = 10'h06c; end
8'h06: begin outa = 10'h29f; end
8'h07: begin outa = 10'h29a; end
8'h08: begin outa = 10'h3ce; end
8'h09: begin outa = 10'h37c; end
8'h0a: begin outa = 10'h058; end
8'h0b: begin outa = 10'h3b2; end
8'h0c: begin outa = 10'h36f; end
8'h0d: begin outa = 10'h2c5; end
8'h0e: begin outa = 10'h23a; end
8'h0f: begin outa = 10'h222; end
8'h10: begin outa = 10'h328; end
8'h11: begin outa = 10'h3c3; end
8'h12: begin outa = 10'h12c; end
8'h13: begin outa = 10'h1d0; end
8'h14: begin outa = 10'h3ff; end
8'h15: begin outa = 10'h115; end
8'h16: begin outa = 10'h3ba; end
8'h17: begin outa = 10'h3ba; end
8'h18: begin outa = 10'h10d; end
8'h19: begin outa = 10'h13b; end
8'h1a: begin outa = 10'h0a0; end
8'h1b: begin outa = 10'h264; end
8'h1c: begin outa = 10'h3a2; end
8'h1d: begin outa = 10'h07c; end
8'h1e: begin outa = 10'h291; end
8'h1f: begin outa = 10'h1d1; end
8'h20: begin outa = 10'h354; end
8'h21: begin outa = 10'h0c0; end
8'h22: begin outa = 10'h191; end
8'h23: begin outa = 10'h379; end
8'h24: begin outa = 10'h073; end
8'h25: begin outa = 10'h2fd; end
8'h26: begin outa = 10'h2e0; end
8'h27: begin outa = 10'h337; end
8'h28: begin outa = 10'h2c7; end
8'h29: begin outa = 10'h19e; end
8'h2a: begin outa = 10'h107; end
8'h2b: begin outa = 10'h06a; end
8'h2c: begin outa = 10'h1c7; end
8'h2d: begin outa = 10'h107; end
8'h2e: begin outa = 10'h0cf; end
8'h2f: begin outa = 10'h009; end
8'h30: begin outa = 10'h09d; end
8'h31: begin outa = 10'h28e; end
8'h32: begin outa = 10'h010; end
8'h33: begin outa = 10'h1e0; end
8'h34: begin outa = 10'h079; end
8'h35: begin outa = 10'h13e; end
8'h36: begin outa = 10'h282; end
8'h37: begin outa = 10'h21c; end
8'h38: begin outa = 10'h148; end
8'h39: begin outa = 10'h3c0; end
8'h3a: begin outa = 10'h176; end
8'h3b: begin outa = 10'h3fc; end
8'h3c: begin outa = 10'h295; end
8'h3d: begin outa = 10'h113; end
8'h3e: begin outa = 10'h354; end
8'h3f: begin outa = 10'h0db; end
8'h40: begin outa = 10'h238; end
8'h41: begin outa = 10'h12b; end
8'h42: begin outa = 10'h1dc; end
8'h43: begin outa = 10'h137; end
8'h44: begin outa = 10'h1e2; end
8'h45: begin outa = 10'h3d5; end
8'h46: begin outa = 10'h30c; end
8'h47: begin outa = 10'h298; end
8'h48: begin outa = 10'h080; end
8'h49: begin outa = 10'h35a; end
8'h4a: begin outa = 10'h01b; end
8'h4b: begin outa = 10'h0a3; end
8'h4c: begin outa = 10'h0b3; end
8'h4d: begin outa = 10'h17a; end
8'h4e: begin outa = 10'h3ae; end
8'h4f: begin outa = 10'h078; end
8'h50: begin outa = 10'h322; end
8'h51: begin outa = 10'h213; end
8'h52: begin outa = 10'h11a; end
8'h53: begin outa = 10'h1a7; end
8'h54: begin outa = 10'h35a; end
8'h55: begin outa = 10'h233; end
8'h56: begin outa = 10'h01d; end
8'h57: begin outa = 10'h2d5; end
8'h58: begin outa = 10'h1a0; end
8'h59: begin outa = 10'h3d0; end
8'h5a: begin outa = 10'h181; end
8'h5b: begin outa = 10'h219; end
8'h5c: begin outa = 10'h26a; end
8'h5d: begin outa = 10'h050; end
8'h5e: begin outa = 10'h189; end
8'h5f: begin outa = 10'h1eb; end
8'h60: begin outa = 10'h224; end
8'h61: begin outa = 10'h2fe; end
8'h62: begin outa = 10'h0ae; end
8'h63: begin outa = 10'h1cd; end
8'h64: begin outa = 10'h273; end
8'h65: begin outa = 10'h268; end
8'h66: begin outa = 10'h111; end
8'h67: begin outa = 10'h1f9; end
8'h68: begin outa = 10'h232; end
8'h69: begin outa = 10'h255; end
8'h6a: begin outa = 10'h34c; end
8'h6b: begin outa = 10'h049; end
8'h6c: begin outa = 10'h197; end
8'h6d: begin outa = 10'h0fe; end
8'h6e: begin outa = 10'h253; end
8'h6f: begin outa = 10'h2de; end
8'h70: begin outa = 10'h13b; end
8'h71: begin outa = 10'h040; end
8'h72: begin outa = 10'h0b4; end
8'h73: begin outa = 10'h233; end
8'h74: begin outa = 10'h198; end
8'h75: begin outa = 10'h018; end
8'h76: begin outa = 10'h2f7; end
8'h77: begin outa = 10'h134; end
8'h78: begin outa = 10'h1ca; end
8'h79: begin outa = 10'h286; end
8'h7a: begin outa = 10'h0e6; end
8'h7b: begin outa = 10'h064; end
8'h7c: begin outa = 10'h257; end
8'h7d: begin outa = 10'h31a; end
8'h7e: begin outa = 10'h247; end
8'h7f: begin outa = 10'h299; end
8'h80: begin outa = 10'h02c; end
8'h81: begin outa = 10'h2bb; end
8'h82: begin outa = 10'h180; end
8'h83: begin outa = 10'h245; end
8'h84: begin outa = 10'h0da; end
8'h85: begin outa = 10'h367; end
8'h86: begin outa = 10'h304; end
8'h87: begin outa = 10'h38b; end
8'h88: begin outa = 10'h09f; end
8'h89: begin outa = 10'h1f0; end
8'h8a: begin outa = 10'h281; end
8'h8b: begin outa = 10'h019; end
8'h8c: begin outa = 10'h1f2; end
8'h8d: begin outa = 10'h0b1; end
8'h8e: begin outa = 10'h058; end
8'h8f: begin outa = 10'h39b; end
8'h90: begin outa = 10'h2ec; end
8'h91: begin outa = 10'h250; end
8'h92: begin outa = 10'h3f4; end
8'h93: begin outa = 10'h057; end
8'h94: begin outa = 10'h18f; end
8'h95: begin outa = 10'h105; end
8'h96: begin outa = 10'h1ae; end
8'h97: begin outa = 10'h04e; end
8'h98: begin outa = 10'h240; end
8'h99: begin outa = 10'h3e4; end
8'h9a: begin outa = 10'h3c6; end
8'h9b: begin outa = 10'h109; end
8'h9c: begin outa = 10'h073; end
8'h9d: begin outa = 10'h19f; end
8'h9e: begin outa = 10'h3b8; end
8'h9f: begin outa = 10'h00e; end
8'ha0: begin outa = 10'h1b3; end
8'ha1: begin outa = 10'h2bd; end
8'ha2: begin outa = 10'h324; end
8'ha3: begin outa = 10'h343; end
8'ha4: begin outa = 10'h1c9; end
8'ha5: begin outa = 10'h185; end
8'ha6: begin outa = 10'h37a; end
8'ha7: begin outa = 10'h0e0; end
8'ha8: begin outa = 10'h0a3; end
8'ha9: begin outa = 10'h019; end
8'haa: begin outa = 10'h099; end
8'hab: begin outa = 10'h376; end
8'hac: begin outa = 10'h077; end
8'had: begin outa = 10'h2b1; end
8'hae: begin outa = 10'h27f; end
8'haf: begin outa = 10'h265; end
8'hb0: begin outa = 10'h156; end
8'hb1: begin outa = 10'h1ce; end
8'hb2: begin outa = 10'h008; end
8'hb3: begin outa = 10'h12e; end
8'hb4: begin outa = 10'h199; end
8'hb5: begin outa = 10'h330; end
8'hb6: begin outa = 10'h1ab; end
8'hb7: begin outa = 10'h3bd; end
8'hb8: begin outa = 10'h0ca; end
8'hb9: begin outa = 10'h367; end
8'hba: begin outa = 10'h334; end
8'hbb: begin outa = 10'h040; end
8'hbc: begin outa = 10'h1a7; end
8'hbd: begin outa = 10'h036; end
8'hbe: begin outa = 10'h223; end
8'hbf: begin outa = 10'h075; end
8'hc0: begin outa = 10'h3c4; end
8'hc1: begin outa = 10'h2cc; end
8'hc2: begin outa = 10'h123; end
8'hc3: begin outa = 10'h3fd; end
8'hc4: begin outa = 10'h11e; end
8'hc5: begin outa = 10'h27c; end
8'hc6: begin outa = 10'h1e2; end
8'hc7: begin outa = 10'h377; end
8'hc8: begin outa = 10'h33a; end
8'hc9: begin outa = 10'h32d; end
8'hca: begin outa = 10'h014; end
8'hcb: begin outa = 10'h332; end
8'hcc: begin outa = 10'h359; end
8'hcd: begin outa = 10'h0a4; end
8'hce: begin outa = 10'h348; end
8'hcf: begin outa = 10'h04b; end
8'hd0: begin outa = 10'h147; end
8'hd1: begin outa = 10'h026; end
8'hd2: begin outa = 10'h103; end
8'hd3: begin outa = 10'h106; end
8'hd4: begin outa = 10'h35a; end
8'hd5: begin outa = 10'h254; end
8'hd6: begin outa = 10'h0cd; end
8'hd7: begin outa = 10'h17c; end
8'hd8: begin outa = 10'h37e; end
8'hd9: begin outa = 10'h0a9; end
8'hda: begin outa = 10'h0fe; end
8'hdb: begin outa = 10'h3c0; end
8'hdc: begin outa = 10'h1d9; end
8'hdd: begin outa = 10'h10e; end
8'hde: begin outa = 10'h394; end
8'hdf: begin outa = 10'h316; end
8'he0: begin outa = 10'h05b; end
8'he1: begin outa = 10'h126; end
8'he2: begin outa = 10'h369; end
8'he3: begin outa = 10'h291; end
8'he4: begin outa = 10'h2ca; end
8'he5: begin outa = 10'h25b; end
8'he6: begin outa = 10'h106; end
8'he7: begin outa = 10'h172; end
8'he8: begin outa = 10'h2f7; end
8'he9: begin outa = 10'h2d3; end
8'hea: begin outa = 10'h182; end
8'heb: begin outa = 10'h327; end
8'hec: begin outa = 10'h1d0; end
8'hed: begin outa = 10'h204; end
8'hee: begin outa = 10'h11f; end
8'hef: begin outa = 10'h365; end
8'hf0: begin outa = 10'h2c2; end
8'hf1: begin outa = 10'h2b5; end
8'hf2: begin outa = 10'h1f8; end
8'hf3: begin outa = 10'h2a7; end
8'hf4: begin outa = 10'h1be; end
8'hf5: begin outa = 10'h25e; end
8'hf6: begin outa = 10'h032; end
8'hf7: begin outa = 10'h2ef; end
8'hf8: begin outa = 10'h02f; end
8'hf9: begin outa = 10'h201; end
8'hfa: begin outa = 10'h054; end
8'hfb: begin outa = 10'h013; end
8'hfc: begin outa = 10'h249; end
8'hfd: begin outa = 10'h09a; end
8'hfe: begin outa = 10'h012; end
8'hff: begin outa = 10'h114; end
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg signed [64+15:0] data;
integer i;
integer b;
reg signed [64+15:0] srs;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==2) begin
data <= 80'h0;
data[75] <= 1'b1;
data[10] <= 1'b1;
end
if (cyc==3) begin
for (i=0; i<85; i=i+1) begin
srs = data>>>i;
//$write (" %x >>> %d == %x\n",data,i,srs);
for (b=0; b<80; b=b+1) begin
if (srs[b] != (b==(75-i) || b==(10-i))) $stop;
end
end
end
if (cyc==10) begin
data <= 80'h0;
data[79] <= 1'b1;
data[10] <= 1'b1;
end
if (cyc==12) begin
for (i=0; i<85; i=i+1) begin
srs = data>>>i;
//$write (" %x >>> %d == %x\n",data,i,srs);
for (b=0; b<80; b=b+1) begin
if (srs[b] != (b>=(79-i) || b==(10-i))) $stop;
end
end
end
if (cyc==20) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg signed [64+15:0] data;
integer i;
integer b;
reg signed [64+15:0] srs;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==2) begin
data <= 80'h0;
data[75] <= 1'b1;
data[10] <= 1'b1;
end
if (cyc==3) begin
for (i=0; i<85; i=i+1) begin
srs = data>>>i;
//$write (" %x >>> %d == %x\n",data,i,srs);
for (b=0; b<80; b=b+1) begin
if (srs[b] != (b==(75-i) || b==(10-i))) $stop;
end
end
end
if (cyc==10) begin
data <= 80'h0;
data[79] <= 1'b1;
data[10] <= 1'b1;
end
if (cyc==12) begin
for (i=0; i<85; i=i+1) begin
srs = data>>>i;
//$write (" %x >>> %d == %x\n",data,i,srs);
for (b=0; b<80; b=b+1) begin
if (srs[b] != (b>=(79-i) || b==(10-i))) $stop;
end
end
end
if (cyc==20) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg signed [64+15:0] data;
integer i;
integer b;
reg signed [64+15:0] srs;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==2) begin
data <= 80'h0;
data[75] <= 1'b1;
data[10] <= 1'b1;
end
if (cyc==3) begin
for (i=0; i<85; i=i+1) begin
srs = data>>>i;
//$write (" %x >>> %d == %x\n",data,i,srs);
for (b=0; b<80; b=b+1) begin
if (srs[b] != (b==(75-i) || b==(10-i))) $stop;
end
end
end
if (cyc==10) begin
data <= 80'h0;
data[79] <= 1'b1;
data[10] <= 1'b1;
end
if (cyc==12) begin
for (i=0; i<85; i=i+1) begin
srs = data>>>i;
//$write (" %x >>> %d == %x\n",data,i,srs);
for (b=0; b<80; b=b+1) begin
if (srs[b] != (b>=(79-i) || b==(10-i))) $stop;
end
end
end
if (cyc==20) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h3e3a62edb61f8c7f
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [31:0] in;
output [31:0] out;
genvar i;
generate
for (i=0; i<16; i=i+1) begin : gblk
assign out[i*2+1:i*2] = in[(30-i*2)+1:(30-i*2)];
end
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h3e3a62edb61f8c7f
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [31:0] in;
output [31:0] out;
genvar i;
generate
for (i=0; i<16; i=i+1) begin : gblk
assign out[i*2+1:i*2] = in[(30-i*2)+1:(30-i*2)];
end
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (clk);
input clk;
reg [7:0] crc;
wire [61:59] ah = crc[5:3];
wire [61:59] bh = ~crc[4:2];
wire [41:2] al = {crc,crc,crc,crc,crc};
wire [41:2] bl = ~{crc[6:0],crc[6:0],crc[6:0],crc[6:0],crc[6:0],crc[6:2]};
reg sel;
wire [61:28] q = ( sel
? func(ah, al)
: func(bh, bl));
function [61:28] func;
input [61:59] inh;
input [41:2] inl;
reg [42:28] func_mid;
reg carry;
begin
carry = &inl[27:2];
func_mid = {1'b0,inl[41:28]} + {14'b0, carry};
func[61:59] = inh + {2'b0, func_mid[42]};
func[58:42] = {17{func_mid[41]}};
func[41:28] = func_mid[41:28];
end
endfunction
integer cyc; initial cyc=1;
always @ (posedge clk) begin
//$write("%d %x\n", cyc, q);
if (cyc!=0) begin
cyc <= cyc + 1;
sel <= ~sel;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
if (cyc==1) begin
sel <= 1'b1;
crc <= 8'h12;
end
if (cyc==2) if (q!=34'h100000484) $stop;
if (cyc==3) if (q!=34'h37fffeddb) $stop;
if (cyc==4) if (q!=34'h080001212) $stop;
if (cyc==5) if (q!=34'h1fffff7ef) $stop;
if (cyc==6) if (q!=34'h200000848) $stop;
if (cyc==7) if (q!=34'h380001ebd) $stop;
if (cyc==8) if (q!=34'h07fffe161) $stop;
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [63:0] d;
reg [31:0] c;
wire [31:0] q = crc (d, c);
reg [31:0] q_r;
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
q_r <= q;
c <= q;
d <= {d[62:0], ^d[63:48]};
//$write("%d crc(%x,%x)=%x\n", cyc, d, c, q);
if (cyc==1) begin
// Assign inputs randomly
q_r <= 32'h12345678;
c <= 32'h12345678;
d <= 64'hffffffff_ffffffff;
end
if (cyc==2) begin
d <= 64'hffffffff_ffffffff;
end
if (cyc==3) begin
d <= 64'hffffffff_ffffffff;
end
if (cyc==4) begin
d <= 64'h50183721_81a04b1a;
end
if (cyc==5) begin
end
if (cyc==9) begin
if (q !== 32'h38295e96) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
function [31:0] crc;
input [63:0] di;
input [31:0] ci;
reg [63:0] drev;
begin
drev = reverse(di);
crc = newcrc(drev, ci);
end
endfunction
function [63:0] reverse;
input [63:0] di;
integer i;
begin
reverse = 64'b0;
for (i=0; i<64; i=i+1) reverse[i] = di[63-i];
end
endfunction
function [31:0] newcrc;
input [63:0] D;
input [31:0] C;
reg [31:0] N;
reg [31:0] DT;
begin
N = 32'b0;
// Note this isn't a real CRC code; it's been munged for privacy
N[0] = D[59]^D[53]^D[52]^D[49]^D[44]^D[41]^D[40]^D[39]^D[37]^D[32]^D[29]^D[26]^D[22]^D[21]^D[20]^D[16]^D[15]^D[14]^D[9]^D[7]^D[0]
^C[29]^C[27]^C[24]^C[23]^C[22]^C[21]^C[19]^C[15]^C[13]^C[10]^C[8]^C[3]^C[1];
N[1] = D[61]^D[57]^D[51]^D[47]^D[43]^D[37]^D[35]^D[32]^D[28]^D[24]^D[22]^D[21]^D[20]^D[16]^D[12]^D[11]^D[10]^D[8]^D[7]^D[6]^D[1]^D[0]
^C[30]^C[27]^C[26]^C[20]^C[16]^C[14]^C[13]^C[11]^C[10]^C[8]^C[5]^C[0];
N[2] = D[63]^D[62]^D[61]^D[60]^D[55]^D[54]^D[52]^D[44]^D[43]^D[42]^D[37]^D[34]^D[33]^D[29]^D[28]^D[25]^D[24]^D[23]^D[22]^D[18]^D[16]^D[15]^D[13]^D[12]^D[11]
^C[31]^C[30]^C[27]^C[22]^C[21]^C[18]^C[15]^C[12]^C[11]^C[10]^C[7];
N[3] = D[62]^D[54]^D[50]^D[47]^D[46]^D[38]^D[36]^D[35]^D[34]^D[33]^D[32]^D[30]^D[27]^D[25]^D[21]^D[20]^D[19]^D[17]^D[15]^D[11]^D[8]^D[5]^D[3]^D[1]^D[0]
^C[28]^C[25]^C[24]^C[13]^C[11]^C[9]^C[8]^C[7]^C[3]^C[1];
N[4] = D[57]^D[54]^D[53]^D[52]^D[45]^D[44]^D[43]^D[39]^D[37]^D[34]^D[33]^D[32]^D[31]^D[28]^D[24]^D[23]^D[20]^D[19]^D[15]^D[14]^D[10]^D[6]^D[1]^D[0]
^C[30]^C[24]^C[20]^C[16]^C[14]^C[11]^C[8]^C[7]^C[6]^C[5]^C[2];
N[5] = D[58]^D[57]^D[50]^D[49]^D[48]^D[47]^D[43]^D[39]^D[29]^D[26]^D[23]^D[22]^D[20]^D[18]^D[14]^D[10]^D[9]^D[6]^D[5]^D[4]^D[1]
^C[27]^C[24]^C[20]^C[19]^C[18]^C[14]^C[13]^C[12]^C[11]^C[8]^C[7]^C[1];
N[6] = D[63]^D[62]^D[61]^D[57]^D[51]^D[50]^D[47]^D[38]^D[37]^D[34]^D[30]^D[28]^D[27]^D[25]^D[21]^D[16]^D[15]^D[10]^D[9]^D[6]^D[5]^D[2]^D[1]
^C[31]^C[27]^C[25]^C[16]^C[13]^C[9]^C[8]^C[7]^C[0];
N[7] = ^D[62]^D[61]^D[59]^D[54]^D[52]^D[51]^D[49]^D[46]^D[45]^D[42]^D[41]^D[38]^D[35]^D[29]^D[26]^D[24]^D[15]^D[12]^D[11]^D[9]^D[2]^D[0]
^C[28]^C[27]^C[26]^C[20]^C[19]^C[18]^C[15]^C[12]^C[7]^C[4];
N[8] = D[62]^D[61]^D[60]^D[59]^D[52]^D[50]^D[48]^D[47]^D[46]^D[45]^D[44]^D[42]^D[41]^D[40]^D[30]^D[24]^D[23]^D[22]^D[19]^D[17]^D[11]^D[10]^D[7]^D[6]^D[2]
^C[31]^C[29]^C[27]^C[22]^C[21]^C[19]^C[17]^C[11]^C[9]^C[7]^C[6];
N[9] = D[62]^D[59]^D[58]^D[57]^D[54]^D[51]^D[50]^D[43]^D[41]^D[39]^D[28]^D[25]^D[24]^D[23]^D[22]^D[21]^D[18]^D[16]^D[15]^D[7]
^C[30]^C[29]^C[27]^C[25]^C[23]^C[22]^C[13]^C[12]^C[7]^C[6]^C[5]^C[1];
N[10] = D[61]^D[60]^D[58]^D[56]^D[54]^D[53]^D[51]^D[48]^D[46]^D[43]^D[42]^D[38]^D[37]^D[35]^D[33]^D[31]^D[30]^D[27]^D[26]^D[24]^D[19]^D[10]^D[8]^D[6]^D[1]
^C[31]^C[30]^C[26]^C[25]^C[24]^C[21]^C[16]^C[12]^C[3]^C[2];
N[11] = D[59]^D[57]^D[56]^D[50]^D[49]^D[48]^D[47]^D[46]^D[45]^D[42]^D[41]^D[40]^D[33]^D[32]^D[30]^D[25]^D[21]^D[15]^D[14]^D[13]^D[12]^D[11]^D[5]^D[1]
^C[27]^C[25]^C[24]^C[21]^C[16]^C[12]^C[7]^C[3]^C[2]^C[1];
N[12] = D[62]^D[61]^D[59]^D[58]^D[56]^D[55]^D[53]^D[48]^D[47]^D[44]^D[43]^D[35]^D[31]^D[30]^D[28]^D[24]^D[23]^D[21]^D[14]^D[5]^D[2]
^C[28]^C[26]^C[25]^C[23]^C[22]^C[18]^C[16]^C[15]^C[6];
N[13] = D[63]^D[60]^D[58]^D[57]^D[55]^D[54]^D[53]^D[51]^D[47]^D[45]^D[42]^D[41]^D[38]^D[28]^D[26]^D[25]^D[22]^D[20]^D[18]^D[17]^D[15]^D[13]^D[12]^D[11]
^C[29]^C[28]^C[25]^C[22]^C[19]^C[17]^C[16]^C[15]^C[14]^C[12]^C[10]^C[9];
N[14] = D[58]^D[56]^D[55]^D[52]^D[47]^D[43]^D[41]^D[40]^D[39]^D[38]^D[30]^D[26]^D[25]^D[22]^D[19]^D[17]^D[13]^D[11]^D[10]^D[9]^D[8]^D[3]^D[2]^D[0]
^C[31]^C[28]^C[20]^C[18]^C[17]^C[16]^C[15]^C[13]^C[11]^C[4]^C[2]^C[1];
N[15] = D[63]^D[62]^D[61]^D[59]^D[58]^D[48]^D[47]^D[43]^D[42]^D[35]^D[28]^D[26]^D[25]^D[24]^D[23]^D[22]^D[21]^D[20]^D[19]^D[17]^D[11]^D[7]^D[2]
^C[30]^C[29]^C[27]^C[24]^C[20]^C[17]^C[16]^C[15]^C[11]^C[9]^C[5];
N[16] = D[60]^D[57]^D[49]^D[46]^D[45]^D[43]^D[39]^D[36]^D[32]^D[30]^D[29]^D[28]^D[27]^D[26]^D[23]^D[20]^D[19]^D[17]^D[11]^D[8]^D[5]^D[1]
^C[28]^C[26]^C[23]^C[22]^C[18]^C[16]^C[13]^C[12]^C[10]^C[9]^C[6];
N[17] = D[63]^D[62]^D[61]^D[60]^D[58]^D[54]^D[53]^D[51]^D[48]^D[42]^D[41]^D[37]^D[36]^D[34]^D[28]^D[27]^D[26]^D[24]^D[13]^D[12]^D[9]^D[7]^D[4]^D[0]
^C[31]^C[30]^C[27]^C[23]^C[20]^C[17]^C[14]^C[9]^C[6]^C[4]^C[3]^C[0];
N[18] = D[63]^D[61]^D[59]^D[56]^D[52]^D[50]^D[47]^D[42]^D[37]^D[35]^D[34]^D[31]^D[30]^D[29]^D[22]^D[19]^D[17]^D[16]^D[11]^D[9]^D[8]^D[7]
^C[26]^C[22]^C[20]^C[19]^C[16]^C[11]^C[8]^C[6]^C[5]^C[0];
N[19] = D[62]^D[60]^D[52]^D[49]^D[44]^D[43]^D[42]^D[37]^D[33]^D[32]^D[29]^D[26]^D[19]^D[17]^D[16]^D[12]^D[10]^D[7]^D[6]^D[4]^D[3]^D[2]
^C[30]^C[29]^C[26]^C[25]^C[22]^C[19]^C[14]^C[7]^C[6]^C[5]^C[2]^C[0];
N[20] = D[63]^D[58]^D[54]^D[48]^D[47]^D[40]^D[39]^D[35]^D[34]^D[32]^D[31]^D[28]^D[27]^D[25]^D[18]^D[12]^D[9]^D[7]^D[5]^D[4]^D[3]^D[2]^D[1]
^C[31]^C[29]^C[28]^C[25]^C[19]^C[18]^C[17]^C[15]^C[10]^C[9]^C[6]^C[4];
N[21] = D[61]^D[59]^D[57]^D[56]^D[53]^D[48]^D[44]^D[43]^D[41]^D[35]^D[29]^D[26]^D[25]^D[20]^D[18]^D[17]^D[16]^D[12]^D[9]^D[6]^D[5]^D[3]^D[1]
^C[30]^C[27]^C[24]^C[23]^C[22]^C[21]^C[20]^C[13]^C[9]^C[3]^C[2];
N[22] = D[63]^D[62]^D[60]^D[57]^D[53]^D[51]^D[45]^D[44]^D[42]^D[34]^D[33]^D[27]^D[20]^D[19]^D[18]^D[15]^D[10]^D[9]^D[8]^D[4]^D[3]
^C[24]^C[23]^C[18]^C[17]^C[16]^C[14]^C[12]^C[11]^C[10]^C[9]^C[6]^C[5];
N[23] = D[58]^D[56]^D[54]^D[51]^D[47]^D[43]^D[42]^D[40]^D[37]^D[36]^D[33]^D[25]^D[23]^D[20]^D[18]^D[16]^D[15]^D[12]^D[10]^D[8]^D[7]^D[5]^D[3]
^C[31]^C[27]^C[26]^C[23]^C[21]^C[18]^C[15]^C[11]^C[10]^C[8]^C[7]^C[1];
N[24] = D[60]^D[59]^D[52]^D[50]^D[48]^D[44]^D[39]^D[36]^D[35]^D[31]^D[30]^D[28]^D[27]^D[23]^D[22]^D[21]^D[19]^D[14]^D[13]^D[12]^D[9]^D[4]^D[1]^D[0]
^C[27]^C[25]^C[23]^C[21]^C[17]^C[11]^C[10]^C[4]^C[0];
N[25] = D[61]^D[60]^D[56]^D[54]^D[51]^D[46]^D[43]^D[41]^D[40]^D[38]^D[37]^D[36]^D[29]^D[28]^D[27]^D[22]^D[17]^D[15]^D[10]^D[7]^D[4]^D[2]
^C[29]^C[28]^C[26]^C[23]^C[18]^C[14]^C[13]^C[12]^C[11]^C[9]^C[8]^C[6];
N[26] = D[63]^D[62]^D[58]^D[55]^D[54]^D[52]^D[50]^D[39]^D[37]^D[36]^D[35]^D[33]^D[31]^D[29]^D[27]^D[18]^D[14]^D[10]^D[3]^D[2]^D[0]
^C[31]^C[27]^C[26]^C[25]^C[24]^C[21]^C[13]^C[12]^C[10]^C[1];
N[27] = D[62]^D[60]^D[58]^D[56]^D[55]^D[54]^D[51]^D[44]^D[41]^D[36]^D[34]^D[32]^D[31]^D[29]^D[28]^D[27]^D[23]^D[17]^D[12]^D[11]^D[8]^D[6]^D[4]^D[2]
^C[31]^C[30]^C[28]^C[27]^C[23]^C[19]^C[17]^C[16]^C[14]^C[12]^C[11]^C[10]^C[3];
N[28] = D[57]^D[54]^D[53]^D[51]^D[50]^D[48]^D[40]^D[38]^D[34]^D[33]^D[31]^D[30]^D[29]^D[27]^D[23]^D[21]^D[14]^D[9]^D[7]^D[6]^D[5]^D[4]^D[0]
^C[31]^C[30]^C[26]^C[24]^C[15]^C[14]^C[13]^C[7]^C[6]^C[4]^C[3]^C[0];
N[29] = D[62]^D[60]^D[55]^D[46]^D[45]^D[44]^D[43]^D[41]^D[40]^D[35]^D[33]^D[32]^D[30]^D[28]^D[25]^D[23]^D[22]^D[13]^D[8]^D[7]^D[6]^D[5]^D[4]^D[3]^D[1]^D[0]
^C[31]^C[28]^C[27]^C[18]^C[11]^C[8]^C[6]^C[4]^C[2]^C[1]^C[0];
N[30] = D[63]^D[62]^D[59]^D[58]^D[55]^D[52]^D[47]^D[44]^D[36]^D[35]^D[34]^D[31]^D[29]^D[22]^D[21]^D[20]^D[19]^D[15]^D[14]^D[10]^D[6]^D[3]^D[2]^D[0]
^C[28]^C[25]^C[24]^C[22]^C[20]^C[15]^C[14]^C[12]^C[10]^C[9]^C[4]^C[0];
N[31] = D[61]^D[58]^D[56]^D[55]^D[54]^D[52]^D[51]^D[50]^D[49]^D[42]^D[38]^D[37]^D[36]^D[34]^D[31]^D[30]^D[27]^D[26]^D[23]^D[22]^D[21]^D[19]^D[18]^D[12]^D[0]
^C[28]^C[26]^C[24]^C[21]^C[17]^C[16]^C[14]^C[13]^C[10]^C[8]^C[2];
newcrc = N;
end
endfunction
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [7:0] cyc; initial cyc=0;
reg [31:0] in;
wire [31:0] out;
t_extend_class_v sub (.in(in), .out(out));
always @ (posedge clk) begin
cyc <= cyc+8'd1;
if (cyc == 8'd1) begin
in <= 32'h10;
end
if (cyc == 8'd2) begin
if (out != 32'h11) $stop;
end
if (cyc == 8'd9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module t_extend_class_v (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [31:0] in;
output [31:0] out;
always @* begin
// When "in" changes, call my method
out = $c("m_myobjp->my_math(",in,")");
end
`systemc_header
#include "t_extend_class_c.h" // Header for contained object
`systemc_interface
t_extend_class_c* m_myobjp; // Pointer to object we are embedding
`systemc_ctor
m_myobjp = new t_extend_class_c(); // Construct contained object
`systemc_dtor
delete m_myobjp; // Destruct contained object
`verilog
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [7:0] cyc; initial cyc=0;
reg [31:0] in;
wire [31:0] out;
t_extend_class_v sub (.in(in), .out(out));
always @ (posedge clk) begin
cyc <= cyc+8'd1;
if (cyc == 8'd1) begin
in <= 32'h10;
end
if (cyc == 8'd2) begin
if (out != 32'h11) $stop;
end
if (cyc == 8'd9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module t_extend_class_v (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [31:0] in;
output [31:0] out;
always @* begin
// When "in" changes, call my method
out = $c("m_myobjp->my_math(",in,")");
end
`systemc_header
#include "t_extend_class_c.h" // Header for contained object
`systemc_interface
t_extend_class_c* m_myobjp; // Pointer to object we are embedding
`systemc_ctor
m_myobjp = new t_extend_class_c(); // Construct contained object
`systemc_dtor
delete m_myobjp; // Destruct contained object
`verilog
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [255:0] a;
reg [60:0] divisor;
reg [60:0] qq;
reg [60:0] rq;
reg signed [60:0] qqs;
reg signed [60:0] rqs;
always @* begin
qq = a[60:0] / divisor;
rq = a[60:0] % divisor;
qqs = $signed(a[60:0]) / $signed(divisor);
rqs = $signed(a[60:0]) % $signed(divisor);
end
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d: %x %x %x %x\n", cyc, qq, rq, qqs, rqs);
if (cyc==1) begin
a <= 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26;
divisor <= 61'h12371;
a[60] <= 1'b0; divisor[60] <= 1'b0; // Unsigned
end
if (cyc==2) begin
a <= 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8;
divisor <= 61'h1238123771;
a[60] <= 1'b0; divisor[60] <= 1'b0; // Unsigned
if (qq!==61'h00000403ad81c0da) $stop;
if (rq!==61'h00000000000090ec) $stop;
if (qqs!==61'h00000403ad81c0da) $stop;
if (rqs!==61'h00000000000090ec) $stop;
end
if (cyc==3) begin
a <= 256'h0e17c88f00d5fe51a982646c8002bd68c3e236ddfd00ddbdad20a48e00f395b8;
divisor <= 61'hf1b;
a[60] <= 1'b1; divisor[60] <= 1'b0; // Signed
if (qq!==61'h000000000090832e) $stop;
if (rq!==61'h0000000334becc6a) $stop;
if (qqs!==61'h000000000090832e) $stop;
if (rqs!==61'h0000000334becc6a) $stop;
end
if (cyc==4) begin
a[60] <= 1'b0; divisor[60] <= 1'b1; // Signed
if (qq!==61'h0001eda37cca1be8) $stop;
if (rq!==61'h0000000000000c40) $stop;
if (qqs!==61'h1fffcf5187c76510) $stop;
if (rqs!==61'h1ffffffffffffd08) $stop;
end
if (cyc==5) begin
a[60] <= 1'b1; divisor[60] <= 1'b1; // Signed
if (qq!==61'h0000000000000000) $stop;
if (rq!==61'h0d20a48e00f395b8) $stop;
if (qqs!==61'h0000000000000000) $stop;
if (rqs!==61'h0d20a48e00f395b8) $stop;
end
if (cyc==6) begin
if (qq!==61'h0000000000000001) $stop;
if (rq!==61'h0d20a48e00f3869d) $stop;
if (qqs!==61'h0000000000000000) $stop;
if (rqs!==61'h1d20a48e00f395b8) $stop;
end
// Div by zero
if (cyc==9) begin
divisor <= 61'd0;
end
if (cyc==10) begin
`ifdef verilator
if (qq !== {61{1'b0}}) $stop;
if (rq !== {61{1'b0}}) $stop;
`else
if (qq !== {61{1'bx}}) $stop;
if (rq !== {61{1'bx}}) $stop;
`endif
if ({16{1'bx}} !== 16'd1/16'd0) $stop; // No div by zero errors
if ({16{1'bx}} !== 16'd1%16'd0) $stop; // No div by zero errors
end
if (cyc==19) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
wire [3:0] Value = crc[3:0];
wire [3:0] Result;
wire [3:0] Result2;
Testit testit (/*AUTOINST*/
// Outputs
.Result (Result[3:0]),
.Result2 (Result2[3:0]),
// Inputs
.clk (clk),
.Value (Value[3:0]));
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x %x %x %x\n",$time, cyc, crc, Result, Result2);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= {56'h0, Result, Result2}
^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$write("[%0t] cyc==%0d crc=%x %x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== 64'h4af37965592f64f9) $stop;
$finish;
end
end
endmodule
module Test (clk, Value, Result);
input clk;
input Value;
output Result;
reg Internal;
assign Result = Internal ^ clk;
always @(posedge clk)
Internal <= #1 Value;
endmodule
module Test_wrap1 (clk, Value, Result);
input clk;
input Value;
output Result;
Test t (clk, Value, Result);
endmodule
module Test_wrap2 (clk, Value, Result);
input clk;
input Value;
output Result;
Test t (clk, Value, Result);
endmodule
module Testit (clk, Value, Result, Result2);
input clk;
input [3:0] Value;
output [3:0] Result;
output [3:0] Result2;
genvar i;
generate
for (i = 0; i < 4; i = i + 1)
begin : a
if ((i == 0) || (i == 2)) begin : gblk
Test_wrap1 test (clk, Value[i] , Result[i]);
end
else begin : gblk
Test_wrap2 test (clk, Value[i], Result[i]);
end
end
endgenerate
assign Result2[0] = a[0].gblk.test.t.Internal;
assign Result2[1] = a[1].gblk.test.t.Internal;
assign Result2[2] = a[2].gblk.test.t.Internal;
assign Result2[3] = a[3].gblk.test.t.Internal;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [2:0] index_a;
reg [2:0] index_b;
prover #(4) p4 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(32) p32 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(63) p63 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(64) p64 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(72) p72 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(126) p126 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(128) p128 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
integer cyc; initial cyc=0;
initial index_a = 3'b0;
initial index_b = 3'b0;
always @* begin
index_a = cyc[2:0]; if (index_a>3'd4) index_a=3'd4;
index_b = cyc[5:3]; if (index_b>3'd4) index_b=3'd4;
end
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module prover (
input clk,
input [2:0] index_a,
input [2:0] index_b
);
parameter WIDTH = 4;
reg signed [WIDTH-1:0] as;
reg signed [WIDTH-1:0] bs;
wire [WIDTH-1:0] b = bs;
always @* begin
casez (index_a)
3'd0: as = {(WIDTH){1'd0}}; // 0
3'd1: as = {{(WIDTH-1){1'd0}}, 1'b1}; // 1
3'd2: as = {1'b0, {(WIDTH-1){1'd0}}}; // 127 or equiv
3'd3: as = {(WIDTH){1'd1}}; // -1
3'd4: as = {1'b1, {(WIDTH-1){1'd0}}}; // -128 or equiv
default: $stop;
endcase
casez (index_b)
3'd0: bs = {(WIDTH){1'd0}}; // 0
3'd1: bs = {{(WIDTH-1){1'd0}}, 1'b1}; // 1
3'd2: bs = {1'b0, {(WIDTH-1){1'd0}}}; // 127 or equiv
3'd3: bs = {(WIDTH){1'd1}}; // -1
3'd4: bs = {1'b1, {(WIDTH-1){1'd0}}}; // -128 or equiv
default: $stop;
endcase
end
reg [7:0] results[4:0][4:0];
wire gt = as>b;
wire gts = as>bs;
wire gte = as>=b;
wire gtes = as>=bs;
wire lt = as<b;
wire lts = as<bs;
wire lte = as<=b;
wire ltes = as<=bs;
reg [7:0] exp;
reg [7:0] got;
integer cyc=0;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc>2) begin
`ifdef TEST_VERBOSE
$write("results[%d][%d] = 8'b%b_%b_%b_%b_%b_%b_%b_%b;\n",
index_a, index_b,
gt, gts, gte, gtes, lt, lts, lte, ltes);
`endif
exp = results[index_a][index_b];
got = {gt, gts, gte, gtes, lt, lts, lte, ltes};
if (exp !== got) begin
$display("%%Error: bad comparison width=%0d: %d/%d got=%b exp=%b", WIDTH, index_a,index_b,got, exp);
$stop;
end
end
end
// Result table
initial begin
// Indexes: 0, 1, -1, 127, -128
// Gt Gts Gte Gtes Lt Lts Lte Ltes
results[0][0] = 8'b0_0_1_1_0_0_1_1;
results[0][1] = 8'b0_0_0_0_1_1_1_1;
results[0][2] = 8'b0_0_1_1_0_0_1_1;
results[0][3] = 8'b0_1_0_1_1_0_1_0;
results[0][4] = 8'b0_1_0_1_1_0_1_0;
results[1][0] = 8'b1_1_1_1_0_0_0_0;
results[1][1] = 8'b0_0_1_1_0_0_1_1;
results[1][2] = 8'b1_1_1_1_0_0_0_0;
results[1][3] = 8'b0_1_0_1_1_0_1_0;
results[1][4] = 8'b0_1_0_1_1_0_1_0;
results[2][0] = 8'b0_0_1_1_0_0_1_1;
results[2][1] = 8'b0_0_0_0_1_1_1_1;
results[2][2] = 8'b0_0_1_1_0_0_1_1;
results[2][3] = 8'b0_1_0_1_1_0_1_0;
results[2][4] = 8'b0_1_0_1_1_0_1_0;
results[3][0] = 8'b1_0_1_0_0_1_0_1;
results[3][1] = 8'b1_0_1_0_0_1_0_1;
results[3][2] = 8'b1_0_1_0_0_1_0_1;
results[3][3] = 8'b0_0_1_1_0_0_1_1;
results[3][4] = 8'b1_1_1_1_0_0_0_0;
results[4][0] = 8'b1_0_1_0_0_1_0_1;
results[4][1] = 8'b1_0_1_0_0_1_0_1;
results[4][2] = 8'b1_0_1_0_0_1_0_1;
results[4][3] = 8'b0_0_0_0_1_1_1_1;
results[4][4] = 8'b0_0_1_1_0_0_1_1;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
logic [7:0] arr [7:0];
logic [7:0] arri [7:0];
has_array am1 (.clk(clk), .arri(arr), .arro(arri));
integer cyc; initial cyc = 0;
initial begin
for (int i = 0; i < 8; i++) begin
arr[i] = 0;
end
end
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5 && arri[1] != 8) begin
$stop;
end
for (int i = 0; i < 7; ++i) begin
arr[i+1] <= arr[i];
end
arr[0] <= arr[0] + 1;
end
endmodule : t
module has_array (
input clk,
input logic [7:0] arri [7:0],
output logic [7:0] arro [7:0]
);
integer cyc; initial cyc = 0;
always @(posedge clk) begin
cyc <= cyc + 1;
if (arri[0] == 10 && cyc == 10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
always @(posedge clk) begin
for (integer i = 0; i < 7; ++i) begin
arro[i+1] <= arro[i];
end
arro[0] = arro[0] + 2;
end
endmodule : has_array
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [63:0] out; // From test of Test.v
// End of automatics
wire reset_l = ~(cyc<15);
wire [63:0] d = crc[63:0];
wire [8:0] t_wa = crc[8:0];
wire [8:0] t_addr = {crc[18:17],3'b0,crc[13:10]};
Test test (/*AUTOINST*/
// Outputs
.out (out[63:0]),
// Inputs
.clk (clk),
.reset_l (reset_l),
.t_wa (t_wa[8:0]),
.d (d[63:0]),
.t_addr (t_addr[8:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h421a41d1541ea652
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, reset_l, t_wa, d, t_addr
);
input clk;
input reset_l;
reg [63:0] m_w0 [47:0];
reg [63:0] m_w1 [23:0];
reg [63:0] m_w2 [23:0];
reg [63:0] m_w3 [23:0];
reg [63:0] m_w4 [23:0];
reg [63:0] m_w5 [23:0];
input [8:0] t_wa;
input [63:0] d;
always @ (posedge clk) begin
if (~reset_l) begin : blk
integer i;
for (i=0; i<48; i=i+1) begin
m_w0[i] <= 64'h0;
end
for (i=0; i<24; i=i+1) begin
m_w1[i] <= 64'h0;
m_w2[i] <= 64'h0;
m_w3[i] <= 64'h0;
m_w4[i] <= 64'h0;
m_w5[i] <= 64'h0;
end
end
else begin
casez (t_wa[8:6])
3'd0: m_w0[t_wa[5:0]] <= d;
3'd1: m_w1[t_wa[4:0]] <= d;
3'd2: m_w2[t_wa[4:0]] <= d;
3'd3: m_w3[t_wa[4:0]] <= d;
3'd4: m_w4[t_wa[4:0]] <= d;
default: m_w5[t_wa[4:0]] <= d;
endcase
end
end
input [8:0] t_addr;
wire [63:0] t_w0 = m_w0[t_addr[5:0]];
wire [63:0] t_w1 = m_w1[t_addr[4:0]];
wire [63:0] t_w2 = m_w2[t_addr[4:0]];
wire [63:0] t_w3 = m_w3[t_addr[4:0]];
wire [63:0] t_w4 = m_w4[t_addr[4:0]];
wire [63:0] t_w5 = m_w5[t_addr[4:0]];
output reg [63:0] out;
always @* begin
casez (t_addr[8:6])
3'd0: out = t_w0;
3'd1: out = t_w1;
3'd2: out = t_w2;
3'd3: out = t_w3;
3'd4: out = t_w4;
default: out = t_w5;
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [63:0] out; // From test of Test.v
// End of automatics
wire reset_l = ~(cyc<15);
wire [63:0] d = crc[63:0];
wire [8:0] t_wa = crc[8:0];
wire [8:0] t_addr = {crc[18:17],3'b0,crc[13:10]};
Test test (/*AUTOINST*/
// Outputs
.out (out[63:0]),
// Inputs
.clk (clk),
.reset_l (reset_l),
.t_wa (t_wa[8:0]),
.d (d[63:0]),
.t_addr (t_addr[8:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h421a41d1541ea652
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, reset_l, t_wa, d, t_addr
);
input clk;
input reset_l;
reg [63:0] m_w0 [47:0];
reg [63:0] m_w1 [23:0];
reg [63:0] m_w2 [23:0];
reg [63:0] m_w3 [23:0];
reg [63:0] m_w4 [23:0];
reg [63:0] m_w5 [23:0];
input [8:0] t_wa;
input [63:0] d;
always @ (posedge clk) begin
if (~reset_l) begin : blk
integer i;
for (i=0; i<48; i=i+1) begin
m_w0[i] <= 64'h0;
end
for (i=0; i<24; i=i+1) begin
m_w1[i] <= 64'h0;
m_w2[i] <= 64'h0;
m_w3[i] <= 64'h0;
m_w4[i] <= 64'h0;
m_w5[i] <= 64'h0;
end
end
else begin
casez (t_wa[8:6])
3'd0: m_w0[t_wa[5:0]] <= d;
3'd1: m_w1[t_wa[4:0]] <= d;
3'd2: m_w2[t_wa[4:0]] <= d;
3'd3: m_w3[t_wa[4:0]] <= d;
3'd4: m_w4[t_wa[4:0]] <= d;
default: m_w5[t_wa[4:0]] <= d;
endcase
end
end
input [8:0] t_addr;
wire [63:0] t_w0 = m_w0[t_addr[5:0]];
wire [63:0] t_w1 = m_w1[t_addr[4:0]];
wire [63:0] t_w2 = m_w2[t_addr[4:0]];
wire [63:0] t_w3 = m_w3[t_addr[4:0]];
wire [63:0] t_w4 = m_w4[t_addr[4:0]];
wire [63:0] t_w5 = m_w5[t_addr[4:0]];
output reg [63:0] out;
always @* begin
casez (t_addr[8:6])
3'd0: out = t_w0;
3'd1: out = t_w1;
3'd2: out = t_w2;
3'd3: out = t_w3;
3'd4: out = t_w4;
default: out = t_w5;
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [63:0] out; // From test of Test.v
// End of automatics
wire reset_l = ~(cyc<15);
wire [63:0] d = crc[63:0];
wire [8:0] t_wa = crc[8:0];
wire [8:0] t_addr = {crc[18:17],3'b0,crc[13:10]};
Test test (/*AUTOINST*/
// Outputs
.out (out[63:0]),
// Inputs
.clk (clk),
.reset_l (reset_l),
.t_wa (t_wa[8:0]),
.d (d[63:0]),
.t_addr (t_addr[8:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h421a41d1541ea652
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, reset_l, t_wa, d, t_addr
);
input clk;
input reset_l;
reg [63:0] m_w0 [47:0];
reg [63:0] m_w1 [23:0];
reg [63:0] m_w2 [23:0];
reg [63:0] m_w3 [23:0];
reg [63:0] m_w4 [23:0];
reg [63:0] m_w5 [23:0];
input [8:0] t_wa;
input [63:0] d;
always @ (posedge clk) begin
if (~reset_l) begin : blk
integer i;
for (i=0; i<48; i=i+1) begin
m_w0[i] <= 64'h0;
end
for (i=0; i<24; i=i+1) begin
m_w1[i] <= 64'h0;
m_w2[i] <= 64'h0;
m_w3[i] <= 64'h0;
m_w4[i] <= 64'h0;
m_w5[i] <= 64'h0;
end
end
else begin
casez (t_wa[8:6])
3'd0: m_w0[t_wa[5:0]] <= d;
3'd1: m_w1[t_wa[4:0]] <= d;
3'd2: m_w2[t_wa[4:0]] <= d;
3'd3: m_w3[t_wa[4:0]] <= d;
3'd4: m_w4[t_wa[4:0]] <= d;
default: m_w5[t_wa[4:0]] <= d;
endcase
end
end
input [8:0] t_addr;
wire [63:0] t_w0 = m_w0[t_addr[5:0]];
wire [63:0] t_w1 = m_w1[t_addr[4:0]];
wire [63:0] t_w2 = m_w2[t_addr[4:0]];
wire [63:0] t_w3 = m_w3[t_addr[4:0]];
wire [63:0] t_w4 = m_w4[t_addr[4:0]];
wire [63:0] t_w5 = m_w5[t_addr[4:0]];
output reg [63:0] out;
always @* begin
casez (t_addr[8:6])
3'd0: out = t_w0;
3'd1: out = t_w1;
3'd2: out = t_w2;
3'd3: out = t_w3;
3'd4: out = t_w4;
default: out = t_w5;
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [63:0] out; // From test of Test.v
// End of automatics
wire reset_l = ~(cyc<15);
wire [63:0] d = crc[63:0];
wire [8:0] t_wa = crc[8:0];
wire [8:0] t_addr = {crc[18:17],3'b0,crc[13:10]};
Test test (/*AUTOINST*/
// Outputs
.out (out[63:0]),
// Inputs
.clk (clk),
.reset_l (reset_l),
.t_wa (t_wa[8:0]),
.d (d[63:0]),
.t_addr (t_addr[8:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h421a41d1541ea652
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, reset_l, t_wa, d, t_addr
);
input clk;
input reset_l;
reg [63:0] m_w0 [47:0];
reg [63:0] m_w1 [23:0];
reg [63:0] m_w2 [23:0];
reg [63:0] m_w3 [23:0];
reg [63:0] m_w4 [23:0];
reg [63:0] m_w5 [23:0];
input [8:0] t_wa;
input [63:0] d;
always @ (posedge clk) begin
if (~reset_l) begin : blk
integer i;
for (i=0; i<48; i=i+1) begin
m_w0[i] <= 64'h0;
end
for (i=0; i<24; i=i+1) begin
m_w1[i] <= 64'h0;
m_w2[i] <= 64'h0;
m_w3[i] <= 64'h0;
m_w4[i] <= 64'h0;
m_w5[i] <= 64'h0;
end
end
else begin
casez (t_wa[8:6])
3'd0: m_w0[t_wa[5:0]] <= d;
3'd1: m_w1[t_wa[4:0]] <= d;
3'd2: m_w2[t_wa[4:0]] <= d;
3'd3: m_w3[t_wa[4:0]] <= d;
3'd4: m_w4[t_wa[4:0]] <= d;
default: m_w5[t_wa[4:0]] <= d;
endcase
end
end
input [8:0] t_addr;
wire [63:0] t_w0 = m_w0[t_addr[5:0]];
wire [63:0] t_w1 = m_w1[t_addr[4:0]];
wire [63:0] t_w2 = m_w2[t_addr[4:0]];
wire [63:0] t_w3 = m_w3[t_addr[4:0]];
wire [63:0] t_w4 = m_w4[t_addr[4:0]];
wire [63:0] t_w5 = m_w5[t_addr[4:0]];
output reg [63:0] out;
always @* begin
casez (t_addr[8:6])
3'd0: out = t_w0;
3'd1: out = t_w1;
3'd2: out = t_w2;
3'd3: out = t_w3;
3'd4: out = t_w4;
default: out = t_w5;
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [31:0] wr_data;
reg wr_en;
wire [31:0] rd_data;
wire [1:0] rd_guards;
wire [1:0] rd_guardsok;
regfile regfile (/*AUTOINST*/
// Outputs
.rd_data (rd_data[31:0]),
.rd_guards (rd_guards[1:0]),
.rd_guardsok (rd_guardsok[1:0]),
// Inputs
.wr_data (wr_data[31:0]),
.wr_en (wr_en),
.clk (clk));
initial wr_en = 0;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
if (!rd_guards[0]) $stop;
if (!rd_guardsok[0]) $stop;
wr_en <= 1'b1;
wr_data <= 32'hfeedf;
end
if (cyc==2) begin
wr_en <= 0;
end
if (cyc==3) begin
wr_en <= 0;
if (rd_data != 32'hfeedf) $stop;
if (rd_guards != 2'b11) $stop;
if (rd_guardsok != 2'b11) $stop;
end
if (cyc==4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module regfile (
input [31:0] wr_data,
input wr_en,
output reg [31:0] rd_data,
output [1:0] rd_guards /*verilator public*/,
output [1:0] rd_guardsok /*verilator public*/,
input clk
);
always @(posedge clk) begin
if (wr_en)
begin
rd_data <= wr_data;
end
end
// this initial statement will induce correct initialize behavior
// initial rd_guards= { 2'b11 };
assign rd_guards= {
rd_data[0],
1'b1
};
assign rd_guardsok[0] = 1'b1;
assign rd_guardsok[1] = rd_data[0];
endmodule // regfile
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [31:0] wr_data;
reg wr_en;
wire [31:0] rd_data;
wire [1:0] rd_guards;
wire [1:0] rd_guardsok;
regfile regfile (/*AUTOINST*/
// Outputs
.rd_data (rd_data[31:0]),
.rd_guards (rd_guards[1:0]),
.rd_guardsok (rd_guardsok[1:0]),
// Inputs
.wr_data (wr_data[31:0]),
.wr_en (wr_en),
.clk (clk));
initial wr_en = 0;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
if (!rd_guards[0]) $stop;
if (!rd_guardsok[0]) $stop;
wr_en <= 1'b1;
wr_data <= 32'hfeedf;
end
if (cyc==2) begin
wr_en <= 0;
end
if (cyc==3) begin
wr_en <= 0;
if (rd_data != 32'hfeedf) $stop;
if (rd_guards != 2'b11) $stop;
if (rd_guardsok != 2'b11) $stop;
end
if (cyc==4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module regfile (
input [31:0] wr_data,
input wr_en,
output reg [31:0] rd_data,
output [1:0] rd_guards /*verilator public*/,
output [1:0] rd_guardsok /*verilator public*/,
input clk
);
always @(posedge clk) begin
if (wr_en)
begin
rd_data <= wr_data;
end
end
// this initial statement will induce correct initialize behavior
// initial rd_guards= { 2'b11 };
assign rd_guards= {
rd_data[0],
1'b1
};
assign rd_guardsok[0] = 1'b1;
assign rd_guardsok[1] = rd_data[0];
endmodule // regfile
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [31:0] wr_data;
reg wr_en;
wire [31:0] rd_data;
wire [1:0] rd_guards;
wire [1:0] rd_guardsok;
regfile regfile (/*AUTOINST*/
// Outputs
.rd_data (rd_data[31:0]),
.rd_guards (rd_guards[1:0]),
.rd_guardsok (rd_guardsok[1:0]),
// Inputs
.wr_data (wr_data[31:0]),
.wr_en (wr_en),
.clk (clk));
initial wr_en = 0;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
if (!rd_guards[0]) $stop;
if (!rd_guardsok[0]) $stop;
wr_en <= 1'b1;
wr_data <= 32'hfeedf;
end
if (cyc==2) begin
wr_en <= 0;
end
if (cyc==3) begin
wr_en <= 0;
if (rd_data != 32'hfeedf) $stop;
if (rd_guards != 2'b11) $stop;
if (rd_guardsok != 2'b11) $stop;
end
if (cyc==4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module regfile (
input [31:0] wr_data,
input wr_en,
output reg [31:0] rd_data,
output [1:0] rd_guards /*verilator public*/,
output [1:0] rd_guardsok /*verilator public*/,
input clk
);
always @(posedge clk) begin
if (wr_en)
begin
rd_data <= wr_data;
end
end
// this initial statement will induce correct initialize behavior
// initial rd_guards= { 2'b11 };
assign rd_guards= {
rd_data[0],
1'b1
};
assign rd_guardsok[0] = 1'b1;
assign rd_guardsok[1] = rd_data[0];
endmodule // regfile
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [31:0] wr_data;
reg wr_en;
wire [31:0] rd_data;
wire [1:0] rd_guards;
wire [1:0] rd_guardsok;
regfile regfile (/*AUTOINST*/
// Outputs
.rd_data (rd_data[31:0]),
.rd_guards (rd_guards[1:0]),
.rd_guardsok (rd_guardsok[1:0]),
// Inputs
.wr_data (wr_data[31:0]),
.wr_en (wr_en),
.clk (clk));
initial wr_en = 0;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
if (!rd_guards[0]) $stop;
if (!rd_guardsok[0]) $stop;
wr_en <= 1'b1;
wr_data <= 32'hfeedf;
end
if (cyc==2) begin
wr_en <= 0;
end
if (cyc==3) begin
wr_en <= 0;
if (rd_data != 32'hfeedf) $stop;
if (rd_guards != 2'b11) $stop;
if (rd_guardsok != 2'b11) $stop;
end
if (cyc==4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module regfile (
input [31:0] wr_data,
input wr_en,
output reg [31:0] rd_data,
output [1:0] rd_guards /*verilator public*/,
output [1:0] rd_guardsok /*verilator public*/,
input clk
);
always @(posedge clk) begin
if (wr_en)
begin
rd_data <= wr_data;
end
end
// this initial statement will induce correct initialize behavior
// initial rd_guards= { 2'b11 };
assign rd_guards= {
rd_data[0],
1'b1
};
assign rd_guardsok[0] = 1'b1;
assign rd_guardsok[1] = rd_data[0];
endmodule // regfile
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
`include "verilated.v"
module t_case_write1_tasks ();
// verilator lint_off WIDTH
// verilator lint_off CASEINCOMPLETE
parameter STRLEN = 78;
task ozonerab;
input [6:0] rab;
inout [STRLEN*8:1] foobar;
// verilator no_inline_task
begin
case (rab[6:0])
7'h00 : foobar = {foobar, " 0"};
7'h01 : foobar = {foobar, " 1"};
7'h02 : foobar = {foobar, " 2"};
7'h03 : foobar = {foobar, " 3"};
7'h04 : foobar = {foobar, " 4"};
7'h05 : foobar = {foobar, " 5"};
7'h06 : foobar = {foobar, " 6"};
7'h07 : foobar = {foobar, " 7"};
7'h08 : foobar = {foobar, " 8"};
7'h09 : foobar = {foobar, " 9"};
7'h0a : foobar = {foobar, " 10"};
7'h0b : foobar = {foobar, " 11"};
7'h0c : foobar = {foobar, " 12"};
7'h0d : foobar = {foobar, " 13"};
7'h0e : foobar = {foobar, " 14"};
7'h0f : foobar = {foobar, " 15"};
7'h10 : foobar = {foobar, " 16"};
7'h11 : foobar = {foobar, " 17"};
7'h12 : foobar = {foobar, " 18"};
7'h13 : foobar = {foobar, " 19"};
7'h14 : foobar = {foobar, " 20"};
7'h15 : foobar = {foobar, " 21"};
7'h16 : foobar = {foobar, " 22"};
7'h17 : foobar = {foobar, " 23"};
7'h18 : foobar = {foobar, " 24"};
7'h19 : foobar = {foobar, " 25"};
7'h1a : foobar = {foobar, " 26"};
7'h1b : foobar = {foobar, " 27"};
7'h1c : foobar = {foobar, " 28"};
7'h1d : foobar = {foobar, " 29"};
7'h1e : foobar = {foobar, " 30"};
7'h1f : foobar = {foobar, " 31"};
7'h20 : foobar = {foobar, " 32"};
7'h21 : foobar = {foobar, " 33"};
7'h22 : foobar = {foobar, " 34"};
7'h23 : foobar = {foobar, " 35"};
7'h24 : foobar = {foobar, " 36"};
7'h25 : foobar = {foobar, " 37"};
7'h26 : foobar = {foobar, " 38"};
7'h27 : foobar = {foobar, " 39"};
7'h28 : foobar = {foobar, " 40"};
7'h29 : foobar = {foobar, " 41"};
7'h2a : foobar = {foobar, " 42"};
7'h2b : foobar = {foobar, " 43"};
7'h2c : foobar = {foobar, " 44"};
7'h2d : foobar = {foobar, " 45"};
7'h2e : foobar = {foobar, " 46"};
7'h2f : foobar = {foobar, " 47"};
7'h30 : foobar = {foobar, " 48"};
7'h31 : foobar = {foobar, " 49"};
7'h32 : foobar = {foobar, " 50"};
7'h33 : foobar = {foobar, " 51"};
7'h34 : foobar = {foobar, " 52"};
7'h35 : foobar = {foobar, " 53"};
7'h36 : foobar = {foobar, " 54"};
7'h37 : foobar = {foobar, " 55"};
7'h38 : foobar = {foobar, " 56"};
7'h39 : foobar = {foobar, " 57"};
7'h3a : foobar = {foobar, " 58"};
7'h3b : foobar = {foobar, " 59"};
7'h3c : foobar = {foobar, " 60"};
7'h3d : foobar = {foobar, " 61"};
7'h3e : foobar = {foobar, " 62"};
7'h3f : foobar = {foobar, " 63"};
7'h40 : foobar = {foobar, " 64"};
7'h41 : foobar = {foobar, " 65"};
7'h42 : foobar = {foobar, " 66"};
7'h43 : foobar = {foobar, " 67"};
7'h44 : foobar = {foobar, " 68"};
7'h45 : foobar = {foobar, " 69"};
7'h46 : foobar = {foobar, " 70"};
7'h47 : foobar = {foobar, " 71"};
7'h48 : foobar = {foobar, " 72"};
7'h49 : foobar = {foobar, " 73"};
7'h4a : foobar = {foobar, " 74"};
7'h4b : foobar = {foobar, " 75"};
7'h4c : foobar = {foobar, " 76"};
7'h4d : foobar = {foobar, " 77"};
7'h4e : foobar = {foobar, " 78"};
7'h4f : foobar = {foobar, " 79"};
7'h50 : foobar = {foobar, " 80"};
7'h51 : foobar = {foobar, " 81"};
7'h52 : foobar = {foobar, " 82"};
7'h53 : foobar = {foobar, " 83"};
7'h54 : foobar = {foobar, " 84"};
7'h55 : foobar = {foobar, " 85"};
7'h56 : foobar = {foobar, " 86"};
7'h57 : foobar = {foobar, " 87"};
7'h58 : foobar = {foobar, " 88"};
7'h59 : foobar = {foobar, " 89"};
7'h5a : foobar = {foobar, " 90"};
7'h5b : foobar = {foobar, " 91"};
7'h5c : foobar = {foobar, " 92"};
7'h5d : foobar = {foobar, " 93"};
7'h5e : foobar = {foobar, " 94"};
7'h5f : foobar = {foobar, " 95"};
7'h60 : foobar = {foobar, " 96"};
7'h61 : foobar = {foobar, " 97"};
7'h62 : foobar = {foobar, " 98"};
7'h63 : foobar = {foobar, " 99"};
7'h64 : foobar = {foobar, " 100"};
7'h65 : foobar = {foobar, " 101"};
7'h66 : foobar = {foobar, " 102"};
7'h67 : foobar = {foobar, " 103"};
7'h68 : foobar = {foobar, " 104"};
7'h69 : foobar = {foobar, " 105"};
7'h6a : foobar = {foobar, " 106"};
7'h6b : foobar = {foobar, " 107"};
7'h6c : foobar = {foobar, " 108"};
7'h6d : foobar = {foobar, " 109"};
7'h6e : foobar = {foobar, " 110"};
7'h6f : foobar = {foobar, " 111"};
7'h70 : foobar = {foobar, " 112"};
7'h71 : foobar = {foobar, " 113"};
7'h72 : foobar = {foobar, " 114"};
7'h73 : foobar = {foobar, " 115"};
7'h74 : foobar = {foobar, " 116"};
7'h75 : foobar = {foobar, " 117"};
7'h76 : foobar = {foobar, " 118"};
7'h77 : foobar = {foobar, " 119"};
7'h78 : foobar = {foobar, " 120"};
7'h79 : foobar = {foobar, " 121"};
7'h7a : foobar = {foobar, " 122"};
7'h7b : foobar = {foobar, " 123"};
7'h7c : foobar = {foobar, " 124"};
7'h7d : foobar = {foobar, " 125"};
7'h7e : foobar = {foobar, " 126"};
7'h7f : foobar = {foobar, " 127"};
default:foobar = {foobar, " 128"};
endcase
end
endtask
task ozonerb;
input [5:0] rb;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (rb[5:0])
6'h10,
6'h17,
6'h1e,
6'h1f: foobar = {foobar, " 129"};
default: ozonerab({1'b1, rb}, foobar);
endcase
end
endtask
task ozonef3f4_iext;
input [1:0] foo;
input [15:0] im16;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo)
2'h0 :
begin
skyway({4{im16[15]}}, foobar);
skyway({4{im16[15]}}, foobar);
skyway(im16[15:12], foobar);
skyway(im16[11: 8], foobar);
skyway(im16[ 7: 4], foobar);
skyway(im16[ 3:0], foobar);
foobar = {foobar, " 130"};
end
2'h1 :
begin
foobar = {foobar, " 131"};
skyway(im16[15:12], foobar);
skyway(im16[11: 8], foobar);
skyway(im16[ 7: 4], foobar);
skyway(im16[ 3:0], foobar);
end
2'h2 :
begin
skyway({4{im16[15]}}, foobar);
skyway({4{im16[15]}}, foobar);
skyway(im16[15:12], foobar);
skyway(im16[11: 8], foobar);
skyway(im16[ 7: 4], foobar);
skyway(im16[ 3:0], foobar);
foobar = {foobar, " 132"};
end
2'h3 :
begin
foobar = {foobar, " 133"};
skyway(im16[15:12], foobar);
skyway(im16[11: 8], foobar);
skyway(im16[ 7: 4], foobar);
skyway(im16[ 3:0], foobar);
end
endcase
end
endtask
task skyway;
input [ 3:0] hex;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (hex)
4'h0 : foobar = {foobar, " 134"};
4'h1 : foobar = {foobar, " 135"};
4'h2 : foobar = {foobar, " 136"};
4'h3 : foobar = {foobar, " 137"};
4'h4 : foobar = {foobar, " 138"};
4'h5 : foobar = {foobar, " 139"};
4'h6 : foobar = {foobar, " 140"};
4'h7 : foobar = {foobar, " 141"};
4'h8 : foobar = {foobar, " 142"};
4'h9 : foobar = {foobar, " 143"};
4'ha : foobar = {foobar, " 144"};
4'hb : foobar = {foobar, " 145"};
4'hc : foobar = {foobar, " 146"};
4'hd : foobar = {foobar, " 147"};
4'he : foobar = {foobar, " 148"};
4'hf : foobar = {foobar, " 149"};
endcase
end
endtask
task ozonesr;
input [ 15:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[11: 9])
3'h0 : foobar = {foobar, " 158"};
3'h1 : foobar = {foobar, " 159"};
3'h2 : foobar = {foobar, " 160"};
3'h3 : foobar = {foobar, " 161"};
3'h4 : foobar = {foobar, " 162"};
3'h5 : foobar = {foobar, " 163"};
3'h6 : foobar = {foobar, " 164"};
3'h7 : foobar = {foobar, " 165"};
endcase
end
endtask
task ozonejk;
input k;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
if (k)
foobar = {foobar, " 166"};
else
foobar = {foobar, " 167"};
end
endtask
task ozoneae;
input [ 2:0] ae;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (ae)
3'b000 : foobar = {foobar, " 168"};
3'b001 : foobar = {foobar, " 169"};
3'b010 : foobar = {foobar, " 170"};
3'b011 : foobar = {foobar, " 171"};
3'b100 : foobar = {foobar, " 172"};
3'b101 : foobar = {foobar, " 173"};
3'b110 : foobar = {foobar, " 174"};
3'b111 : foobar = {foobar, " 175"};
endcase
end
endtask
task ozoneaee;
input [ 2:0] aee;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (aee)
3'b001,
3'b011,
3'b101,
3'b111 : foobar = {foobar, " 176"};
3'b000 : foobar = {foobar, " 177"};
3'b010 : foobar = {foobar, " 178"};
3'b100 : foobar = {foobar, " 179"};
3'b110 : foobar = {foobar, " 180"};
endcase
end
endtask
task ozoneape;
input [ 2:0] ape;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (ape)
3'b001,
3'b011,
3'b101,
3'b111 : foobar = {foobar, " 181"};
3'b000 : foobar = {foobar, " 182"};
3'b010 : foobar = {foobar, " 183"};
3'b100 : foobar = {foobar, " 184"};
3'b110 : foobar = {foobar, " 185"};
endcase
end
endtask
task ozonef1;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[24:21])
4'h0 :
if (foo[26])
foobar = {foobar, " 186"};
else
foobar = {foobar, " 187"};
4'h1 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 188"};
2'b01 : foobar = {foobar, " 189"};
2'b10 : foobar = {foobar, " 190"};
2'b11 : foobar = {foobar, " 191"};
endcase
4'h2 : foobar = {foobar, " 192"};
4'h3 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 193"};
2'b01 : foobar = {foobar, " 194"};
2'b10 : foobar = {foobar, " 195"};
2'b11 : foobar = {foobar, " 196"};
endcase
4'h4 :
if (foo[26])
foobar = {foobar, " 197"};
else
foobar = {foobar, " 198"};
4'h5 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 199"};
2'b01 : foobar = {foobar, " 200"};
2'b10 : foobar = {foobar, " 201"};
2'b11 : foobar = {foobar, " 202"};
endcase
4'h6 : foobar = {foobar, " 203"};
4'h7 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 204"};
2'b01 : foobar = {foobar, " 205"};
2'b10 : foobar = {foobar, " 206"};
2'b11 : foobar = {foobar, " 207"};
endcase
4'h8 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 208"};
2'b01 : foobar = {foobar, " 209"};
2'b10 : foobar = {foobar, " 210"};
2'b11 : foobar = {foobar, " 211"};
endcase
4'h9 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 212"};
2'b01 : foobar = {foobar, " 213"};
2'b10 : foobar = {foobar, " 214"};
2'b11 : foobar = {foobar, " 215"};
endcase
4'ha :
if (foo[25])
foobar = {foobar, " 216"};
else
foobar = {foobar, " 217"};
4'hb :
if (foo[25])
foobar = {foobar, " 218"};
else
foobar = {foobar, " 219"};
4'hc :
if (foo[26])
foobar = {foobar, " 220"};
else
foobar = {foobar, " 221"};
4'hd :
case (foo[26:25])
2'b00 : foobar = {foobar, " 222"};
2'b01 : foobar = {foobar, " 223"};
2'b10 : foobar = {foobar, " 224"};
2'b11 : foobar = {foobar, " 225"};
endcase
4'he :
case (foo[26:25])
2'b00 : foobar = {foobar, " 226"};
2'b01 : foobar = {foobar, " 227"};
2'b10 : foobar = {foobar, " 228"};
2'b11 : foobar = {foobar, " 229"};
endcase
4'hf :
case (foo[26:25])
2'b00 : foobar = {foobar, " 230"};
2'b01 : foobar = {foobar, " 231"};
2'b10 : foobar = {foobar, " 232"};
2'b11 : foobar = {foobar, " 233"};
endcase
endcase
end
endtask
task ozonef1e;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[27:21])
7'h00:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 234"};
foobar = {foobar, " 235"};
end
7'h01:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 236"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 237"};
foobar = {foobar, " 238"};
end
7'h02:
foobar = {foobar, " 239"};
7'h03:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 240"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 241"};
foobar = {foobar, " 242"};
end
7'h04:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 243"};
foobar = {foobar," 244"};
end
7'h05:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 245"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 246"};
end
7'h06:
foobar = {foobar, " 247"};
7'h07:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 248"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 249"};
end
7'h08:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 250"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 251"};
end
7'h09:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 252"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 253"};
end
7'h0a:
begin
ozoneae(foo[17:15], foobar);
foobar = {foobar," 254"};
end
7'h0b:
begin
ozoneae(foo[17:15], foobar);
foobar = {foobar," 255"};
end
7'h0c:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 256"};
end
7'h0d:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 257"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 258"};
end
7'h0e:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 259"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 260"};
end
7'h0f:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 261"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 262"};
end
7'h10:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 263"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 264"};
foobar = {foobar, " 265"};
foobar = {foobar, " 266"};
end
7'h11:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 267"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 268"};
foobar = {foobar, " 269"};
foobar = {foobar, " 270"};
end
7'h12:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 271"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 272"};
foobar = {foobar, " 273"};
foobar = {foobar, " 274"};
end
7'h13:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 275"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 276"};
foobar = {foobar, " 277"};
foobar = {foobar, " 278"};
end
7'h14:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 279"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 280"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 281"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 282"};
foobar = {foobar, " 283"};
foobar = {foobar, " 284"};
end
7'h15:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 285"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 286"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 287"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 288"};
foobar = {foobar, " 289"};
foobar = {foobar, " 290"};
end
7'h16:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 291"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 292"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 293"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 294"};
foobar = {foobar, " 295"};
foobar = {foobar, " 296"};
end
7'h17:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 297"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 298"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 299"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 300"};
foobar = {foobar, " 301"};
foobar = {foobar, " 302"};
end
7'h18:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 303"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 304"};
foobar = {foobar, " 305"};
foobar = {foobar, " 306"};
end
7'h19:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 307"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 308"};
foobar = {foobar, " 309"};
foobar = {foobar, " 310"};
end
7'h1a:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 311"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 312"};
foobar = {foobar, " 313"};
foobar = {foobar, " 314"};
end
7'h1b:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 315"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 316"};
foobar = {foobar, " 317"};
foobar = {foobar, " 318"};
end
7'h1c:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 319"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 320"};
foobar = {foobar, " 321"};
foobar = {foobar, " 322"};
end
7'h1d:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 323"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 324"};
foobar = {foobar, " 325"};
foobar = {foobar, " 326"};
end
7'h1e:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 327"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 328"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 329"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 330"};
foobar = {foobar, " 331"};
foobar = {foobar, " 332"};
end
7'h1f:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 333"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 334"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 335"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 336"};
foobar = {foobar, " 337"};
foobar = {foobar, " 338"};
end
7'h20:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 339"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 340"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 341"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 342"};
foobar = {foobar, " 343"};
foobar = {foobar, " 344"};
end
7'h21:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 345"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 346"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 347"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 348"};
foobar = {foobar, " 349"};
foobar = {foobar, " 350"};
end
7'h22:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 351"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 352"};
foobar = {foobar, " 353"};
foobar = {foobar, " 354"};
end
7'h23:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 355"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 356"};
foobar = {foobar, " 357"};
foobar = {foobar, " 358"};
end
7'h24:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 359"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 360"};
foobar = {foobar, " 361"};
foobar = {foobar, " 362"};
end
7'h25:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 363"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 364"};
foobar = {foobar, " 365"};
foobar = {foobar, " 366"};
end
7'h26:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 367"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 368"};
foobar = {foobar, " 369"};
foobar = {foobar, " 370"};
end
7'h27:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 371"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 372"};
foobar = {foobar, " 373"};
foobar = {foobar, " 374"};
end
7'h28:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 375"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 376"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 377"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 378"};
foobar = {foobar, " 379"};
foobar = {foobar, " 380"};
end
7'h29:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 381"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 382"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 383"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 384"};
foobar = {foobar, " 385"};
foobar = {foobar, " 386"};
end
7'h2a:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 387"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 388"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 389"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 390"};
foobar = {foobar, " 391"};
foobar = {foobar, " 392"};
end
7'h2b:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 393"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 394"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 395"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 396"};
foobar = {foobar, " 397"};
foobar = {foobar, " 398"};
end
7'h2c:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 399"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 400"};
foobar = {foobar, " 401"};
foobar = {foobar, " 402"};
end
7'h2d:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 403"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 404"};
foobar = {foobar, " 405"};
foobar = {foobar, " 406"};
end
7'h2e:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 407"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 408"};
foobar = {foobar, " 409"};
foobar = {foobar, " 410"};
end
7'h2f:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 411"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 412"};
foobar = {foobar, " 413"};
foobar = {foobar, " 414"};
end
7'h30:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 415"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 416"};
foobar = {foobar, " 417"};
foobar = {foobar, " 418"};
end
7'h31:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 419"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 420"};
foobar = {foobar, " 421"};
foobar = {foobar, " 422"};
end
7'h32:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 423"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 424"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 425"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 426"};
foobar = {foobar, " 427"};
foobar = {foobar, " 428"};
end
7'h33:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 429"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 430"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 431"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 432"};
foobar = {foobar, " 433"};
foobar = {foobar, " 434"};
end
7'h34:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 435"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 436"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 437"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 438"};
foobar = {foobar, " 439"};
foobar = {foobar, " 440"};
end
7'h35:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 441"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 442"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 443"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 444"};
foobar = {foobar, " 445"};
foobar = {foobar, " 446"};
end
7'h36:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 447"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 448"};
foobar = {foobar, " 449"};
foobar = {foobar, " 450"};
end
7'h37:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 451"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 452"};
foobar = {foobar, " 453"};
foobar = {foobar, " 454"};
end
7'h38:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 455"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 456"};
foobar = {foobar, " 457"};
end
7'h39:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 458"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 459"};
foobar = {foobar, " 460"};
end
7'h3a:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 461"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 462"};
foobar = {foobar, " 463"};
end
7'h3b:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 464"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 465"};
foobar = {foobar, " 466"};
end
7'h3c:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 467"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 468"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 469"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 470"};
foobar = {foobar, " 471"};
end
7'h3d:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 472"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 473"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 474"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 475"};
foobar = {foobar, " 476"};
end
7'h3e:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 477"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 478"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 479"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 480"};
foobar = {foobar, " 481"};
end
7'h3f:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 482"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 483"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 484"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 485"};
foobar = {foobar, " 486"};
end
7'h40:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 487"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 488"};
foobar = {foobar, " 489"};
foobar = {foobar, " 490"};
end
7'h41:
begin
foobar = {foobar, " 491"};
foobar = {foobar, " 492"};
end
7'h42:
begin
foobar = {foobar, " 493"};
foobar = {foobar, " 494"};
end
7'h43:
begin
foobar = {foobar, " 495"};
foobar = {foobar, " 496"};
end
7'h44:
begin
foobar = {foobar, " 497"};
foobar = {foobar, " 498"};
end
7'h45:
foobar = {foobar, " 499"};
7'h46:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 500"};
foobar = {foobar, " 501"};
foobar = {foobar, " 502"};
end
7'h47:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 503"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 504"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 505"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 506"};
foobar = {foobar, " 507"};
foobar = {foobar, " 508"};
end
7'h48:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 509"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 510"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 511"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 512"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 513"};
end
7'h49:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 514"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 515"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 516"};
end
7'h4a:
foobar = {foobar," 517"};
7'h4b:
foobar = {foobar, " 518"};
7'h4c:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 519"};
foobar = {foobar, " 520"};
foobar = {foobar, " 521"};
end
7'h4d:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 522"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 523"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 524"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 525"};
foobar = {foobar, " 526"};
foobar = {foobar, " 527"};
end
7'h4e:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 528"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 529"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 530"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 531"};
end
7'h4f:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 532"};
end
7'h50:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 533"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 534"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 535"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 536"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 537"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 538"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 539"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 540"};
end
7'h51:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 541"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 542"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 543"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 544"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 545"};
end
7'h52:
foobar = {foobar, " 546"};
7'h53:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 547"};
end
7'h54:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 548"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 549"};
end
7'h55:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 550"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 551"};
end
7'h56:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 552"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 553"};
foobar = {foobar, " 554"};
end
7'h57:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 555"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 556"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 557"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 558"};
end
7'h58:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 559"};
end
7'h59:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 560"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 561"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 562"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 563"};
end
7'h5a:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 564"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 565"};
end
7'h5b:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 566"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 567"};
end
7'h5c:
begin
foobar = {foobar," 568"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 569"};
foobar = {foobar," 570"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 571"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 572"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar, " 573"};
end
7'h5d:
begin
foobar = {foobar," 574"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 575"};
foobar = {foobar," 576"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 577"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 578"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar, " 579"};
end
7'h5e:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 580"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 581"};
end
7'h5f:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 582"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 583"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 584"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 585"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 586"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 587"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 588"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 589"};
end
7'h60:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 590"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 591"};
end
7'h61:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 592"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 593"};
end
7'h62:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 594"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 595"};
end
7'h63:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 596"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 597"};
end
7'h64:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 598"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 599"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 600"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 601"};
end
7'h65:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 602"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 603"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 604"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 605"};
end
7'h66:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 606"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 607"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 608"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 609"};
end
7'h67:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 610"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 611"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 612"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 613"};
end
7'h68:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 614"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 615"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 616"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 617"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 618"};
ozoneape(foo[17:15], foobar);
end
7'h69:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 619"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 620"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 621"};
end
7'h6a:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 622"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 623"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 624"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 625"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 626"};
ozoneae(foo[17:15], foobar);
end
7'h6b:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 627"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 628"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 629"};
end
7'h6c:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 630"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 631"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 632"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 633"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 634"};
ozoneae(foo[17:15], foobar);
end
7'h6d:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 635"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 636"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 637"};
end
7'h6e:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 638"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 639"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 640"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 641"};
end
7'h6f:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 642"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 643"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 644"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 645"};
end
7'h70:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 646"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 647"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 648"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 649"};
end
7'h71:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 650"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 651"};
end
7'h72:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 652"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 653"};
end
7'h73:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 654"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 655"};
ozoneae(foo[17:15], foobar);
end
7'h74:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 656"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 657"};
ozoneae(foo[17:15], foobar);
end
7'h75:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 658"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 659"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 660"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 661"};
foobar = {foobar, " 662"};
foobar = {foobar, " 663"};
end
7'h76:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 664"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 665"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 666"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 667"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 668"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 669"};
end
7'h77:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 670"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 671"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 672"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 673"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 674"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 675"};
end
7'h78,
7'h79,
7'h7a,
7'h7b,
7'h7c,
7'h7d,
7'h7e,
7'h7f:
foobar = {foobar," 676"};
endcase
end
endtask
task ozonef2;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[24:21])
4'h0 :
case (foo[26:25])
2'b00 : foobar = {foobar," 677"};
2'b01 : foobar = {foobar," 678"};
2'b10 : foobar = {foobar," 679"};
2'b11 : foobar = {foobar," 680"};
endcase
4'h1 :
case (foo[26:25])
2'b00 : foobar = {foobar," 681"};
2'b01 : foobar = {foobar," 682"};
2'b10 : foobar = {foobar," 683"};
2'b11 : foobar = {foobar," 684"};
endcase
4'h2 :
case (foo[26:25])
2'b00 : foobar = {foobar," 685"};
2'b01 : foobar = {foobar," 686"};
2'b10 : foobar = {foobar," 687"};
2'b11 : foobar = {foobar," 688"};
endcase
4'h3 :
case (foo[26:25])
2'b00 : foobar = {foobar," 689"};
2'b01 : foobar = {foobar," 690"};
2'b10 : foobar = {foobar," 691"};
2'b11 : foobar = {foobar," 692"};
endcase
4'h4 :
case (foo[26:25])
2'b00 : foobar = {foobar," 693"};
2'b01 : foobar = {foobar," 694"};
2'b10 : foobar = {foobar," 695"};
2'b11 : foobar = {foobar," 696"};
endcase
4'h5 :
case (foo[26:25])
2'b00 : foobar = {foobar," 697"};
2'b01 : foobar = {foobar," 698"};
2'b10 : foobar = {foobar," 699"};
2'b11 : foobar = {foobar," 700"};
endcase
4'h6 :
case (foo[26:25])
2'b00 : foobar = {foobar," 701"};
2'b01 : foobar = {foobar," 702"};
2'b10 : foobar = {foobar," 703"};
2'b11 : foobar = {foobar," 704"};
endcase
4'h7 :
case (foo[26:25])
2'b00 : foobar = {foobar," 705"};
2'b01 : foobar = {foobar," 706"};
2'b10 : foobar = {foobar," 707"};
2'b11 : foobar = {foobar," 708"};
endcase
4'h8 :
if (foo[26])
foobar = {foobar," 709"};
else
foobar = {foobar," 710"};
4'h9 :
case (foo[26:25])
2'b00 : foobar = {foobar," 711"};
2'b01 : foobar = {foobar," 712"};
2'b10 : foobar = {foobar," 713"};
2'b11 : foobar = {foobar," 714"};
endcase
4'ha :
case (foo[26:25])
2'b00 : foobar = {foobar," 715"};
2'b01 : foobar = {foobar," 716"};
2'b10 : foobar = {foobar," 717"};
2'b11 : foobar = {foobar," 718"};
endcase
4'hb :
case (foo[26:25])
2'b00 : foobar = {foobar," 719"};
2'b01 : foobar = {foobar," 720"};
2'b10 : foobar = {foobar," 721"};
2'b11 : foobar = {foobar," 722"};
endcase
4'hc :
if (foo[26])
foobar = {foobar," 723"};
else
foobar = {foobar," 724"};
4'hd :
case (foo[26:25])
2'b00 : foobar = {foobar," 725"};
2'b01 : foobar = {foobar," 726"};
2'b10 : foobar = {foobar," 727"};
2'b11 : foobar = {foobar," 728"};
endcase
4'he :
case (foo[26:25])
2'b00 : foobar = {foobar," 729"};
2'b01 : foobar = {foobar," 730"};
2'b10 : foobar = {foobar," 731"};
2'b11 : foobar = {foobar," 732"};
endcase
4'hf :
case (foo[26:25])
2'b00 : foobar = {foobar," 733"};
2'b01 : foobar = {foobar," 734"};
2'b10 : foobar = {foobar," 735"};
2'b11 : foobar = {foobar," 736"};
endcase
endcase
end
endtask
task ozonef2e;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
casez (foo[25:21])
5'h00 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 737"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 738"};
end
5'h01 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 739"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 740"};
end
5'h02 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 741"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 742"};
end
5'h03 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 743"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 744"};
end
5'h04 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 745"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 746"};
end
5'h05 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 747"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 748"};
end
5'h06 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 749"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 750"};
end
5'h07 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 751"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 752"};
end
5'h08 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 753"};
if (foo[ 6])
foobar = {foobar," 754"};
else
foobar = {foobar," 755"};
end
5'h09 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 756"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 757"};
end
5'h0a :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 758"};
ozoneae(foo[17:15], foobar);
end
5'h0b :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 759"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 760"};
end
5'h0c :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 761"};
end
5'h0d :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 762"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 763"};
end
5'h0e :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 764"};
ozoneae(foo[17:15], foobar);
end
5'h0f :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 765"};
ozoneae(foo[17:15], foobar);
end
5'h10 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 766"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 767"};
end
5'h11 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 768"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 769"};
end
5'h18 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 770"};
if (foo[ 6])
foobar = {foobar," 771"};
else
foobar = {foobar," 772"};
end
5'h1a :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 773"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 774"};
end
5'h1b :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 775"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 776"};
if (foo[ 6])
foobar = {foobar," 777"};
else
foobar = {foobar," 778"};
foobar = {foobar," 779"};
end
5'h1c :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 780"};
end
5'h1d :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 781"};
if (foo[ 6])
foobar = {foobar," 782"};
else
foobar = {foobar," 783"};
foobar = {foobar," 784"};
end
5'h1e :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 785"};
if (foo[ 6])
foobar = {foobar," 786"};
else
foobar = {foobar," 787"};
foobar = {foobar," 788"};
end
5'h1f :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 789"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 790"};
if (foo[ 6])
foobar = {foobar," 791"};
else
foobar = {foobar," 792"};
foobar = {foobar," 793"};
end
default :
foobar = {foobar," 794"};
endcase
end
endtask
task ozonef3e;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[25:21])
5'h00,
5'h01,
5'h02:
begin
ozoneae(foo[20:18], foobar);
case (foo[22:21])
2'h0: foobar = {foobar," 795"};
2'h1: foobar = {foobar," 796"};
2'h2: foobar = {foobar," 797"};
endcase
ozoneae(foo[17:15], foobar);
foobar = {foobar," 798"};
if (foo[ 9])
ozoneae(foo[ 8: 6], foobar);
else
ozonef3e_te(foo[ 8: 6], foobar);
foobar = {foobar," 799"};
end
5'h08,
5'h09,
5'h0d,
5'h0e,
5'h0f:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 800"};
ozoneae(foo[17:15], foobar);
case (foo[23:21])
3'h0: foobar = {foobar," 801"};
3'h1: foobar = {foobar," 802"};
3'h5: foobar = {foobar," 803"};
3'h6: foobar = {foobar," 804"};
3'h7: foobar = {foobar," 805"};
endcase
if (foo[ 9])
ozoneae(foo[ 8: 6], foobar);
else
ozonef3e_te(foo[ 8: 6], foobar);
end
5'h0a,
5'h0b:
begin
ozoneae(foo[17:15], foobar);
if (foo[21])
foobar = {foobar," 806"};
else
foobar = {foobar," 807"};
if (foo[ 9])
ozoneae(foo[ 8: 6], foobar);
else
ozonef3e_te(foo[ 8: 6], foobar);
end
5'h0c:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 808"};
if (foo[ 9])
ozoneae(foo[ 8: 6], foobar);
else
ozonef3e_te(foo[ 8: 6], foobar);
foobar = {foobar," 809"};
ozoneae(foo[17:15], foobar);
end
5'h10,
5'h11,
5'h12,
5'h13:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 810"};
ozoneae(foo[17:15], foobar);
case (foo[22:21])
2'h0,
2'h2:
foobar = {foobar," 811"};
2'h1,
2'h3:
foobar = {foobar," 812"};
endcase
ozoneae(foo[ 8: 6], foobar);
foobar = {foobar," 813"};
ozoneae((foo[20:18]+1), foobar);
foobar = {foobar," 814"};
ozoneae((foo[17:15]+1), foobar);
case (foo[22:21])
2'h0,
2'h3:
foobar = {foobar," 815"};
2'h1,
2'h2:
foobar = {foobar," 816"};
endcase
ozoneae((foo[ 8: 6]+1), foobar);
end
5'h18:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 817"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 818"};
ozoneae(foo[ 8: 6], foobar);
foobar = {foobar," 819"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 820"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 821"};
ozoneae(foo[ 8: 6], foobar);
end
default :
foobar = {foobar," 822"};
endcase
end
endtask
task ozonef3e_te;
input [ 2:0] te;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (te)
3'b100 : foobar = {foobar, " 823"};
3'b101 : foobar = {foobar, " 824"};
3'b110 : foobar = {foobar, " 825"};
default: foobar = {foobar, " 826"};
endcase
end
endtask
task ozonearm;
input [ 2:0] ate;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (ate)
3'b000 : foobar = {foobar, " 827"};
3'b001 : foobar = {foobar, " 828"};
3'b010 : foobar = {foobar, " 829"};
3'b011 : foobar = {foobar, " 830"};
3'b100 : foobar = {foobar, " 831"};
3'b101 : foobar = {foobar, " 832"};
3'b110 : foobar = {foobar, " 833"};
3'b111 : foobar = {foobar, " 834"};
endcase
end
endtask
task ozonebmuop;
input [ 4:0] f4;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (f4[ 4:0])
5'h00,
5'h04 :
foobar = {foobar, " 835"};
5'h01,
5'h05 :
foobar = {foobar, " 836"};
5'h02,
5'h06 :
foobar = {foobar, " 837"};
5'h03,
5'h07 :
foobar = {foobar, " 838"};
5'h08,
5'h18 :
foobar = {foobar, " 839"};
5'h09,
5'h19 :
foobar = {foobar, " 840"};
5'h0a,
5'h1a :
foobar = {foobar, " 841"};
5'h0b :
foobar = {foobar, " 842"};
5'h1b :
foobar = {foobar, " 843"};
5'h0c,
5'h1c :
foobar = {foobar, " 844"};
5'h0d,
5'h1d :
foobar = {foobar, " 845"};
5'h1e :
foobar = {foobar, " 846"};
endcase
end
endtask
task ozonef3;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
reg nacho;
// verilator no_inline_task
begin : f3_body
nacho = 1'b0;
case (foo[24:21])
4'h0:
case (foo[26:25])
2'b00 : foobar = {foobar, " 847"};
2'b01 : foobar = {foobar, " 848"};
2'b10 : foobar = {foobar, " 849"};
2'b11 : foobar = {foobar, " 850"};
endcase
4'h1:
case (foo[26:25])
2'b00 : foobar = {foobar, " 851"};
2'b01 : foobar = {foobar, " 852"};
2'b10 : foobar = {foobar, " 853"};
2'b11 : foobar = {foobar, " 854"};
endcase
4'h2:
case (foo[26:25])
2'b00 : foobar = {foobar, " 855"};
2'b01 : foobar = {foobar, " 856"};
2'b10 : foobar = {foobar, " 857"};
2'b11 : foobar = {foobar, " 858"};
endcase
4'h8,
4'h9,
4'hd,
4'he,
4'hf :
case (foo[26:25])
2'b00 : foobar = {foobar, " 859"};
2'b01 : foobar = {foobar, " 860"};
2'b10 : foobar = {foobar, " 861"};
2'b11 : foobar = {foobar, " 862"};
endcase
4'ha,
4'hb :
if (foo[25])
foobar = {foobar, " 863"};
else
foobar = {foobar, " 864"};
4'hc :
if (foo[26])
foobar = {foobar, " 865"};
else
foobar = {foobar, " 866"};
default :
begin
foobar = {foobar, " 867"};
nacho = 1'b1;
end
endcase
if (~nacho)
begin
case (foo[24:21])
4'h8 :
foobar = {foobar, " 868"};
4'h9 :
foobar = {foobar, " 869"};
4'ha,
4'he :
foobar = {foobar, " 870"};
4'hb,
4'hf :
foobar = {foobar, " 871"};
4'hd :
foobar = {foobar, " 872"};
endcase
if (foo[20])
case (foo[18:16])
3'b000 : foobar = {foobar, " 873"};
3'b100 : foobar = {foobar, " 874"};
default: foobar = {foobar, " 875"};
endcase
else
ozoneae(foo[18:16], foobar);
if (foo[24:21] === 4'hc)
if (foo[25])
foobar = {foobar, " 876"};
else
foobar = {foobar, " 877"};
case (foo[24:21])
4'h0,
4'h1,
4'h2:
foobar = {foobar, " 878"};
endcase
end
end
endtask
task ozonerx;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[19:18])
2'h0 : foobar = {foobar, " 879"};
2'h1 : foobar = {foobar, " 880"};
2'h2 : foobar = {foobar, " 881"};
2'h3 : foobar = {foobar, " 882"};
endcase
case (foo[17:16])
2'h1 : foobar = {foobar, " 883"};
2'h2 : foobar = {foobar, " 884"};
2'h3 : foobar = {foobar, " 885"};
endcase
end
endtask
task ozonerme;
input [ 2:0] rme;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (rme)
3'h0 : foobar = {foobar, " 886"};
3'h1 : foobar = {foobar, " 887"};
3'h2 : foobar = {foobar, " 888"};
3'h3 : foobar = {foobar, " 889"};
3'h4 : foobar = {foobar, " 890"};
3'h5 : foobar = {foobar, " 891"};
3'h6 : foobar = {foobar, " 892"};
3'h7 : foobar = {foobar, " 893"};
endcase
end
endtask
task ozoneye;
input [5:0] ye;
input l;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
foobar = {foobar, " 894"};
ozonerme(ye[5:3],foobar);
case ({ye[ 2:0], l})
4'h2,
4'ha: foobar = {foobar, " 895"};
4'h4,
4'hb: foobar = {foobar, " 896"};
4'h6,
4'he: foobar = {foobar, " 897"};
4'h8,
4'hc: foobar = {foobar, " 898"};
endcase
end
endtask
task ozonef1e_ye;
input [5:0] ye;
input l;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
foobar = {foobar, " 899"};
ozonerme(ye[5:3],foobar);
ozonef1e_inc_dec(ye[5:0], l ,foobar);
end
endtask
task ozonef1e_h;
input [ 2:0] e;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
if (e[ 2:0] <= 3'h4)
foobar = {foobar, " 900"};
end
endtask
task ozonef1e_inc_dec;
input [5:0] ye;
input l;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case ({ye[ 2:0], l})
4'h2,
4'h3,
4'ha: foobar = {foobar, " 901"};
4'h4,
4'h5,
4'hb: foobar = {foobar, " 902"};
4'h6,
4'h7,
4'he: foobar = {foobar, " 903"};
4'h8,
4'h9,
4'hc: foobar = {foobar, " 904"};
4'hf: foobar = {foobar, " 905"};
endcase
end
endtask
task ozonef1e_hl;
input [ 2:0] e;
input l;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case ({e[ 2:0], l})
4'h0,
4'h2,
4'h4,
4'h6,
4'h8: foobar = {foobar, " 906"};
4'h1,
4'h3,
4'h5,
4'h7,
4'h9: foobar = {foobar, " 907"};
endcase
end
endtask
task ozonexe;
input [ 3:0] xe;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (xe[3])
1'b0 : foobar = {foobar, " 908"};
1'b1 : foobar = {foobar, " 909"};
endcase
case (xe[ 2:0])
3'h1,
3'h5: foobar = {foobar, " 910"};
3'h2,
3'h6: foobar = {foobar, " 911"};
3'h3,
3'h7: foobar = {foobar, " 912"};
3'h4: foobar = {foobar, " 913"};
endcase
end
endtask
task ozonerp;
input [ 2:0] rp;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (rp)
3'h0 : foobar = {foobar, " 914"};
3'h1 : foobar = {foobar, " 915"};
3'h2 : foobar = {foobar, " 916"};
3'h3 : foobar = {foobar, " 917"};
3'h4 : foobar = {foobar, " 918"};
3'h5 : foobar = {foobar, " 919"};
3'h6 : foobar = {foobar, " 920"};
3'h7 : foobar = {foobar, " 921"};
endcase
end
endtask
task ozonery;
input [ 3:0] ry;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (ry)
4'h0 : foobar = {foobar, " 922"};
4'h1 : foobar = {foobar, " 923"};
4'h2 : foobar = {foobar, " 924"};
4'h3 : foobar = {foobar, " 925"};
4'h4 : foobar = {foobar, " 926"};
4'h5 : foobar = {foobar, " 927"};
4'h6 : foobar = {foobar, " 928"};
4'h7 : foobar = {foobar, " 929"};
4'h8 : foobar = {foobar, " 930"};
4'h9 : foobar = {foobar, " 931"};
4'ha : foobar = {foobar, " 932"};
4'hb : foobar = {foobar, " 933"};
4'hc : foobar = {foobar, " 934"};
4'hd : foobar = {foobar, " 935"};
4'he : foobar = {foobar, " 936"};
4'hf : foobar = {foobar, " 937"};
endcase
end
endtask
task ozonearx;
input [ 15:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[1:0])
2'h0 : foobar = {foobar, " 938"};
2'h1 : foobar = {foobar, " 939"};
2'h2 : foobar = {foobar, " 940"};
2'h3 : foobar = {foobar, " 941"};
endcase
end
endtask
task ozonef3f4imop;
input [ 4:0] f3f4iml;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
casez (f3f4iml)
5'b000??: foobar = {foobar, " 942"};
5'b001??: foobar = {foobar, " 943"};
5'b?10??: foobar = {foobar, " 944"};
5'b0110?: foobar = {foobar, " 945"};
5'b01110: foobar = {foobar, " 946"};
5'b01111: foobar = {foobar, " 947"};
5'b10???: foobar = {foobar, " 948"};
5'b11100: foobar = {foobar, " 949"};
5'b11101: foobar = {foobar, " 950"};
5'b11110: foobar = {foobar, " 951"};
5'b11111: foobar = {foobar, " 952"};
endcase
end
endtask
task ozonecon;
input [ 4:0] con;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (con)
5'h00 : foobar = {foobar, " 953"};
5'h01 : foobar = {foobar, " 954"};
5'h02 : foobar = {foobar, " 955"};
5'h03 : foobar = {foobar, " 956"};
5'h04 : foobar = {foobar, " 957"};
5'h05 : foobar = {foobar, " 958"};
5'h06 : foobar = {foobar, " 959"};
5'h07 : foobar = {foobar, " 960"};
5'h08 : foobar = {foobar, " 961"};
5'h09 : foobar = {foobar, " 962"};
5'h0a : foobar = {foobar, " 963"};
5'h0b : foobar = {foobar, " 964"};
5'h0c : foobar = {foobar, " 965"};
5'h0d : foobar = {foobar, " 966"};
5'h0e : foobar = {foobar, " 967"};
5'h0f : foobar = {foobar, " 968"};
5'h10 : foobar = {foobar, " 969"};
5'h11 : foobar = {foobar, " 970"};
5'h12 : foobar = {foobar, " 971"};
5'h13 : foobar = {foobar, " 972"};
5'h14 : foobar = {foobar, " 973"};
5'h15 : foobar = {foobar, " 974"};
5'h16 : foobar = {foobar, " 975"};
5'h17 : foobar = {foobar, " 976"};
5'h18 : foobar = {foobar, " 977"};
5'h19 : foobar = {foobar, " 978"};
5'h1a : foobar = {foobar, " 979"};
5'h1b : foobar = {foobar, " 980"};
5'h1c : foobar = {foobar, " 981"};
5'h1d : foobar = {foobar, " 982"};
5'h1e : foobar = {foobar, " 983"};
5'h1f : foobar = {foobar, " 984"};
endcase
end
endtask
task ozonedr;
input [ 15:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[ 9: 6])
4'h0 : foobar = {foobar, " 985"};
4'h1 : foobar = {foobar, " 986"};
4'h2 : foobar = {foobar, " 987"};
4'h3 : foobar = {foobar, " 988"};
4'h4 : foobar = {foobar, " 989"};
4'h5 : foobar = {foobar, " 990"};
4'h6 : foobar = {foobar, " 991"};
4'h7 : foobar = {foobar, " 992"};
4'h8 : foobar = {foobar, " 993"};
4'h9 : foobar = {foobar, " 994"};
4'ha : foobar = {foobar, " 995"};
4'hb : foobar = {foobar, " 996"};
4'hc : foobar = {foobar, " 997"};
4'hd : foobar = {foobar, " 998"};
4'he : foobar = {foobar, " 999"};
4'hf : foobar = {foobar, " 1000"};
endcase
end
endtask
task ozoneshift;
input [ 15:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[ 4: 3])
2'h0 : foobar = {foobar, " 1001"};
2'h1 : foobar = {foobar, " 1002"};
2'h2 : foobar = {foobar, " 1003"};
2'h3 : foobar = {foobar, " 1004"};
endcase
end
endtask
task ozoneacc;
input foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo)
2'h0 : foobar = {foobar, " 1005"};
2'h1 : foobar = {foobar, " 1006"};
endcase
end
endtask
task ozonehl;
input foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo)
2'h0 : foobar = {foobar, " 1007"};
2'h1 : foobar = {foobar, " 1008"};
endcase
end
endtask
task dude;
inout [STRLEN*8: 1] foobar;
reg [ 7:0] temp;
integer i;
reg nacho;
// verilator no_inline_task
begin : justify_block
nacho = 1'b0;
for (i=STRLEN-1; i>1; i=i-1)
begin
temp = foobar>>((STRLEN-1)*8);
if (temp || nacho)
nacho = 1'b1;
else
begin
foobar = foobar<<8;
foobar[8:1] = 32;
end
end
end
endtask
task big_case;
input [ 31:0] fd;
input [ 31:0] foo;
reg [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
foobar = " 1009";
if (&foo === 1'bx)
$fwrite(fd, " 1010");
else
casez ( {foo[31:26], foo[19:15], foo[5:0]} )
17'b00_111?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1011"};
ozoneacc(~foo[26], foobar);
ozonehl(foo[20], foobar);
foobar = {foobar, " 1012"};
ozonerx(foo, foobar);
dude(foobar);
$fwrite (fd, " 1013:%s", foobar);
end
17'b01_001?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1014"};
ozonerx(foo, foobar);
foobar = {foobar, " 1015"};
foobar = {foobar, " 1016"};
ozonehl(foo[20], foobar);
dude(foobar);
$fwrite (fd, " 1017:%s", foobar);
end
17'b10_100?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1018"};
ozonerx(foo, foobar);
foobar = {foobar, " 1019"};
foobar = {foobar, " 1020"};
ozonehl(foo[20], foobar);
dude(foobar);
$fwrite (fd, " 1021:%s", foobar);
end
17'b10_101?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1022"};
if (foo[20])
begin
foobar = {foobar, " 1023"};
ozoneacc(foo[18], foobar);
foobar = {foobar, " 1024"};
foobar = {foobar, " 1025"};
if (foo[19])
foobar = {foobar, " 1026"};
else
foobar = {foobar, " 1027"};
end
else
ozonerx(foo, foobar);
dude(foobar);
$fwrite (fd, " 1028:%s", foobar);
end
17'b10_110?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1029"};
foobar = {foobar, " 1030"};
ozonehl(foo[20], foobar);
foobar = {foobar, " 1031"};
ozonerx(foo, foobar);
dude(foobar);
$fwrite (fd, " 1032:%s", foobar);
end
17'b10_111?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1033"};
foobar = {foobar, " 1034"};
ozonehl(foo[20], foobar);
foobar = {foobar, " 1035"};
ozonerx(foo, foobar);
dude(foobar);
$fwrite (fd, " 1036:%s", foobar);
end
17'b11_001?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1037"};
ozonerx(foo, foobar);
foobar = {foobar, " 1038"};
foobar = {foobar, " 1039"};
ozonehl(foo[20], foobar);
dude(foobar);
$fwrite (fd, " 1040:%s", foobar);
end
17'b11_111?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1041"};
foobar = {foobar, " 1042"};
ozonerx(foo, foobar);
foobar = {foobar, " 1043"};
if (foo[20])
foobar = {foobar, " 1044"};
else
foobar = {foobar, " 1045"};
dude(foobar);
$fwrite (fd, " 1046:%s", foobar);
end
17'b00_10??_?_????_?1_1111 :
casez (foo[11: 5])
7'b??_0_010_0:
begin
foobar = " 1047";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1048"};
ozonef1e(foo, foobar);
dude(foobar);
$fwrite (fd, " 1049:%s", foobar);
end
7'b00_?_110_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1050"};
case ({foo[ 9],foo[ 5]})
2'b00:
begin
foobar = {foobar, " 1051"};
ozoneae(foo[14:12], foobar);
ozonehl(foo[ 5], foobar);
end
2'b01:
begin
foobar = {foobar, " 1052"};
ozoneae(foo[14:12], foobar);
ozonehl(foo[ 5], foobar);
end
2'b10:
begin
foobar = {foobar, " 1053"};
ozoneae(foo[14:12], foobar);
end
2'b11: foobar = {foobar, " 1054"};
endcase
dude(foobar);
$fwrite (fd, " 1055:%s", foobar);
end
7'b01_?_110_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1056"};
case ({foo[ 9],foo[ 5]})
2'b00:
begin
ozoneae(foo[14:12], foobar);
ozonehl(foo[ 5], foobar);
foobar = {foobar, " 1057"};
end
2'b01:
begin
ozoneae(foo[14:12], foobar);
ozonehl(foo[ 5], foobar);
foobar = {foobar, " 1058"};
end
2'b10:
begin
ozoneae(foo[14:12], foobar);
foobar = {foobar, " 1059"};
end
2'b11: foobar = {foobar, " 1060"};
endcase
dude(foobar);
$fwrite (fd, " 1061:%s", foobar);
end
7'b10_0_110_0:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1062"};
foobar = {foobar, " 1063"};
if (foo[12])
foobar = {foobar, " 1064"};
else
ozonerab({4'b1001, foo[14:12]}, foobar);
dude(foobar);
$fwrite (fd, " 1065:%s", foobar);
end
7'b10_0_110_1:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1066"};
if (foo[12])
foobar = {foobar, " 1067"};
else
ozonerab({4'b1001, foo[14:12]}, foobar);
foobar = {foobar, " 1068"};
dude(foobar);
$fwrite (fd, " 1069:%s", foobar);
end
7'b??_?_000_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1070"};
foobar = {foobar, " 1071"};
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
foobar = {foobar, " 1072"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1073:%s", foobar);
end
7'b??_?_100_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1074"};
foobar = {foobar, " 1075"};
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
foobar = {foobar, " 1076"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1077:%s", foobar);
end
7'b??_?_001_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1078"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
foobar = {foobar, " 1079"};
foobar = {foobar, " 1080"};
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1081:%s", foobar);
end
7'b??_?_011_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1082"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
foobar = {foobar, " 1083"};
foobar = {foobar, " 1084"};
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1085:%s", foobar);
end
7'b??_?_101_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1086"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1087:%s", foobar);
end
endcase
17'b00_10??_?_????_?0_0110 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1088"};
ozoneae(foo[ 8: 6], foobar);
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
foobar = {foobar, " 1089"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1090:%s", foobar);
end
17'b00_10??_?_????_00_0111 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1091"};
if (foo[ 6])
foobar = {foobar, " 1092"};
else
ozonerab({4'b1001, foo[ 8: 6]}, foobar);
foobar = {foobar, " 1093"};
foobar = {foobar, " 1094"};
ozonerme(foo[14:12],foobar);
case (foo[11: 9])
3'h2,
3'h5,
3'h6,
3'h7:
ozonef1e_inc_dec(foo[14:9],1'b0,foobar);
3'h1,
3'h3,
3'h4:
foobar = {foobar, " 1095"};
endcase
dude(foobar);
$fwrite (fd, " 1096:%s", foobar);
end
17'b00_10??_?_????_?0_0100 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1097"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
foobar = {foobar, " 1098"};
ozoneae(foo[ 8: 6], foobar);
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1099:%s", foobar);
end
17'b00_10??_?_????_10_0111 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1100"};
foobar = {foobar, " 1101"};
ozonerme(foo[14:12],foobar);
case (foo[11: 9])
3'h2,
3'h5,
3'h6,
3'h7:
ozonef1e_inc_dec(foo[14:9],1'b0,foobar);
3'h1,
3'h3,
3'h4:
foobar = {foobar, " 1102"};
endcase
foobar = {foobar, " 1103"};
if (foo[ 6])
foobar = {foobar, " 1104"};
else
ozonerab({4'b1001, foo[ 8: 6]}, foobar);
dude(foobar);
$fwrite (fd, " 1105:%s", foobar);
end
17'b00_10??_?_????_?0_1110 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1106"};
case (foo[11:9])
3'h2:
begin
foobar = {foobar, " 1107"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1108"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1109"};
end
3'h6:
begin
foobar = {foobar, " 1110"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1111"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1112"};
end
3'h0:
begin
foobar = {foobar, " 1113"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1114"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1115"};
if (foo[ 7: 5] >= 3'h5)
foobar = {foobar, " 1116"};
else
ozonexe(foo[ 8: 5], foobar);
end
3'h1:
begin
foobar = {foobar, " 1117"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1118"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1119"};
if (foo[ 7: 5] >= 3'h5)
foobar = {foobar, " 1120"};
else
ozonexe(foo[ 8: 5], foobar);
end
3'h4:
begin
foobar = {foobar, " 1121"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1122"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1123"};
if (foo[ 7: 5] >= 3'h5)
foobar = {foobar, " 1124"};
else
ozonexe(foo[ 8: 5], foobar);
end
3'h5:
begin
foobar = {foobar, " 1125"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1126"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1127"};
if (foo[ 7: 5] >= 3'h5)
foobar = {foobar, " 1128"};
else
ozonexe(foo[ 8: 5], foobar);
end
endcase
dude(foobar);
$fwrite (fd, " 1129:%s", foobar);
end
17'b00_10??_?_????_?0_1111 :
casez (foo[14: 9])
6'b001_10_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1130"};
foobar = {foobar, " 1131"};
ozonef1e_hl(foo[ 7: 5],foo[ 9],foobar);
foobar = {foobar, " 1132"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1133:%s", foobar);
end
6'b???_11_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1134"};
ozoneae(foo[14:12], foobar);
ozonef1e_hl(foo[ 7: 5],foo[ 9],foobar);
foobar = {foobar, " 1135"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1136:%s", foobar);
end
6'b000_10_1,
6'b010_10_1,
6'b100_10_1,
6'b110_10_1:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1137"};
ozonerab({4'b1001, foo[14:12]}, foobar);
foobar = {foobar, " 1138"};
if ((foo[ 7: 5] >= 3'h1) & (foo[ 7: 5] <= 3'h3))
foobar = {foobar, " 1139"};
else
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1140:%s", foobar);
end
6'b000_10_0,
6'b010_10_0,
6'b100_10_0,
6'b110_10_0:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1141"};
foobar = {foobar, " 1142"};
ozonerab({4'b1001, foo[14:12]}, foobar);
foobar = {foobar, " 1143"};
foobar = {foobar, " 1144"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1145"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1146:%s", foobar);
end
6'b???_00_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1147"};
if (foo[ 9])
begin
foobar = {foobar, " 1148"};
ozoneae(foo[14:12], foobar);
end
else
begin
foobar = {foobar, " 1149"};
ozoneae(foo[14:12], foobar);
foobar = {foobar, " 1150"};
end
foobar = {foobar, " 1151"};
foobar = {foobar, " 1152"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1153"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1154:%s", foobar);
end
6'b???_01_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1155"};
ozoneae(foo[14:12], foobar);
if (foo[ 9])
foobar = {foobar, " 1156"};
else
foobar = {foobar, " 1157"};
foobar = {foobar, " 1158"};
foobar = {foobar, " 1159"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1160"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1161:%s", foobar);
end
6'b011_10_0:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1162"};
case (foo[ 8: 5])
4'h0: foobar = {foobar, " 1163"};
4'h1: foobar = {foobar, " 1164"};
4'h2: foobar = {foobar, " 1165"};
4'h3: foobar = {foobar, " 1166"};
4'h4: foobar = {foobar, " 1167"};
4'h5: foobar = {foobar, " 1168"};
4'h8: foobar = {foobar, " 1169"};
4'h9: foobar = {foobar, " 1170"};
4'ha: foobar = {foobar, " 1171"};
4'hb: foobar = {foobar, " 1172"};
4'hc: foobar = {foobar, " 1173"};
4'hd: foobar = {foobar, " 1174"};
default: foobar = {foobar, " 1175"};
endcase
dude(foobar);
$fwrite (fd, " 1176:%s", foobar);
end
default: foobar = {foobar, " 1177"};
endcase
17'b00_10??_?_????_?0_110? :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1178"};
foobar = {foobar, " 1179"};
ozonef1e_hl(foo[11:9], foo[0], foobar);
foobar = {foobar, " 1180"};
ozonef1e_ye(foo[14:9],1'b0,foobar);
foobar = {foobar, " 1181"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1182"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1183:%s", foobar);
end
17'b00_10??_?_????_?1_110? :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1184"};
foobar = {foobar, " 1185"};
ozonef1e_hl(foo[11:9],foo[0],foobar);
foobar = {foobar, " 1186"};
ozonef1e_ye(foo[14:9],foo[ 0],foobar);
foobar = {foobar, " 1187"};
foobar = {foobar, " 1188"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1189"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1190:%s", foobar);
end
17'b00_10??_?_????_?0_101? :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1191"};
ozonef1e_ye(foo[14:9],foo[ 0],foobar);
foobar = {foobar, " 1192"};
foobar = {foobar, " 1193"};
ozonef1e_hl(foo[11:9],foo[0],foobar);
foobar = {foobar, " 1194"};
foobar = {foobar, " 1195"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1196"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1197:%s", foobar);
end
17'b00_10??_?_????_?0_1001 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1198"};
foobar = {foobar, " 1199"};
ozonef1e_h(foo[11:9],foobar);
foobar = {foobar, " 1200"};
ozonef1e_ye(foo[14:9],1'b0,foobar);
foobar = {foobar, " 1201"};
case (foo[ 7: 5])
3'h1,
3'h2,
3'h3:
foobar = {foobar, " 1202"};
default:
begin
foobar = {foobar, " 1203"};
foobar = {foobar, " 1204"};
ozonexe(foo[ 8: 5], foobar);
end
endcase
dude(foobar);
$fwrite (fd, " 1205:%s", foobar);
end
17'b00_10??_?_????_?0_0101 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1206"};
case (foo[11: 9])
3'h1,
3'h3,
3'h4:
foobar = {foobar, " 1207"};
default:
begin
ozonef1e_ye(foo[14:9],1'b0,foobar);
foobar = {foobar, " 1208"};
foobar = {foobar, " 1209"};
end
endcase
foobar = {foobar, " 1210"};
foobar = {foobar, " 1211"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1212"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1213:%s", foobar);
end
17'b00_10??_?_????_?1_1110 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1214"};
ozonef1e_ye(foo[14:9],1'b0,foobar);
foobar = {foobar, " 1215"};
foobar = {foobar, " 1216"};
ozonef1e_h(foo[11: 9],foobar);
foobar = {foobar, " 1217"};
foobar = {foobar, " 1218"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1219"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1220:%s", foobar);
end
17'b00_10??_?_????_?0_1000 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1221"};
ozonef1e_ye(foo[14:9],1'b0,foobar);
foobar = {foobar, " 1222"};
foobar = {foobar, " 1223"};
ozonef1e_h(foo[11: 9],foobar);
foobar = {foobar, " 1224"};
foobar = {foobar, " 1225"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1226"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1227:%s", foobar);
end
17'b10_01??_?_????_??_???? :
begin
if (foo[27])
foobar = " 1228";
else
foobar = " 1229";
ozonecon(foo[20:16], foobar);
foobar = {foobar, " 1230"};
ozonef2(foo[31:0], foobar);
dude(foobar);
$fwrite (fd, " 1231:%s", foobar);
end
17'b00_1000_?_????_01_0011 :
if (~|foo[ 9: 8])
begin
if (foo[ 7])
foobar = " 1232";
else
foobar = " 1233";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1234"};
ozonef2e(foo[31:0], foobar);
dude(foobar);
$fwrite (fd, " 1235:%s", foobar);
end
else
begin
foobar = " 1236";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1237"};
ozonef3e(foo[31:0], foobar);
dude(foobar);
$fwrite (fd, " 1238:%s", foobar);
end
17'b11_110?_1_????_??_???? :
begin
ozonef3(foo[31:0], foobar);
dude(foobar);
$fwrite(fd, " 1239:%s", foobar);
end
17'b11_110?_0_????_??_???? :
begin : f4_body
casez (foo[24:20])
5'b0_1110,
5'b1_0???,
5'b1_1111:
begin
$fwrite (fd, " 1240");
end
5'b0_00??:
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1241"};
ozoneacc(foo[25], foobar);
ozonebmuop(foo[24:20], foobar);
ozoneae(foo[18:16], foobar);
foobar = {foobar, " 1242"};
dude(foobar);
$fwrite(fd, " 1243:%s", foobar);
end
5'b0_01??:
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1244"};
ozoneacc(foo[25], foobar);
ozonebmuop(foo[24:20], foobar);
ozonearm(foo[18:16], foobar);
dude(foobar);
$fwrite(fd, " 1245:%s", foobar);
end
5'b0_1011:
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1246"};
ozonebmuop(foo[24:20], foobar);
foobar = {foobar, " 1247"};
ozoneae(foo[18:16], foobar);
foobar = {foobar, " 1248"};
dude(foobar);
$fwrite(fd, " 1249:%s", foobar);
end
5'b0_100?,
5'b0_1010,
5'b0_110? :
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1250"};
ozonebmuop(foo[24:20], foobar);
foobar = {foobar, " 1251"};
ozoneacc(foo[25], foobar);
foobar = {foobar, " 1252"};
ozoneae(foo[18:16], foobar);
foobar = {foobar, " 1253"};
dude(foobar);
$fwrite(fd, " 1254:%s", foobar);
end
5'b0_1111 :
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1255"};
ozoneacc(foo[25], foobar);
foobar = {foobar, " 1256"};
ozoneae(foo[18:16], foobar);
dude(foobar);
$fwrite(fd, " 1257:%s", foobar);
end
5'b1_10??,
5'b1_110?,
5'b1_1110 :
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1258"};
ozonebmuop(foo[24:20], foobar);
foobar = {foobar, " 1259"};
ozoneacc(foo[25], foobar);
foobar = {foobar, " 1260"};
ozonearm(foo[18:16], foobar);
foobar = {foobar, " 1261"};
dude(foobar);
$fwrite(fd, " 1262:%s", foobar);
end
endcase
end
17'b11_100?_?_????_??_???? :
casez (foo[23:19])
5'b111??,
5'b0111?:
begin
ozoneae(foo[26:24], foobar);
foobar = {foobar, " 1263"};
ozonef3f4imop(foo[23:19], foobar);
foobar = {foobar, " 1264"};
ozoneae(foo[18:16], foobar);
foobar = {foobar, " 1265"};
skyway(foo[15:12], foobar);
skyway(foo[11: 8], foobar);
skyway(foo[ 7: 4], foobar);
skyway(foo[ 3:0], foobar);
foobar = {foobar, " 1266"};
dude(foobar);
$fwrite(fd, " 1267:%s", foobar);
end
5'b?0???,
5'b110??:
begin
ozoneae(foo[26:24], foobar);
foobar = {foobar, " 1268"};
if (foo[23:21] == 3'b100)
foobar = {foobar, " 1269"};
ozoneae(foo[18:16], foobar);
if (foo[19])
foobar = {foobar, " 1270"};
else
foobar = {foobar, " 1271"};
ozonef3f4imop(foo[23:19], foobar);
foobar = {foobar, " 1272"};
ozonef3f4_iext(foo[20:19], foo[15:0], foobar);
dude(foobar);
$fwrite(fd, " 1273:%s", foobar);
end
5'b010??,
5'b0110?:
begin
ozoneae(foo[18:16], foobar);
if (foo[19])
foobar = {foobar, " 1274"};
else
foobar = {foobar, " 1275"};
ozonef3f4imop(foo[23:19], foobar);
foobar = {foobar, " 1276"};
ozonef3f4_iext(foo[20:19], foo[15:0], foobar);
dude(foobar);
$fwrite(fd, " 1277:%s", foobar);
end
endcase
17'b00_1000_?_????_11_0011 :
begin
foobar = " 1278";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1279"};
casez (foo[25:21])
5'b0_1110,
5'b1_0???,
5'b1_1111:
begin
$fwrite(fd, " 1280");
end
5'b0_00??:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1281"};
ozoneae(foo[17:15], foobar);
ozonebmuop(foo[25:21], foobar);
ozoneae(foo[ 8: 6], foobar);
foobar = {foobar, " 1282"};
dude(foobar);
$fwrite(fd, " 1283:%s", foobar);
end
5'b0_01??:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1284"};
ozoneae(foo[17:15], foobar);
ozonebmuop(foo[25:21], foobar);
ozonearm(foo[ 8: 6], foobar);
dude(foobar);
$fwrite(fd, " 1285:%s", foobar);
end
5'b0_1011:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1286"};
ozonebmuop(foo[25:21], foobar);
foobar = {foobar, " 1287"};
ozoneae(foo[ 8: 6], foobar);
foobar = {foobar, " 1288"};
dude(foobar);
$fwrite(fd, " 1289:%s", foobar);
end
5'b0_100?,
5'b0_1010,
5'b0_110? :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1290"};
ozonebmuop(foo[25:21], foobar);
foobar = {foobar, " 1291"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 1292"};
ozoneae(foo[ 8: 6], foobar);
foobar = {foobar, " 1293"};
dude(foobar);
$fwrite(fd, " 1294:%s", foobar);
end
5'b0_1111 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1295"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 1296"};
ozoneae(foo[ 8: 6], foobar);
dude(foobar);
$fwrite(fd, " 1297:%s", foobar);
end
5'b1_10??,
5'b1_110?,
5'b1_1110 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1298"};
ozonebmuop(foo[25:21], foobar);
foobar = {foobar, " 1299"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 1300"};
ozonearm(foo[ 8: 6], foobar);
foobar = {foobar, " 1301"};
dude(foobar);
$fwrite(fd, " 1302:%s", foobar);
end
endcase
end
17'b00_0010_?_????_??_???? :
begin
$fwrite(fd, " 1304a:%x;%x", foobar, foo[25:20]);
ozonerab({1'b0, foo[25:20]}, foobar);
$fwrite(fd, " 1304b:%x", foobar);
foobar = {foobar, " 1303"};
$fwrite(fd, " 1304c:%x;%x", foobar, foo[19:16]);
skyway(foo[19:16], foobar);
$fwrite(fd, " 1304d:%x", foobar);
dude(foobar);
$fwrite(fd, " 1304e:%x", foobar);
$fwrite(fd, " 1304:%s", foobar);
end
17'b00_01??_?_????_??_???? :
begin
if (foo[27])
begin
foobar = {foobar, " 1305"};
if (foo[26])
foobar = {foobar, " 1306"};
else
foobar = {foobar, " 1307"};
skyway(foo[19:16], foobar);
foobar = {foobar, " 1308"};
ozonerab({1'b0, foo[25:20]}, foobar);
end
else
begin
ozonerab({1'b0, foo[25:20]}, foobar);
foobar = {foobar, " 1309"};
if (foo[26])
foobar = {foobar, " 1310"};
else
foobar = {foobar, " 1311"};
skyway(foo[19:16], foobar);
foobar = {foobar, " 1312"};
end
dude(foobar);
$fwrite(fd, " 1313:%s", foobar);
end
17'b01_000?_?_????_??_???? :
begin
if (foo[26])
begin
ozonerb(foo[25:20], foobar);
foobar = {foobar, " 1314"};
ozoneae(foo[18:16], foobar);
ozonehl(foo[19], foobar);
end
else
begin
ozoneae(foo[18:16], foobar);
ozonehl(foo[19], foobar);
foobar = {foobar, " 1315"};
ozonerb(foo[25:20], foobar);
end
dude(foobar);
$fwrite(fd, " 1316:%s", foobar);
end
17'b01_10??_?_????_??_???? :
begin
if (foo[27])
begin
ozonerab({1'b0, foo[25:20]}, foobar);
foobar = {foobar, " 1317"};
ozonerx(foo, foobar);
end
else
begin
ozonerx(foo, foobar);
foobar = {foobar, " 1318"};
ozonerab({1'b0, foo[25:20]}, foobar);
end
dude(foobar);
$fwrite(fd, " 1319:%s", foobar);
end
17'b11_101?_?_????_??_???? :
begin
ozonerab (foo[26:20], foobar);
foobar = {foobar, " 1320"};
skyway(foo[19:16], foobar);
skyway(foo[15:12], foobar);
skyway(foo[11: 8], foobar);
skyway(foo[ 7: 4], foobar);
skyway(foo[ 3: 0], foobar);
dude(foobar);
$fwrite(fd, " 1321:%s", foobar);
end
17'b11_0000_?_????_??_???? :
begin
casez (foo[25:23])
3'b00?:
begin
ozonerab(foo[22:16], foobar);
foobar = {foobar, " 1322"};
end
3'b01?:
begin
foobar = {foobar, " 1323"};
if (foo[22:16]>=7'h60)
foobar = {foobar, " 1324"};
else
ozonerab(foo[22:16], foobar);
end
3'b110:
foobar = {foobar, " 1325"};
3'b10?:
begin
foobar = {foobar, " 1326"};
if (foo[22:16]>=7'h60)
foobar = {foobar, " 1327"};
else
ozonerab(foo[22:16], foobar);
end
3'b111:
begin
foobar = {foobar, " 1328"};
ozonerab(foo[22:16], foobar);
foobar = {foobar, " 1329"};
end
endcase
dude(foobar);
$fwrite(fd, " 1330:%s", foobar);
end
17'b00_10??_?_????_?1_0000 :
begin
if (foo[27])
begin
foobar = {foobar, " 1331"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1332"};
skyway(foo[19:16], foobar);
skyway({foo[15],foo[11: 9]}, foobar);
skyway(foo[ 8: 5], foobar);
foobar = {foobar, " 1333"};
if (foo[26:20]>=7'h60)
foobar = {foobar, " 1334"};
else
ozonerab(foo[26:20], foobar);
end
else
begin
ozonerab(foo[26:20], foobar);
foobar = {foobar, " 1335"};
foobar = {foobar, " 1336"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1337"};
skyway(foo[19:16], foobar);
skyway({foo[15],foo[11: 9]}, foobar);
skyway(foo[ 8: 5], foobar);
foobar = {foobar, " 1338"};
end
dude(foobar);
$fwrite(fd, " 1339:%s", foobar);
end
17'b00_101?_1_0000_?1_0010 :
if (~|foo[11: 7])
begin
if (foo[ 6])
begin
foobar = {foobar, " 1340"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1341"};
ozonejk(foo[ 5], foobar);
foobar = {foobar, " 1342"};
if (foo[26:20]>=7'h60)
foobar = {foobar, " 1343"};
else
ozonerab(foo[26:20], foobar);
end
else
begin
ozonerab(foo[26:20], foobar);
foobar = {foobar, " 1344"};
foobar = {foobar, " 1345"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1346"};
ozonejk(foo[ 5], foobar);
foobar = {foobar, " 1347"};
end
dude(foobar);
$fwrite(fd, " 1348:%s", foobar);
end
else
$fwrite(fd, " 1349");
17'b00_100?_0_0011_?1_0101 :
if (~|foo[ 8: 7])
begin
if (foo[6])
begin
ozonerab(foo[26:20], foobar);
foobar = {foobar, " 1350"};
ozoneye(foo[14: 9],foo[ 5], foobar);
end
else
begin
ozoneye(foo[14: 9],foo[ 5], foobar);
foobar = {foobar, " 1351"};
if (foo[26:20]>=7'h60)
foobar = {foobar, " 1352"};
else
ozonerab(foo[26:20], foobar);
end
dude(foobar);
$fwrite(fd, " 1353:%s", foobar);
end
else
$fwrite(fd, " 1354");
17'b00_1001_0_0000_?1_0010 :
if (~|foo[25:20])
begin
ozoneye(foo[14: 9],1'b0, foobar);
foobar = {foobar, " 1355"};
ozonef1e_h(foo[11: 9],foobar);
foobar = {foobar, " 1356"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1357"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite(fd, " 1358:%s", foobar);
end
else
$fwrite(fd, " 1359");
17'b00_101?_0_????_?1_0010 :
if (~foo[13])
begin
if (foo[12])
begin
foobar = {foobar, " 1360"};
if (foo[26:20]>=7'h60)
foobar = {foobar, " 1361"};
else
ozonerab(foo[26:20], foobar);
foobar = {foobar, " 1362"};
foobar = {foobar, " 1363"};
skyway({1'b0,foo[18:16]}, foobar);
skyway({foo[15],foo[11: 9]}, foobar);
skyway(foo[ 8: 5], foobar);
dude(foobar);
$fwrite(fd, " 1364:%s", foobar);
end
else
begin
ozonerab(foo[26:20], foobar);
foobar = {foobar, " 1365"};
foobar = {foobar, " 1366"};
skyway({1'b0,foo[18:16]}, foobar);
skyway({foo[15],foo[11: 9]}, foobar);
skyway(foo[ 8: 5], foobar);
dude(foobar);
$fwrite(fd, " 1367:%s", foobar);
end
end
else
$fwrite(fd, " 1368");
17'b01_01??_?_????_??_???? :
begin
ozonerab({1'b0,foo[27:26],foo[19:16]}, foobar);
foobar = {foobar, " 1369"};
ozonerab({1'b0,foo[25:20]}, foobar);
dude(foobar);
$fwrite(fd, " 1370:%s", foobar);
end
17'b00_100?_?_???0_11_0101 :
if (~foo[6])
begin
foobar = " 1371";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1372"};
ozonerab({foo[ 9: 7],foo[19:16]}, foobar);
foobar = {foobar, " 1373"};
ozonerab({foo[26:20]}, foobar);
dude(foobar);
$fwrite(fd, " 1374:%s", foobar);
end
else
$fwrite(fd, " 1375");
17'b00_1000_?_????_?1_0010 :
if (~|foo[25:24])
begin
ozonery(foo[23:20], foobar);
foobar = {foobar, " 1376"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1377"};
skyway(foo[19:16], foobar);
skyway({foo[15],foo[11: 9]}, foobar);
skyway(foo[ 8: 5], foobar);
dude(foobar);
$fwrite(fd, " 1378:%s", foobar);
end
else if ((foo[25:24] == 2'b10) & ~|foo[19:15] & ~|foo[11: 6])
begin
ozonery(foo[23:20], foobar);
foobar = {foobar, " 1379"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1380"};
ozonejk(foo[ 5], foobar);
dude(foobar);
$fwrite(fd, " 1381:%s", foobar);
end
else
$fwrite(fd, " 1382");
17'b11_01??_?_????_??_????,
17'b10_00??_?_????_??_???? :
if (foo[30])
$fwrite(fd, " 1383:%s", foo[27:16]);
else
$fwrite(fd, " 1384:%s", foo[27:16]);
17'b00_10??_?_????_01_1000 :
if (~foo[6])
begin
if (foo[7])
$fwrite(fd, " 1385:%s", foo[27: 8]);
else
$fwrite(fd, " 1386:%s", foo[27: 8]);
end
else
$fwrite(fd, " 1387");
17'b00_10??_?_????_11_1000 :
begin
foobar = " 1388";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1389"};
if (foo[15])
foobar = {foobar, " 1390"};
else
foobar = {foobar, " 1391"};
skyway(foo[27:24], foobar);
skyway(foo[23:20], foobar);
skyway(foo[19:16], foobar);
skyway(foo[ 9: 6], foobar);
dude(foobar);
$fwrite(fd, " 1392:%s", foobar);
end
17'b11_0001_?_????_??_???? :
casez (foo[25:22])
4'b01?? :
begin
foobar = " 1393";
ozonecon(foo[20:16], foobar);
case (foo[23:21])
3'h0 : foobar = {foobar, " 1394"};
3'h1 : foobar = {foobar, " 1395"};
3'h2 : foobar = {foobar, " 1396"};
3'h3 : foobar = {foobar, " 1397"};
3'h4 : foobar = {foobar, " 1398"};
3'h5 : foobar = {foobar, " 1399"};
3'h6 : foobar = {foobar, " 1400"};
3'h7 : foobar = {foobar, " 1401"};
endcase
dude(foobar);
$fwrite(fd, " 1402:%s", foobar);
end
4'b0000 :
$fwrite(fd, " 1403:%s", foo[21:16]);
4'b0010 :
if (~|foo[21:16])
$fwrite(fd, " 1404");
4'b1010 :
if (~|foo[21:17])
begin
if (foo[16])
$fwrite(fd, " 1405");
else
$fwrite(fd, " 1406");
end
default :
$fwrite(fd, " 1407");
endcase
17'b01_11??_?_????_??_???? :
if (foo[27:23] === 5'h00)
$fwrite(fd, " 1408:%s", foo[22:16]);
else
$fwrite(fd, " 1409:%s", foo[22:16]);
default: $fwrite(fd, " 1410");
endcase
end
endtask
//(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\",\",\\4,\");\");" nil nil nil)
//(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\");\");" nil nil nil)
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
`include "verilated.v"
module t_case_write1_tasks ();
// verilator lint_off WIDTH
// verilator lint_off CASEINCOMPLETE
parameter STRLEN = 78;
task ozonerab;
input [6:0] rab;
inout [STRLEN*8:1] foobar;
// verilator no_inline_task
begin
case (rab[6:0])
7'h00 : foobar = {foobar, " 0"};
7'h01 : foobar = {foobar, " 1"};
7'h02 : foobar = {foobar, " 2"};
7'h03 : foobar = {foobar, " 3"};
7'h04 : foobar = {foobar, " 4"};
7'h05 : foobar = {foobar, " 5"};
7'h06 : foobar = {foobar, " 6"};
7'h07 : foobar = {foobar, " 7"};
7'h08 : foobar = {foobar, " 8"};
7'h09 : foobar = {foobar, " 9"};
7'h0a : foobar = {foobar, " 10"};
7'h0b : foobar = {foobar, " 11"};
7'h0c : foobar = {foobar, " 12"};
7'h0d : foobar = {foobar, " 13"};
7'h0e : foobar = {foobar, " 14"};
7'h0f : foobar = {foobar, " 15"};
7'h10 : foobar = {foobar, " 16"};
7'h11 : foobar = {foobar, " 17"};
7'h12 : foobar = {foobar, " 18"};
7'h13 : foobar = {foobar, " 19"};
7'h14 : foobar = {foobar, " 20"};
7'h15 : foobar = {foobar, " 21"};
7'h16 : foobar = {foobar, " 22"};
7'h17 : foobar = {foobar, " 23"};
7'h18 : foobar = {foobar, " 24"};
7'h19 : foobar = {foobar, " 25"};
7'h1a : foobar = {foobar, " 26"};
7'h1b : foobar = {foobar, " 27"};
7'h1c : foobar = {foobar, " 28"};
7'h1d : foobar = {foobar, " 29"};
7'h1e : foobar = {foobar, " 30"};
7'h1f : foobar = {foobar, " 31"};
7'h20 : foobar = {foobar, " 32"};
7'h21 : foobar = {foobar, " 33"};
7'h22 : foobar = {foobar, " 34"};
7'h23 : foobar = {foobar, " 35"};
7'h24 : foobar = {foobar, " 36"};
7'h25 : foobar = {foobar, " 37"};
7'h26 : foobar = {foobar, " 38"};
7'h27 : foobar = {foobar, " 39"};
7'h28 : foobar = {foobar, " 40"};
7'h29 : foobar = {foobar, " 41"};
7'h2a : foobar = {foobar, " 42"};
7'h2b : foobar = {foobar, " 43"};
7'h2c : foobar = {foobar, " 44"};
7'h2d : foobar = {foobar, " 45"};
7'h2e : foobar = {foobar, " 46"};
7'h2f : foobar = {foobar, " 47"};
7'h30 : foobar = {foobar, " 48"};
7'h31 : foobar = {foobar, " 49"};
7'h32 : foobar = {foobar, " 50"};
7'h33 : foobar = {foobar, " 51"};
7'h34 : foobar = {foobar, " 52"};
7'h35 : foobar = {foobar, " 53"};
7'h36 : foobar = {foobar, " 54"};
7'h37 : foobar = {foobar, " 55"};
7'h38 : foobar = {foobar, " 56"};
7'h39 : foobar = {foobar, " 57"};
7'h3a : foobar = {foobar, " 58"};
7'h3b : foobar = {foobar, " 59"};
7'h3c : foobar = {foobar, " 60"};
7'h3d : foobar = {foobar, " 61"};
7'h3e : foobar = {foobar, " 62"};
7'h3f : foobar = {foobar, " 63"};
7'h40 : foobar = {foobar, " 64"};
7'h41 : foobar = {foobar, " 65"};
7'h42 : foobar = {foobar, " 66"};
7'h43 : foobar = {foobar, " 67"};
7'h44 : foobar = {foobar, " 68"};
7'h45 : foobar = {foobar, " 69"};
7'h46 : foobar = {foobar, " 70"};
7'h47 : foobar = {foobar, " 71"};
7'h48 : foobar = {foobar, " 72"};
7'h49 : foobar = {foobar, " 73"};
7'h4a : foobar = {foobar, " 74"};
7'h4b : foobar = {foobar, " 75"};
7'h4c : foobar = {foobar, " 76"};
7'h4d : foobar = {foobar, " 77"};
7'h4e : foobar = {foobar, " 78"};
7'h4f : foobar = {foobar, " 79"};
7'h50 : foobar = {foobar, " 80"};
7'h51 : foobar = {foobar, " 81"};
7'h52 : foobar = {foobar, " 82"};
7'h53 : foobar = {foobar, " 83"};
7'h54 : foobar = {foobar, " 84"};
7'h55 : foobar = {foobar, " 85"};
7'h56 : foobar = {foobar, " 86"};
7'h57 : foobar = {foobar, " 87"};
7'h58 : foobar = {foobar, " 88"};
7'h59 : foobar = {foobar, " 89"};
7'h5a : foobar = {foobar, " 90"};
7'h5b : foobar = {foobar, " 91"};
7'h5c : foobar = {foobar, " 92"};
7'h5d : foobar = {foobar, " 93"};
7'h5e : foobar = {foobar, " 94"};
7'h5f : foobar = {foobar, " 95"};
7'h60 : foobar = {foobar, " 96"};
7'h61 : foobar = {foobar, " 97"};
7'h62 : foobar = {foobar, " 98"};
7'h63 : foobar = {foobar, " 99"};
7'h64 : foobar = {foobar, " 100"};
7'h65 : foobar = {foobar, " 101"};
7'h66 : foobar = {foobar, " 102"};
7'h67 : foobar = {foobar, " 103"};
7'h68 : foobar = {foobar, " 104"};
7'h69 : foobar = {foobar, " 105"};
7'h6a : foobar = {foobar, " 106"};
7'h6b : foobar = {foobar, " 107"};
7'h6c : foobar = {foobar, " 108"};
7'h6d : foobar = {foobar, " 109"};
7'h6e : foobar = {foobar, " 110"};
7'h6f : foobar = {foobar, " 111"};
7'h70 : foobar = {foobar, " 112"};
7'h71 : foobar = {foobar, " 113"};
7'h72 : foobar = {foobar, " 114"};
7'h73 : foobar = {foobar, " 115"};
7'h74 : foobar = {foobar, " 116"};
7'h75 : foobar = {foobar, " 117"};
7'h76 : foobar = {foobar, " 118"};
7'h77 : foobar = {foobar, " 119"};
7'h78 : foobar = {foobar, " 120"};
7'h79 : foobar = {foobar, " 121"};
7'h7a : foobar = {foobar, " 122"};
7'h7b : foobar = {foobar, " 123"};
7'h7c : foobar = {foobar, " 124"};
7'h7d : foobar = {foobar, " 125"};
7'h7e : foobar = {foobar, " 126"};
7'h7f : foobar = {foobar, " 127"};
default:foobar = {foobar, " 128"};
endcase
end
endtask
task ozonerb;
input [5:0] rb;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (rb[5:0])
6'h10,
6'h17,
6'h1e,
6'h1f: foobar = {foobar, " 129"};
default: ozonerab({1'b1, rb}, foobar);
endcase
end
endtask
task ozonef3f4_iext;
input [1:0] foo;
input [15:0] im16;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo)
2'h0 :
begin
skyway({4{im16[15]}}, foobar);
skyway({4{im16[15]}}, foobar);
skyway(im16[15:12], foobar);
skyway(im16[11: 8], foobar);
skyway(im16[ 7: 4], foobar);
skyway(im16[ 3:0], foobar);
foobar = {foobar, " 130"};
end
2'h1 :
begin
foobar = {foobar, " 131"};
skyway(im16[15:12], foobar);
skyway(im16[11: 8], foobar);
skyway(im16[ 7: 4], foobar);
skyway(im16[ 3:0], foobar);
end
2'h2 :
begin
skyway({4{im16[15]}}, foobar);
skyway({4{im16[15]}}, foobar);
skyway(im16[15:12], foobar);
skyway(im16[11: 8], foobar);
skyway(im16[ 7: 4], foobar);
skyway(im16[ 3:0], foobar);
foobar = {foobar, " 132"};
end
2'h3 :
begin
foobar = {foobar, " 133"};
skyway(im16[15:12], foobar);
skyway(im16[11: 8], foobar);
skyway(im16[ 7: 4], foobar);
skyway(im16[ 3:0], foobar);
end
endcase
end
endtask
task skyway;
input [ 3:0] hex;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (hex)
4'h0 : foobar = {foobar, " 134"};
4'h1 : foobar = {foobar, " 135"};
4'h2 : foobar = {foobar, " 136"};
4'h3 : foobar = {foobar, " 137"};
4'h4 : foobar = {foobar, " 138"};
4'h5 : foobar = {foobar, " 139"};
4'h6 : foobar = {foobar, " 140"};
4'h7 : foobar = {foobar, " 141"};
4'h8 : foobar = {foobar, " 142"};
4'h9 : foobar = {foobar, " 143"};
4'ha : foobar = {foobar, " 144"};
4'hb : foobar = {foobar, " 145"};
4'hc : foobar = {foobar, " 146"};
4'hd : foobar = {foobar, " 147"};
4'he : foobar = {foobar, " 148"};
4'hf : foobar = {foobar, " 149"};
endcase
end
endtask
task ozonesr;
input [ 15:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[11: 9])
3'h0 : foobar = {foobar, " 158"};
3'h1 : foobar = {foobar, " 159"};
3'h2 : foobar = {foobar, " 160"};
3'h3 : foobar = {foobar, " 161"};
3'h4 : foobar = {foobar, " 162"};
3'h5 : foobar = {foobar, " 163"};
3'h6 : foobar = {foobar, " 164"};
3'h7 : foobar = {foobar, " 165"};
endcase
end
endtask
task ozonejk;
input k;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
if (k)
foobar = {foobar, " 166"};
else
foobar = {foobar, " 167"};
end
endtask
task ozoneae;
input [ 2:0] ae;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (ae)
3'b000 : foobar = {foobar, " 168"};
3'b001 : foobar = {foobar, " 169"};
3'b010 : foobar = {foobar, " 170"};
3'b011 : foobar = {foobar, " 171"};
3'b100 : foobar = {foobar, " 172"};
3'b101 : foobar = {foobar, " 173"};
3'b110 : foobar = {foobar, " 174"};
3'b111 : foobar = {foobar, " 175"};
endcase
end
endtask
task ozoneaee;
input [ 2:0] aee;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (aee)
3'b001,
3'b011,
3'b101,
3'b111 : foobar = {foobar, " 176"};
3'b000 : foobar = {foobar, " 177"};
3'b010 : foobar = {foobar, " 178"};
3'b100 : foobar = {foobar, " 179"};
3'b110 : foobar = {foobar, " 180"};
endcase
end
endtask
task ozoneape;
input [ 2:0] ape;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (ape)
3'b001,
3'b011,
3'b101,
3'b111 : foobar = {foobar, " 181"};
3'b000 : foobar = {foobar, " 182"};
3'b010 : foobar = {foobar, " 183"};
3'b100 : foobar = {foobar, " 184"};
3'b110 : foobar = {foobar, " 185"};
endcase
end
endtask
task ozonef1;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[24:21])
4'h0 :
if (foo[26])
foobar = {foobar, " 186"};
else
foobar = {foobar, " 187"};
4'h1 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 188"};
2'b01 : foobar = {foobar, " 189"};
2'b10 : foobar = {foobar, " 190"};
2'b11 : foobar = {foobar, " 191"};
endcase
4'h2 : foobar = {foobar, " 192"};
4'h3 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 193"};
2'b01 : foobar = {foobar, " 194"};
2'b10 : foobar = {foobar, " 195"};
2'b11 : foobar = {foobar, " 196"};
endcase
4'h4 :
if (foo[26])
foobar = {foobar, " 197"};
else
foobar = {foobar, " 198"};
4'h5 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 199"};
2'b01 : foobar = {foobar, " 200"};
2'b10 : foobar = {foobar, " 201"};
2'b11 : foobar = {foobar, " 202"};
endcase
4'h6 : foobar = {foobar, " 203"};
4'h7 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 204"};
2'b01 : foobar = {foobar, " 205"};
2'b10 : foobar = {foobar, " 206"};
2'b11 : foobar = {foobar, " 207"};
endcase
4'h8 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 208"};
2'b01 : foobar = {foobar, " 209"};
2'b10 : foobar = {foobar, " 210"};
2'b11 : foobar = {foobar, " 211"};
endcase
4'h9 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 212"};
2'b01 : foobar = {foobar, " 213"};
2'b10 : foobar = {foobar, " 214"};
2'b11 : foobar = {foobar, " 215"};
endcase
4'ha :
if (foo[25])
foobar = {foobar, " 216"};
else
foobar = {foobar, " 217"};
4'hb :
if (foo[25])
foobar = {foobar, " 218"};
else
foobar = {foobar, " 219"};
4'hc :
if (foo[26])
foobar = {foobar, " 220"};
else
foobar = {foobar, " 221"};
4'hd :
case (foo[26:25])
2'b00 : foobar = {foobar, " 222"};
2'b01 : foobar = {foobar, " 223"};
2'b10 : foobar = {foobar, " 224"};
2'b11 : foobar = {foobar, " 225"};
endcase
4'he :
case (foo[26:25])
2'b00 : foobar = {foobar, " 226"};
2'b01 : foobar = {foobar, " 227"};
2'b10 : foobar = {foobar, " 228"};
2'b11 : foobar = {foobar, " 229"};
endcase
4'hf :
case (foo[26:25])
2'b00 : foobar = {foobar, " 230"};
2'b01 : foobar = {foobar, " 231"};
2'b10 : foobar = {foobar, " 232"};
2'b11 : foobar = {foobar, " 233"};
endcase
endcase
end
endtask
task ozonef1e;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[27:21])
7'h00:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 234"};
foobar = {foobar, " 235"};
end
7'h01:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 236"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 237"};
foobar = {foobar, " 238"};
end
7'h02:
foobar = {foobar, " 239"};
7'h03:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 240"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 241"};
foobar = {foobar, " 242"};
end
7'h04:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 243"};
foobar = {foobar," 244"};
end
7'h05:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 245"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 246"};
end
7'h06:
foobar = {foobar, " 247"};
7'h07:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 248"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 249"};
end
7'h08:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 250"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 251"};
end
7'h09:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 252"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 253"};
end
7'h0a:
begin
ozoneae(foo[17:15], foobar);
foobar = {foobar," 254"};
end
7'h0b:
begin
ozoneae(foo[17:15], foobar);
foobar = {foobar," 255"};
end
7'h0c:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 256"};
end
7'h0d:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 257"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 258"};
end
7'h0e:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 259"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 260"};
end
7'h0f:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 261"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 262"};
end
7'h10:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 263"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 264"};
foobar = {foobar, " 265"};
foobar = {foobar, " 266"};
end
7'h11:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 267"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 268"};
foobar = {foobar, " 269"};
foobar = {foobar, " 270"};
end
7'h12:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 271"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 272"};
foobar = {foobar, " 273"};
foobar = {foobar, " 274"};
end
7'h13:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 275"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 276"};
foobar = {foobar, " 277"};
foobar = {foobar, " 278"};
end
7'h14:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 279"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 280"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 281"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 282"};
foobar = {foobar, " 283"};
foobar = {foobar, " 284"};
end
7'h15:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 285"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 286"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 287"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 288"};
foobar = {foobar, " 289"};
foobar = {foobar, " 290"};
end
7'h16:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 291"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 292"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 293"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 294"};
foobar = {foobar, " 295"};
foobar = {foobar, " 296"};
end
7'h17:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 297"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 298"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 299"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 300"};
foobar = {foobar, " 301"};
foobar = {foobar, " 302"};
end
7'h18:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 303"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 304"};
foobar = {foobar, " 305"};
foobar = {foobar, " 306"};
end
7'h19:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 307"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 308"};
foobar = {foobar, " 309"};
foobar = {foobar, " 310"};
end
7'h1a:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 311"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 312"};
foobar = {foobar, " 313"};
foobar = {foobar, " 314"};
end
7'h1b:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 315"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 316"};
foobar = {foobar, " 317"};
foobar = {foobar, " 318"};
end
7'h1c:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 319"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 320"};
foobar = {foobar, " 321"};
foobar = {foobar, " 322"};
end
7'h1d:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 323"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 324"};
foobar = {foobar, " 325"};
foobar = {foobar, " 326"};
end
7'h1e:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 327"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 328"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 329"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 330"};
foobar = {foobar, " 331"};
foobar = {foobar, " 332"};
end
7'h1f:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 333"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 334"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 335"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 336"};
foobar = {foobar, " 337"};
foobar = {foobar, " 338"};
end
7'h20:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 339"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 340"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 341"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 342"};
foobar = {foobar, " 343"};
foobar = {foobar, " 344"};
end
7'h21:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 345"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 346"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 347"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 348"};
foobar = {foobar, " 349"};
foobar = {foobar, " 350"};
end
7'h22:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 351"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 352"};
foobar = {foobar, " 353"};
foobar = {foobar, " 354"};
end
7'h23:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 355"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 356"};
foobar = {foobar, " 357"};
foobar = {foobar, " 358"};
end
7'h24:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 359"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 360"};
foobar = {foobar, " 361"};
foobar = {foobar, " 362"};
end
7'h25:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 363"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 364"};
foobar = {foobar, " 365"};
foobar = {foobar, " 366"};
end
7'h26:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 367"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 368"};
foobar = {foobar, " 369"};
foobar = {foobar, " 370"};
end
7'h27:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 371"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 372"};
foobar = {foobar, " 373"};
foobar = {foobar, " 374"};
end
7'h28:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 375"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 376"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 377"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 378"};
foobar = {foobar, " 379"};
foobar = {foobar, " 380"};
end
7'h29:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 381"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 382"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 383"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 384"};
foobar = {foobar, " 385"};
foobar = {foobar, " 386"};
end
7'h2a:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 387"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 388"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 389"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 390"};
foobar = {foobar, " 391"};
foobar = {foobar, " 392"};
end
7'h2b:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 393"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 394"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 395"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 396"};
foobar = {foobar, " 397"};
foobar = {foobar, " 398"};
end
7'h2c:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 399"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 400"};
foobar = {foobar, " 401"};
foobar = {foobar, " 402"};
end
7'h2d:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 403"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 404"};
foobar = {foobar, " 405"};
foobar = {foobar, " 406"};
end
7'h2e:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 407"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 408"};
foobar = {foobar, " 409"};
foobar = {foobar, " 410"};
end
7'h2f:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 411"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 412"};
foobar = {foobar, " 413"};
foobar = {foobar, " 414"};
end
7'h30:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 415"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 416"};
foobar = {foobar, " 417"};
foobar = {foobar, " 418"};
end
7'h31:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 419"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 420"};
foobar = {foobar, " 421"};
foobar = {foobar, " 422"};
end
7'h32:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 423"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 424"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 425"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 426"};
foobar = {foobar, " 427"};
foobar = {foobar, " 428"};
end
7'h33:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 429"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 430"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 431"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 432"};
foobar = {foobar, " 433"};
foobar = {foobar, " 434"};
end
7'h34:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 435"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 436"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 437"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 438"};
foobar = {foobar, " 439"};
foobar = {foobar, " 440"};
end
7'h35:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 441"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 442"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 443"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 444"};
foobar = {foobar, " 445"};
foobar = {foobar, " 446"};
end
7'h36:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 447"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 448"};
foobar = {foobar, " 449"};
foobar = {foobar, " 450"};
end
7'h37:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 451"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 452"};
foobar = {foobar, " 453"};
foobar = {foobar, " 454"};
end
7'h38:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 455"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 456"};
foobar = {foobar, " 457"};
end
7'h39:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 458"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 459"};
foobar = {foobar, " 460"};
end
7'h3a:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 461"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 462"};
foobar = {foobar, " 463"};
end
7'h3b:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 464"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 465"};
foobar = {foobar, " 466"};
end
7'h3c:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 467"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 468"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 469"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 470"};
foobar = {foobar, " 471"};
end
7'h3d:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 472"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 473"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 474"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 475"};
foobar = {foobar, " 476"};
end
7'h3e:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 477"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 478"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 479"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 480"};
foobar = {foobar, " 481"};
end
7'h3f:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 482"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 483"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 484"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 485"};
foobar = {foobar, " 486"};
end
7'h40:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 487"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 488"};
foobar = {foobar, " 489"};
foobar = {foobar, " 490"};
end
7'h41:
begin
foobar = {foobar, " 491"};
foobar = {foobar, " 492"};
end
7'h42:
begin
foobar = {foobar, " 493"};
foobar = {foobar, " 494"};
end
7'h43:
begin
foobar = {foobar, " 495"};
foobar = {foobar, " 496"};
end
7'h44:
begin
foobar = {foobar, " 497"};
foobar = {foobar, " 498"};
end
7'h45:
foobar = {foobar, " 499"};
7'h46:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 500"};
foobar = {foobar, " 501"};
foobar = {foobar, " 502"};
end
7'h47:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 503"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 504"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 505"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 506"};
foobar = {foobar, " 507"};
foobar = {foobar, " 508"};
end
7'h48:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 509"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 510"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 511"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 512"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 513"};
end
7'h49:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 514"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 515"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 516"};
end
7'h4a:
foobar = {foobar," 517"};
7'h4b:
foobar = {foobar, " 518"};
7'h4c:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 519"};
foobar = {foobar, " 520"};
foobar = {foobar, " 521"};
end
7'h4d:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 522"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 523"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 524"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 525"};
foobar = {foobar, " 526"};
foobar = {foobar, " 527"};
end
7'h4e:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 528"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 529"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 530"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 531"};
end
7'h4f:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 532"};
end
7'h50:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 533"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 534"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 535"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 536"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 537"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 538"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 539"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 540"};
end
7'h51:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 541"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 542"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 543"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 544"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 545"};
end
7'h52:
foobar = {foobar, " 546"};
7'h53:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 547"};
end
7'h54:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 548"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 549"};
end
7'h55:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 550"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 551"};
end
7'h56:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 552"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 553"};
foobar = {foobar, " 554"};
end
7'h57:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 555"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 556"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 557"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 558"};
end
7'h58:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 559"};
end
7'h59:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 560"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 561"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 562"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 563"};
end
7'h5a:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 564"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 565"};
end
7'h5b:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 566"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 567"};
end
7'h5c:
begin
foobar = {foobar," 568"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 569"};
foobar = {foobar," 570"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 571"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 572"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar, " 573"};
end
7'h5d:
begin
foobar = {foobar," 574"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 575"};
foobar = {foobar," 576"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 577"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 578"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar, " 579"};
end
7'h5e:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 580"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 581"};
end
7'h5f:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 582"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 583"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 584"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 585"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 586"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 587"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 588"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 589"};
end
7'h60:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 590"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 591"};
end
7'h61:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 592"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 593"};
end
7'h62:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 594"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 595"};
end
7'h63:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 596"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 597"};
end
7'h64:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 598"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 599"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 600"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 601"};
end
7'h65:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 602"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 603"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 604"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 605"};
end
7'h66:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 606"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 607"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 608"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 609"};
end
7'h67:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 610"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 611"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 612"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 613"};
end
7'h68:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 614"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 615"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 616"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 617"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 618"};
ozoneape(foo[17:15], foobar);
end
7'h69:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 619"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 620"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 621"};
end
7'h6a:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 622"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 623"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 624"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 625"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 626"};
ozoneae(foo[17:15], foobar);
end
7'h6b:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 627"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 628"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 629"};
end
7'h6c:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 630"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 631"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 632"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 633"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 634"};
ozoneae(foo[17:15], foobar);
end
7'h6d:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 635"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 636"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 637"};
end
7'h6e:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 638"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 639"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 640"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 641"};
end
7'h6f:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 642"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 643"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 644"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 645"};
end
7'h70:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 646"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 647"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 648"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 649"};
end
7'h71:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 650"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 651"};
end
7'h72:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 652"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 653"};
end
7'h73:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 654"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 655"};
ozoneae(foo[17:15], foobar);
end
7'h74:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 656"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 657"};
ozoneae(foo[17:15], foobar);
end
7'h75:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 658"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 659"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 660"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 661"};
foobar = {foobar, " 662"};
foobar = {foobar, " 663"};
end
7'h76:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 664"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 665"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 666"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 667"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 668"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 669"};
end
7'h77:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 670"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 671"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 672"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 673"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 674"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 675"};
end
7'h78,
7'h79,
7'h7a,
7'h7b,
7'h7c,
7'h7d,
7'h7e,
7'h7f:
foobar = {foobar," 676"};
endcase
end
endtask
task ozonef2;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[24:21])
4'h0 :
case (foo[26:25])
2'b00 : foobar = {foobar," 677"};
2'b01 : foobar = {foobar," 678"};
2'b10 : foobar = {foobar," 679"};
2'b11 : foobar = {foobar," 680"};
endcase
4'h1 :
case (foo[26:25])
2'b00 : foobar = {foobar," 681"};
2'b01 : foobar = {foobar," 682"};
2'b10 : foobar = {foobar," 683"};
2'b11 : foobar = {foobar," 684"};
endcase
4'h2 :
case (foo[26:25])
2'b00 : foobar = {foobar," 685"};
2'b01 : foobar = {foobar," 686"};
2'b10 : foobar = {foobar," 687"};
2'b11 : foobar = {foobar," 688"};
endcase
4'h3 :
case (foo[26:25])
2'b00 : foobar = {foobar," 689"};
2'b01 : foobar = {foobar," 690"};
2'b10 : foobar = {foobar," 691"};
2'b11 : foobar = {foobar," 692"};
endcase
4'h4 :
case (foo[26:25])
2'b00 : foobar = {foobar," 693"};
2'b01 : foobar = {foobar," 694"};
2'b10 : foobar = {foobar," 695"};
2'b11 : foobar = {foobar," 696"};
endcase
4'h5 :
case (foo[26:25])
2'b00 : foobar = {foobar," 697"};
2'b01 : foobar = {foobar," 698"};
2'b10 : foobar = {foobar," 699"};
2'b11 : foobar = {foobar," 700"};
endcase
4'h6 :
case (foo[26:25])
2'b00 : foobar = {foobar," 701"};
2'b01 : foobar = {foobar," 702"};
2'b10 : foobar = {foobar," 703"};
2'b11 : foobar = {foobar," 704"};
endcase
4'h7 :
case (foo[26:25])
2'b00 : foobar = {foobar," 705"};
2'b01 : foobar = {foobar," 706"};
2'b10 : foobar = {foobar," 707"};
2'b11 : foobar = {foobar," 708"};
endcase
4'h8 :
if (foo[26])
foobar = {foobar," 709"};
else
foobar = {foobar," 710"};
4'h9 :
case (foo[26:25])
2'b00 : foobar = {foobar," 711"};
2'b01 : foobar = {foobar," 712"};
2'b10 : foobar = {foobar," 713"};
2'b11 : foobar = {foobar," 714"};
endcase
4'ha :
case (foo[26:25])
2'b00 : foobar = {foobar," 715"};
2'b01 : foobar = {foobar," 716"};
2'b10 : foobar = {foobar," 717"};
2'b11 : foobar = {foobar," 718"};
endcase
4'hb :
case (foo[26:25])
2'b00 : foobar = {foobar," 719"};
2'b01 : foobar = {foobar," 720"};
2'b10 : foobar = {foobar," 721"};
2'b11 : foobar = {foobar," 722"};
endcase
4'hc :
if (foo[26])
foobar = {foobar," 723"};
else
foobar = {foobar," 724"};
4'hd :
case (foo[26:25])
2'b00 : foobar = {foobar," 725"};
2'b01 : foobar = {foobar," 726"};
2'b10 : foobar = {foobar," 727"};
2'b11 : foobar = {foobar," 728"};
endcase
4'he :
case (foo[26:25])
2'b00 : foobar = {foobar," 729"};
2'b01 : foobar = {foobar," 730"};
2'b10 : foobar = {foobar," 731"};
2'b11 : foobar = {foobar," 732"};
endcase
4'hf :
case (foo[26:25])
2'b00 : foobar = {foobar," 733"};
2'b01 : foobar = {foobar," 734"};
2'b10 : foobar = {foobar," 735"};
2'b11 : foobar = {foobar," 736"};
endcase
endcase
end
endtask
task ozonef2e;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
casez (foo[25:21])
5'h00 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 737"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 738"};
end
5'h01 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 739"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 740"};
end
5'h02 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 741"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 742"};
end
5'h03 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 743"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 744"};
end
5'h04 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 745"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 746"};
end
5'h05 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 747"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 748"};
end
5'h06 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 749"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 750"};
end
5'h07 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 751"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 752"};
end
5'h08 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 753"};
if (foo[ 6])
foobar = {foobar," 754"};
else
foobar = {foobar," 755"};
end
5'h09 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 756"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 757"};
end
5'h0a :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 758"};
ozoneae(foo[17:15], foobar);
end
5'h0b :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 759"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 760"};
end
5'h0c :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 761"};
end
5'h0d :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 762"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 763"};
end
5'h0e :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 764"};
ozoneae(foo[17:15], foobar);
end
5'h0f :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 765"};
ozoneae(foo[17:15], foobar);
end
5'h10 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 766"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 767"};
end
5'h11 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 768"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 769"};
end
5'h18 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 770"};
if (foo[ 6])
foobar = {foobar," 771"};
else
foobar = {foobar," 772"};
end
5'h1a :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 773"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 774"};
end
5'h1b :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 775"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 776"};
if (foo[ 6])
foobar = {foobar," 777"};
else
foobar = {foobar," 778"};
foobar = {foobar," 779"};
end
5'h1c :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 780"};
end
5'h1d :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 781"};
if (foo[ 6])
foobar = {foobar," 782"};
else
foobar = {foobar," 783"};
foobar = {foobar," 784"};
end
5'h1e :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 785"};
if (foo[ 6])
foobar = {foobar," 786"};
else
foobar = {foobar," 787"};
foobar = {foobar," 788"};
end
5'h1f :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 789"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 790"};
if (foo[ 6])
foobar = {foobar," 791"};
else
foobar = {foobar," 792"};
foobar = {foobar," 793"};
end
default :
foobar = {foobar," 794"};
endcase
end
endtask
task ozonef3e;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[25:21])
5'h00,
5'h01,
5'h02:
begin
ozoneae(foo[20:18], foobar);
case (foo[22:21])
2'h0: foobar = {foobar," 795"};
2'h1: foobar = {foobar," 796"};
2'h2: foobar = {foobar," 797"};
endcase
ozoneae(foo[17:15], foobar);
foobar = {foobar," 798"};
if (foo[ 9])
ozoneae(foo[ 8: 6], foobar);
else
ozonef3e_te(foo[ 8: 6], foobar);
foobar = {foobar," 799"};
end
5'h08,
5'h09,
5'h0d,
5'h0e,
5'h0f:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 800"};
ozoneae(foo[17:15], foobar);
case (foo[23:21])
3'h0: foobar = {foobar," 801"};
3'h1: foobar = {foobar," 802"};
3'h5: foobar = {foobar," 803"};
3'h6: foobar = {foobar," 804"};
3'h7: foobar = {foobar," 805"};
endcase
if (foo[ 9])
ozoneae(foo[ 8: 6], foobar);
else
ozonef3e_te(foo[ 8: 6], foobar);
end
5'h0a,
5'h0b:
begin
ozoneae(foo[17:15], foobar);
if (foo[21])
foobar = {foobar," 806"};
else
foobar = {foobar," 807"};
if (foo[ 9])
ozoneae(foo[ 8: 6], foobar);
else
ozonef3e_te(foo[ 8: 6], foobar);
end
5'h0c:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 808"};
if (foo[ 9])
ozoneae(foo[ 8: 6], foobar);
else
ozonef3e_te(foo[ 8: 6], foobar);
foobar = {foobar," 809"};
ozoneae(foo[17:15], foobar);
end
5'h10,
5'h11,
5'h12,
5'h13:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 810"};
ozoneae(foo[17:15], foobar);
case (foo[22:21])
2'h0,
2'h2:
foobar = {foobar," 811"};
2'h1,
2'h3:
foobar = {foobar," 812"};
endcase
ozoneae(foo[ 8: 6], foobar);
foobar = {foobar," 813"};
ozoneae((foo[20:18]+1), foobar);
foobar = {foobar," 814"};
ozoneae((foo[17:15]+1), foobar);
case (foo[22:21])
2'h0,
2'h3:
foobar = {foobar," 815"};
2'h1,
2'h2:
foobar = {foobar," 816"};
endcase
ozoneae((foo[ 8: 6]+1), foobar);
end
5'h18:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 817"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 818"};
ozoneae(foo[ 8: 6], foobar);
foobar = {foobar," 819"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 820"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 821"};
ozoneae(foo[ 8: 6], foobar);
end
default :
foobar = {foobar," 822"};
endcase
end
endtask
task ozonef3e_te;
input [ 2:0] te;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (te)
3'b100 : foobar = {foobar, " 823"};
3'b101 : foobar = {foobar, " 824"};
3'b110 : foobar = {foobar, " 825"};
default: foobar = {foobar, " 826"};
endcase
end
endtask
task ozonearm;
input [ 2:0] ate;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (ate)
3'b000 : foobar = {foobar, " 827"};
3'b001 : foobar = {foobar, " 828"};
3'b010 : foobar = {foobar, " 829"};
3'b011 : foobar = {foobar, " 830"};
3'b100 : foobar = {foobar, " 831"};
3'b101 : foobar = {foobar, " 832"};
3'b110 : foobar = {foobar, " 833"};
3'b111 : foobar = {foobar, " 834"};
endcase
end
endtask
task ozonebmuop;
input [ 4:0] f4;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (f4[ 4:0])
5'h00,
5'h04 :
foobar = {foobar, " 835"};
5'h01,
5'h05 :
foobar = {foobar, " 836"};
5'h02,
5'h06 :
foobar = {foobar, " 837"};
5'h03,
5'h07 :
foobar = {foobar, " 838"};
5'h08,
5'h18 :
foobar = {foobar, " 839"};
5'h09,
5'h19 :
foobar = {foobar, " 840"};
5'h0a,
5'h1a :
foobar = {foobar, " 841"};
5'h0b :
foobar = {foobar, " 842"};
5'h1b :
foobar = {foobar, " 843"};
5'h0c,
5'h1c :
foobar = {foobar, " 844"};
5'h0d,
5'h1d :
foobar = {foobar, " 845"};
5'h1e :
foobar = {foobar, " 846"};
endcase
end
endtask
task ozonef3;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
reg nacho;
// verilator no_inline_task
begin : f3_body
nacho = 1'b0;
case (foo[24:21])
4'h0:
case (foo[26:25])
2'b00 : foobar = {foobar, " 847"};
2'b01 : foobar = {foobar, " 848"};
2'b10 : foobar = {foobar, " 849"};
2'b11 : foobar = {foobar, " 850"};
endcase
4'h1:
case (foo[26:25])
2'b00 : foobar = {foobar, " 851"};
2'b01 : foobar = {foobar, " 852"};
2'b10 : foobar = {foobar, " 853"};
2'b11 : foobar = {foobar, " 854"};
endcase
4'h2:
case (foo[26:25])
2'b00 : foobar = {foobar, " 855"};
2'b01 : foobar = {foobar, " 856"};
2'b10 : foobar = {foobar, " 857"};
2'b11 : foobar = {foobar, " 858"};
endcase
4'h8,
4'h9,
4'hd,
4'he,
4'hf :
case (foo[26:25])
2'b00 : foobar = {foobar, " 859"};
2'b01 : foobar = {foobar, " 860"};
2'b10 : foobar = {foobar, " 861"};
2'b11 : foobar = {foobar, " 862"};
endcase
4'ha,
4'hb :
if (foo[25])
foobar = {foobar, " 863"};
else
foobar = {foobar, " 864"};
4'hc :
if (foo[26])
foobar = {foobar, " 865"};
else
foobar = {foobar, " 866"};
default :
begin
foobar = {foobar, " 867"};
nacho = 1'b1;
end
endcase
if (~nacho)
begin
case (foo[24:21])
4'h8 :
foobar = {foobar, " 868"};
4'h9 :
foobar = {foobar, " 869"};
4'ha,
4'he :
foobar = {foobar, " 870"};
4'hb,
4'hf :
foobar = {foobar, " 871"};
4'hd :
foobar = {foobar, " 872"};
endcase
if (foo[20])
case (foo[18:16])
3'b000 : foobar = {foobar, " 873"};
3'b100 : foobar = {foobar, " 874"};
default: foobar = {foobar, " 875"};
endcase
else
ozoneae(foo[18:16], foobar);
if (foo[24:21] === 4'hc)
if (foo[25])
foobar = {foobar, " 876"};
else
foobar = {foobar, " 877"};
case (foo[24:21])
4'h0,
4'h1,
4'h2:
foobar = {foobar, " 878"};
endcase
end
end
endtask
task ozonerx;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[19:18])
2'h0 : foobar = {foobar, " 879"};
2'h1 : foobar = {foobar, " 880"};
2'h2 : foobar = {foobar, " 881"};
2'h3 : foobar = {foobar, " 882"};
endcase
case (foo[17:16])
2'h1 : foobar = {foobar, " 883"};
2'h2 : foobar = {foobar, " 884"};
2'h3 : foobar = {foobar, " 885"};
endcase
end
endtask
task ozonerme;
input [ 2:0] rme;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (rme)
3'h0 : foobar = {foobar, " 886"};
3'h1 : foobar = {foobar, " 887"};
3'h2 : foobar = {foobar, " 888"};
3'h3 : foobar = {foobar, " 889"};
3'h4 : foobar = {foobar, " 890"};
3'h5 : foobar = {foobar, " 891"};
3'h6 : foobar = {foobar, " 892"};
3'h7 : foobar = {foobar, " 893"};
endcase
end
endtask
task ozoneye;
input [5:0] ye;
input l;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
foobar = {foobar, " 894"};
ozonerme(ye[5:3],foobar);
case ({ye[ 2:0], l})
4'h2,
4'ha: foobar = {foobar, " 895"};
4'h4,
4'hb: foobar = {foobar, " 896"};
4'h6,
4'he: foobar = {foobar, " 897"};
4'h8,
4'hc: foobar = {foobar, " 898"};
endcase
end
endtask
task ozonef1e_ye;
input [5:0] ye;
input l;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
foobar = {foobar, " 899"};
ozonerme(ye[5:3],foobar);
ozonef1e_inc_dec(ye[5:0], l ,foobar);
end
endtask
task ozonef1e_h;
input [ 2:0] e;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
if (e[ 2:0] <= 3'h4)
foobar = {foobar, " 900"};
end
endtask
task ozonef1e_inc_dec;
input [5:0] ye;
input l;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case ({ye[ 2:0], l})
4'h2,
4'h3,
4'ha: foobar = {foobar, " 901"};
4'h4,
4'h5,
4'hb: foobar = {foobar, " 902"};
4'h6,
4'h7,
4'he: foobar = {foobar, " 903"};
4'h8,
4'h9,
4'hc: foobar = {foobar, " 904"};
4'hf: foobar = {foobar, " 905"};
endcase
end
endtask
task ozonef1e_hl;
input [ 2:0] e;
input l;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case ({e[ 2:0], l})
4'h0,
4'h2,
4'h4,
4'h6,
4'h8: foobar = {foobar, " 906"};
4'h1,
4'h3,
4'h5,
4'h7,
4'h9: foobar = {foobar, " 907"};
endcase
end
endtask
task ozonexe;
input [ 3:0] xe;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (xe[3])
1'b0 : foobar = {foobar, " 908"};
1'b1 : foobar = {foobar, " 909"};
endcase
case (xe[ 2:0])
3'h1,
3'h5: foobar = {foobar, " 910"};
3'h2,
3'h6: foobar = {foobar, " 911"};
3'h3,
3'h7: foobar = {foobar, " 912"};
3'h4: foobar = {foobar, " 913"};
endcase
end
endtask
task ozonerp;
input [ 2:0] rp;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (rp)
3'h0 : foobar = {foobar, " 914"};
3'h1 : foobar = {foobar, " 915"};
3'h2 : foobar = {foobar, " 916"};
3'h3 : foobar = {foobar, " 917"};
3'h4 : foobar = {foobar, " 918"};
3'h5 : foobar = {foobar, " 919"};
3'h6 : foobar = {foobar, " 920"};
3'h7 : foobar = {foobar, " 921"};
endcase
end
endtask
task ozonery;
input [ 3:0] ry;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (ry)
4'h0 : foobar = {foobar, " 922"};
4'h1 : foobar = {foobar, " 923"};
4'h2 : foobar = {foobar, " 924"};
4'h3 : foobar = {foobar, " 925"};
4'h4 : foobar = {foobar, " 926"};
4'h5 : foobar = {foobar, " 927"};
4'h6 : foobar = {foobar, " 928"};
4'h7 : foobar = {foobar, " 929"};
4'h8 : foobar = {foobar, " 930"};
4'h9 : foobar = {foobar, " 931"};
4'ha : foobar = {foobar, " 932"};
4'hb : foobar = {foobar, " 933"};
4'hc : foobar = {foobar, " 934"};
4'hd : foobar = {foobar, " 935"};
4'he : foobar = {foobar, " 936"};
4'hf : foobar = {foobar, " 937"};
endcase
end
endtask
task ozonearx;
input [ 15:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[1:0])
2'h0 : foobar = {foobar, " 938"};
2'h1 : foobar = {foobar, " 939"};
2'h2 : foobar = {foobar, " 940"};
2'h3 : foobar = {foobar, " 941"};
endcase
end
endtask
task ozonef3f4imop;
input [ 4:0] f3f4iml;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
casez (f3f4iml)
5'b000??: foobar = {foobar, " 942"};
5'b001??: foobar = {foobar, " 943"};
5'b?10??: foobar = {foobar, " 944"};
5'b0110?: foobar = {foobar, " 945"};
5'b01110: foobar = {foobar, " 946"};
5'b01111: foobar = {foobar, " 947"};
5'b10???: foobar = {foobar, " 948"};
5'b11100: foobar = {foobar, " 949"};
5'b11101: foobar = {foobar, " 950"};
5'b11110: foobar = {foobar, " 951"};
5'b11111: foobar = {foobar, " 952"};
endcase
end
endtask
task ozonecon;
input [ 4:0] con;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (con)
5'h00 : foobar = {foobar, " 953"};
5'h01 : foobar = {foobar, " 954"};
5'h02 : foobar = {foobar, " 955"};
5'h03 : foobar = {foobar, " 956"};
5'h04 : foobar = {foobar, " 957"};
5'h05 : foobar = {foobar, " 958"};
5'h06 : foobar = {foobar, " 959"};
5'h07 : foobar = {foobar, " 960"};
5'h08 : foobar = {foobar, " 961"};
5'h09 : foobar = {foobar, " 962"};
5'h0a : foobar = {foobar, " 963"};
5'h0b : foobar = {foobar, " 964"};
5'h0c : foobar = {foobar, " 965"};
5'h0d : foobar = {foobar, " 966"};
5'h0e : foobar = {foobar, " 967"};
5'h0f : foobar = {foobar, " 968"};
5'h10 : foobar = {foobar, " 969"};
5'h11 : foobar = {foobar, " 970"};
5'h12 : foobar = {foobar, " 971"};
5'h13 : foobar = {foobar, " 972"};
5'h14 : foobar = {foobar, " 973"};
5'h15 : foobar = {foobar, " 974"};
5'h16 : foobar = {foobar, " 975"};
5'h17 : foobar = {foobar, " 976"};
5'h18 : foobar = {foobar, " 977"};
5'h19 : foobar = {foobar, " 978"};
5'h1a : foobar = {foobar, " 979"};
5'h1b : foobar = {foobar, " 980"};
5'h1c : foobar = {foobar, " 981"};
5'h1d : foobar = {foobar, " 982"};
5'h1e : foobar = {foobar, " 983"};
5'h1f : foobar = {foobar, " 984"};
endcase
end
endtask
task ozonedr;
input [ 15:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[ 9: 6])
4'h0 : foobar = {foobar, " 985"};
4'h1 : foobar = {foobar, " 986"};
4'h2 : foobar = {foobar, " 987"};
4'h3 : foobar = {foobar, " 988"};
4'h4 : foobar = {foobar, " 989"};
4'h5 : foobar = {foobar, " 990"};
4'h6 : foobar = {foobar, " 991"};
4'h7 : foobar = {foobar, " 992"};
4'h8 : foobar = {foobar, " 993"};
4'h9 : foobar = {foobar, " 994"};
4'ha : foobar = {foobar, " 995"};
4'hb : foobar = {foobar, " 996"};
4'hc : foobar = {foobar, " 997"};
4'hd : foobar = {foobar, " 998"};
4'he : foobar = {foobar, " 999"};
4'hf : foobar = {foobar, " 1000"};
endcase
end
endtask
task ozoneshift;
input [ 15:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[ 4: 3])
2'h0 : foobar = {foobar, " 1001"};
2'h1 : foobar = {foobar, " 1002"};
2'h2 : foobar = {foobar, " 1003"};
2'h3 : foobar = {foobar, " 1004"};
endcase
end
endtask
task ozoneacc;
input foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo)
2'h0 : foobar = {foobar, " 1005"};
2'h1 : foobar = {foobar, " 1006"};
endcase
end
endtask
task ozonehl;
input foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo)
2'h0 : foobar = {foobar, " 1007"};
2'h1 : foobar = {foobar, " 1008"};
endcase
end
endtask
task dude;
inout [STRLEN*8: 1] foobar;
reg [ 7:0] temp;
integer i;
reg nacho;
// verilator no_inline_task
begin : justify_block
nacho = 1'b0;
for (i=STRLEN-1; i>1; i=i-1)
begin
temp = foobar>>((STRLEN-1)*8);
if (temp || nacho)
nacho = 1'b1;
else
begin
foobar = foobar<<8;
foobar[8:1] = 32;
end
end
end
endtask
task big_case;
input [ 31:0] fd;
input [ 31:0] foo;
reg [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
foobar = " 1009";
if (&foo === 1'bx)
$fwrite(fd, " 1010");
else
casez ( {foo[31:26], foo[19:15], foo[5:0]} )
17'b00_111?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1011"};
ozoneacc(~foo[26], foobar);
ozonehl(foo[20], foobar);
foobar = {foobar, " 1012"};
ozonerx(foo, foobar);
dude(foobar);
$fwrite (fd, " 1013:%s", foobar);
end
17'b01_001?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1014"};
ozonerx(foo, foobar);
foobar = {foobar, " 1015"};
foobar = {foobar, " 1016"};
ozonehl(foo[20], foobar);
dude(foobar);
$fwrite (fd, " 1017:%s", foobar);
end
17'b10_100?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1018"};
ozonerx(foo, foobar);
foobar = {foobar, " 1019"};
foobar = {foobar, " 1020"};
ozonehl(foo[20], foobar);
dude(foobar);
$fwrite (fd, " 1021:%s", foobar);
end
17'b10_101?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1022"};
if (foo[20])
begin
foobar = {foobar, " 1023"};
ozoneacc(foo[18], foobar);
foobar = {foobar, " 1024"};
foobar = {foobar, " 1025"};
if (foo[19])
foobar = {foobar, " 1026"};
else
foobar = {foobar, " 1027"};
end
else
ozonerx(foo, foobar);
dude(foobar);
$fwrite (fd, " 1028:%s", foobar);
end
17'b10_110?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1029"};
foobar = {foobar, " 1030"};
ozonehl(foo[20], foobar);
foobar = {foobar, " 1031"};
ozonerx(foo, foobar);
dude(foobar);
$fwrite (fd, " 1032:%s", foobar);
end
17'b10_111?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1033"};
foobar = {foobar, " 1034"};
ozonehl(foo[20], foobar);
foobar = {foobar, " 1035"};
ozonerx(foo, foobar);
dude(foobar);
$fwrite (fd, " 1036:%s", foobar);
end
17'b11_001?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1037"};
ozonerx(foo, foobar);
foobar = {foobar, " 1038"};
foobar = {foobar, " 1039"};
ozonehl(foo[20], foobar);
dude(foobar);
$fwrite (fd, " 1040:%s", foobar);
end
17'b11_111?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1041"};
foobar = {foobar, " 1042"};
ozonerx(foo, foobar);
foobar = {foobar, " 1043"};
if (foo[20])
foobar = {foobar, " 1044"};
else
foobar = {foobar, " 1045"};
dude(foobar);
$fwrite (fd, " 1046:%s", foobar);
end
17'b00_10??_?_????_?1_1111 :
casez (foo[11: 5])
7'b??_0_010_0:
begin
foobar = " 1047";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1048"};
ozonef1e(foo, foobar);
dude(foobar);
$fwrite (fd, " 1049:%s", foobar);
end
7'b00_?_110_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1050"};
case ({foo[ 9],foo[ 5]})
2'b00:
begin
foobar = {foobar, " 1051"};
ozoneae(foo[14:12], foobar);
ozonehl(foo[ 5], foobar);
end
2'b01:
begin
foobar = {foobar, " 1052"};
ozoneae(foo[14:12], foobar);
ozonehl(foo[ 5], foobar);
end
2'b10:
begin
foobar = {foobar, " 1053"};
ozoneae(foo[14:12], foobar);
end
2'b11: foobar = {foobar, " 1054"};
endcase
dude(foobar);
$fwrite (fd, " 1055:%s", foobar);
end
7'b01_?_110_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1056"};
case ({foo[ 9],foo[ 5]})
2'b00:
begin
ozoneae(foo[14:12], foobar);
ozonehl(foo[ 5], foobar);
foobar = {foobar, " 1057"};
end
2'b01:
begin
ozoneae(foo[14:12], foobar);
ozonehl(foo[ 5], foobar);
foobar = {foobar, " 1058"};
end
2'b10:
begin
ozoneae(foo[14:12], foobar);
foobar = {foobar, " 1059"};
end
2'b11: foobar = {foobar, " 1060"};
endcase
dude(foobar);
$fwrite (fd, " 1061:%s", foobar);
end
7'b10_0_110_0:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1062"};
foobar = {foobar, " 1063"};
if (foo[12])
foobar = {foobar, " 1064"};
else
ozonerab({4'b1001, foo[14:12]}, foobar);
dude(foobar);
$fwrite (fd, " 1065:%s", foobar);
end
7'b10_0_110_1:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1066"};
if (foo[12])
foobar = {foobar, " 1067"};
else
ozonerab({4'b1001, foo[14:12]}, foobar);
foobar = {foobar, " 1068"};
dude(foobar);
$fwrite (fd, " 1069:%s", foobar);
end
7'b??_?_000_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1070"};
foobar = {foobar, " 1071"};
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
foobar = {foobar, " 1072"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1073:%s", foobar);
end
7'b??_?_100_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1074"};
foobar = {foobar, " 1075"};
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
foobar = {foobar, " 1076"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1077:%s", foobar);
end
7'b??_?_001_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1078"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
foobar = {foobar, " 1079"};
foobar = {foobar, " 1080"};
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1081:%s", foobar);
end
7'b??_?_011_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1082"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
foobar = {foobar, " 1083"};
foobar = {foobar, " 1084"};
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1085:%s", foobar);
end
7'b??_?_101_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1086"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1087:%s", foobar);
end
endcase
17'b00_10??_?_????_?0_0110 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1088"};
ozoneae(foo[ 8: 6], foobar);
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
foobar = {foobar, " 1089"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1090:%s", foobar);
end
17'b00_10??_?_????_00_0111 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1091"};
if (foo[ 6])
foobar = {foobar, " 1092"};
else
ozonerab({4'b1001, foo[ 8: 6]}, foobar);
foobar = {foobar, " 1093"};
foobar = {foobar, " 1094"};
ozonerme(foo[14:12],foobar);
case (foo[11: 9])
3'h2,
3'h5,
3'h6,
3'h7:
ozonef1e_inc_dec(foo[14:9],1'b0,foobar);
3'h1,
3'h3,
3'h4:
foobar = {foobar, " 1095"};
endcase
dude(foobar);
$fwrite (fd, " 1096:%s", foobar);
end
17'b00_10??_?_????_?0_0100 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1097"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
foobar = {foobar, " 1098"};
ozoneae(foo[ 8: 6], foobar);
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1099:%s", foobar);
end
17'b00_10??_?_????_10_0111 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1100"};
foobar = {foobar, " 1101"};
ozonerme(foo[14:12],foobar);
case (foo[11: 9])
3'h2,
3'h5,
3'h6,
3'h7:
ozonef1e_inc_dec(foo[14:9],1'b0,foobar);
3'h1,
3'h3,
3'h4:
foobar = {foobar, " 1102"};
endcase
foobar = {foobar, " 1103"};
if (foo[ 6])
foobar = {foobar, " 1104"};
else
ozonerab({4'b1001, foo[ 8: 6]}, foobar);
dude(foobar);
$fwrite (fd, " 1105:%s", foobar);
end
17'b00_10??_?_????_?0_1110 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1106"};
case (foo[11:9])
3'h2:
begin
foobar = {foobar, " 1107"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1108"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1109"};
end
3'h6:
begin
foobar = {foobar, " 1110"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1111"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1112"};
end
3'h0:
begin
foobar = {foobar, " 1113"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1114"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1115"};
if (foo[ 7: 5] >= 3'h5)
foobar = {foobar, " 1116"};
else
ozonexe(foo[ 8: 5], foobar);
end
3'h1:
begin
foobar = {foobar, " 1117"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1118"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1119"};
if (foo[ 7: 5] >= 3'h5)
foobar = {foobar, " 1120"};
else
ozonexe(foo[ 8: 5], foobar);
end
3'h4:
begin
foobar = {foobar, " 1121"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1122"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1123"};
if (foo[ 7: 5] >= 3'h5)
foobar = {foobar, " 1124"};
else
ozonexe(foo[ 8: 5], foobar);
end
3'h5:
begin
foobar = {foobar, " 1125"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1126"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1127"};
if (foo[ 7: 5] >= 3'h5)
foobar = {foobar, " 1128"};
else
ozonexe(foo[ 8: 5], foobar);
end
endcase
dude(foobar);
$fwrite (fd, " 1129:%s", foobar);
end
17'b00_10??_?_????_?0_1111 :
casez (foo[14: 9])
6'b001_10_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1130"};
foobar = {foobar, " 1131"};
ozonef1e_hl(foo[ 7: 5],foo[ 9],foobar);
foobar = {foobar, " 1132"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1133:%s", foobar);
end
6'b???_11_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1134"};
ozoneae(foo[14:12], foobar);
ozonef1e_hl(foo[ 7: 5],foo[ 9],foobar);
foobar = {foobar, " 1135"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1136:%s", foobar);
end
6'b000_10_1,
6'b010_10_1,
6'b100_10_1,
6'b110_10_1:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1137"};
ozonerab({4'b1001, foo[14:12]}, foobar);
foobar = {foobar, " 1138"};
if ((foo[ 7: 5] >= 3'h1) & (foo[ 7: 5] <= 3'h3))
foobar = {foobar, " 1139"};
else
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1140:%s", foobar);
end
6'b000_10_0,
6'b010_10_0,
6'b100_10_0,
6'b110_10_0:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1141"};
foobar = {foobar, " 1142"};
ozonerab({4'b1001, foo[14:12]}, foobar);
foobar = {foobar, " 1143"};
foobar = {foobar, " 1144"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1145"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1146:%s", foobar);
end
6'b???_00_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1147"};
if (foo[ 9])
begin
foobar = {foobar, " 1148"};
ozoneae(foo[14:12], foobar);
end
else
begin
foobar = {foobar, " 1149"};
ozoneae(foo[14:12], foobar);
foobar = {foobar, " 1150"};
end
foobar = {foobar, " 1151"};
foobar = {foobar, " 1152"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1153"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1154:%s", foobar);
end
6'b???_01_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1155"};
ozoneae(foo[14:12], foobar);
if (foo[ 9])
foobar = {foobar, " 1156"};
else
foobar = {foobar, " 1157"};
foobar = {foobar, " 1158"};
foobar = {foobar, " 1159"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1160"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1161:%s", foobar);
end
6'b011_10_0:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1162"};
case (foo[ 8: 5])
4'h0: foobar = {foobar, " 1163"};
4'h1: foobar = {foobar, " 1164"};
4'h2: foobar = {foobar, " 1165"};
4'h3: foobar = {foobar, " 1166"};
4'h4: foobar = {foobar, " 1167"};
4'h5: foobar = {foobar, " 1168"};
4'h8: foobar = {foobar, " 1169"};
4'h9: foobar = {foobar, " 1170"};
4'ha: foobar = {foobar, " 1171"};
4'hb: foobar = {foobar, " 1172"};
4'hc: foobar = {foobar, " 1173"};
4'hd: foobar = {foobar, " 1174"};
default: foobar = {foobar, " 1175"};
endcase
dude(foobar);
$fwrite (fd, " 1176:%s", foobar);
end
default: foobar = {foobar, " 1177"};
endcase
17'b00_10??_?_????_?0_110? :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1178"};
foobar = {foobar, " 1179"};
ozonef1e_hl(foo[11:9], foo[0], foobar);
foobar = {foobar, " 1180"};
ozonef1e_ye(foo[14:9],1'b0,foobar);
foobar = {foobar, " 1181"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1182"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1183:%s", foobar);
end
17'b00_10??_?_????_?1_110? :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1184"};
foobar = {foobar, " 1185"};
ozonef1e_hl(foo[11:9],foo[0],foobar);
foobar = {foobar, " 1186"};
ozonef1e_ye(foo[14:9],foo[ 0],foobar);
foobar = {foobar, " 1187"};
foobar = {foobar, " 1188"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1189"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1190:%s", foobar);
end
17'b00_10??_?_????_?0_101? :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1191"};
ozonef1e_ye(foo[14:9],foo[ 0],foobar);
foobar = {foobar, " 1192"};
foobar = {foobar, " 1193"};
ozonef1e_hl(foo[11:9],foo[0],foobar);
foobar = {foobar, " 1194"};
foobar = {foobar, " 1195"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1196"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1197:%s", foobar);
end
17'b00_10??_?_????_?0_1001 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1198"};
foobar = {foobar, " 1199"};
ozonef1e_h(foo[11:9],foobar);
foobar = {foobar, " 1200"};
ozonef1e_ye(foo[14:9],1'b0,foobar);
foobar = {foobar, " 1201"};
case (foo[ 7: 5])
3'h1,
3'h2,
3'h3:
foobar = {foobar, " 1202"};
default:
begin
foobar = {foobar, " 1203"};
foobar = {foobar, " 1204"};
ozonexe(foo[ 8: 5], foobar);
end
endcase
dude(foobar);
$fwrite (fd, " 1205:%s", foobar);
end
17'b00_10??_?_????_?0_0101 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1206"};
case (foo[11: 9])
3'h1,
3'h3,
3'h4:
foobar = {foobar, " 1207"};
default:
begin
ozonef1e_ye(foo[14:9],1'b0,foobar);
foobar = {foobar, " 1208"};
foobar = {foobar, " 1209"};
end
endcase
foobar = {foobar, " 1210"};
foobar = {foobar, " 1211"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1212"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1213:%s", foobar);
end
17'b00_10??_?_????_?1_1110 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1214"};
ozonef1e_ye(foo[14:9],1'b0,foobar);
foobar = {foobar, " 1215"};
foobar = {foobar, " 1216"};
ozonef1e_h(foo[11: 9],foobar);
foobar = {foobar, " 1217"};
foobar = {foobar, " 1218"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1219"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1220:%s", foobar);
end
17'b00_10??_?_????_?0_1000 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1221"};
ozonef1e_ye(foo[14:9],1'b0,foobar);
foobar = {foobar, " 1222"};
foobar = {foobar, " 1223"};
ozonef1e_h(foo[11: 9],foobar);
foobar = {foobar, " 1224"};
foobar = {foobar, " 1225"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1226"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1227:%s", foobar);
end
17'b10_01??_?_????_??_???? :
begin
if (foo[27])
foobar = " 1228";
else
foobar = " 1229";
ozonecon(foo[20:16], foobar);
foobar = {foobar, " 1230"};
ozonef2(foo[31:0], foobar);
dude(foobar);
$fwrite (fd, " 1231:%s", foobar);
end
17'b00_1000_?_????_01_0011 :
if (~|foo[ 9: 8])
begin
if (foo[ 7])
foobar = " 1232";
else
foobar = " 1233";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1234"};
ozonef2e(foo[31:0], foobar);
dude(foobar);
$fwrite (fd, " 1235:%s", foobar);
end
else
begin
foobar = " 1236";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1237"};
ozonef3e(foo[31:0], foobar);
dude(foobar);
$fwrite (fd, " 1238:%s", foobar);
end
17'b11_110?_1_????_??_???? :
begin
ozonef3(foo[31:0], foobar);
dude(foobar);
$fwrite(fd, " 1239:%s", foobar);
end
17'b11_110?_0_????_??_???? :
begin : f4_body
casez (foo[24:20])
5'b0_1110,
5'b1_0???,
5'b1_1111:
begin
$fwrite (fd, " 1240");
end
5'b0_00??:
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1241"};
ozoneacc(foo[25], foobar);
ozonebmuop(foo[24:20], foobar);
ozoneae(foo[18:16], foobar);
foobar = {foobar, " 1242"};
dude(foobar);
$fwrite(fd, " 1243:%s", foobar);
end
5'b0_01??:
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1244"};
ozoneacc(foo[25], foobar);
ozonebmuop(foo[24:20], foobar);
ozonearm(foo[18:16], foobar);
dude(foobar);
$fwrite(fd, " 1245:%s", foobar);
end
5'b0_1011:
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1246"};
ozonebmuop(foo[24:20], foobar);
foobar = {foobar, " 1247"};
ozoneae(foo[18:16], foobar);
foobar = {foobar, " 1248"};
dude(foobar);
$fwrite(fd, " 1249:%s", foobar);
end
5'b0_100?,
5'b0_1010,
5'b0_110? :
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1250"};
ozonebmuop(foo[24:20], foobar);
foobar = {foobar, " 1251"};
ozoneacc(foo[25], foobar);
foobar = {foobar, " 1252"};
ozoneae(foo[18:16], foobar);
foobar = {foobar, " 1253"};
dude(foobar);
$fwrite(fd, " 1254:%s", foobar);
end
5'b0_1111 :
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1255"};
ozoneacc(foo[25], foobar);
foobar = {foobar, " 1256"};
ozoneae(foo[18:16], foobar);
dude(foobar);
$fwrite(fd, " 1257:%s", foobar);
end
5'b1_10??,
5'b1_110?,
5'b1_1110 :
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1258"};
ozonebmuop(foo[24:20], foobar);
foobar = {foobar, " 1259"};
ozoneacc(foo[25], foobar);
foobar = {foobar, " 1260"};
ozonearm(foo[18:16], foobar);
foobar = {foobar, " 1261"};
dude(foobar);
$fwrite(fd, " 1262:%s", foobar);
end
endcase
end
17'b11_100?_?_????_??_???? :
casez (foo[23:19])
5'b111??,
5'b0111?:
begin
ozoneae(foo[26:24], foobar);
foobar = {foobar, " 1263"};
ozonef3f4imop(foo[23:19], foobar);
foobar = {foobar, " 1264"};
ozoneae(foo[18:16], foobar);
foobar = {foobar, " 1265"};
skyway(foo[15:12], foobar);
skyway(foo[11: 8], foobar);
skyway(foo[ 7: 4], foobar);
skyway(foo[ 3:0], foobar);
foobar = {foobar, " 1266"};
dude(foobar);
$fwrite(fd, " 1267:%s", foobar);
end
5'b?0???,
5'b110??:
begin
ozoneae(foo[26:24], foobar);
foobar = {foobar, " 1268"};
if (foo[23:21] == 3'b100)
foobar = {foobar, " 1269"};
ozoneae(foo[18:16], foobar);
if (foo[19])
foobar = {foobar, " 1270"};
else
foobar = {foobar, " 1271"};
ozonef3f4imop(foo[23:19], foobar);
foobar = {foobar, " 1272"};
ozonef3f4_iext(foo[20:19], foo[15:0], foobar);
dude(foobar);
$fwrite(fd, " 1273:%s", foobar);
end
5'b010??,
5'b0110?:
begin
ozoneae(foo[18:16], foobar);
if (foo[19])
foobar = {foobar, " 1274"};
else
foobar = {foobar, " 1275"};
ozonef3f4imop(foo[23:19], foobar);
foobar = {foobar, " 1276"};
ozonef3f4_iext(foo[20:19], foo[15:0], foobar);
dude(foobar);
$fwrite(fd, " 1277:%s", foobar);
end
endcase
17'b00_1000_?_????_11_0011 :
begin
foobar = " 1278";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1279"};
casez (foo[25:21])
5'b0_1110,
5'b1_0???,
5'b1_1111:
begin
$fwrite(fd, " 1280");
end
5'b0_00??:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1281"};
ozoneae(foo[17:15], foobar);
ozonebmuop(foo[25:21], foobar);
ozoneae(foo[ 8: 6], foobar);
foobar = {foobar, " 1282"};
dude(foobar);
$fwrite(fd, " 1283:%s", foobar);
end
5'b0_01??:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1284"};
ozoneae(foo[17:15], foobar);
ozonebmuop(foo[25:21], foobar);
ozonearm(foo[ 8: 6], foobar);
dude(foobar);
$fwrite(fd, " 1285:%s", foobar);
end
5'b0_1011:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1286"};
ozonebmuop(foo[25:21], foobar);
foobar = {foobar, " 1287"};
ozoneae(foo[ 8: 6], foobar);
foobar = {foobar, " 1288"};
dude(foobar);
$fwrite(fd, " 1289:%s", foobar);
end
5'b0_100?,
5'b0_1010,
5'b0_110? :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1290"};
ozonebmuop(foo[25:21], foobar);
foobar = {foobar, " 1291"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 1292"};
ozoneae(foo[ 8: 6], foobar);
foobar = {foobar, " 1293"};
dude(foobar);
$fwrite(fd, " 1294:%s", foobar);
end
5'b0_1111 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1295"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 1296"};
ozoneae(foo[ 8: 6], foobar);
dude(foobar);
$fwrite(fd, " 1297:%s", foobar);
end
5'b1_10??,
5'b1_110?,
5'b1_1110 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1298"};
ozonebmuop(foo[25:21], foobar);
foobar = {foobar, " 1299"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 1300"};
ozonearm(foo[ 8: 6], foobar);
foobar = {foobar, " 1301"};
dude(foobar);
$fwrite(fd, " 1302:%s", foobar);
end
endcase
end
17'b00_0010_?_????_??_???? :
begin
$fwrite(fd, " 1304a:%x;%x", foobar, foo[25:20]);
ozonerab({1'b0, foo[25:20]}, foobar);
$fwrite(fd, " 1304b:%x", foobar);
foobar = {foobar, " 1303"};
$fwrite(fd, " 1304c:%x;%x", foobar, foo[19:16]);
skyway(foo[19:16], foobar);
$fwrite(fd, " 1304d:%x", foobar);
dude(foobar);
$fwrite(fd, " 1304e:%x", foobar);
$fwrite(fd, " 1304:%s", foobar);
end
17'b00_01??_?_????_??_???? :
begin
if (foo[27])
begin
foobar = {foobar, " 1305"};
if (foo[26])
foobar = {foobar, " 1306"};
else
foobar = {foobar, " 1307"};
skyway(foo[19:16], foobar);
foobar = {foobar, " 1308"};
ozonerab({1'b0, foo[25:20]}, foobar);
end
else
begin
ozonerab({1'b0, foo[25:20]}, foobar);
foobar = {foobar, " 1309"};
if (foo[26])
foobar = {foobar, " 1310"};
else
foobar = {foobar, " 1311"};
skyway(foo[19:16], foobar);
foobar = {foobar, " 1312"};
end
dude(foobar);
$fwrite(fd, " 1313:%s", foobar);
end
17'b01_000?_?_????_??_???? :
begin
if (foo[26])
begin
ozonerb(foo[25:20], foobar);
foobar = {foobar, " 1314"};
ozoneae(foo[18:16], foobar);
ozonehl(foo[19], foobar);
end
else
begin
ozoneae(foo[18:16], foobar);
ozonehl(foo[19], foobar);
foobar = {foobar, " 1315"};
ozonerb(foo[25:20], foobar);
end
dude(foobar);
$fwrite(fd, " 1316:%s", foobar);
end
17'b01_10??_?_????_??_???? :
begin
if (foo[27])
begin
ozonerab({1'b0, foo[25:20]}, foobar);
foobar = {foobar, " 1317"};
ozonerx(foo, foobar);
end
else
begin
ozonerx(foo, foobar);
foobar = {foobar, " 1318"};
ozonerab({1'b0, foo[25:20]}, foobar);
end
dude(foobar);
$fwrite(fd, " 1319:%s", foobar);
end
17'b11_101?_?_????_??_???? :
begin
ozonerab (foo[26:20], foobar);
foobar = {foobar, " 1320"};
skyway(foo[19:16], foobar);
skyway(foo[15:12], foobar);
skyway(foo[11: 8], foobar);
skyway(foo[ 7: 4], foobar);
skyway(foo[ 3: 0], foobar);
dude(foobar);
$fwrite(fd, " 1321:%s", foobar);
end
17'b11_0000_?_????_??_???? :
begin
casez (foo[25:23])
3'b00?:
begin
ozonerab(foo[22:16], foobar);
foobar = {foobar, " 1322"};
end
3'b01?:
begin
foobar = {foobar, " 1323"};
if (foo[22:16]>=7'h60)
foobar = {foobar, " 1324"};
else
ozonerab(foo[22:16], foobar);
end
3'b110:
foobar = {foobar, " 1325"};
3'b10?:
begin
foobar = {foobar, " 1326"};
if (foo[22:16]>=7'h60)
foobar = {foobar, " 1327"};
else
ozonerab(foo[22:16], foobar);
end
3'b111:
begin
foobar = {foobar, " 1328"};
ozonerab(foo[22:16], foobar);
foobar = {foobar, " 1329"};
end
endcase
dude(foobar);
$fwrite(fd, " 1330:%s", foobar);
end
17'b00_10??_?_????_?1_0000 :
begin
if (foo[27])
begin
foobar = {foobar, " 1331"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1332"};
skyway(foo[19:16], foobar);
skyway({foo[15],foo[11: 9]}, foobar);
skyway(foo[ 8: 5], foobar);
foobar = {foobar, " 1333"};
if (foo[26:20]>=7'h60)
foobar = {foobar, " 1334"};
else
ozonerab(foo[26:20], foobar);
end
else
begin
ozonerab(foo[26:20], foobar);
foobar = {foobar, " 1335"};
foobar = {foobar, " 1336"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1337"};
skyway(foo[19:16], foobar);
skyway({foo[15],foo[11: 9]}, foobar);
skyway(foo[ 8: 5], foobar);
foobar = {foobar, " 1338"};
end
dude(foobar);
$fwrite(fd, " 1339:%s", foobar);
end
17'b00_101?_1_0000_?1_0010 :
if (~|foo[11: 7])
begin
if (foo[ 6])
begin
foobar = {foobar, " 1340"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1341"};
ozonejk(foo[ 5], foobar);
foobar = {foobar, " 1342"};
if (foo[26:20]>=7'h60)
foobar = {foobar, " 1343"};
else
ozonerab(foo[26:20], foobar);
end
else
begin
ozonerab(foo[26:20], foobar);
foobar = {foobar, " 1344"};
foobar = {foobar, " 1345"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1346"};
ozonejk(foo[ 5], foobar);
foobar = {foobar, " 1347"};
end
dude(foobar);
$fwrite(fd, " 1348:%s", foobar);
end
else
$fwrite(fd, " 1349");
17'b00_100?_0_0011_?1_0101 :
if (~|foo[ 8: 7])
begin
if (foo[6])
begin
ozonerab(foo[26:20], foobar);
foobar = {foobar, " 1350"};
ozoneye(foo[14: 9],foo[ 5], foobar);
end
else
begin
ozoneye(foo[14: 9],foo[ 5], foobar);
foobar = {foobar, " 1351"};
if (foo[26:20]>=7'h60)
foobar = {foobar, " 1352"};
else
ozonerab(foo[26:20], foobar);
end
dude(foobar);
$fwrite(fd, " 1353:%s", foobar);
end
else
$fwrite(fd, " 1354");
17'b00_1001_0_0000_?1_0010 :
if (~|foo[25:20])
begin
ozoneye(foo[14: 9],1'b0, foobar);
foobar = {foobar, " 1355"};
ozonef1e_h(foo[11: 9],foobar);
foobar = {foobar, " 1356"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1357"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite(fd, " 1358:%s", foobar);
end
else
$fwrite(fd, " 1359");
17'b00_101?_0_????_?1_0010 :
if (~foo[13])
begin
if (foo[12])
begin
foobar = {foobar, " 1360"};
if (foo[26:20]>=7'h60)
foobar = {foobar, " 1361"};
else
ozonerab(foo[26:20], foobar);
foobar = {foobar, " 1362"};
foobar = {foobar, " 1363"};
skyway({1'b0,foo[18:16]}, foobar);
skyway({foo[15],foo[11: 9]}, foobar);
skyway(foo[ 8: 5], foobar);
dude(foobar);
$fwrite(fd, " 1364:%s", foobar);
end
else
begin
ozonerab(foo[26:20], foobar);
foobar = {foobar, " 1365"};
foobar = {foobar, " 1366"};
skyway({1'b0,foo[18:16]}, foobar);
skyway({foo[15],foo[11: 9]}, foobar);
skyway(foo[ 8: 5], foobar);
dude(foobar);
$fwrite(fd, " 1367:%s", foobar);
end
end
else
$fwrite(fd, " 1368");
17'b01_01??_?_????_??_???? :
begin
ozonerab({1'b0,foo[27:26],foo[19:16]}, foobar);
foobar = {foobar, " 1369"};
ozonerab({1'b0,foo[25:20]}, foobar);
dude(foobar);
$fwrite(fd, " 1370:%s", foobar);
end
17'b00_100?_?_???0_11_0101 :
if (~foo[6])
begin
foobar = " 1371";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1372"};
ozonerab({foo[ 9: 7],foo[19:16]}, foobar);
foobar = {foobar, " 1373"};
ozonerab({foo[26:20]}, foobar);
dude(foobar);
$fwrite(fd, " 1374:%s", foobar);
end
else
$fwrite(fd, " 1375");
17'b00_1000_?_????_?1_0010 :
if (~|foo[25:24])
begin
ozonery(foo[23:20], foobar);
foobar = {foobar, " 1376"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1377"};
skyway(foo[19:16], foobar);
skyway({foo[15],foo[11: 9]}, foobar);
skyway(foo[ 8: 5], foobar);
dude(foobar);
$fwrite(fd, " 1378:%s", foobar);
end
else if ((foo[25:24] == 2'b10) & ~|foo[19:15] & ~|foo[11: 6])
begin
ozonery(foo[23:20], foobar);
foobar = {foobar, " 1379"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1380"};
ozonejk(foo[ 5], foobar);
dude(foobar);
$fwrite(fd, " 1381:%s", foobar);
end
else
$fwrite(fd, " 1382");
17'b11_01??_?_????_??_????,
17'b10_00??_?_????_??_???? :
if (foo[30])
$fwrite(fd, " 1383:%s", foo[27:16]);
else
$fwrite(fd, " 1384:%s", foo[27:16]);
17'b00_10??_?_????_01_1000 :
if (~foo[6])
begin
if (foo[7])
$fwrite(fd, " 1385:%s", foo[27: 8]);
else
$fwrite(fd, " 1386:%s", foo[27: 8]);
end
else
$fwrite(fd, " 1387");
17'b00_10??_?_????_11_1000 :
begin
foobar = " 1388";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1389"};
if (foo[15])
foobar = {foobar, " 1390"};
else
foobar = {foobar, " 1391"};
skyway(foo[27:24], foobar);
skyway(foo[23:20], foobar);
skyway(foo[19:16], foobar);
skyway(foo[ 9: 6], foobar);
dude(foobar);
$fwrite(fd, " 1392:%s", foobar);
end
17'b11_0001_?_????_??_???? :
casez (foo[25:22])
4'b01?? :
begin
foobar = " 1393";
ozonecon(foo[20:16], foobar);
case (foo[23:21])
3'h0 : foobar = {foobar, " 1394"};
3'h1 : foobar = {foobar, " 1395"};
3'h2 : foobar = {foobar, " 1396"};
3'h3 : foobar = {foobar, " 1397"};
3'h4 : foobar = {foobar, " 1398"};
3'h5 : foobar = {foobar, " 1399"};
3'h6 : foobar = {foobar, " 1400"};
3'h7 : foobar = {foobar, " 1401"};
endcase
dude(foobar);
$fwrite(fd, " 1402:%s", foobar);
end
4'b0000 :
$fwrite(fd, " 1403:%s", foo[21:16]);
4'b0010 :
if (~|foo[21:16])
$fwrite(fd, " 1404");
4'b1010 :
if (~|foo[21:17])
begin
if (foo[16])
$fwrite(fd, " 1405");
else
$fwrite(fd, " 1406");
end
default :
$fwrite(fd, " 1407");
endcase
17'b01_11??_?_????_??_???? :
if (foo[27:23] === 5'h00)
$fwrite(fd, " 1408:%s", foo[22:16]);
else
$fwrite(fd, " 1409:%s", foo[22:16]);
default: $fwrite(fd, " 1410");
endcase
end
endtask
//(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\",\",\\4,\");\");" nil nil nil)
//(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\");\");" nil nil nil)
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
parameter PAR = 3;
input clk;
`ifdef verilator
// Else it becomes a localparam, per IEEE 4.10.1, but we don't check it
defparam m3.FROMDEFP = 19;
`endif
m3 #(.P3(PAR),
.P2(2))
m3(.clk(clk));
integer cyc=1;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==1) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module m3
#(
parameter UNCH = 99,
parameter P1 = 10,
parameter P2 = 20,
P3 = 30
)
(/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam LOC = 13;
parameter FROMDEFP = 11;
initial begin
$display("%x %x %x",P1,P2,P3);
end
always @ (posedge clk) begin
if (UNCH !== 99) $stop;
if (P1 !== 10) $stop;
if (P2 !== 2) $stop;
if (P3 !== 3) $stop;
`ifdef verilator
if (FROMDEFP !== 19) $stop;
`endif
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
`include "verilated.v"
module t_case_write2_tasks ();
// verilator lint_off WIDTH
// verilator lint_off CASEINCOMPLETE
`define FD_BITS 31:0
parameter STRLEN = 78;
task ozonerab;
input [6:0] rab;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (rab[6:0])
7'h00 : $fwrite (fd, " 0");
7'h01 : $fwrite (fd, " 1");
7'h02 : $fwrite (fd, " 2");
7'h03 : $fwrite (fd, " 3");
7'h04 : $fwrite (fd, " 4");
7'h05 : $fwrite (fd, " 5");
7'h06 : $fwrite (fd, " 6");
7'h07 : $fwrite (fd, " 7");
7'h08 : $fwrite (fd, " 8");
7'h09 : $fwrite (fd, " 9");
7'h0a : $fwrite (fd, " 10");
7'h0b : $fwrite (fd, " 11");
7'h0c : $fwrite (fd, " 12");
7'h0d : $fwrite (fd, " 13");
7'h0e : $fwrite (fd, " 14");
7'h0f : $fwrite (fd, " 15");
7'h10 : $fwrite (fd, " 16");
7'h11 : $fwrite (fd, " 17");
7'h12 : $fwrite (fd, " 18");
7'h13 : $fwrite (fd, " 19");
7'h14 : $fwrite (fd, " 20");
7'h15 : $fwrite (fd, " 21");
7'h16 : $fwrite (fd, " 22");
7'h17 : $fwrite (fd, " 23");
7'h18 : $fwrite (fd, " 24");
7'h19 : $fwrite (fd, " 25");
7'h1a : $fwrite (fd, " 26");
7'h1b : $fwrite (fd, " 27");
7'h1c : $fwrite (fd, " 28");
7'h1d : $fwrite (fd, " 29");
7'h1e : $fwrite (fd, " 30");
7'h1f : $fwrite (fd, " 31");
7'h20 : $fwrite (fd, " 32");
7'h21 : $fwrite (fd, " 33");
7'h22 : $fwrite (fd, " 34");
7'h23 : $fwrite (fd, " 35");
7'h24 : $fwrite (fd, " 36");
7'h25 : $fwrite (fd, " 37");
7'h26 : $fwrite (fd, " 38");
7'h27 : $fwrite (fd, " 39");
7'h28 : $fwrite (fd, " 40");
7'h29 : $fwrite (fd, " 41");
7'h2a : $fwrite (fd, " 42");
7'h2b : $fwrite (fd, " 43");
7'h2c : $fwrite (fd, " 44");
7'h2d : $fwrite (fd, " 45");
7'h2e : $fwrite (fd, " 46");
7'h2f : $fwrite (fd, " 47");
7'h30 : $fwrite (fd, " 48");
7'h31 : $fwrite (fd, " 49");
7'h32 : $fwrite (fd, " 50");
7'h33 : $fwrite (fd, " 51");
7'h34 : $fwrite (fd, " 52");
7'h35 : $fwrite (fd, " 53");
7'h36 : $fwrite (fd, " 54");
7'h37 : $fwrite (fd, " 55");
7'h38 : $fwrite (fd, " 56");
7'h39 : $fwrite (fd, " 57");
7'h3a : $fwrite (fd, " 58");
7'h3b : $fwrite (fd, " 59");
7'h3c : $fwrite (fd, " 60");
7'h3d : $fwrite (fd, " 61");
7'h3e : $fwrite (fd, " 62");
7'h3f : $fwrite (fd, " 63");
7'h40 : $fwrite (fd, " 64");
7'h41 : $fwrite (fd, " 65");
7'h42 : $fwrite (fd, " 66");
7'h43 : $fwrite (fd, " 67");
7'h44 : $fwrite (fd, " 68");
7'h45 : $fwrite (fd, " 69");
7'h46 : $fwrite (fd, " 70");
7'h47 : $fwrite (fd, " 71");
7'h48 : $fwrite (fd, " 72");
7'h49 : $fwrite (fd, " 73");
7'h4a : $fwrite (fd, " 74");
7'h4b : $fwrite (fd, " 75");
7'h4c : $fwrite (fd, " 76");
7'h4d : $fwrite (fd, " 77");
7'h4e : $fwrite (fd, " 78");
7'h4f : $fwrite (fd, " 79");
7'h50 : $fwrite (fd, " 80");
7'h51 : $fwrite (fd, " 81");
7'h52 : $fwrite (fd, " 82");
7'h53 : $fwrite (fd, " 83");
7'h54 : $fwrite (fd, " 84");
7'h55 : $fwrite (fd, " 85");
7'h56 : $fwrite (fd, " 86");
7'h57 : $fwrite (fd, " 87");
7'h58 : $fwrite (fd, " 88");
7'h59 : $fwrite (fd, " 89");
7'h5a : $fwrite (fd, " 90");
7'h5b : $fwrite (fd, " 91");
7'h5c : $fwrite (fd, " 92");
7'h5d : $fwrite (fd, " 93");
7'h5e : $fwrite (fd, " 94");
7'h5f : $fwrite (fd, " 95");
7'h60 : $fwrite (fd, " 96");
7'h61 : $fwrite (fd, " 97");
7'h62 : $fwrite (fd, " 98");
7'h63 : $fwrite (fd, " 99");
7'h64 : $fwrite (fd, " 100");
7'h65 : $fwrite (fd, " 101");
7'h66 : $fwrite (fd, " 102");
7'h67 : $fwrite (fd, " 103");
7'h68 : $fwrite (fd, " 104");
7'h69 : $fwrite (fd, " 105");
7'h6a : $fwrite (fd, " 106");
7'h6b : $fwrite (fd, " 107");
7'h6c : $fwrite (fd, " 108");
7'h6d : $fwrite (fd, " 109");
7'h6e : $fwrite (fd, " 110");
7'h6f : $fwrite (fd, " 111");
7'h70 : $fwrite (fd, " 112");
7'h71 : $fwrite (fd, " 113");
7'h72 : $fwrite (fd, " 114");
7'h73 : $fwrite (fd, " 115");
7'h74 : $fwrite (fd, " 116");
7'h75 : $fwrite (fd, " 117");
7'h76 : $fwrite (fd, " 118");
7'h77 : $fwrite (fd, " 119");
7'h78 : $fwrite (fd, " 120");
7'h79 : $fwrite (fd, " 121");
7'h7a : $fwrite (fd, " 122");
7'h7b : $fwrite (fd, " 123");
7'h7c : $fwrite (fd, " 124");
7'h7d : $fwrite (fd, " 125");
7'h7e : $fwrite (fd, " 126");
7'h7f : $fwrite (fd, " 127");
default:$fwrite (fd, " 128");
endcase
end
endtask
task ozonerb;
input [5:0] rb;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (rb[5:0])
6'h10,
6'h17,
6'h1e,
6'h1f: $fwrite (fd, " 129");
default: ozonerab({1'b1, rb}, fd);
endcase
end
endtask
task ozonef3f4_iext;
input [1:0] foo;
input [15:0] im16;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo)
2'h0 :
begin
skyway({4{im16[15]}}, fd);
skyway({4{im16[15]}}, fd);
skyway(im16[15:12], fd);
skyway(im16[11: 8], fd);
skyway(im16[ 7: 4], fd);
skyway(im16[ 3:0], fd);
$fwrite (fd, " 130");
end
2'h1 :
begin
$fwrite (fd, " 131");
skyway(im16[15:12], fd);
skyway(im16[11: 8], fd);
skyway(im16[ 7: 4], fd);
skyway(im16[ 3:0], fd);
end
2'h2 :
begin
skyway({4{im16[15]}}, fd);
skyway({4{im16[15]}}, fd);
skyway(im16[15:12], fd);
skyway(im16[11: 8], fd);
skyway(im16[ 7: 4], fd);
skyway(im16[ 3:0], fd);
$fwrite (fd, " 132");
end
2'h3 :
begin
$fwrite (fd, " 133");
skyway(im16[15:12], fd);
skyway(im16[11: 8], fd);
skyway(im16[ 7: 4], fd);
skyway(im16[ 3:0], fd);
end
endcase
end
endtask
task skyway;
input [ 3:0] hex;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (hex)
4'h0 : $fwrite (fd, " 134");
4'h1 : $fwrite (fd, " 135");
4'h2 : $fwrite (fd, " 136");
4'h3 : $fwrite (fd, " 137");
4'h4 : $fwrite (fd, " 138");
4'h5 : $fwrite (fd, " 139");
4'h6 : $fwrite (fd, " 140");
4'h7 : $fwrite (fd, " 141");
4'h8 : $fwrite (fd, " 142");
4'h9 : $fwrite (fd, " 143");
4'ha : $fwrite (fd, " 144");
4'hb : $fwrite (fd, " 145");
4'hc : $fwrite (fd, " 146");
4'hd : $fwrite (fd, " 147");
4'he : $fwrite (fd, " 148");
4'hf : $fwrite (fd, " 149");
endcase
end
endtask
task ozonesr;
input [ 15:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[11: 9])
3'h0 : $fwrite (fd, " 158");
3'h1 : $fwrite (fd, " 159");
3'h2 : $fwrite (fd, " 160");
3'h3 : $fwrite (fd, " 161");
3'h4 : $fwrite (fd, " 162");
3'h5 : $fwrite (fd, " 163");
3'h6 : $fwrite (fd, " 164");
3'h7 : $fwrite (fd, " 165");
endcase
end
endtask
task ozonejk;
input k;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
if (k)
$fwrite (fd, " 166");
else
$fwrite (fd, " 167");
end
endtask
task ozoneae;
input [ 2:0] ae;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (ae)
3'b000 : $fwrite (fd, " 168");
3'b001 : $fwrite (fd, " 169");
3'b010 : $fwrite (fd, " 170");
3'b011 : $fwrite (fd, " 171");
3'b100 : $fwrite (fd, " 172");
3'b101 : $fwrite (fd, " 173");
3'b110 : $fwrite (fd, " 174");
3'b111 : $fwrite (fd, " 175");
endcase
end
endtask
task ozoneaee;
input [ 2:0] aee;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (aee)
3'b001,
3'b011,
3'b101,
3'b111 : $fwrite (fd, " 176");
3'b000 : $fwrite (fd, " 177");
3'b010 : $fwrite (fd, " 178");
3'b100 : $fwrite (fd, " 179");
3'b110 : $fwrite (fd, " 180");
endcase
end
endtask
task ozoneape;
input [ 2:0] ape;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (ape)
3'b001,
3'b011,
3'b101,
3'b111 : $fwrite (fd, " 181");
3'b000 : $fwrite (fd, " 182");
3'b010 : $fwrite (fd, " 183");
3'b100 : $fwrite (fd, " 184");
3'b110 : $fwrite (fd, " 185");
endcase
end
endtask
task ozonef1;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[24:21])
4'h0 :
if (foo[26])
$fwrite (fd, " 186");
else
$fwrite (fd, " 187");
4'h1 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 188");
2'b01 : $fwrite (fd, " 189");
2'b10 : $fwrite (fd, " 190");
2'b11 : $fwrite (fd, " 191");
endcase
4'h2 : $fwrite (fd, " 192");
4'h3 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 193");
2'b01 : $fwrite (fd, " 194");
2'b10 : $fwrite (fd, " 195");
2'b11 : $fwrite (fd, " 196");
endcase
4'h4 :
if (foo[26])
$fwrite (fd, " 197");
else
$fwrite (fd, " 198");
4'h5 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 199");
2'b01 : $fwrite (fd, " 200");
2'b10 : $fwrite (fd, " 201");
2'b11 : $fwrite (fd, " 202");
endcase
4'h6 : $fwrite (fd, " 203");
4'h7 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 204");
2'b01 : $fwrite (fd, " 205");
2'b10 : $fwrite (fd, " 206");
2'b11 : $fwrite (fd, " 207");
endcase
4'h8 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 208");
2'b01 : $fwrite (fd, " 209");
2'b10 : $fwrite (fd, " 210");
2'b11 : $fwrite (fd, " 211");
endcase
4'h9 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 212");
2'b01 : $fwrite (fd, " 213");
2'b10 : $fwrite (fd, " 214");
2'b11 : $fwrite (fd, " 215");
endcase
4'ha :
if (foo[25])
$fwrite (fd, " 216");
else
$fwrite (fd, " 217");
4'hb :
if (foo[25])
$fwrite (fd, " 218");
else
$fwrite (fd, " 219");
4'hc :
if (foo[26])
$fwrite (fd, " 220");
else
$fwrite (fd, " 221");
4'hd :
case (foo[26:25])
2'b00 : $fwrite (fd, " 222");
2'b01 : $fwrite (fd, " 223");
2'b10 : $fwrite (fd, " 224");
2'b11 : $fwrite (fd, " 225");
endcase
4'he :
case (foo[26:25])
2'b00 : $fwrite (fd, " 226");
2'b01 : $fwrite (fd, " 227");
2'b10 : $fwrite (fd, " 228");
2'b11 : $fwrite (fd, " 229");
endcase
4'hf :
case (foo[26:25])
2'b00 : $fwrite (fd, " 230");
2'b01 : $fwrite (fd, " 231");
2'b10 : $fwrite (fd, " 232");
2'b11 : $fwrite (fd, " 233");
endcase
endcase
end
endtask
task ozonef1e;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[27:21])
7'h00:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 234");
$fwrite (fd, " 235");
end
7'h01:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 236");
ozoneae(foo[17:15], fd);
$fwrite (fd," 237");
$fwrite (fd, " 238");
end
7'h02:
$fwrite (fd, " 239");
7'h03:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 240");
ozoneae(foo[17:15], fd);
$fwrite (fd," 241");
$fwrite (fd, " 242");
end
7'h04:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 243");
$fwrite (fd," 244");
end
7'h05:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 245");
ozoneae(foo[17:15], fd);
$fwrite (fd," 246");
end
7'h06:
$fwrite (fd, " 247");
7'h07:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 248");
ozoneae(foo[17:15], fd);
$fwrite (fd," 249");
end
7'h08:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 250");
ozoneae(foo[17:15], fd);
$fwrite (fd," 251");
end
7'h09:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 252");
ozoneae(foo[17:15], fd);
$fwrite (fd," 253");
end
7'h0a:
begin
ozoneae(foo[17:15], fd);
$fwrite (fd," 254");
end
7'h0b:
begin
ozoneae(foo[17:15], fd);
$fwrite (fd," 255");
end
7'h0c:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 256");
end
7'h0d:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 257");
ozoneae(foo[17:15], fd);
$fwrite (fd," 258");
end
7'h0e:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 259");
ozoneae(foo[17:15], fd);
$fwrite (fd," 260");
end
7'h0f:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 261");
ozoneae(foo[17:15], fd);
$fwrite (fd," 262");
end
7'h10:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 263");
ozoneae(foo[17:15], fd);
$fwrite (fd," 264");
$fwrite (fd, " 265");
$fwrite (fd, " 266");
end
7'h11:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 267");
ozoneae(foo[17:15], fd);
$fwrite (fd," 268");
$fwrite (fd, " 269");
$fwrite (fd, " 270");
end
7'h12:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 271");
ozoneae(foo[17:15], fd);
$fwrite (fd," 272");
$fwrite (fd, " 273");
$fwrite (fd, " 274");
end
7'h13:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 275");
ozoneae(foo[17:15], fd);
$fwrite (fd," 276");
$fwrite (fd, " 277");
$fwrite (fd, " 278");
end
7'h14:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 279");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 280");
ozoneape(foo[20:18], fd);
$fwrite (fd," 281");
ozoneape(foo[17:15], fd);
$fwrite (fd," 282");
$fwrite (fd, " 283");
$fwrite (fd, " 284");
end
7'h15:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 285");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 286");
ozoneape(foo[20:18], fd);
$fwrite (fd," 287");
ozoneape(foo[17:15], fd);
$fwrite (fd," 288");
$fwrite (fd, " 289");
$fwrite (fd, " 290");
end
7'h16:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 291");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 292");
ozoneape(foo[20:18], fd);
$fwrite (fd," 293");
ozoneape(foo[17:15], fd);
$fwrite (fd," 294");
$fwrite (fd, " 295");
$fwrite (fd, " 296");
end
7'h17:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 297");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 298");
ozoneape(foo[20:18], fd);
$fwrite (fd," 299");
ozoneape(foo[17:15], fd);
$fwrite (fd," 300");
$fwrite (fd, " 301");
$fwrite (fd, " 302");
end
7'h18:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 303");
ozoneae(foo[17:15], fd);
$fwrite (fd," 304");
$fwrite (fd, " 305");
$fwrite (fd, " 306");
end
7'h19:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 307");
ozoneae(foo[17:15], fd);
$fwrite (fd," 308");
$fwrite (fd, " 309");
$fwrite (fd, " 310");
end
7'h1a:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 311");
ozoneae(foo[17:15], fd);
$fwrite (fd," 312");
$fwrite (fd, " 313");
$fwrite (fd, " 314");
end
7'h1b:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 315");
ozoneae(foo[17:15], fd);
$fwrite (fd," 316");
$fwrite (fd, " 317");
$fwrite (fd, " 318");
end
7'h1c:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 319");
ozoneae(foo[17:15], fd);
$fwrite (fd," 320");
$fwrite (fd, " 321");
$fwrite (fd, " 322");
end
7'h1d:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 323");
ozoneae(foo[17:15], fd);
$fwrite (fd," 324");
$fwrite (fd, " 325");
$fwrite (fd, " 326");
end
7'h1e:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 327");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 328");
ozoneape(foo[20:18], fd);
$fwrite (fd," 329");
ozoneape(foo[17:15], fd);
$fwrite (fd," 330");
$fwrite (fd, " 331");
$fwrite (fd, " 332");
end
7'h1f:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 333");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 334");
ozoneape(foo[20:18], fd);
$fwrite (fd," 335");
ozoneape(foo[17:15], fd);
$fwrite (fd," 336");
$fwrite (fd, " 337");
$fwrite (fd, " 338");
end
7'h20:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 339");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 340");
ozoneape(foo[20:18], fd);
$fwrite (fd," 341");
ozoneape(foo[17:15], fd);
$fwrite (fd," 342");
$fwrite (fd, " 343");
$fwrite (fd, " 344");
end
7'h21:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 345");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 346");
ozoneape(foo[20:18], fd);
$fwrite (fd," 347");
ozoneape(foo[17:15], fd);
$fwrite (fd," 348");
$fwrite (fd, " 349");
$fwrite (fd, " 350");
end
7'h22:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 351");
ozoneae(foo[17:15], fd);
$fwrite (fd," 352");
$fwrite (fd, " 353");
$fwrite (fd, " 354");
end
7'h23:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 355");
ozoneae(foo[17:15], fd);
$fwrite (fd," 356");
$fwrite (fd, " 357");
$fwrite (fd, " 358");
end
7'h24:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 359");
ozoneae(foo[17:15], fd);
$fwrite (fd," 360");
$fwrite (fd, " 361");
$fwrite (fd, " 362");
end
7'h25:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 363");
ozoneae(foo[17:15], fd);
$fwrite (fd," 364");
$fwrite (fd, " 365");
$fwrite (fd, " 366");
end
7'h26:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 367");
ozoneae(foo[17:15], fd);
$fwrite (fd," 368");
$fwrite (fd, " 369");
$fwrite (fd, " 370");
end
7'h27:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 371");
ozoneae(foo[17:15], fd);
$fwrite (fd," 372");
$fwrite (fd, " 373");
$fwrite (fd, " 374");
end
7'h28:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 375");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 376");
ozoneape(foo[20:18], fd);
$fwrite (fd," 377");
ozoneape(foo[17:15], fd);
$fwrite (fd," 378");
$fwrite (fd, " 379");
$fwrite (fd, " 380");
end
7'h29:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 381");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 382");
ozoneape(foo[20:18], fd);
$fwrite (fd," 383");
ozoneape(foo[17:15], fd);
$fwrite (fd," 384");
$fwrite (fd, " 385");
$fwrite (fd, " 386");
end
7'h2a:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 387");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 388");
ozoneape(foo[20:18], fd);
$fwrite (fd," 389");
ozoneape(foo[17:15], fd);
$fwrite (fd," 390");
$fwrite (fd, " 391");
$fwrite (fd, " 392");
end
7'h2b:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 393");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 394");
ozoneape(foo[20:18], fd);
$fwrite (fd," 395");
ozoneape(foo[17:15], fd);
$fwrite (fd," 396");
$fwrite (fd, " 397");
$fwrite (fd, " 398");
end
7'h2c:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 399");
ozoneae(foo[17:15], fd);
$fwrite (fd," 400");
$fwrite (fd, " 401");
$fwrite (fd, " 402");
end
7'h2d:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 403");
ozoneae(foo[17:15], fd);
$fwrite (fd," 404");
$fwrite (fd, " 405");
$fwrite (fd, " 406");
end
7'h2e:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 407");
ozoneae(foo[17:15], fd);
$fwrite (fd," 408");
$fwrite (fd, " 409");
$fwrite (fd, " 410");
end
7'h2f:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 411");
ozoneae(foo[17:15], fd);
$fwrite (fd," 412");
$fwrite (fd, " 413");
$fwrite (fd, " 414");
end
7'h30:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 415");
ozoneae(foo[17:15], fd);
$fwrite (fd," 416");
$fwrite (fd, " 417");
$fwrite (fd, " 418");
end
7'h31:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 419");
ozoneae(foo[17:15], fd);
$fwrite (fd," 420");
$fwrite (fd, " 421");
$fwrite (fd, " 422");
end
7'h32:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 423");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 424");
ozoneape(foo[20:18], fd);
$fwrite (fd," 425");
ozoneape(foo[17:15], fd);
$fwrite (fd," 426");
$fwrite (fd, " 427");
$fwrite (fd, " 428");
end
7'h33:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 429");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 430");
ozoneape(foo[20:18], fd);
$fwrite (fd," 431");
ozoneape(foo[17:15], fd);
$fwrite (fd," 432");
$fwrite (fd, " 433");
$fwrite (fd, " 434");
end
7'h34:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 435");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 436");
ozoneape(foo[20:18], fd);
$fwrite (fd," 437");
ozoneape(foo[17:15], fd);
$fwrite (fd," 438");
$fwrite (fd, " 439");
$fwrite (fd, " 440");
end
7'h35:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 441");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 442");
ozoneape(foo[20:18], fd);
$fwrite (fd," 443");
ozoneape(foo[17:15], fd);
$fwrite (fd," 444");
$fwrite (fd, " 445");
$fwrite (fd, " 446");
end
7'h36:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 447");
ozoneae(foo[17:15], fd);
$fwrite (fd," 448");
$fwrite (fd, " 449");
$fwrite (fd, " 450");
end
7'h37:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 451");
ozoneae(foo[17:15], fd);
$fwrite (fd," 452");
$fwrite (fd, " 453");
$fwrite (fd, " 454");
end
7'h38:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 455");
ozoneae(foo[17:15], fd);
$fwrite (fd," 456");
$fwrite (fd, " 457");
end
7'h39:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 458");
ozoneae(foo[17:15], fd);
$fwrite (fd," 459");
$fwrite (fd, " 460");
end
7'h3a:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 461");
ozoneae(foo[17:15], fd);
$fwrite (fd," 462");
$fwrite (fd, " 463");
end
7'h3b:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 464");
ozoneae(foo[17:15], fd);
$fwrite (fd," 465");
$fwrite (fd, " 466");
end
7'h3c:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 467");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 468");
ozoneape(foo[20:18], fd);
$fwrite (fd," 469");
ozoneape(foo[17:15], fd);
$fwrite (fd," 470");
$fwrite (fd, " 471");
end
7'h3d:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 472");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 473");
ozoneape(foo[20:18], fd);
$fwrite (fd," 474");
ozoneape(foo[17:15], fd);
$fwrite (fd," 475");
$fwrite (fd, " 476");
end
7'h3e:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 477");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 478");
ozoneape(foo[20:18], fd);
$fwrite (fd," 479");
ozoneape(foo[17:15], fd);
$fwrite (fd," 480");
$fwrite (fd, " 481");
end
7'h3f:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 482");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 483");
ozoneape(foo[20:18], fd);
$fwrite (fd," 484");
ozoneape(foo[17:15], fd);
$fwrite (fd," 485");
$fwrite (fd, " 486");
end
7'h40:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 487");
ozoneae(foo[17:15], fd);
$fwrite (fd," 488");
$fwrite (fd, " 489");
$fwrite (fd, " 490");
end
7'h41:
begin
$fwrite (fd, " 491");
$fwrite (fd, " 492");
end
7'h42:
begin
$fwrite (fd, " 493");
$fwrite (fd, " 494");
end
7'h43:
begin
$fwrite (fd, " 495");
$fwrite (fd, " 496");
end
7'h44:
begin
$fwrite (fd, " 497");
$fwrite (fd, " 498");
end
7'h45:
$fwrite (fd, " 499");
7'h46:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 500");
$fwrite (fd, " 501");
$fwrite (fd, " 502");
end
7'h47:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 503");
ozoneae(foo[17:15], fd);
$fwrite (fd," 504");
ozoneape(foo[20:18], fd);
$fwrite (fd," 505");
ozoneape(foo[20:18], fd);
$fwrite (fd," 506");
$fwrite (fd, " 507");
$fwrite (fd, " 508");
end
7'h48:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 509");
ozoneape(foo[20:18], fd);
$fwrite (fd," 510");
ozoneape(foo[20:18], fd);
$fwrite (fd," 511");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 512");
ozoneape(foo[17:15], fd);
$fwrite (fd," 513");
end
7'h49:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 514");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 515");
ozoneape(foo[17:15], fd);
$fwrite (fd," 516");
end
7'h4a:
$fwrite (fd," 517");
7'h4b:
$fwrite (fd, " 518");
7'h4c:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 519");
$fwrite (fd, " 520");
$fwrite (fd, " 521");
end
7'h4d:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 522");
ozoneae(foo[17:15], fd);
$fwrite (fd," 523");
ozoneape(foo[20:18], fd);
$fwrite (fd," 524");
ozoneape(foo[20:18], fd);
$fwrite (fd," 525");
$fwrite (fd, " 526");
$fwrite (fd, " 527");
end
7'h4e:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 528");
ozoneae(foo[17:15], fd);
$fwrite (fd," 529");
ozoneape(foo[20:18], fd);
$fwrite (fd," 530");
ozoneape(foo[20:18], fd);
$fwrite (fd," 531");
end
7'h4f:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 532");
end
7'h50:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 533");
ozoneae(foo[17:15], fd);
$fwrite (fd," 534");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 535");
ozoneae(foo[17:15], fd);
$fwrite (fd," 536");
ozoneape(foo[20:18], fd);
$fwrite (fd," 537");
ozoneae(foo[17:15], fd);
$fwrite (fd," 538");
ozoneape(foo[20:18], fd);
$fwrite (fd," 539");
ozoneae(foo[17:15], fd);
$fwrite (fd," 540");
end
7'h51:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 541");
ozoneape(foo[20:18], fd);
$fwrite (fd," 542");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 543");
ozoneape(foo[20:18], fd);
$fwrite (fd," 544");
ozoneae(foo[17:15], fd);
$fwrite (fd," 545");
end
7'h52:
$fwrite (fd, " 546");
7'h53:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 547");
end
7'h54:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 548");
ozoneae(foo[17:15], fd);
$fwrite (fd," 549");
end
7'h55:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 550");
ozoneae(foo[17:15], fd);
$fwrite (fd," 551");
end
7'h56:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 552");
ozoneae(foo[17:15], fd);
$fwrite (fd," 553");
$fwrite (fd, " 554");
end
7'h57:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 555");
ozoneae(foo[17:15], fd);
$fwrite (fd," 556");
ozoneape(foo[20:18], fd);
$fwrite (fd," 557");
ozoneape(foo[20:18], fd);
$fwrite (fd," 558");
end
7'h58:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 559");
end
7'h59:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 560");
ozoneae(foo[17:15], fd);
$fwrite (fd," 561");
ozoneape(foo[20:18], fd);
$fwrite (fd," 562");
ozoneape(foo[20:18], fd);
$fwrite (fd," 563");
end
7'h5a:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 564");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 565");
end
7'h5b:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 566");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 567");
end
7'h5c:
begin
$fwrite (fd," 568");
ozoneape(foo[17:15], fd);
$fwrite (fd," 569");
$fwrite (fd," 570");
ozoneape(foo[17:15], fd);
$fwrite (fd," 571");
ozoneae(foo[20:18], fd);
$fwrite (fd," 572");
ozoneaee(foo[17:15], fd);
$fwrite (fd, " 573");
end
7'h5d:
begin
$fwrite (fd," 574");
ozoneape(foo[17:15], fd);
$fwrite (fd," 575");
$fwrite (fd," 576");
ozoneape(foo[17:15], fd);
$fwrite (fd," 577");
ozoneae(foo[20:18], fd);
$fwrite (fd," 578");
ozoneaee(foo[17:15], fd);
$fwrite (fd, " 579");
end
7'h5e:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 580");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 581");
end
7'h5f:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 582");
ozoneae(foo[17:15], fd);
$fwrite (fd," 583");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 584");
ozoneae(foo[17:15], fd);
$fwrite (fd," 585");
ozoneape(foo[20:18], fd);
$fwrite (fd," 586");
ozoneae(foo[17:15], fd);
$fwrite (fd," 587");
ozoneape(foo[20:18], fd);
$fwrite (fd," 588");
ozoneae(foo[17:15], fd);
$fwrite (fd," 589");
end
7'h60:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 590");
ozoneae(foo[17:15], fd);
$fwrite (fd," 591");
end
7'h61:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 592");
ozoneae(foo[17:15], fd);
$fwrite (fd," 593");
end
7'h62:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 594");
ozoneae(foo[17:15], fd);
$fwrite (fd," 595");
end
7'h63:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 596");
ozoneae(foo[17:15], fd);
$fwrite (fd," 597");
end
7'h64:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 598");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 599");
ozoneape(foo[20:18], fd);
$fwrite (fd," 600");
ozoneape(foo[17:15], fd);
$fwrite (fd," 601");
end
7'h65:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 602");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 603");
ozoneape(foo[20:18], fd);
$fwrite (fd," 604");
ozoneape(foo[17:15], fd);
$fwrite (fd," 605");
end
7'h66:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 606");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 607");
ozoneape(foo[20:18], fd);
$fwrite (fd," 608");
ozoneape(foo[17:15], fd);
$fwrite (fd," 609");
end
7'h67:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 610");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 611");
ozoneape(foo[20:18], fd);
$fwrite (fd," 612");
ozoneape(foo[17:15], fd);
$fwrite (fd," 613");
end
7'h68:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 614");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 615");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 616");
ozoneape(foo[20:18], fd);
$fwrite (fd," 617");
ozoneape(foo[20:18], fd);
$fwrite (fd," 618");
ozoneape(foo[17:15], fd);
end
7'h69:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 619");
ozoneae(foo[17:15], fd);
$fwrite (fd," 620");
ozoneae(foo[20:18], fd);
$fwrite (fd," 621");
end
7'h6a:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 622");
ozoneae(foo[17:15], fd);
$fwrite (fd," 623");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 624");
ozoneape(foo[20:18], fd);
$fwrite (fd," 625");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 626");
ozoneae(foo[17:15], fd);
end
7'h6b:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 627");
ozoneae(foo[17:15], fd);
$fwrite (fd," 628");
ozoneae(foo[20:18], fd);
$fwrite (fd," 629");
end
7'h6c:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 630");
ozoneae(foo[17:15], fd);
$fwrite (fd," 631");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 632");
ozoneape(foo[20:18], fd);
$fwrite (fd," 633");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 634");
ozoneae(foo[17:15], fd);
end
7'h6d:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 635");
ozoneae(foo[17:15], fd);
$fwrite (fd," 636");
ozoneae(foo[20:18], fd);
$fwrite (fd," 637");
end
7'h6e:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 638");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 639");
ozoneape(foo[20:18], fd);
$fwrite (fd," 640");
ozoneape(foo[17:15], fd);
$fwrite (fd," 641");
end
7'h6f:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 642");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 643");
ozoneape(foo[20:18], fd);
$fwrite (fd," 644");
ozoneape(foo[17:15], fd);
$fwrite (fd," 645");
end
7'h70:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 646");
ozoneae(foo[20:18], fd);
$fwrite (fd," 647");
ozoneae(foo[17:15], fd);
$fwrite (fd," 648");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 649");
end
7'h71:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 650");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 651");
end
7'h72:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 652");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 653");
end
7'h73:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 654");
ozoneae(foo[20:18], fd);
$fwrite (fd," 655");
ozoneae(foo[17:15], fd);
end
7'h74:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 656");
ozoneae(foo[20:18], fd);
$fwrite (fd," 657");
ozoneae(foo[17:15], fd);
end
7'h75:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 658");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 659");
ozoneape(foo[20:18], fd);
$fwrite (fd," 660");
ozoneape(foo[17:15], fd);
$fwrite (fd," 661");
$fwrite (fd, " 662");
$fwrite (fd, " 663");
end
7'h76:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 664");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 665");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 666");
ozoneape(foo[20:18], fd);
$fwrite (fd," 667");
ozoneape(foo[17:15], fd);
$fwrite (fd," 668");
ozoneape(foo[20:18], fd);
$fwrite (fd," 669");
end
7'h77:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 670");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 671");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 672");
ozoneape(foo[20:18], fd);
$fwrite (fd," 673");
ozoneape(foo[17:15], fd);
$fwrite (fd," 674");
ozoneape(foo[17:15], fd);
$fwrite (fd," 675");
end
7'h78,
7'h79,
7'h7a,
7'h7b,
7'h7c,
7'h7d,
7'h7e,
7'h7f:
$fwrite (fd," 676");
endcase
end
endtask
task ozonef2;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[24:21])
4'h0 :
case (foo[26:25])
2'b00 : $fwrite (fd," 677");
2'b01 : $fwrite (fd," 678");
2'b10 : $fwrite (fd," 679");
2'b11 : $fwrite (fd," 680");
endcase
4'h1 :
case (foo[26:25])
2'b00 : $fwrite (fd," 681");
2'b01 : $fwrite (fd," 682");
2'b10 : $fwrite (fd," 683");
2'b11 : $fwrite (fd," 684");
endcase
4'h2 :
case (foo[26:25])
2'b00 : $fwrite (fd," 685");
2'b01 : $fwrite (fd," 686");
2'b10 : $fwrite (fd," 687");
2'b11 : $fwrite (fd," 688");
endcase
4'h3 :
case (foo[26:25])
2'b00 : $fwrite (fd," 689");
2'b01 : $fwrite (fd," 690");
2'b10 : $fwrite (fd," 691");
2'b11 : $fwrite (fd," 692");
endcase
4'h4 :
case (foo[26:25])
2'b00 : $fwrite (fd," 693");
2'b01 : $fwrite (fd," 694");
2'b10 : $fwrite (fd," 695");
2'b11 : $fwrite (fd," 696");
endcase
4'h5 :
case (foo[26:25])
2'b00 : $fwrite (fd," 697");
2'b01 : $fwrite (fd," 698");
2'b10 : $fwrite (fd," 699");
2'b11 : $fwrite (fd," 700");
endcase
4'h6 :
case (foo[26:25])
2'b00 : $fwrite (fd," 701");
2'b01 : $fwrite (fd," 702");
2'b10 : $fwrite (fd," 703");
2'b11 : $fwrite (fd," 704");
endcase
4'h7 :
case (foo[26:25])
2'b00 : $fwrite (fd," 705");
2'b01 : $fwrite (fd," 706");
2'b10 : $fwrite (fd," 707");
2'b11 : $fwrite (fd," 708");
endcase
4'h8 :
if (foo[26])
$fwrite (fd," 709");
else
$fwrite (fd," 710");
4'h9 :
case (foo[26:25])
2'b00 : $fwrite (fd," 711");
2'b01 : $fwrite (fd," 712");
2'b10 : $fwrite (fd," 713");
2'b11 : $fwrite (fd," 714");
endcase
4'ha :
case (foo[26:25])
2'b00 : $fwrite (fd," 715");
2'b01 : $fwrite (fd," 716");
2'b10 : $fwrite (fd," 717");
2'b11 : $fwrite (fd," 718");
endcase
4'hb :
case (foo[26:25])
2'b00 : $fwrite (fd," 719");
2'b01 : $fwrite (fd," 720");
2'b10 : $fwrite (fd," 721");
2'b11 : $fwrite (fd," 722");
endcase
4'hc :
if (foo[26])
$fwrite (fd," 723");
else
$fwrite (fd," 724");
4'hd :
case (foo[26:25])
2'b00 : $fwrite (fd," 725");
2'b01 : $fwrite (fd," 726");
2'b10 : $fwrite (fd," 727");
2'b11 : $fwrite (fd," 728");
endcase
4'he :
case (foo[26:25])
2'b00 : $fwrite (fd," 729");
2'b01 : $fwrite (fd," 730");
2'b10 : $fwrite (fd," 731");
2'b11 : $fwrite (fd," 732");
endcase
4'hf :
case (foo[26:25])
2'b00 : $fwrite (fd," 733");
2'b01 : $fwrite (fd," 734");
2'b10 : $fwrite (fd," 735");
2'b11 : $fwrite (fd," 736");
endcase
endcase
end
endtask
task ozonef2e;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
casez (foo[25:21])
5'h00 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 737");
ozoneae(foo[17:15], fd);
$fwrite (fd," 738");
end
5'h01 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 739");
ozoneae(foo[17:15], fd);
$fwrite (fd," 740");
end
5'h02 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 741");
ozoneae(foo[17:15], fd);
$fwrite (fd," 742");
end
5'h03 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 743");
ozoneae(foo[17:15], fd);
$fwrite (fd," 744");
end
5'h04 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 745");
ozoneae(foo[17:15], fd);
$fwrite (fd," 746");
end
5'h05 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 747");
ozoneae(foo[17:15], fd);
$fwrite (fd," 748");
end
5'h06 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 749");
ozoneae(foo[17:15], fd);
$fwrite (fd," 750");
end
5'h07 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 751");
ozoneae(foo[17:15], fd);
$fwrite (fd," 752");
end
5'h08 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 753");
if (foo[ 6])
$fwrite (fd," 754");
else
$fwrite (fd," 755");
end
5'h09 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 756");
ozoneae(foo[17:15], fd);
$fwrite (fd," 757");
end
5'h0a :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 758");
ozoneae(foo[17:15], fd);
end
5'h0b :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 759");
ozoneae(foo[17:15], fd);
$fwrite (fd," 760");
end
5'h0c :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 761");
end
5'h0d :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 762");
ozoneae(foo[17:15], fd);
$fwrite (fd," 763");
end
5'h0e :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 764");
ozoneae(foo[17:15], fd);
end
5'h0f :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 765");
ozoneae(foo[17:15], fd);
end
5'h10 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 766");
ozoneae(foo[17:15], fd);
$fwrite (fd," 767");
end
5'h11 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 768");
ozoneae(foo[17:15], fd);
$fwrite (fd," 769");
end
5'h18 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 770");
if (foo[ 6])
$fwrite (fd," 771");
else
$fwrite (fd," 772");
end
5'h1a :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 773");
ozoneae(foo[17:15], fd);
$fwrite (fd," 774");
end
5'h1b :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 775");
ozoneae(foo[17:15], fd);
$fwrite (fd," 776");
if (foo[ 6])
$fwrite (fd," 777");
else
$fwrite (fd," 778");
$fwrite (fd," 779");
end
5'h1c :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 780");
end
5'h1d :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 781");
if (foo[ 6])
$fwrite (fd," 782");
else
$fwrite (fd," 783");
$fwrite (fd," 784");
end
5'h1e :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 785");
if (foo[ 6])
$fwrite (fd," 786");
else
$fwrite (fd," 787");
$fwrite (fd," 788");
end
5'h1f :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 789");
ozoneae(foo[17:15], fd);
$fwrite (fd," 790");
if (foo[ 6])
$fwrite (fd," 791");
else
$fwrite (fd," 792");
$fwrite (fd," 793");
end
default :
$fwrite (fd," 794");
endcase
end
endtask
task ozonef3e;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[25:21])
5'h00,
5'h01,
5'h02:
begin
ozoneae(foo[20:18], fd);
case (foo[22:21])
2'h0: $fwrite (fd," 795");
2'h1: $fwrite (fd," 796");
2'h2: $fwrite (fd," 797");
endcase
ozoneae(foo[17:15], fd);
$fwrite (fd," 798");
if (foo[ 9])
ozoneae(foo[ 8: 6], fd);
else
ozonef3e_te(foo[ 8: 6], fd);
$fwrite (fd," 799");
end
5'h08,
5'h09,
5'h0d,
5'h0e,
5'h0f:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 800");
ozoneae(foo[17:15], fd);
case (foo[23:21])
3'h0: $fwrite (fd," 801");
3'h1: $fwrite (fd," 802");
3'h5: $fwrite (fd," 803");
3'h6: $fwrite (fd," 804");
3'h7: $fwrite (fd," 805");
endcase
if (foo[ 9])
ozoneae(foo[ 8: 6], fd);
else
ozonef3e_te(foo[ 8: 6], fd);
end
5'h0a,
5'h0b:
begin
ozoneae(foo[17:15], fd);
if (foo[21])
$fwrite (fd," 806");
else
$fwrite (fd," 807");
if (foo[ 9])
ozoneae(foo[ 8: 6], fd);
else
ozonef3e_te(foo[ 8: 6], fd);
end
5'h0c:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 808");
if (foo[ 9])
ozoneae(foo[ 8: 6], fd);
else
ozonef3e_te(foo[ 8: 6], fd);
$fwrite (fd," 809");
ozoneae(foo[17:15], fd);
end
5'h10,
5'h11,
5'h12,
5'h13:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 810");
ozoneae(foo[17:15], fd);
case (foo[22:21])
2'h0,
2'h2:
$fwrite (fd," 811");
2'h1,
2'h3:
$fwrite (fd," 812");
endcase
ozoneae(foo[ 8: 6], fd);
$fwrite (fd," 813");
ozoneae((foo[20:18]+1), fd);
$fwrite (fd," 814");
ozoneae((foo[17:15]+1), fd);
case (foo[22:21])
2'h0,
2'h3:
$fwrite (fd," 815");
2'h1,
2'h2:
$fwrite (fd," 816");
endcase
ozoneae((foo[ 8: 6]+1), fd);
end
5'h18:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 817");
ozoneae(foo[17:15], fd);
$fwrite (fd," 818");
ozoneae(foo[ 8: 6], fd);
$fwrite (fd," 819");
ozoneae(foo[20:18], fd);
$fwrite (fd," 820");
ozoneae(foo[17:15], fd);
$fwrite (fd," 821");
ozoneae(foo[ 8: 6], fd);
end
default :
$fwrite (fd," 822");
endcase
end
endtask
task ozonef3e_te;
input [ 2:0] te;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (te)
3'b100 : $fwrite (fd, " 823");
3'b101 : $fwrite (fd, " 824");
3'b110 : $fwrite (fd, " 825");
default: $fwrite (fd, " 826");
endcase
end
endtask
task ozonearm;
input [ 2:0] ate;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (ate)
3'b000 : $fwrite (fd, " 827");
3'b001 : $fwrite (fd, " 828");
3'b010 : $fwrite (fd, " 829");
3'b011 : $fwrite (fd, " 830");
3'b100 : $fwrite (fd, " 831");
3'b101 : $fwrite (fd, " 832");
3'b110 : $fwrite (fd, " 833");
3'b111 : $fwrite (fd, " 834");
endcase
end
endtask
task ozonebmuop;
input [ 4:0] f4;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (f4[ 4:0])
5'h00,
5'h04 :
$fwrite (fd, " 835");
5'h01,
5'h05 :
$fwrite (fd, " 836");
5'h02,
5'h06 :
$fwrite (fd, " 837");
5'h03,
5'h07 :
$fwrite (fd, " 838");
5'h08,
5'h18 :
$fwrite (fd, " 839");
5'h09,
5'h19 :
$fwrite (fd, " 840");
5'h0a,
5'h1a :
$fwrite (fd, " 841");
5'h0b :
$fwrite (fd, " 842");
5'h1b :
$fwrite (fd, " 843");
5'h0c,
5'h1c :
$fwrite (fd, " 844");
5'h0d,
5'h1d :
$fwrite (fd, " 845");
5'h1e :
$fwrite (fd, " 846");
endcase
end
endtask
task ozonef3;
input [ 31:0] foo;
input [`FD_BITS] fd;
reg nacho;
// verilator no_inline_task
begin : f3_body
nacho = 1'b0;
case (foo[24:21])
4'h0:
case (foo[26:25])
2'b00 : $fwrite (fd, " 847");
2'b01 : $fwrite (fd, " 848");
2'b10 : $fwrite (fd, " 849");
2'b11 : $fwrite (fd, " 850");
endcase
4'h1:
case (foo[26:25])
2'b00 : $fwrite (fd, " 851");
2'b01 : $fwrite (fd, " 852");
2'b10 : $fwrite (fd, " 853");
2'b11 : $fwrite (fd, " 854");
endcase
4'h2:
case (foo[26:25])
2'b00 : $fwrite (fd, " 855");
2'b01 : $fwrite (fd, " 856");
2'b10 : $fwrite (fd, " 857");
2'b11 : $fwrite (fd, " 858");
endcase
4'h8,
4'h9,
4'hd,
4'he,
4'hf :
case (foo[26:25])
2'b00 : $fwrite (fd, " 859");
2'b01 : $fwrite (fd, " 860");
2'b10 : $fwrite (fd, " 861");
2'b11 : $fwrite (fd, " 862");
endcase
4'ha,
4'hb :
if (foo[25])
$fwrite (fd, " 863");
else
$fwrite (fd, " 864");
4'hc :
if (foo[26])
$fwrite (fd, " 865");
else
$fwrite (fd, " 866");
default :
begin
$fwrite (fd, " 867");
nacho = 1'b1;
end
endcase
if (~nacho)
begin
case (foo[24:21])
4'h8 :
$fwrite (fd, " 868");
4'h9 :
$fwrite (fd, " 869");
4'ha,
4'he :
$fwrite (fd, " 870");
4'hb,
4'hf :
$fwrite (fd, " 871");
4'hd :
$fwrite (fd, " 872");
endcase
if (foo[20])
case (foo[18:16])
3'b000 : $fwrite (fd, " 873");
3'b100 : $fwrite (fd, " 874");
default: $fwrite (fd, " 875");
endcase
else
ozoneae(foo[18:16], fd);
if (foo[24:21] === 4'hc)
if (foo[25])
$fwrite (fd, " 876");
else
$fwrite (fd, " 877");
case (foo[24:21])
4'h0,
4'h1,
4'h2:
$fwrite (fd, " 878");
endcase
end
end
endtask
task ozonerx;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[19:18])
2'h0 : $fwrite (fd, " 879");
2'h1 : $fwrite (fd, " 880");
2'h2 : $fwrite (fd, " 881");
2'h3 : $fwrite (fd, " 882");
endcase
case (foo[17:16])
2'h1 : $fwrite (fd, " 883");
2'h2 : $fwrite (fd, " 884");
2'h3 : $fwrite (fd, " 885");
endcase
end
endtask
task ozonerme;
input [ 2:0] rme;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (rme)
3'h0 : $fwrite (fd, " 886");
3'h1 : $fwrite (fd, " 887");
3'h2 : $fwrite (fd, " 888");
3'h3 : $fwrite (fd, " 889");
3'h4 : $fwrite (fd, " 890");
3'h5 : $fwrite (fd, " 891");
3'h6 : $fwrite (fd, " 892");
3'h7 : $fwrite (fd, " 893");
endcase
end
endtask
task ozoneye;
input [5:0] ye;
input l;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
$fwrite (fd, " 894");
ozonerme(ye[5:3], fd);
case ({ye[ 2:0], l})
4'h2,
4'ha: $fwrite (fd, " 895");
4'h4,
4'hb: $fwrite (fd, " 896");
4'h6,
4'he: $fwrite (fd, " 897");
4'h8,
4'hc: $fwrite (fd, " 898");
endcase
end
endtask
task ozonef1e_ye;
input [5:0] ye;
input l;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
$fwrite (fd, " 899");
ozonerme(ye[5:3], fd);
ozonef1e_inc_dec(ye[5:0], l , fd);
end
endtask
task ozonef1e_h;
input [ 2:0] e;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
if (e[ 2:0] <= 3'h4)
$fwrite (fd, " 900");
end
endtask
task ozonef1e_inc_dec;
input [5:0] ye;
input l;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case ({ye[ 2:0], l})
4'h2,
4'h3,
4'ha: $fwrite (fd, " 901");
4'h4,
4'h5,
4'hb: $fwrite (fd, " 902");
4'h6,
4'h7,
4'he: $fwrite (fd, " 903");
4'h8,
4'h9,
4'hc: $fwrite (fd, " 904");
4'hf: $fwrite (fd, " 905");
endcase
end
endtask
task ozonef1e_hl;
input [ 2:0] e;
input l;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case ({e[ 2:0], l})
4'h0,
4'h2,
4'h4,
4'h6,
4'h8: $fwrite (fd, " 906");
4'h1,
4'h3,
4'h5,
4'h7,
4'h9: $fwrite (fd, " 907");
endcase
end
endtask
task ozonexe;
input [ 3:0] xe;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (xe[3])
1'b0 : $fwrite (fd, " 908");
1'b1 : $fwrite (fd, " 909");
endcase
case (xe[ 2:0])
3'h1,
3'h5: $fwrite (fd, " 910");
3'h2,
3'h6: $fwrite (fd, " 911");
3'h3,
3'h7: $fwrite (fd, " 912");
3'h4: $fwrite (fd, " 913");
endcase
end
endtask
task ozonerp;
input [ 2:0] rp;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (rp)
3'h0 : $fwrite (fd, " 914");
3'h1 : $fwrite (fd, " 915");
3'h2 : $fwrite (fd, " 916");
3'h3 : $fwrite (fd, " 917");
3'h4 : $fwrite (fd, " 918");
3'h5 : $fwrite (fd, " 919");
3'h6 : $fwrite (fd, " 920");
3'h7 : $fwrite (fd, " 921");
endcase
end
endtask
task ozonery;
input [ 3:0] ry;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (ry)
4'h0 : $fwrite (fd, " 922");
4'h1 : $fwrite (fd, " 923");
4'h2 : $fwrite (fd, " 924");
4'h3 : $fwrite (fd, " 925");
4'h4 : $fwrite (fd, " 926");
4'h5 : $fwrite (fd, " 927");
4'h6 : $fwrite (fd, " 928");
4'h7 : $fwrite (fd, " 929");
4'h8 : $fwrite (fd, " 930");
4'h9 : $fwrite (fd, " 931");
4'ha : $fwrite (fd, " 932");
4'hb : $fwrite (fd, " 933");
4'hc : $fwrite (fd, " 934");
4'hd : $fwrite (fd, " 935");
4'he : $fwrite (fd, " 936");
4'hf : $fwrite (fd, " 937");
endcase
end
endtask
task ozonearx;
input [ 15:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[1:0])
2'h0 : $fwrite (fd, " 938");
2'h1 : $fwrite (fd, " 939");
2'h2 : $fwrite (fd, " 940");
2'h3 : $fwrite (fd, " 941");
endcase
end
endtask
task ozonef3f4imop;
input [ 4:0] f3f4iml;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
casez (f3f4iml)
5'b000??: $fwrite (fd, " 942");
5'b001??: $fwrite (fd, " 943");
5'b?10??: $fwrite (fd, " 944");
5'b0110?: $fwrite (fd, " 945");
5'b01110: $fwrite (fd, " 946");
5'b01111: $fwrite (fd, " 947");
5'b10???: $fwrite (fd, " 948");
5'b11100: $fwrite (fd, " 949");
5'b11101: $fwrite (fd, " 950");
5'b11110: $fwrite (fd, " 951");
5'b11111: $fwrite (fd, " 952");
endcase
end
endtask
task ozonecon;
input [ 4:0] con;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (con)
5'h00 : $fwrite (fd, " 953");
5'h01 : $fwrite (fd, " 954");
5'h02 : $fwrite (fd, " 955");
5'h03 : $fwrite (fd, " 956");
5'h04 : $fwrite (fd, " 957");
5'h05 : $fwrite (fd, " 958");
5'h06 : $fwrite (fd, " 959");
5'h07 : $fwrite (fd, " 960");
5'h08 : $fwrite (fd, " 961");
5'h09 : $fwrite (fd, " 962");
5'h0a : $fwrite (fd, " 963");
5'h0b : $fwrite (fd, " 964");
5'h0c : $fwrite (fd, " 965");
5'h0d : $fwrite (fd, " 966");
5'h0e : $fwrite (fd, " 967");
5'h0f : $fwrite (fd, " 968");
5'h10 : $fwrite (fd, " 969");
5'h11 : $fwrite (fd, " 970");
5'h12 : $fwrite (fd, " 971");
5'h13 : $fwrite (fd, " 972");
5'h14 : $fwrite (fd, " 973");
5'h15 : $fwrite (fd, " 974");
5'h16 : $fwrite (fd, " 975");
5'h17 : $fwrite (fd, " 976");
5'h18 : $fwrite (fd, " 977");
5'h19 : $fwrite (fd, " 978");
5'h1a : $fwrite (fd, " 979");
5'h1b : $fwrite (fd, " 980");
5'h1c : $fwrite (fd, " 981");
5'h1d : $fwrite (fd, " 982");
5'h1e : $fwrite (fd, " 983");
5'h1f : $fwrite (fd, " 984");
endcase
end
endtask
task ozonedr;
input [ 15:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[ 9: 6])
4'h0 : $fwrite (fd, " 985");
4'h1 : $fwrite (fd, " 986");
4'h2 : $fwrite (fd, " 987");
4'h3 : $fwrite (fd, " 988");
4'h4 : $fwrite (fd, " 989");
4'h5 : $fwrite (fd, " 990");
4'h6 : $fwrite (fd, " 991");
4'h7 : $fwrite (fd, " 992");
4'h8 : $fwrite (fd, " 993");
4'h9 : $fwrite (fd, " 994");
4'ha : $fwrite (fd, " 995");
4'hb : $fwrite (fd, " 996");
4'hc : $fwrite (fd, " 997");
4'hd : $fwrite (fd, " 998");
4'he : $fwrite (fd, " 999");
4'hf : $fwrite (fd, " 1000");
endcase
end
endtask
task ozoneshift;
input [ 15:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[ 4: 3])
2'h0 : $fwrite (fd, " 1001");
2'h1 : $fwrite (fd, " 1002");
2'h2 : $fwrite (fd, " 1003");
2'h3 : $fwrite (fd, " 1004");
endcase
end
endtask
task ozoneacc;
input foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo)
2'h0 : $fwrite (fd, " 1005");
2'h1 : $fwrite (fd, " 1006");
endcase
end
endtask
task ozonehl;
input foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo)
2'h0 : $fwrite (fd, " 1007");
2'h1 : $fwrite (fd, " 1008");
endcase
end
endtask
task dude;
input [`FD_BITS] fd;
// verilator no_inline_task
$fwrite(fd," dude");
endtask
task big_case;
input [ `FD_BITS] fd;
input [ 31:0] foo;
// verilator no_inline_task
begin
$fwrite(fd," 1009");
if (&foo === 1'bx)
$fwrite(fd, " 1010");
else
casez ( {foo[31:26], foo[19:15], foo[5:0]} )
17'b00_111?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1011");
ozoneacc(~foo[26], fd);
ozonehl(foo[20], fd);
$fwrite (fd, " 1012");
ozonerx(foo, fd);
dude(fd);
$fwrite (fd, " 1013");
end
17'b01_001?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1014");
ozonerx(foo, fd);
$fwrite (fd, " 1015");
$fwrite (fd, " 1016:%x", foo[20]);
ozonehl(foo[20], fd);
dude(fd);
$fwrite (fd, " 1017");
end
17'b10_100?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1018");
ozonerx(foo, fd);
$fwrite (fd, " 1019");
$fwrite (fd, " 1020");
ozonehl(foo[20], fd);
dude(fd);
$fwrite (fd, " 1021");
end
17'b10_101?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1022");
if (foo[20])
begin
$fwrite (fd, " 1023");
ozoneacc(foo[18], fd);
$fwrite (fd, " 1024");
$fwrite (fd, " 1025");
if (foo[19])
$fwrite (fd, " 1026");
else
$fwrite (fd, " 1027");
end
else
ozonerx(foo, fd);
dude(fd);
$fwrite (fd, " 1028");
end
17'b10_110?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1029");
$fwrite (fd, " 1030");
ozonehl(foo[20], fd);
$fwrite (fd, " 1031");
ozonerx(foo, fd);
dude(fd);
$fwrite (fd, " 1032");
end
17'b10_111?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1033");
$fwrite (fd, " 1034");
ozonehl(foo[20], fd);
$fwrite (fd, " 1035");
ozonerx(foo, fd);
dude(fd);
$fwrite (fd, " 1036");
end
17'b11_001?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1037");
ozonerx(foo, fd);
$fwrite (fd, " 1038");
$fwrite (fd, " 1039");
ozonehl(foo[20], fd);
dude(fd);
$fwrite (fd, " 1040");
end
17'b11_111?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1041");
$fwrite (fd, " 1042");
ozonerx(foo, fd);
$fwrite (fd, " 1043");
if (foo[20])
$fwrite (fd, " 1044");
else
$fwrite (fd, " 1045");
dude(fd);
$fwrite (fd, " 1046");
end
17'b00_10??_?_????_?1_1111 :
casez (foo[11: 5])
7'b??_0_010_0:
begin
$fwrite (fd, " 1047");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1048");
ozonef1e(foo, fd);
dude(fd);
$fwrite (fd, " 1049");
end
7'b00_?_110_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1050");
case ({foo[ 9],foo[ 5]})
2'b00:
begin
$fwrite (fd, " 1051");
ozoneae(foo[14:12], fd);
ozonehl(foo[ 5], fd);
end
2'b01:
begin
$fwrite (fd, " 1052");
ozoneae(foo[14:12], fd);
ozonehl(foo[ 5], fd);
end
2'b10:
begin
$fwrite (fd, " 1053");
ozoneae(foo[14:12], fd);
end
2'b11: $fwrite (fd, " 1054");
endcase
dude(fd);
$fwrite (fd, " 1055");
end
7'b01_?_110_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1056");
case ({foo[ 9],foo[ 5]})
2'b00:
begin
ozoneae(foo[14:12], fd);
ozonehl(foo[ 5], fd);
$fwrite (fd, " 1057");
end
2'b01:
begin
ozoneae(foo[14:12], fd);
ozonehl(foo[ 5], fd);
$fwrite (fd, " 1058");
end
2'b10:
begin
ozoneae(foo[14:12], fd);
$fwrite (fd, " 1059");
end
2'b11: $fwrite (fd, " 1060");
endcase
dude(fd);
$fwrite (fd, " 1061");
end
7'b10_0_110_0:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1062");
$fwrite (fd, " 1063");
if (foo[12])
$fwrite (fd, " 1064");
else
ozonerab({4'b1001, foo[14:12]}, fd);
dude(fd);
$fwrite (fd, " 1065");
end
7'b10_0_110_1:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1066");
if (foo[12])
$fwrite (fd, " 1067");
else
ozonerab({4'b1001, foo[14:12]}, fd);
$fwrite (fd, " 1068");
dude(fd);
$fwrite (fd, " 1069");
end
7'b??_?_000_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1070");
$fwrite (fd, " 1071");
ozonef1e_hl(foo[11:9],foo[ 5], fd);
$fwrite (fd, " 1072");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1073");
end
7'b??_?_100_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1074");
$fwrite (fd, " 1075");
ozonef1e_hl(foo[11:9],foo[ 5], fd);
$fwrite (fd, " 1076");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1077");
end
7'b??_?_001_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1078");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
$fwrite (fd, " 1079");
$fwrite (fd, " 1080");
ozonef1e_hl(foo[11:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1081");
end
7'b??_?_011_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1082");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
$fwrite (fd, " 1083");
$fwrite (fd, " 1084");
ozonef1e_hl(foo[11:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1085");
end
7'b??_?_101_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1086");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1087");
end
endcase
17'b00_10??_?_????_?0_0110 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1088");
ozoneae(foo[ 8: 6], fd);
ozonef1e_hl(foo[11:9],foo[ 5], fd);
$fwrite (fd, " 1089");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1090");
end
17'b00_10??_?_????_00_0111 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1091");
if (foo[ 6])
$fwrite (fd, " 1092");
else
ozonerab({4'b1001, foo[ 8: 6]}, fd);
$fwrite (fd, " 1093");
$fwrite (fd, " 1094");
ozonerme(foo[14:12], fd);
case (foo[11: 9])
3'h2,
3'h5,
3'h6,
3'h7:
ozonef1e_inc_dec(foo[14:9],1'b0, fd);
3'h1,
3'h3,
3'h4:
$fwrite (fd, " 1095");
endcase
dude(fd);
$fwrite (fd, " 1096");
end
17'b00_10??_?_????_?0_0100 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1097");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
$fwrite (fd, " 1098");
ozoneae(foo[ 8: 6], fd);
ozonef1e_hl(foo[11:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1099");
end
17'b00_10??_?_????_10_0111 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1100");
$fwrite (fd, " 1101");
ozonerme(foo[14:12], fd);
case (foo[11: 9])
3'h2,
3'h5,
3'h6,
3'h7:
ozonef1e_inc_dec(foo[14:9],1'b0, fd);
3'h1,
3'h3,
3'h4:
$fwrite (fd, " 1102");
endcase
$fwrite (fd, " 1103");
if (foo[ 6])
$fwrite (fd, " 1104");
else
ozonerab({4'b1001, foo[ 8: 6]}, fd);
dude(fd);
$fwrite (fd, " 1105");
end
17'b00_10??_?_????_?0_1110 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1106");
case (foo[11:9])
3'h2:
begin
$fwrite (fd, " 1107");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1108");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1109");
end
3'h6:
begin
$fwrite (fd, " 1110");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1111");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1112");
end
3'h0:
begin
$fwrite (fd, " 1113");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1114");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1115");
if (foo[ 7: 5] >= 3'h5)
$fwrite (fd, " 1116");
else
ozonexe(foo[ 8: 5], fd);
end
3'h1:
begin
$fwrite (fd, " 1117");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1118");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1119");
if (foo[ 7: 5] >= 3'h5)
$fwrite (fd, " 1120");
else
ozonexe(foo[ 8: 5], fd);
end
3'h4:
begin
$fwrite (fd, " 1121");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1122");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1123");
if (foo[ 7: 5] >= 3'h5)
$fwrite (fd, " 1124");
else
ozonexe(foo[ 8: 5], fd);
end
3'h5:
begin
$fwrite (fd, " 1125");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1126");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1127");
if (foo[ 7: 5] >= 3'h5)
$fwrite (fd, " 1128");
else
ozonexe(foo[ 8: 5], fd);
end
endcase
dude(fd);
$fwrite (fd, " 1129");
end
17'b00_10??_?_????_?0_1111 :
casez (foo[14: 9])
6'b001_10_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1130");
$fwrite (fd, " 1131");
ozonef1e_hl(foo[ 7: 5],foo[ 9], fd);
$fwrite (fd, " 1132");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1133");
end
6'b???_11_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1134");
ozoneae(foo[14:12], fd);
ozonef1e_hl(foo[ 7: 5],foo[ 9], fd);
$fwrite (fd, " 1135");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1136");
end
6'b000_10_1,
6'b010_10_1,
6'b100_10_1,
6'b110_10_1:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1137");
ozonerab({4'b1001, foo[14:12]}, fd);
$fwrite (fd, " 1138");
if ((foo[ 7: 5] >= 3'h1) & (foo[ 7: 5] <= 3'h3))
$fwrite (fd, " 1139");
else
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1140");
end
6'b000_10_0,
6'b010_10_0,
6'b100_10_0,
6'b110_10_0:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1141");
$fwrite (fd, " 1142");
ozonerab({4'b1001, foo[14:12]}, fd);
$fwrite (fd, " 1143");
$fwrite (fd, " 1144");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1145");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1146");
end
6'b???_00_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1147");
if (foo[ 9])
begin
$fwrite (fd, " 1148");
ozoneae(foo[14:12], fd);
end
else
begin
$fwrite (fd, " 1149");
ozoneae(foo[14:12], fd);
$fwrite (fd, " 1150");
end
$fwrite (fd, " 1151");
$fwrite (fd, " 1152");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1153");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1154");
end
6'b???_01_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1155");
ozoneae(foo[14:12], fd);
if (foo[ 9])
$fwrite (fd, " 1156");
else
$fwrite (fd, " 1157");
$fwrite (fd, " 1158");
$fwrite (fd, " 1159");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1160");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1161");
end
6'b011_10_0:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1162");
case (foo[ 8: 5])
4'h0: $fwrite (fd, " 1163");
4'h1: $fwrite (fd, " 1164");
4'h2: $fwrite (fd, " 1165");
4'h3: $fwrite (fd, " 1166");
4'h4: $fwrite (fd, " 1167");
4'h5: $fwrite (fd, " 1168");
4'h8: $fwrite (fd, " 1169");
4'h9: $fwrite (fd, " 1170");
4'ha: $fwrite (fd, " 1171");
4'hb: $fwrite (fd, " 1172");
4'hc: $fwrite (fd, " 1173");
4'hd: $fwrite (fd, " 1174");
default: $fwrite (fd, " 1175");
endcase
dude(fd);
$fwrite (fd, " 1176");
end
default: $fwrite (fd, " 1177");
endcase
17'b00_10??_?_????_?0_110? :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1178");
$fwrite (fd, " 1179");
ozonef1e_hl(foo[11:9], foo[0], fd);
$fwrite (fd, " 1180");
ozonef1e_ye(foo[14:9],1'b0, fd);
$fwrite (fd, " 1181");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1182");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1183");
end
17'b00_10??_?_????_?1_110? :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1184");
$fwrite (fd, " 1185");
ozonef1e_hl(foo[11:9],foo[0], fd);
$fwrite (fd, " 1186");
ozonef1e_ye(foo[14:9],foo[ 0], fd);
$fwrite (fd, " 1187");
$fwrite (fd, " 1188");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1189");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1190");
end
17'b00_10??_?_????_?0_101? :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1191");
ozonef1e_ye(foo[14:9],foo[ 0], fd);
$fwrite (fd, " 1192");
$fwrite (fd, " 1193");
ozonef1e_hl(foo[11:9],foo[0], fd);
$fwrite (fd, " 1194");
$fwrite (fd, " 1195");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1196");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1197");
end
17'b00_10??_?_????_?0_1001 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1198");
$fwrite (fd, " 1199");
ozonef1e_h(foo[11:9], fd);
$fwrite (fd, " 1200");
ozonef1e_ye(foo[14:9],1'b0, fd);
$fwrite (fd, " 1201");
case (foo[ 7: 5])
3'h1,
3'h2,
3'h3:
$fwrite (fd, " 1202");
default:
begin
$fwrite (fd, " 1203");
$fwrite (fd, " 1204");
ozonexe(foo[ 8: 5], fd);
end
endcase
dude(fd);
$fwrite (fd, " 1205");
end
17'b00_10??_?_????_?0_0101 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1206");
case (foo[11: 9])
3'h1,
3'h3,
3'h4:
$fwrite (fd, " 1207");
default:
begin
ozonef1e_ye(foo[14:9],1'b0, fd);
$fwrite (fd, " 1208");
$fwrite (fd, " 1209");
end
endcase
$fwrite (fd, " 1210");
$fwrite (fd, " 1211");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1212");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1213");
end
17'b00_10??_?_????_?1_1110 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1214");
ozonef1e_ye(foo[14:9],1'b0, fd);
$fwrite (fd, " 1215");
$fwrite (fd, " 1216");
ozonef1e_h(foo[11: 9], fd);
$fwrite (fd, " 1217");
$fwrite (fd, " 1218");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1219");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1220");
end
17'b00_10??_?_????_?0_1000 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1221");
ozonef1e_ye(foo[14:9],1'b0, fd);
$fwrite (fd, " 1222");
$fwrite (fd, " 1223");
ozonef1e_h(foo[11: 9], fd);
$fwrite (fd, " 1224");
$fwrite (fd, " 1225");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1226");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1227");
end
17'b10_01??_?_????_??_???? :
begin
if (foo[27])
$fwrite (fd," 1228");
else
$fwrite (fd," 1229");
ozonecon(foo[20:16], fd);
$fwrite (fd, " 1230");
ozonef2(foo[31:0], fd);
dude(fd);
$fwrite (fd, " 1231");
end
17'b00_1000_?_????_01_0011 :
if (~|foo[ 9: 8])
begin
if (foo[ 7])
$fwrite (fd," 1232");
else
$fwrite (fd," 1233");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1234");
ozonef2e(foo[31:0], fd);
dude(fd);
$fwrite (fd, " 1235");
end
else
begin
$fwrite (fd, " 1236");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1237");
ozonef3e(foo[31:0], fd);
dude(fd);
$fwrite (fd, " 1238");
end
17'b11_110?_1_????_??_???? :
begin
ozonef3(foo[31:0], fd);
dude(fd);
$fwrite(fd, " 1239");
end
17'b11_110?_0_????_??_???? :
begin : f4_body
casez (foo[24:20])
5'b0_1110,
5'b1_0???,
5'b1_1111:
begin
$fwrite (fd, " 1240");
end
5'b0_00??:
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1241");
ozoneacc(foo[25], fd);
ozonebmuop(foo[24:20], fd);
ozoneae(foo[18:16], fd);
$fwrite (fd, " 1242");
dude(fd);
$fwrite(fd, " 1243");
end
5'b0_01??:
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1244");
ozoneacc(foo[25], fd);
ozonebmuop(foo[24:20], fd);
ozonearm(foo[18:16], fd);
dude(fd);
$fwrite(fd, " 1245");
end
5'b0_1011:
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1246");
ozonebmuop(foo[24:20], fd);
$fwrite (fd, " 1247");
ozoneae(foo[18:16], fd);
$fwrite (fd, " 1248");
dude(fd);
$fwrite(fd, " 1249");
end
5'b0_100?,
5'b0_1010,
5'b0_110? :
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1250");
ozonebmuop(foo[24:20], fd);
$fwrite (fd, " 1251");
ozoneacc(foo[25], fd);
$fwrite (fd, " 1252");
ozoneae(foo[18:16], fd);
$fwrite (fd, " 1253");
dude(fd);
$fwrite(fd, " 1254");
end
5'b0_1111 :
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1255");
ozoneacc(foo[25], fd);
$fwrite (fd, " 1256");
ozoneae(foo[18:16], fd);
dude(fd);
$fwrite(fd, " 1257");
end
5'b1_10??,
5'b1_110?,
5'b1_1110 :
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1258");
ozonebmuop(foo[24:20], fd);
$fwrite (fd, " 1259");
ozoneacc(foo[25], fd);
$fwrite (fd, " 1260");
ozonearm(foo[18:16], fd);
$fwrite (fd, " 1261");
dude(fd);
$fwrite(fd, " 1262");
end
endcase
end
17'b11_100?_?_????_??_???? :
casez (foo[23:19])
5'b111??,
5'b0111?:
begin
ozoneae(foo[26:24], fd);
$fwrite (fd, " 1263");
ozonef3f4imop(foo[23:19], fd);
$fwrite (fd, " 1264");
ozoneae(foo[18:16], fd);
$fwrite (fd, " 1265");
skyway(foo[15:12], fd);
skyway(foo[11: 8], fd);
skyway(foo[ 7: 4], fd);
skyway(foo[ 3:0], fd);
$fwrite (fd, " 1266");
dude(fd);
$fwrite(fd, " 1267");
end
5'b?0???,
5'b110??:
begin
ozoneae(foo[26:24], fd);
$fwrite (fd, " 1268");
if (foo[23:21] == 3'b100)
$fwrite (fd, " 1269");
ozoneae(foo[18:16], fd);
if (foo[19])
$fwrite (fd, " 1270");
else
$fwrite (fd, " 1271");
ozonef3f4imop(foo[23:19], fd);
$fwrite (fd, " 1272");
ozonef3f4_iext(foo[20:19], foo[15:0], fd);
dude(fd);
$fwrite(fd, " 1273");
end
5'b010??,
5'b0110?:
begin
ozoneae(foo[18:16], fd);
if (foo[19])
$fwrite (fd, " 1274");
else
$fwrite (fd, " 1275");
ozonef3f4imop(foo[23:19], fd);
$fwrite (fd, " 1276");
ozonef3f4_iext(foo[20:19], foo[15:0], fd);
dude(fd);
$fwrite(fd, " 1277");
end
endcase
17'b00_1000_?_????_11_0011 :
begin
$fwrite (fd," 1278");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1279");
casez (foo[25:21])
5'b0_1110,
5'b1_0???,
5'b1_1111:
begin
$fwrite(fd, " 1280");
end
5'b0_00??:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1281");
ozoneae(foo[17:15], fd);
ozonebmuop(foo[25:21], fd);
ozoneae(foo[ 8: 6], fd);
$fwrite (fd, " 1282");
dude(fd);
$fwrite(fd, " 1283");
end
5'b0_01??:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1284");
ozoneae(foo[17:15], fd);
ozonebmuop(foo[25:21], fd);
ozonearm(foo[ 8: 6], fd);
dude(fd);
$fwrite(fd, " 1285");
end
5'b0_1011:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1286");
ozonebmuop(foo[25:21], fd);
$fwrite (fd, " 1287");
ozoneae(foo[ 8: 6], fd);
$fwrite (fd, " 1288");
dude(fd);
$fwrite(fd, " 1289");
end
5'b0_100?,
5'b0_1010,
5'b0_110? :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1290");
ozonebmuop(foo[25:21], fd);
$fwrite (fd, " 1291");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 1292");
ozoneae(foo[ 8: 6], fd);
$fwrite (fd, " 1293");
dude(fd);
$fwrite(fd, " 1294");
end
5'b0_1111 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1295");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 1296");
ozoneae(foo[ 8: 6], fd);
dude(fd);
$fwrite(fd, " 1297");
end
5'b1_10??,
5'b1_110?,
5'b1_1110 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1298");
ozonebmuop(foo[25:21], fd);
$fwrite (fd, " 1299");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 1300");
ozonearm(foo[ 8: 6], fd);
$fwrite (fd, " 1301");
dude(fd);
$fwrite(fd, " 1302");
end
endcase
end
17'b00_0010_?_????_??_???? :
begin
ozonerab({1'b0, foo[25:20]}, fd);
$fwrite (fd, " 1303");
skyway(foo[19:16], fd);
dude(fd);
$fwrite(fd, " 1304");
end
17'b00_01??_?_????_??_???? :
begin
if (foo[27])
begin
$fwrite (fd, " 1305");
if (foo[26])
$fwrite (fd, " 1306");
else
$fwrite (fd, " 1307");
skyway(foo[19:16], fd);
$fwrite (fd, " 1308");
ozonerab({1'b0, foo[25:20]}, fd);
end
else
begin
ozonerab({1'b0, foo[25:20]}, fd);
$fwrite (fd, " 1309");
if (foo[26])
$fwrite (fd, " 1310");
else
$fwrite (fd, " 1311");
skyway(foo[19:16], fd);
$fwrite (fd, " 1312");
end
dude(fd);
$fwrite(fd, " 1313");
end
17'b01_000?_?_????_??_???? :
begin
if (foo[26])
begin
ozonerb(foo[25:20], fd);
$fwrite (fd, " 1314");
ozoneae(foo[18:16], fd);
ozonehl(foo[19], fd);
end
else
begin
ozoneae(foo[18:16], fd);
ozonehl(foo[19], fd);
$fwrite (fd, " 1315");
ozonerb(foo[25:20], fd);
end
dude(fd);
$fwrite(fd, " 1316");
end
17'b01_10??_?_????_??_???? :
begin
if (foo[27])
begin
ozonerab({1'b0, foo[25:20]}, fd);
$fwrite (fd, " 1317");
ozonerx(foo, fd);
end
else
begin
ozonerx(foo, fd);
$fwrite (fd, " 1318");
ozonerab({1'b0, foo[25:20]}, fd);
end
dude(fd);
$fwrite(fd, " 1319");
end
17'b11_101?_?_????_??_???? :
begin
ozonerab (foo[26:20], fd);
$fwrite (fd, " 1320");
skyway(foo[19:16], fd);
skyway(foo[15:12], fd);
skyway(foo[11: 8], fd);
skyway(foo[ 7: 4], fd);
skyway(foo[ 3: 0], fd);
dude(fd);
$fwrite(fd, " 1321");
end
17'b11_0000_?_????_??_???? :
begin
casez (foo[25:23])
3'b00?:
begin
ozonerab(foo[22:16], fd);
$fwrite (fd, " 1322");
end
3'b01?:
begin
$fwrite (fd, " 1323");
if (foo[22:16]>=7'h60)
$fwrite (fd, " 1324");
else
ozonerab(foo[22:16], fd);
end
3'b110:
$fwrite (fd, " 1325");
3'b10?:
begin
$fwrite (fd, " 1326");
if (foo[22:16]>=7'h60)
$fwrite (fd, " 1327");
else
ozonerab(foo[22:16], fd);
end
3'b111:
begin
$fwrite (fd, " 1328");
ozonerab(foo[22:16], fd);
$fwrite (fd, " 1329");
end
endcase
dude(fd);
$fwrite(fd, " 1330");
end
17'b00_10??_?_????_?1_0000 :
begin
if (foo[27])
begin
$fwrite (fd, " 1331");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1332");
skyway(foo[19:16], fd);
skyway({foo[15],foo[11: 9]}, fd);
skyway(foo[ 8: 5], fd);
$fwrite (fd, " 1333");
if (foo[26:20]>=7'h60)
$fwrite (fd, " 1334");
else
ozonerab(foo[26:20], fd);
end
else
begin
ozonerab(foo[26:20], fd);
$fwrite (fd, " 1335");
$fwrite (fd, " 1336");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1337");
skyway(foo[19:16], fd);
skyway({foo[15],foo[11: 9]}, fd);
skyway(foo[ 8: 5], fd);
$fwrite (fd, " 1338");
end
dude(fd);
$fwrite(fd, " 1339");
end
17'b00_101?_1_0000_?1_0010 :
if (~|foo[11: 7])
begin
if (foo[ 6])
begin
$fwrite (fd, " 1340");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1341");
ozonejk(foo[ 5], fd);
$fwrite (fd, " 1342");
if (foo[26:20]>=7'h60)
$fwrite (fd, " 1343");
else
ozonerab(foo[26:20], fd);
end
else
begin
ozonerab(foo[26:20], fd);
$fwrite (fd, " 1344");
$fwrite (fd, " 1345");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1346");
ozonejk(foo[ 5], fd);
$fwrite (fd, " 1347");
end
dude(fd);
$fwrite(fd, " 1348");
end
else
$fwrite(fd, " 1349");
17'b00_100?_0_0011_?1_0101 :
if (~|foo[ 8: 7])
begin
if (foo[6])
begin
ozonerab(foo[26:20], fd);
$fwrite (fd, " 1350");
ozoneye(foo[14: 9],foo[ 5], fd);
end
else
begin
ozoneye(foo[14: 9],foo[ 5], fd);
$fwrite (fd, " 1351");
if (foo[26:20]>=7'h60)
$fwrite (fd, " 1352");
else
ozonerab(foo[26:20], fd);
end
dude(fd);
$fwrite(fd, " 1353");
end
else
$fwrite(fd, " 1354");
17'b00_1001_0_0000_?1_0010 :
if (~|foo[25:20])
begin
ozoneye(foo[14: 9],1'b0, fd);
$fwrite (fd, " 1355");
ozonef1e_h(foo[11: 9], fd);
$fwrite (fd, " 1356");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1357");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite(fd, " 1358");
end
else
$fwrite(fd, " 1359");
17'b00_101?_0_????_?1_0010 :
if (~foo[13])
begin
if (foo[12])
begin
$fwrite (fd, " 1360");
if (foo[26:20]>=7'h60)
$fwrite (fd, " 1361");
else
ozonerab(foo[26:20], fd);
$fwrite (fd, " 1362");
$fwrite (fd, " 1363");
skyway({1'b0,foo[18:16]}, fd);
skyway({foo[15],foo[11: 9]}, fd);
skyway(foo[ 8: 5], fd);
dude(fd);
$fwrite(fd, " 1364");
end
else
begin
ozonerab(foo[26:20], fd);
$fwrite (fd, " 1365");
$fwrite (fd, " 1366");
skyway({1'b0,foo[18:16]}, fd);
skyway({foo[15],foo[11: 9]}, fd);
skyway(foo[ 8: 5], fd);
dude(fd);
$fwrite(fd, " 1367");
end
end
else
$fwrite(fd, " 1368");
17'b01_01??_?_????_??_???? :
begin
ozonerab({1'b0,foo[27:26],foo[19:16]}, fd);
$fwrite (fd, " 1369");
ozonerab({1'b0,foo[25:20]}, fd);
dude(fd);
$fwrite(fd, " 1370");
end
17'b00_100?_?_???0_11_0101 :
if (~foo[6])
begin
$fwrite (fd," 1371");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1372");
ozonerab({foo[ 9: 7],foo[19:16]}, fd);
$fwrite (fd, " 1373");
ozonerab({foo[26:20]}, fd);
dude(fd);
$fwrite(fd, " 1374");
end
else
$fwrite(fd, " 1375");
17'b00_1000_?_????_?1_0010 :
if (~|foo[25:24])
begin
ozonery(foo[23:20], fd);
$fwrite (fd, " 1376");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1377");
skyway(foo[19:16], fd);
skyway({foo[15],foo[11: 9]}, fd);
skyway(foo[ 8: 5], fd);
dude(fd);
$fwrite(fd, " 1378");
end
else if ((foo[25:24] == 2'b10) & ~|foo[19:15] & ~|foo[11: 6])
begin
ozonery(foo[23:20], fd);
$fwrite (fd, " 1379");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1380");
ozonejk(foo[ 5], fd);
dude(fd);
$fwrite(fd, " 1381");
end
else
$fwrite(fd, " 1382");
17'b11_01??_?_????_??_????,
17'b10_00??_?_????_??_???? :
if (foo[30])
$fwrite(fd, " 1383:%x", foo[27:16]);
else
$fwrite(fd, " 1384:%x", foo[27:16]);
17'b00_10??_?_????_01_1000 :
if (~foo[6])
begin
if (foo[7])
$fwrite(fd, " 1385:%x", foo[27: 8]);
else
$fwrite(fd, " 1386:%x", foo[27: 8]);
end
else
$fwrite(fd, " 1387");
17'b00_10??_?_????_11_1000 :
begin
$fwrite (fd," 1388");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1389");
if (foo[15])
$fwrite (fd, " 1390");
else
$fwrite (fd, " 1391");
skyway(foo[27:24], fd);
skyway(foo[23:20], fd);
skyway(foo[19:16], fd);
skyway(foo[ 9: 6], fd);
dude(fd);
$fwrite(fd, " 1392");
end
17'b11_0001_?_????_??_???? :
casez (foo[25:22])
4'b01?? :
begin
$fwrite (fd," 1393");
ozonecon(foo[20:16], fd);
case (foo[23:21])
3'h0 : $fwrite (fd, " 1394");
3'h1 : $fwrite (fd, " 1395");
3'h2 : $fwrite (fd, " 1396");
3'h3 : $fwrite (fd, " 1397");
3'h4 : $fwrite (fd, " 1398");
3'h5 : $fwrite (fd, " 1399");
3'h6 : $fwrite (fd, " 1400");
3'h7 : $fwrite (fd, " 1401");
endcase
dude(fd);
$fwrite(fd, " 1402");
end
4'b0000 :
$fwrite(fd, " 1403:%x", foo[21:16]);
4'b0010 :
if (~|foo[21:16])
$fwrite(fd, " 1404");
4'b1010 :
if (~|foo[21:17])
begin
if (foo[16])
$fwrite(fd, " 1405");
else
$fwrite(fd, " 1406");
end
default :
$fwrite(fd, " 1407");
endcase
17'b01_11??_?_????_??_???? :
if (foo[27:23] === 5'h00)
$fwrite(fd, " 1408:%x", foo[22:16]);
else
$fwrite(fd, " 1409:%x", foo[22:16]);
default: $fwrite(fd, " 1410");
endcase
end
endtask
//(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\",\",\\4,\");\");" nil nil nil)
//(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\");\");" nil nil nil)
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (clk);
input clk;
reg [2:0] a;
reg [2:0] b;
reg q;
f6 f6 (/*AUTOINST*/
// Outputs
.q (q),
// Inputs
.a (a[2:0]),
.b (b[2:0]),
.clk (clk));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a <= 3'b000;
b <= 3'b100;
end
if (cyc==2) begin
a <= 3'b011;
b <= 3'b001;
if (q != 1'b0) $stop;
end
if (cyc==3) begin
a <= 3'b011;
b <= 3'b011;
if (q != 1'b0) $stop;
end
if (cyc==9) begin
if (q != 1'b1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module f6 (a, b, clk, q);
input [2:0] a;
input [2:0] b;
input clk;
output q;
reg out;
function func6;
reg result;
input [5:0] src;
begin
if (src[5:0] == 6'b011011) begin
result = 1'b1;
end
else begin
result = 1'b0;
end
func6 = result;
end
endfunction
wire [5:0] w6 = {a, b};
always @(posedge clk) begin
out <= func6(w6);
end
assign q = out;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (clk);
input clk;
reg [2:0] a;
reg [2:0] b;
reg q;
f6 f6 (/*AUTOINST*/
// Outputs
.q (q),
// Inputs
.a (a[2:0]),
.b (b[2:0]),
.clk (clk));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a <= 3'b000;
b <= 3'b100;
end
if (cyc==2) begin
a <= 3'b011;
b <= 3'b001;
if (q != 1'b0) $stop;
end
if (cyc==3) begin
a <= 3'b011;
b <= 3'b011;
if (q != 1'b0) $stop;
end
if (cyc==9) begin
if (q != 1'b1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module f6 (a, b, clk, q);
input [2:0] a;
input [2:0] b;
input clk;
output q;
reg out;
function func6;
reg result;
input [5:0] src;
begin
if (src[5:0] == 6'b011011) begin
result = 1'b1;
end
else begin
result = 1'b0;
end
func6 = result;
end
endfunction
wire [5:0] w6 = {a, b};
always @(posedge clk) begin
out <= func6(w6);
end
assign q = out;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
fastclk, clk
);
`ifdef EDGE_DETECT_STYLE // Two 'common' forms of latching, with full combo, and with pos/negedge
`define posstyle posedge
`define negstyle negedge
`else
`define posstyle
`define negstyle
`endif
input fastclk;
input clk;
reg [7:0] data;
reg [7:0] data_a;
reg [7:0] data_a_a;
reg [7:0] data_a_b;
reg [7:0] data_b;
reg [7:0] data_b_a;
reg [7:0] data_b_b;
reg [8*6-1:0] check [100:0];
wire [8*6-1:0] compare = {data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b};
initial begin
check[7'd19] = {8'h0d, 8'h0e, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd20] = {8'h0d, 8'h0e, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd21] = {8'h15, 8'h16, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd22] = {8'h15, 8'h16, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd23] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e};
check[7'd24] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e};
check[7'd25] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e};
check[7'd26] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h0e};
check[7'd27] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h0e};
check[7'd28] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd29] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd30] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd31] = {8'h1f, 8'h20, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd32] = {8'h1f, 8'h20, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd33] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16};
check[7'd34] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16};
check[7'd35] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16};
check[7'd36] = {8'h1f, 8'h20, 8'h20, 8'h1f, 8'h20, 8'h16};
check[7'd37] = {8'h1f, 8'h20, 8'h20, 8'h1f, 8'h20, 8'h16};
end
// verilator lint_off COMBDLY
always @ (`posstyle clk /*AS*/ or data) begin
if (clk) begin
data_a <= data + 8'd1;
end
end
always @ (`posstyle clk /*AS*/ or data_a) begin
if (clk) begin
data_a_a <= data_a + 8'd1;
end
end
always @ (`posstyle clk /*AS*/ or data_b) begin
if (clk) begin
data_b_a <= data_b + 8'd1;
end
end
always @ (`negstyle clk /*AS*/ or data or data_a) begin
if (~clk) begin
data_b <= data + 8'd1;
data_a_b <= data_a + 8'd1;
data_b_b <= data_b + 8'd1;
end
end
integer cyc; initial cyc=0;
always @ (posedge fastclk) begin
cyc <= cyc+1;
`ifdef TEST_VERBOSE
$write("%d %x %x %x %x %x %x\n",cyc,data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b);
`endif
if (cyc>=19 && cyc<36) begin
if (compare !== check[cyc]) begin
$write("[%0t] Mismatch, got=%x, exp=%x\n", $time, compare, check[cyc]);
$stop;
end
end
if (cyc == 10) begin
data <= 8'd12;
end
if (cyc == 20) begin
data <= 8'd20;
end
if (cyc == 30) begin
data <= 8'd30;
end
if (cyc == 40) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
fastclk, clk
);
`ifdef EDGE_DETECT_STYLE // Two 'common' forms of latching, with full combo, and with pos/negedge
`define posstyle posedge
`define negstyle negedge
`else
`define posstyle
`define negstyle
`endif
input fastclk;
input clk;
reg [7:0] data;
reg [7:0] data_a;
reg [7:0] data_a_a;
reg [7:0] data_a_b;
reg [7:0] data_b;
reg [7:0] data_b_a;
reg [7:0] data_b_b;
reg [8*6-1:0] check [100:0];
wire [8*6-1:0] compare = {data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b};
initial begin
check[7'd19] = {8'h0d, 8'h0e, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd20] = {8'h0d, 8'h0e, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd21] = {8'h15, 8'h16, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd22] = {8'h15, 8'h16, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd23] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e};
check[7'd24] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e};
check[7'd25] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e};
check[7'd26] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h0e};
check[7'd27] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h0e};
check[7'd28] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd29] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd30] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd31] = {8'h1f, 8'h20, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd32] = {8'h1f, 8'h20, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd33] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16};
check[7'd34] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16};
check[7'd35] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16};
check[7'd36] = {8'h1f, 8'h20, 8'h20, 8'h1f, 8'h20, 8'h16};
check[7'd37] = {8'h1f, 8'h20, 8'h20, 8'h1f, 8'h20, 8'h16};
end
// verilator lint_off COMBDLY
always @ (`posstyle clk /*AS*/ or data) begin
if (clk) begin
data_a <= data + 8'd1;
end
end
always @ (`posstyle clk /*AS*/ or data_a) begin
if (clk) begin
data_a_a <= data_a + 8'd1;
end
end
always @ (`posstyle clk /*AS*/ or data_b) begin
if (clk) begin
data_b_a <= data_b + 8'd1;
end
end
always @ (`negstyle clk /*AS*/ or data or data_a) begin
if (~clk) begin
data_b <= data + 8'd1;
data_a_b <= data_a + 8'd1;
data_b_b <= data_b + 8'd1;
end
end
integer cyc; initial cyc=0;
always @ (posedge fastclk) begin
cyc <= cyc+1;
`ifdef TEST_VERBOSE
$write("%d %x %x %x %x %x %x\n",cyc,data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b);
`endif
if (cyc>=19 && cyc<36) begin
if (compare !== check[cyc]) begin
$write("[%0t] Mismatch, got=%x, exp=%x\n", $time, compare, check[cyc]);
$stop;
end
end
if (cyc == 10) begin
data <= 8'd12;
end
if (cyc == 20) begin
data <= 8'd20;
end
if (cyc == 30) begin
data <= 8'd30;
end
if (cyc == 40) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [63:0] sum;
wire [31:0] out1;
wire [31:0] out2;
sub sub (.in1(crc[15:0]), .in2(crc[31:16]), .out1(out1), .out2);
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x sum=%x out=%x %x\n",$time, cyc, crc, sum, out1, out2);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {out2,out1};
if (cyc==1) begin
// Setup
crc <= 64'h00000000_00000097;
sum <= 64'h0;
end
else if (cyc==90) begin
if (sum !== 64'he396068aba3898a2) $stop;
end
else if (cyc==91) begin
end
else if (cyc==92) begin
end
else if (cyc==93) begin
end
else if (cyc==94) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub (/*AUTOARG*/
// Outputs
out1, out2,
// Inputs
in1, in2
);
input [15:0] in1;
input [15:0] in2;
output reg signed [31:0] out1;
output reg unsigned [31:0] out2;
always @* begin
// verilator lint_off WIDTH
out1 = $signed(in1) * $signed(in2);
out2 = $unsigned(in1) * $unsigned(in2);
// verilator lint_on WIDTH
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [63:0] sum;
wire [31:0] out1;
wire [31:0] out2;
sub sub (.in1(crc[15:0]), .in2(crc[31:16]), .out1(out1), .out2);
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x sum=%x out=%x %x\n",$time, cyc, crc, sum, out1, out2);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {out2,out1};
if (cyc==1) begin
// Setup
crc <= 64'h00000000_00000097;
sum <= 64'h0;
end
else if (cyc==90) begin
if (sum !== 64'he396068aba3898a2) $stop;
end
else if (cyc==91) begin
end
else if (cyc==92) begin
end
else if (cyc==93) begin
end
else if (cyc==94) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub (/*AUTOARG*/
// Outputs
out1, out2,
// Inputs
in1, in2
);
input [15:0] in1;
input [15:0] in2;
output reg signed [31:0] out1;
output reg unsigned [31:0] out2;
always @* begin
// verilator lint_off WIDTH
out1 = $signed(in1) * $signed(in2);
out2 = $unsigned(in1) * $unsigned(in2);
// verilator lint_on WIDTH
end
endmodule
|
module cclk_detector #(
parameter CLK_RATE = 50000000
)(
input clk,
input rst,
input cclk,
output ready
);
parameter CTR_SIZE = $clog2(CLK_RATE/50000);
reg [CTR_SIZE-1:0] ctr_d, ctr_q;
reg ready_d, ready_q;
assign ready = ready_q;
// ready should only go high once cclk has been high for a while
// if cclk ever falls, ready should go low again
always @(ctr_q or cclk) begin
ready_d = 1'b0;
if (cclk == 1'b0) begin // when cclk is 0 reset the counter
ctr_d = 1'b0;
end else if (ctr_q != {CTR_SIZE{1'b1}}) begin
ctr_d = ctr_q + 1'b1; // counter isn't max value yet
end else begin
ctr_d = ctr_q;
ready_d = 1'b1; // counter reached the max, we are ready
end
end
always @(posedge clk) begin
if (rst) begin
ctr_q <= 1'b0;
ready_q <= 1'b0;
end else begin
ctr_q <= ctr_d;
ready_q <= ready_d;
end
end
endmodule
|
(** * PE: Partial Evaluation *)
(* $Date: 2013-07-17 16:19:11 -0400 (Wed, 17 Jul 2013) $ *)
(* Chapter author/maintainer: Chung-chieh Shan *)
(** Equiv.v introduced constant folding as an example of a program
transformation and proved that it preserves the meaning of the
program. Constant folding operates on manifest constants such
as [ANum] expressions. For example, it simplifies the command
[Y ::= APlus (ANum 3) (ANum 1)] to the command [Y ::= ANum 4].
However, it does not propagate known constants along data flow.
For example, it does not simplify the sequence
X ::= ANum 3;; Y ::= APlus (AId X) (ANum 1)
to
X ::= ANum 3;; Y ::= ANum 4
because it forgets that [X] is [3] by the time it gets to [Y].
We naturally want to enhance constant folding so that it
propagates known constants and uses them to simplify programs.
Doing so constitutes a rudimentary form of _partial evaluation_.
As we will see, partial evaluation is so called because it is
like running a program, except only part of the program can be
evaluated because only part of the input to the program is known.
For example, we can only simplify the program
X ::= ANum 3;; Y ::= AMinus (APlus (AId X) (ANum 1)) (AId Y)
to
X ::= ANum 3;; Y ::= AMinus (ANum 4) (AId Y)
without knowing the initial value of [Y]. *)
Require Export Imp.
Require Import FunctionalExtensionality.
(* ####################################################### *)
(** * Generalizing Constant Folding *)
(** The starting point of partial evaluation is to represent our
partial knowledge about the state. For example, between the two
assignments above, the partial evaluator may know only that [X] is
[3] and nothing about any other variable. *)
(** ** Partial States *)
(** Conceptually speaking, we can think of such partial states as the
type [id -> option nat] (as opposed to the type [id -> nat] of
concrete, full states). However, in addition to looking up and
updating the values of individual variables in a partial state, we
may also want to compare two partial states to see if and where
they differ, to handle conditional control flow. It is not possible
to compare two arbitrary functions in this way, so we represent
partial states in a more concrete format: as a list of [id * nat]
pairs. *)
Definition pe_state := list (id * nat).
(** The idea is that a variable [id] appears in the list if and only
if we know its current [nat] value. The [pe_lookup] function thus
interprets this concrete representation. (If the same variable
[id] appears multiple times in the list, the first occurrence
wins, but we will define our partial evaluator to never construct
such a [pe_state].) *)
Fixpoint pe_lookup (pe_st : pe_state) (V:id) : option nat :=
match pe_st with
| [] => None
| (V',n')::pe_st => if eq_id_dec V V' then Some n'
else pe_lookup pe_st V
end.
(** For example, [empty_pe_state] represents complete ignorance about
every variable -- the function that maps every [id] to [None]. *)
Definition empty_pe_state : pe_state := [].
(** More generally, if the [list] representing a [pe_state] does not
contain some [id], then that [pe_state] must map that [id] to
[None]. Before we prove this fact, we first define a useful
tactic for reasoning with [id] equality. The tactic
compare V V' SCase
means to reason by cases over [eq_id_dec V V'].
In the case where [V = V'], the tactic
substitutes [V] for [V'] throughout. *)
Tactic Notation "compare" ident(i) ident(j) ident(c) :=
let H := fresh "Heq" i j in
destruct (eq_id_dec i j);
[ Case_aux c "equal"; subst j
| Case_aux c "not equal" ].
Theorem pe_domain: forall pe_st V n,
pe_lookup pe_st V = Some n ->
In V (map (@fst _ _) pe_st).
Proof. intros pe_st V n H. induction pe_st as [| [V' n'] pe_st].
Case "[]". inversion H.
Case "::". simpl in H. simpl. compare V V' SCase; auto. Qed.
(** *** Aside on [In].
We will make heavy use of the [In] predicate from the standard library.
[In] is equivalent to the [appears_in] predicate introduced in Logic.v, but
defined using a [Fixpoint] rather than an [Inductive]. *)
Print In.
(* ===> Fixpoint In {A:Type} (a: A) (l:list A) : Prop :=
match l with
| [] => False
| b :: m => b = a \/ In a m
end
: forall A : Type, A -> list A -> Prop *)
(** [In] comes with various useful lemmas. *)
Check in_or_app.
(* ===> in_or_app: forall (A : Type) (l m : list A) (a : A),
In a l \/ In a m -> In a (l ++ m) *)
Check filter_In.
(* ===> filter_In : forall (A : Type) (f : A -> bool) (x : A) (l : list A),
In x (filter f l) <-> In x l /\ f x = true *)
Check in_dec.
(* ===> in_dec : forall A : Type,
(forall x y : A, {x = y} + {x <> y}) ->
forall (a : A) (l : list A), {In a l} + {~ In a l}] *)
(** Note that we can compute with [in_dec], just as with [eq_id_dec]. *)
(** ** Arithmetic Expressions *)
(** Partial evaluation of [aexp] is straightforward -- it is basically
the same as constant folding, [fold_constants_aexp], except that
sometimes the partial state tells us the current value of a
variable and we can replace it by a constant expression. *)
Fixpoint pe_aexp (pe_st : pe_state) (a : aexp) : aexp :=
match a with
| ANum n => ANum n
| AId i => match pe_lookup pe_st i with (* <----- NEW *)
| Some n => ANum n
| None => AId i
end
| APlus a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 + n2)
| (a1', a2') => APlus a1' a2'
end
| AMinus a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 - n2)
| (a1', a2') => AMinus a1' a2'
end
| AMult a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 * n2)
| (a1', a2') => AMult a1' a2'
end
end.
(** This partial evaluator folds constants but does not apply the
associativity of addition. *)
Example test_pe_aexp1:
pe_aexp [(X,3)] (APlus (APlus (AId X) (ANum 1)) (AId Y))
= APlus (ANum 4) (AId Y).
Proof. reflexivity. Qed.
Example text_pe_aexp2:
pe_aexp [(Y,3)] (APlus (APlus (AId X) (ANum 1)) (AId Y))
= APlus (APlus (AId X) (ANum 1)) (ANum 3).
Proof. reflexivity. Qed.
(** Now, in what sense is [pe_aexp] correct? It is reasonable to
define the correctness of [pe_aexp] as follows: whenever a full
state [st:state] is _consistent_ with a partial state
[pe_st:pe_state] (in other words, every variable to which [pe_st]
assigns a value is assigned the same value by [st]), evaluating
[a] and evaluating [pe_aexp pe_st a] in [st] yields the same
result. This statement is indeed true. *)
Definition pe_consistent (st:state) (pe_st:pe_state) :=
forall V n, Some n = pe_lookup pe_st V -> st V = n.
Theorem pe_aexp_correct_weak: forall st pe_st, pe_consistent st pe_st ->
forall a, aeval st a = aeval st (pe_aexp pe_st a).
Proof. unfold pe_consistent. intros st pe_st H a.
aexp_cases (induction a) Case; simpl;
try reflexivity;
try (destruct (pe_aexp pe_st a1);
destruct (pe_aexp pe_st a2);
rewrite IHa1; rewrite IHa2; reflexivity).
(* Compared to fold_constants_aexp_sound,
the only interesting case is AId *)
Case "AId".
remember (pe_lookup pe_st i) as l. destruct l.
SCase "Some". rewrite H with (n:=n) by apply Heql. reflexivity.
SCase "None". reflexivity.
Qed.
(** However, we will soon want our partial evaluator to remove
assignments. For example, it will simplify
X ::= ANum 3;; Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
to just
Y ::= AMinus (ANum 3) (AId Y);; X ::= ANum 4
by delaying the assignment to [X] until the end. To accomplish
this simplification, we need the result of partial evaluating
pe_aexp [(X,3)] (AMinus (AId X) (AId Y))
to be equal to [AMinus (ANum 3) (AId Y)] and _not_ the original
expression [AMinus (AId X) (AId Y)]. After all, it would be
incorrect, not just inefficient, to transform
X ::= ANum 3;; Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
to
Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
even though the output expressions [AMinus (ANum 3) (AId Y)] and
[AMinus (AId X) (AId Y)] both satisfy the correctness criterion
that we just proved. Indeed, if we were to just define [pe_aexp
pe_st a = a] then the theorem [pe_aexp_correct'] would already
trivially hold.
Instead, we want to prove that the [pe_aexp] is correct in a
stronger sense: evaluating the expression produced by partial
evaluation ([aeval st (pe_aexp pe_st a)]) must not depend on those
parts of the full state [st] that are already specified in the
partial state [pe_st]. To be more precise, let us define a
function [pe_override], which updates [st] with the contents of
[pe_st]. In other words, [pe_override] carries out the
assignments listed in [pe_st] on top of [st]. *)
Fixpoint pe_override (st:state) (pe_st:pe_state) : state :=
match pe_st with
| [] => st
| (V,n)::pe_st => update (pe_override st pe_st) V n
end.
Example test_pe_override:
pe_override (update empty_state Y 1) [(X,3);(Z,2)]
= update (update (update empty_state Y 1) Z 2) X 3.
Proof. reflexivity. Qed.
(** Although [pe_override] operates on a concrete [list] representing
a [pe_state], its behavior is defined entirely by the [pe_lookup]
interpretation of the [pe_state]. *)
Theorem pe_override_correct: forall st pe_st V0,
pe_override st pe_st V0 =
match pe_lookup pe_st V0 with
| Some n => n
| None => st V0
end.
Proof. intros. induction pe_st as [| [V n] pe_st]. reflexivity.
simpl in *. unfold update.
compare V0 V Case; auto. rewrite eq_id; auto. rewrite neq_id; auto. Qed.
(** We can relate [pe_consistent] to [pe_override] in two ways.
First, overriding a state with a partial state always gives a
state that is consistent with the partial state. Second, if a
state is already consistent with a partial state, then overriding
the state with the partial state gives the same state. *)
Theorem pe_override_consistent: forall st pe_st,
pe_consistent (pe_override st pe_st) pe_st.
Proof. intros st pe_st V n H. rewrite pe_override_correct.
destruct (pe_lookup pe_st V); inversion H. reflexivity. Qed.
Theorem pe_consistent_override: forall st pe_st,
pe_consistent st pe_st -> forall V, st V = pe_override st pe_st V.
Proof. intros st pe_st H V. rewrite pe_override_correct.
remember (pe_lookup pe_st V) as l. destruct l; auto. Qed.
(** Now we can state and prove that [pe_aexp] is correct in the
stronger sense that will help us define the rest of the partial
evaluator.
Intuitively, running a program using partial evaluation is a
two-stage process. In the first, _static_ stage, we partially
evaluate the given program with respect to some partial state to
get a _residual_ program. In the second, _dynamic_ stage, we
evaluate the residual program with respect to the rest of the
state. This dynamic state provides values for those variables
that are unknown in the static (partial) state. Thus, the
residual program should be equivalent to _prepending_ the
assignments listed in the partial state to the original program. *)
Theorem pe_aexp_correct: forall (pe_st:pe_state) (a:aexp) (st:state),
aeval (pe_override st pe_st) a = aeval st (pe_aexp pe_st a).
Proof.
intros pe_st a st.
aexp_cases (induction a) Case; simpl;
try reflexivity;
try (destruct (pe_aexp pe_st a1);
destruct (pe_aexp pe_st a2);
rewrite IHa1; rewrite IHa2; reflexivity).
(* Compared to fold_constants_aexp_sound, the only
interesting case is AId. *)
rewrite pe_override_correct. destruct (pe_lookup pe_st i); reflexivity.
Qed.
(** ** Boolean Expressions *)
(** The partial evaluation of boolean expressions is similar. In
fact, it is entirely analogous to the constant folding of boolean
expressions, because our language has no boolean variables. *)
Fixpoint pe_bexp (pe_st : pe_state) (b : bexp) : bexp :=
match b with
| BTrue => BTrue
| BFalse => BFalse
| BEq a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => if beq_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BEq a1' a2'
end
| BLe a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => if ble_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BLe a1' a2'
end
| BNot b1 =>
match (pe_bexp pe_st b1) with
| BTrue => BFalse
| BFalse => BTrue
| b1' => BNot b1'
end
| BAnd b1 b2 =>
match (pe_bexp pe_st b1, pe_bexp pe_st b2) with
| (BTrue, BTrue) => BTrue
| (BTrue, BFalse) => BFalse
| (BFalse, BTrue) => BFalse
| (BFalse, BFalse) => BFalse
| (b1', b2') => BAnd b1' b2'
end
end.
Example test_pe_bexp1:
pe_bexp [(X,3)] (BNot (BLe (AId X) (ANum 3)))
= BFalse.
Proof. reflexivity. Qed.
Example test_pe_bexp2: forall b,
b = BNot (BLe (AId X) (APlus (AId X) (ANum 1))) ->
pe_bexp [] b = b.
Proof. intros b H. rewrite -> H. reflexivity. Qed.
(** The correctness of [pe_bexp] is analogous to the correctness of
[pe_aexp] above. *)
Theorem pe_bexp_correct: forall (pe_st:pe_state) (b:bexp) (st:state),
beval (pe_override st pe_st) b = beval st (pe_bexp pe_st b).
Proof.
intros pe_st b st.
bexp_cases (induction b) Case; simpl;
try reflexivity;
try (remember (pe_aexp pe_st a) as a';
remember (pe_aexp pe_st a0) as a0';
assert (Ha: aeval (pe_override st pe_st) a = aeval st a');
assert (Ha0: aeval (pe_override st pe_st) a0 = aeval st a0');
try (subst; apply pe_aexp_correct);
destruct a'; destruct a0'; rewrite Ha; rewrite Ha0;
simpl; try destruct (beq_nat n n0); try destruct (ble_nat n n0);
reflexivity);
try (destruct (pe_bexp pe_st b); rewrite IHb; reflexivity);
try (destruct (pe_bexp pe_st b1);
destruct (pe_bexp pe_st b2);
rewrite IHb1; rewrite IHb2; reflexivity).
Qed.
(* ####################################################### *)
(** * Partial Evaluation of Commands, Without Loops *)
(** What about the partial evaluation of commands? The analogy
between partial evaluation and full evaluation continues: Just as
full evaluation of a command turns an initial state into a final
state, partial evaluation of a command turns an initial partial
state into a final partial state. The difference is that, because
the state is partial, some parts of the command may not be
executable at the static stage. Therefore, just as [pe_aexp]
returns a residual [aexp] and [pe_bexp] returns a residual [bexp]
above, partially evaluating a command yields a residual command.
Another way in which our partial evaluator is similar to a full
evaluator is that it does not terminate on all commands. It is
not hard to build a partial evaluator that terminates on all
commands; what is hard is building a partial evaluator that
terminates on all commands yet automatically performs desired
optimizations such as unrolling loops. Often a partial evaluator
can be coaxed into terminating more often and performing more
optimizations by writing the source program differently so that
the separation between static and dynamic information becomes more
apparent. Such coaxing is the art of _binding-time improvement_.
The binding time of a variable tells when its value is known --
either "static", or "dynamic."
Anyway, for now we will just live with the fact that our partial
evaluator is not a total function from the source command and the
initial partial state to the residual command and the final
partial state. To model this non-termination, just as with the
full evaluation of commands, we use an inductively defined
relation. We write
c1 / st || c1' / st'
to mean that partially evaluating the source command [c1] in the
initial partial state [st] yields the residual command [c1'] and
the final partial state [st']. For example, we want something like
(X ::= ANum 3 ;; Y ::= AMult (AId Z) (APlus (AId X) (AId X)))
/ [] || (Y ::= AMult (AId Z) (ANum 6)) / [(X,3)]
to hold. The assignment to [X] appears in the final partial state,
not the residual command. *)
(** ** Assignment *)
(** Let's start by considering how to partially evaluate an
assignment. The two assignments in the source program above needs
to be treated differently. The first assignment [X ::= ANum 3],
is _static_: its right-hand-side is a constant (more generally,
simplifies to a constant), so we should update our partial state
at [X] to [3] and produce no residual code. (Actually, we produce
a residual [SKIP].) The second assignment [Y ::= AMult (AId Z)
(APlus (AId X) (AId X))] is _dynamic_: its right-hand-side does
not simplify to a constant, so we should leave it in the residual
code and remove [Y], if present, from our partial state. To
implement these two cases, we define the functions [pe_add] and
[pe_remove]. Like [pe_override] above, these functions operate on
a concrete [list] representing a [pe_state], but the theorems
[pe_add_correct] and [pe_remove_correct] specify their behavior by
the [pe_lookup] interpretation of the [pe_state]. *)
Fixpoint pe_remove (pe_st:pe_state) (V:id) : pe_state :=
match pe_st with
| [] => []
| (V',n')::pe_st => if eq_id_dec V V' then pe_remove pe_st V
else (V',n') :: pe_remove pe_st V
end.
Theorem pe_remove_correct: forall pe_st V V0,
pe_lookup (pe_remove pe_st V) V0
= if eq_id_dec V V0 then None else pe_lookup pe_st V0.
Proof. intros pe_st V V0. induction pe_st as [| [V' n'] pe_st].
Case "[]". destruct (eq_id_dec V V0); reflexivity.
Case "::". simpl. compare V V' SCase.
SCase "equal". rewrite IHpe_st.
destruct (eq_id_dec V V0). reflexivity. rewrite neq_id; auto.
SCase "not equal". simpl. compare V0 V' SSCase.
SSCase "equal". rewrite neq_id; auto.
SSCase "not equal". rewrite IHpe_st. reflexivity.
Qed.
Definition pe_add (pe_st:pe_state) (V:id) (n:nat) : pe_state :=
(V,n) :: pe_remove pe_st V.
Theorem pe_add_correct: forall pe_st V n V0,
pe_lookup (pe_add pe_st V n) V0
= if eq_id_dec V V0 then Some n else pe_lookup pe_st V0.
Proof. intros pe_st V n V0. unfold pe_add. simpl.
compare V V0 Case.
Case "equal". rewrite eq_id; auto.
Case "not equal". rewrite pe_remove_correct. repeat rewrite neq_id; auto.
Qed.
(** We will use the two theorems below to show that our partial
evaluator correctly deals with dynamic assignments and static
assignments, respectively. *)
Theorem pe_override_update_remove: forall st pe_st V n,
update (pe_override st pe_st) V n =
pe_override (update st V n) (pe_remove pe_st V).
Proof. intros st pe_st V n. apply functional_extensionality. intros V0.
unfold update. rewrite !pe_override_correct. rewrite pe_remove_correct.
destruct (eq_id_dec V V0); reflexivity. Qed.
Theorem pe_override_update_add: forall st pe_st V n,
update (pe_override st pe_st) V n =
pe_override st (pe_add pe_st V n).
Proof. intros st pe_st V n. apply functional_extensionality. intros V0.
unfold update. rewrite !pe_override_correct. rewrite pe_add_correct.
destruct (eq_id_dec V V0); reflexivity. Qed.
(** ** Conditional *)
(** Trickier than assignments to partially evaluate is the
conditional, [IFB b1 THEN c1 ELSE c2 FI]. If [b1] simplifies to
[BTrue] or [BFalse] then it's easy: we know which branch will be
taken, so just take that branch. If [b1] does not simplify to a
constant, then we need to take both branches, and the final
partial state may differ between the two branches!
The following program illustrates the difficulty:
X ::= ANum 3;;
IFB BLe (AId Y) (ANum 4) THEN
Y ::= ANum 4;;
IFB BEq (AId X) (AId Y) THEN Y ::= ANum 999 ELSE SKIP FI
ELSE SKIP FI
Suppose the initial partial state is empty. We don't know
statically how [Y] compares to [4], so we must partially evaluate
both branches of the (outer) conditional. On the [THEN] branch,
we know that [Y] is set to [4] and can even use that knowledge to
simplify the code somewhat. On the [ELSE] branch, we still don't
know the exact value of [Y] at the end. What should the final
partial state and residual program be?
One way to handle such a dynamic conditional is to take the
intersection of the final partial states of the two branches. In
this example, we take the intersection of [(Y,4),(X,3)] and
[(X,3)], so the overall final partial state is [(X,3)]. To
compensate for forgetting that [Y] is [4], we need to add an
assignment [Y ::= ANum 4] to the end of the [THEN] branch. So,
the residual program will be something like
SKIP;;
IFB BLe (AId Y) (ANum 4) THEN
SKIP;;
SKIP;;
Y ::= ANum 4
ELSE SKIP FI
Programming this case in Coq calls for several auxiliary
functions: we need to compute the intersection of two [pe_state]s
and turn their difference into sequences of assignments.
First, we show how to compute whether two [pe_state]s to disagree
at a given variable. In the theorem [pe_disagree_domain], we
prove that two [pe_state]s can only disagree at variables that
appear in at least one of them. *)
Definition pe_disagree_at (pe_st1 pe_st2 : pe_state) (V:id) : bool :=
match pe_lookup pe_st1 V, pe_lookup pe_st2 V with
| Some x, Some y => negb (beq_nat x y)
| None, None => false
| _, _ => true
end.
Theorem pe_disagree_domain: forall (pe_st1 pe_st2 : pe_state) (V:id),
true = pe_disagree_at pe_st1 pe_st2 V ->
In V (map (@fst _ _) pe_st1 ++ map (@fst _ _) pe_st2).
Proof. unfold pe_disagree_at. intros pe_st1 pe_st2 V H.
apply in_or_app.
remember (pe_lookup pe_st1 V) as lookup1.
destruct lookup1 as [n1|]. left. apply pe_domain with n1. auto.
remember (pe_lookup pe_st2 V) as lookup2.
destruct lookup2 as [n2|]. right. apply pe_domain with n2. auto.
inversion H. Qed.
(** We define the [pe_compare] function to list the variables where
two given [pe_state]s disagree. This list is exact, according to
the theorem [pe_compare_correct]: a variable appears on the list
if and only if the two given [pe_state]s disagree at that
variable. Furthermore, we use the [pe_unique] function to
eliminate duplicates from the list. *)
Fixpoint pe_unique (l : list id) : list id :=
match l with
| [] => []
| x::l => x :: filter (fun y => if eq_id_dec x y then false else true) (pe_unique l)
end.
Theorem pe_unique_correct: forall l x,
In x l <-> In x (pe_unique l).
Proof. intros l x. induction l as [| h t]. reflexivity.
simpl in *. split.
Case "->".
intros. inversion H; clear H.
left. assumption.
destruct (eq_id_dec h x).
left. assumption.
right. apply filter_In. split.
apply IHt. assumption.
rewrite neq_id; auto.
Case "<-".
intros. inversion H; clear H.
left. assumption.
apply filter_In in H0. inversion H0. right. apply IHt. assumption.
Qed.
Definition pe_compare (pe_st1 pe_st2 : pe_state) : list id :=
pe_unique (filter (pe_disagree_at pe_st1 pe_st2)
(map (@fst _ _) pe_st1 ++ map (@fst _ _) pe_st2)).
Theorem pe_compare_correct: forall pe_st1 pe_st2 V,
pe_lookup pe_st1 V = pe_lookup pe_st2 V <->
~ In V (pe_compare pe_st1 pe_st2).
Proof. intros pe_st1 pe_st2 V.
unfold pe_compare. rewrite <- pe_unique_correct. rewrite filter_In.
split; intros Heq.
Case "->".
intro. destruct H. unfold pe_disagree_at in H0. rewrite Heq in H0.
destruct (pe_lookup pe_st2 V).
rewrite <- beq_nat_refl in H0. inversion H0.
inversion H0.
Case "<-".
assert (Hagree: pe_disagree_at pe_st1 pe_st2 V = false).
SCase "Proof of assertion".
remember (pe_disagree_at pe_st1 pe_st2 V) as disagree.
destruct disagree; [| reflexivity].
apply pe_disagree_domain in Heqdisagree.
apply ex_falso_quodlibet. apply Heq. split. assumption. reflexivity.
unfold pe_disagree_at in Hagree.
destruct (pe_lookup pe_st1 V) as [n1|];
destruct (pe_lookup pe_st2 V) as [n2|];
try reflexivity; try solve by inversion.
rewrite negb_false_iff in Hagree.
apply beq_nat_true in Hagree. subst. reflexivity. Qed.
(** The intersection of two partial states is the result of removing
from one of them all the variables where the two disagree. We
define the function [pe_removes], in terms of [pe_remove] above,
to perform such a removal of a whole list of variables at once.
The theorem [pe_compare_removes] testifies that the [pe_lookup]
interpretation of the result of this intersection operation is the
same no matter which of the two partial states we remove the
variables from. Because [pe_override] only depends on the
[pe_lookup] interpretation of partial states, [pe_override] also
does not care which of the two partial states we remove the
variables from; that theorem [pe_compare_override] is used in the
correctness proof shortly. *)
Fixpoint pe_removes (pe_st:pe_state) (ids : list id) : pe_state :=
match ids with
| [] => pe_st
| V::ids => pe_remove (pe_removes pe_st ids) V
end.
Theorem pe_removes_correct: forall pe_st ids V,
pe_lookup (pe_removes pe_st ids) V =
if in_dec eq_id_dec V ids then None else pe_lookup pe_st V.
Proof. intros pe_st ids V. induction ids as [| V' ids]. reflexivity.
simpl. rewrite pe_remove_correct. rewrite IHids.
compare V' V Case.
reflexivity.
destruct (in_dec eq_id_dec V ids);
reflexivity.
Qed.
Theorem pe_compare_removes: forall pe_st1 pe_st2 V,
pe_lookup (pe_removes pe_st1 (pe_compare pe_st1 pe_st2)) V =
pe_lookup (pe_removes pe_st2 (pe_compare pe_st1 pe_st2)) V.
Proof. intros pe_st1 pe_st2 V. rewrite !pe_removes_correct.
destruct (in_dec eq_id_dec V (pe_compare pe_st1 pe_st2)).
reflexivity.
apply pe_compare_correct. auto. Qed.
Theorem pe_compare_override: forall pe_st1 pe_st2 st,
pe_override st (pe_removes pe_st1 (pe_compare pe_st1 pe_st2)) =
pe_override st (pe_removes pe_st2 (pe_compare pe_st1 pe_st2)).
Proof. intros. apply functional_extensionality. intros V.
rewrite !pe_override_correct. rewrite pe_compare_removes. reflexivity.
Qed.
(** Finally, we define an [assign] function to turn the difference
between two partial states into a sequence of assignment commands.
More precisely, [assign pe_st ids] generates an assignment command
for each variable listed in [ids]. *)
Fixpoint assign (pe_st : pe_state) (ids : list id) : com :=
match ids with
| [] => SKIP
| V::ids => match pe_lookup pe_st V with
| Some n => (assign pe_st ids;; V ::= ANum n)
| None => assign pe_st ids
end
end.
(** The command generated by [assign] always terminates, because it is
just a sequence of assignments. The (total) function [assigned]
below computes the effect of the command on the (dynamic state).
The theorem [assign_removes] then confirms that the generated
assignments perfectly compensate for removing the variables from
the partial state. *)
Definition assigned (pe_st:pe_state) (ids : list id) (st:state) : state :=
fun V => if in_dec eq_id_dec V ids then
match pe_lookup pe_st V with
| Some n => n
| None => st V
end
else st V.
Theorem assign_removes: forall pe_st ids st,
pe_override st pe_st =
pe_override (assigned pe_st ids st) (pe_removes pe_st ids).
Proof. intros pe_st ids st. apply functional_extensionality. intros V.
rewrite !pe_override_correct. rewrite pe_removes_correct. unfold assigned.
destruct (in_dec eq_id_dec V ids); destruct (pe_lookup pe_st V); reflexivity.
Qed.
Lemma ceval_extensionality: forall c st st1 st2,
c / st || st1 -> (forall V, st1 V = st2 V) -> c / st || st2.
Proof. intros c st st1 st2 H Heq.
apply functional_extensionality in Heq. rewrite <- Heq. apply H. Qed.
Theorem eval_assign: forall pe_st ids st,
assign pe_st ids / st || assigned pe_st ids st.
Proof. intros pe_st ids st. induction ids as [| V ids]; simpl.
Case "[]". eapply ceval_extensionality. apply E_Skip. reflexivity.
Case "V::ids".
remember (pe_lookup pe_st V) as lookup. destruct lookup.
SCase "Some". eapply E_Seq. apply IHids. unfold assigned. simpl.
eapply ceval_extensionality. apply E_Ass. simpl. reflexivity.
intros V0. unfold update. compare V V0 SSCase.
SSCase "equal". rewrite <- Heqlookup. reflexivity.
SSCase "not equal". destruct (in_dec eq_id_dec V0 ids); auto.
SCase "None". eapply ceval_extensionality. apply IHids.
unfold assigned. intros V0. simpl. compare V V0 SSCase.
SSCase "equal". rewrite <- Heqlookup.
destruct (in_dec eq_id_dec V ids); reflexivity.
SSCase "not equal". destruct (in_dec eq_id_dec V0 ids); reflexivity. Qed.
(** ** The Partial Evaluation Relation *)
(** At long last, we can define a partial evaluator for commands
without loops, as an inductive relation! The inequality
conditions in [PE_AssDynamic] and [PE_If] are just to keep the
partial evaluator deterministic; they are not required for
correctness. *)
Reserved Notation "c1 '/' st '||' c1' '/' st'"
(at level 40, st at level 39, c1' at level 39).
Inductive pe_com : com -> pe_state -> com -> pe_state -> Prop :=
| PE_Skip : forall pe_st,
SKIP / pe_st || SKIP / pe_st
| PE_AssStatic : forall pe_st a1 n1 l,
pe_aexp pe_st a1 = ANum n1 ->
(l ::= a1) / pe_st || SKIP / pe_add pe_st l n1
| PE_AssDynamic : forall pe_st a1 a1' l,
pe_aexp pe_st a1 = a1' ->
(forall n, a1' <> ANum n) ->
(l ::= a1) / pe_st || (l ::= a1') / pe_remove pe_st l
| PE_Seq : forall pe_st pe_st' pe_st'' c1 c2 c1' c2',
c1 / pe_st || c1' / pe_st' ->
c2 / pe_st' || c2' / pe_st'' ->
(c1 ;; c2) / pe_st || (c1' ;; c2') / pe_st''
| PE_IfTrue : forall pe_st pe_st' b1 c1 c2 c1',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c1' / pe_st'
| PE_IfFalse : forall pe_st pe_st' b1 c1 c2 c2',
pe_bexp pe_st b1 = BFalse ->
c2 / pe_st || c2' / pe_st' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c2' / pe_st'
| PE_If : forall pe_st pe_st1 pe_st2 b1 c1 c2 c1' c2',
pe_bexp pe_st b1 <> BTrue ->
pe_bexp pe_st b1 <> BFalse ->
c1 / pe_st || c1' / pe_st1 ->
c2 / pe_st || c2' / pe_st2 ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st
|| (IFB pe_bexp pe_st b1
THEN c1' ;; assign pe_st1 (pe_compare pe_st1 pe_st2)
ELSE c2' ;; assign pe_st2 (pe_compare pe_st1 pe_st2) FI)
/ pe_removes pe_st1 (pe_compare pe_st1 pe_st2)
where "c1 '/' st '||' c1' '/' st'" := (pe_com c1 st c1' st').
Tactic Notation "pe_com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "PE_Skip"
| Case_aux c "PE_AssStatic" | Case_aux c "PE_AssDynamic"
| Case_aux c "PE_Seq"
| Case_aux c "PE_IfTrue" | Case_aux c "PE_IfFalse" | Case_aux c "PE_If" ].
Hint Constructors pe_com.
Hint Constructors ceval.
(** ** Examples *)
(** Below are some examples of using the partial evaluator. To make
the [pe_com] relation actually usable for automatic partial
evaluation, we would need to define more automation tactics in
Coq. That is not hard to do, but it is not needed here. *)
Example pe_example1:
(X ::= ANum 3 ;; Y ::= AMult (AId Z) (APlus (AId X) (AId X)))
/ [] || (SKIP;; Y ::= AMult (AId Z) (ANum 6)) / [(X,3)].
Proof. eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_AssDynamic. reflexivity. intros n H. inversion H. Qed.
Example pe_example2:
(X ::= ANum 3 ;; IFB BLe (AId X) (ANum 4) THEN X ::= ANum 4 ELSE SKIP FI)
/ [] || (SKIP;; SKIP) / [(X,4)].
Proof. eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_IfTrue. reflexivity.
eapply PE_AssStatic. reflexivity. Qed.
Example pe_example3:
(X ::= ANum 3;;
IFB BLe (AId Y) (ANum 4) THEN
Y ::= ANum 4;;
IFB BEq (AId X) (AId Y) THEN Y ::= ANum 999 ELSE SKIP FI
ELSE SKIP FI) / []
|| (SKIP;;
IFB BLe (AId Y) (ANum 4) THEN
(SKIP;; SKIP);; (SKIP;; Y ::= ANum 4)
ELSE SKIP;; SKIP FI)
/ [(X,3)].
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_If; intuition eauto; try solve by inversion.
econstructor. eapply PE_AssStatic. reflexivity.
eapply PE_IfFalse. reflexivity. econstructor.
reflexivity. reflexivity. Qed.
(** ** Correctness of Partial Evaluation *)
(** Finally let's prove that this partial evaluator is correct! *)
Reserved Notation "c' '/' pe_st' '/' st '||' st''"
(at level 40, pe_st' at level 39, st at level 39).
Inductive pe_ceval
(c':com) (pe_st':pe_state) (st:state) (st'':state) : Prop :=
| pe_ceval_intro : forall st',
c' / st || st' ->
pe_override st' pe_st' = st'' ->
c' / pe_st' / st || st''
where "c' '/' pe_st' '/' st '||' st''" := (pe_ceval c' pe_st' st st'').
Hint Constructors pe_ceval.
Theorem pe_com_complete:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' ->
forall st st'',
(c / pe_override st pe_st || st'') ->
(c' / pe_st' / st || st'').
Proof. intros c pe_st pe_st' c' Hpe.
pe_com_cases (induction Hpe) Case; intros st st'' Heval;
try (inversion Heval; subst;
try (rewrite -> pe_bexp_correct, -> H in *; solve by inversion);
[]);
eauto.
Case "PE_AssStatic". econstructor. econstructor.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_add.
rewrite -> H. reflexivity.
Case "PE_AssDynamic". econstructor. econstructor. reflexivity.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_remove.
reflexivity.
Case "PE_Seq".
edestruct IHHpe1. eassumption. subst.
edestruct IHHpe2. eassumption.
eauto.
Case "PE_If". inversion Heval; subst.
SCase "E'IfTrue". edestruct IHHpe1. eassumption.
econstructor. apply E_IfTrue. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite <- assign_removes. eassumption.
SCase "E_IfFalse". edestruct IHHpe2. eassumption.
econstructor. apply E_IfFalse. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite -> pe_compare_override.
rewrite <- assign_removes. eassumption.
Qed.
Theorem pe_com_sound:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' ->
forall st st'',
(c' / pe_st' / st || st'') ->
(c / pe_override st pe_st || st'').
Proof. intros c pe_st pe_st' c' Hpe.
pe_com_cases (induction Hpe) Case;
intros st st'' [st' Heval Heq];
try (inversion Heval; []; subst); auto.
Case "PE_AssStatic". rewrite <- pe_override_update_add. apply E_Ass.
rewrite -> pe_aexp_correct. rewrite -> H. reflexivity.
Case "PE_AssDynamic". rewrite <- pe_override_update_remove. apply E_Ass.
rewrite <- pe_aexp_correct. reflexivity.
Case "PE_Seq". eapply E_Seq; eauto.
Case "PE_IfTrue". apply E_IfTrue.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity. eauto.
Case "PE_IfFalse". apply E_IfFalse.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity. eauto.
Case "PE_If".
inversion Heval; subst; inversion H7;
(eapply ceval_deterministic in H8; [| apply eval_assign]); subst.
SCase "E_IfTrue".
apply E_IfTrue. rewrite -> pe_bexp_correct. assumption.
rewrite <- assign_removes. eauto.
SCase "E_IfFalse".
rewrite -> pe_compare_override.
apply E_IfFalse. rewrite -> pe_bexp_correct. assumption.
rewrite <- assign_removes. eauto.
Qed.
(** The main theorem. Thanks to David Menendez for this formulation! *)
Corollary pe_com_correct:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' ->
forall st st'',
(c / pe_override st pe_st || st'') <->
(c' / pe_st' / st || st'').
Proof. intros c pe_st pe_st' c' H st st''. split.
Case "->". apply pe_com_complete. apply H.
Case "<-". apply pe_com_sound. apply H.
Qed.
(* ####################################################### *)
(** * Partial Evaluation of Loops *)
(** It may seem straightforward at first glance to extend the partial
evaluation relation [pe_com] above to loops. Indeed, many loops
are easy to deal with. Considered this repeated-squaring loop,
for example:
WHILE BLe (ANum 1) (AId X) DO
Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1)
END
If we know neither [X] nor [Y] statically, then the entire loop is
dynamic and the residual command should be the same. If we know
[X] but not [Y], then the loop can be unrolled all the way and the
residual command should be
Y ::= AMult (AId Y) (AId Y);;
Y ::= AMult (AId Y) (AId Y);;
Y ::= AMult (AId Y) (AId Y)
if [X] is initially [3] (and finally [0]). In general, a loop is
easy to partially evaluate if the final partial state of the loop
body is equal to the initial state, or if its guard condition is
static.
But there are other loops for which it is hard to express the
residual program we want in Imp. For example, take this program
for checking if [Y] is even or odd:
X ::= ANum 0;;
WHILE BLe (ANum 1) (AId Y) DO
Y ::= AMinus (AId Y) (ANum 1);;
X ::= AMinus (ANum 1) (AId X)
END
The value of [X] alternates between [0] and [1] during the loop.
Ideally, we would like to unroll this loop, not all the way but
_two-fold_, into something like
WHILE BLe (ANum 1) (AId Y) DO
Y ::= AMinus (AId Y) (ANum 1);;
IF BLe (ANum 1) (AId Y) THEN
Y ::= AMinus (AId Y) (ANum 1)
ELSE
X ::= ANum 1;; EXIT
FI
END;;
X ::= ANum 0
Unfortunately, there is no [EXIT] command in Imp. Without
extending the range of control structures available in our
language, the best we can do is to repeat loop-guard tests or add
flag variables. Neither option is terribly attractive.
Still, as a digression, below is an attempt at performing partial
evaluation on Imp commands. We add one more command argument
[c''] to the [pe_com] relation, which keeps track of a loop to
roll up. *)
Module Loop.
Reserved Notation "c1 '/' st '||' c1' '/' st' '/' c''"
(at level 40, st at level 39, c1' at level 39, st' at level 39).
Inductive pe_com : com -> pe_state -> com -> pe_state -> com -> Prop :=
| PE_Skip : forall pe_st,
SKIP / pe_st || SKIP / pe_st / SKIP
| PE_AssStatic : forall pe_st a1 n1 l,
pe_aexp pe_st a1 = ANum n1 ->
(l ::= a1) / pe_st || SKIP / pe_add pe_st l n1 / SKIP
| PE_AssDynamic : forall pe_st a1 a1' l,
pe_aexp pe_st a1 = a1' ->
(forall n, a1' <> ANum n) ->
(l ::= a1) / pe_st || (l ::= a1') / pe_remove pe_st l / SKIP
| PE_Seq : forall pe_st pe_st' pe_st'' c1 c2 c1' c2' c'',
c1 / pe_st || c1' / pe_st' / SKIP ->
c2 / pe_st' || c2' / pe_st'' / c'' ->
(c1 ;; c2) / pe_st || (c1' ;; c2') / pe_st'' / c''
| PE_IfTrue : forall pe_st pe_st' b1 c1 c2 c1' c'',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c1' / pe_st' / c''
| PE_IfFalse : forall pe_st pe_st' b1 c1 c2 c2' c'',
pe_bexp pe_st b1 = BFalse ->
c2 / pe_st || c2' / pe_st' / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c2' / pe_st' / c''
| PE_If : forall pe_st pe_st1 pe_st2 b1 c1 c2 c1' c2' c'',
pe_bexp pe_st b1 <> BTrue ->
pe_bexp pe_st b1 <> BFalse ->
c1 / pe_st || c1' / pe_st1 / c'' ->
c2 / pe_st || c2' / pe_st2 / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st
|| (IFB pe_bexp pe_st b1
THEN c1' ;; assign pe_st1 (pe_compare pe_st1 pe_st2)
ELSE c2' ;; assign pe_st2 (pe_compare pe_st1 pe_st2) FI)
/ pe_removes pe_st1 (pe_compare pe_st1 pe_st2)
/ c''
| PE_WhileEnd : forall pe_st b1 c1,
pe_bexp pe_st b1 = BFalse ->
(WHILE b1 DO c1 END) / pe_st || SKIP / pe_st / SKIP
| PE_WhileLoop : forall pe_st pe_st' pe_st'' b1 c1 c1' c2' c2'',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st' || c2' / pe_st'' / c2'' ->
pe_compare pe_st pe_st'' <> [] ->
(WHILE b1 DO c1 END) / pe_st || (c1';;c2') / pe_st'' / c2''
| PE_While : forall pe_st pe_st' pe_st'' b1 c1 c1' c2' c2'',
pe_bexp pe_st b1 <> BFalse ->
pe_bexp pe_st b1 <> BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st' || c2' / pe_st'' / c2'' ->
pe_compare pe_st pe_st'' <> [] ->
(c2'' = SKIP \/ c2'' = WHILE b1 DO c1 END) ->
(WHILE b1 DO c1 END) / pe_st
|| (IFB pe_bexp pe_st b1
THEN c1';; c2';; assign pe_st'' (pe_compare pe_st pe_st'')
ELSE assign pe_st (pe_compare pe_st pe_st'') FI)
/ pe_removes pe_st (pe_compare pe_st pe_st'')
/ c2''
| PE_WhileFixedEnd : forall pe_st b1 c1,
pe_bexp pe_st b1 <> BFalse ->
(WHILE b1 DO c1 END) / pe_st || SKIP / pe_st / (WHILE b1 DO c1 END)
| PE_WhileFixedLoop : forall pe_st pe_st' pe_st'' b1 c1 c1' c2',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st'
|| c2' / pe_st'' / (WHILE b1 DO c1 END) ->
pe_compare pe_st pe_st'' = [] ->
(WHILE b1 DO c1 END) / pe_st
|| (WHILE BTrue DO SKIP END) / pe_st / SKIP
(* Because we have an infinite loop, we should actually
start to throw away the rest of the program:
(WHILE b1 DO c1 END) / pe_st
|| SKIP / pe_st / (WHILE BTrue DO SKIP END) *)
| PE_WhileFixed : forall pe_st pe_st' pe_st'' b1 c1 c1' c2',
pe_bexp pe_st b1 <> BFalse ->
pe_bexp pe_st b1 <> BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st'
|| c2' / pe_st'' / (WHILE b1 DO c1 END) ->
pe_compare pe_st pe_st'' = [] ->
(WHILE b1 DO c1 END) / pe_st
|| (WHILE pe_bexp pe_st b1 DO c1';; c2' END) / pe_st / SKIP
where "c1 '/' st '||' c1' '/' st' '/' c''" := (pe_com c1 st c1' st' c'').
Tactic Notation "pe_com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "PE_Skip"
| Case_aux c "PE_AssStatic" | Case_aux c "PE_AssDynamic"
| Case_aux c "PE_Seq"
| Case_aux c "PE_IfTrue" | Case_aux c "PE_IfFalse" | Case_aux c "PE_If"
| Case_aux c "PE_WhileEnd" | Case_aux c "PE_WhileLoop"
| Case_aux c "PE_While" | Case_aux c "PE_WhileFixedEnd"
| Case_aux c "PE_WhileFixedLoop" | Case_aux c "PE_WhileFixed" ].
Hint Constructors pe_com.
(** ** Examples *)
Ltac step i :=
(eapply i; intuition eauto; try solve by inversion);
repeat (try eapply PE_Seq;
try (eapply PE_AssStatic; simpl; reflexivity);
try (eapply PE_AssDynamic;
[ simpl; reflexivity
| intuition eauto; solve by inversion ])).
Definition square_loop: com :=
WHILE BLe (ANum 1) (AId X) DO
Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1)
END.
Example pe_loop_example1:
square_loop / []
|| (WHILE BLe (ANum 1) (AId X) DO
(Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1));; SKIP
END) / [] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
step PE_WhileFixed. step PE_WhileFixedEnd. reflexivity.
reflexivity. reflexivity. Qed.
Example pe_loop_example2:
(X ::= ANum 3;; square_loop) / []
|| (SKIP;;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
SKIP) / [(X,0)] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_WhileLoop.
step PE_WhileLoop.
step PE_WhileLoop.
step PE_WhileEnd.
inversion H. inversion H. inversion H.
reflexivity. reflexivity. Qed.
Example pe_loop_example3:
(Z ::= ANum 3;; subtract_slowly) / []
|| (SKIP;;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
WHILE BNot (BEq (AId X) (ANum 0)) DO
(SKIP;; X ::= AMinus (AId X) (ANum 1));; SKIP
END;;
SKIP;; Z ::= ANum 0
ELSE SKIP;; Z ::= ANum 1 FI;; SKIP
ELSE SKIP;; Z ::= ANum 2 FI;; SKIP
ELSE SKIP;; Z ::= ANum 3 FI) / [] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_While.
step PE_While.
step PE_While.
step PE_WhileFixed.
step PE_WhileFixedEnd.
reflexivity. inversion H. inversion H. inversion H.
reflexivity. reflexivity. Qed.
Example pe_loop_example4:
(X ::= ANum 0;;
WHILE BLe (AId X) (ANum 2) DO
X ::= AMinus (ANum 1) (AId X)
END) / [] || (SKIP;; WHILE BTrue DO SKIP END) / [(X,0)] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_WhileFixedLoop.
step PE_WhileLoop.
step PE_WhileFixedEnd.
inversion H. reflexivity. reflexivity. reflexivity. Qed.
(** ** Correctness *)
(** Because this partial evaluator can unroll a loop n-fold where n is
a (finite) integer greater than one, in order to show it correct
we need to perform induction not structurally on dynamic
evaluation but on the number of times dynamic evaluation enters a
loop body. *)
Reserved Notation "c1 '/' st '||' st' '#' n"
(at level 40, st at level 39, st' at level 39).
Inductive ceval_count : com -> state -> state -> nat -> Prop :=
| E'Skip : forall st,
SKIP / st || st # 0
| E'Ass : forall st a1 n l,
aeval st a1 = n ->
(l ::= a1) / st || (update st l n) # 0
| E'Seq : forall c1 c2 st st' st'' n1 n2,
c1 / st || st' # n1 ->
c2 / st' || st'' # n2 ->
(c1 ;; c2) / st || st'' # (n1 + n2)
| E'IfTrue : forall st st' b1 c1 c2 n,
beval st b1 = true ->
c1 / st || st' # n ->
(IFB b1 THEN c1 ELSE c2 FI) / st || st' # n
| E'IfFalse : forall st st' b1 c1 c2 n,
beval st b1 = false ->
c2 / st || st' # n ->
(IFB b1 THEN c1 ELSE c2 FI) / st || st' # n
| E'WhileEnd : forall b1 st c1,
beval st b1 = false ->
(WHILE b1 DO c1 END) / st || st # 0
| E'WhileLoop : forall st st' st'' b1 c1 n1 n2,
beval st b1 = true ->
c1 / st || st' # n1 ->
(WHILE b1 DO c1 END) / st' || st'' # n2 ->
(WHILE b1 DO c1 END) / st || st'' # S (n1 + n2)
where "c1 '/' st '||' st' # n" := (ceval_count c1 st st' n).
Tactic Notation "ceval_count_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E'Skip" | Case_aux c "E'Ass" | Case_aux c "E'Seq"
| Case_aux c "E'IfTrue" | Case_aux c "E'IfFalse"
| Case_aux c "E'WhileEnd" | Case_aux c "E'WhileLoop" ].
Hint Constructors ceval_count.
Theorem ceval_count_complete: forall c st st',
c / st || st' -> exists n, c / st || st' # n.
Proof. intros c st st' Heval.
induction Heval;
try inversion IHHeval1;
try inversion IHHeval2;
try inversion IHHeval;
eauto. Qed.
Theorem ceval_count_sound: forall c st st' n,
c / st || st' # n -> c / st || st'.
Proof. intros c st st' n Heval. induction Heval; eauto. Qed.
Theorem pe_compare_nil_lookup: forall pe_st1 pe_st2,
pe_compare pe_st1 pe_st2 = [] ->
forall V, pe_lookup pe_st1 V = pe_lookup pe_st2 V.
Proof. intros pe_st1 pe_st2 H V.
apply (pe_compare_correct pe_st1 pe_st2 V).
rewrite H. intro. inversion H0. Qed.
Theorem pe_compare_nil_override: forall pe_st1 pe_st2,
pe_compare pe_st1 pe_st2 = [] ->
forall st, pe_override st pe_st1 = pe_override st pe_st2.
Proof. intros pe_st1 pe_st2 H st.
apply functional_extensionality. intros V.
rewrite !pe_override_correct.
apply pe_compare_nil_lookup with (V:=V) in H.
rewrite H. reflexivity. Qed.
Reserved Notation "c' '/' pe_st' '/' c'' '/' st '||' st'' '#' n"
(at level 40, pe_st' at level 39, c'' at level 39,
st at level 39, st'' at level 39).
Inductive pe_ceval_count (c':com) (pe_st':pe_state) (c'':com)
(st:state) (st'':state) (n:nat) : Prop :=
| pe_ceval_count_intro : forall st' n',
c' / st || st' ->
c'' / pe_override st' pe_st' || st'' # n' ->
n' <= n ->
c' / pe_st' / c'' / st || st'' # n
where "c' '/' pe_st' '/' c'' '/' st '||' st'' '#' n" :=
(pe_ceval_count c' pe_st' c'' st st'' n).
Hint Constructors pe_ceval_count.
Lemma pe_ceval_count_le: forall c' pe_st' c'' st st'' n n',
n' <= n ->
c' / pe_st' / c'' / st || st'' # n' ->
c' / pe_st' / c'' / st || st'' # n.
Proof. intros c' pe_st' c'' st st'' n n' Hle H. inversion H.
econstructor; try eassumption. omega. Qed.
Theorem pe_com_complete:
forall c pe_st pe_st' c' c'', c / pe_st || c' / pe_st' / c'' ->
forall st st'' n,
(c / pe_override st pe_st || st'' # n) ->
(c' / pe_st' / c'' / st || st'' # n).
Proof. intros c pe_st pe_st' c' c'' Hpe.
pe_com_cases (induction Hpe) Case; intros st st'' n Heval;
try (inversion Heval; subst;
try (rewrite -> pe_bexp_correct, -> H in *; solve by inversion);
[]);
eauto.
Case "PE_AssStatic". econstructor. econstructor.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_add.
rewrite -> H. apply E'Skip. auto.
Case "PE_AssDynamic". econstructor. econstructor. reflexivity.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_remove.
apply E'Skip. auto.
Case "PE_Seq".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor; eauto. omega.
Case "PE_If". inversion Heval; subst.
SCase "E'IfTrue". edestruct IHHpe1. eassumption.
econstructor. apply E_IfTrue. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite <- assign_removes. eassumption. eassumption.
SCase "E_IfFalse". edestruct IHHpe2. eassumption.
econstructor. apply E_IfFalse. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite -> pe_compare_override.
rewrite <- assign_removes. eassumption. eassumption.
Case "PE_WhileLoop".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor; eauto. omega.
Case "PE_While". inversion Heval; subst.
SCase "E_WhileEnd". econstructor. apply E_IfFalse.
rewrite <- pe_bexp_correct. assumption.
apply eval_assign.
rewrite <- assign_removes. inversion H2; subst; auto.
auto.
SCase "E_WhileLoop".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor. apply E_IfTrue.
rewrite <- pe_bexp_correct. assumption.
repeat eapply E_Seq; eauto. apply eval_assign.
rewrite -> pe_compare_override, <- assign_removes. eassumption.
omega.
Case "PE_WhileFixedLoop". apply ex_falso_quodlibet.
generalize dependent (S (n1 + n2)). intros n.
clear - Case H H0 IHHpe1 IHHpe2. generalize dependent st.
induction n using lt_wf_ind; intros st Heval. inversion Heval; subst.
SCase "E'WhileEnd". rewrite pe_bexp_correct, H in H7. inversion H7.
SCase "E'WhileLoop".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
rewrite <- (pe_compare_nil_override _ _ H0) in H7.
apply H1 in H7; [| omega]. inversion H7.
Case "PE_WhileFixed". generalize dependent st.
induction n using lt_wf_ind; intros st Heval. inversion Heval; subst.
SCase "E'WhileEnd". rewrite pe_bexp_correct in H8. eauto.
SCase "E'WhileLoop". rewrite pe_bexp_correct in H5.
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
rewrite <- (pe_compare_nil_override _ _ H1) in H8.
apply H2 in H8; [| omega]. inversion H8.
econstructor; [ eapply E_WhileLoop; eauto | eassumption | omega].
Qed.
Theorem pe_com_sound:
forall c pe_st pe_st' c' c'', c / pe_st || c' / pe_st' / c'' ->
forall st st'' n,
(c' / pe_st' / c'' / st || st'' # n) ->
(c / pe_override st pe_st || st'').
Proof. intros c pe_st pe_st' c' c'' Hpe.
pe_com_cases (induction Hpe) Case;
intros st st'' n [st' n' Heval Heval' Hle];
try (inversion Heval; []; subst);
try (inversion Heval'; []; subst); eauto.
Case "PE_AssStatic". rewrite <- pe_override_update_add. apply E_Ass.
rewrite -> pe_aexp_correct. rewrite -> H. reflexivity.
Case "PE_AssDynamic". rewrite <- pe_override_update_remove. apply E_Ass.
rewrite <- pe_aexp_correct. reflexivity.
Case "PE_Seq". eapply E_Seq; eauto.
Case "PE_IfTrue". apply E_IfTrue.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe. eauto.
Case "PE_IfFalse". apply E_IfFalse.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe. eauto.
Case "PE_If". inversion Heval; subst; inversion H7; subst; clear H7.
SCase "E_IfTrue".
eapply ceval_deterministic in H8; [| apply eval_assign]. subst.
rewrite <- assign_removes in Heval'.
apply E_IfTrue. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe1. eauto.
SCase "E_IfFalse".
eapply ceval_deterministic in H8; [| apply eval_assign]. subst.
rewrite -> pe_compare_override in Heval'.
rewrite <- assign_removes in Heval'.
apply E_IfFalse. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe2. eauto.
Case "PE_WhileEnd". apply E_WhileEnd.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
Case "PE_WhileLoop". eapply E_WhileLoop.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe1. eauto. eapply IHHpe2. eauto.
Case "PE_While". inversion Heval; subst.
SCase "E_IfTrue".
inversion H9. subst. clear H9.
inversion H10. subst. clear H10.
eapply ceval_deterministic in H11; [| apply eval_assign]. subst.
rewrite -> pe_compare_override in Heval'.
rewrite <- assign_removes in Heval'.
eapply E_WhileLoop. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe1. eauto.
eapply IHHpe2. eauto.
SCase "E_IfFalse". apply ceval_count_sound in Heval'.
eapply ceval_deterministic in H9; [| apply eval_assign]. subst.
rewrite <- assign_removes in Heval'.
inversion H2; subst.
SSCase "c2'' = SKIP". inversion Heval'. subst. apply E_WhileEnd.
rewrite -> pe_bexp_correct. assumption.
SSCase "c2'' = WHILE b1 DO c1 END". assumption.
Case "PE_WhileFixedEnd". eapply ceval_count_sound. apply Heval'.
Case "PE_WhileFixedLoop".
apply loop_never_stops in Heval. inversion Heval.
Case "PE_WhileFixed".
clear - Case H1 IHHpe1 IHHpe2 Heval.
remember (WHILE pe_bexp pe_st b1 DO c1';; c2' END) as c'.
ceval_cases (induction Heval) SCase;
inversion Heqc'; subst; clear Heqc'.
SCase "E_WhileEnd". apply E_WhileEnd.
rewrite pe_bexp_correct. assumption.
SCase "E_WhileLoop".
assert (IHHeval2' := IHHeval2 (refl_equal _)).
apply ceval_count_complete in IHHeval2'. inversion IHHeval2'.
clear IHHeval1 IHHeval2 IHHeval2'.
inversion Heval1. subst.
eapply E_WhileLoop. rewrite pe_bexp_correct. assumption. eauto.
eapply IHHpe2. econstructor. eassumption.
rewrite <- (pe_compare_nil_override _ _ H1). eassumption. apply le_n.
Qed.
Corollary pe_com_correct:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' / SKIP ->
forall st st'',
(c / pe_override st pe_st || st'') <->
(exists st', c' / st || st' /\ pe_override st' pe_st' = st'').
Proof. intros c pe_st pe_st' c' H st st''. split.
Case "->". intros Heval.
apply ceval_count_complete in Heval. inversion Heval as [n Heval'].
apply pe_com_complete with (st:=st) (st'':=st'') (n:=n) in H.
inversion H as [? ? ? Hskip ?]. inversion Hskip. subst. eauto.
assumption.
Case "<-". intros [st' [Heval Heq]]. subst st''.
eapply pe_com_sound in H. apply H.
econstructor. apply Heval. apply E'Skip. apply le_n.
Qed.
End Loop.
(* ####################################################### *)
(** * Partial Evaluation of Flowchart Programs *)
(** Instead of partially evaluating [WHILE] loops directly, the
standard approach to partially evaluating imperative programs is
to convert them into _flowcharts_. In other words, it turns out
that adding labels and jumps to our language makes it much easier
to partially evaluate. The result of partially evaluating a
flowchart is a residual flowchart. If we are lucky, the jumps in
the residual flowchart can be converted back to [WHILE] loops, but
that is not possible in general; we do not pursue it here. *)
(** ** Basic blocks *)
(** A flowchart is made of _basic blocks_, which we represent with the
inductive type [block]. A basic block is a sequence of
assignments (the constructor [Assign]), concluding with a
conditional jump (the constructor [If]) or an unconditional jump
(the constructor [Goto]). The destinations of the jumps are
specified by _labels_, which can be of any type. Therefore, we
parameterize the [block] type by the type of labels. *)
Inductive block (Label:Type) : Type :=
| Goto : Label -> block Label
| If : bexp -> Label -> Label -> block Label
| Assign : id -> aexp -> block Label -> block Label.
Tactic Notation "block_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "Goto" | Case_aux c "If" | Case_aux c "Assign" ].
Arguments Goto {Label} _.
Arguments If {Label} _ _ _.
Arguments Assign {Label} _ _ _.
(** We use the "even or odd" program, expressed above in Imp, as our
running example. Converting this program into a flowchart turns
out to require 4 labels, so we define the following type. *)
Inductive parity_label : Type :=
| entry : parity_label
| loop : parity_label
| body : parity_label
| done : parity_label.
(** The following [block] is the basic block found at the [body] label
of the example program. *)
Definition parity_body : block parity_label :=
Assign Y (AMinus (AId Y) (ANum 1))
(Assign X (AMinus (ANum 1) (AId X))
(Goto loop)).
(** To evaluate a basic block, given an initial state, is to compute
the final state and the label to jump to next. Because basic
blocks do not _contain_ loops or other control structures,
evaluation of basic blocks is a total function -- we don't need to
worry about non-termination. *)
Fixpoint keval {L:Type} (st:state) (k : block L) : state * L :=
match k with
| Goto l => (st, l)
| If b l1 l2 => (st, if beval st b then l1 else l2)
| Assign i a k => keval (update st i (aeval st a)) k
end.
Example keval_example:
keval empty_state parity_body
= (update (update empty_state Y 0) X 1, loop).
Proof. reflexivity. Qed.
(** ** Flowchart programs *)
(** A flowchart program is simply a lookup function that maps labels
to basic blocks. Actually, some labels are _halting states_ and
do not map to any basic block. So, more precisely, a flowchart
[program] whose labels are of type [L] is a function from [L] to
[option (block L)]. *)
Definition program (L:Type) : Type := L -> option (block L).
Definition parity : program parity_label := fun l =>
match l with
| entry => Some (Assign X (ANum 0) (Goto loop))
| loop => Some (If (BLe (ANum 1) (AId Y)) body done)
| body => Some parity_body
| done => None (* halt *)
end.
(** Unlike a basic block, a program may not terminate, so we model the
evaluation of programs by an inductive relation [peval] rather
than a recursive function. *)
Inductive peval {L:Type} (p : program L)
: state -> L -> state -> L -> Prop :=
| E_None: forall st l,
p l = None ->
peval p st l st l
| E_Some: forall st l k st' l' st'' l'',
p l = Some k ->
keval st k = (st', l') ->
peval p st' l' st'' l'' ->
peval p st l st'' l''.
Example parity_eval: peval parity empty_state entry empty_state done.
Proof. erewrite f_equal with (f := fun st => peval _ _ _ st _).
eapply E_Some. reflexivity. reflexivity.
eapply E_Some. reflexivity. reflexivity.
apply E_None. reflexivity.
apply functional_extensionality. intros i. rewrite update_same; auto.
Qed.
Tactic Notation "peval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_None" | Case_aux c "E_Some" ].
(** ** Partial evaluation of basic blocks and flowchart programs *)
(** Partial evaluation changes the label type in a systematic way: if
the label type used to be [L], it becomes [pe_state * L]. So the
same label in the original program may be unfolded, or blown up,
into multiple labels by being paired with different partial
states. For example, the label [loop] in the [parity] program
will become two labels: [([(X,0)], loop)] and [([(X,1)], loop)].
This change of label type is reflected in the types of [pe_block]
and [pe_program] defined presently. *)
Fixpoint pe_block {L:Type} (pe_st:pe_state) (k : block L)
: block (pe_state * L) :=
match k with
| Goto l => Goto (pe_st, l)
| If b l1 l2 =>
match pe_bexp pe_st b with
| BTrue => Goto (pe_st, l1)
| BFalse => Goto (pe_st, l2)
| b' => If b' (pe_st, l1) (pe_st, l2)
end
| Assign i a k =>
match pe_aexp pe_st a with
| ANum n => pe_block (pe_add pe_st i n) k
| a' => Assign i a' (pe_block (pe_remove pe_st i) k)
end
end.
Example pe_block_example:
pe_block [(X,0)] parity_body
= Assign Y (AMinus (AId Y) (ANum 1)) (Goto ([(X,1)], loop)).
Proof. reflexivity. Qed.
Theorem pe_block_correct: forall (L:Type) st pe_st k st' pe_st' (l':L),
keval st (pe_block pe_st k) = (st', (pe_st', l')) ->
keval (pe_override st pe_st) k = (pe_override st' pe_st', l').
Proof. intros. generalize dependent pe_st. generalize dependent st.
block_cases (induction k as [l | b l1 l2 | i a k]) Case;
intros st pe_st H.
Case "Goto". inversion H; reflexivity.
Case "If".
replace (keval st (pe_block pe_st (If b l1 l2)))
with (keval st (If (pe_bexp pe_st b) (pe_st, l1) (pe_st, l2)))
in H by (simpl; destruct (pe_bexp pe_st b); reflexivity).
simpl in *. rewrite pe_bexp_correct.
destruct (beval st (pe_bexp pe_st b)); inversion H; reflexivity.
Case "Assign".
simpl in *. rewrite pe_aexp_correct.
destruct (pe_aexp pe_st a); simpl;
try solve [rewrite pe_override_update_add; apply IHk; apply H];
solve [rewrite pe_override_update_remove; apply IHk; apply H].
Qed.
Definition pe_program {L:Type} (p : program L)
: program (pe_state * L) :=
fun pe_l => match pe_l with (pe_st, l) =>
option_map (pe_block pe_st) (p l)
end.
Inductive pe_peval {L:Type} (p : program L)
(st:state) (pe_st:pe_state) (l:L) (st'o:state) (l':L) : Prop :=
| pe_peval_intro : forall st' pe_st',
peval (pe_program p) st (pe_st, l) st' (pe_st', l') ->
pe_override st' pe_st' = st'o ->
pe_peval p st pe_st l st'o l'.
Theorem pe_program_correct:
forall (L:Type) (p : program L) st pe_st l st'o l',
peval p (pe_override st pe_st) l st'o l' <->
pe_peval p st pe_st l st'o l'.
Proof. intros.
split; [Case "->" | Case "<-"].
Case "->". intros Heval.
remember (pe_override st pe_st) as sto.
generalize dependent pe_st. generalize dependent st.
peval_cases (induction Heval as
[ sto l Hlookup | sto l k st'o l' st''o l'' Hlookup Hkeval Heval ])
SCase; intros st pe_st Heqsto; subst sto.
SCase "E_None". eapply pe_peval_intro. apply E_None.
simpl. rewrite Hlookup. reflexivity. reflexivity.
SCase "E_Some".
remember (keval st (pe_block pe_st k)) as x.
destruct x as [st' [pe_st' l'_]].
symmetry in Heqx. erewrite pe_block_correct in Hkeval by apply Heqx.
inversion Hkeval. subst st'o l'_. clear Hkeval.
edestruct IHHeval. reflexivity. subst st''o. clear IHHeval.
eapply pe_peval_intro; [| reflexivity]. eapply E_Some; eauto.
simpl. rewrite Hlookup. reflexivity.
Case "<-". intros [st' pe_st' Heval Heqst'o].
remember (pe_st, l) as pe_st_l.
remember (pe_st', l') as pe_st'_l'.
generalize dependent pe_st. generalize dependent l.
peval_cases (induction Heval as
[ st [pe_st_ l_] Hlookup
| st [pe_st_ l_] pe_k st' [pe_st'_ l'_] st'' [pe_st'' l'']
Hlookup Hkeval Heval ])
SCase; intros l pe_st Heqpe_st_l;
inversion Heqpe_st_l; inversion Heqpe_st'_l'; repeat subst.
SCase "E_None". apply E_None. simpl in Hlookup.
destruct (p l'); [ solve [ inversion Hlookup ] | reflexivity ].
SCase "E_Some".
simpl in Hlookup. remember (p l) as k.
destruct k as [k|]; inversion Hlookup; subst.
eapply E_Some; eauto. apply pe_block_correct. apply Hkeval.
Qed.
|
(** * PE: Partial Evaluation *)
(* $Date: 2013-07-17 16:19:11 -0400 (Wed, 17 Jul 2013) $ *)
(* Chapter author/maintainer: Chung-chieh Shan *)
(** Equiv.v introduced constant folding as an example of a program
transformation and proved that it preserves the meaning of the
program. Constant folding operates on manifest constants such
as [ANum] expressions. For example, it simplifies the command
[Y ::= APlus (ANum 3) (ANum 1)] to the command [Y ::= ANum 4].
However, it does not propagate known constants along data flow.
For example, it does not simplify the sequence
X ::= ANum 3;; Y ::= APlus (AId X) (ANum 1)
to
X ::= ANum 3;; Y ::= ANum 4
because it forgets that [X] is [3] by the time it gets to [Y].
We naturally want to enhance constant folding so that it
propagates known constants and uses them to simplify programs.
Doing so constitutes a rudimentary form of _partial evaluation_.
As we will see, partial evaluation is so called because it is
like running a program, except only part of the program can be
evaluated because only part of the input to the program is known.
For example, we can only simplify the program
X ::= ANum 3;; Y ::= AMinus (APlus (AId X) (ANum 1)) (AId Y)
to
X ::= ANum 3;; Y ::= AMinus (ANum 4) (AId Y)
without knowing the initial value of [Y]. *)
Require Export Imp.
Require Import FunctionalExtensionality.
(* ####################################################### *)
(** * Generalizing Constant Folding *)
(** The starting point of partial evaluation is to represent our
partial knowledge about the state. For example, between the two
assignments above, the partial evaluator may know only that [X] is
[3] and nothing about any other variable. *)
(** ** Partial States *)
(** Conceptually speaking, we can think of such partial states as the
type [id -> option nat] (as opposed to the type [id -> nat] of
concrete, full states). However, in addition to looking up and
updating the values of individual variables in a partial state, we
may also want to compare two partial states to see if and where
they differ, to handle conditional control flow. It is not possible
to compare two arbitrary functions in this way, so we represent
partial states in a more concrete format: as a list of [id * nat]
pairs. *)
Definition pe_state := list (id * nat).
(** The idea is that a variable [id] appears in the list if and only
if we know its current [nat] value. The [pe_lookup] function thus
interprets this concrete representation. (If the same variable
[id] appears multiple times in the list, the first occurrence
wins, but we will define our partial evaluator to never construct
such a [pe_state].) *)
Fixpoint pe_lookup (pe_st : pe_state) (V:id) : option nat :=
match pe_st with
| [] => None
| (V',n')::pe_st => if eq_id_dec V V' then Some n'
else pe_lookup pe_st V
end.
(** For example, [empty_pe_state] represents complete ignorance about
every variable -- the function that maps every [id] to [None]. *)
Definition empty_pe_state : pe_state := [].
(** More generally, if the [list] representing a [pe_state] does not
contain some [id], then that [pe_state] must map that [id] to
[None]. Before we prove this fact, we first define a useful
tactic for reasoning with [id] equality. The tactic
compare V V' SCase
means to reason by cases over [eq_id_dec V V'].
In the case where [V = V'], the tactic
substitutes [V] for [V'] throughout. *)
Tactic Notation "compare" ident(i) ident(j) ident(c) :=
let H := fresh "Heq" i j in
destruct (eq_id_dec i j);
[ Case_aux c "equal"; subst j
| Case_aux c "not equal" ].
Theorem pe_domain: forall pe_st V n,
pe_lookup pe_st V = Some n ->
In V (map (@fst _ _) pe_st).
Proof. intros pe_st V n H. induction pe_st as [| [V' n'] pe_st].
Case "[]". inversion H.
Case "::". simpl in H. simpl. compare V V' SCase; auto. Qed.
(** *** Aside on [In].
We will make heavy use of the [In] predicate from the standard library.
[In] is equivalent to the [appears_in] predicate introduced in Logic.v, but
defined using a [Fixpoint] rather than an [Inductive]. *)
Print In.
(* ===> Fixpoint In {A:Type} (a: A) (l:list A) : Prop :=
match l with
| [] => False
| b :: m => b = a \/ In a m
end
: forall A : Type, A -> list A -> Prop *)
(** [In] comes with various useful lemmas. *)
Check in_or_app.
(* ===> in_or_app: forall (A : Type) (l m : list A) (a : A),
In a l \/ In a m -> In a (l ++ m) *)
Check filter_In.
(* ===> filter_In : forall (A : Type) (f : A -> bool) (x : A) (l : list A),
In x (filter f l) <-> In x l /\ f x = true *)
Check in_dec.
(* ===> in_dec : forall A : Type,
(forall x y : A, {x = y} + {x <> y}) ->
forall (a : A) (l : list A), {In a l} + {~ In a l}] *)
(** Note that we can compute with [in_dec], just as with [eq_id_dec]. *)
(** ** Arithmetic Expressions *)
(** Partial evaluation of [aexp] is straightforward -- it is basically
the same as constant folding, [fold_constants_aexp], except that
sometimes the partial state tells us the current value of a
variable and we can replace it by a constant expression. *)
Fixpoint pe_aexp (pe_st : pe_state) (a : aexp) : aexp :=
match a with
| ANum n => ANum n
| AId i => match pe_lookup pe_st i with (* <----- NEW *)
| Some n => ANum n
| None => AId i
end
| APlus a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 + n2)
| (a1', a2') => APlus a1' a2'
end
| AMinus a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 - n2)
| (a1', a2') => AMinus a1' a2'
end
| AMult a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 * n2)
| (a1', a2') => AMult a1' a2'
end
end.
(** This partial evaluator folds constants but does not apply the
associativity of addition. *)
Example test_pe_aexp1:
pe_aexp [(X,3)] (APlus (APlus (AId X) (ANum 1)) (AId Y))
= APlus (ANum 4) (AId Y).
Proof. reflexivity. Qed.
Example text_pe_aexp2:
pe_aexp [(Y,3)] (APlus (APlus (AId X) (ANum 1)) (AId Y))
= APlus (APlus (AId X) (ANum 1)) (ANum 3).
Proof. reflexivity. Qed.
(** Now, in what sense is [pe_aexp] correct? It is reasonable to
define the correctness of [pe_aexp] as follows: whenever a full
state [st:state] is _consistent_ with a partial state
[pe_st:pe_state] (in other words, every variable to which [pe_st]
assigns a value is assigned the same value by [st]), evaluating
[a] and evaluating [pe_aexp pe_st a] in [st] yields the same
result. This statement is indeed true. *)
Definition pe_consistent (st:state) (pe_st:pe_state) :=
forall V n, Some n = pe_lookup pe_st V -> st V = n.
Theorem pe_aexp_correct_weak: forall st pe_st, pe_consistent st pe_st ->
forall a, aeval st a = aeval st (pe_aexp pe_st a).
Proof. unfold pe_consistent. intros st pe_st H a.
aexp_cases (induction a) Case; simpl;
try reflexivity;
try (destruct (pe_aexp pe_st a1);
destruct (pe_aexp pe_st a2);
rewrite IHa1; rewrite IHa2; reflexivity).
(* Compared to fold_constants_aexp_sound,
the only interesting case is AId *)
Case "AId".
remember (pe_lookup pe_st i) as l. destruct l.
SCase "Some". rewrite H with (n:=n) by apply Heql. reflexivity.
SCase "None". reflexivity.
Qed.
(** However, we will soon want our partial evaluator to remove
assignments. For example, it will simplify
X ::= ANum 3;; Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
to just
Y ::= AMinus (ANum 3) (AId Y);; X ::= ANum 4
by delaying the assignment to [X] until the end. To accomplish
this simplification, we need the result of partial evaluating
pe_aexp [(X,3)] (AMinus (AId X) (AId Y))
to be equal to [AMinus (ANum 3) (AId Y)] and _not_ the original
expression [AMinus (AId X) (AId Y)]. After all, it would be
incorrect, not just inefficient, to transform
X ::= ANum 3;; Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
to
Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
even though the output expressions [AMinus (ANum 3) (AId Y)] and
[AMinus (AId X) (AId Y)] both satisfy the correctness criterion
that we just proved. Indeed, if we were to just define [pe_aexp
pe_st a = a] then the theorem [pe_aexp_correct'] would already
trivially hold.
Instead, we want to prove that the [pe_aexp] is correct in a
stronger sense: evaluating the expression produced by partial
evaluation ([aeval st (pe_aexp pe_st a)]) must not depend on those
parts of the full state [st] that are already specified in the
partial state [pe_st]. To be more precise, let us define a
function [pe_override], which updates [st] with the contents of
[pe_st]. In other words, [pe_override] carries out the
assignments listed in [pe_st] on top of [st]. *)
Fixpoint pe_override (st:state) (pe_st:pe_state) : state :=
match pe_st with
| [] => st
| (V,n)::pe_st => update (pe_override st pe_st) V n
end.
Example test_pe_override:
pe_override (update empty_state Y 1) [(X,3);(Z,2)]
= update (update (update empty_state Y 1) Z 2) X 3.
Proof. reflexivity. Qed.
(** Although [pe_override] operates on a concrete [list] representing
a [pe_state], its behavior is defined entirely by the [pe_lookup]
interpretation of the [pe_state]. *)
Theorem pe_override_correct: forall st pe_st V0,
pe_override st pe_st V0 =
match pe_lookup pe_st V0 with
| Some n => n
| None => st V0
end.
Proof. intros. induction pe_st as [| [V n] pe_st]. reflexivity.
simpl in *. unfold update.
compare V0 V Case; auto. rewrite eq_id; auto. rewrite neq_id; auto. Qed.
(** We can relate [pe_consistent] to [pe_override] in two ways.
First, overriding a state with a partial state always gives a
state that is consistent with the partial state. Second, if a
state is already consistent with a partial state, then overriding
the state with the partial state gives the same state. *)
Theorem pe_override_consistent: forall st pe_st,
pe_consistent (pe_override st pe_st) pe_st.
Proof. intros st pe_st V n H. rewrite pe_override_correct.
destruct (pe_lookup pe_st V); inversion H. reflexivity. Qed.
Theorem pe_consistent_override: forall st pe_st,
pe_consistent st pe_st -> forall V, st V = pe_override st pe_st V.
Proof. intros st pe_st H V. rewrite pe_override_correct.
remember (pe_lookup pe_st V) as l. destruct l; auto. Qed.
(** Now we can state and prove that [pe_aexp] is correct in the
stronger sense that will help us define the rest of the partial
evaluator.
Intuitively, running a program using partial evaluation is a
two-stage process. In the first, _static_ stage, we partially
evaluate the given program with respect to some partial state to
get a _residual_ program. In the second, _dynamic_ stage, we
evaluate the residual program with respect to the rest of the
state. This dynamic state provides values for those variables
that are unknown in the static (partial) state. Thus, the
residual program should be equivalent to _prepending_ the
assignments listed in the partial state to the original program. *)
Theorem pe_aexp_correct: forall (pe_st:pe_state) (a:aexp) (st:state),
aeval (pe_override st pe_st) a = aeval st (pe_aexp pe_st a).
Proof.
intros pe_st a st.
aexp_cases (induction a) Case; simpl;
try reflexivity;
try (destruct (pe_aexp pe_st a1);
destruct (pe_aexp pe_st a2);
rewrite IHa1; rewrite IHa2; reflexivity).
(* Compared to fold_constants_aexp_sound, the only
interesting case is AId. *)
rewrite pe_override_correct. destruct (pe_lookup pe_st i); reflexivity.
Qed.
(** ** Boolean Expressions *)
(** The partial evaluation of boolean expressions is similar. In
fact, it is entirely analogous to the constant folding of boolean
expressions, because our language has no boolean variables. *)
Fixpoint pe_bexp (pe_st : pe_state) (b : bexp) : bexp :=
match b with
| BTrue => BTrue
| BFalse => BFalse
| BEq a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => if beq_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BEq a1' a2'
end
| BLe a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => if ble_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BLe a1' a2'
end
| BNot b1 =>
match (pe_bexp pe_st b1) with
| BTrue => BFalse
| BFalse => BTrue
| b1' => BNot b1'
end
| BAnd b1 b2 =>
match (pe_bexp pe_st b1, pe_bexp pe_st b2) with
| (BTrue, BTrue) => BTrue
| (BTrue, BFalse) => BFalse
| (BFalse, BTrue) => BFalse
| (BFalse, BFalse) => BFalse
| (b1', b2') => BAnd b1' b2'
end
end.
Example test_pe_bexp1:
pe_bexp [(X,3)] (BNot (BLe (AId X) (ANum 3)))
= BFalse.
Proof. reflexivity. Qed.
Example test_pe_bexp2: forall b,
b = BNot (BLe (AId X) (APlus (AId X) (ANum 1))) ->
pe_bexp [] b = b.
Proof. intros b H. rewrite -> H. reflexivity. Qed.
(** The correctness of [pe_bexp] is analogous to the correctness of
[pe_aexp] above. *)
Theorem pe_bexp_correct: forall (pe_st:pe_state) (b:bexp) (st:state),
beval (pe_override st pe_st) b = beval st (pe_bexp pe_st b).
Proof.
intros pe_st b st.
bexp_cases (induction b) Case; simpl;
try reflexivity;
try (remember (pe_aexp pe_st a) as a';
remember (pe_aexp pe_st a0) as a0';
assert (Ha: aeval (pe_override st pe_st) a = aeval st a');
assert (Ha0: aeval (pe_override st pe_st) a0 = aeval st a0');
try (subst; apply pe_aexp_correct);
destruct a'; destruct a0'; rewrite Ha; rewrite Ha0;
simpl; try destruct (beq_nat n n0); try destruct (ble_nat n n0);
reflexivity);
try (destruct (pe_bexp pe_st b); rewrite IHb; reflexivity);
try (destruct (pe_bexp pe_st b1);
destruct (pe_bexp pe_st b2);
rewrite IHb1; rewrite IHb2; reflexivity).
Qed.
(* ####################################################### *)
(** * Partial Evaluation of Commands, Without Loops *)
(** What about the partial evaluation of commands? The analogy
between partial evaluation and full evaluation continues: Just as
full evaluation of a command turns an initial state into a final
state, partial evaluation of a command turns an initial partial
state into a final partial state. The difference is that, because
the state is partial, some parts of the command may not be
executable at the static stage. Therefore, just as [pe_aexp]
returns a residual [aexp] and [pe_bexp] returns a residual [bexp]
above, partially evaluating a command yields a residual command.
Another way in which our partial evaluator is similar to a full
evaluator is that it does not terminate on all commands. It is
not hard to build a partial evaluator that terminates on all
commands; what is hard is building a partial evaluator that
terminates on all commands yet automatically performs desired
optimizations such as unrolling loops. Often a partial evaluator
can be coaxed into terminating more often and performing more
optimizations by writing the source program differently so that
the separation between static and dynamic information becomes more
apparent. Such coaxing is the art of _binding-time improvement_.
The binding time of a variable tells when its value is known --
either "static", or "dynamic."
Anyway, for now we will just live with the fact that our partial
evaluator is not a total function from the source command and the
initial partial state to the residual command and the final
partial state. To model this non-termination, just as with the
full evaluation of commands, we use an inductively defined
relation. We write
c1 / st || c1' / st'
to mean that partially evaluating the source command [c1] in the
initial partial state [st] yields the residual command [c1'] and
the final partial state [st']. For example, we want something like
(X ::= ANum 3 ;; Y ::= AMult (AId Z) (APlus (AId X) (AId X)))
/ [] || (Y ::= AMult (AId Z) (ANum 6)) / [(X,3)]
to hold. The assignment to [X] appears in the final partial state,
not the residual command. *)
(** ** Assignment *)
(** Let's start by considering how to partially evaluate an
assignment. The two assignments in the source program above needs
to be treated differently. The first assignment [X ::= ANum 3],
is _static_: its right-hand-side is a constant (more generally,
simplifies to a constant), so we should update our partial state
at [X] to [3] and produce no residual code. (Actually, we produce
a residual [SKIP].) The second assignment [Y ::= AMult (AId Z)
(APlus (AId X) (AId X))] is _dynamic_: its right-hand-side does
not simplify to a constant, so we should leave it in the residual
code and remove [Y], if present, from our partial state. To
implement these two cases, we define the functions [pe_add] and
[pe_remove]. Like [pe_override] above, these functions operate on
a concrete [list] representing a [pe_state], but the theorems
[pe_add_correct] and [pe_remove_correct] specify their behavior by
the [pe_lookup] interpretation of the [pe_state]. *)
Fixpoint pe_remove (pe_st:pe_state) (V:id) : pe_state :=
match pe_st with
| [] => []
| (V',n')::pe_st => if eq_id_dec V V' then pe_remove pe_st V
else (V',n') :: pe_remove pe_st V
end.
Theorem pe_remove_correct: forall pe_st V V0,
pe_lookup (pe_remove pe_st V) V0
= if eq_id_dec V V0 then None else pe_lookup pe_st V0.
Proof. intros pe_st V V0. induction pe_st as [| [V' n'] pe_st].
Case "[]". destruct (eq_id_dec V V0); reflexivity.
Case "::". simpl. compare V V' SCase.
SCase "equal". rewrite IHpe_st.
destruct (eq_id_dec V V0). reflexivity. rewrite neq_id; auto.
SCase "not equal". simpl. compare V0 V' SSCase.
SSCase "equal". rewrite neq_id; auto.
SSCase "not equal". rewrite IHpe_st. reflexivity.
Qed.
Definition pe_add (pe_st:pe_state) (V:id) (n:nat) : pe_state :=
(V,n) :: pe_remove pe_st V.
Theorem pe_add_correct: forall pe_st V n V0,
pe_lookup (pe_add pe_st V n) V0
= if eq_id_dec V V0 then Some n else pe_lookup pe_st V0.
Proof. intros pe_st V n V0. unfold pe_add. simpl.
compare V V0 Case.
Case "equal". rewrite eq_id; auto.
Case "not equal". rewrite pe_remove_correct. repeat rewrite neq_id; auto.
Qed.
(** We will use the two theorems below to show that our partial
evaluator correctly deals with dynamic assignments and static
assignments, respectively. *)
Theorem pe_override_update_remove: forall st pe_st V n,
update (pe_override st pe_st) V n =
pe_override (update st V n) (pe_remove pe_st V).
Proof. intros st pe_st V n. apply functional_extensionality. intros V0.
unfold update. rewrite !pe_override_correct. rewrite pe_remove_correct.
destruct (eq_id_dec V V0); reflexivity. Qed.
Theorem pe_override_update_add: forall st pe_st V n,
update (pe_override st pe_st) V n =
pe_override st (pe_add pe_st V n).
Proof. intros st pe_st V n. apply functional_extensionality. intros V0.
unfold update. rewrite !pe_override_correct. rewrite pe_add_correct.
destruct (eq_id_dec V V0); reflexivity. Qed.
(** ** Conditional *)
(** Trickier than assignments to partially evaluate is the
conditional, [IFB b1 THEN c1 ELSE c2 FI]. If [b1] simplifies to
[BTrue] or [BFalse] then it's easy: we know which branch will be
taken, so just take that branch. If [b1] does not simplify to a
constant, then we need to take both branches, and the final
partial state may differ between the two branches!
The following program illustrates the difficulty:
X ::= ANum 3;;
IFB BLe (AId Y) (ANum 4) THEN
Y ::= ANum 4;;
IFB BEq (AId X) (AId Y) THEN Y ::= ANum 999 ELSE SKIP FI
ELSE SKIP FI
Suppose the initial partial state is empty. We don't know
statically how [Y] compares to [4], so we must partially evaluate
both branches of the (outer) conditional. On the [THEN] branch,
we know that [Y] is set to [4] and can even use that knowledge to
simplify the code somewhat. On the [ELSE] branch, we still don't
know the exact value of [Y] at the end. What should the final
partial state and residual program be?
One way to handle such a dynamic conditional is to take the
intersection of the final partial states of the two branches. In
this example, we take the intersection of [(Y,4),(X,3)] and
[(X,3)], so the overall final partial state is [(X,3)]. To
compensate for forgetting that [Y] is [4], we need to add an
assignment [Y ::= ANum 4] to the end of the [THEN] branch. So,
the residual program will be something like
SKIP;;
IFB BLe (AId Y) (ANum 4) THEN
SKIP;;
SKIP;;
Y ::= ANum 4
ELSE SKIP FI
Programming this case in Coq calls for several auxiliary
functions: we need to compute the intersection of two [pe_state]s
and turn their difference into sequences of assignments.
First, we show how to compute whether two [pe_state]s to disagree
at a given variable. In the theorem [pe_disagree_domain], we
prove that two [pe_state]s can only disagree at variables that
appear in at least one of them. *)
Definition pe_disagree_at (pe_st1 pe_st2 : pe_state) (V:id) : bool :=
match pe_lookup pe_st1 V, pe_lookup pe_st2 V with
| Some x, Some y => negb (beq_nat x y)
| None, None => false
| _, _ => true
end.
Theorem pe_disagree_domain: forall (pe_st1 pe_st2 : pe_state) (V:id),
true = pe_disagree_at pe_st1 pe_st2 V ->
In V (map (@fst _ _) pe_st1 ++ map (@fst _ _) pe_st2).
Proof. unfold pe_disagree_at. intros pe_st1 pe_st2 V H.
apply in_or_app.
remember (pe_lookup pe_st1 V) as lookup1.
destruct lookup1 as [n1|]. left. apply pe_domain with n1. auto.
remember (pe_lookup pe_st2 V) as lookup2.
destruct lookup2 as [n2|]. right. apply pe_domain with n2. auto.
inversion H. Qed.
(** We define the [pe_compare] function to list the variables where
two given [pe_state]s disagree. This list is exact, according to
the theorem [pe_compare_correct]: a variable appears on the list
if and only if the two given [pe_state]s disagree at that
variable. Furthermore, we use the [pe_unique] function to
eliminate duplicates from the list. *)
Fixpoint pe_unique (l : list id) : list id :=
match l with
| [] => []
| x::l => x :: filter (fun y => if eq_id_dec x y then false else true) (pe_unique l)
end.
Theorem pe_unique_correct: forall l x,
In x l <-> In x (pe_unique l).
Proof. intros l x. induction l as [| h t]. reflexivity.
simpl in *. split.
Case "->".
intros. inversion H; clear H.
left. assumption.
destruct (eq_id_dec h x).
left. assumption.
right. apply filter_In. split.
apply IHt. assumption.
rewrite neq_id; auto.
Case "<-".
intros. inversion H; clear H.
left. assumption.
apply filter_In in H0. inversion H0. right. apply IHt. assumption.
Qed.
Definition pe_compare (pe_st1 pe_st2 : pe_state) : list id :=
pe_unique (filter (pe_disagree_at pe_st1 pe_st2)
(map (@fst _ _) pe_st1 ++ map (@fst _ _) pe_st2)).
Theorem pe_compare_correct: forall pe_st1 pe_st2 V,
pe_lookup pe_st1 V = pe_lookup pe_st2 V <->
~ In V (pe_compare pe_st1 pe_st2).
Proof. intros pe_st1 pe_st2 V.
unfold pe_compare. rewrite <- pe_unique_correct. rewrite filter_In.
split; intros Heq.
Case "->".
intro. destruct H. unfold pe_disagree_at in H0. rewrite Heq in H0.
destruct (pe_lookup pe_st2 V).
rewrite <- beq_nat_refl in H0. inversion H0.
inversion H0.
Case "<-".
assert (Hagree: pe_disagree_at pe_st1 pe_st2 V = false).
SCase "Proof of assertion".
remember (pe_disagree_at pe_st1 pe_st2 V) as disagree.
destruct disagree; [| reflexivity].
apply pe_disagree_domain in Heqdisagree.
apply ex_falso_quodlibet. apply Heq. split. assumption. reflexivity.
unfold pe_disagree_at in Hagree.
destruct (pe_lookup pe_st1 V) as [n1|];
destruct (pe_lookup pe_st2 V) as [n2|];
try reflexivity; try solve by inversion.
rewrite negb_false_iff in Hagree.
apply beq_nat_true in Hagree. subst. reflexivity. Qed.
(** The intersection of two partial states is the result of removing
from one of them all the variables where the two disagree. We
define the function [pe_removes], in terms of [pe_remove] above,
to perform such a removal of a whole list of variables at once.
The theorem [pe_compare_removes] testifies that the [pe_lookup]
interpretation of the result of this intersection operation is the
same no matter which of the two partial states we remove the
variables from. Because [pe_override] only depends on the
[pe_lookup] interpretation of partial states, [pe_override] also
does not care which of the two partial states we remove the
variables from; that theorem [pe_compare_override] is used in the
correctness proof shortly. *)
Fixpoint pe_removes (pe_st:pe_state) (ids : list id) : pe_state :=
match ids with
| [] => pe_st
| V::ids => pe_remove (pe_removes pe_st ids) V
end.
Theorem pe_removes_correct: forall pe_st ids V,
pe_lookup (pe_removes pe_st ids) V =
if in_dec eq_id_dec V ids then None else pe_lookup pe_st V.
Proof. intros pe_st ids V. induction ids as [| V' ids]. reflexivity.
simpl. rewrite pe_remove_correct. rewrite IHids.
compare V' V Case.
reflexivity.
destruct (in_dec eq_id_dec V ids);
reflexivity.
Qed.
Theorem pe_compare_removes: forall pe_st1 pe_st2 V,
pe_lookup (pe_removes pe_st1 (pe_compare pe_st1 pe_st2)) V =
pe_lookup (pe_removes pe_st2 (pe_compare pe_st1 pe_st2)) V.
Proof. intros pe_st1 pe_st2 V. rewrite !pe_removes_correct.
destruct (in_dec eq_id_dec V (pe_compare pe_st1 pe_st2)).
reflexivity.
apply pe_compare_correct. auto. Qed.
Theorem pe_compare_override: forall pe_st1 pe_st2 st,
pe_override st (pe_removes pe_st1 (pe_compare pe_st1 pe_st2)) =
pe_override st (pe_removes pe_st2 (pe_compare pe_st1 pe_st2)).
Proof. intros. apply functional_extensionality. intros V.
rewrite !pe_override_correct. rewrite pe_compare_removes. reflexivity.
Qed.
(** Finally, we define an [assign] function to turn the difference
between two partial states into a sequence of assignment commands.
More precisely, [assign pe_st ids] generates an assignment command
for each variable listed in [ids]. *)
Fixpoint assign (pe_st : pe_state) (ids : list id) : com :=
match ids with
| [] => SKIP
| V::ids => match pe_lookup pe_st V with
| Some n => (assign pe_st ids;; V ::= ANum n)
| None => assign pe_st ids
end
end.
(** The command generated by [assign] always terminates, because it is
just a sequence of assignments. The (total) function [assigned]
below computes the effect of the command on the (dynamic state).
The theorem [assign_removes] then confirms that the generated
assignments perfectly compensate for removing the variables from
the partial state. *)
Definition assigned (pe_st:pe_state) (ids : list id) (st:state) : state :=
fun V => if in_dec eq_id_dec V ids then
match pe_lookup pe_st V with
| Some n => n
| None => st V
end
else st V.
Theorem assign_removes: forall pe_st ids st,
pe_override st pe_st =
pe_override (assigned pe_st ids st) (pe_removes pe_st ids).
Proof. intros pe_st ids st. apply functional_extensionality. intros V.
rewrite !pe_override_correct. rewrite pe_removes_correct. unfold assigned.
destruct (in_dec eq_id_dec V ids); destruct (pe_lookup pe_st V); reflexivity.
Qed.
Lemma ceval_extensionality: forall c st st1 st2,
c / st || st1 -> (forall V, st1 V = st2 V) -> c / st || st2.
Proof. intros c st st1 st2 H Heq.
apply functional_extensionality in Heq. rewrite <- Heq. apply H. Qed.
Theorem eval_assign: forall pe_st ids st,
assign pe_st ids / st || assigned pe_st ids st.
Proof. intros pe_st ids st. induction ids as [| V ids]; simpl.
Case "[]". eapply ceval_extensionality. apply E_Skip. reflexivity.
Case "V::ids".
remember (pe_lookup pe_st V) as lookup. destruct lookup.
SCase "Some". eapply E_Seq. apply IHids. unfold assigned. simpl.
eapply ceval_extensionality. apply E_Ass. simpl. reflexivity.
intros V0. unfold update. compare V V0 SSCase.
SSCase "equal". rewrite <- Heqlookup. reflexivity.
SSCase "not equal". destruct (in_dec eq_id_dec V0 ids); auto.
SCase "None". eapply ceval_extensionality. apply IHids.
unfold assigned. intros V0. simpl. compare V V0 SSCase.
SSCase "equal". rewrite <- Heqlookup.
destruct (in_dec eq_id_dec V ids); reflexivity.
SSCase "not equal". destruct (in_dec eq_id_dec V0 ids); reflexivity. Qed.
(** ** The Partial Evaluation Relation *)
(** At long last, we can define a partial evaluator for commands
without loops, as an inductive relation! The inequality
conditions in [PE_AssDynamic] and [PE_If] are just to keep the
partial evaluator deterministic; they are not required for
correctness. *)
Reserved Notation "c1 '/' st '||' c1' '/' st'"
(at level 40, st at level 39, c1' at level 39).
Inductive pe_com : com -> pe_state -> com -> pe_state -> Prop :=
| PE_Skip : forall pe_st,
SKIP / pe_st || SKIP / pe_st
| PE_AssStatic : forall pe_st a1 n1 l,
pe_aexp pe_st a1 = ANum n1 ->
(l ::= a1) / pe_st || SKIP / pe_add pe_st l n1
| PE_AssDynamic : forall pe_st a1 a1' l,
pe_aexp pe_st a1 = a1' ->
(forall n, a1' <> ANum n) ->
(l ::= a1) / pe_st || (l ::= a1') / pe_remove pe_st l
| PE_Seq : forall pe_st pe_st' pe_st'' c1 c2 c1' c2',
c1 / pe_st || c1' / pe_st' ->
c2 / pe_st' || c2' / pe_st'' ->
(c1 ;; c2) / pe_st || (c1' ;; c2') / pe_st''
| PE_IfTrue : forall pe_st pe_st' b1 c1 c2 c1',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c1' / pe_st'
| PE_IfFalse : forall pe_st pe_st' b1 c1 c2 c2',
pe_bexp pe_st b1 = BFalse ->
c2 / pe_st || c2' / pe_st' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c2' / pe_st'
| PE_If : forall pe_st pe_st1 pe_st2 b1 c1 c2 c1' c2',
pe_bexp pe_st b1 <> BTrue ->
pe_bexp pe_st b1 <> BFalse ->
c1 / pe_st || c1' / pe_st1 ->
c2 / pe_st || c2' / pe_st2 ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st
|| (IFB pe_bexp pe_st b1
THEN c1' ;; assign pe_st1 (pe_compare pe_st1 pe_st2)
ELSE c2' ;; assign pe_st2 (pe_compare pe_st1 pe_st2) FI)
/ pe_removes pe_st1 (pe_compare pe_st1 pe_st2)
where "c1 '/' st '||' c1' '/' st'" := (pe_com c1 st c1' st').
Tactic Notation "pe_com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "PE_Skip"
| Case_aux c "PE_AssStatic" | Case_aux c "PE_AssDynamic"
| Case_aux c "PE_Seq"
| Case_aux c "PE_IfTrue" | Case_aux c "PE_IfFalse" | Case_aux c "PE_If" ].
Hint Constructors pe_com.
Hint Constructors ceval.
(** ** Examples *)
(** Below are some examples of using the partial evaluator. To make
the [pe_com] relation actually usable for automatic partial
evaluation, we would need to define more automation tactics in
Coq. That is not hard to do, but it is not needed here. *)
Example pe_example1:
(X ::= ANum 3 ;; Y ::= AMult (AId Z) (APlus (AId X) (AId X)))
/ [] || (SKIP;; Y ::= AMult (AId Z) (ANum 6)) / [(X,3)].
Proof. eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_AssDynamic. reflexivity. intros n H. inversion H. Qed.
Example pe_example2:
(X ::= ANum 3 ;; IFB BLe (AId X) (ANum 4) THEN X ::= ANum 4 ELSE SKIP FI)
/ [] || (SKIP;; SKIP) / [(X,4)].
Proof. eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_IfTrue. reflexivity.
eapply PE_AssStatic. reflexivity. Qed.
Example pe_example3:
(X ::= ANum 3;;
IFB BLe (AId Y) (ANum 4) THEN
Y ::= ANum 4;;
IFB BEq (AId X) (AId Y) THEN Y ::= ANum 999 ELSE SKIP FI
ELSE SKIP FI) / []
|| (SKIP;;
IFB BLe (AId Y) (ANum 4) THEN
(SKIP;; SKIP);; (SKIP;; Y ::= ANum 4)
ELSE SKIP;; SKIP FI)
/ [(X,3)].
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_If; intuition eauto; try solve by inversion.
econstructor. eapply PE_AssStatic. reflexivity.
eapply PE_IfFalse. reflexivity. econstructor.
reflexivity. reflexivity. Qed.
(** ** Correctness of Partial Evaluation *)
(** Finally let's prove that this partial evaluator is correct! *)
Reserved Notation "c' '/' pe_st' '/' st '||' st''"
(at level 40, pe_st' at level 39, st at level 39).
Inductive pe_ceval
(c':com) (pe_st':pe_state) (st:state) (st'':state) : Prop :=
| pe_ceval_intro : forall st',
c' / st || st' ->
pe_override st' pe_st' = st'' ->
c' / pe_st' / st || st''
where "c' '/' pe_st' '/' st '||' st''" := (pe_ceval c' pe_st' st st'').
Hint Constructors pe_ceval.
Theorem pe_com_complete:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' ->
forall st st'',
(c / pe_override st pe_st || st'') ->
(c' / pe_st' / st || st'').
Proof. intros c pe_st pe_st' c' Hpe.
pe_com_cases (induction Hpe) Case; intros st st'' Heval;
try (inversion Heval; subst;
try (rewrite -> pe_bexp_correct, -> H in *; solve by inversion);
[]);
eauto.
Case "PE_AssStatic". econstructor. econstructor.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_add.
rewrite -> H. reflexivity.
Case "PE_AssDynamic". econstructor. econstructor. reflexivity.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_remove.
reflexivity.
Case "PE_Seq".
edestruct IHHpe1. eassumption. subst.
edestruct IHHpe2. eassumption.
eauto.
Case "PE_If". inversion Heval; subst.
SCase "E'IfTrue". edestruct IHHpe1. eassumption.
econstructor. apply E_IfTrue. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite <- assign_removes. eassumption.
SCase "E_IfFalse". edestruct IHHpe2. eassumption.
econstructor. apply E_IfFalse. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite -> pe_compare_override.
rewrite <- assign_removes. eassumption.
Qed.
Theorem pe_com_sound:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' ->
forall st st'',
(c' / pe_st' / st || st'') ->
(c / pe_override st pe_st || st'').
Proof. intros c pe_st pe_st' c' Hpe.
pe_com_cases (induction Hpe) Case;
intros st st'' [st' Heval Heq];
try (inversion Heval; []; subst); auto.
Case "PE_AssStatic". rewrite <- pe_override_update_add. apply E_Ass.
rewrite -> pe_aexp_correct. rewrite -> H. reflexivity.
Case "PE_AssDynamic". rewrite <- pe_override_update_remove. apply E_Ass.
rewrite <- pe_aexp_correct. reflexivity.
Case "PE_Seq". eapply E_Seq; eauto.
Case "PE_IfTrue". apply E_IfTrue.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity. eauto.
Case "PE_IfFalse". apply E_IfFalse.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity. eauto.
Case "PE_If".
inversion Heval; subst; inversion H7;
(eapply ceval_deterministic in H8; [| apply eval_assign]); subst.
SCase "E_IfTrue".
apply E_IfTrue. rewrite -> pe_bexp_correct. assumption.
rewrite <- assign_removes. eauto.
SCase "E_IfFalse".
rewrite -> pe_compare_override.
apply E_IfFalse. rewrite -> pe_bexp_correct. assumption.
rewrite <- assign_removes. eauto.
Qed.
(** The main theorem. Thanks to David Menendez for this formulation! *)
Corollary pe_com_correct:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' ->
forall st st'',
(c / pe_override st pe_st || st'') <->
(c' / pe_st' / st || st'').
Proof. intros c pe_st pe_st' c' H st st''. split.
Case "->". apply pe_com_complete. apply H.
Case "<-". apply pe_com_sound. apply H.
Qed.
(* ####################################################### *)
(** * Partial Evaluation of Loops *)
(** It may seem straightforward at first glance to extend the partial
evaluation relation [pe_com] above to loops. Indeed, many loops
are easy to deal with. Considered this repeated-squaring loop,
for example:
WHILE BLe (ANum 1) (AId X) DO
Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1)
END
If we know neither [X] nor [Y] statically, then the entire loop is
dynamic and the residual command should be the same. If we know
[X] but not [Y], then the loop can be unrolled all the way and the
residual command should be
Y ::= AMult (AId Y) (AId Y);;
Y ::= AMult (AId Y) (AId Y);;
Y ::= AMult (AId Y) (AId Y)
if [X] is initially [3] (and finally [0]). In general, a loop is
easy to partially evaluate if the final partial state of the loop
body is equal to the initial state, or if its guard condition is
static.
But there are other loops for which it is hard to express the
residual program we want in Imp. For example, take this program
for checking if [Y] is even or odd:
X ::= ANum 0;;
WHILE BLe (ANum 1) (AId Y) DO
Y ::= AMinus (AId Y) (ANum 1);;
X ::= AMinus (ANum 1) (AId X)
END
The value of [X] alternates between [0] and [1] during the loop.
Ideally, we would like to unroll this loop, not all the way but
_two-fold_, into something like
WHILE BLe (ANum 1) (AId Y) DO
Y ::= AMinus (AId Y) (ANum 1);;
IF BLe (ANum 1) (AId Y) THEN
Y ::= AMinus (AId Y) (ANum 1)
ELSE
X ::= ANum 1;; EXIT
FI
END;;
X ::= ANum 0
Unfortunately, there is no [EXIT] command in Imp. Without
extending the range of control structures available in our
language, the best we can do is to repeat loop-guard tests or add
flag variables. Neither option is terribly attractive.
Still, as a digression, below is an attempt at performing partial
evaluation on Imp commands. We add one more command argument
[c''] to the [pe_com] relation, which keeps track of a loop to
roll up. *)
Module Loop.
Reserved Notation "c1 '/' st '||' c1' '/' st' '/' c''"
(at level 40, st at level 39, c1' at level 39, st' at level 39).
Inductive pe_com : com -> pe_state -> com -> pe_state -> com -> Prop :=
| PE_Skip : forall pe_st,
SKIP / pe_st || SKIP / pe_st / SKIP
| PE_AssStatic : forall pe_st a1 n1 l,
pe_aexp pe_st a1 = ANum n1 ->
(l ::= a1) / pe_st || SKIP / pe_add pe_st l n1 / SKIP
| PE_AssDynamic : forall pe_st a1 a1' l,
pe_aexp pe_st a1 = a1' ->
(forall n, a1' <> ANum n) ->
(l ::= a1) / pe_st || (l ::= a1') / pe_remove pe_st l / SKIP
| PE_Seq : forall pe_st pe_st' pe_st'' c1 c2 c1' c2' c'',
c1 / pe_st || c1' / pe_st' / SKIP ->
c2 / pe_st' || c2' / pe_st'' / c'' ->
(c1 ;; c2) / pe_st || (c1' ;; c2') / pe_st'' / c''
| PE_IfTrue : forall pe_st pe_st' b1 c1 c2 c1' c'',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c1' / pe_st' / c''
| PE_IfFalse : forall pe_st pe_st' b1 c1 c2 c2' c'',
pe_bexp pe_st b1 = BFalse ->
c2 / pe_st || c2' / pe_st' / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c2' / pe_st' / c''
| PE_If : forall pe_st pe_st1 pe_st2 b1 c1 c2 c1' c2' c'',
pe_bexp pe_st b1 <> BTrue ->
pe_bexp pe_st b1 <> BFalse ->
c1 / pe_st || c1' / pe_st1 / c'' ->
c2 / pe_st || c2' / pe_st2 / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st
|| (IFB pe_bexp pe_st b1
THEN c1' ;; assign pe_st1 (pe_compare pe_st1 pe_st2)
ELSE c2' ;; assign pe_st2 (pe_compare pe_st1 pe_st2) FI)
/ pe_removes pe_st1 (pe_compare pe_st1 pe_st2)
/ c''
| PE_WhileEnd : forall pe_st b1 c1,
pe_bexp pe_st b1 = BFalse ->
(WHILE b1 DO c1 END) / pe_st || SKIP / pe_st / SKIP
| PE_WhileLoop : forall pe_st pe_st' pe_st'' b1 c1 c1' c2' c2'',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st' || c2' / pe_st'' / c2'' ->
pe_compare pe_st pe_st'' <> [] ->
(WHILE b1 DO c1 END) / pe_st || (c1';;c2') / pe_st'' / c2''
| PE_While : forall pe_st pe_st' pe_st'' b1 c1 c1' c2' c2'',
pe_bexp pe_st b1 <> BFalse ->
pe_bexp pe_st b1 <> BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st' || c2' / pe_st'' / c2'' ->
pe_compare pe_st pe_st'' <> [] ->
(c2'' = SKIP \/ c2'' = WHILE b1 DO c1 END) ->
(WHILE b1 DO c1 END) / pe_st
|| (IFB pe_bexp pe_st b1
THEN c1';; c2';; assign pe_st'' (pe_compare pe_st pe_st'')
ELSE assign pe_st (pe_compare pe_st pe_st'') FI)
/ pe_removes pe_st (pe_compare pe_st pe_st'')
/ c2''
| PE_WhileFixedEnd : forall pe_st b1 c1,
pe_bexp pe_st b1 <> BFalse ->
(WHILE b1 DO c1 END) / pe_st || SKIP / pe_st / (WHILE b1 DO c1 END)
| PE_WhileFixedLoop : forall pe_st pe_st' pe_st'' b1 c1 c1' c2',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st'
|| c2' / pe_st'' / (WHILE b1 DO c1 END) ->
pe_compare pe_st pe_st'' = [] ->
(WHILE b1 DO c1 END) / pe_st
|| (WHILE BTrue DO SKIP END) / pe_st / SKIP
(* Because we have an infinite loop, we should actually
start to throw away the rest of the program:
(WHILE b1 DO c1 END) / pe_st
|| SKIP / pe_st / (WHILE BTrue DO SKIP END) *)
| PE_WhileFixed : forall pe_st pe_st' pe_st'' b1 c1 c1' c2',
pe_bexp pe_st b1 <> BFalse ->
pe_bexp pe_st b1 <> BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st'
|| c2' / pe_st'' / (WHILE b1 DO c1 END) ->
pe_compare pe_st pe_st'' = [] ->
(WHILE b1 DO c1 END) / pe_st
|| (WHILE pe_bexp pe_st b1 DO c1';; c2' END) / pe_st / SKIP
where "c1 '/' st '||' c1' '/' st' '/' c''" := (pe_com c1 st c1' st' c'').
Tactic Notation "pe_com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "PE_Skip"
| Case_aux c "PE_AssStatic" | Case_aux c "PE_AssDynamic"
| Case_aux c "PE_Seq"
| Case_aux c "PE_IfTrue" | Case_aux c "PE_IfFalse" | Case_aux c "PE_If"
| Case_aux c "PE_WhileEnd" | Case_aux c "PE_WhileLoop"
| Case_aux c "PE_While" | Case_aux c "PE_WhileFixedEnd"
| Case_aux c "PE_WhileFixedLoop" | Case_aux c "PE_WhileFixed" ].
Hint Constructors pe_com.
(** ** Examples *)
Ltac step i :=
(eapply i; intuition eauto; try solve by inversion);
repeat (try eapply PE_Seq;
try (eapply PE_AssStatic; simpl; reflexivity);
try (eapply PE_AssDynamic;
[ simpl; reflexivity
| intuition eauto; solve by inversion ])).
Definition square_loop: com :=
WHILE BLe (ANum 1) (AId X) DO
Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1)
END.
Example pe_loop_example1:
square_loop / []
|| (WHILE BLe (ANum 1) (AId X) DO
(Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1));; SKIP
END) / [] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
step PE_WhileFixed. step PE_WhileFixedEnd. reflexivity.
reflexivity. reflexivity. Qed.
Example pe_loop_example2:
(X ::= ANum 3;; square_loop) / []
|| (SKIP;;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
SKIP) / [(X,0)] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_WhileLoop.
step PE_WhileLoop.
step PE_WhileLoop.
step PE_WhileEnd.
inversion H. inversion H. inversion H.
reflexivity. reflexivity. Qed.
Example pe_loop_example3:
(Z ::= ANum 3;; subtract_slowly) / []
|| (SKIP;;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
WHILE BNot (BEq (AId X) (ANum 0)) DO
(SKIP;; X ::= AMinus (AId X) (ANum 1));; SKIP
END;;
SKIP;; Z ::= ANum 0
ELSE SKIP;; Z ::= ANum 1 FI;; SKIP
ELSE SKIP;; Z ::= ANum 2 FI;; SKIP
ELSE SKIP;; Z ::= ANum 3 FI) / [] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_While.
step PE_While.
step PE_While.
step PE_WhileFixed.
step PE_WhileFixedEnd.
reflexivity. inversion H. inversion H. inversion H.
reflexivity. reflexivity. Qed.
Example pe_loop_example4:
(X ::= ANum 0;;
WHILE BLe (AId X) (ANum 2) DO
X ::= AMinus (ANum 1) (AId X)
END) / [] || (SKIP;; WHILE BTrue DO SKIP END) / [(X,0)] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_WhileFixedLoop.
step PE_WhileLoop.
step PE_WhileFixedEnd.
inversion H. reflexivity. reflexivity. reflexivity. Qed.
(** ** Correctness *)
(** Because this partial evaluator can unroll a loop n-fold where n is
a (finite) integer greater than one, in order to show it correct
we need to perform induction not structurally on dynamic
evaluation but on the number of times dynamic evaluation enters a
loop body. *)
Reserved Notation "c1 '/' st '||' st' '#' n"
(at level 40, st at level 39, st' at level 39).
Inductive ceval_count : com -> state -> state -> nat -> Prop :=
| E'Skip : forall st,
SKIP / st || st # 0
| E'Ass : forall st a1 n l,
aeval st a1 = n ->
(l ::= a1) / st || (update st l n) # 0
| E'Seq : forall c1 c2 st st' st'' n1 n2,
c1 / st || st' # n1 ->
c2 / st' || st'' # n2 ->
(c1 ;; c2) / st || st'' # (n1 + n2)
| E'IfTrue : forall st st' b1 c1 c2 n,
beval st b1 = true ->
c1 / st || st' # n ->
(IFB b1 THEN c1 ELSE c2 FI) / st || st' # n
| E'IfFalse : forall st st' b1 c1 c2 n,
beval st b1 = false ->
c2 / st || st' # n ->
(IFB b1 THEN c1 ELSE c2 FI) / st || st' # n
| E'WhileEnd : forall b1 st c1,
beval st b1 = false ->
(WHILE b1 DO c1 END) / st || st # 0
| E'WhileLoop : forall st st' st'' b1 c1 n1 n2,
beval st b1 = true ->
c1 / st || st' # n1 ->
(WHILE b1 DO c1 END) / st' || st'' # n2 ->
(WHILE b1 DO c1 END) / st || st'' # S (n1 + n2)
where "c1 '/' st '||' st' # n" := (ceval_count c1 st st' n).
Tactic Notation "ceval_count_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E'Skip" | Case_aux c "E'Ass" | Case_aux c "E'Seq"
| Case_aux c "E'IfTrue" | Case_aux c "E'IfFalse"
| Case_aux c "E'WhileEnd" | Case_aux c "E'WhileLoop" ].
Hint Constructors ceval_count.
Theorem ceval_count_complete: forall c st st',
c / st || st' -> exists n, c / st || st' # n.
Proof. intros c st st' Heval.
induction Heval;
try inversion IHHeval1;
try inversion IHHeval2;
try inversion IHHeval;
eauto. Qed.
Theorem ceval_count_sound: forall c st st' n,
c / st || st' # n -> c / st || st'.
Proof. intros c st st' n Heval. induction Heval; eauto. Qed.
Theorem pe_compare_nil_lookup: forall pe_st1 pe_st2,
pe_compare pe_st1 pe_st2 = [] ->
forall V, pe_lookup pe_st1 V = pe_lookup pe_st2 V.
Proof. intros pe_st1 pe_st2 H V.
apply (pe_compare_correct pe_st1 pe_st2 V).
rewrite H. intro. inversion H0. Qed.
Theorem pe_compare_nil_override: forall pe_st1 pe_st2,
pe_compare pe_st1 pe_st2 = [] ->
forall st, pe_override st pe_st1 = pe_override st pe_st2.
Proof. intros pe_st1 pe_st2 H st.
apply functional_extensionality. intros V.
rewrite !pe_override_correct.
apply pe_compare_nil_lookup with (V:=V) in H.
rewrite H. reflexivity. Qed.
Reserved Notation "c' '/' pe_st' '/' c'' '/' st '||' st'' '#' n"
(at level 40, pe_st' at level 39, c'' at level 39,
st at level 39, st'' at level 39).
Inductive pe_ceval_count (c':com) (pe_st':pe_state) (c'':com)
(st:state) (st'':state) (n:nat) : Prop :=
| pe_ceval_count_intro : forall st' n',
c' / st || st' ->
c'' / pe_override st' pe_st' || st'' # n' ->
n' <= n ->
c' / pe_st' / c'' / st || st'' # n
where "c' '/' pe_st' '/' c'' '/' st '||' st'' '#' n" :=
(pe_ceval_count c' pe_st' c'' st st'' n).
Hint Constructors pe_ceval_count.
Lemma pe_ceval_count_le: forall c' pe_st' c'' st st'' n n',
n' <= n ->
c' / pe_st' / c'' / st || st'' # n' ->
c' / pe_st' / c'' / st || st'' # n.
Proof. intros c' pe_st' c'' st st'' n n' Hle H. inversion H.
econstructor; try eassumption. omega. Qed.
Theorem pe_com_complete:
forall c pe_st pe_st' c' c'', c / pe_st || c' / pe_st' / c'' ->
forall st st'' n,
(c / pe_override st pe_st || st'' # n) ->
(c' / pe_st' / c'' / st || st'' # n).
Proof. intros c pe_st pe_st' c' c'' Hpe.
pe_com_cases (induction Hpe) Case; intros st st'' n Heval;
try (inversion Heval; subst;
try (rewrite -> pe_bexp_correct, -> H in *; solve by inversion);
[]);
eauto.
Case "PE_AssStatic". econstructor. econstructor.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_add.
rewrite -> H. apply E'Skip. auto.
Case "PE_AssDynamic". econstructor. econstructor. reflexivity.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_remove.
apply E'Skip. auto.
Case "PE_Seq".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor; eauto. omega.
Case "PE_If". inversion Heval; subst.
SCase "E'IfTrue". edestruct IHHpe1. eassumption.
econstructor. apply E_IfTrue. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite <- assign_removes. eassumption. eassumption.
SCase "E_IfFalse". edestruct IHHpe2. eassumption.
econstructor. apply E_IfFalse. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite -> pe_compare_override.
rewrite <- assign_removes. eassumption. eassumption.
Case "PE_WhileLoop".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor; eauto. omega.
Case "PE_While". inversion Heval; subst.
SCase "E_WhileEnd". econstructor. apply E_IfFalse.
rewrite <- pe_bexp_correct. assumption.
apply eval_assign.
rewrite <- assign_removes. inversion H2; subst; auto.
auto.
SCase "E_WhileLoop".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor. apply E_IfTrue.
rewrite <- pe_bexp_correct. assumption.
repeat eapply E_Seq; eauto. apply eval_assign.
rewrite -> pe_compare_override, <- assign_removes. eassumption.
omega.
Case "PE_WhileFixedLoop". apply ex_falso_quodlibet.
generalize dependent (S (n1 + n2)). intros n.
clear - Case H H0 IHHpe1 IHHpe2. generalize dependent st.
induction n using lt_wf_ind; intros st Heval. inversion Heval; subst.
SCase "E'WhileEnd". rewrite pe_bexp_correct, H in H7. inversion H7.
SCase "E'WhileLoop".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
rewrite <- (pe_compare_nil_override _ _ H0) in H7.
apply H1 in H7; [| omega]. inversion H7.
Case "PE_WhileFixed". generalize dependent st.
induction n using lt_wf_ind; intros st Heval. inversion Heval; subst.
SCase "E'WhileEnd". rewrite pe_bexp_correct in H8. eauto.
SCase "E'WhileLoop". rewrite pe_bexp_correct in H5.
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
rewrite <- (pe_compare_nil_override _ _ H1) in H8.
apply H2 in H8; [| omega]. inversion H8.
econstructor; [ eapply E_WhileLoop; eauto | eassumption | omega].
Qed.
Theorem pe_com_sound:
forall c pe_st pe_st' c' c'', c / pe_st || c' / pe_st' / c'' ->
forall st st'' n,
(c' / pe_st' / c'' / st || st'' # n) ->
(c / pe_override st pe_st || st'').
Proof. intros c pe_st pe_st' c' c'' Hpe.
pe_com_cases (induction Hpe) Case;
intros st st'' n [st' n' Heval Heval' Hle];
try (inversion Heval; []; subst);
try (inversion Heval'; []; subst); eauto.
Case "PE_AssStatic". rewrite <- pe_override_update_add. apply E_Ass.
rewrite -> pe_aexp_correct. rewrite -> H. reflexivity.
Case "PE_AssDynamic". rewrite <- pe_override_update_remove. apply E_Ass.
rewrite <- pe_aexp_correct. reflexivity.
Case "PE_Seq". eapply E_Seq; eauto.
Case "PE_IfTrue". apply E_IfTrue.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe. eauto.
Case "PE_IfFalse". apply E_IfFalse.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe. eauto.
Case "PE_If". inversion Heval; subst; inversion H7; subst; clear H7.
SCase "E_IfTrue".
eapply ceval_deterministic in H8; [| apply eval_assign]. subst.
rewrite <- assign_removes in Heval'.
apply E_IfTrue. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe1. eauto.
SCase "E_IfFalse".
eapply ceval_deterministic in H8; [| apply eval_assign]. subst.
rewrite -> pe_compare_override in Heval'.
rewrite <- assign_removes in Heval'.
apply E_IfFalse. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe2. eauto.
Case "PE_WhileEnd". apply E_WhileEnd.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
Case "PE_WhileLoop". eapply E_WhileLoop.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe1. eauto. eapply IHHpe2. eauto.
Case "PE_While". inversion Heval; subst.
SCase "E_IfTrue".
inversion H9. subst. clear H9.
inversion H10. subst. clear H10.
eapply ceval_deterministic in H11; [| apply eval_assign]. subst.
rewrite -> pe_compare_override in Heval'.
rewrite <- assign_removes in Heval'.
eapply E_WhileLoop. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe1. eauto.
eapply IHHpe2. eauto.
SCase "E_IfFalse". apply ceval_count_sound in Heval'.
eapply ceval_deterministic in H9; [| apply eval_assign]. subst.
rewrite <- assign_removes in Heval'.
inversion H2; subst.
SSCase "c2'' = SKIP". inversion Heval'. subst. apply E_WhileEnd.
rewrite -> pe_bexp_correct. assumption.
SSCase "c2'' = WHILE b1 DO c1 END". assumption.
Case "PE_WhileFixedEnd". eapply ceval_count_sound. apply Heval'.
Case "PE_WhileFixedLoop".
apply loop_never_stops in Heval. inversion Heval.
Case "PE_WhileFixed".
clear - Case H1 IHHpe1 IHHpe2 Heval.
remember (WHILE pe_bexp pe_st b1 DO c1';; c2' END) as c'.
ceval_cases (induction Heval) SCase;
inversion Heqc'; subst; clear Heqc'.
SCase "E_WhileEnd". apply E_WhileEnd.
rewrite pe_bexp_correct. assumption.
SCase "E_WhileLoop".
assert (IHHeval2' := IHHeval2 (refl_equal _)).
apply ceval_count_complete in IHHeval2'. inversion IHHeval2'.
clear IHHeval1 IHHeval2 IHHeval2'.
inversion Heval1. subst.
eapply E_WhileLoop. rewrite pe_bexp_correct. assumption. eauto.
eapply IHHpe2. econstructor. eassumption.
rewrite <- (pe_compare_nil_override _ _ H1). eassumption. apply le_n.
Qed.
Corollary pe_com_correct:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' / SKIP ->
forall st st'',
(c / pe_override st pe_st || st'') <->
(exists st', c' / st || st' /\ pe_override st' pe_st' = st'').
Proof. intros c pe_st pe_st' c' H st st''. split.
Case "->". intros Heval.
apply ceval_count_complete in Heval. inversion Heval as [n Heval'].
apply pe_com_complete with (st:=st) (st'':=st'') (n:=n) in H.
inversion H as [? ? ? Hskip ?]. inversion Hskip. subst. eauto.
assumption.
Case "<-". intros [st' [Heval Heq]]. subst st''.
eapply pe_com_sound in H. apply H.
econstructor. apply Heval. apply E'Skip. apply le_n.
Qed.
End Loop.
(* ####################################################### *)
(** * Partial Evaluation of Flowchart Programs *)
(** Instead of partially evaluating [WHILE] loops directly, the
standard approach to partially evaluating imperative programs is
to convert them into _flowcharts_. In other words, it turns out
that adding labels and jumps to our language makes it much easier
to partially evaluate. The result of partially evaluating a
flowchart is a residual flowchart. If we are lucky, the jumps in
the residual flowchart can be converted back to [WHILE] loops, but
that is not possible in general; we do not pursue it here. *)
(** ** Basic blocks *)
(** A flowchart is made of _basic blocks_, which we represent with the
inductive type [block]. A basic block is a sequence of
assignments (the constructor [Assign]), concluding with a
conditional jump (the constructor [If]) or an unconditional jump
(the constructor [Goto]). The destinations of the jumps are
specified by _labels_, which can be of any type. Therefore, we
parameterize the [block] type by the type of labels. *)
Inductive block (Label:Type) : Type :=
| Goto : Label -> block Label
| If : bexp -> Label -> Label -> block Label
| Assign : id -> aexp -> block Label -> block Label.
Tactic Notation "block_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "Goto" | Case_aux c "If" | Case_aux c "Assign" ].
Arguments Goto {Label} _.
Arguments If {Label} _ _ _.
Arguments Assign {Label} _ _ _.
(** We use the "even or odd" program, expressed above in Imp, as our
running example. Converting this program into a flowchart turns
out to require 4 labels, so we define the following type. *)
Inductive parity_label : Type :=
| entry : parity_label
| loop : parity_label
| body : parity_label
| done : parity_label.
(** The following [block] is the basic block found at the [body] label
of the example program. *)
Definition parity_body : block parity_label :=
Assign Y (AMinus (AId Y) (ANum 1))
(Assign X (AMinus (ANum 1) (AId X))
(Goto loop)).
(** To evaluate a basic block, given an initial state, is to compute
the final state and the label to jump to next. Because basic
blocks do not _contain_ loops or other control structures,
evaluation of basic blocks is a total function -- we don't need to
worry about non-termination. *)
Fixpoint keval {L:Type} (st:state) (k : block L) : state * L :=
match k with
| Goto l => (st, l)
| If b l1 l2 => (st, if beval st b then l1 else l2)
| Assign i a k => keval (update st i (aeval st a)) k
end.
Example keval_example:
keval empty_state parity_body
= (update (update empty_state Y 0) X 1, loop).
Proof. reflexivity. Qed.
(** ** Flowchart programs *)
(** A flowchart program is simply a lookup function that maps labels
to basic blocks. Actually, some labels are _halting states_ and
do not map to any basic block. So, more precisely, a flowchart
[program] whose labels are of type [L] is a function from [L] to
[option (block L)]. *)
Definition program (L:Type) : Type := L -> option (block L).
Definition parity : program parity_label := fun l =>
match l with
| entry => Some (Assign X (ANum 0) (Goto loop))
| loop => Some (If (BLe (ANum 1) (AId Y)) body done)
| body => Some parity_body
| done => None (* halt *)
end.
(** Unlike a basic block, a program may not terminate, so we model the
evaluation of programs by an inductive relation [peval] rather
than a recursive function. *)
Inductive peval {L:Type} (p : program L)
: state -> L -> state -> L -> Prop :=
| E_None: forall st l,
p l = None ->
peval p st l st l
| E_Some: forall st l k st' l' st'' l'',
p l = Some k ->
keval st k = (st', l') ->
peval p st' l' st'' l'' ->
peval p st l st'' l''.
Example parity_eval: peval parity empty_state entry empty_state done.
Proof. erewrite f_equal with (f := fun st => peval _ _ _ st _).
eapply E_Some. reflexivity. reflexivity.
eapply E_Some. reflexivity. reflexivity.
apply E_None. reflexivity.
apply functional_extensionality. intros i. rewrite update_same; auto.
Qed.
Tactic Notation "peval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_None" | Case_aux c "E_Some" ].
(** ** Partial evaluation of basic blocks and flowchart programs *)
(** Partial evaluation changes the label type in a systematic way: if
the label type used to be [L], it becomes [pe_state * L]. So the
same label in the original program may be unfolded, or blown up,
into multiple labels by being paired with different partial
states. For example, the label [loop] in the [parity] program
will become two labels: [([(X,0)], loop)] and [([(X,1)], loop)].
This change of label type is reflected in the types of [pe_block]
and [pe_program] defined presently. *)
Fixpoint pe_block {L:Type} (pe_st:pe_state) (k : block L)
: block (pe_state * L) :=
match k with
| Goto l => Goto (pe_st, l)
| If b l1 l2 =>
match pe_bexp pe_st b with
| BTrue => Goto (pe_st, l1)
| BFalse => Goto (pe_st, l2)
| b' => If b' (pe_st, l1) (pe_st, l2)
end
| Assign i a k =>
match pe_aexp pe_st a with
| ANum n => pe_block (pe_add pe_st i n) k
| a' => Assign i a' (pe_block (pe_remove pe_st i) k)
end
end.
Example pe_block_example:
pe_block [(X,0)] parity_body
= Assign Y (AMinus (AId Y) (ANum 1)) (Goto ([(X,1)], loop)).
Proof. reflexivity. Qed.
Theorem pe_block_correct: forall (L:Type) st pe_st k st' pe_st' (l':L),
keval st (pe_block pe_st k) = (st', (pe_st', l')) ->
keval (pe_override st pe_st) k = (pe_override st' pe_st', l').
Proof. intros. generalize dependent pe_st. generalize dependent st.
block_cases (induction k as [l | b l1 l2 | i a k]) Case;
intros st pe_st H.
Case "Goto". inversion H; reflexivity.
Case "If".
replace (keval st (pe_block pe_st (If b l1 l2)))
with (keval st (If (pe_bexp pe_st b) (pe_st, l1) (pe_st, l2)))
in H by (simpl; destruct (pe_bexp pe_st b); reflexivity).
simpl in *. rewrite pe_bexp_correct.
destruct (beval st (pe_bexp pe_st b)); inversion H; reflexivity.
Case "Assign".
simpl in *. rewrite pe_aexp_correct.
destruct (pe_aexp pe_st a); simpl;
try solve [rewrite pe_override_update_add; apply IHk; apply H];
solve [rewrite pe_override_update_remove; apply IHk; apply H].
Qed.
Definition pe_program {L:Type} (p : program L)
: program (pe_state * L) :=
fun pe_l => match pe_l with (pe_st, l) =>
option_map (pe_block pe_st) (p l)
end.
Inductive pe_peval {L:Type} (p : program L)
(st:state) (pe_st:pe_state) (l:L) (st'o:state) (l':L) : Prop :=
| pe_peval_intro : forall st' pe_st',
peval (pe_program p) st (pe_st, l) st' (pe_st', l') ->
pe_override st' pe_st' = st'o ->
pe_peval p st pe_st l st'o l'.
Theorem pe_program_correct:
forall (L:Type) (p : program L) st pe_st l st'o l',
peval p (pe_override st pe_st) l st'o l' <->
pe_peval p st pe_st l st'o l'.
Proof. intros.
split; [Case "->" | Case "<-"].
Case "->". intros Heval.
remember (pe_override st pe_st) as sto.
generalize dependent pe_st. generalize dependent st.
peval_cases (induction Heval as
[ sto l Hlookup | sto l k st'o l' st''o l'' Hlookup Hkeval Heval ])
SCase; intros st pe_st Heqsto; subst sto.
SCase "E_None". eapply pe_peval_intro. apply E_None.
simpl. rewrite Hlookup. reflexivity. reflexivity.
SCase "E_Some".
remember (keval st (pe_block pe_st k)) as x.
destruct x as [st' [pe_st' l'_]].
symmetry in Heqx. erewrite pe_block_correct in Hkeval by apply Heqx.
inversion Hkeval. subst st'o l'_. clear Hkeval.
edestruct IHHeval. reflexivity. subst st''o. clear IHHeval.
eapply pe_peval_intro; [| reflexivity]. eapply E_Some; eauto.
simpl. rewrite Hlookup. reflexivity.
Case "<-". intros [st' pe_st' Heval Heqst'o].
remember (pe_st, l) as pe_st_l.
remember (pe_st', l') as pe_st'_l'.
generalize dependent pe_st. generalize dependent l.
peval_cases (induction Heval as
[ st [pe_st_ l_] Hlookup
| st [pe_st_ l_] pe_k st' [pe_st'_ l'_] st'' [pe_st'' l'']
Hlookup Hkeval Heval ])
SCase; intros l pe_st Heqpe_st_l;
inversion Heqpe_st_l; inversion Heqpe_st'_l'; repeat subst.
SCase "E_None". apply E_None. simpl in Hlookup.
destruct (p l'); [ solve [ inversion Hlookup ] | reflexivity ].
SCase "E_Some".
simpl in Hlookup. remember (p l) as k.
destruct k as [k|]; inversion Hlookup; subst.
eapply E_Some; eauto. apply pe_block_correct. apply Hkeval.
Qed.
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (clk);
input clk;
tpub p1 (.clk(clk), .i(32'd1));
tpub p2 (.clk(clk), .i(32'd2));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
`ifdef verilator
$c("publicTop();");
`endif
end
if (cyc==20) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
task publicTop;
// verilator public
// We have different optimizations if only one of something, so try it out.
$write("Hello in publicTop\n");
endtask
endmodule
module tpub (
input clk,
input [31:0] i);
reg [23:0] var_long;
reg [59:0] var_quad;
reg [71:0] var_wide;
reg var_bool;
// verilator lint_off BLKANDNBLK
reg [11:0] var_flop;
// verilator lint_on BLKANDNBLK
reg [23:0] got_long /*verilator public*/;
reg [59:0] got_quad /*verilator public*/;
reg [71:0] got_wide /*verilator public*/;
reg got_bool /*verilator public*/;
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
// cyc==1 is in top level
if (cyc==2) begin
publicNoArgs;
publicSetBool(1'b1);
publicSetLong(24'habca);
publicSetQuad(60'h4444_3333_2222);
publicSetWide(72'h12_5678_9123_1245_2352);
var_flop <= 12'habe;
end
if (cyc==3) begin
if (1'b1 != publicGetSetBool(1'b0)) $stop;
if (24'habca != publicGetSetLong(24'h1234)) $stop;
if (60'h4444_3333_2222 != publicGetSetQuad(60'h123_4567_89ab)) $stop;
if (72'h12_5678_9123_1245_2352 != publicGetSetWide(72'hac_abca_aaaa_bbbb_1234)) $stop;
end
if (cyc==4) begin
publicGetBool(got_bool);
if (1'b0 != got_bool) $stop;
publicGetLong(got_long);
if (24'h1234 != got_long) $stop;
publicGetQuad(got_quad);
if (60'h123_4567_89ab != got_quad) $stop;
publicGetWide(got_wide);
if (72'hac_abca_aaaa_bbbb_1234 != got_wide) $stop;
end
//
`ifdef VERILATOR_PUBLIC_TASKS
if (cyc==11) begin
$c("publicNoArgs();");
$c("publicSetBool(true);");
$c("publicSetLong(0x11bca);");
$c("publicSetQuad(VL_ULL(0x66655554444));");
$c("publicSetFlop(0x321);");
//Unsupported: $c("WData w[3] = {0x12, 0x5678_9123, 0x1245_2352}; publicSetWide(w);");
end
if (cyc==12) begin
$c("got_bool = publicGetSetBool(true);");
$c("got_long = publicGetSetLong(0x11bca);");
$c("got_quad = publicGetSetQuad(VL_ULL(0xaaaabbbbcccc));");
end
if (cyc==13) begin
$c("{ bool gb; publicGetBool(gb); got_bool=gb; }");
if (1'b1 != got_bool) $stop;
$c("publicGetLong(got_long);");
if (24'h11bca != got_long) $stop;
$c("{ vluint64_t qq; publicGetQuad(qq); got_quad=qq; }");
if (60'haaaa_bbbb_cccc != got_quad) $stop;
$c("{ WData gw[3]; publicGetWide(gw); VL_ASSIGN_W(72,got_wide,gw); }");
if (72'hac_abca_aaaa_bbbb_1234 != got_wide) $stop;
//Below doesn't work, because we're calling it inside the loop that sets var_flop
// if (12'h321 != var_flop) $stop;
end
if (cyc==14) begin
if ($c32("publicInstNum()") != i) $stop;
end
`endif
end
end
task publicEmpty;
// verilator public
begin end
endtask
task publicNoArgs;
// verilator public
$write("Hello in publicNoArgs\n");
endtask
task publicSetBool;
// verilator public
input in_bool;
var_bool = in_bool;
endtask
task publicSetLong;
// verilator public
input [23:0] in_long;
reg [23:0] not_long;
begin
not_long = ~in_long; // Test that we can have local variables
var_long = ~not_long;
end
endtask
task publicSetQuad;
// verilator public
input [59:0] in_quad;
var_quad = in_quad;
endtask
task publicSetFlop;
// verilator public
input [11:0] in_flop;
var_flop = in_flop;
endtask
task publicSetWide;
// verilator public
input [71:0] in_wide;
var_wide = in_wide;
endtask
task publicGetBool;
// verilator public
output out_bool;
out_bool = var_bool;
endtask
task publicGetLong;
// verilator public
output [23:0] out_long;
out_long = var_long;
endtask
task publicGetQuad;
// verilator public
output [59:0] out_quad;
out_quad = var_quad;
endtask
task publicGetWide;
// verilator public
output [71:0] out_wide;
out_wide = var_wide;
endtask
function publicGetSetBool;
// verilator public
input in_bool;
begin
publicGetSetBool = var_bool;
var_bool = in_bool;
end
endfunction
function [23:0] publicGetSetLong;
// verilator public
input [23:0] in_long;
begin
publicGetSetLong = var_long;
var_long = in_long;
end
endfunction
function [59:0] publicGetSetQuad;
// verilator public
input [59:0] in_quad;
begin
publicGetSetQuad = var_quad;
var_quad = in_quad;
end
endfunction
function [71:0] publicGetSetWide;
// Can't be public, as no wide return types in C++
input [71:0] in_wide;
begin
publicGetSetWide = var_wide;
var_wide = in_wide;
end
endfunction
`ifdef VERILATOR_PUBLIC_TASKS
function [31:0] publicInstNum;
// verilator public
publicInstNum = i;
endfunction
`endif
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (clk);
input clk;
tpub p1 (.clk(clk), .i(32'd1));
tpub p2 (.clk(clk), .i(32'd2));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
`ifdef verilator
$c("publicTop();");
`endif
end
if (cyc==20) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
task publicTop;
// verilator public
// We have different optimizations if only one of something, so try it out.
$write("Hello in publicTop\n");
endtask
endmodule
module tpub (
input clk,
input [31:0] i);
reg [23:0] var_long;
reg [59:0] var_quad;
reg [71:0] var_wide;
reg var_bool;
// verilator lint_off BLKANDNBLK
reg [11:0] var_flop;
// verilator lint_on BLKANDNBLK
reg [23:0] got_long /*verilator public*/;
reg [59:0] got_quad /*verilator public*/;
reg [71:0] got_wide /*verilator public*/;
reg got_bool /*verilator public*/;
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
// cyc==1 is in top level
if (cyc==2) begin
publicNoArgs;
publicSetBool(1'b1);
publicSetLong(24'habca);
publicSetQuad(60'h4444_3333_2222);
publicSetWide(72'h12_5678_9123_1245_2352);
var_flop <= 12'habe;
end
if (cyc==3) begin
if (1'b1 != publicGetSetBool(1'b0)) $stop;
if (24'habca != publicGetSetLong(24'h1234)) $stop;
if (60'h4444_3333_2222 != publicGetSetQuad(60'h123_4567_89ab)) $stop;
if (72'h12_5678_9123_1245_2352 != publicGetSetWide(72'hac_abca_aaaa_bbbb_1234)) $stop;
end
if (cyc==4) begin
publicGetBool(got_bool);
if (1'b0 != got_bool) $stop;
publicGetLong(got_long);
if (24'h1234 != got_long) $stop;
publicGetQuad(got_quad);
if (60'h123_4567_89ab != got_quad) $stop;
publicGetWide(got_wide);
if (72'hac_abca_aaaa_bbbb_1234 != got_wide) $stop;
end
//
`ifdef VERILATOR_PUBLIC_TASKS
if (cyc==11) begin
$c("publicNoArgs();");
$c("publicSetBool(true);");
$c("publicSetLong(0x11bca);");
$c("publicSetQuad(VL_ULL(0x66655554444));");
$c("publicSetFlop(0x321);");
//Unsupported: $c("WData w[3] = {0x12, 0x5678_9123, 0x1245_2352}; publicSetWide(w);");
end
if (cyc==12) begin
$c("got_bool = publicGetSetBool(true);");
$c("got_long = publicGetSetLong(0x11bca);");
$c("got_quad = publicGetSetQuad(VL_ULL(0xaaaabbbbcccc));");
end
if (cyc==13) begin
$c("{ bool gb; publicGetBool(gb); got_bool=gb; }");
if (1'b1 != got_bool) $stop;
$c("publicGetLong(got_long);");
if (24'h11bca != got_long) $stop;
$c("{ vluint64_t qq; publicGetQuad(qq); got_quad=qq; }");
if (60'haaaa_bbbb_cccc != got_quad) $stop;
$c("{ WData gw[3]; publicGetWide(gw); VL_ASSIGN_W(72,got_wide,gw); }");
if (72'hac_abca_aaaa_bbbb_1234 != got_wide) $stop;
//Below doesn't work, because we're calling it inside the loop that sets var_flop
// if (12'h321 != var_flop) $stop;
end
if (cyc==14) begin
if ($c32("publicInstNum()") != i) $stop;
end
`endif
end
end
task publicEmpty;
// verilator public
begin end
endtask
task publicNoArgs;
// verilator public
$write("Hello in publicNoArgs\n");
endtask
task publicSetBool;
// verilator public
input in_bool;
var_bool = in_bool;
endtask
task publicSetLong;
// verilator public
input [23:0] in_long;
reg [23:0] not_long;
begin
not_long = ~in_long; // Test that we can have local variables
var_long = ~not_long;
end
endtask
task publicSetQuad;
// verilator public
input [59:0] in_quad;
var_quad = in_quad;
endtask
task publicSetFlop;
// verilator public
input [11:0] in_flop;
var_flop = in_flop;
endtask
task publicSetWide;
// verilator public
input [71:0] in_wide;
var_wide = in_wide;
endtask
task publicGetBool;
// verilator public
output out_bool;
out_bool = var_bool;
endtask
task publicGetLong;
// verilator public
output [23:0] out_long;
out_long = var_long;
endtask
task publicGetQuad;
// verilator public
output [59:0] out_quad;
out_quad = var_quad;
endtask
task publicGetWide;
// verilator public
output [71:0] out_wide;
out_wide = var_wide;
endtask
function publicGetSetBool;
// verilator public
input in_bool;
begin
publicGetSetBool = var_bool;
var_bool = in_bool;
end
endfunction
function [23:0] publicGetSetLong;
// verilator public
input [23:0] in_long;
begin
publicGetSetLong = var_long;
var_long = in_long;
end
endfunction
function [59:0] publicGetSetQuad;
// verilator public
input [59:0] in_quad;
begin
publicGetSetQuad = var_quad;
var_quad = in_quad;
end
endfunction
function [71:0] publicGetSetWide;
// Can't be public, as no wide return types in C++
input [71:0] in_wide;
begin
publicGetSetWide = var_wide;
var_wide = in_wide;
end
endfunction
`ifdef VERILATOR_PUBLIC_TASKS
function [31:0] publicInstNum;
// verilator public
publicInstNum = i;
endfunction
`endif
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2010 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
wire monclk = ~clk;
int in;
int fr_a;
int fr_b;
int fr_chk;
sub sub (.*);
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d in=%x fr_a=%x b=%x fr_chk=%x\n",$time, cyc, in, fr_a, fr_b, fr_chk);
`endif
cyc <= cyc + 1;
in <= {in[30:0], in[31]^in[2]^in[0]};
if (cyc==0) begin
// Setup
in <= 32'hd70a4497;
end
else if (cyc<3) begin
end
else if (cyc<10) begin
if (fr_chk != fr_a) $stop;
if (fr_chk != fr_b) $stop;
end
else if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
always @(posedge t.monclk) begin
mon_eval();
end
endmodule
import "DPI-C" context function void mon_scope_name (input string formatted /*verilator sformat*/ );
import "DPI-C" context function void mon_register_b(string name, int isOut);
import "DPI-C" context function void mon_register_done();
import "DPI-C" context function void mon_eval();
module sub (/*AUTOARG*/
// Outputs
fr_a, fr_b, fr_chk,
// Inputs
in
);
`systemc_imp_header
void mon_class_name(const char* namep);
void mon_register_a(const char* namep, void* sigp, bool isOut);
`verilog
input int in /*verilator public_flat_rd*/;
output int fr_a /*verilator public_flat_rw @(posedge t.monclk)*/;
output int fr_b /*verilator public_flat_rw @(posedge t.monclk)*/;
output int fr_chk;
always @* fr_chk = in + 1;
initial begin
// Test the naming
$c("mon_class_name(name());");
mon_scope_name("%m");
// Scheme A - pass pointer directly
$c("mon_register_a(\"in\",&",in,",false);");
$c("mon_register_a(\"fr_a\",&",fr_a,",true);");
// Scheme B - use VPIish callbacks to see what signals exist
mon_register_b("in", 0);
mon_register_b("fr_b", 1);
mon_register_done();
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2010 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
wire monclk = ~clk;
int in;
int fr_a;
int fr_b;
int fr_chk;
sub sub (.*);
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d in=%x fr_a=%x b=%x fr_chk=%x\n",$time, cyc, in, fr_a, fr_b, fr_chk);
`endif
cyc <= cyc + 1;
in <= {in[30:0], in[31]^in[2]^in[0]};
if (cyc==0) begin
// Setup
in <= 32'hd70a4497;
end
else if (cyc<3) begin
end
else if (cyc<10) begin
if (fr_chk != fr_a) $stop;
if (fr_chk != fr_b) $stop;
end
else if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
always @(posedge t.monclk) begin
mon_eval();
end
endmodule
import "DPI-C" context function void mon_scope_name (input string formatted /*verilator sformat*/ );
import "DPI-C" context function void mon_register_b(string name, int isOut);
import "DPI-C" context function void mon_register_done();
import "DPI-C" context function void mon_eval();
module sub (/*AUTOARG*/
// Outputs
fr_a, fr_b, fr_chk,
// Inputs
in
);
`systemc_imp_header
void mon_class_name(const char* namep);
void mon_register_a(const char* namep, void* sigp, bool isOut);
`verilog
input int in /*verilator public_flat_rd*/;
output int fr_a /*verilator public_flat_rw @(posedge t.monclk)*/;
output int fr_b /*verilator public_flat_rw @(posedge t.monclk)*/;
output int fr_chk;
always @* fr_chk = in + 1;
initial begin
// Test the naming
$c("mon_class_name(name());");
mon_scope_name("%m");
// Scheme A - pass pointer directly
$c("mon_register_a(\"in\",&",in,",false);");
$c("mon_register_a(\"fr_a\",&",fr_a,",true);");
// Scheme B - use VPIish callbacks to see what signals exist
mon_register_b("in", 0);
mon_register_b("fr_b", 1);
mon_register_done();
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2010 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
wire monclk = ~clk;
int in;
int fr_a;
int fr_b;
int fr_chk;
sub sub (.*);
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d in=%x fr_a=%x b=%x fr_chk=%x\n",$time, cyc, in, fr_a, fr_b, fr_chk);
`endif
cyc <= cyc + 1;
in <= {in[30:0], in[31]^in[2]^in[0]};
if (cyc==0) begin
// Setup
in <= 32'hd70a4497;
end
else if (cyc<3) begin
end
else if (cyc<10) begin
if (fr_chk != fr_a) $stop;
if (fr_chk != fr_b) $stop;
end
else if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
always @(posedge t.monclk) begin
mon_eval();
end
endmodule
import "DPI-C" context function void mon_scope_name (input string formatted /*verilator sformat*/ );
import "DPI-C" context function void mon_register_b(string name, int isOut);
import "DPI-C" context function void mon_register_done();
import "DPI-C" context function void mon_eval();
module sub (/*AUTOARG*/
// Outputs
fr_a, fr_b, fr_chk,
// Inputs
in
);
`systemc_imp_header
void mon_class_name(const char* namep);
void mon_register_a(const char* namep, void* sigp, bool isOut);
`verilog
input int in /*verilator public_flat_rd*/;
output int fr_a /*verilator public_flat_rw @(posedge t.monclk)*/;
output int fr_b /*verilator public_flat_rw @(posedge t.monclk)*/;
output int fr_chk;
always @* fr_chk = in + 1;
initial begin
// Test the naming
$c("mon_class_name(name());");
mon_scope_name("%m");
// Scheme A - pass pointer directly
$c("mon_register_a(\"in\",&",in,",false);");
$c("mon_register_a(\"fr_a\",&",fr_a,",true);");
// Scheme B - use VPIish callbacks to see what signals exist
mon_register_b("in", 0);
mon_register_b("fr_b", 1);
mon_register_done();
end
endmodule
|
/* pbkdfengine.v
*
* Copyright (c) 2013 kramble
* Parts copyright (c) 2011 [email protected]
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`define ICARUS // Comment this out when using the altera virtual_wire interface in ltcminer.v
`timescale 1ns/1ps
module pbkdfengine
(hash_clk, pbkdf_clk, data1, data2, data3, target, nonce_msb, nonce_out, golden_nonce_out, golden_nonce_match, loadnonce,
salsa_din, salsa_dout, salsa_busy, salsa_result, salsa_reset, salsa_start, salsa_shift, hash_out);
input hash_clk; // Just drives shift register
input pbkdf_clk;
input [255:0] data1;
input [255:0] data2;
input [127:0] data3;
input [31:0] target;
input [3:0] nonce_msb;
output reg [31:0] nonce_out;
output reg [31:0] hash_out; // Hash value for nonce_out (ztex port)
output [31:0] golden_nonce_out;
output golden_nonce_match; // Strobe valid one cycle on a match (needed for serial comms)
input loadnonce; // Strobe loads nonce (used for serial interface)
parameter SBITS = 8; // Shift data path width
input [SBITS-1:0] salsa_dout;
output [SBITS-1:0] salsa_din;
input salsa_busy, salsa_result; // NB hash_clk domain
output salsa_reset;
output salsa_start;
output reg salsa_shift = 1'b0; // NB hash_clk domain
reg [4:0]resetcycles = 4'd0;
reg reset = 1'b0;
assign salsa_reset = reset; // Propagate reset to salsaengine
`ifdef WANTCYCLICRESET
reg [23:0]cycresetcount = 24'd0;
`endif
always @ (posedge pbkdf_clk)
begin
// Hard code a 31 cycle reset (NB assumes THREADS=16 in salsaengine, else we need more)
// NB hash_clk is faster than pbkdf_clk so the salsaengine will actually be initialised well before
// this period ends, but keep to 15 for now as simulation uses equal pbkdf and salsa clock speeds.
resetcycles <= resetcycles + 1'd1;
if (resetcycles == 0)
reset <= 1'b1;
if (resetcycles == 31)
begin
reset <= 1'b0;
resetcycles <= 31;
end
`ifdef WANTCYCLICRESET
// Cyclical reset every 2_500_000 clocks to ensure salsa pipeline does not drift out of sync
// This may be unneccessary if we reset every loadnonce
// Actually it seems to do more harm than good, so disabled
cycresetcount <= cycresetcount + 1'd1;
if (cycresetcount == 2_500_000) // 10 per second at 25MHz (adjust as neccessary)
begin
cycresetcount <= 24'd0;
resetcycles <= 5'd0;
end
`endif
// Reset on loadnonce (the hash results will be junk anyway since data changes, so no loss of shares)
if (loadnonce)
resetcycles <= 5'd0;
end
`ifndef ICARUS
reg [31:0] nonce_previous_load = 32'hffffffff; // See note in salsa mix FSM
`endif
`ifndef NOMULTICORE
`ifdef SIM
reg [27:0] nonce_cnt = 28'h318f; // Start point for simulation (NB also define SIM in serial.v)
`else
reg [27:0] nonce_cnt = 28'd0; // Multiple cores use different prefix
`endif
wire [31:0] nonce;
assign nonce = { nonce_msb, nonce_cnt };
`else
reg [31:0] nonce = 32'd0; // NB Initially loaded from data3[127:96], see salsa mix FSM
`endif
reg [31:0] nonce_sr = 32'd0; // Nonce is shifted to salsaengine for storage/retrieval (hash_clk domain)
reg [31:0] golden_nonce = 32'd0;
assign golden_nonce_out = golden_nonce;
reg golden_nonce_match = 1'b0;
reg [2:0] nonce_wait = 3'd0;
reg [255:0] rx_state;
reg [511:0] rx_input;
wire [255:0] tx_hash;
reg [255:0] khash = 256'd0; // Key hash (NB scrypt.c calls this ihash)
reg [255:0] ihash = 256'd0; // IPAD hash
reg [255:0] ohash = 256'd0; // OPAD hash
`ifdef SIM
reg [255:0] final_hash = 256'd0; // Just for DEBUG, only need top 32 bits in live code.
`endif
reg [2:0] blockcnt = 3'd0; // Takes values 1..5 for block iteration
reg [1023:0] Xbuf = 1024'd0; // Shared input/output buffer and shift register (hash_clk domain)
reg [5:0] cnt = 6'd0;
wire feedback;
assign feedback = (cnt != 6'b0);
assign salsa_din = Xbuf[1023:1024-SBITS];
wire [1023:0] MixOutRewire; // Need to do endian conversion (see the generate below)
// MixOut is little-endian word format to match scrypt.c so convert back to big-endian
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin : Xrewire
wire [31:0] mix;
assign mix = Xbuf[`IDX(i)]; // NB MixOut now shares Xbuf since shifted in/out
assign MixOutRewire[`IDX(i)] = { mix[7:0], mix[15:8], mix[23:16], mix[31:24] };
end
endgenerate
// Interface control. This should be OK provided the threads remain evenly spaced (hence we reset on loadnonce)
reg SMixInRdy_state = 1'b0; // SMix input ready flag (set in SHA256, reset in SMIX)
reg SMixOutRdy_state = 1'b0; // SMix output ready flag (set in SMIX, reset in SHA256)
wire SMixInRdy;
wire SMixOutRdy;
reg Set_SMixInRdy = 1'b0;
reg Clr_SMixOutRdy = 1'b0;
wire Clr_SMixInRdy;
wire Set_SMixOutRdy;
reg [4:0]salsa_busy_d = 0; // Sync to pbkdf_clk domain
reg [4:0]salsa_result_d = 0;
always @ (posedge hash_clk)
begin
// Sync to pbkdf_clk domain
salsa_busy_d[0] <= salsa_busy;
if (salsa_busy & ~ salsa_busy_d[0])
salsa_busy_d[1] <= ~ salsa_busy_d[1]; // Toggle on busy going high
salsa_result_d[0] <= salsa_result;
if (salsa_result & ~ salsa_result_d[0])
salsa_result_d[1] <= ~ salsa_result_d[1]; // Toggle on result going high
end
always @ (posedge pbkdf_clk)
begin
salsa_busy_d[4:2] <= salsa_busy_d[3:1];
salsa_result_d[4:2] <= salsa_result_d[3:1];
if (Set_SMixInRdy)
SMixInRdy_state <= 1'b1;
if (Clr_SMixInRdy)
SMixInRdy_state <= 1'b0; // Clr overrides set
if (Set_SMixOutRdy)
SMixOutRdy_state <= 1'b1;
if (Clr_SMixOutRdy)
SMixOutRdy_state <= 1'b0; // Clr overrides set
// CARE there is a race with Set_SMixInRdy, Clr_SMixOutRdy which are set in the FSM
// Need to assert reset for several cycles to ensure consistency (acutally use 15 since salsaengine needs more)
if (reset)
begin // Reset takes priority
SMixInRdy_state <= 1'b0;
SMixOutRdy_state <= 1'b0;
end
end
assign Clr_SMixInRdy = SMixInRdy_state & (salsa_busy_d[3] ^ salsa_busy_d[4]); // Clear on transition to busy
assign Set_SMixOutRdy = ~SMixOutRdy_state & (salsa_result_d[3] ^ salsa_result_d[4]); // Set on transition to result
// Achieves identical timing to original version, but probably overkill
assign SMixInRdy = Clr_SMixInRdy ? 1'b0 : Set_SMixInRdy ? 1'b1 : SMixInRdy_state;
assign SMixOutRdy = Clr_SMixOutRdy ? 1'b0 : Set_SMixOutRdy ? 1'b1 : SMixOutRdy_state;
assign salsa_start = SMixInRdy;
// Clock crossing flags for shift register control (span pbkdf_clk, hash_clk domains)
reg [3:0]Xbuf_load_request = 1'b0;
reg [3:0]shift_request = 1'b0;
reg [3:0]shift_acknowledge = 1'b0;
// Controller FSM for PBKDF2_SHA256_80_128 (multiple hashes using the sha256_transform)
// Based on scrypt.c from cgminer (Colin Percival, ArtForz)
parameter S_IDLE=0,
S_H1= 1, S_H2= 2, S_H3= 3, S_H4= 4, S_H5= 5, S_H6= 6, // Initial hash of block header (khash)
S_I1= 7, S_I2= 8, S_I3= 9, S_I4=10, S_I5=11, S_I6=12, // IPAD hash (ihash)
S_O1=13, S_O2=14, S_O3=15, // OPAD hash (ohash)
S_B1=16, S_B2=17, S_B3=18, S_B4=19, S_B5=20, S_B6=21, // Iterate blocks
S_NONCE=22, S_SHIFT_IN=41, S_SHIFT_OUT=42, // Direction relative to salsa unit
// Final PBKDF2_SHA256_80_128_32 (reuses S_H1 to S_H6 for khash, alternatively could piplenine value)
S_R1=23, S_R2=24, S_R3=25, S_R4=26, S_R5=27, S_R6=28, // Final PBKDF2_SHA256_80_128_32
S_R7=29, S_R8=30, S_R9=31, S_R10=32, S_R11=33, S_R12=34,
S_R13=35, S_R14=36, S_R15=37, S_R16=38, S_R17=39, S_R18=40;
reg [5:0] state = S_IDLE;
reg mode = 0; // 0=PBKDF2_SHA256_80_128, 1=PBKDF2_SHA256_80_128_32
reg start_output = 0;
always @ (posedge pbkdf_clk)
begin
Set_SMixInRdy <= 1'b0; // Ugly hack, these are overriden below
Clr_SMixOutRdy <= 1'b0;
golden_nonce_match <= 1'b0; // Default to reset
shift_acknowledge[3:1] <= shift_acknowledge[2:0]; // Clock crossing
`ifdef ICARUS
if (loadnonce) // Separate clock domains means comparison is unsafe
`else
if (loadnonce || (nonce_previous_load != data3[127:96]))
`endif
begin
`ifdef NOMULTICORE
nonce <= data3[127:96]; // Supports loading of initial nonce for test purposes (potentially
// overriden by the increment below, but this occurs very rarely)
// This also gives a consistent start point when we send the first work
// packet (but ONLY the first one since its always zero) when using live data
// as we initialise nonce_previous_load to ffffffff
`else
nonce_cnt <= data3[123:96]; // The 4 msb of nonce are hardwired in MULTICORE mode, so test nonce
// needs to be <= 0fffffff and will only match in the 0 core
`endif
`ifndef ICARUS
nonce_previous_load <= data3[127:96];
`endif
end
if (reset == 1'b1)
begin
state <= S_IDLE;
start_output <= 1'b0;
end
else
begin
case (state)
S_IDLE: begin
if (SMixOutRdy & ~start_output)
begin
shift_request[0] <= ~shift_request[0]; // Request shifter to start
state <= S_SHIFT_OUT;
end
else
begin
if (start_output || // Process output
!SMixInRdy) // Process input unless already done
begin
start_output <= 1'b0;
mode <= 1'b0;
// Both cases use same initial calculaton of khash (its not worth trying to reuse previous khash
// for the second case as we're not constrained by SHA256 timing)
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { data2, data1 }; // Block header is passwd (used as key)
blockcnt <= 3'd1;
cnt <= 6'd0;
if (SMixOutRdy) // Give preference to output
mode <= 1'b1;
state <= S_H1;
end
end
end
// Hash the block header (result is khash)
S_H1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_H2;
end
end
S_H2: begin // Sync hash
state <= S_H3;
end
S_H3: begin // Sync hash
rx_state <= tx_hash;
// Hash last 16 bytes of header including nonce and padded to 64 bytes with 1, zeros and length
// NB this sequence is used for both input and final PBKDF2_SHA256, hence switch nonce on mode
rx_input <= { 384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000,
mode ? nonce_sr : nonce, data3[95:0] };
state <= S_H4;
end
S_H4: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_H5;
end
end
S_H5: begin // Sync hash
state <= S_H6;
end
S_H6: begin // Sync hash
khash <= tx_hash; // Save for OPAD hash
// Setup for IPAD hash
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h3636363636363636363636363636363636363636363636363636363636363636 ,
tx_hash ^ 256'h3636363636363636363636363636363636363636363636363636363636363636 };
cnt <= 6'd0;
if (mode)
state <= S_R1;
else
state <= S_I1;
end
// IPAD hash
S_I1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_I2;
end
end
S_I2: begin // Sync hash
state <= S_I3;
end
S_I3: begin // Sync hash
rx_state <= tx_hash;
rx_input <= { data2, data1 }; // Passwd (used as message)
state <= S_I4;
end
S_I4: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_I5;
end
end
S_I5: begin // Sync hash
state <= S_I6;
end
S_I6: begin // Sync hash
ihash <= tx_hash; // Save result
// Setup for OPAD hash
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c ,
khash ^ 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c };
cnt <= 6'd0;
state <= S_O1;
end
// OPAD hash
S_O1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_O2;
end
end
S_O2: begin // Sync hash
state <= S_O3;
end
S_O3: begin // Sync hash
ohash <= tx_hash; // Save result
// Setup for block iteration
rx_state <= ihash;
// TODO hardwire top 29 bits of blockcnt as zero
rx_input <= { 352'h000004a000000000000000000000000000000000000000000000000000000000000000000000000080000000,
29'd0, blockcnt, nonce, data3[95:0] }; // blockcnt is 3 bits, top 29 are hardcoded 0
blockcnt <= blockcnt + 1'd1; // Increment for next time
cnt <= 6'd0;
state <= S_B1;
end
// Block iteration (4 cycles)
S_B1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_B2;
end
end
S_B2: begin // Sync hash
state <= S_B3;
end
S_B3: begin // Sync hash
rx_state <= ohash;
rx_input <= { 256'h0000030000000000000000000000000000000000000000000000000080000000, tx_hash };
state <= S_B4;
end
S_B4: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_B5;
end
end
S_B5: begin // Sync hash
state <= S_B6;
end
S_B6: begin
khash <= tx_hash; // Save temporarily (for Xbuf)
Xbuf_load_request[0] <= ~Xbuf_load_request[0]; // NB also loads nonce_sr
if (blockcnt == 3'd5)
begin
nonce_wait <= 3'd7;
state <= S_NONCE;
end
else begin
// Setup for next block
rx_state <= ihash;
rx_input <= { 352'h000004a000000000000000000000000000000000000000000000000000000000000000000000000080000000,
29'd0, blockcnt, nonce, data3[95:0] }; // blockcnt is 3 bits, top 29 are hardcoded 0
blockcnt <= blockcnt + 1'd1; // Increment for next time
cnt <= 6'd0;
state <= S_B1;
end
end
S_NONCE: begin
// Need to delay a few clocks for Xbuf_load_request to complete
nonce_wait <= nonce_wait - 1'd1;
if (nonce_wait == 0)
begin
`ifndef NOMULTICORE
nonce_cnt <= nonce_cnt + 1'd1;
`else
nonce <= nonce + 1'd1;
`endif
shift_request[0] <= ~shift_request[0];
state <= S_SHIFT_IN;
end
end
S_SHIFT_IN: begin // Shifting from PBKDF2_SHA256 to salsa
if (shift_acknowledge[3] != shift_acknowledge[2])
begin
Set_SMixInRdy <= 1'd1; // Flag salsa to start
state <= S_IDLE;
end
end
S_SHIFT_OUT: begin // Shifting from salsa to PBKDF2_SHA256
if (shift_acknowledge[3] != shift_acknowledge[2])
begin
start_output <= 1'd1; // Flag self to start
state <= S_IDLE;
end
end
// Final PBKDF2_SHA256_80_128_32 NB Entered from S_H6 via mode flag
// Similar to S_I0 but using MixOut as salt and finalblk padding
S_R1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R2;
end
end
S_R2: begin // Sync hash
state <= S_R3;
end
S_R3: begin // Sync hash
rx_state <= tx_hash;
rx_input <= MixOutRewire[511:0]; // Salt (first block)
state <= S_R4;
end
S_R4: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R5;
end
end
S_R5: begin // Sync hash
state <= S_R6;
end
S_R6: begin // Sync hash
rx_state <= tx_hash;
rx_input <= MixOutRewire[1023:512]; // Salt (second block)
state <= S_R7;
end
S_R7: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R8;
end
end
S_R8: begin // Sync hash
state <= S_R9;
end
S_R9: begin // Sync hash
rx_state <= tx_hash;
// Final padding
rx_input <= 512'h00000620000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000001;
state <= S_R10;
end
S_R10: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R11;
end
end
S_R11: begin // Sync hash
state <= S_R12;
end
S_R12: begin // Sync hash
ihash <= tx_hash; // Save (reuse ihash)
// Setup for OPAD hash
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c ,
khash ^ 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c };
cnt <= 6'd0;
state <= S_R13;
end
S_R13: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R14;
end
end
S_R14: begin // Sync hash
state <= S_R15;
end
S_R15: begin // Sync hash
rx_state <= tx_hash;
rx_input <= { 256'h0000030000000000000000000000000000000000000000000000000080000000, ihash };
state <= S_R16;
end
S_R16: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R17;
end
end
S_R17: begin // Sync hash
state <= S_R18;
end
S_R18: begin // Sync hash
// Check for golden nonce in tx_hash
`ifdef SIM
final_hash <= tx_hash; // For debug
`endif
nonce_out <= nonce_sr; // Ztex port
hash_out <= tx_hash[255:224];
// Could optimise target calc ...
if ( { tx_hash[231:224], tx_hash[239:232], tx_hash[247:240], tx_hash[255:248] } < target)
begin
golden_nonce <= nonce_sr;
golden_nonce_match <= 1'b1; // Set flag (for one cycle only, see default at top)
end
state <= S_IDLE;
mode <= 1'b0;
// SMixOutRdy <= 1'b0; // Original version
Clr_SMixOutRdy <= 1'b1; // Ugly hack
end
endcase
end
end
// Shift register control - NB hash_clk domain
reg [10:0]shift_count = 11'd0; // hash_clk domain
always @ (posedge hash_clk)
begin
if (reset)
begin
salsa_shift <= 1'b0;
shift_count <= 11'd0;
end
// Clock crossing logic
Xbuf_load_request[3:1] <= Xbuf_load_request[2:0];
if (Xbuf_load_request[3] != Xbuf_load_request[2])
begin
// Shift output into X buffer from MSB->LSB
Xbuf[255:0] <= Xbuf[511:256];
Xbuf[511:256] <= Xbuf[767:512];
Xbuf[767:512] <= Xbuf[1023:768];
Xbuf[1023:768] <= khash;
nonce_sr <= nonce; // Loaded several times, but of no consequence
end
shift_request[3:1] <= shift_request[2:0];
if (shift_request[3] != shift_request[2])
begin
salsa_shift <= 1'b1;
end
if (salsa_shift)
begin
shift_count <= shift_count + 1'b1;
Xbuf <= { Xbuf[1023-SBITS:0], nonce_sr[31:32-SBITS] };
nonce_sr <= { nonce_sr[31-SBITS:0], salsa_dout };
end
if (shift_count == (1024+32)/SBITS-1)
begin
shift_acknowledge[0] = ~shift_acknowledge[0];
shift_count <= 0;
salsa_shift <= 0;
end
end
// Using LOOP=64 to simplify timing (needs slightly modified version of original sha256_transform.v)
// since pipelining is inappropriate for ltc (we need to rehash same data several times in succession)
sha256_transform # (.LOOP(64)) sha256_blk (
.clk(pbkdf_clk),
.feedback(feedback),
.cnt(cnt),
.rx_state(rx_state),
.rx_input(rx_input),
.tx_hash(tx_hash)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [3:0] l_stop = crc[3:0];
wire [3:0] l_break = crc[7:4];
wire [3:0] l_continue = crc[11:8];
/*AUTOWIRE*/
wire [15:0] out0 = Test0(l_stop, l_break, l_continue);
wire [15:0] out1 = Test1(l_stop, l_break, l_continue);
wire [15:0] out2 = Test2(l_stop, l_break, l_continue);
wire [15:0] out3 = Test3(l_stop, l_break, l_continue);
// Aggregate outputs into a single result vector
wire [63:0] result = {out3,out2,out1,out0};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
if (out0!==out1) $stop;
if (out0!==out2) $stop;
if (out0!==out3) $stop;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h293e9f9798e97da0
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
function [15:0] Test0;
input [3:0] loop_stop;
input [3:0] loop_break;
input [3:0] loop_continue;
integer i;
reg broken;
Test0 = 0;
broken = 0;
begin
for (i=1; i<20; i=i+1) begin
if (!broken) begin
Test0 = Test0 + 1;
if (i[3:0] != loop_continue) begin // continue
if (i[3:0] == loop_break) begin
broken = 1'b1;
end
if (!broken) begin
Test0 = Test0 + i[15:0];
end
end
end
end
end
endfunction
function [15:0] Test1;
input [3:0] loop_stop;
input [3:0] loop_break;
input [3:0] loop_continue;
integer i;
Test1 = 0;
begin : outer_block
for (i=1; i<20; i=i+1) begin : inner_block
Test1 = Test1 + 1;
// continue, IE jump to end-of-inner_block. Must be inside inner_block.
if (i[3:0] == loop_continue) disable inner_block;
// break, IE jump to end-of-outer_block. Must be inside outer_block.
if (i[3:0] == loop_break) disable outer_block;
Test1 = Test1 + i[15:0];
end : inner_block
end : outer_block
endfunction
function [15:0] Test2;
input [3:0] loop_stop;
input [3:0] loop_break;
input [3:0] loop_continue;
integer i;
Test2 = 0;
begin
for (i=1; i<20; i=i+1) begin
Test2 = Test2 + 1;
if (i[3:0] == loop_continue) continue;
if (i[3:0] == loop_break) break;
Test2 = Test2 + i[15:0];
end
end
endfunction
function [15:0] Test3;
input [3:0] loop_stop;
input [3:0] loop_break;
input [3:0] loop_continue;
integer i;
Test3 = 0;
begin
for (i=1; i<20; i=i+1) begin
Test3 = Test3 + 1;
if (i[3:0] == loop_continue) continue;
// return, IE jump to end-of-function optionally setting return value
if (i[3:0] == loop_break) return Test3;
Test3 = Test3 + i[15:0];
end
end
endfunction
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
// verilator lint_off WIDTH
// verilator lint_off VARHIDDEN
module t (
clk
);
input clk;
integer cyc=0;
reg [63:0] crc; initial crc = 64'h1;
chk chk (.clk (clk),
.rst_l (1'b1),
.expr (|crc)
);
always @ (posedge clk) begin
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==0) begin
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module chk (input clk, input rst_l, input expr);
integer errors; initial errors = 0;
task printerr;
input [8*64:1] msg;
begin
errors = errors + 1;
$write("%%Error: %0s\n", msg);
$stop;
end
endtask
always @(posedge clk) begin
if (rst_l) begin
if (expr == 1'b0) begin
printerr("expr not asserted");
end
end
end
wire noxs = ((expr ^ expr) == 1'b0);
reg hasx;
always @ (noxs) begin
if (noxs) begin
hasx = 1'b0;
end
else begin
hasx = 1'b1;
end
end
always @(posedge clk) begin
if (rst_l) begin
if (hasx) begin
printerr("expr has unknowns");
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
// verilator lint_off WIDTH
// verilator lint_off VARHIDDEN
module t (
clk
);
input clk;
integer cyc=0;
reg [63:0] crc; initial crc = 64'h1;
chk chk (.clk (clk),
.rst_l (1'b1),
.expr (|crc)
);
always @ (posedge clk) begin
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==0) begin
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module chk (input clk, input rst_l, input expr);
integer errors; initial errors = 0;
task printerr;
input [8*64:1] msg;
begin
errors = errors + 1;
$write("%%Error: %0s\n", msg);
$stop;
end
endtask
always @(posedge clk) begin
if (rst_l) begin
if (expr == 1'b0) begin
printerr("expr not asserted");
end
end
end
wire noxs = ((expr ^ expr) == 1'b0);
reg hasx;
always @ (noxs) begin
if (noxs) begin
hasx = 1'b0;
end
else begin
hasx = 1'b1;
end
end
always @(posedge clk) begin
if (rst_l) begin
if (hasx) begin
printerr("expr has unknowns");
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
// verilator lint_off WIDTH
// verilator lint_off VARHIDDEN
module t (
clk
);
input clk;
integer cyc=0;
reg [63:0] crc; initial crc = 64'h1;
chk chk (.clk (clk),
.rst_l (1'b1),
.expr (|crc)
);
always @ (posedge clk) begin
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==0) begin
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module chk (input clk, input rst_l, input expr);
integer errors; initial errors = 0;
task printerr;
input [8*64:1] msg;
begin
errors = errors + 1;
$write("%%Error: %0s\n", msg);
$stop;
end
endtask
always @(posedge clk) begin
if (rst_l) begin
if (expr == 1'b0) begin
printerr("expr not asserted");
end
end
end
wire noxs = ((expr ^ expr) == 1'b0);
reg hasx;
always @ (noxs) begin
if (noxs) begin
hasx = 1'b0;
end
else begin
hasx = 1'b1;
end
end
always @(posedge clk) begin
if (rst_l) begin
if (hasx) begin
printerr("expr has unknowns");
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [71:0] muxed; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.muxed (muxed[71:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {muxed[63:0]};
wire [5:0] width_check = cyc[5:0] + 1;
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h20050a66e7b253d1
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
muxed,
// Inputs
clk, in
);
input clk;
input [31:0] in;
output [71:0] muxed;
wire [71:0] a = {in[7:0],~in[31:0],in[31:0]};
wire [71:0] b = {~in[7:0],in[31:0],~in[31:0]};
/*AUTOWIRE*/
Muxer muxer (
.sa (0),
.sb (in[0]),
/*AUTOINST*/
// Outputs
.muxed (muxed[71:0]),
// Inputs
.a (a[71:0]),
.b (b[71:0]));
endmodule
module Muxer (/*AUTOARG*/
// Outputs
muxed,
// Inputs
sa, sb, a, b
);
input sa;
input sb;
output wire [71:0] muxed;
input [71:0] a;
input [71:0] b;
// Constification wasn't sizing with inlining and gave
// unsized error on below
// v
assign muxed = (({72{sa}} & a)
| ({72{sb}} & b));
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
wire [1:0] clkvec = crc[1:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [1:0] count; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.count (count[1:0]),
// Inputs
.clkvec (clkvec[1:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {62'h0, count};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'hfe8bac0bb1a0e53b
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
`ifdef T_TEST1
module Test
(
input wire [1:0] clkvec,
// verilator lint_off MULTIDRIVEN
output reg [1:0] count
// verilator lint_on MULTIDRIVEN
);
genvar igen;
generate
for (igen=0; igen<2; igen=igen+1) begin : code_gen
initial count[igen] = 1'b0;
always @ (posedge clkvec[igen])
count[igen] <= count[igen] + 1;
end
endgenerate
always @ (count) begin
$write("hi\n");
end
endmodule
`endif
`ifdef T_TEST2
module Test
(
input wire [1:0] clkvec,
// verilator lint_off MULTIDRIVEN
output reg [1:0] count
// verilator lint_on MULTIDRIVEN
);
genvar igen;
generate
for (igen=0; igen<2; igen=igen+1) begin : code_gen
wire clk_tmp = clkvec[igen];
// Unsupported: Count is multidriven, though if we did better analysis it wouldn't
// need to be.
initial count[igen] = 1'b0;
always @ (posedge clk_tmp)
count[igen] <= count[igen] + 1;
end
endgenerate
endmodule
`endif
`ifdef T_TEST3
module Test
(
input wire [1:0] clkvec,
output wire [1:0] count
);
genvar igen;
generate
for (igen=0; igen<2; igen=igen+1) begin : code_gen
wire clk_tmp = clkvec[igen];
reg tmp_count = 1'b0;
always @ (posedge clk_tmp) begin
tmp_count <= tmp_count + 1;
end
assign count[igen] = tmp_count;
end
endgenerate
endmodule
`endif
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
wire [1:0] clkvec = crc[1:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [1:0] count; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.count (count[1:0]),
// Inputs
.clkvec (clkvec[1:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {62'h0, count};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'hfe8bac0bb1a0e53b
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
`ifdef T_TEST1
module Test
(
input wire [1:0] clkvec,
// verilator lint_off MULTIDRIVEN
output reg [1:0] count
// verilator lint_on MULTIDRIVEN
);
genvar igen;
generate
for (igen=0; igen<2; igen=igen+1) begin : code_gen
initial count[igen] = 1'b0;
always @ (posedge clkvec[igen])
count[igen] <= count[igen] + 1;
end
endgenerate
always @ (count) begin
$write("hi\n");
end
endmodule
`endif
`ifdef T_TEST2
module Test
(
input wire [1:0] clkvec,
// verilator lint_off MULTIDRIVEN
output reg [1:0] count
// verilator lint_on MULTIDRIVEN
);
genvar igen;
generate
for (igen=0; igen<2; igen=igen+1) begin : code_gen
wire clk_tmp = clkvec[igen];
// Unsupported: Count is multidriven, though if we did better analysis it wouldn't
// need to be.
initial count[igen] = 1'b0;
always @ (posedge clk_tmp)
count[igen] <= count[igen] + 1;
end
endgenerate
endmodule
`endif
`ifdef T_TEST3
module Test
(
input wire [1:0] clkvec,
output wire [1:0] count
);
genvar igen;
generate
for (igen=0; igen<2; igen=igen+1) begin : code_gen
wire clk_tmp = clkvec[igen];
reg tmp_count = 1'b0;
always @ (posedge clk_tmp) begin
tmp_count <= tmp_count + 1;
end
assign count[igen] = tmp_count;
end
endgenerate
endmodule
`endif
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
/*verilator public_module*/
input clk;
// No verilator_public needed, because it's outside the "" in the $c statement
reg [7:0] cyc; initial cyc=0;
reg c_worked;
reg [8:0] c_wider;
wire one = 1'b1;
always @ (posedge clk) begin
cyc <= cyc+8'd1;
// coverage testing
if (one) begin end
if (!one) begin end
if (cyc[0]) begin end if (!cyc[0]) begin end // multiple on a line
if (cyc == 8'd1) begin
c_worked <= 0;
end
if (cyc == 8'd2) begin
`ifdef VERILATOR
$c("VL_PRINTF(\"Calling $c, calling $c...\\n\");");
$c("VL_PRINTF(\"Cyc=%d\\n\",",cyc,");");
c_worked <= $c("my_function()");
c_wider <= $c9("0x10");
`else
c_worked <= 1'b1;
c_wider <= 9'h10;
`endif
end
if (cyc == 8'd3) begin
if (c_worked !== 1'b1) $stop;
if (c_wider !== 9'h10) $stop;
$finish;
end
end
`ifdef verilator
`systemc_header
#define DID_INT_HEADER 1
`systemc_interface
#ifndef DID_INT_HEADER
#error "`systemc_header didn't work"
#endif
bool m_did_ctor;
vluint32_t my_function() {
if (!m_did_ctor) vl_fatal(__FILE__,__LINE__,__FILE__,"`systemc_ctor didn't work");
return 1;
}
`systemc_imp_header
#define DID_IMP_HEADER 1
`systemc_implementation
#ifndef DID_IMP_HEADER
#error "`systemc_imp_header didn't work"
#endif
`systemc_ctor
m_did_ctor = 1;
`systemc_dtor
printf("In systemc_dtor\n");
printf("*-* All Finished *-*\n");
`verilog
// Test verilator comment after a endif
`endif // verilator
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
/*verilator public_module*/
input clk;
// No verilator_public needed, because it's outside the "" in the $c statement
reg [7:0] cyc; initial cyc=0;
reg c_worked;
reg [8:0] c_wider;
wire one = 1'b1;
always @ (posedge clk) begin
cyc <= cyc+8'd1;
// coverage testing
if (one) begin end
if (!one) begin end
if (cyc[0]) begin end if (!cyc[0]) begin end // multiple on a line
if (cyc == 8'd1) begin
c_worked <= 0;
end
if (cyc == 8'd2) begin
`ifdef VERILATOR
$c("VL_PRINTF(\"Calling $c, calling $c...\\n\");");
$c("VL_PRINTF(\"Cyc=%d\\n\",",cyc,");");
c_worked <= $c("my_function()");
c_wider <= $c9("0x10");
`else
c_worked <= 1'b1;
c_wider <= 9'h10;
`endif
end
if (cyc == 8'd3) begin
if (c_worked !== 1'b1) $stop;
if (c_wider !== 9'h10) $stop;
$finish;
end
end
`ifdef verilator
`systemc_header
#define DID_INT_HEADER 1
`systemc_interface
#ifndef DID_INT_HEADER
#error "`systemc_header didn't work"
#endif
bool m_did_ctor;
vluint32_t my_function() {
if (!m_did_ctor) vl_fatal(__FILE__,__LINE__,__FILE__,"`systemc_ctor didn't work");
return 1;
}
`systemc_imp_header
#define DID_IMP_HEADER 1
`systemc_implementation
#ifndef DID_IMP_HEADER
#error "`systemc_imp_header didn't work"
#endif
`systemc_ctor
m_did_ctor = 1;
`systemc_dtor
printf("In systemc_dtor\n");
printf("*-* All Finished *-*\n");
`verilog
// Test verilator comment after a endif
`endif // verilator
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [7:0] sel = crc[7:0];
wire [255+3:0] in = {crc[2:0],crc,crc,crc,crc};
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] out; // From test of Test.v
// End of automatics
/* Test AUTO_TEMPLATE (
.i\([0-9]+\) (in[\1 +:4]),
); */
Test test (/*AUTOINST*/
// Outputs
.out (out[3:0]),
// Inputs
.sel (sel[7:0]),
.i0 (in[0 +:4]), // Templated
.i1 (in[1 +:4]), // Templated
.i2 (in[2 +:4]), // Templated
.i3 (in[3 +:4]), // Templated
.i4 (in[4 +:4]), // Templated
.i5 (in[5 +:4]), // Templated
.i6 (in[6 +:4]), // Templated
.i7 (in[7 +:4]), // Templated
.i8 (in[8 +:4]), // Templated
.i9 (in[9 +:4]), // Templated
.i10 (in[10 +:4]), // Templated
.i11 (in[11 +:4]), // Templated
.i12 (in[12 +:4]), // Templated
.i13 (in[13 +:4]), // Templated
.i14 (in[14 +:4]), // Templated
.i15 (in[15 +:4]), // Templated
.i16 (in[16 +:4]), // Templated
.i17 (in[17 +:4]), // Templated
.i18 (in[18 +:4]), // Templated
.i19 (in[19 +:4]), // Templated
.i20 (in[20 +:4]), // Templated
.i21 (in[21 +:4]), // Templated
.i22 (in[22 +:4]), // Templated
.i23 (in[23 +:4]), // Templated
.i24 (in[24 +:4]), // Templated
.i25 (in[25 +:4]), // Templated
.i26 (in[26 +:4]), // Templated
.i27 (in[27 +:4]), // Templated
.i28 (in[28 +:4]), // Templated
.i29 (in[29 +:4]), // Templated
.i30 (in[30 +:4]), // Templated
.i31 (in[31 +:4]), // Templated
.i32 (in[32 +:4]), // Templated
.i33 (in[33 +:4]), // Templated
.i34 (in[34 +:4]), // Templated
.i35 (in[35 +:4]), // Templated
.i36 (in[36 +:4]), // Templated
.i37 (in[37 +:4]), // Templated
.i38 (in[38 +:4]), // Templated
.i39 (in[39 +:4]), // Templated
.i40 (in[40 +:4]), // Templated
.i41 (in[41 +:4]), // Templated
.i42 (in[42 +:4]), // Templated
.i43 (in[43 +:4]), // Templated
.i44 (in[44 +:4]), // Templated
.i45 (in[45 +:4]), // Templated
.i46 (in[46 +:4]), // Templated
.i47 (in[47 +:4]), // Templated
.i48 (in[48 +:4]), // Templated
.i49 (in[49 +:4]), // Templated
.i50 (in[50 +:4]), // Templated
.i51 (in[51 +:4]), // Templated
.i52 (in[52 +:4]), // Templated
.i53 (in[53 +:4]), // Templated
.i54 (in[54 +:4]), // Templated
.i55 (in[55 +:4]), // Templated
.i56 (in[56 +:4]), // Templated
.i57 (in[57 +:4]), // Templated
.i58 (in[58 +:4]), // Templated
.i59 (in[59 +:4]), // Templated
.i60 (in[60 +:4]), // Templated
.i61 (in[61 +:4]), // Templated
.i62 (in[62 +:4]), // Templated
.i63 (in[63 +:4]), // Templated
.i64 (in[64 +:4]), // Templated
.i65 (in[65 +:4]), // Templated
.i66 (in[66 +:4]), // Templated
.i67 (in[67 +:4]), // Templated
.i68 (in[68 +:4]), // Templated
.i69 (in[69 +:4]), // Templated
.i70 (in[70 +:4]), // Templated
.i71 (in[71 +:4]), // Templated
.i72 (in[72 +:4]), // Templated
.i73 (in[73 +:4]), // Templated
.i74 (in[74 +:4]), // Templated
.i75 (in[75 +:4]), // Templated
.i76 (in[76 +:4]), // Templated
.i77 (in[77 +:4]), // Templated
.i78 (in[78 +:4]), // Templated
.i79 (in[79 +:4]), // Templated
.i80 (in[80 +:4]), // Templated
.i81 (in[81 +:4]), // Templated
.i82 (in[82 +:4]), // Templated
.i83 (in[83 +:4]), // Templated
.i84 (in[84 +:4]), // Templated
.i85 (in[85 +:4]), // Templated
.i86 (in[86 +:4]), // Templated
.i87 (in[87 +:4]), // Templated
.i88 (in[88 +:4]), // Templated
.i89 (in[89 +:4]), // Templated
.i90 (in[90 +:4]), // Templated
.i91 (in[91 +:4]), // Templated
.i92 (in[92 +:4]), // Templated
.i93 (in[93 +:4]), // Templated
.i94 (in[94 +:4]), // Templated
.i95 (in[95 +:4]), // Templated
.i96 (in[96 +:4]), // Templated
.i97 (in[97 +:4]), // Templated
.i98 (in[98 +:4]), // Templated
.i99 (in[99 +:4]), // Templated
.i100 (in[100 +:4]), // Templated
.i101 (in[101 +:4]), // Templated
.i102 (in[102 +:4]), // Templated
.i103 (in[103 +:4]), // Templated
.i104 (in[104 +:4]), // Templated
.i105 (in[105 +:4]), // Templated
.i106 (in[106 +:4]), // Templated
.i107 (in[107 +:4]), // Templated
.i108 (in[108 +:4]), // Templated
.i109 (in[109 +:4]), // Templated
.i110 (in[110 +:4]), // Templated
.i111 (in[111 +:4]), // Templated
.i112 (in[112 +:4]), // Templated
.i113 (in[113 +:4]), // Templated
.i114 (in[114 +:4]), // Templated
.i115 (in[115 +:4]), // Templated
.i116 (in[116 +:4]), // Templated
.i117 (in[117 +:4]), // Templated
.i118 (in[118 +:4]), // Templated
.i119 (in[119 +:4]), // Templated
.i120 (in[120 +:4]), // Templated
.i121 (in[121 +:4]), // Templated
.i122 (in[122 +:4]), // Templated
.i123 (in[123 +:4]), // Templated
.i124 (in[124 +:4]), // Templated
.i125 (in[125 +:4]), // Templated
.i126 (in[126 +:4]), // Templated
.i127 (in[127 +:4]), // Templated
.i128 (in[128 +:4]), // Templated
.i129 (in[129 +:4]), // Templated
.i130 (in[130 +:4]), // Templated
.i131 (in[131 +:4]), // Templated
.i132 (in[132 +:4]), // Templated
.i133 (in[133 +:4]), // Templated
.i134 (in[134 +:4]), // Templated
.i135 (in[135 +:4]), // Templated
.i136 (in[136 +:4]), // Templated
.i137 (in[137 +:4]), // Templated
.i138 (in[138 +:4]), // Templated
.i139 (in[139 +:4]), // Templated
.i140 (in[140 +:4]), // Templated
.i141 (in[141 +:4]), // Templated
.i142 (in[142 +:4]), // Templated
.i143 (in[143 +:4]), // Templated
.i144 (in[144 +:4]), // Templated
.i145 (in[145 +:4]), // Templated
.i146 (in[146 +:4]), // Templated
.i147 (in[147 +:4]), // Templated
.i148 (in[148 +:4]), // Templated
.i149 (in[149 +:4]), // Templated
.i150 (in[150 +:4]), // Templated
.i151 (in[151 +:4]), // Templated
.i152 (in[152 +:4]), // Templated
.i153 (in[153 +:4]), // Templated
.i154 (in[154 +:4]), // Templated
.i155 (in[155 +:4]), // Templated
.i156 (in[156 +:4]), // Templated
.i157 (in[157 +:4]), // Templated
.i158 (in[158 +:4]), // Templated
.i159 (in[159 +:4]), // Templated
.i160 (in[160 +:4]), // Templated
.i161 (in[161 +:4]), // Templated
.i162 (in[162 +:4]), // Templated
.i163 (in[163 +:4]), // Templated
.i164 (in[164 +:4]), // Templated
.i165 (in[165 +:4]), // Templated
.i166 (in[166 +:4]), // Templated
.i167 (in[167 +:4]), // Templated
.i168 (in[168 +:4]), // Templated
.i169 (in[169 +:4]), // Templated
.i170 (in[170 +:4]), // Templated
.i171 (in[171 +:4]), // Templated
.i172 (in[172 +:4]), // Templated
.i173 (in[173 +:4]), // Templated
.i174 (in[174 +:4]), // Templated
.i175 (in[175 +:4]), // Templated
.i176 (in[176 +:4]), // Templated
.i177 (in[177 +:4]), // Templated
.i178 (in[178 +:4]), // Templated
.i179 (in[179 +:4]), // Templated
.i180 (in[180 +:4]), // Templated
.i181 (in[181 +:4]), // Templated
.i182 (in[182 +:4]), // Templated
.i183 (in[183 +:4]), // Templated
.i184 (in[184 +:4]), // Templated
.i185 (in[185 +:4]), // Templated
.i186 (in[186 +:4]), // Templated
.i187 (in[187 +:4]), // Templated
.i188 (in[188 +:4]), // Templated
.i189 (in[189 +:4]), // Templated
.i190 (in[190 +:4]), // Templated
.i191 (in[191 +:4]), // Templated
.i192 (in[192 +:4]), // Templated
.i193 (in[193 +:4]), // Templated
.i194 (in[194 +:4]), // Templated
.i195 (in[195 +:4]), // Templated
.i196 (in[196 +:4]), // Templated
.i197 (in[197 +:4]), // Templated
.i198 (in[198 +:4]), // Templated
.i199 (in[199 +:4]), // Templated
.i200 (in[200 +:4]), // Templated
.i201 (in[201 +:4]), // Templated
.i202 (in[202 +:4]), // Templated
.i203 (in[203 +:4]), // Templated
.i204 (in[204 +:4]), // Templated
.i205 (in[205 +:4]), // Templated
.i206 (in[206 +:4]), // Templated
.i207 (in[207 +:4]), // Templated
.i208 (in[208 +:4]), // Templated
.i209 (in[209 +:4]), // Templated
.i210 (in[210 +:4]), // Templated
.i211 (in[211 +:4]), // Templated
.i212 (in[212 +:4]), // Templated
.i213 (in[213 +:4]), // Templated
.i214 (in[214 +:4]), // Templated
.i215 (in[215 +:4]), // Templated
.i216 (in[216 +:4]), // Templated
.i217 (in[217 +:4]), // Templated
.i218 (in[218 +:4]), // Templated
.i219 (in[219 +:4]), // Templated
.i220 (in[220 +:4]), // Templated
.i221 (in[221 +:4]), // Templated
.i222 (in[222 +:4]), // Templated
.i223 (in[223 +:4]), // Templated
.i224 (in[224 +:4]), // Templated
.i225 (in[225 +:4]), // Templated
.i226 (in[226 +:4]), // Templated
.i227 (in[227 +:4]), // Templated
.i228 (in[228 +:4]), // Templated
.i229 (in[229 +:4]), // Templated
.i230 (in[230 +:4]), // Templated
.i231 (in[231 +:4]), // Templated
.i232 (in[232 +:4]), // Templated
.i233 (in[233 +:4]), // Templated
.i234 (in[234 +:4]), // Templated
.i235 (in[235 +:4]), // Templated
.i236 (in[236 +:4]), // Templated
.i237 (in[237 +:4]), // Templated
.i238 (in[238 +:4]), // Templated
.i239 (in[239 +:4]), // Templated
.i240 (in[240 +:4]), // Templated
.i241 (in[241 +:4]), // Templated
.i242 (in[242 +:4]), // Templated
.i243 (in[243 +:4]), // Templated
.i244 (in[244 +:4]), // Templated
.i245 (in[245 +:4]), // Templated
.i246 (in[246 +:4]), // Templated
.i247 (in[247 +:4]), // Templated
.i248 (in[248 +:4]), // Templated
.i249 (in[249 +:4]), // Templated
.i250 (in[250 +:4]), // Templated
.i251 (in[251 +:4]), // Templated
.i252 (in[252 +:4]), // Templated
.i253 (in[253 +:4]), // Templated
.i254 (in[254 +:4]), // Templated
.i255 (in[255 +:4])); // Templated
// Aggregate outputs into a single result vector
wire [63:0] result = {60'h0, out};
// What checksum will we end up with
`define EXPECTED_SUM 64'h36f3051d15caf07a
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test
( output wire [3:0] out,
input [7:0] sel,
input [3:0] i0, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16,
i17, i18, i19, i20, i21, i22, i23, i24, i25, i26, i27, i28, i29, i30, i31, i32, i33,
i34, i35, i36, i37, i38, i39, i40, i41, i42, i43, i44, i45, i46, i47, i48, i49, i50,
i51, i52, i53, i54, i55, i56, i57, i58, i59, i60, i61, i62, i63, i64, i65, i66, i67,
i68, i69, i70, i71, i72, i73, i74, i75, i76, i77, i78, i79, i80, i81, i82, i83, i84,
i85, i86, i87, i88, i89, i90, i91, i92, i93, i94, i95, i96, i97, i98, i99, i100, i101,
i102, i103, i104, i105, i106, i107, i108, i109, i110, i111, i112, i113, i114, i115,
i116, i117, i118, i119, i120, i121, i122, i123, i124, i125, i126, i127, i128, i129,
i130, i131, i132, i133, i134, i135, i136, i137, i138, i139, i140, i141, i142, i143,
i144, i145, i146, i147, i148, i149, i150, i151, i152, i153, i154, i155, i156, i157,
i158, i159, i160, i161, i162, i163, i164, i165, i166, i167, i168, i169, i170, i171,
i172, i173, i174, i175, i176, i177, i178, i179, i180, i181, i182, i183, i184, i185,
i186, i187, i188, i189, i190, i191, i192, i193, i194, i195, i196, i197, i198, i199,
i200, i201, i202, i203, i204, i205, i206, i207, i208, i209, i210, i211, i212, i213,
i214, i215, i216, i217, i218, i219, i220, i221, i222, i223, i224, i225, i226, i227,
i228, i229, i230, i231, i232, i233, i234, i235, i236, i237, i238, i239, i240, i241,
i242, i243, i244, i245, i246, i247, i248, i249, i250, i251, i252, i253, i254, i255
);
assign out
= (sel==8'h00) ? i0 : (sel==8'h01) ? i1 : (sel==8'h02) ? i2 : (sel==8'h03) ? i3
: (sel==8'h04) ? i4 : (sel==8'h05) ? i5 : (sel==8'h06) ? i6 : (sel==8'h07) ? i7
: (sel==8'h08) ? i8 : (sel==8'h09) ? i9 : (sel==8'h0a) ? i10 : (sel==8'h0b) ? i11
: (sel==8'h0c) ? i12 : (sel==8'h0d) ? i13 : (sel==8'h0e) ? i14 : (sel==8'h0f) ? i15
: (sel==8'h10) ? i16 : (sel==8'h11) ? i17 : (sel==8'h12) ? i18 : (sel==8'h13) ? i19
: (sel==8'h14) ? i20 : (sel==8'h15) ? i21 : (sel==8'h16) ? i22 : (sel==8'h17) ? i23
: (sel==8'h18) ? i24 : (sel==8'h19) ? i25 : (sel==8'h1a) ? i26 : (sel==8'h1b) ? i27
: (sel==8'h1c) ? i28 : (sel==8'h1d) ? i29 : (sel==8'h1e) ? i30 : (sel==8'h1f) ? i31
: (sel==8'h20) ? i32 : (sel==8'h21) ? i33 : (sel==8'h22) ? i34 : (sel==8'h23) ? i35
: (sel==8'h24) ? i36 : (sel==8'h25) ? i37 : (sel==8'h26) ? i38 : (sel==8'h27) ? i39
: (sel==8'h28) ? i40 : (sel==8'h29) ? i41 : (sel==8'h2a) ? i42 : (sel==8'h2b) ? i43
: (sel==8'h2c) ? i44 : (sel==8'h2d) ? i45 : (sel==8'h2e) ? i46 : (sel==8'h2f) ? i47
: (sel==8'h30) ? i48 : (sel==8'h31) ? i49 : (sel==8'h32) ? i50 : (sel==8'h33) ? i51
: (sel==8'h34) ? i52 : (sel==8'h35) ? i53 : (sel==8'h36) ? i54 : (sel==8'h37) ? i55
: (sel==8'h38) ? i56 : (sel==8'h39) ? i57 : (sel==8'h3a) ? i58 : (sel==8'h3b) ? i59
: (sel==8'h3c) ? i60 : (sel==8'h3d) ? i61 : (sel==8'h3e) ? i62 : (sel==8'h3f) ? i63
: (sel==8'h40) ? i64 : (sel==8'h41) ? i65 : (sel==8'h42) ? i66 : (sel==8'h43) ? i67
: (sel==8'h44) ? i68 : (sel==8'h45) ? i69 : (sel==8'h46) ? i70 : (sel==8'h47) ? i71
: (sel==8'h48) ? i72 : (sel==8'h49) ? i73 : (sel==8'h4a) ? i74 : (sel==8'h4b) ? i75
: (sel==8'h4c) ? i76 : (sel==8'h4d) ? i77 : (sel==8'h4e) ? i78 : (sel==8'h4f) ? i79
: (sel==8'h50) ? i80 : (sel==8'h51) ? i81 : (sel==8'h52) ? i82 : (sel==8'h53) ? i83
: (sel==8'h54) ? i84 : (sel==8'h55) ? i85 : (sel==8'h56) ? i86 : (sel==8'h57) ? i87
: (sel==8'h58) ? i88 : (sel==8'h59) ? i89 : (sel==8'h5a) ? i90 : (sel==8'h5b) ? i91
: (sel==8'h5c) ? i92 : (sel==8'h5d) ? i93 : (sel==8'h5e) ? i94 : (sel==8'h5f) ? i95
: (sel==8'h60) ? i96 : (sel==8'h61) ? i97 : (sel==8'h62) ? i98 : (sel==8'h63) ? i99
: (sel==8'h64) ? i100 : (sel==8'h65) ? i101 : (sel==8'h66) ? i102 : (sel==8'h67) ? i103
: (sel==8'h68) ? i104 : (sel==8'h69) ? i105 : (sel==8'h6a) ? i106 : (sel==8'h6b) ? i107
: (sel==8'h6c) ? i108 : (sel==8'h6d) ? i109 : (sel==8'h6e) ? i110 : (sel==8'h6f) ? i111
: (sel==8'h70) ? i112 : (sel==8'h71) ? i113 : (sel==8'h72) ? i114 : (sel==8'h73) ? i115
: (sel==8'h74) ? i116 : (sel==8'h75) ? i117 : (sel==8'h76) ? i118 : (sel==8'h77) ? i119
: (sel==8'h78) ? i120 : (sel==8'h79) ? i121 : (sel==8'h7a) ? i122 : (sel==8'h7b) ? i123
: (sel==8'h7c) ? i124 : (sel==8'h7d) ? i125 : (sel==8'h7e) ? i126 : (sel==8'h7f) ? i127
: (sel==8'h80) ? i128 : (sel==8'h81) ? i129 : (sel==8'h82) ? i130 : (sel==8'h83) ? i131
: (sel==8'h84) ? i132 : (sel==8'h85) ? i133 : (sel==8'h86) ? i134 : (sel==8'h87) ? i135
: (sel==8'h88) ? i136 : (sel==8'h89) ? i137 : (sel==8'h8a) ? i138 : (sel==8'h8b) ? i139
: (sel==8'h8c) ? i140 : (sel==8'h8d) ? i141 : (sel==8'h8e) ? i142 : (sel==8'h8f) ? i143
: (sel==8'h90) ? i144 : (sel==8'h91) ? i145 : (sel==8'h92) ? i146 : (sel==8'h93) ? i147
: (sel==8'h94) ? i148 : (sel==8'h95) ? i149 : (sel==8'h96) ? i150 : (sel==8'h98) ? i151
: (sel==8'h99) ? i152 : (sel==8'h9a) ? i153 : (sel==8'h9b) ? i154 : (sel==8'h9c) ? i155
: (sel==8'h9d) ? i156 : (sel==8'h9e) ? i157 : (sel==8'h9f) ? i158 : (sel==8'ha0) ? i159
: (sel==8'ha1) ? i160 : (sel==8'ha2) ? i161 : (sel==8'ha3) ? i162 : (sel==8'ha4) ? i163
: (sel==8'ha5) ? i164 : (sel==8'ha6) ? i165 : (sel==8'ha7) ? i166 : (sel==8'ha8) ? i167
: (sel==8'ha9) ? i168 : (sel==8'haa) ? i169 : (sel==8'hab) ? i170 : (sel==8'hac) ? i171
: (sel==8'had) ? i172 : (sel==8'hae) ? i173 : (sel==8'haf) ? i174 : (sel==8'hb0) ? i175
: (sel==8'hb1) ? i176 : (sel==8'hb2) ? i177 : (sel==8'hb3) ? i178 : (sel==8'hb4) ? i179
: (sel==8'hb5) ? i180 : (sel==8'hb6) ? i181 : (sel==8'hb7) ? i182 : (sel==8'hb8) ? i183
: (sel==8'hb9) ? i184 : (sel==8'hba) ? i185 : (sel==8'hbb) ? i186 : (sel==8'hbc) ? i187
: (sel==8'hbd) ? i188 : (sel==8'hbe) ? i189 : (sel==8'hbf) ? i190 : (sel==8'hc0) ? i191
: (sel==8'hc1) ? i192 : (sel==8'hc2) ? i193 : (sel==8'hc3) ? i194 : (sel==8'hc4) ? i195
: (sel==8'hc5) ? i196 : (sel==8'hc6) ? i197 : (sel==8'hc7) ? i198 : (sel==8'hc8) ? i199
: (sel==8'hc9) ? i200 : (sel==8'hca) ? i201 : (sel==8'hcb) ? i202 : (sel==8'hcc) ? i203
: (sel==8'hcd) ? i204 : (sel==8'hce) ? i205 : (sel==8'hcf) ? i206 : (sel==8'hd0) ? i207
: (sel==8'hd1) ? i208 : (sel==8'hd2) ? i209 : (sel==8'hd3) ? i210 : (sel==8'hd4) ? i211
: (sel==8'hd5) ? i212 : (sel==8'hd6) ? i213 : (sel==8'hd7) ? i214 : (sel==8'hd8) ? i215
: (sel==8'hd9) ? i216 : (sel==8'hda) ? i217 : (sel==8'hdb) ? i218 : (sel==8'hdc) ? i219
: (sel==8'hdd) ? i220 : (sel==8'hde) ? i221 : (sel==8'hdf) ? i222 : (sel==8'he0) ? i223
: (sel==8'he1) ? i224 : (sel==8'he2) ? i225 : (sel==8'he3) ? i226 : (sel==8'he4) ? i227
: (sel==8'he5) ? i228 : (sel==8'he6) ? i229 : (sel==8'he7) ? i230 : (sel==8'he8) ? i231
: (sel==8'he9) ? i232 : (sel==8'hea) ? i233 : (sel==8'heb) ? i234 : (sel==8'hec) ? i235
: (sel==8'hed) ? i236 : (sel==8'hee) ? i237 : (sel==8'hef) ? i238 : (sel==8'hf0) ? i239
: (sel==8'hf1) ? i240 : (sel==8'hf2) ? i241 : (sel==8'hf3) ? i242 : (sel==8'hf4) ? i243
: (sel==8'hf5) ? i244 : (sel==8'hf6) ? i245 : (sel==8'hf7) ? i246 : (sel==8'hf8) ? i247
: (sel==8'hf9) ? i248 : (sel==8'hfa) ? i249 : (sel==8'hfb) ? i250 : (sel==8'hfc) ? i251
: (sel==8'hfd) ? i252 : (sel==8'hfe) ? i253 : (sel==8'hff) ? i254 : i255;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t_case_huge_sub (/*AUTOARG*/
// Outputs
outa, outb, outc,
// Inputs
index
);
input [7:0] index;
output [9:0] outa;
output [1:0] outb;
output outc;
// =============================
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [9:0] outa;
reg [1:0] outb;
reg outc;
// End of automatics
// =============================
// Created from perl
// for $i (0..1023) { printf "\t10'h%03x: begin outa = 10'h%03x; outb = 2'b%02b; outc = 1'b%d; end\n", $i, rand(1024),rand(4),rand(2); };
always @(/*AS*/index) begin
case (index)
8'h00: begin outa = 10'h152; outb = 2'b00; outc = 1'b1; end
8'h01: begin outa = 10'h318; outb = 2'b11; outc = 1'b1; end
8'h02: begin outa = 10'h29f; outb = 2'b11; outc = 1'b0; end
8'h03: begin outa = 10'h392; outb = 2'b01; outc = 1'b1; end
8'h04: begin outa = 10'h1ef; outb = 2'b00; outc = 1'b0; end
8'h05: begin outa = 10'h06c; outb = 2'b10; outc = 1'b1; end
8'h06: begin outa = 10'h29f; outb = 2'b11; outc = 1'b0; end
8'h07: begin outa = 10'h29a; outb = 2'b10; outc = 1'b0; end
8'h08: begin outa = 10'h3ce; outb = 2'b01; outc = 1'b0; end
8'h09: begin outa = 10'h37c; outb = 2'b01; outc = 1'b0; end
8'h0a: begin outa = 10'h058; outb = 2'b10; outc = 1'b0; end
8'h0b: begin outa = 10'h3b2; outb = 2'b01; outc = 1'b1; end
8'h0c: begin outa = 10'h36f; outb = 2'b11; outc = 1'b0; end
8'h0d: begin outa = 10'h2c5; outb = 2'b11; outc = 1'b0; end
8'h0e: begin outa = 10'h23a; outb = 2'b00; outc = 1'b0; end
8'h0f: begin outa = 10'h222; outb = 2'b01; outc = 1'b1; end
8'h10: begin outa = 10'h328; outb = 2'b00; outc = 1'b1; end
8'h11: begin outa = 10'h3c3; outb = 2'b00; outc = 1'b1; end
8'h12: begin outa = 10'h12c; outb = 2'b01; outc = 1'b0; end
8'h13: begin outa = 10'h1d0; outb = 2'b00; outc = 1'b1; end
8'h14: begin outa = 10'h3ff; outb = 2'b01; outc = 1'b1; end
8'h15: begin outa = 10'h115; outb = 2'b11; outc = 1'b1; end
8'h16: begin outa = 10'h3ba; outb = 2'b10; outc = 1'b0; end
8'h17: begin outa = 10'h3ba; outb = 2'b00; outc = 1'b0; end
8'h18: begin outa = 10'h10d; outb = 2'b00; outc = 1'b1; end
8'h19: begin outa = 10'h13b; outb = 2'b01; outc = 1'b1; end
8'h1a: begin outa = 10'h0a0; outb = 2'b10; outc = 1'b1; end
8'h1b: begin outa = 10'h264; outb = 2'b11; outc = 1'b0; end
8'h1c: begin outa = 10'h3a2; outb = 2'b10; outc = 1'b0; end
8'h1d: begin outa = 10'h07c; outb = 2'b00; outc = 1'b1; end
8'h1e: begin outa = 10'h291; outb = 2'b00; outc = 1'b0; end
8'h1f: begin outa = 10'h1d1; outb = 2'b10; outc = 1'b0; end
8'h20: begin outa = 10'h354; outb = 2'b11; outc = 1'b1; end
8'h21: begin outa = 10'h0c0; outb = 2'b00; outc = 1'b1; end
8'h22: begin outa = 10'h191; outb = 2'b00; outc = 1'b0; end
8'h23: begin outa = 10'h379; outb = 2'b01; outc = 1'b0; end
8'h24: begin outa = 10'h073; outb = 2'b00; outc = 1'b0; end
8'h25: begin outa = 10'h2fd; outb = 2'b11; outc = 1'b1; end
8'h26: begin outa = 10'h2e0; outb = 2'b11; outc = 1'b1; end
8'h27: begin outa = 10'h337; outb = 2'b01; outc = 1'b1; end
8'h28: begin outa = 10'h2c7; outb = 2'b11; outc = 1'b1; end
8'h29: begin outa = 10'h19e; outb = 2'b11; outc = 1'b0; end
8'h2a: begin outa = 10'h107; outb = 2'b10; outc = 1'b0; end
8'h2b: begin outa = 10'h06a; outb = 2'b01; outc = 1'b1; end
8'h2c: begin outa = 10'h1c7; outb = 2'b01; outc = 1'b1; end
8'h2d: begin outa = 10'h107; outb = 2'b10; outc = 1'b0; end
8'h2e: begin outa = 10'h0cf; outb = 2'b01; outc = 1'b1; end
8'h2f: begin outa = 10'h009; outb = 2'b11; outc = 1'b1; end
8'h30: begin outa = 10'h09d; outb = 2'b00; outc = 1'b1; end
8'h31: begin outa = 10'h28e; outb = 2'b00; outc = 1'b0; end
8'h32: begin outa = 10'h010; outb = 2'b01; outc = 1'b0; end
8'h33: begin outa = 10'h1e0; outb = 2'b10; outc = 1'b0; end
8'h34: begin outa = 10'h079; outb = 2'b01; outc = 1'b1; end
8'h35: begin outa = 10'h13e; outb = 2'b10; outc = 1'b1; end
8'h36: begin outa = 10'h282; outb = 2'b11; outc = 1'b0; end
8'h37: begin outa = 10'h21c; outb = 2'b11; outc = 1'b1; end
8'h38: begin outa = 10'h148; outb = 2'b00; outc = 1'b1; end
8'h39: begin outa = 10'h3c0; outb = 2'b10; outc = 1'b0; end
8'h3a: begin outa = 10'h176; outb = 2'b01; outc = 1'b1; end
8'h3b: begin outa = 10'h3fc; outb = 2'b10; outc = 1'b1; end
8'h3c: begin outa = 10'h295; outb = 2'b11; outc = 1'b1; end
8'h3d: begin outa = 10'h113; outb = 2'b10; outc = 1'b1; end
8'h3e: begin outa = 10'h354; outb = 2'b01; outc = 1'b1; end
8'h3f: begin outa = 10'h0db; outb = 2'b11; outc = 1'b0; end
8'h40: begin outa = 10'h238; outb = 2'b01; outc = 1'b0; end
8'h41: begin outa = 10'h12b; outb = 2'b01; outc = 1'b1; end
8'h42: begin outa = 10'h1dc; outb = 2'b10; outc = 1'b0; end
8'h43: begin outa = 10'h137; outb = 2'b01; outc = 1'b1; end
8'h44: begin outa = 10'h1e2; outb = 2'b01; outc = 1'b1; end
8'h45: begin outa = 10'h3d5; outb = 2'b11; outc = 1'b1; end
8'h46: begin outa = 10'h30c; outb = 2'b11; outc = 1'b0; end
8'h47: begin outa = 10'h298; outb = 2'b11; outc = 1'b0; end
8'h48: begin outa = 10'h080; outb = 2'b00; outc = 1'b1; end
8'h49: begin outa = 10'h35a; outb = 2'b11; outc = 1'b1; end
8'h4a: begin outa = 10'h01b; outb = 2'b00; outc = 1'b0; end
8'h4b: begin outa = 10'h0a3; outb = 2'b11; outc = 1'b0; end
8'h4c: begin outa = 10'h0b3; outb = 2'b11; outc = 1'b1; end
8'h4d: begin outa = 10'h17a; outb = 2'b00; outc = 1'b0; end
8'h4e: begin outa = 10'h3ae; outb = 2'b11; outc = 1'b0; end
8'h4f: begin outa = 10'h078; outb = 2'b11; outc = 1'b0; end
8'h50: begin outa = 10'h322; outb = 2'b00; outc = 1'b1; end
8'h51: begin outa = 10'h213; outb = 2'b11; outc = 1'b0; end
8'h52: begin outa = 10'h11a; outb = 2'b11; outc = 1'b0; end
8'h53: begin outa = 10'h1a7; outb = 2'b00; outc = 1'b0; end
8'h54: begin outa = 10'h35a; outb = 2'b00; outc = 1'b1; end
8'h55: begin outa = 10'h233; outb = 2'b00; outc = 1'b0; end
8'h56: begin outa = 10'h01d; outb = 2'b01; outc = 1'b1; end
8'h57: begin outa = 10'h2d5; outb = 2'b00; outc = 1'b0; end
8'h58: begin outa = 10'h1a0; outb = 2'b00; outc = 1'b1; end
8'h59: begin outa = 10'h3d0; outb = 2'b00; outc = 1'b1; end
8'h5a: begin outa = 10'h181; outb = 2'b01; outc = 1'b1; end
8'h5b: begin outa = 10'h219; outb = 2'b01; outc = 1'b1; end
8'h5c: begin outa = 10'h26a; outb = 2'b01; outc = 1'b1; end
8'h5d: begin outa = 10'h050; outb = 2'b10; outc = 1'b0; end
8'h5e: begin outa = 10'h189; outb = 2'b10; outc = 1'b0; end
8'h5f: begin outa = 10'h1eb; outb = 2'b01; outc = 1'b1; end
8'h60: begin outa = 10'h224; outb = 2'b00; outc = 1'b1; end
8'h61: begin outa = 10'h2fe; outb = 2'b00; outc = 1'b0; end
8'h62: begin outa = 10'h0ae; outb = 2'b00; outc = 1'b1; end
8'h63: begin outa = 10'h1cd; outb = 2'b00; outc = 1'b0; end
8'h64: begin outa = 10'h273; outb = 2'b10; outc = 1'b1; end
8'h65: begin outa = 10'h268; outb = 2'b10; outc = 1'b0; end
8'h66: begin outa = 10'h111; outb = 2'b01; outc = 1'b0; end
8'h67: begin outa = 10'h1f9; outb = 2'b00; outc = 1'b0; end
8'h68: begin outa = 10'h232; outb = 2'b00; outc = 1'b1; end
8'h69: begin outa = 10'h255; outb = 2'b11; outc = 1'b0; end
8'h6a: begin outa = 10'h34c; outb = 2'b01; outc = 1'b1; end
8'h6b: begin outa = 10'h049; outb = 2'b01; outc = 1'b1; end
8'h6c: begin outa = 10'h197; outb = 2'b11; outc = 1'b0; end
8'h6d: begin outa = 10'h0fe; outb = 2'b11; outc = 1'b0; end
8'h6e: begin outa = 10'h253; outb = 2'b01; outc = 1'b1; end
8'h6f: begin outa = 10'h2de; outb = 2'b11; outc = 1'b0; end
8'h70: begin outa = 10'h13b; outb = 2'b10; outc = 1'b1; end
8'h71: begin outa = 10'h040; outb = 2'b10; outc = 1'b0; end
8'h72: begin outa = 10'h0b4; outb = 2'b00; outc = 1'b1; end
8'h73: begin outa = 10'h233; outb = 2'b11; outc = 1'b1; end
8'h74: begin outa = 10'h198; outb = 2'b00; outc = 1'b1; end
8'h75: begin outa = 10'h018; outb = 2'b00; outc = 1'b1; end
8'h76: begin outa = 10'h2f7; outb = 2'b00; outc = 1'b1; end
8'h77: begin outa = 10'h134; outb = 2'b11; outc = 1'b0; end
8'h78: begin outa = 10'h1ca; outb = 2'b10; outc = 1'b0; end
8'h79: begin outa = 10'h286; outb = 2'b10; outc = 1'b1; end
8'h7a: begin outa = 10'h0e6; outb = 2'b11; outc = 1'b1; end
8'h7b: begin outa = 10'h064; outb = 2'b10; outc = 1'b1; end
8'h7c: begin outa = 10'h257; outb = 2'b00; outc = 1'b1; end
8'h7d: begin outa = 10'h31a; outb = 2'b10; outc = 1'b1; end
8'h7e: begin outa = 10'h247; outb = 2'b01; outc = 1'b0; end
8'h7f: begin outa = 10'h299; outb = 2'b00; outc = 1'b0; end
8'h80: begin outa = 10'h02c; outb = 2'b00; outc = 1'b0; end
8'h81: begin outa = 10'h2bb; outb = 2'b11; outc = 1'b0; end
8'h82: begin outa = 10'h180; outb = 2'b10; outc = 1'b0; end
8'h83: begin outa = 10'h245; outb = 2'b01; outc = 1'b1; end
8'h84: begin outa = 10'h0da; outb = 2'b10; outc = 1'b0; end
8'h85: begin outa = 10'h367; outb = 2'b10; outc = 1'b0; end
8'h86: begin outa = 10'h304; outb = 2'b01; outc = 1'b0; end
8'h87: begin outa = 10'h38b; outb = 2'b11; outc = 1'b0; end
8'h88: begin outa = 10'h09f; outb = 2'b01; outc = 1'b0; end
8'h89: begin outa = 10'h1f0; outb = 2'b10; outc = 1'b1; end
8'h8a: begin outa = 10'h281; outb = 2'b10; outc = 1'b1; end
8'h8b: begin outa = 10'h019; outb = 2'b00; outc = 1'b0; end
8'h8c: begin outa = 10'h1f2; outb = 2'b10; outc = 1'b0; end
8'h8d: begin outa = 10'h0b1; outb = 2'b01; outc = 1'b1; end
8'h8e: begin outa = 10'h058; outb = 2'b01; outc = 1'b1; end
8'h8f: begin outa = 10'h39b; outb = 2'b00; outc = 1'b1; end
8'h90: begin outa = 10'h2ec; outb = 2'b10; outc = 1'b1; end
8'h91: begin outa = 10'h250; outb = 2'b00; outc = 1'b1; end
8'h92: begin outa = 10'h3f4; outb = 2'b10; outc = 1'b1; end
8'h93: begin outa = 10'h057; outb = 2'b10; outc = 1'b1; end
8'h94: begin outa = 10'h18f; outb = 2'b01; outc = 1'b1; end
8'h95: begin outa = 10'h105; outb = 2'b01; outc = 1'b1; end
8'h96: begin outa = 10'h1ae; outb = 2'b00; outc = 1'b1; end
8'h97: begin outa = 10'h04e; outb = 2'b10; outc = 1'b0; end
8'h98: begin outa = 10'h240; outb = 2'b11; outc = 1'b0; end
8'h99: begin outa = 10'h3e4; outb = 2'b01; outc = 1'b0; end
8'h9a: begin outa = 10'h3c6; outb = 2'b01; outc = 1'b0; end
8'h9b: begin outa = 10'h109; outb = 2'b00; outc = 1'b1; end
8'h9c: begin outa = 10'h073; outb = 2'b10; outc = 1'b1; end
8'h9d: begin outa = 10'h19f; outb = 2'b01; outc = 1'b0; end
8'h9e: begin outa = 10'h3b8; outb = 2'b01; outc = 1'b0; end
8'h9f: begin outa = 10'h00e; outb = 2'b00; outc = 1'b1; end
8'ha0: begin outa = 10'h1b3; outb = 2'b11; outc = 1'b1; end
8'ha1: begin outa = 10'h2bd; outb = 2'b11; outc = 1'b0; end
8'ha2: begin outa = 10'h324; outb = 2'b00; outc = 1'b1; end
8'ha3: begin outa = 10'h343; outb = 2'b10; outc = 1'b0; end
8'ha4: begin outa = 10'h1c9; outb = 2'b01; outc = 1'b0; end
8'ha5: begin outa = 10'h185; outb = 2'b00; outc = 1'b1; end
8'ha6: begin outa = 10'h37a; outb = 2'b00; outc = 1'b1; end
8'ha7: begin outa = 10'h0e0; outb = 2'b01; outc = 1'b1; end
8'ha8: begin outa = 10'h0a3; outb = 2'b10; outc = 1'b0; end
8'ha9: begin outa = 10'h019; outb = 2'b11; outc = 1'b0; end
8'haa: begin outa = 10'h099; outb = 2'b00; outc = 1'b1; end
8'hab: begin outa = 10'h376; outb = 2'b01; outc = 1'b1; end
8'hac: begin outa = 10'h077; outb = 2'b00; outc = 1'b1; end
8'had: begin outa = 10'h2b1; outb = 2'b11; outc = 1'b1; end
8'hae: begin outa = 10'h27f; outb = 2'b00; outc = 1'b0; end
8'haf: begin outa = 10'h265; outb = 2'b11; outc = 1'b0; end
8'hb0: begin outa = 10'h156; outb = 2'b10; outc = 1'b1; end
8'hb1: begin outa = 10'h1ce; outb = 2'b00; outc = 1'b0; end
8'hb2: begin outa = 10'h008; outb = 2'b01; outc = 1'b0; end
8'hb3: begin outa = 10'h12e; outb = 2'b11; outc = 1'b1; end
8'hb4: begin outa = 10'h199; outb = 2'b11; outc = 1'b0; end
8'hb5: begin outa = 10'h330; outb = 2'b10; outc = 1'b0; end
8'hb6: begin outa = 10'h1ab; outb = 2'b01; outc = 1'b1; end
8'hb7: begin outa = 10'h3bd; outb = 2'b00; outc = 1'b0; end
8'hb8: begin outa = 10'h0ca; outb = 2'b10; outc = 1'b0; end
8'hb9: begin outa = 10'h367; outb = 2'b00; outc = 1'b0; end
8'hba: begin outa = 10'h334; outb = 2'b00; outc = 1'b0; end
8'hbb: begin outa = 10'h040; outb = 2'b00; outc = 1'b1; end
8'hbc: begin outa = 10'h1a7; outb = 2'b10; outc = 1'b1; end
8'hbd: begin outa = 10'h036; outb = 2'b11; outc = 1'b1; end
8'hbe: begin outa = 10'h223; outb = 2'b11; outc = 1'b1; end
8'hbf: begin outa = 10'h075; outb = 2'b01; outc = 1'b0; end
8'hc0: begin outa = 10'h3c4; outb = 2'b00; outc = 1'b1; end
8'hc1: begin outa = 10'h2cc; outb = 2'b01; outc = 1'b0; end
8'hc2: begin outa = 10'h123; outb = 2'b01; outc = 1'b0; end
8'hc3: begin outa = 10'h3fd; outb = 2'b01; outc = 1'b1; end
8'hc4: begin outa = 10'h11e; outb = 2'b00; outc = 1'b0; end
8'hc5: begin outa = 10'h27c; outb = 2'b11; outc = 1'b1; end
8'hc6: begin outa = 10'h1e2; outb = 2'b11; outc = 1'b0; end
8'hc7: begin outa = 10'h377; outb = 2'b11; outc = 1'b0; end
8'hc8: begin outa = 10'h33a; outb = 2'b11; outc = 1'b0; end
8'hc9: begin outa = 10'h32d; outb = 2'b11; outc = 1'b1; end
8'hca: begin outa = 10'h014; outb = 2'b11; outc = 1'b0; end
8'hcb: begin outa = 10'h332; outb = 2'b10; outc = 1'b0; end
8'hcc: begin outa = 10'h359; outb = 2'b00; outc = 1'b0; end
8'hcd: begin outa = 10'h0a4; outb = 2'b10; outc = 1'b1; end
8'hce: begin outa = 10'h348; outb = 2'b00; outc = 1'b1; end
8'hcf: begin outa = 10'h04b; outb = 2'b11; outc = 1'b1; end
8'hd0: begin outa = 10'h147; outb = 2'b10; outc = 1'b1; end
8'hd1: begin outa = 10'h026; outb = 2'b00; outc = 1'b1; end
8'hd2: begin outa = 10'h103; outb = 2'b00; outc = 1'b0; end
8'hd3: begin outa = 10'h106; outb = 2'b00; outc = 1'b1; end
8'hd4: begin outa = 10'h35a; outb = 2'b00; outc = 1'b0; end
8'hd5: begin outa = 10'h254; outb = 2'b01; outc = 1'b0; end
8'hd6: begin outa = 10'h0cd; outb = 2'b01; outc = 1'b0; end
8'hd7: begin outa = 10'h17c; outb = 2'b11; outc = 1'b1; end
8'hd8: begin outa = 10'h37e; outb = 2'b10; outc = 1'b1; end
8'hd9: begin outa = 10'h0a9; outb = 2'b11; outc = 1'b1; end
8'hda: begin outa = 10'h0fe; outb = 2'b01; outc = 1'b0; end
8'hdb: begin outa = 10'h3c0; outb = 2'b11; outc = 1'b1; end
8'hdc: begin outa = 10'h1d9; outb = 2'b10; outc = 1'b1; end
8'hdd: begin outa = 10'h10e; outb = 2'b00; outc = 1'b1; end
8'hde: begin outa = 10'h394; outb = 2'b01; outc = 1'b0; end
8'hdf: begin outa = 10'h316; outb = 2'b01; outc = 1'b0; end
8'he0: begin outa = 10'h05b; outb = 2'b11; outc = 1'b0; end
8'he1: begin outa = 10'h126; outb = 2'b01; outc = 1'b1; end
8'he2: begin outa = 10'h369; outb = 2'b11; outc = 1'b0; end
8'he3: begin outa = 10'h291; outb = 2'b10; outc = 1'b1; end
8'he4: begin outa = 10'h2ca; outb = 2'b00; outc = 1'b1; end
8'he5: begin outa = 10'h25b; outb = 2'b01; outc = 1'b1; end
8'he6: begin outa = 10'h106; outb = 2'b00; outc = 1'b0; end
8'he7: begin outa = 10'h172; outb = 2'b11; outc = 1'b1; end
8'he8: begin outa = 10'h2f7; outb = 2'b00; outc = 1'b1; end
8'he9: begin outa = 10'h2d3; outb = 2'b11; outc = 1'b1; end
8'hea: begin outa = 10'h182; outb = 2'b00; outc = 1'b0; end
8'heb: begin outa = 10'h327; outb = 2'b00; outc = 1'b1; end
8'hec: begin outa = 10'h1d0; outb = 2'b10; outc = 1'b0; end
8'hed: begin outa = 10'h204; outb = 2'b00; outc = 1'b1; end
8'hee: begin outa = 10'h11f; outb = 2'b00; outc = 1'b1; end
8'hef: begin outa = 10'h365; outb = 2'b11; outc = 1'b1; end
8'hf0: begin outa = 10'h2c2; outb = 2'b01; outc = 1'b1; end
8'hf1: begin outa = 10'h2b5; outb = 2'b10; outc = 1'b0; end
8'hf2: begin outa = 10'h1f8; outb = 2'b10; outc = 1'b1; end
8'hf3: begin outa = 10'h2a7; outb = 2'b01; outc = 1'b1; end
8'hf4: begin outa = 10'h1be; outb = 2'b10; outc = 1'b1; end
8'hf5: begin outa = 10'h25e; outb = 2'b10; outc = 1'b1; end
8'hf6: begin outa = 10'h032; outb = 2'b10; outc = 1'b0; end
8'hf7: begin outa = 10'h2ef; outb = 2'b00; outc = 1'b0; end
8'hf8: begin outa = 10'h02f; outb = 2'b00; outc = 1'b1; end
8'hf9: begin outa = 10'h201; outb = 2'b10; outc = 1'b0; end
8'hfa: begin outa = 10'h054; outb = 2'b01; outc = 1'b1; end
8'hfb: begin outa = 10'h013; outb = 2'b10; outc = 1'b0; end
8'hfc: begin outa = 10'h249; outb = 2'b01; outc = 1'b0; end
8'hfd: begin outa = 10'h09a; outb = 2'b10; outc = 1'b0; end
8'hfe: begin outa = 10'h012; outb = 2'b00; outc = 1'b0; end
8'hff: begin outa = 10'h114; outb = 2'b10; outc = 1'b1; end
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t_case_huge_sub (/*AUTOARG*/
// Outputs
outa, outb, outc,
// Inputs
index
);
input [7:0] index;
output [9:0] outa;
output [1:0] outb;
output outc;
// =============================
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [9:0] outa;
reg [1:0] outb;
reg outc;
// End of automatics
// =============================
// Created from perl
// for $i (0..1023) { printf "\t10'h%03x: begin outa = 10'h%03x; outb = 2'b%02b; outc = 1'b%d; end\n", $i, rand(1024),rand(4),rand(2); };
always @(/*AS*/index) begin
case (index)
8'h00: begin outa = 10'h152; outb = 2'b00; outc = 1'b1; end
8'h01: begin outa = 10'h318; outb = 2'b11; outc = 1'b1; end
8'h02: begin outa = 10'h29f; outb = 2'b11; outc = 1'b0; end
8'h03: begin outa = 10'h392; outb = 2'b01; outc = 1'b1; end
8'h04: begin outa = 10'h1ef; outb = 2'b00; outc = 1'b0; end
8'h05: begin outa = 10'h06c; outb = 2'b10; outc = 1'b1; end
8'h06: begin outa = 10'h29f; outb = 2'b11; outc = 1'b0; end
8'h07: begin outa = 10'h29a; outb = 2'b10; outc = 1'b0; end
8'h08: begin outa = 10'h3ce; outb = 2'b01; outc = 1'b0; end
8'h09: begin outa = 10'h37c; outb = 2'b01; outc = 1'b0; end
8'h0a: begin outa = 10'h058; outb = 2'b10; outc = 1'b0; end
8'h0b: begin outa = 10'h3b2; outb = 2'b01; outc = 1'b1; end
8'h0c: begin outa = 10'h36f; outb = 2'b11; outc = 1'b0; end
8'h0d: begin outa = 10'h2c5; outb = 2'b11; outc = 1'b0; end
8'h0e: begin outa = 10'h23a; outb = 2'b00; outc = 1'b0; end
8'h0f: begin outa = 10'h222; outb = 2'b01; outc = 1'b1; end
8'h10: begin outa = 10'h328; outb = 2'b00; outc = 1'b1; end
8'h11: begin outa = 10'h3c3; outb = 2'b00; outc = 1'b1; end
8'h12: begin outa = 10'h12c; outb = 2'b01; outc = 1'b0; end
8'h13: begin outa = 10'h1d0; outb = 2'b00; outc = 1'b1; end
8'h14: begin outa = 10'h3ff; outb = 2'b01; outc = 1'b1; end
8'h15: begin outa = 10'h115; outb = 2'b11; outc = 1'b1; end
8'h16: begin outa = 10'h3ba; outb = 2'b10; outc = 1'b0; end
8'h17: begin outa = 10'h3ba; outb = 2'b00; outc = 1'b0; end
8'h18: begin outa = 10'h10d; outb = 2'b00; outc = 1'b1; end
8'h19: begin outa = 10'h13b; outb = 2'b01; outc = 1'b1; end
8'h1a: begin outa = 10'h0a0; outb = 2'b10; outc = 1'b1; end
8'h1b: begin outa = 10'h264; outb = 2'b11; outc = 1'b0; end
8'h1c: begin outa = 10'h3a2; outb = 2'b10; outc = 1'b0; end
8'h1d: begin outa = 10'h07c; outb = 2'b00; outc = 1'b1; end
8'h1e: begin outa = 10'h291; outb = 2'b00; outc = 1'b0; end
8'h1f: begin outa = 10'h1d1; outb = 2'b10; outc = 1'b0; end
8'h20: begin outa = 10'h354; outb = 2'b11; outc = 1'b1; end
8'h21: begin outa = 10'h0c0; outb = 2'b00; outc = 1'b1; end
8'h22: begin outa = 10'h191; outb = 2'b00; outc = 1'b0; end
8'h23: begin outa = 10'h379; outb = 2'b01; outc = 1'b0; end
8'h24: begin outa = 10'h073; outb = 2'b00; outc = 1'b0; end
8'h25: begin outa = 10'h2fd; outb = 2'b11; outc = 1'b1; end
8'h26: begin outa = 10'h2e0; outb = 2'b11; outc = 1'b1; end
8'h27: begin outa = 10'h337; outb = 2'b01; outc = 1'b1; end
8'h28: begin outa = 10'h2c7; outb = 2'b11; outc = 1'b1; end
8'h29: begin outa = 10'h19e; outb = 2'b11; outc = 1'b0; end
8'h2a: begin outa = 10'h107; outb = 2'b10; outc = 1'b0; end
8'h2b: begin outa = 10'h06a; outb = 2'b01; outc = 1'b1; end
8'h2c: begin outa = 10'h1c7; outb = 2'b01; outc = 1'b1; end
8'h2d: begin outa = 10'h107; outb = 2'b10; outc = 1'b0; end
8'h2e: begin outa = 10'h0cf; outb = 2'b01; outc = 1'b1; end
8'h2f: begin outa = 10'h009; outb = 2'b11; outc = 1'b1; end
8'h30: begin outa = 10'h09d; outb = 2'b00; outc = 1'b1; end
8'h31: begin outa = 10'h28e; outb = 2'b00; outc = 1'b0; end
8'h32: begin outa = 10'h010; outb = 2'b01; outc = 1'b0; end
8'h33: begin outa = 10'h1e0; outb = 2'b10; outc = 1'b0; end
8'h34: begin outa = 10'h079; outb = 2'b01; outc = 1'b1; end
8'h35: begin outa = 10'h13e; outb = 2'b10; outc = 1'b1; end
8'h36: begin outa = 10'h282; outb = 2'b11; outc = 1'b0; end
8'h37: begin outa = 10'h21c; outb = 2'b11; outc = 1'b1; end
8'h38: begin outa = 10'h148; outb = 2'b00; outc = 1'b1; end
8'h39: begin outa = 10'h3c0; outb = 2'b10; outc = 1'b0; end
8'h3a: begin outa = 10'h176; outb = 2'b01; outc = 1'b1; end
8'h3b: begin outa = 10'h3fc; outb = 2'b10; outc = 1'b1; end
8'h3c: begin outa = 10'h295; outb = 2'b11; outc = 1'b1; end
8'h3d: begin outa = 10'h113; outb = 2'b10; outc = 1'b1; end
8'h3e: begin outa = 10'h354; outb = 2'b01; outc = 1'b1; end
8'h3f: begin outa = 10'h0db; outb = 2'b11; outc = 1'b0; end
8'h40: begin outa = 10'h238; outb = 2'b01; outc = 1'b0; end
8'h41: begin outa = 10'h12b; outb = 2'b01; outc = 1'b1; end
8'h42: begin outa = 10'h1dc; outb = 2'b10; outc = 1'b0; end
8'h43: begin outa = 10'h137; outb = 2'b01; outc = 1'b1; end
8'h44: begin outa = 10'h1e2; outb = 2'b01; outc = 1'b1; end
8'h45: begin outa = 10'h3d5; outb = 2'b11; outc = 1'b1; end
8'h46: begin outa = 10'h30c; outb = 2'b11; outc = 1'b0; end
8'h47: begin outa = 10'h298; outb = 2'b11; outc = 1'b0; end
8'h48: begin outa = 10'h080; outb = 2'b00; outc = 1'b1; end
8'h49: begin outa = 10'h35a; outb = 2'b11; outc = 1'b1; end
8'h4a: begin outa = 10'h01b; outb = 2'b00; outc = 1'b0; end
8'h4b: begin outa = 10'h0a3; outb = 2'b11; outc = 1'b0; end
8'h4c: begin outa = 10'h0b3; outb = 2'b11; outc = 1'b1; end
8'h4d: begin outa = 10'h17a; outb = 2'b00; outc = 1'b0; end
8'h4e: begin outa = 10'h3ae; outb = 2'b11; outc = 1'b0; end
8'h4f: begin outa = 10'h078; outb = 2'b11; outc = 1'b0; end
8'h50: begin outa = 10'h322; outb = 2'b00; outc = 1'b1; end
8'h51: begin outa = 10'h213; outb = 2'b11; outc = 1'b0; end
8'h52: begin outa = 10'h11a; outb = 2'b11; outc = 1'b0; end
8'h53: begin outa = 10'h1a7; outb = 2'b00; outc = 1'b0; end
8'h54: begin outa = 10'h35a; outb = 2'b00; outc = 1'b1; end
8'h55: begin outa = 10'h233; outb = 2'b00; outc = 1'b0; end
8'h56: begin outa = 10'h01d; outb = 2'b01; outc = 1'b1; end
8'h57: begin outa = 10'h2d5; outb = 2'b00; outc = 1'b0; end
8'h58: begin outa = 10'h1a0; outb = 2'b00; outc = 1'b1; end
8'h59: begin outa = 10'h3d0; outb = 2'b00; outc = 1'b1; end
8'h5a: begin outa = 10'h181; outb = 2'b01; outc = 1'b1; end
8'h5b: begin outa = 10'h219; outb = 2'b01; outc = 1'b1; end
8'h5c: begin outa = 10'h26a; outb = 2'b01; outc = 1'b1; end
8'h5d: begin outa = 10'h050; outb = 2'b10; outc = 1'b0; end
8'h5e: begin outa = 10'h189; outb = 2'b10; outc = 1'b0; end
8'h5f: begin outa = 10'h1eb; outb = 2'b01; outc = 1'b1; end
8'h60: begin outa = 10'h224; outb = 2'b00; outc = 1'b1; end
8'h61: begin outa = 10'h2fe; outb = 2'b00; outc = 1'b0; end
8'h62: begin outa = 10'h0ae; outb = 2'b00; outc = 1'b1; end
8'h63: begin outa = 10'h1cd; outb = 2'b00; outc = 1'b0; end
8'h64: begin outa = 10'h273; outb = 2'b10; outc = 1'b1; end
8'h65: begin outa = 10'h268; outb = 2'b10; outc = 1'b0; end
8'h66: begin outa = 10'h111; outb = 2'b01; outc = 1'b0; end
8'h67: begin outa = 10'h1f9; outb = 2'b00; outc = 1'b0; end
8'h68: begin outa = 10'h232; outb = 2'b00; outc = 1'b1; end
8'h69: begin outa = 10'h255; outb = 2'b11; outc = 1'b0; end
8'h6a: begin outa = 10'h34c; outb = 2'b01; outc = 1'b1; end
8'h6b: begin outa = 10'h049; outb = 2'b01; outc = 1'b1; end
8'h6c: begin outa = 10'h197; outb = 2'b11; outc = 1'b0; end
8'h6d: begin outa = 10'h0fe; outb = 2'b11; outc = 1'b0; end
8'h6e: begin outa = 10'h253; outb = 2'b01; outc = 1'b1; end
8'h6f: begin outa = 10'h2de; outb = 2'b11; outc = 1'b0; end
8'h70: begin outa = 10'h13b; outb = 2'b10; outc = 1'b1; end
8'h71: begin outa = 10'h040; outb = 2'b10; outc = 1'b0; end
8'h72: begin outa = 10'h0b4; outb = 2'b00; outc = 1'b1; end
8'h73: begin outa = 10'h233; outb = 2'b11; outc = 1'b1; end
8'h74: begin outa = 10'h198; outb = 2'b00; outc = 1'b1; end
8'h75: begin outa = 10'h018; outb = 2'b00; outc = 1'b1; end
8'h76: begin outa = 10'h2f7; outb = 2'b00; outc = 1'b1; end
8'h77: begin outa = 10'h134; outb = 2'b11; outc = 1'b0; end
8'h78: begin outa = 10'h1ca; outb = 2'b10; outc = 1'b0; end
8'h79: begin outa = 10'h286; outb = 2'b10; outc = 1'b1; end
8'h7a: begin outa = 10'h0e6; outb = 2'b11; outc = 1'b1; end
8'h7b: begin outa = 10'h064; outb = 2'b10; outc = 1'b1; end
8'h7c: begin outa = 10'h257; outb = 2'b00; outc = 1'b1; end
8'h7d: begin outa = 10'h31a; outb = 2'b10; outc = 1'b1; end
8'h7e: begin outa = 10'h247; outb = 2'b01; outc = 1'b0; end
8'h7f: begin outa = 10'h299; outb = 2'b00; outc = 1'b0; end
8'h80: begin outa = 10'h02c; outb = 2'b00; outc = 1'b0; end
8'h81: begin outa = 10'h2bb; outb = 2'b11; outc = 1'b0; end
8'h82: begin outa = 10'h180; outb = 2'b10; outc = 1'b0; end
8'h83: begin outa = 10'h245; outb = 2'b01; outc = 1'b1; end
8'h84: begin outa = 10'h0da; outb = 2'b10; outc = 1'b0; end
8'h85: begin outa = 10'h367; outb = 2'b10; outc = 1'b0; end
8'h86: begin outa = 10'h304; outb = 2'b01; outc = 1'b0; end
8'h87: begin outa = 10'h38b; outb = 2'b11; outc = 1'b0; end
8'h88: begin outa = 10'h09f; outb = 2'b01; outc = 1'b0; end
8'h89: begin outa = 10'h1f0; outb = 2'b10; outc = 1'b1; end
8'h8a: begin outa = 10'h281; outb = 2'b10; outc = 1'b1; end
8'h8b: begin outa = 10'h019; outb = 2'b00; outc = 1'b0; end
8'h8c: begin outa = 10'h1f2; outb = 2'b10; outc = 1'b0; end
8'h8d: begin outa = 10'h0b1; outb = 2'b01; outc = 1'b1; end
8'h8e: begin outa = 10'h058; outb = 2'b01; outc = 1'b1; end
8'h8f: begin outa = 10'h39b; outb = 2'b00; outc = 1'b1; end
8'h90: begin outa = 10'h2ec; outb = 2'b10; outc = 1'b1; end
8'h91: begin outa = 10'h250; outb = 2'b00; outc = 1'b1; end
8'h92: begin outa = 10'h3f4; outb = 2'b10; outc = 1'b1; end
8'h93: begin outa = 10'h057; outb = 2'b10; outc = 1'b1; end
8'h94: begin outa = 10'h18f; outb = 2'b01; outc = 1'b1; end
8'h95: begin outa = 10'h105; outb = 2'b01; outc = 1'b1; end
8'h96: begin outa = 10'h1ae; outb = 2'b00; outc = 1'b1; end
8'h97: begin outa = 10'h04e; outb = 2'b10; outc = 1'b0; end
8'h98: begin outa = 10'h240; outb = 2'b11; outc = 1'b0; end
8'h99: begin outa = 10'h3e4; outb = 2'b01; outc = 1'b0; end
8'h9a: begin outa = 10'h3c6; outb = 2'b01; outc = 1'b0; end
8'h9b: begin outa = 10'h109; outb = 2'b00; outc = 1'b1; end
8'h9c: begin outa = 10'h073; outb = 2'b10; outc = 1'b1; end
8'h9d: begin outa = 10'h19f; outb = 2'b01; outc = 1'b0; end
8'h9e: begin outa = 10'h3b8; outb = 2'b01; outc = 1'b0; end
8'h9f: begin outa = 10'h00e; outb = 2'b00; outc = 1'b1; end
8'ha0: begin outa = 10'h1b3; outb = 2'b11; outc = 1'b1; end
8'ha1: begin outa = 10'h2bd; outb = 2'b11; outc = 1'b0; end
8'ha2: begin outa = 10'h324; outb = 2'b00; outc = 1'b1; end
8'ha3: begin outa = 10'h343; outb = 2'b10; outc = 1'b0; end
8'ha4: begin outa = 10'h1c9; outb = 2'b01; outc = 1'b0; end
8'ha5: begin outa = 10'h185; outb = 2'b00; outc = 1'b1; end
8'ha6: begin outa = 10'h37a; outb = 2'b00; outc = 1'b1; end
8'ha7: begin outa = 10'h0e0; outb = 2'b01; outc = 1'b1; end
8'ha8: begin outa = 10'h0a3; outb = 2'b10; outc = 1'b0; end
8'ha9: begin outa = 10'h019; outb = 2'b11; outc = 1'b0; end
8'haa: begin outa = 10'h099; outb = 2'b00; outc = 1'b1; end
8'hab: begin outa = 10'h376; outb = 2'b01; outc = 1'b1; end
8'hac: begin outa = 10'h077; outb = 2'b00; outc = 1'b1; end
8'had: begin outa = 10'h2b1; outb = 2'b11; outc = 1'b1; end
8'hae: begin outa = 10'h27f; outb = 2'b00; outc = 1'b0; end
8'haf: begin outa = 10'h265; outb = 2'b11; outc = 1'b0; end
8'hb0: begin outa = 10'h156; outb = 2'b10; outc = 1'b1; end
8'hb1: begin outa = 10'h1ce; outb = 2'b00; outc = 1'b0; end
8'hb2: begin outa = 10'h008; outb = 2'b01; outc = 1'b0; end
8'hb3: begin outa = 10'h12e; outb = 2'b11; outc = 1'b1; end
8'hb4: begin outa = 10'h199; outb = 2'b11; outc = 1'b0; end
8'hb5: begin outa = 10'h330; outb = 2'b10; outc = 1'b0; end
8'hb6: begin outa = 10'h1ab; outb = 2'b01; outc = 1'b1; end
8'hb7: begin outa = 10'h3bd; outb = 2'b00; outc = 1'b0; end
8'hb8: begin outa = 10'h0ca; outb = 2'b10; outc = 1'b0; end
8'hb9: begin outa = 10'h367; outb = 2'b00; outc = 1'b0; end
8'hba: begin outa = 10'h334; outb = 2'b00; outc = 1'b0; end
8'hbb: begin outa = 10'h040; outb = 2'b00; outc = 1'b1; end
8'hbc: begin outa = 10'h1a7; outb = 2'b10; outc = 1'b1; end
8'hbd: begin outa = 10'h036; outb = 2'b11; outc = 1'b1; end
8'hbe: begin outa = 10'h223; outb = 2'b11; outc = 1'b1; end
8'hbf: begin outa = 10'h075; outb = 2'b01; outc = 1'b0; end
8'hc0: begin outa = 10'h3c4; outb = 2'b00; outc = 1'b1; end
8'hc1: begin outa = 10'h2cc; outb = 2'b01; outc = 1'b0; end
8'hc2: begin outa = 10'h123; outb = 2'b01; outc = 1'b0; end
8'hc3: begin outa = 10'h3fd; outb = 2'b01; outc = 1'b1; end
8'hc4: begin outa = 10'h11e; outb = 2'b00; outc = 1'b0; end
8'hc5: begin outa = 10'h27c; outb = 2'b11; outc = 1'b1; end
8'hc6: begin outa = 10'h1e2; outb = 2'b11; outc = 1'b0; end
8'hc7: begin outa = 10'h377; outb = 2'b11; outc = 1'b0; end
8'hc8: begin outa = 10'h33a; outb = 2'b11; outc = 1'b0; end
8'hc9: begin outa = 10'h32d; outb = 2'b11; outc = 1'b1; end
8'hca: begin outa = 10'h014; outb = 2'b11; outc = 1'b0; end
8'hcb: begin outa = 10'h332; outb = 2'b10; outc = 1'b0; end
8'hcc: begin outa = 10'h359; outb = 2'b00; outc = 1'b0; end
8'hcd: begin outa = 10'h0a4; outb = 2'b10; outc = 1'b1; end
8'hce: begin outa = 10'h348; outb = 2'b00; outc = 1'b1; end
8'hcf: begin outa = 10'h04b; outb = 2'b11; outc = 1'b1; end
8'hd0: begin outa = 10'h147; outb = 2'b10; outc = 1'b1; end
8'hd1: begin outa = 10'h026; outb = 2'b00; outc = 1'b1; end
8'hd2: begin outa = 10'h103; outb = 2'b00; outc = 1'b0; end
8'hd3: begin outa = 10'h106; outb = 2'b00; outc = 1'b1; end
8'hd4: begin outa = 10'h35a; outb = 2'b00; outc = 1'b0; end
8'hd5: begin outa = 10'h254; outb = 2'b01; outc = 1'b0; end
8'hd6: begin outa = 10'h0cd; outb = 2'b01; outc = 1'b0; end
8'hd7: begin outa = 10'h17c; outb = 2'b11; outc = 1'b1; end
8'hd8: begin outa = 10'h37e; outb = 2'b10; outc = 1'b1; end
8'hd9: begin outa = 10'h0a9; outb = 2'b11; outc = 1'b1; end
8'hda: begin outa = 10'h0fe; outb = 2'b01; outc = 1'b0; end
8'hdb: begin outa = 10'h3c0; outb = 2'b11; outc = 1'b1; end
8'hdc: begin outa = 10'h1d9; outb = 2'b10; outc = 1'b1; end
8'hdd: begin outa = 10'h10e; outb = 2'b00; outc = 1'b1; end
8'hde: begin outa = 10'h394; outb = 2'b01; outc = 1'b0; end
8'hdf: begin outa = 10'h316; outb = 2'b01; outc = 1'b0; end
8'he0: begin outa = 10'h05b; outb = 2'b11; outc = 1'b0; end
8'he1: begin outa = 10'h126; outb = 2'b01; outc = 1'b1; end
8'he2: begin outa = 10'h369; outb = 2'b11; outc = 1'b0; end
8'he3: begin outa = 10'h291; outb = 2'b10; outc = 1'b1; end
8'he4: begin outa = 10'h2ca; outb = 2'b00; outc = 1'b1; end
8'he5: begin outa = 10'h25b; outb = 2'b01; outc = 1'b1; end
8'he6: begin outa = 10'h106; outb = 2'b00; outc = 1'b0; end
8'he7: begin outa = 10'h172; outb = 2'b11; outc = 1'b1; end
8'he8: begin outa = 10'h2f7; outb = 2'b00; outc = 1'b1; end
8'he9: begin outa = 10'h2d3; outb = 2'b11; outc = 1'b1; end
8'hea: begin outa = 10'h182; outb = 2'b00; outc = 1'b0; end
8'heb: begin outa = 10'h327; outb = 2'b00; outc = 1'b1; end
8'hec: begin outa = 10'h1d0; outb = 2'b10; outc = 1'b0; end
8'hed: begin outa = 10'h204; outb = 2'b00; outc = 1'b1; end
8'hee: begin outa = 10'h11f; outb = 2'b00; outc = 1'b1; end
8'hef: begin outa = 10'h365; outb = 2'b11; outc = 1'b1; end
8'hf0: begin outa = 10'h2c2; outb = 2'b01; outc = 1'b1; end
8'hf1: begin outa = 10'h2b5; outb = 2'b10; outc = 1'b0; end
8'hf2: begin outa = 10'h1f8; outb = 2'b10; outc = 1'b1; end
8'hf3: begin outa = 10'h2a7; outb = 2'b01; outc = 1'b1; end
8'hf4: begin outa = 10'h1be; outb = 2'b10; outc = 1'b1; end
8'hf5: begin outa = 10'h25e; outb = 2'b10; outc = 1'b1; end
8'hf6: begin outa = 10'h032; outb = 2'b10; outc = 1'b0; end
8'hf7: begin outa = 10'h2ef; outb = 2'b00; outc = 1'b0; end
8'hf8: begin outa = 10'h02f; outb = 2'b00; outc = 1'b1; end
8'hf9: begin outa = 10'h201; outb = 2'b10; outc = 1'b0; end
8'hfa: begin outa = 10'h054; outb = 2'b01; outc = 1'b1; end
8'hfb: begin outa = 10'h013; outb = 2'b10; outc = 1'b0; end
8'hfc: begin outa = 10'h249; outb = 2'b01; outc = 1'b0; end
8'hfd: begin outa = 10'h09a; outb = 2'b10; outc = 1'b0; end
8'hfe: begin outa = 10'h012; outb = 2'b00; outc = 1'b0; end
8'hff: begin outa = 10'h114; outb = 2'b10; outc = 1'b1; end
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
wire [15:-16] sel2 = crc[31:0];
wire [80:-10] sel3 = {crc[26:0],crc};
wire [3:0] out21 = sel2[-3 : -6];
wire [3:0] out22 = sel2[{1'b0,crc[3:0]} - 16 +: 4];
wire [3:0] out23 = sel2[{1'b0,crc[3:0]} - 10 -: 4];
wire [3:0] out31 = sel3[-3 : -6];
wire [3:0] out32 = sel3[crc[5:0] - 6 +: 4];
wire [3:0] out33 = sel3[crc[5:0] - 6 -: 4];
// Aggregate outputs into a single result vector
wire [63:0] result = {40'h0, out21, out22, out23, out31, out32, out33};
reg [15:-16] sel1;
initial begin
// Path clearing
sel1 = 32'h12345678;
if (sel1 != 32'h12345678) $stop;
if (sel1[-13 : -16] != 4'h8) $stop;
if (sel1[3:0] != 4'h4) $stop;
if (sel1[4 +: 4] != 4'h3) $stop;
if (sel1[11 -: 4] != 4'h2) $stop;
end
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] sels=%x,%x,%x %x,%x,%x\n",$time, out21,out22,out23, out31,out32,out33);
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'hba7fe1e7ac128362
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
wire [15:-16] sel2 = crc[31:0];
wire [80:-10] sel3 = {crc[26:0],crc};
wire [3:0] out21 = sel2[-3 : -6];
wire [3:0] out22 = sel2[{1'b0,crc[3:0]} - 16 +: 4];
wire [3:0] out23 = sel2[{1'b0,crc[3:0]} - 10 -: 4];
wire [3:0] out31 = sel3[-3 : -6];
wire [3:0] out32 = sel3[crc[5:0] - 6 +: 4];
wire [3:0] out33 = sel3[crc[5:0] - 6 -: 4];
// Aggregate outputs into a single result vector
wire [63:0] result = {40'h0, out21, out22, out23, out31, out32, out33};
reg [15:-16] sel1;
initial begin
// Path clearing
sel1 = 32'h12345678;
if (sel1 != 32'h12345678) $stop;
if (sel1[-13 : -16] != 4'h8) $stop;
if (sel1[3:0] != 4'h4) $stop;
if (sel1[4 +: 4] != 4'h3) $stop;
if (sel1[11 -: 4] != 4'h2) $stop;
end
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] sels=%x,%x,%x %x,%x,%x\n",$time, out21,out22,out23, out31,out32,out33);
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'hba7fe1e7ac128362
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
wire [15:-16] sel2 = crc[31:0];
wire [80:-10] sel3 = {crc[26:0],crc};
wire [3:0] out21 = sel2[-3 : -6];
wire [3:0] out22 = sel2[{1'b0,crc[3:0]} - 16 +: 4];
wire [3:0] out23 = sel2[{1'b0,crc[3:0]} - 10 -: 4];
wire [3:0] out31 = sel3[-3 : -6];
wire [3:0] out32 = sel3[crc[5:0] - 6 +: 4];
wire [3:0] out33 = sel3[crc[5:0] - 6 -: 4];
// Aggregate outputs into a single result vector
wire [63:0] result = {40'h0, out21, out22, out23, out31, out32, out33};
reg [15:-16] sel1;
initial begin
// Path clearing
sel1 = 32'h12345678;
if (sel1 != 32'h12345678) $stop;
if (sel1[-13 : -16] != 4'h8) $stop;
if (sel1[3:0] != 4'h4) $stop;
if (sel1[4 +: 4] != 4'h3) $stop;
if (sel1[11 -: 4] != 4'h2) $stop;
end
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] sels=%x,%x,%x %x,%x,%x\n",$time, out21,out22,out23, out31,out32,out33);
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'hba7fe1e7ac128362
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [41:0] aaa;
wire [41:0] bbb;
// verilator public_module
wire [41:0] z_0;
wire [41:0] z_1;
wide w_0(
.xxx( { {40{1'b0}},2'b11 } ),
.yyy( aaa[1:0] ),
.zzz( z_0 )
);
wide w_1(
.xxx( aaa ),
.yyy( 2'b10 ),
.zzz( z_1 )
);
assign bbb= z_0 + z_1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
aaa <= 42'b01;
end
if (cyc==2) begin
aaa <= 42'b10;
if (z_0 != 42'h4) $stop;
if (z_1 != 42'h3) $stop;
end
if (cyc==3) begin
if (z_0 != 42'h5) $stop;
if (z_1 != 42'h4) $stop;
end
if (cyc==4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module wide (
input [41:0] xxx,
input [1:0] yyy,
output [41:0] zzz
);
// verilator public_module
assign zzz = xxx+ { {40{1'b0}},yyy };
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
typedef enum { EN_ZERO,
EN_ONE
} En_t;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Insure that we can declare a type with a function declaration
function enum integer {
EF_TRUE = 1,
EF_FALSE = 0 }
f_enum_inv ( input a);
f_enum_inv = a ? EF_FALSE : EF_TRUE;
endfunction
initial begin
if (f_enum_inv(1) != 0) $stop;
if (f_enum_inv(0) != 1) $stop;
end
En_t a, z;
sub sub (/*AUTOINST*/
// Outputs
.z (z),
// Inputs
.a (a));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a <= EN_ZERO;
end
if (cyc==2) begin
a <= EN_ONE;
if (z != EN_ONE) $stop;
end
if (cyc==3) begin
if (z != EN_ZERO) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module sub (input En_t a, output En_t z);
always @* z = (a==EN_ONE) ? EN_ZERO : EN_ONE;
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// End:
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer _mode;
reg _guard1;
reg [127:0] r_wide0;
reg _guard2;
wire [63:0] r_wide1;
reg _guard3;
reg _guard4;
reg _guard5;
reg _guard6;
assign r_wide1 = r_wide0[127:64];
// surefire lint_off STMINI
initial _mode = 0;
always @ (posedge clk) begin
if (_mode==0) begin
$write("[%0t] t_equal: Running\n", $time);
_guard1 <= 0;
_guard2 <= 0;
_guard3 <= 0;
_guard4 <= 0;
_guard5 <= 0;
_guard6 <= 0;
_mode<=1;
r_wide0 <= {32'h aa111111,32'hbb222222,32'hcc333333,32'hdd444444};
end
else if (_mode==1) begin
_mode<=2;
//
if (5'd10 != 5'b1010) $stop;
if (5'd10 != 5'd10) $stop;
if (5'd10 != 5'ha) $stop;
if (5'd10 != 5'o12) $stop;
if (5'd10 != 5'B 1010) $stop;
if (5'd10 != 5'D10) $stop;
if (5'd10 != 5'H a) $stop;
if (5'd10 != 5 'O 12) $stop;
//
if (r_wide0 !== {32'haa111111,32'hbb222222,32'hcc333333,32'hdd444444}) $stop;
if (r_wide1 !== {32'haa111111,32'hbb222222}) $stop;
if (|{_guard1,_guard2,_guard3,_guard4,_guard5,_guard6}) begin
$write("Guard error %x %x %x %x %x\n",_guard1,_guard2,_guard3,_guard4,_guard5);
$stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t;
real n0; initial n0 = 0.0;
real n1; initial n1 = 1.0;
real n2; initial n2 = 0.1;
real n3; initial n3 = 1.2345e-15;
real n4; initial n4 = 2.579e+15;
reg [7:0] r8; initial r8 = 3;
initial begin
// Display formatting
$display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n0,n0,n0,n0);
$display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n0,n0,n0,n0);
$display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n0,n0,n0,n0);
$display;
$display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n1,n1,n1,n1);
$display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n1,n1,n1,n1);
$display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n1,n1,n1,n1);
$display;
$display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n2,n2,n2,n2);
$display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n2,n2,n2,n2);
$display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n2,n2,n2,n2);
$display;
$display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n3,n3,n3,n3);
$display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n3,n3,n3,n3);
$display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n3,n3,n3,n3);
$display;
$display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n4,n4,n4,n4);
$display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n4,n4,n4,n4);
$display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n4,n4,n4,n4);
$display;
$display("r8=%d n1=%g n2=%g", r8, n1, n2);
$display("n1=%g n2=%g r8=%d", n1, n2, r8);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t;
real n0; initial n0 = 0.0;
real n1; initial n1 = 1.0;
real n2; initial n2 = 0.1;
real n3; initial n3 = 1.2345e-15;
real n4; initial n4 = 2.579e+15;
reg [7:0] r8; initial r8 = 3;
initial begin
// Display formatting
$display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n0,n0,n0,n0);
$display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n0,n0,n0,n0);
$display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n0,n0,n0,n0);
$display;
$display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n1,n1,n1,n1);
$display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n1,n1,n1,n1);
$display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n1,n1,n1,n1);
$display;
$display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n2,n2,n2,n2);
$display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n2,n2,n2,n2);
$display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n2,n2,n2,n2);
$display;
$display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n3,n3,n3,n3);
$display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n3,n3,n3,n3);
$display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n3,n3,n3,n3);
$display;
$display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n4,n4,n4,n4);
$display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n4,n4,n4,n4);
$display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n4,n4,n4,n4);
$display;
$display("r8=%d n1=%g n2=%g", r8, n1, n2);
$display("n1=%g n2=%g r8=%d", n1, n2, r8);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t;
real n0; initial n0 = 0.0;
real n1; initial n1 = 1.0;
real n2; initial n2 = 0.1;
real n3; initial n3 = 1.2345e-15;
real n4; initial n4 = 2.579e+15;
reg [7:0] r8; initial r8 = 3;
initial begin
// Display formatting
$display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n0,n0,n0,n0);
$display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n0,n0,n0,n0);
$display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n0,n0,n0,n0);
$display;
$display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n1,n1,n1,n1);
$display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n1,n1,n1,n1);
$display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n1,n1,n1,n1);
$display;
$display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n2,n2,n2,n2);
$display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n2,n2,n2,n2);
$display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n2,n2,n2,n2);
$display;
$display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n3,n3,n3,n3);
$display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n3,n3,n3,n3);
$display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n3,n3,n3,n3);
$display;
$display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n4,n4,n4,n4);
$display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n4,n4,n4,n4);
$display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n4,n4,n4,n4);
$display;
$display("r8=%d n1=%g n2=%g", r8, n1, n2);
$display("n1=%g n2=%g r8=%d", n1, n2, r8);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [255:0] i;
wire [255:0] q;
assign q = {
i[176],i[168],i[126],i[177],i[097],i[123],i[231],i[039],
i[156],i[026],i[001],i[052],i[005],i[240],i[157],i[048],
i[111],i[088],i[133],i[225],i[046],i[038],i[004],i[234],
i[115],i[008],i[069],i[099],i[137],i[130],i[255],i[122],
i[223],i[195],i[224],i[083],i[094],i[018],i[067],i[034],
i[221],i[105],i[104],i[107],i[053],i[066],i[020],i[174],
i[010],i[196],i[003],i[041],i[071],i[194],i[154],i[110],
i[186],i[210],i[040],i[044],i[243],i[236],i[239],i[183],
i[164],i[064],i[086],i[193],i[055],i[206],i[203],i[128],
i[190],i[233],i[023],i[022],i[135],i[108],i[061],i[139],
i[180],i[043],i[109],i[090],i[229],i[238],i[095],i[173],
i[208],i[054],i[025],i[024],i[148],i[079],i[246],i[142],
i[181],i[129],i[120],i[220],i[036],i[159],i[201],i[119],
i[216],i[152],i[175],i[138],i[242],i[143],i[101],i[035],
i[228],i[082],i[211],i[062],i[076],i[124],i[150],i[149],
i[235],i[227],i[250],i[134],i[068],i[032],i[060],i[144],
i[042],i[163],i[087],i[059],i[213],i[251],i[200],i[070],
i[145],i[204],i[249],i[191],i[127],i[247],i[106],i[017],
i[028],i[045],i[215],i[162],i[205],i[073],i[065],i[084],
i[153],i[158],i[085],i[197],i[212],i[114],i[096],i[118],
i[146],i[030],i[058],i[230],i[141],i[000],i[199],i[171],
i[182],i[185],i[021],i[016],i[033],i[237],i[015],i[112],
i[222],i[253],i[244],i[031],i[248],i[092],i[226],i[179],
i[189],i[056],i[132],i[116],i[072],i[184],i[027],i[002],
i[103],i[125],i[009],i[078],i[178],i[245],i[170],i[161],
i[102],i[047],i[192],i[012],i[057],i[207],i[187],i[151],
i[218],i[254],i[214],i[037],i[131],i[165],i[011],i[098],
i[169],i[209],i[167],i[202],i[100],i[172],i[147],i[013],
i[136],i[166],i[252],i[077],i[051],i[074],i[140],i[050],
i[217],i[198],i[081],i[091],i[075],i[121],i[188],i[219],
i[160],i[241],i[080],i[155],i[019],i[006],i[014],i[029],
i[089],i[049],i[113],i[232],i[007],i[117],i[063],i[093]
};
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("%x %x\n", q, i);
`endif
if (cyc==1) begin
i <= 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26;
end
if (cyc==2) begin
i <= 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8;
if (q != 256'h697bad4b0cf2d7fa4ad22809293710bb67d1eb3131e8eb2135f2c7bd820baa84) $stop;
end
if (cyc==3) begin
if (q != 256'h320eda5078b3e942353d16dddc8b29fd773b4fcec8323612dadfb1fa483f602c) $stop;
end
if (cyc==4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
// surefire lint_off _NETNM
// surefire lint_off STMINI
input clk;
integer _mode; initial _mode = 0;
wire [2:0] b3; reg [2:0] g3;
wire [5:0] b6; reg [5:0] g6;
t_func_grey2bin #(3) g2b3 (.b(b3), .g(g3));
t_func_grey2bin #(6) g2b6 (.b(b6), .g(g6));
always @ (posedge clk) begin
if (_mode==0) begin
_mode <= 1;
g3 <= 3'b101;
g6 <= 6'b110101;
end
else if (_mode==1) begin
if (b3 !== 3'b110) $stop;
if (b6 !== 6'b100110) $stop;
_mode <= 2;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
// Module gray2bin
// convert an arbitrary width gray coded number to binary. The conversion
// of a 4 bit gray (represented as "g") to binary ("b") would go as follows:
// b[3] = ^g[3] = g[3]
// b[2] = ^g[3:2]
// b[1] = ^g[3:1]
// b[0] = ^g[3:[SZ-1:0] cur0]
module t_func_grey2bin (/*AUTOARG*/
// Outputs
b,
// Inputs
g
);
// surefire lint_off STMFOR
parameter SZ = 5;
output [SZ-1:0] b;
input [SZ-1:0] g;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [SZ-1:0] b;
// End of automatics
integer i;
always @(/*AUTOSENSE*/g)
for (i=0; i<SZ; i=i+1)
b[i] = ^(g >> i); // surefire lint_off_line LATASS
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
// surefire lint_off _NETNM
// surefire lint_off STMINI
input clk;
integer _mode; initial _mode = 0;
wire [2:0] b3; reg [2:0] g3;
wire [5:0] b6; reg [5:0] g6;
t_func_grey2bin #(3) g2b3 (.b(b3), .g(g3));
t_func_grey2bin #(6) g2b6 (.b(b6), .g(g6));
always @ (posedge clk) begin
if (_mode==0) begin
_mode <= 1;
g3 <= 3'b101;
g6 <= 6'b110101;
end
else if (_mode==1) begin
if (b3 !== 3'b110) $stop;
if (b6 !== 6'b100110) $stop;
_mode <= 2;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
// Module gray2bin
// convert an arbitrary width gray coded number to binary. The conversion
// of a 4 bit gray (represented as "g") to binary ("b") would go as follows:
// b[3] = ^g[3] = g[3]
// b[2] = ^g[3:2]
// b[1] = ^g[3:1]
// b[0] = ^g[3:[SZ-1:0] cur0]
module t_func_grey2bin (/*AUTOARG*/
// Outputs
b,
// Inputs
g
);
// surefire lint_off STMFOR
parameter SZ = 5;
output [SZ-1:0] b;
input [SZ-1:0] g;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [SZ-1:0] b;
// End of automatics
integer i;
always @(/*AUTOSENSE*/g)
for (i=0; i<SZ; i=i+1)
b[i] = ^(g >> i); // surefire lint_off_line LATASS
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
parameter DW = 4;
wire [3:0] drv_a = crc[3:0];
wire [3:0] drv_b = crc[7:4];
wire [3:0] drv_e = crc[19:16];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [DW-1:0] drv; // To/From test1 of Test1.v
wire [DW-1:0] drv2; // From test2 of Test2.v
// End of automatics
Test1 test1 (/*AUTOINST*/
// Inouts
.drv (drv[DW-1:0]),
// Inputs
.drv_a (drv_a[DW-1:0]),
.drv_b (drv_b[DW-1:0]),
.drv_e (drv_e[DW-1:0]));
Test2 test2 (/*AUTOINST*/
// Outputs
.drv2 (drv2[DW-1:0]),
// Inputs
.drv_a (drv_a[DW-1:0]),
.drv_b (drv_b[DW-1:0]),
.drv_e (drv_e[DW-1:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {60'h0, drv};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x drv=%x %x (%b??%b:%b)\n",$time, cyc, crc, drv, drv2, drv_e,drv_a,drv_b);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
if (drv2 != drv) $stop;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hd95d216c5a2945d0
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test1 #(
parameter DW = 4
)(
input wire [DW-1:0] drv_a,
input wire [DW-1:0] drv_b,
input wire [DW-1:0] drv_e,
inout wire [DW-1:0] drv
);
wire drv_0, drv_1, drv_2, drv_3;
bufif1 bufa0 (drv_0, drv_a[0], drv_e[0]);
bufif1 bufb0 (drv_0, drv_b[0], ~drv_e[0]);
bufif1 bufa1 (drv_1, drv_a[1], drv_e[1]);
bufif1 bufb1 (drv_1, drv_b[1], ~drv_e[1]);
bufif1 bufa2 (drv_2, drv_a[2], drv_e[2]);
bufif1 bufb2 (drv_2, drv_b[2], ~drv_e[2]);
bufif1 bufa3 (drv_3, drv_a[3], drv_e[3]);
bufif1 bufb3 (drv_3, drv_b[3], ~drv_e[3]);
assign drv = {drv_3,drv_2,drv_1,drv_0};
endmodule
module Test2 #(
parameter DW = 4
)(
input wire [DW-1:0] drv_a,
input wire [DW-1:0] drv_b,
input wire [DW-1:0] drv_e,
inout wire [DW-1:0] drv2
);
wire [DW-1:0] drv_all;
bufif1 bufa [DW-1:0] (drv_all, drv_a, drv_e);
// Below ~= bufif1 bufb [DW-1:0] (drv_all, drv_b, ~drv_e);
bufif1 bufb [DW-1:0] ({drv_all[3], drv_all[2], drv_all[1], drv_all[0]},
{drv_b[3], drv_b[2], drv_b[1], drv_b[0]},
{~drv_e[3], ~drv_e[2], ~drv_e[1], ~drv_e[0]});
assign drv2 = drv_all;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
parameter DW = 4;
wire [3:0] drv_a = crc[3:0];
wire [3:0] drv_b = crc[7:4];
wire [3:0] drv_e = crc[19:16];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [DW-1:0] drv; // To/From test1 of Test1.v
wire [DW-1:0] drv2; // From test2 of Test2.v
// End of automatics
Test1 test1 (/*AUTOINST*/
// Inouts
.drv (drv[DW-1:0]),
// Inputs
.drv_a (drv_a[DW-1:0]),
.drv_b (drv_b[DW-1:0]),
.drv_e (drv_e[DW-1:0]));
Test2 test2 (/*AUTOINST*/
// Outputs
.drv2 (drv2[DW-1:0]),
// Inputs
.drv_a (drv_a[DW-1:0]),
.drv_b (drv_b[DW-1:0]),
.drv_e (drv_e[DW-1:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {60'h0, drv};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x drv=%x %x (%b??%b:%b)\n",$time, cyc, crc, drv, drv2, drv_e,drv_a,drv_b);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
if (drv2 != drv) $stop;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hd95d216c5a2945d0
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test1 #(
parameter DW = 4
)(
input wire [DW-1:0] drv_a,
input wire [DW-1:0] drv_b,
input wire [DW-1:0] drv_e,
inout wire [DW-1:0] drv
);
wire drv_0, drv_1, drv_2, drv_3;
bufif1 bufa0 (drv_0, drv_a[0], drv_e[0]);
bufif1 bufb0 (drv_0, drv_b[0], ~drv_e[0]);
bufif1 bufa1 (drv_1, drv_a[1], drv_e[1]);
bufif1 bufb1 (drv_1, drv_b[1], ~drv_e[1]);
bufif1 bufa2 (drv_2, drv_a[2], drv_e[2]);
bufif1 bufb2 (drv_2, drv_b[2], ~drv_e[2]);
bufif1 bufa3 (drv_3, drv_a[3], drv_e[3]);
bufif1 bufb3 (drv_3, drv_b[3], ~drv_e[3]);
assign drv = {drv_3,drv_2,drv_1,drv_0};
endmodule
module Test2 #(
parameter DW = 4
)(
input wire [DW-1:0] drv_a,
input wire [DW-1:0] drv_b,
input wire [DW-1:0] drv_e,
inout wire [DW-1:0] drv2
);
wire [DW-1:0] drv_all;
bufif1 bufa [DW-1:0] (drv_all, drv_a, drv_e);
// Below ~= bufif1 bufb [DW-1:0] (drv_all, drv_b, ~drv_e);
bufif1 bufb [DW-1:0] ({drv_all[3], drv_all[2], drv_all[1], drv_all[0]},
{drv_b[3], drv_b[2], drv_b[1], drv_b[0]},
{~drv_e[3], ~drv_e[2], ~drv_e[1], ~drv_e[0]});
assign drv2 = drv_all;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
parameter DW = 4;
wire [3:0] drv_a = crc[3:0];
wire [3:0] drv_b = crc[7:4];
wire [3:0] drv_e = crc[19:16];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [DW-1:0] drv; // To/From test1 of Test1.v
wire [DW-1:0] drv2; // From test2 of Test2.v
// End of automatics
Test1 test1 (/*AUTOINST*/
// Inouts
.drv (drv[DW-1:0]),
// Inputs
.drv_a (drv_a[DW-1:0]),
.drv_b (drv_b[DW-1:0]),
.drv_e (drv_e[DW-1:0]));
Test2 test2 (/*AUTOINST*/
// Outputs
.drv2 (drv2[DW-1:0]),
// Inputs
.drv_a (drv_a[DW-1:0]),
.drv_b (drv_b[DW-1:0]),
.drv_e (drv_e[DW-1:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {60'h0, drv};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x drv=%x %x (%b??%b:%b)\n",$time, cyc, crc, drv, drv2, drv_e,drv_a,drv_b);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
if (drv2 != drv) $stop;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hd95d216c5a2945d0
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test1 #(
parameter DW = 4
)(
input wire [DW-1:0] drv_a,
input wire [DW-1:0] drv_b,
input wire [DW-1:0] drv_e,
inout wire [DW-1:0] drv
);
wire drv_0, drv_1, drv_2, drv_3;
bufif1 bufa0 (drv_0, drv_a[0], drv_e[0]);
bufif1 bufb0 (drv_0, drv_b[0], ~drv_e[0]);
bufif1 bufa1 (drv_1, drv_a[1], drv_e[1]);
bufif1 bufb1 (drv_1, drv_b[1], ~drv_e[1]);
bufif1 bufa2 (drv_2, drv_a[2], drv_e[2]);
bufif1 bufb2 (drv_2, drv_b[2], ~drv_e[2]);
bufif1 bufa3 (drv_3, drv_a[3], drv_e[3]);
bufif1 bufb3 (drv_3, drv_b[3], ~drv_e[3]);
assign drv = {drv_3,drv_2,drv_1,drv_0};
endmodule
module Test2 #(
parameter DW = 4
)(
input wire [DW-1:0] drv_a,
input wire [DW-1:0] drv_b,
input wire [DW-1:0] drv_e,
inout wire [DW-1:0] drv2
);
wire [DW-1:0] drv_all;
bufif1 bufa [DW-1:0] (drv_all, drv_a, drv_e);
// Below ~= bufif1 bufb [DW-1:0] (drv_all, drv_b, ~drv_e);
bufif1 bufb [DW-1:0] ({drv_all[3], drv_all[2], drv_all[1], drv_all[0]},
{drv_b[3], drv_b[2], drv_b[1], drv_b[0]},
{~drv_e[3], ~drv_e[2], ~drv_e[1], ~drv_e[0]});
assign drv2 = drv_all;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
parameter DW = 4;
wire [3:0] drv_a = crc[3:0];
wire [3:0] drv_b = crc[7:4];
wire [3:0] drv_e = crc[19:16];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [DW-1:0] drv; // To/From test1 of Test1.v
wire [DW-1:0] drv2; // From test2 of Test2.v
// End of automatics
Test1 test1 (/*AUTOINST*/
// Inouts
.drv (drv[DW-1:0]),
// Inputs
.drv_a (drv_a[DW-1:0]),
.drv_b (drv_b[DW-1:0]),
.drv_e (drv_e[DW-1:0]));
Test2 test2 (/*AUTOINST*/
// Outputs
.drv2 (drv2[DW-1:0]),
// Inputs
.drv_a (drv_a[DW-1:0]),
.drv_b (drv_b[DW-1:0]),
.drv_e (drv_e[DW-1:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {60'h0, drv};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x drv=%x %x (%b??%b:%b)\n",$time, cyc, crc, drv, drv2, drv_e,drv_a,drv_b);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
if (drv2 != drv) $stop;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hd95d216c5a2945d0
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test1 #(
parameter DW = 4
)(
input wire [DW-1:0] drv_a,
input wire [DW-1:0] drv_b,
input wire [DW-1:0] drv_e,
inout wire [DW-1:0] drv
);
wire drv_0, drv_1, drv_2, drv_3;
bufif1 bufa0 (drv_0, drv_a[0], drv_e[0]);
bufif1 bufb0 (drv_0, drv_b[0], ~drv_e[0]);
bufif1 bufa1 (drv_1, drv_a[1], drv_e[1]);
bufif1 bufb1 (drv_1, drv_b[1], ~drv_e[1]);
bufif1 bufa2 (drv_2, drv_a[2], drv_e[2]);
bufif1 bufb2 (drv_2, drv_b[2], ~drv_e[2]);
bufif1 bufa3 (drv_3, drv_a[3], drv_e[3]);
bufif1 bufb3 (drv_3, drv_b[3], ~drv_e[3]);
assign drv = {drv_3,drv_2,drv_1,drv_0};
endmodule
module Test2 #(
parameter DW = 4
)(
input wire [DW-1:0] drv_a,
input wire [DW-1:0] drv_b,
input wire [DW-1:0] drv_e,
inout wire [DW-1:0] drv2
);
wire [DW-1:0] drv_all;
bufif1 bufa [DW-1:0] (drv_all, drv_a, drv_e);
// Below ~= bufif1 bufb [DW-1:0] (drv_all, drv_b, ~drv_e);
bufif1 bufb [DW-1:0] ({drv_all[3], drv_all[2], drv_all[1], drv_all[0]},
{drv_b[3], drv_b[2], drv_b[1], drv_b[0]},
{~drv_e[3], ~drv_e[2], ~drv_e[1], ~drv_e[0]});
assign drv2 = drv_all;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
parameter DW = 4;
wire [3:0] drv_a = crc[3:0];
wire [3:0] drv_b = crc[7:4];
wire [3:0] drv_e = crc[19:16];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [DW-1:0] drv; // To/From test1 of Test1.v
wire [DW-1:0] drv2; // From test2 of Test2.v
// End of automatics
Test1 test1 (/*AUTOINST*/
// Inouts
.drv (drv[DW-1:0]),
// Inputs
.drv_a (drv_a[DW-1:0]),
.drv_b (drv_b[DW-1:0]),
.drv_e (drv_e[DW-1:0]));
Test2 test2 (/*AUTOINST*/
// Outputs
.drv2 (drv2[DW-1:0]),
// Inputs
.drv_a (drv_a[DW-1:0]),
.drv_b (drv_b[DW-1:0]),
.drv_e (drv_e[DW-1:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {60'h0, drv};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x drv=%x %x (%b??%b:%b)\n",$time, cyc, crc, drv, drv2, drv_e,drv_a,drv_b);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
if (drv2 != drv) $stop;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hd95d216c5a2945d0
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test1 #(
parameter DW = 4
)(
input wire [DW-1:0] drv_a,
input wire [DW-1:0] drv_b,
input wire [DW-1:0] drv_e,
inout wire [DW-1:0] drv
);
wire drv_0, drv_1, drv_2, drv_3;
bufif1 bufa0 (drv_0, drv_a[0], drv_e[0]);
bufif1 bufb0 (drv_0, drv_b[0], ~drv_e[0]);
bufif1 bufa1 (drv_1, drv_a[1], drv_e[1]);
bufif1 bufb1 (drv_1, drv_b[1], ~drv_e[1]);
bufif1 bufa2 (drv_2, drv_a[2], drv_e[2]);
bufif1 bufb2 (drv_2, drv_b[2], ~drv_e[2]);
bufif1 bufa3 (drv_3, drv_a[3], drv_e[3]);
bufif1 bufb3 (drv_3, drv_b[3], ~drv_e[3]);
assign drv = {drv_3,drv_2,drv_1,drv_0};
endmodule
module Test2 #(
parameter DW = 4
)(
input wire [DW-1:0] drv_a,
input wire [DW-1:0] drv_b,
input wire [DW-1:0] drv_e,
inout wire [DW-1:0] drv2
);
wire [DW-1:0] drv_all;
bufif1 bufa [DW-1:0] (drv_all, drv_a, drv_e);
// Below ~= bufif1 bufb [DW-1:0] (drv_all, drv_b, ~drv_e);
bufif1 bufb [DW-1:0] ({drv_all[3], drv_all[2], drv_all[1], drv_all[0]},
{drv_b[3], drv_b[2], drv_b[1], drv_b[0]},
{~drv_e[3], ~drv_e[2], ~drv_e[1], ~drv_e[0]});
assign drv2 = drv_all;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer j;
integer hit_count;
reg [63:0] cam_lookup_hit_vector;
strings strings ();
task show;
input [8*8-1:0] str;
reg [7:0] char;
integer loc;
begin
$write("[%0t] ",$time);
strings.stringStart(8*8-1);
for (char = strings.stringByte(str); !strings.isNull(char); char = strings.stringByte(str)) begin
$write("%c",char);
end
$write("\n");
end
endtask
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
show("hello\000xx");
end
if (cyc==2) begin
show("world\000xx");
end
if (cyc==4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module strings;
// **NOT** reentrant, just a test!
integer index;
task stringStart;
input [31:0] bits;
begin
index = (bits-1)/8;
end
endtask
function isNull;
input [7:0] chr;
isNull = (chr == 8'h0);
endfunction
function [7:0] stringByte;
input [8*8-1:0] str;
begin
if (index<=0) stringByte=8'h0;
else stringByte = str[index*8 +: 8];
index = index - 1;
end
endfunction
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [15:0] m_din;
// OK
reg [15:0] c_split_1, c_split_2, c_split_3, c_split_4, c_split_5;
always @ (posedge clk) begin
if (cyc==0) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
c_split_1 <= 16'h0;
c_split_2 <= 16'h0;
c_split_3 <= 16'h0;
c_split_4 <= 0;
c_split_5 <= 0;
// End of automatics
end
else begin
c_split_1 <= m_din;
c_split_2 <= c_split_1;
c_split_3 <= c_split_2 & {16{(cyc!=0)}};
if (cyc==1) begin
c_split_4 <= 16'h4;
c_split_5 <= 16'h5;
end
else begin
c_split_4 <= c_split_3;
c_split_5 <= c_split_4;
end
end
end
// OK
reg [15:0] d_split_1, d_split_2;
always @ (posedge clk) begin
if (cyc==0) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
d_split_1 <= 16'h0;
d_split_2 <= 16'h0;
// End of automatics
end
else begin
d_split_1 <= m_din;
d_split_2 <= d_split_1;
d_split_1 <= ~m_din;
end
end
// Not OK
always @ (posedge clk) begin
if (cyc==0) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
// End of automatics
end
else begin
$write(" foo %x", m_din);
$write(" bar %x\n", m_din);
end
end
// Not OK
reg [15:0] e_split_1, e_split_2;
always @ (posedge clk) begin
if (cyc==0) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
e_split_1 = 16'h0;
e_split_2 = 16'h0;
// End of automatics
end
else begin
e_split_1 = m_din;
e_split_2 = e_split_1;
end
end
// Not OK
reg [15:0] f_split_1, f_split_2;
always @ (posedge clk) begin
if (cyc==0) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
f_split_1 = 16'h0;
f_split_2 = 16'h0;
// End of automatics
end
else begin
f_split_2 = f_split_1;
f_split_1 = m_din;
end
end
always @ (posedge clk) begin
if (cyc!=0) begin
//$write(" C %d %x %x\n", cyc, c_split_1, c_split_2);
cyc<=cyc+1;
if (cyc==1) begin
m_din <= 16'hfeed;
end
if (cyc==3) begin
end
if (cyc==4) begin
m_din <= 16'he11e;
if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop;
if (!(e_split_1==16'hfeed && e_split_2==16'hfeed)) $stop;
if (!(f_split_1==16'hfeed && f_split_2==16'hfeed)) $stop;
end
if (cyc==5) begin
m_din <= 16'he22e;
if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop;
// Two valid orderings, as we don't know which posedge clk gets evaled first
if (!(e_split_1==16'hfeed && e_split_2==16'hfeed) && !(e_split_1==16'he11e && e_split_2==16'he11e)) $stop;
if (!(f_split_1==16'hfeed && f_split_2==16'hfeed) && !(f_split_1==16'he11e && f_split_2==16'hfeed)) $stop;
end
if (cyc==6) begin
m_din <= 16'he33e;
if (!(c_split_1==16'he11e && c_split_2==16'hfeed && c_split_3==16'hfeed)) $stop;
if (!(d_split_1==16'h1ee1 && d_split_2==16'h0112)) $stop;
// Two valid orderings, as we don't know which posedge clk gets evaled first
if (!(e_split_1==16'he11e && e_split_2==16'he11e) && !(e_split_1==16'he22e && e_split_2==16'he22e)) $stop;
if (!(f_split_1==16'he11e && f_split_2==16'hfeed) && !(f_split_1==16'he22e && f_split_2==16'he11e)) $stop;
end
if (cyc==7) begin
m_din <= 16'he44e;
if (!(c_split_1==16'he22e && c_split_2==16'he11e && c_split_3==16'hfeed)) $stop;
end
if (cyc==8) begin
m_din <= 16'he55e;
if (!(c_split_1==16'he33e && c_split_2==16'he22e && c_split_3==16'he11e
&& c_split_4==16'hfeed && c_split_5==16'hfeed)) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [15:0] m_din;
// OK
reg [15:0] c_split_1, c_split_2, c_split_3, c_split_4, c_split_5;
always @ (posedge clk) begin
if (cyc==0) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
c_split_1 <= 16'h0;
c_split_2 <= 16'h0;
c_split_3 <= 16'h0;
c_split_4 <= 0;
c_split_5 <= 0;
// End of automatics
end
else begin
c_split_1 <= m_din;
c_split_2 <= c_split_1;
c_split_3 <= c_split_2 & {16{(cyc!=0)}};
if (cyc==1) begin
c_split_4 <= 16'h4;
c_split_5 <= 16'h5;
end
else begin
c_split_4 <= c_split_3;
c_split_5 <= c_split_4;
end
end
end
// OK
reg [15:0] d_split_1, d_split_2;
always @ (posedge clk) begin
if (cyc==0) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
d_split_1 <= 16'h0;
d_split_2 <= 16'h0;
// End of automatics
end
else begin
d_split_1 <= m_din;
d_split_2 <= d_split_1;
d_split_1 <= ~m_din;
end
end
// Not OK
always @ (posedge clk) begin
if (cyc==0) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
// End of automatics
end
else begin
$write(" foo %x", m_din);
$write(" bar %x\n", m_din);
end
end
// Not OK
reg [15:0] e_split_1, e_split_2;
always @ (posedge clk) begin
if (cyc==0) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
e_split_1 = 16'h0;
e_split_2 = 16'h0;
// End of automatics
end
else begin
e_split_1 = m_din;
e_split_2 = e_split_1;
end
end
// Not OK
reg [15:0] f_split_1, f_split_2;
always @ (posedge clk) begin
if (cyc==0) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
f_split_1 = 16'h0;
f_split_2 = 16'h0;
// End of automatics
end
else begin
f_split_2 = f_split_1;
f_split_1 = m_din;
end
end
always @ (posedge clk) begin
if (cyc!=0) begin
//$write(" C %d %x %x\n", cyc, c_split_1, c_split_2);
cyc<=cyc+1;
if (cyc==1) begin
m_din <= 16'hfeed;
end
if (cyc==3) begin
end
if (cyc==4) begin
m_din <= 16'he11e;
if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop;
if (!(e_split_1==16'hfeed && e_split_2==16'hfeed)) $stop;
if (!(f_split_1==16'hfeed && f_split_2==16'hfeed)) $stop;
end
if (cyc==5) begin
m_din <= 16'he22e;
if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop;
// Two valid orderings, as we don't know which posedge clk gets evaled first
if (!(e_split_1==16'hfeed && e_split_2==16'hfeed) && !(e_split_1==16'he11e && e_split_2==16'he11e)) $stop;
if (!(f_split_1==16'hfeed && f_split_2==16'hfeed) && !(f_split_1==16'he11e && f_split_2==16'hfeed)) $stop;
end
if (cyc==6) begin
m_din <= 16'he33e;
if (!(c_split_1==16'he11e && c_split_2==16'hfeed && c_split_3==16'hfeed)) $stop;
if (!(d_split_1==16'h1ee1 && d_split_2==16'h0112)) $stop;
// Two valid orderings, as we don't know which posedge clk gets evaled first
if (!(e_split_1==16'he11e && e_split_2==16'he11e) && !(e_split_1==16'he22e && e_split_2==16'he22e)) $stop;
if (!(f_split_1==16'he11e && f_split_2==16'hfeed) && !(f_split_1==16'he22e && f_split_2==16'he11e)) $stop;
end
if (cyc==7) begin
m_din <= 16'he44e;
if (!(c_split_1==16'he22e && c_split_2==16'he11e && c_split_3==16'hfeed)) $stop;
end
if (cyc==8) begin
m_din <= 16'he55e;
if (!(c_split_1==16'he33e && c_split_2==16'he22e && c_split_3==16'he11e
&& c_split_4==16'hfeed && c_split_5==16'hfeed)) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [15:0] m_din;
// OK
reg [15:0] c_split_1, c_split_2, c_split_3, c_split_4, c_split_5;
always @ (posedge clk) begin
if (cyc==0) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
c_split_1 <= 16'h0;
c_split_2 <= 16'h0;
c_split_3 <= 16'h0;
c_split_4 <= 0;
c_split_5 <= 0;
// End of automatics
end
else begin
c_split_1 <= m_din;
c_split_2 <= c_split_1;
c_split_3 <= c_split_2 & {16{(cyc!=0)}};
if (cyc==1) begin
c_split_4 <= 16'h4;
c_split_5 <= 16'h5;
end
else begin
c_split_4 <= c_split_3;
c_split_5 <= c_split_4;
end
end
end
// OK
reg [15:0] d_split_1, d_split_2;
always @ (posedge clk) begin
if (cyc==0) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
d_split_1 <= 16'h0;
d_split_2 <= 16'h0;
// End of automatics
end
else begin
d_split_1 <= m_din;
d_split_2 <= d_split_1;
d_split_1 <= ~m_din;
end
end
// Not OK
always @ (posedge clk) begin
if (cyc==0) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
// End of automatics
end
else begin
$write(" foo %x", m_din);
$write(" bar %x\n", m_din);
end
end
// Not OK
reg [15:0] e_split_1, e_split_2;
always @ (posedge clk) begin
if (cyc==0) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
e_split_1 = 16'h0;
e_split_2 = 16'h0;
// End of automatics
end
else begin
e_split_1 = m_din;
e_split_2 = e_split_1;
end
end
// Not OK
reg [15:0] f_split_1, f_split_2;
always @ (posedge clk) begin
if (cyc==0) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
f_split_1 = 16'h0;
f_split_2 = 16'h0;
// End of automatics
end
else begin
f_split_2 = f_split_1;
f_split_1 = m_din;
end
end
always @ (posedge clk) begin
if (cyc!=0) begin
//$write(" C %d %x %x\n", cyc, c_split_1, c_split_2);
cyc<=cyc+1;
if (cyc==1) begin
m_din <= 16'hfeed;
end
if (cyc==3) begin
end
if (cyc==4) begin
m_din <= 16'he11e;
if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop;
if (!(e_split_1==16'hfeed && e_split_2==16'hfeed)) $stop;
if (!(f_split_1==16'hfeed && f_split_2==16'hfeed)) $stop;
end
if (cyc==5) begin
m_din <= 16'he22e;
if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop;
// Two valid orderings, as we don't know which posedge clk gets evaled first
if (!(e_split_1==16'hfeed && e_split_2==16'hfeed) && !(e_split_1==16'he11e && e_split_2==16'he11e)) $stop;
if (!(f_split_1==16'hfeed && f_split_2==16'hfeed) && !(f_split_1==16'he11e && f_split_2==16'hfeed)) $stop;
end
if (cyc==6) begin
m_din <= 16'he33e;
if (!(c_split_1==16'he11e && c_split_2==16'hfeed && c_split_3==16'hfeed)) $stop;
if (!(d_split_1==16'h1ee1 && d_split_2==16'h0112)) $stop;
// Two valid orderings, as we don't know which posedge clk gets evaled first
if (!(e_split_1==16'he11e && e_split_2==16'he11e) && !(e_split_1==16'he22e && e_split_2==16'he22e)) $stop;
if (!(f_split_1==16'he11e && f_split_2==16'hfeed) && !(f_split_1==16'he22e && f_split_2==16'he11e)) $stop;
end
if (cyc==7) begin
m_din <= 16'he44e;
if (!(c_split_1==16'he22e && c_split_2==16'he11e && c_split_3==16'hfeed)) $stop;
end
if (cyc==8) begin
m_din <= 16'he55e;
if (!(c_split_1==16'he33e && c_split_2==16'he22e && c_split_3==16'he11e
&& c_split_4==16'hfeed && c_split_5==16'hfeed)) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
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