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//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_niosII_core_cpu_debug_slave_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_niosII_core_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_niosII_core_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Response Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Response Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Response Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Response Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Response Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Response Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Response Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/17/2016 05:20:59 PM
// Design Name:
// Module Name: Priority_Codec_32
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Priority_Codec_32(
input wire [25:0] Data_Dec_i,
output reg [4:0] Data_Bin_o
);
always @(Data_Dec_i)
begin
if(~Data_Dec_i[25]) begin Data_Bin_o = 5'b00000;//0
end else if(~Data_Dec_i[24]) begin Data_Bin_o = 5'b00001;//1
end else if(~Data_Dec_i[23]) begin Data_Bin_o = 5'b00010;//2
end else if(~Data_Dec_i[22]) begin Data_Bin_o = 5'b00011;//3
end else if(~Data_Dec_i[21]) begin Data_Bin_o = 5'b00100;//4
end else if(~Data_Dec_i[20]) begin Data_Bin_o = 5'b00101;//5
end else if(~Data_Dec_i[19]) begin Data_Bin_o = 5'b00110;//6
end else if(~Data_Dec_i[18]) begin Data_Bin_o = 5'b00111;//7
end else if(~Data_Dec_i[17]) begin Data_Bin_o = 5'b01000;//8
end else if(~Data_Dec_i[16]) begin Data_Bin_o = 5'b01001;//9
end else if(~Data_Dec_i[15]) begin Data_Bin_o = 5'b01010;//10
end else if(~Data_Dec_i[14]) begin Data_Bin_o = 5'b01011;//11
end else if(~Data_Dec_i[13]) begin Data_Bin_o = 5'b01100;//12
end else if(~Data_Dec_i[12]) begin Data_Bin_o = 5'b01101;//13
end else if(~Data_Dec_i[11]) begin Data_Bin_o = 5'b01110;//14
end else if(~Data_Dec_i[10]) begin Data_Bin_o = 5'b01111;//15
end else if(~Data_Dec_i[9]) begin Data_Bin_o = 5'b10000;//16
end else if(~Data_Dec_i[8]) begin Data_Bin_o = 5'b10001;//17
end else if(~Data_Dec_i[7]) begin Data_Bin_o = 5'b10010;//18
end else if(~Data_Dec_i[6]) begin Data_Bin_o = 5'b10011;//19
end else if(~Data_Dec_i[5]) begin Data_Bin_o = 5'b10100;//20
end else if(~Data_Dec_i[4]) begin Data_Bin_o = 5'b10101;//21
end else if(~Data_Dec_i[3]) begin Data_Bin_o = 5'b10110;//22
end else if(~Data_Dec_i[2]) begin Data_Bin_o = 5'b10111;//23
end else if(~Data_Dec_i[1]) begin Data_Bin_o = 5'b11000;//24
end else if(~Data_Dec_i[0]) begin Data_Bin_o = 5'b10101;//25
end
else Data_Bin_o = 5'b00000;//zero value
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/17/2016 05:20:59 PM
// Design Name:
// Module Name: Priority_Codec_32
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Priority_Codec_32(
input wire [25:0] Data_Dec_i,
output reg [4:0] Data_Bin_o
);
always @(Data_Dec_i)
begin
if(~Data_Dec_i[25]) begin Data_Bin_o = 5'b00000;//0
end else if(~Data_Dec_i[24]) begin Data_Bin_o = 5'b00001;//1
end else if(~Data_Dec_i[23]) begin Data_Bin_o = 5'b00010;//2
end else if(~Data_Dec_i[22]) begin Data_Bin_o = 5'b00011;//3
end else if(~Data_Dec_i[21]) begin Data_Bin_o = 5'b00100;//4
end else if(~Data_Dec_i[20]) begin Data_Bin_o = 5'b00101;//5
end else if(~Data_Dec_i[19]) begin Data_Bin_o = 5'b00110;//6
end else if(~Data_Dec_i[18]) begin Data_Bin_o = 5'b00111;//7
end else if(~Data_Dec_i[17]) begin Data_Bin_o = 5'b01000;//8
end else if(~Data_Dec_i[16]) begin Data_Bin_o = 5'b01001;//9
end else if(~Data_Dec_i[15]) begin Data_Bin_o = 5'b01010;//10
end else if(~Data_Dec_i[14]) begin Data_Bin_o = 5'b01011;//11
end else if(~Data_Dec_i[13]) begin Data_Bin_o = 5'b01100;//12
end else if(~Data_Dec_i[12]) begin Data_Bin_o = 5'b01101;//13
end else if(~Data_Dec_i[11]) begin Data_Bin_o = 5'b01110;//14
end else if(~Data_Dec_i[10]) begin Data_Bin_o = 5'b01111;//15
end else if(~Data_Dec_i[9]) begin Data_Bin_o = 5'b10000;//16
end else if(~Data_Dec_i[8]) begin Data_Bin_o = 5'b10001;//17
end else if(~Data_Dec_i[7]) begin Data_Bin_o = 5'b10010;//18
end else if(~Data_Dec_i[6]) begin Data_Bin_o = 5'b10011;//19
end else if(~Data_Dec_i[5]) begin Data_Bin_o = 5'b10100;//20
end else if(~Data_Dec_i[4]) begin Data_Bin_o = 5'b10101;//21
end else if(~Data_Dec_i[3]) begin Data_Bin_o = 5'b10110;//22
end else if(~Data_Dec_i[2]) begin Data_Bin_o = 5'b10111;//23
end else if(~Data_Dec_i[1]) begin Data_Bin_o = 5'b11000;//24
end else if(~Data_Dec_i[0]) begin Data_Bin_o = 5'b10101;//25
end
else Data_Bin_o = 5'b00000;//zero value
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:40:46 12/20/2010
// Design Name:
// Module Name: clk_test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module clk_test(
input clk,
input sysclk,
output [31:0] snes_sysclk_freq
);
reg [31:0] snes_sysclk_freq_r;
assign snes_sysclk_freq = snes_sysclk_freq_r;
reg [31:0] sysclk_counter;
reg [31:0] sysclk_value;
initial snes_sysclk_freq_r = 32'hFFFFFFFF;
initial sysclk_counter = 0;
initial sysclk_value = 0;
reg [1:0] sysclk_sreg;
always @(posedge clk) sysclk_sreg <= {sysclk_sreg[0], sysclk};
wire sysclk_rising = (sysclk_sreg == 2'b01);
always @(posedge clk) begin
if(sysclk_counter < 96000000) begin
sysclk_counter <= sysclk_counter + 1;
if(sysclk_rising) sysclk_value <= sysclk_value + 1;
end else begin
snes_sysclk_freq_r <= sysclk_value;
sysclk_counter <= 0;
sysclk_value <= 0;
end
end
endmodule
|
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axi to vector
// A generic module to merge all axi signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule
`default_nettype wire
|
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axi to vector
// A generic module to merge all axi signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule
`default_nettype wire
|
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axi to vector
// A generic module to merge all axi signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule
`default_nettype wire
|
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axi to vector
// A generic module to merge all axi signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule
`default_nettype wire
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAP_TB_V
`define SKY130_FD_SC_LP__TAP_TB_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__tap.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_lp__tap dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAP_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FA_BLACKBOX_V
`define SKY130_FD_SC_MS__FA_BLACKBOX_V
/**
* fa: Full adder.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__fa (
COUT,
SUM ,
A ,
B ,
CIN
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__FA_BLACKBOX_V
|
`timescale 1ns / 1ps
`include "constants.vh"
//////////////////////////////////////////////////////////////////////////////////
// Company: TU Darmstadt
// Engineer: Florian Beyer
//
// Create Date: 17:06:57 02/23/2017
// Design Name:
// Module Name: SpongentHash
// Project Name: spongent
// Target Devices:
// Tool versions:
// Description: SpongentHash is the top-level module of SPONGENT. This version
// has some potential to decrease it`s area and increase the overall performance.
// Therefore the input data, which contains the value to be hashed, has to be stored
// in the hardware ram.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SpongentHash(clk, rst, en, rdy, hash_out);
input rst;
input clk;
input en;
output reg rdy;
output reg [87:0] hash_out;
reg [263:0] state;
reg [512:0] data;
reg [ 87:0] hash;
reg [ 31:0] i, count;
reg wr_en;
reg [263:0] absorb_state_in;
reg absorb_enable;
reg absorb_rst;
wire absorb_out_rdy;
wire [263:0] absorb_state_out;
Absorb absorb_instance (
.state_in(absorb_state_in),
.state_out(absorb_state_out),
.clk(clk),
.rst(absorb_rst),
.en(absorb_enable),
.rdy(absorb_out_rdy)
);
always @ (posedge clk or posedge rst) begin
if (rst) begin
rdy = 0;
state = 0;
//data = {"Hello WorldHello WorldZY", 8'h80, 8'h00, 8'h00, 8'h00, 8'h00, 8'h00, 8'h00, 8'h00, 8'h00}; //padding
data = {"Spongent is a lightweight Hashfunction", 8'h80, 8'h00, 8'h00, 8'h00, 8'h00, 8'h00};
//count = 3;
count = 4;
wr_en = 1;
absorb_rst = rst;
absorb_state_in = 0;
absorb_enable = 0;
hash = 0;
end else if (en) begin
absorb_rst = 0;
if (wr_en) begin
wr_en = 0;
// Call Absorb for every block of data with length `R_SizeInBytes.
// The padding before ensures, that databitlen % rate(88) = 0;
if (count > 0) begin
// XOR (^) the last 11 bytes of state with the actual datablock.
for (i = 0; i < `R_SizeInBytes*8; i = i+8) begin
state[i+:8] = state[i+:8] ^ data[count * 88 - (i+8) +:8];
end
absorb_state_in = state;
absorb_enable = 1;
end else begin
for (i = 0; i < `R_SizeInBytes*8; i = i+8) begin
hash[i+:8] = hash[i+:8] ^ state[i +:8];
end
hash_out = hash;
rdy = 1;
end
end
// If output of absorb is ready, save it´s state and reset absorb.
// Then enable the computation in SpongentHash again (wr_en=1).
if (absorb_out_rdy) begin
state = absorb_state_out;
absorb_rst = 1;
if (count > 0) begin
count = count - 1;
wr_en = 1;
end
end
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
// Date : Sat Jan 21 14:32:46 2017
// Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mult16_16_sim_netlist.v
// Design : mult16_16
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xcku035-fbva676-3-e
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "mult16_16,mult_gen_v12_0_12,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "mult_gen_v12_0_12,Vivado 2016.4" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(CLK,
A,
B,
P);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_intf CLK" *) input CLK;
(* x_interface_info = "xilinx.com:signal:data:1.0 a_intf DATA" *) input [15:0]A;
(* x_interface_info = "xilinx.com:signal:data:1.0 b_intf DATA" *) input [15:0]B;
(* x_interface_info = "xilinx.com:signal:data:1.0 p_intf DATA" *) output [7:0]P;
wire [15:0]A;
wire [15:0]B;
wire CLK;
wire [7:0]P;
wire [47:0]NLW_U0_PCASC_UNCONNECTED;
wire [1:0]NLW_U0_ZERO_DETECT_UNCONNECTED;
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "16" *)
(* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "16" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "0" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "4" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "0" *)
(* C_OUT_HIGH = "31" *)
(* C_OUT_LOW = "24" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "kintexu" *)
(* c_optimize_goal = "1" *)
(* downgradeipidentifiedwarnings = "yes" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 U0
(.A(A),
.B(B),
.CE(1'b1),
.CLK(CLK),
.P(P),
.PCASC(NLW_U0_PCASC_UNCONNECTED[47:0]),
.SCLR(1'b0),
.ZERO_DETECT(NLW_U0_ZERO_DETECT_UNCONNECTED[1:0]));
endmodule
(* C_A_TYPE = "1" *) (* C_A_WIDTH = "16" *) (* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *) (* C_B_WIDTH = "16" *) (* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *) (* C_HAS_CE = "0" *) (* C_HAS_SCLR = "0" *)
(* C_HAS_ZERO_DETECT = "0" *) (* C_LATENCY = "4" *) (* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "0" *) (* C_OPTIMIZE_GOAL = "1" *) (* C_OUT_HIGH = "31" *)
(* C_OUT_LOW = "24" *) (* C_ROUND_OUTPUT = "0" *) (* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *) (* C_XDEVICEFAMILY = "kintexu" *) (* downgradeipidentifiedwarnings = "yes" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12
(CLK,
A,
B,
CE,
SCLR,
ZERO_DETECT,
P,
PCASC);
input CLK;
input [15:0]A;
input [15:0]B;
input CE;
input SCLR;
output [1:0]ZERO_DETECT;
output [7:0]P;
output [47:0]PCASC;
wire \<const0> ;
wire [15:0]A;
wire [15:0]B;
wire CLK;
wire [7:0]P;
wire [47:0]NLW_i_mult_PCASC_UNCONNECTED;
wire [1:0]NLW_i_mult_ZERO_DETECT_UNCONNECTED;
assign PCASC[47] = \<const0> ;
assign PCASC[46] = \<const0> ;
assign PCASC[45] = \<const0> ;
assign PCASC[44] = \<const0> ;
assign PCASC[43] = \<const0> ;
assign PCASC[42] = \<const0> ;
assign PCASC[41] = \<const0> ;
assign PCASC[40] = \<const0> ;
assign PCASC[39] = \<const0> ;
assign PCASC[38] = \<const0> ;
assign PCASC[37] = \<const0> ;
assign PCASC[36] = \<const0> ;
assign PCASC[35] = \<const0> ;
assign PCASC[34] = \<const0> ;
assign PCASC[33] = \<const0> ;
assign PCASC[32] = \<const0> ;
assign PCASC[31] = \<const0> ;
assign PCASC[30] = \<const0> ;
assign PCASC[29] = \<const0> ;
assign PCASC[28] = \<const0> ;
assign PCASC[27] = \<const0> ;
assign PCASC[26] = \<const0> ;
assign PCASC[25] = \<const0> ;
assign PCASC[24] = \<const0> ;
assign PCASC[23] = \<const0> ;
assign PCASC[22] = \<const0> ;
assign PCASC[21] = \<const0> ;
assign PCASC[20] = \<const0> ;
assign PCASC[19] = \<const0> ;
assign PCASC[18] = \<const0> ;
assign PCASC[17] = \<const0> ;
assign PCASC[16] = \<const0> ;
assign PCASC[15] = \<const0> ;
assign PCASC[14] = \<const0> ;
assign PCASC[13] = \<const0> ;
assign PCASC[12] = \<const0> ;
assign PCASC[11] = \<const0> ;
assign PCASC[10] = \<const0> ;
assign PCASC[9] = \<const0> ;
assign PCASC[8] = \<const0> ;
assign PCASC[7] = \<const0> ;
assign PCASC[6] = \<const0> ;
assign PCASC[5] = \<const0> ;
assign PCASC[4] = \<const0> ;
assign PCASC[3] = \<const0> ;
assign PCASC[2] = \<const0> ;
assign PCASC[1] = \<const0> ;
assign PCASC[0] = \<const0> ;
assign ZERO_DETECT[1] = \<const0> ;
assign ZERO_DETECT[0] = \<const0> ;
GND GND
(.G(\<const0> ));
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "16" *)
(* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "16" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "0" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "4" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "0" *)
(* C_OUT_HIGH = "31" *)
(* C_OUT_LOW = "24" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "kintexu" *)
(* c_optimize_goal = "1" *)
(* downgradeipidentifiedwarnings = "yes" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12_viv i_mult
(.A(A),
.B(B),
.CE(1'b0),
.CLK(CLK),
.P(P),
.PCASC(NLW_i_mult_PCASC_UNCONNECTED[47:0]),
.SCLR(1'b0),
.ZERO_DETECT(NLW_i_mult_ZERO_DETECT_UNCONNECTED[1:0]));
endmodule
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`pragma protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=64)
`pragma protect key_block
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`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`pragma protect key_block
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`pragma protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`pragma protect key_block
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`pragma protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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`pragma protect key_keyowner="ATRENTA", key_keyname="ATR-SG-2015-RSA-3", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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`pragma protect key_keyowner="Xilinx", key_keyname="xilinx_2016_05", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-PREC-RSA", key_method="rsa"
`pragma protect encoding = (enctype="base64", line_length=76, bytes=256)
`pragma protect key_block
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`pragma protect key_keyowner="Synplicity", key_keyname="SYNP05_001", key_method="rsa"
`pragma protect encoding = (enctype="base64", line_length=76, bytes=256)
`pragma protect key_block
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`pragma protect data_block
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`pragma protect end_protected
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//-----------------------------------------------------------------------------
// system_nfa_accept_samples_generic_hw_top_3_wrapper.v
//-----------------------------------------------------------------------------
module system_nfa_accept_samples_generic_hw_top_3_wrapper
(
aclk,
aresetn,
indices_MPLB_Clk,
indices_MPLB_Rst,
indices_M_request,
indices_M_priority,
indices_M_busLock,
indices_M_RNW,
indices_M_BE,
indices_M_MSize,
indices_M_size,
indices_M_type,
indices_M_TAttribute,
indices_M_lockErr,
indices_M_abort,
indices_M_UABus,
indices_M_ABus,
indices_M_wrDBus,
indices_M_wrBurst,
indices_M_rdBurst,
indices_PLB_MAddrAck,
indices_PLB_MSSize,
indices_PLB_MRearbitrate,
indices_PLB_MTimeout,
indices_PLB_MBusy,
indices_PLB_MRdErr,
indices_PLB_MWrErr,
indices_PLB_MIRQ,
indices_PLB_MRdDBus,
indices_PLB_MRdWdAddr,
indices_PLB_MRdDAck,
indices_PLB_MRdBTerm,
indices_PLB_MWrDAck,
indices_PLB_MWrBTerm,
nfa_finals_buckets_MPLB_Clk,
nfa_finals_buckets_MPLB_Rst,
nfa_finals_buckets_M_request,
nfa_finals_buckets_M_priority,
nfa_finals_buckets_M_busLock,
nfa_finals_buckets_M_RNW,
nfa_finals_buckets_M_BE,
nfa_finals_buckets_M_MSize,
nfa_finals_buckets_M_size,
nfa_finals_buckets_M_type,
nfa_finals_buckets_M_TAttribute,
nfa_finals_buckets_M_lockErr,
nfa_finals_buckets_M_abort,
nfa_finals_buckets_M_UABus,
nfa_finals_buckets_M_ABus,
nfa_finals_buckets_M_wrDBus,
nfa_finals_buckets_M_wrBurst,
nfa_finals_buckets_M_rdBurst,
nfa_finals_buckets_PLB_MAddrAck,
nfa_finals_buckets_PLB_MSSize,
nfa_finals_buckets_PLB_MRearbitrate,
nfa_finals_buckets_PLB_MTimeout,
nfa_finals_buckets_PLB_MBusy,
nfa_finals_buckets_PLB_MRdErr,
nfa_finals_buckets_PLB_MWrErr,
nfa_finals_buckets_PLB_MIRQ,
nfa_finals_buckets_PLB_MRdDBus,
nfa_finals_buckets_PLB_MRdWdAddr,
nfa_finals_buckets_PLB_MRdDAck,
nfa_finals_buckets_PLB_MRdBTerm,
nfa_finals_buckets_PLB_MWrDAck,
nfa_finals_buckets_PLB_MWrBTerm,
nfa_forward_buckets_MPLB_Clk,
nfa_forward_buckets_MPLB_Rst,
nfa_forward_buckets_M_request,
nfa_forward_buckets_M_priority,
nfa_forward_buckets_M_busLock,
nfa_forward_buckets_M_RNW,
nfa_forward_buckets_M_BE,
nfa_forward_buckets_M_MSize,
nfa_forward_buckets_M_size,
nfa_forward_buckets_M_type,
nfa_forward_buckets_M_TAttribute,
nfa_forward_buckets_M_lockErr,
nfa_forward_buckets_M_abort,
nfa_forward_buckets_M_UABus,
nfa_forward_buckets_M_ABus,
nfa_forward_buckets_M_wrDBus,
nfa_forward_buckets_M_wrBurst,
nfa_forward_buckets_M_rdBurst,
nfa_forward_buckets_PLB_MAddrAck,
nfa_forward_buckets_PLB_MSSize,
nfa_forward_buckets_PLB_MRearbitrate,
nfa_forward_buckets_PLB_MTimeout,
nfa_forward_buckets_PLB_MBusy,
nfa_forward_buckets_PLB_MRdErr,
nfa_forward_buckets_PLB_MWrErr,
nfa_forward_buckets_PLB_MIRQ,
nfa_forward_buckets_PLB_MRdDBus,
nfa_forward_buckets_PLB_MRdWdAddr,
nfa_forward_buckets_PLB_MRdDAck,
nfa_forward_buckets_PLB_MRdBTerm,
nfa_forward_buckets_PLB_MWrDAck,
nfa_forward_buckets_PLB_MWrBTerm,
nfa_initials_buckets_MPLB_Clk,
nfa_initials_buckets_MPLB_Rst,
nfa_initials_buckets_M_request,
nfa_initials_buckets_M_priority,
nfa_initials_buckets_M_busLock,
nfa_initials_buckets_M_RNW,
nfa_initials_buckets_M_BE,
nfa_initials_buckets_M_MSize,
nfa_initials_buckets_M_size,
nfa_initials_buckets_M_type,
nfa_initials_buckets_M_TAttribute,
nfa_initials_buckets_M_lockErr,
nfa_initials_buckets_M_abort,
nfa_initials_buckets_M_UABus,
nfa_initials_buckets_M_ABus,
nfa_initials_buckets_M_wrDBus,
nfa_initials_buckets_M_wrBurst,
nfa_initials_buckets_M_rdBurst,
nfa_initials_buckets_PLB_MAddrAck,
nfa_initials_buckets_PLB_MSSize,
nfa_initials_buckets_PLB_MRearbitrate,
nfa_initials_buckets_PLB_MTimeout,
nfa_initials_buckets_PLB_MBusy,
nfa_initials_buckets_PLB_MRdErr,
nfa_initials_buckets_PLB_MWrErr,
nfa_initials_buckets_PLB_MIRQ,
nfa_initials_buckets_PLB_MRdDBus,
nfa_initials_buckets_PLB_MRdWdAddr,
nfa_initials_buckets_PLB_MRdDAck,
nfa_initials_buckets_PLB_MRdBTerm,
nfa_initials_buckets_PLB_MWrDAck,
nfa_initials_buckets_PLB_MWrBTerm,
sample_buffer_MPLB_Clk,
sample_buffer_MPLB_Rst,
sample_buffer_M_request,
sample_buffer_M_priority,
sample_buffer_M_busLock,
sample_buffer_M_RNW,
sample_buffer_M_BE,
sample_buffer_M_MSize,
sample_buffer_M_size,
sample_buffer_M_type,
sample_buffer_M_TAttribute,
sample_buffer_M_lockErr,
sample_buffer_M_abort,
sample_buffer_M_UABus,
sample_buffer_M_ABus,
sample_buffer_M_wrDBus,
sample_buffer_M_wrBurst,
sample_buffer_M_rdBurst,
sample_buffer_PLB_MAddrAck,
sample_buffer_PLB_MSSize,
sample_buffer_PLB_MRearbitrate,
sample_buffer_PLB_MTimeout,
sample_buffer_PLB_MBusy,
sample_buffer_PLB_MRdErr,
sample_buffer_PLB_MWrErr,
sample_buffer_PLB_MIRQ,
sample_buffer_PLB_MRdDBus,
sample_buffer_PLB_MRdWdAddr,
sample_buffer_PLB_MRdDAck,
sample_buffer_PLB_MRdBTerm,
sample_buffer_PLB_MWrDAck,
sample_buffer_PLB_MWrBTerm,
splb_slv0_SPLB_Clk,
splb_slv0_SPLB_Rst,
splb_slv0_PLB_ABus,
splb_slv0_PLB_UABus,
splb_slv0_PLB_PAValid,
splb_slv0_PLB_SAValid,
splb_slv0_PLB_rdPrim,
splb_slv0_PLB_wrPrim,
splb_slv0_PLB_masterID,
splb_slv0_PLB_abort,
splb_slv0_PLB_busLock,
splb_slv0_PLB_RNW,
splb_slv0_PLB_BE,
splb_slv0_PLB_MSize,
splb_slv0_PLB_size,
splb_slv0_PLB_type,
splb_slv0_PLB_lockErr,
splb_slv0_PLB_wrDBus,
splb_slv0_PLB_wrBurst,
splb_slv0_PLB_rdBurst,
splb_slv0_PLB_wrPendReq,
splb_slv0_PLB_rdPendReq,
splb_slv0_PLB_wrPendPri,
splb_slv0_PLB_rdPendPri,
splb_slv0_PLB_reqPri,
splb_slv0_PLB_TAttribute,
splb_slv0_Sl_addrAck,
splb_slv0_Sl_SSize,
splb_slv0_Sl_wait,
splb_slv0_Sl_rearbitrate,
splb_slv0_Sl_wrDAck,
splb_slv0_Sl_wrComp,
splb_slv0_Sl_wrBTerm,
splb_slv0_Sl_rdDBus,
splb_slv0_Sl_rdWdAddr,
splb_slv0_Sl_rdDAck,
splb_slv0_Sl_rdComp,
splb_slv0_Sl_rdBTerm,
splb_slv0_Sl_MBusy,
splb_slv0_Sl_MWrErr,
splb_slv0_Sl_MRdErr,
splb_slv0_Sl_MIRQ
);
input aclk;
input aresetn;
input indices_MPLB_Clk;
input indices_MPLB_Rst;
output indices_M_request;
output [0:1] indices_M_priority;
output indices_M_busLock;
output indices_M_RNW;
output [0:7] indices_M_BE;
output [0:1] indices_M_MSize;
output [0:3] indices_M_size;
output [0:2] indices_M_type;
output [0:15] indices_M_TAttribute;
output indices_M_lockErr;
output indices_M_abort;
output [0:31] indices_M_UABus;
output [0:31] indices_M_ABus;
output [0:63] indices_M_wrDBus;
output indices_M_wrBurst;
output indices_M_rdBurst;
input indices_PLB_MAddrAck;
input [0:1] indices_PLB_MSSize;
input indices_PLB_MRearbitrate;
input indices_PLB_MTimeout;
input indices_PLB_MBusy;
input indices_PLB_MRdErr;
input indices_PLB_MWrErr;
input indices_PLB_MIRQ;
input [0:63] indices_PLB_MRdDBus;
input [0:3] indices_PLB_MRdWdAddr;
input indices_PLB_MRdDAck;
input indices_PLB_MRdBTerm;
input indices_PLB_MWrDAck;
input indices_PLB_MWrBTerm;
input nfa_finals_buckets_MPLB_Clk;
input nfa_finals_buckets_MPLB_Rst;
output nfa_finals_buckets_M_request;
output [0:1] nfa_finals_buckets_M_priority;
output nfa_finals_buckets_M_busLock;
output nfa_finals_buckets_M_RNW;
output [0:7] nfa_finals_buckets_M_BE;
output [0:1] nfa_finals_buckets_M_MSize;
output [0:3] nfa_finals_buckets_M_size;
output [0:2] nfa_finals_buckets_M_type;
output [0:15] nfa_finals_buckets_M_TAttribute;
output nfa_finals_buckets_M_lockErr;
output nfa_finals_buckets_M_abort;
output [0:31] nfa_finals_buckets_M_UABus;
output [0:31] nfa_finals_buckets_M_ABus;
output [0:63] nfa_finals_buckets_M_wrDBus;
output nfa_finals_buckets_M_wrBurst;
output nfa_finals_buckets_M_rdBurst;
input nfa_finals_buckets_PLB_MAddrAck;
input [0:1] nfa_finals_buckets_PLB_MSSize;
input nfa_finals_buckets_PLB_MRearbitrate;
input nfa_finals_buckets_PLB_MTimeout;
input nfa_finals_buckets_PLB_MBusy;
input nfa_finals_buckets_PLB_MRdErr;
input nfa_finals_buckets_PLB_MWrErr;
input nfa_finals_buckets_PLB_MIRQ;
input [0:63] nfa_finals_buckets_PLB_MRdDBus;
input [0:3] nfa_finals_buckets_PLB_MRdWdAddr;
input nfa_finals_buckets_PLB_MRdDAck;
input nfa_finals_buckets_PLB_MRdBTerm;
input nfa_finals_buckets_PLB_MWrDAck;
input nfa_finals_buckets_PLB_MWrBTerm;
input nfa_forward_buckets_MPLB_Clk;
input nfa_forward_buckets_MPLB_Rst;
output nfa_forward_buckets_M_request;
output [0:1] nfa_forward_buckets_M_priority;
output nfa_forward_buckets_M_busLock;
output nfa_forward_buckets_M_RNW;
output [0:7] nfa_forward_buckets_M_BE;
output [0:1] nfa_forward_buckets_M_MSize;
output [0:3] nfa_forward_buckets_M_size;
output [0:2] nfa_forward_buckets_M_type;
output [0:15] nfa_forward_buckets_M_TAttribute;
output nfa_forward_buckets_M_lockErr;
output nfa_forward_buckets_M_abort;
output [0:31] nfa_forward_buckets_M_UABus;
output [0:31] nfa_forward_buckets_M_ABus;
output [0:63] nfa_forward_buckets_M_wrDBus;
output nfa_forward_buckets_M_wrBurst;
output nfa_forward_buckets_M_rdBurst;
input nfa_forward_buckets_PLB_MAddrAck;
input [0:1] nfa_forward_buckets_PLB_MSSize;
input nfa_forward_buckets_PLB_MRearbitrate;
input nfa_forward_buckets_PLB_MTimeout;
input nfa_forward_buckets_PLB_MBusy;
input nfa_forward_buckets_PLB_MRdErr;
input nfa_forward_buckets_PLB_MWrErr;
input nfa_forward_buckets_PLB_MIRQ;
input [0:63] nfa_forward_buckets_PLB_MRdDBus;
input [0:3] nfa_forward_buckets_PLB_MRdWdAddr;
input nfa_forward_buckets_PLB_MRdDAck;
input nfa_forward_buckets_PLB_MRdBTerm;
input nfa_forward_buckets_PLB_MWrDAck;
input nfa_forward_buckets_PLB_MWrBTerm;
input nfa_initials_buckets_MPLB_Clk;
input nfa_initials_buckets_MPLB_Rst;
output nfa_initials_buckets_M_request;
output [0:1] nfa_initials_buckets_M_priority;
output nfa_initials_buckets_M_busLock;
output nfa_initials_buckets_M_RNW;
output [0:7] nfa_initials_buckets_M_BE;
output [0:1] nfa_initials_buckets_M_MSize;
output [0:3] nfa_initials_buckets_M_size;
output [0:2] nfa_initials_buckets_M_type;
output [0:15] nfa_initials_buckets_M_TAttribute;
output nfa_initials_buckets_M_lockErr;
output nfa_initials_buckets_M_abort;
output [0:31] nfa_initials_buckets_M_UABus;
output [0:31] nfa_initials_buckets_M_ABus;
output [0:63] nfa_initials_buckets_M_wrDBus;
output nfa_initials_buckets_M_wrBurst;
output nfa_initials_buckets_M_rdBurst;
input nfa_initials_buckets_PLB_MAddrAck;
input [0:1] nfa_initials_buckets_PLB_MSSize;
input nfa_initials_buckets_PLB_MRearbitrate;
input nfa_initials_buckets_PLB_MTimeout;
input nfa_initials_buckets_PLB_MBusy;
input nfa_initials_buckets_PLB_MRdErr;
input nfa_initials_buckets_PLB_MWrErr;
input nfa_initials_buckets_PLB_MIRQ;
input [0:63] nfa_initials_buckets_PLB_MRdDBus;
input [0:3] nfa_initials_buckets_PLB_MRdWdAddr;
input nfa_initials_buckets_PLB_MRdDAck;
input nfa_initials_buckets_PLB_MRdBTerm;
input nfa_initials_buckets_PLB_MWrDAck;
input nfa_initials_buckets_PLB_MWrBTerm;
input sample_buffer_MPLB_Clk;
input sample_buffer_MPLB_Rst;
output sample_buffer_M_request;
output [0:1] sample_buffer_M_priority;
output sample_buffer_M_busLock;
output sample_buffer_M_RNW;
output [0:7] sample_buffer_M_BE;
output [0:1] sample_buffer_M_MSize;
output [0:3] sample_buffer_M_size;
output [0:2] sample_buffer_M_type;
output [0:15] sample_buffer_M_TAttribute;
output sample_buffer_M_lockErr;
output sample_buffer_M_abort;
output [0:31] sample_buffer_M_UABus;
output [0:31] sample_buffer_M_ABus;
output [0:63] sample_buffer_M_wrDBus;
output sample_buffer_M_wrBurst;
output sample_buffer_M_rdBurst;
input sample_buffer_PLB_MAddrAck;
input [0:1] sample_buffer_PLB_MSSize;
input sample_buffer_PLB_MRearbitrate;
input sample_buffer_PLB_MTimeout;
input sample_buffer_PLB_MBusy;
input sample_buffer_PLB_MRdErr;
input sample_buffer_PLB_MWrErr;
input sample_buffer_PLB_MIRQ;
input [0:63] sample_buffer_PLB_MRdDBus;
input [0:3] sample_buffer_PLB_MRdWdAddr;
input sample_buffer_PLB_MRdDAck;
input sample_buffer_PLB_MRdBTerm;
input sample_buffer_PLB_MWrDAck;
input sample_buffer_PLB_MWrBTerm;
input splb_slv0_SPLB_Clk;
input splb_slv0_SPLB_Rst;
input [0:31] splb_slv0_PLB_ABus;
input [0:31] splb_slv0_PLB_UABus;
input splb_slv0_PLB_PAValid;
input splb_slv0_PLB_SAValid;
input splb_slv0_PLB_rdPrim;
input splb_slv0_PLB_wrPrim;
input [0:2] splb_slv0_PLB_masterID;
input splb_slv0_PLB_abort;
input splb_slv0_PLB_busLock;
input splb_slv0_PLB_RNW;
input [0:7] splb_slv0_PLB_BE;
input [0:1] splb_slv0_PLB_MSize;
input [0:3] splb_slv0_PLB_size;
input [0:2] splb_slv0_PLB_type;
input splb_slv0_PLB_lockErr;
input [0:63] splb_slv0_PLB_wrDBus;
input splb_slv0_PLB_wrBurst;
input splb_slv0_PLB_rdBurst;
input splb_slv0_PLB_wrPendReq;
input splb_slv0_PLB_rdPendReq;
input [0:1] splb_slv0_PLB_wrPendPri;
input [0:1] splb_slv0_PLB_rdPendPri;
input [0:1] splb_slv0_PLB_reqPri;
input [0:15] splb_slv0_PLB_TAttribute;
output splb_slv0_Sl_addrAck;
output [0:1] splb_slv0_Sl_SSize;
output splb_slv0_Sl_wait;
output splb_slv0_Sl_rearbitrate;
output splb_slv0_Sl_wrDAck;
output splb_slv0_Sl_wrComp;
output splb_slv0_Sl_wrBTerm;
output [0:63] splb_slv0_Sl_rdDBus;
output [0:3] splb_slv0_Sl_rdWdAddr;
output splb_slv0_Sl_rdDAck;
output splb_slv0_Sl_rdComp;
output splb_slv0_Sl_rdBTerm;
output [0:5] splb_slv0_Sl_MBusy;
output [0:5] splb_slv0_Sl_MWrErr;
output [0:5] splb_slv0_Sl_MRdErr;
output [0:5] splb_slv0_Sl_MIRQ;
nfa_accept_samples_generic_hw_top
#(
.RESET_ACTIVE_LOW ( 1 ),
.C_indices_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_indices_AWIDTH ( 32 ),
.C_indices_DWIDTH ( 64 ),
.C_indices_NATIVE_DWIDTH ( 64 ),
.C_nfa_finals_buckets_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_nfa_finals_buckets_AWIDTH ( 32 ),
.C_nfa_finals_buckets_DWIDTH ( 64 ),
.C_nfa_finals_buckets_NATIVE_DWIDTH ( 64 ),
.C_nfa_forward_buckets_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_nfa_forward_buckets_AWIDTH ( 32 ),
.C_nfa_forward_buckets_DWIDTH ( 64 ),
.C_nfa_forward_buckets_NATIVE_DWIDTH ( 64 ),
.C_nfa_initials_buckets_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_nfa_initials_buckets_AWIDTH ( 32 ),
.C_nfa_initials_buckets_DWIDTH ( 64 ),
.C_nfa_initials_buckets_NATIVE_DWIDTH ( 64 ),
.C_sample_buffer_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_sample_buffer_AWIDTH ( 32 ),
.C_sample_buffer_DWIDTH ( 64 ),
.C_sample_buffer_NATIVE_DWIDTH ( 64 ),
.C_SPLB_SLV0_BASEADDR ( 32'hD3000000 ),
.C_SPLB_SLV0_HIGHADDR ( 32'hD30000FF ),
.C_SPLB_SLV0_AWIDTH ( 32 ),
.C_SPLB_SLV0_DWIDTH ( 64 ),
.C_SPLB_SLV0_NUM_MASTERS ( 6 ),
.C_SPLB_SLV0_MID_WIDTH ( 3 ),
.C_SPLB_SLV0_NATIVE_DWIDTH ( 32 ),
.C_SPLB_SLV0_P2P ( 0 ),
.C_SPLB_SLV0_SUPPORT_BURSTS ( 0 ),
.C_SPLB_SLV0_SMALLEST_MASTER ( 32 ),
.C_SPLB_SLV0_INCLUDE_DPHASE_TIMER ( 0 )
)
nfa_accept_samples_generic_hw_top_3 (
.aclk ( aclk ),
.aresetn ( aresetn ),
.indices_MPLB_Clk ( indices_MPLB_Clk ),
.indices_MPLB_Rst ( indices_MPLB_Rst ),
.indices_M_request ( indices_M_request ),
.indices_M_priority ( indices_M_priority ),
.indices_M_busLock ( indices_M_busLock ),
.indices_M_RNW ( indices_M_RNW ),
.indices_M_BE ( indices_M_BE ),
.indices_M_MSize ( indices_M_MSize ),
.indices_M_size ( indices_M_size ),
.indices_M_type ( indices_M_type ),
.indices_M_TAttribute ( indices_M_TAttribute ),
.indices_M_lockErr ( indices_M_lockErr ),
.indices_M_abort ( indices_M_abort ),
.indices_M_UABus ( indices_M_UABus ),
.indices_M_ABus ( indices_M_ABus ),
.indices_M_wrDBus ( indices_M_wrDBus ),
.indices_M_wrBurst ( indices_M_wrBurst ),
.indices_M_rdBurst ( indices_M_rdBurst ),
.indices_PLB_MAddrAck ( indices_PLB_MAddrAck ),
.indices_PLB_MSSize ( indices_PLB_MSSize ),
.indices_PLB_MRearbitrate ( indices_PLB_MRearbitrate ),
.indices_PLB_MTimeout ( indices_PLB_MTimeout ),
.indices_PLB_MBusy ( indices_PLB_MBusy ),
.indices_PLB_MRdErr ( indices_PLB_MRdErr ),
.indices_PLB_MWrErr ( indices_PLB_MWrErr ),
.indices_PLB_MIRQ ( indices_PLB_MIRQ ),
.indices_PLB_MRdDBus ( indices_PLB_MRdDBus ),
.indices_PLB_MRdWdAddr ( indices_PLB_MRdWdAddr ),
.indices_PLB_MRdDAck ( indices_PLB_MRdDAck ),
.indices_PLB_MRdBTerm ( indices_PLB_MRdBTerm ),
.indices_PLB_MWrDAck ( indices_PLB_MWrDAck ),
.indices_PLB_MWrBTerm ( indices_PLB_MWrBTerm ),
.nfa_finals_buckets_MPLB_Clk ( nfa_finals_buckets_MPLB_Clk ),
.nfa_finals_buckets_MPLB_Rst ( nfa_finals_buckets_MPLB_Rst ),
.nfa_finals_buckets_M_request ( nfa_finals_buckets_M_request ),
.nfa_finals_buckets_M_priority ( nfa_finals_buckets_M_priority ),
.nfa_finals_buckets_M_busLock ( nfa_finals_buckets_M_busLock ),
.nfa_finals_buckets_M_RNW ( nfa_finals_buckets_M_RNW ),
.nfa_finals_buckets_M_BE ( nfa_finals_buckets_M_BE ),
.nfa_finals_buckets_M_MSize ( nfa_finals_buckets_M_MSize ),
.nfa_finals_buckets_M_size ( nfa_finals_buckets_M_size ),
.nfa_finals_buckets_M_type ( nfa_finals_buckets_M_type ),
.nfa_finals_buckets_M_TAttribute ( nfa_finals_buckets_M_TAttribute ),
.nfa_finals_buckets_M_lockErr ( nfa_finals_buckets_M_lockErr ),
.nfa_finals_buckets_M_abort ( nfa_finals_buckets_M_abort ),
.nfa_finals_buckets_M_UABus ( nfa_finals_buckets_M_UABus ),
.nfa_finals_buckets_M_ABus ( nfa_finals_buckets_M_ABus ),
.nfa_finals_buckets_M_wrDBus ( nfa_finals_buckets_M_wrDBus ),
.nfa_finals_buckets_M_wrBurst ( nfa_finals_buckets_M_wrBurst ),
.nfa_finals_buckets_M_rdBurst ( nfa_finals_buckets_M_rdBurst ),
.nfa_finals_buckets_PLB_MAddrAck ( nfa_finals_buckets_PLB_MAddrAck ),
.nfa_finals_buckets_PLB_MSSize ( nfa_finals_buckets_PLB_MSSize ),
.nfa_finals_buckets_PLB_MRearbitrate ( nfa_finals_buckets_PLB_MRearbitrate ),
.nfa_finals_buckets_PLB_MTimeout ( nfa_finals_buckets_PLB_MTimeout ),
.nfa_finals_buckets_PLB_MBusy ( nfa_finals_buckets_PLB_MBusy ),
.nfa_finals_buckets_PLB_MRdErr ( nfa_finals_buckets_PLB_MRdErr ),
.nfa_finals_buckets_PLB_MWrErr ( nfa_finals_buckets_PLB_MWrErr ),
.nfa_finals_buckets_PLB_MIRQ ( nfa_finals_buckets_PLB_MIRQ ),
.nfa_finals_buckets_PLB_MRdDBus ( nfa_finals_buckets_PLB_MRdDBus ),
.nfa_finals_buckets_PLB_MRdWdAddr ( nfa_finals_buckets_PLB_MRdWdAddr ),
.nfa_finals_buckets_PLB_MRdDAck ( nfa_finals_buckets_PLB_MRdDAck ),
.nfa_finals_buckets_PLB_MRdBTerm ( nfa_finals_buckets_PLB_MRdBTerm ),
.nfa_finals_buckets_PLB_MWrDAck ( nfa_finals_buckets_PLB_MWrDAck ),
.nfa_finals_buckets_PLB_MWrBTerm ( nfa_finals_buckets_PLB_MWrBTerm ),
.nfa_forward_buckets_MPLB_Clk ( nfa_forward_buckets_MPLB_Clk ),
.nfa_forward_buckets_MPLB_Rst ( nfa_forward_buckets_MPLB_Rst ),
.nfa_forward_buckets_M_request ( nfa_forward_buckets_M_request ),
.nfa_forward_buckets_M_priority ( nfa_forward_buckets_M_priority ),
.nfa_forward_buckets_M_busLock ( nfa_forward_buckets_M_busLock ),
.nfa_forward_buckets_M_RNW ( nfa_forward_buckets_M_RNW ),
.nfa_forward_buckets_M_BE ( nfa_forward_buckets_M_BE ),
.nfa_forward_buckets_M_MSize ( nfa_forward_buckets_M_MSize ),
.nfa_forward_buckets_M_size ( nfa_forward_buckets_M_size ),
.nfa_forward_buckets_M_type ( nfa_forward_buckets_M_type ),
.nfa_forward_buckets_M_TAttribute ( nfa_forward_buckets_M_TAttribute ),
.nfa_forward_buckets_M_lockErr ( nfa_forward_buckets_M_lockErr ),
.nfa_forward_buckets_M_abort ( nfa_forward_buckets_M_abort ),
.nfa_forward_buckets_M_UABus ( nfa_forward_buckets_M_UABus ),
.nfa_forward_buckets_M_ABus ( nfa_forward_buckets_M_ABus ),
.nfa_forward_buckets_M_wrDBus ( nfa_forward_buckets_M_wrDBus ),
.nfa_forward_buckets_M_wrBurst ( nfa_forward_buckets_M_wrBurst ),
.nfa_forward_buckets_M_rdBurst ( nfa_forward_buckets_M_rdBurst ),
.nfa_forward_buckets_PLB_MAddrAck ( nfa_forward_buckets_PLB_MAddrAck ),
.nfa_forward_buckets_PLB_MSSize ( nfa_forward_buckets_PLB_MSSize ),
.nfa_forward_buckets_PLB_MRearbitrate ( nfa_forward_buckets_PLB_MRearbitrate ),
.nfa_forward_buckets_PLB_MTimeout ( nfa_forward_buckets_PLB_MTimeout ),
.nfa_forward_buckets_PLB_MBusy ( nfa_forward_buckets_PLB_MBusy ),
.nfa_forward_buckets_PLB_MRdErr ( nfa_forward_buckets_PLB_MRdErr ),
.nfa_forward_buckets_PLB_MWrErr ( nfa_forward_buckets_PLB_MWrErr ),
.nfa_forward_buckets_PLB_MIRQ ( nfa_forward_buckets_PLB_MIRQ ),
.nfa_forward_buckets_PLB_MRdDBus ( nfa_forward_buckets_PLB_MRdDBus ),
.nfa_forward_buckets_PLB_MRdWdAddr ( nfa_forward_buckets_PLB_MRdWdAddr ),
.nfa_forward_buckets_PLB_MRdDAck ( nfa_forward_buckets_PLB_MRdDAck ),
.nfa_forward_buckets_PLB_MRdBTerm ( nfa_forward_buckets_PLB_MRdBTerm ),
.nfa_forward_buckets_PLB_MWrDAck ( nfa_forward_buckets_PLB_MWrDAck ),
.nfa_forward_buckets_PLB_MWrBTerm ( nfa_forward_buckets_PLB_MWrBTerm ),
.nfa_initials_buckets_MPLB_Clk ( nfa_initials_buckets_MPLB_Clk ),
.nfa_initials_buckets_MPLB_Rst ( nfa_initials_buckets_MPLB_Rst ),
.nfa_initials_buckets_M_request ( nfa_initials_buckets_M_request ),
.nfa_initials_buckets_M_priority ( nfa_initials_buckets_M_priority ),
.nfa_initials_buckets_M_busLock ( nfa_initials_buckets_M_busLock ),
.nfa_initials_buckets_M_RNW ( nfa_initials_buckets_M_RNW ),
.nfa_initials_buckets_M_BE ( nfa_initials_buckets_M_BE ),
.nfa_initials_buckets_M_MSize ( nfa_initials_buckets_M_MSize ),
.nfa_initials_buckets_M_size ( nfa_initials_buckets_M_size ),
.nfa_initials_buckets_M_type ( nfa_initials_buckets_M_type ),
.nfa_initials_buckets_M_TAttribute ( nfa_initials_buckets_M_TAttribute ),
.nfa_initials_buckets_M_lockErr ( nfa_initials_buckets_M_lockErr ),
.nfa_initials_buckets_M_abort ( nfa_initials_buckets_M_abort ),
.nfa_initials_buckets_M_UABus ( nfa_initials_buckets_M_UABus ),
.nfa_initials_buckets_M_ABus ( nfa_initials_buckets_M_ABus ),
.nfa_initials_buckets_M_wrDBus ( nfa_initials_buckets_M_wrDBus ),
.nfa_initials_buckets_M_wrBurst ( nfa_initials_buckets_M_wrBurst ),
.nfa_initials_buckets_M_rdBurst ( nfa_initials_buckets_M_rdBurst ),
.nfa_initials_buckets_PLB_MAddrAck ( nfa_initials_buckets_PLB_MAddrAck ),
.nfa_initials_buckets_PLB_MSSize ( nfa_initials_buckets_PLB_MSSize ),
.nfa_initials_buckets_PLB_MRearbitrate ( nfa_initials_buckets_PLB_MRearbitrate ),
.nfa_initials_buckets_PLB_MTimeout ( nfa_initials_buckets_PLB_MTimeout ),
.nfa_initials_buckets_PLB_MBusy ( nfa_initials_buckets_PLB_MBusy ),
.nfa_initials_buckets_PLB_MRdErr ( nfa_initials_buckets_PLB_MRdErr ),
.nfa_initials_buckets_PLB_MWrErr ( nfa_initials_buckets_PLB_MWrErr ),
.nfa_initials_buckets_PLB_MIRQ ( nfa_initials_buckets_PLB_MIRQ ),
.nfa_initials_buckets_PLB_MRdDBus ( nfa_initials_buckets_PLB_MRdDBus ),
.nfa_initials_buckets_PLB_MRdWdAddr ( nfa_initials_buckets_PLB_MRdWdAddr ),
.nfa_initials_buckets_PLB_MRdDAck ( nfa_initials_buckets_PLB_MRdDAck ),
.nfa_initials_buckets_PLB_MRdBTerm ( nfa_initials_buckets_PLB_MRdBTerm ),
.nfa_initials_buckets_PLB_MWrDAck ( nfa_initials_buckets_PLB_MWrDAck ),
.nfa_initials_buckets_PLB_MWrBTerm ( nfa_initials_buckets_PLB_MWrBTerm ),
.sample_buffer_MPLB_Clk ( sample_buffer_MPLB_Clk ),
.sample_buffer_MPLB_Rst ( sample_buffer_MPLB_Rst ),
.sample_buffer_M_request ( sample_buffer_M_request ),
.sample_buffer_M_priority ( sample_buffer_M_priority ),
.sample_buffer_M_busLock ( sample_buffer_M_busLock ),
.sample_buffer_M_RNW ( sample_buffer_M_RNW ),
.sample_buffer_M_BE ( sample_buffer_M_BE ),
.sample_buffer_M_MSize ( sample_buffer_M_MSize ),
.sample_buffer_M_size ( sample_buffer_M_size ),
.sample_buffer_M_type ( sample_buffer_M_type ),
.sample_buffer_M_TAttribute ( sample_buffer_M_TAttribute ),
.sample_buffer_M_lockErr ( sample_buffer_M_lockErr ),
.sample_buffer_M_abort ( sample_buffer_M_abort ),
.sample_buffer_M_UABus ( sample_buffer_M_UABus ),
.sample_buffer_M_ABus ( sample_buffer_M_ABus ),
.sample_buffer_M_wrDBus ( sample_buffer_M_wrDBus ),
.sample_buffer_M_wrBurst ( sample_buffer_M_wrBurst ),
.sample_buffer_M_rdBurst ( sample_buffer_M_rdBurst ),
.sample_buffer_PLB_MAddrAck ( sample_buffer_PLB_MAddrAck ),
.sample_buffer_PLB_MSSize ( sample_buffer_PLB_MSSize ),
.sample_buffer_PLB_MRearbitrate ( sample_buffer_PLB_MRearbitrate ),
.sample_buffer_PLB_MTimeout ( sample_buffer_PLB_MTimeout ),
.sample_buffer_PLB_MBusy ( sample_buffer_PLB_MBusy ),
.sample_buffer_PLB_MRdErr ( sample_buffer_PLB_MRdErr ),
.sample_buffer_PLB_MWrErr ( sample_buffer_PLB_MWrErr ),
.sample_buffer_PLB_MIRQ ( sample_buffer_PLB_MIRQ ),
.sample_buffer_PLB_MRdDBus ( sample_buffer_PLB_MRdDBus ),
.sample_buffer_PLB_MRdWdAddr ( sample_buffer_PLB_MRdWdAddr ),
.sample_buffer_PLB_MRdDAck ( sample_buffer_PLB_MRdDAck ),
.sample_buffer_PLB_MRdBTerm ( sample_buffer_PLB_MRdBTerm ),
.sample_buffer_PLB_MWrDAck ( sample_buffer_PLB_MWrDAck ),
.sample_buffer_PLB_MWrBTerm ( sample_buffer_PLB_MWrBTerm ),
.splb_slv0_SPLB_Clk ( splb_slv0_SPLB_Clk ),
.splb_slv0_SPLB_Rst ( splb_slv0_SPLB_Rst ),
.splb_slv0_PLB_ABus ( splb_slv0_PLB_ABus ),
.splb_slv0_PLB_UABus ( splb_slv0_PLB_UABus ),
.splb_slv0_PLB_PAValid ( splb_slv0_PLB_PAValid ),
.splb_slv0_PLB_SAValid ( splb_slv0_PLB_SAValid ),
.splb_slv0_PLB_rdPrim ( splb_slv0_PLB_rdPrim ),
.splb_slv0_PLB_wrPrim ( splb_slv0_PLB_wrPrim ),
.splb_slv0_PLB_masterID ( splb_slv0_PLB_masterID ),
.splb_slv0_PLB_abort ( splb_slv0_PLB_abort ),
.splb_slv0_PLB_busLock ( splb_slv0_PLB_busLock ),
.splb_slv0_PLB_RNW ( splb_slv0_PLB_RNW ),
.splb_slv0_PLB_BE ( splb_slv0_PLB_BE ),
.splb_slv0_PLB_MSize ( splb_slv0_PLB_MSize ),
.splb_slv0_PLB_size ( splb_slv0_PLB_size ),
.splb_slv0_PLB_type ( splb_slv0_PLB_type ),
.splb_slv0_PLB_lockErr ( splb_slv0_PLB_lockErr ),
.splb_slv0_PLB_wrDBus ( splb_slv0_PLB_wrDBus ),
.splb_slv0_PLB_wrBurst ( splb_slv0_PLB_wrBurst ),
.splb_slv0_PLB_rdBurst ( splb_slv0_PLB_rdBurst ),
.splb_slv0_PLB_wrPendReq ( splb_slv0_PLB_wrPendReq ),
.splb_slv0_PLB_rdPendReq ( splb_slv0_PLB_rdPendReq ),
.splb_slv0_PLB_wrPendPri ( splb_slv0_PLB_wrPendPri ),
.splb_slv0_PLB_rdPendPri ( splb_slv0_PLB_rdPendPri ),
.splb_slv0_PLB_reqPri ( splb_slv0_PLB_reqPri ),
.splb_slv0_PLB_TAttribute ( splb_slv0_PLB_TAttribute ),
.splb_slv0_Sl_addrAck ( splb_slv0_Sl_addrAck ),
.splb_slv0_Sl_SSize ( splb_slv0_Sl_SSize ),
.splb_slv0_Sl_wait ( splb_slv0_Sl_wait ),
.splb_slv0_Sl_rearbitrate ( splb_slv0_Sl_rearbitrate ),
.splb_slv0_Sl_wrDAck ( splb_slv0_Sl_wrDAck ),
.splb_slv0_Sl_wrComp ( splb_slv0_Sl_wrComp ),
.splb_slv0_Sl_wrBTerm ( splb_slv0_Sl_wrBTerm ),
.splb_slv0_Sl_rdDBus ( splb_slv0_Sl_rdDBus ),
.splb_slv0_Sl_rdWdAddr ( splb_slv0_Sl_rdWdAddr ),
.splb_slv0_Sl_rdDAck ( splb_slv0_Sl_rdDAck ),
.splb_slv0_Sl_rdComp ( splb_slv0_Sl_rdComp ),
.splb_slv0_Sl_rdBTerm ( splb_slv0_Sl_rdBTerm ),
.splb_slv0_Sl_MBusy ( splb_slv0_Sl_MBusy ),
.splb_slv0_Sl_MWrErr ( splb_slv0_Sl_MWrErr ),
.splb_slv0_Sl_MRdErr ( splb_slv0_Sl_MRdErr ),
.splb_slv0_Sl_MIRQ ( splb_slv0_Sl_MIRQ )
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21A_BEHAVIORAL_V
`define SKY130_FD_SC_LP__O21A_BEHAVIORAL_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__o21a (
X ,
A1,
A2,
B1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X, or0_out, B1 );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21A_BEHAVIORAL_V |
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/18.1std/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
// $Revision: #1 $
// $Date: 2018/07/18 $
// $Author: psgswbuild $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_pipeline_base (
clk,
reset,
in_ready,
in_valid,
in_data,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter PIPELINE_READY = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input clk;
input reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
reg full0;
reg full1;
reg [DATA_WIDTH-1:0] data0;
reg [DATA_WIDTH-1:0] data1;
assign out_valid = full1;
assign out_data = data1;
generate if (PIPELINE_READY == 1)
begin : REGISTERED_READY_PLINE
assign in_ready = !full0;
always @(posedge clk, posedge reset) begin
if (reset) begin
data0 <= {DATA_WIDTH{1'b0}};
data1 <= {DATA_WIDTH{1'b0}};
end else begin
// ----------------------------
// always load the second slot if we can
// ----------------------------
if (~full0)
data0 <= in_data;
// ----------------------------
// first slot is loaded either from the second,
// or with new data
// ----------------------------
if (~full1 || (out_ready && out_valid)) begin
if (full0)
data1 <= data0;
else
data1 <= in_data;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
full0 <= 1'b0;
full1 <= 1'b0;
end else begin
// no data in pipeline
if (~full0 & ~full1) begin
if (in_valid) begin
full1 <= 1'b1;
end
end // ~f1 & ~f0
// one datum in pipeline
if (full1 & ~full0) begin
if (in_valid & ~out_ready) begin
full0 <= 1'b1;
end
// back to empty
if (~in_valid & out_ready) begin
full1 <= 1'b0;
end
end // f1 & ~f0
// two data in pipeline
if (full1 & full0) begin
// go back to one datum state
if (out_ready) begin
full0 <= 1'b0;
end
end // end go back to one datum stage
end
end
end
else
begin : UNREGISTERED_READY_PLINE
// in_ready will be a pass through of the out_ready signal as it is not registered
assign in_ready = (~full1) | out_ready;
always @(posedge clk or posedge reset) begin
if (reset) begin
data1 <= 'b0;
full1 <= 1'b0;
end
else begin
if (in_ready) begin
data1 <= in_data;
full1 <= in_valid;
end
end
end
end
endgenerate
endmodule
|
//-----------------------------------------------------
// Design Name : hw1_B_testbench
// File Name : hw1_B_testbench.v
// Function : This program will test hw1_B.v
// Coder : hydai
//-----------------------------------------------------
`timescale 1 ns/1 ns
`include "hw1_B.v"
module hw1_B_testbench ;
reg [15:0] data;
reg [15:0] control;
reg clk, rst_n;
wire [15:0] R0, R1, R2, R3;
hw1_B testB(data,
control,
clk,
rst_n,
R0,
R1,
R2,
R3);
initial begin
#0 rst_n = 1'b0; clk = 1'b0; control = 16'h0000;
$display ("====================================================================");
$display ("Simulate hw1_B");
$display ("Time %t status", $time);
$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
rst_n, data, control, R0, R1, R2, R3);
#20 rst_n = 1'b1;
$display ("====================================================================");
$display ("Time %t status", $time);
$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
rst_n, data, control, R0, R1, R2, R3);
// R0 <- 0x0101
#20 data = 16'h0101; control = 16'b011_111_111_111_0001;
$display ("====================================================================");
$display ("Time %t status", $time);
$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
rst_n, data, control, R0, R1, R2, R3);
// R0 <- 0x0202; R1 <- R0
#20 data = 16'h0202; control = 16'b011_000_111_111_0011;
$display ("====================================================================");
$display ("Time %t status", $time);
$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
rst_n, data, control, R0, R1, R2, R3);
// R0 <- 0x0303, R1 <- R0, R2 <- R1
#20 data = 16'h0303; control = 16'b011_000_001_111_0111;
$display ("====================================================================");
$display ("Time %t status", $time);
$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
rst_n, data, control, R0, R1, R2, R3);
// R0 <- 0x0404, R1 <- R0, R2 <- R1, R3 <- R2
#20 data = 16'h0404; control = 16'b011_000_001_010_1111;
$display ("====================================================================");
$display ("Time %t status", $time);
$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
rst_n, data, control, R0, R1, R2, R3);
// R0 <- R3, R1 <- R0, R2 <- R1, R3 <- R2
#20 control = 16'b010_000_001_010_1111;
$display ("====================================================================");
$display ("Time %t status", $time);
$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
rst_n, data, control, R0, R1, R2, R3);
// R0 <- R3, R1 <- R0, R2 <- R1, R3 <- R2
#20 control = 16'b010_000_001_010_1111;
$display ("====================================================================");
$display ("Time %t status", $time);
$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
rst_n, data, control, R0, R1, R2, R3);
#20
$display ("====================================================================");
$display ("Time %t status", $time);
$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
rst_n, data, control, R0, R1, R2, R3);
$display ("====================================================================");
#40 $finish;
end
always begin
#10 clk = ~clk;
end
initial begin
$fsdbDumpfile("hw1_B_testbench.fsdb");
$fsdbDumpvars;
end
endmodule // End of Module hw1_B_testbench
|
/*
Anthony De Caria - June 15, 2014
This module is the structure that interfaces NIOS-II with two AD7264 A-D-Cs.
This is done using SPI protocol.
It takes key signals from NIOS (CPOL, CPHA, ss), and transforms them into SCLK and SS signals.
In addition, it also creates the structures needed to collect and transmit data to and from the AD7264s
A 16-bit serializer for transmitting.
And two 14-bit deserializers for receiving, as the AD7264 is a dual channel device.
*/
module ADCConnector
(
SPIClock, resetn,
CPOL, CPHA, ss,
SCLK, SS, MOSI1, MISO1A, MISO1B, MOSI2, MISO2A, MISO2B,
dataOutOfMaster1, dataIntoMaster1A, dataIntoMaster1B, dataOutOfMaster2, dataIntoMaster2A, dataIntoMaster2B,
masterSaysLoad1, masterSaysLoad2, finishedCycling, loadedData1, loadedData2
);
/*
I/Os
*/
// General I/Os //
input SPIClock;
input resetn;
// CPU I/Os //
input CPOL;
input CPHA;
input ss;
input masterSaysLoad1;
input masterSaysLoad2;
output finishedCycling;
output loadedData1;
output loadedData2;
// Data I/Os //
input [15:0]dataOutOfMaster1;
output [13:0]dataIntoMaster1A;
output [13:0]dataIntoMaster1B;
input [15:0]dataOutOfMaster2;
output [13:0]dataIntoMaster2A;
output [13:0]dataIntoMaster2B;
// SPI I/Os //
output SCLK;
output SS;
output MOSI1;
input MISO1A;
input MISO1B;
output MOSI2;
input MISO2A;
input MISO2B;
// Intra-Connector wires //
wire [5:0] master_counter_bit;
wire Des_en, Ser_en;
wire inboxLineIn1A, inboxLineIn1B, inboxLineIn2A, inboxLineIn2B, outboxLineOut1, outboxLineOut2;
wire [15:0] outboxQ1, outboxQ2;
wire registerSignal;
// Early assignments //
assign SS = ss;
assign Ser_en = ~master_counter_bit[5] & ~master_counter_bit[4];
assign Des_en = (~master_counter_bit[5] & master_counter_bit[4] & (master_counter_bit[3] | master_counter_bit[2] | master_counter_bit[1] & master_counter_bit[0]) ) | (master_counter_bit[5] & ~master_counter_bit[4] & ~master_counter_bit[3] & ~master_counter_bit[2] & ~master_counter_bit[1] & ~master_counter_bit[0]);
assign finishedCycling = master_counter_bit[5];
assign loadedData1 = (outboxQ1 == dataOutOfMaster1)? 1'b1: 1'b0;
// assign loadedData2 = (outboxQ2 == dataOutOfMaster2)? 1'b1: 1'b0;
assign loadedData2 = 1'b1;
assign outboxLineOut1 = outboxQ1[15];
assign outboxLineOut2 = outboxQ2[15];
/*
Counter
This is the counter that will be used to pace out the sending out and receiving parts of the
*/
Six_Bit_Counter_Enable_Async PocketWatch
(
.clk(SPIClock),
.resetn(resetn & ~SS),
.enable(~SS & ~(master_counter_bit[5] & ~master_counter_bit[4] & ~master_counter_bit[3] & ~master_counter_bit[2] & ~master_counter_bit[1] & master_counter_bit[0]) ),
.q(master_counter_bit)
);
/*
Signal Makers
*/
SCLKMaker TimeLord
(
.Clk(SPIClock),
.S(ss),
.CPOL(CPOL),
.SCLK(SCLK)
);
SPIRSMaker Level
(
.CPHA(CPHA),
.CPOL(CPOL),
.RS(registerSignal)
);
/*
Serializers
*/
Shift_Register_16_Enable_Async_Muxed OutBox1
(
.clk(~(SPIClock ^ registerSignal)),
.resetn(resetn),
.enable(Ser_en),
.select(masterSaysLoad1),
.d(dataOutOfMaster1),
.q(outboxQ1)
);
/*
Deserializers
*/
Shift_Register_14_Enable_Async InBox1A
(
.clk(~(SPIClock ^ registerSignal)),
.resetn(resetn),
.enable(Des_en),
.d(inboxLineIn1A),
.q(dataIntoMaster1A)
);
Shift_Register_14_Enable_Async InBox1B
(
.clk(~(SPIClock ^ registerSignal)),
.resetn(resetn),
.enable(Des_en),
.d(inboxLineIn1B),
.q(dataIntoMaster1B)
);
/*
Tri-state buffers
*/
TriStateBuffer_2_1bit BorderGuardOut1
(
.In(outboxLineOut1),
.Select(Ser_en),
.Out(MOSI1)
);
TriStateBuffer_2_1bit BorderGuardIn1A
(
.In(MISO1A),
.Select(Des_en),
.Out(inboxLineIn1A)
);
TriStateBuffer_2_1bit BorderGuardIn1B
(
.In(MISO1B),
.Select(Des_en),
.Out(inboxLineIn1B)
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// (c) Copyright 2008 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//
///////////////////////////////////////////////////////////////////////////////
//
// GLOBAL_LOGIC
//
//
// Description: The GLOBAL_LOGIC module handles channel bonding, channel
// verification, channel error manangement and idle generation.
//
// This module supports 4 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aur1_GLOBAL_LOGIC
(
// GTP Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Aurora Lane Interface
LANE_UP,
SOFT_ERROR,
HARD_ERROR,
CHANNEL_BOND_LOAD,
GOT_A,
GOT_V,
GEN_A,
GEN_K,
GEN_R,
GEN_V,
RESET_LANES,
// System Interface
USER_CLK,
RESET,
POWER_DOWN,
CHANNEL_UP,
START_RX,
CHANNEL_SOFT_ERROR,
CHANNEL_HARD_ERROR
);
`define DLY #1
//***********************************Port Declarations*******************************
// GTP Interface
input [0:3] CH_BOND_DONE;
output EN_CHAN_SYNC;
// Aurora Lane Interface
input [0:3] SOFT_ERROR;
input [0:3] LANE_UP;
input [0:3] HARD_ERROR;
input [0:3] CHANNEL_BOND_LOAD;
input [0:7] GOT_A;
input [0:3] GOT_V;
output [0:3] GEN_A;
output [0:7] GEN_K;
output [0:7] GEN_R;
output [0:7] GEN_V;
output [0:3] RESET_LANES;
// System Interface
input USER_CLK;
input RESET;
input POWER_DOWN;
output CHANNEL_UP;
output START_RX;
output CHANNEL_SOFT_ERROR;
output CHANNEL_HARD_ERROR;
//*********************************Wire Declarations**********************************
wire gen_ver_i;
wire reset_channel_i;
wire did_ver_i;
//*********************************Main Body of Code**********************************
// State Machine for channel bonding and verification.
aur1_CHANNEL_INIT_SM channel_init_sm_i
(
// GTP Interface
.CH_BOND_DONE(CH_BOND_DONE),
.EN_CHAN_SYNC(EN_CHAN_SYNC),
// Aurora Lane Interface
.CHANNEL_BOND_LOAD(CHANNEL_BOND_LOAD),
.GOT_A(GOT_A),
.GOT_V(GOT_V),
.RESET_LANES(RESET_LANES),
// System Interface
.USER_CLK(USER_CLK),
.RESET(RESET),
.START_RX(START_RX),
.CHANNEL_UP(CHANNEL_UP),
// Idle and Verification Sequence Generator Interface
.DID_VER(did_ver_i),
.GEN_VER(gen_ver_i),
// Channel Error Management Module Interface
.RESET_CHANNEL(reset_channel_i)
);
// Idle and verification sequence generator module.
aur1_IDLE_AND_VER_GEN idle_and_ver_gen_i
(
// Channel Init SM Interface
.GEN_VER(gen_ver_i),
.DID_VER(did_ver_i),
// Aurora Lane Interface
.GEN_A(GEN_A),
.GEN_K(GEN_K),
.GEN_R(GEN_R),
.GEN_V(GEN_V),
// System Interface
.RESET(RESET),
.USER_CLK(USER_CLK)
);
// Channel Error Management module.
aur1_CHANNEL_ERROR_DETECT channel_error_detect_i
(
// Aurora Lane Interface
.SOFT_ERROR(SOFT_ERROR),
.HARD_ERROR(HARD_ERROR),
.LANE_UP(LANE_UP),
// System Interface
.USER_CLK(USER_CLK),
.POWER_DOWN(POWER_DOWN),
.CHANNEL_SOFT_ERROR(CHANNEL_SOFT_ERROR),
.CHANNEL_HARD_ERROR(CHANNEL_HARD_ERROR),
// Channel Init State Machine Interface
.RESET_CHANNEL(reset_channel_i)
);
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_lfsr72(
clk,
nrst,
ena,
word
);
input clk;
input nrst;
input ena;
output reg [71:0] word;
always @(posedge clk or negedge nrst) begin
if(~nrst) begin
word <= 72'hAAF0F0AA55F0F0AA55;
end
else if(ena) begin
word[71] <= word[0];
word[70:66] <= word[71:67];
word[65] <= word[66] ^ word[0];
word[64:25] <= word[65:26];
word[24] <= word[25] ^ word[0];
word[23:19] <= word[24:20];
word[18] <= word[19] ^ word[0];
word[17:0] <= word[18:1];
end
end
endmodule
|
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: frame_rate.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.1.0 Build 185 10/21/2015 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module frame_rate (
inclk0,
c0,
c1,
locked);
input inclk0;
output c0;
output c1;
output locked;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c1"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "10000"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.005000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "0.010000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.00500000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "0.01000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "frame_rate.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "10000"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "5000"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK1"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL frame_rate.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL frame_rate.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL frame_rate.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL frame_rate.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL frame_rate.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL frame_rate_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL frame_rate_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
//reads data and puts it on out
module usb_input(clk,reset,data,rd,rxf,out,newout,hold,state);
input clk, reset; //clock and reset
input [7:0] data; //the data pins from the USB fifo
input rxf; //the rxf pin from the USB fifo
output rd; //the rd pin from the USB fifo
reg rd;
output[7:0] out; //this is where data goes when it has been read from the fifo
reg[7:0] out;
output newout; //when this is high, out contains a new chunk of data
reg newout;
input hold; //as long as hold is high, this module sits
//still module and will not accept new data from the fifo
output state; //for debugging purposes
reg[3:0] state;
parameter RESET = 0; //state data
parameter WAIT = 1;
parameter WAIT2 = 2;
parameter WAIT3 = 3;
parameter DATA_COMING = 4;
parameter DATA_COMING_2 = 5;
parameter DATA_COMING_3 = 6;
parameter DATA_COMING_4 = 7;
parameter DATA_COMING_5 = 8;
parameter DATA_HERE = 9;
parameter DATA_LEAVING =10;
parameter DATA_LEAVING_2=11;
parameter DATA_LEAVING_3=12;
parameter DATA_LEAVING_4=13;
parameter DATA_LEAVING_5=14;
parameter DATA_LEAVING_6=15;
initial
state <= WAIT;
always @ (posedge clk)
if(reset)
begin
newout <= 0;
rd <= 1; //we can't read data
state <= WAIT;
end
else
if(~hold)
begin
newout <= 0;
case(state)
WAIT:
if(~rxf) //if rxf is low and nobody's asking us to wait then there is data waiting for us
begin
rd <= 1; //so ask for it
state <= WAIT2; //and start waiting for it
end
WAIT2:
if(~rxf) //double check
begin
rd <= 1;
state <= WAIT3;
end
else
state <= WAIT;
WAIT3:
if(~rxf) //and triple check (should only need one, but oh well...)
begin
rd <= 0;
state <= DATA_COMING;
end
else
state <= WAIT;
DATA_COMING: //once rd goes low we gotta wait a bit for the data to stabilize
state <= DATA_COMING_2;
DATA_COMING_2:
state <= DATA_COMING_3;
DATA_COMING_3:
state <= DATA_HERE;
DATA_HERE:
begin
out <= data; //the data is valid by now so read it
state <= DATA_LEAVING;
newout <= 1; //let folks know we've got new data
end
DATA_LEAVING: //wait a cycle to clear the data to make sure we latch onto it correctly
begin
//rd <= 1; // ORIGINAL
state <= DATA_LEAVING_2;
newout <= 0; //let folks know the data's a clock cycle old now
end
DATA_LEAVING_2: //wait another cycle to make sure that the RD to RD pre-charge time is met
state <= DATA_LEAVING_3;
DATA_LEAVING_3: //wait another cycle to make sure that the RD to RD pre-charge time is met
state <= DATA_LEAVING_4;
DATA_LEAVING_4: //wait another cycle to make sure that the RD to RD pre-charge time is met
state <= DATA_LEAVING_5;
DATA_LEAVING_5: //wait another cycle to make sure that the RD to RD pre-charge time is met
state <= DATA_LEAVING_6;
DATA_LEAVING_6: //wait another cycle to make sure that the RD to RD pre-charge time is met
begin
state <= WAIT;
rd <= 1;
end
default:
state <= WAIT;
endcase
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFXTP_PP_SYMBOL_V
`define SKY130_FD_SC_HS__DFXTP_PP_SYMBOL_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFXTP_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR2B_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__OR2B_PP_SYMBOL_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__or2b (
//# {{data|Data Signals}}
input A ,
input B_N ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR2B_PP_SYMBOL_V
|
module write(clk, vsel, write, writenum, C, mdata, sximm8, PC, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
parameter width= 1;
input clk, write;
input [1:0] vsel;
input [2:0] writenum;
input [7:0] PC;
input [15:0] C, mdata, sximm8;
output [15:0] reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7;
reg [15:0] data_in;
reg [7:0] regSelect;
//Update based on clock
//regSelect chooses which register to update -> 1 means update
always @(*) begin
case(writenum)
3'b000: regSelect= write? 8'b00000001: 8'b00000000; //if write= 1 and writenum= 000
3'b001: regSelect= write? 8'b00000010: 8'b00000000; //if write= 1 and writenum= 001
3'b010: regSelect= write? 8'b00000100: 8'b00000000; //if write= 1 and writenum= 010
3'b011: regSelect= write? 8'b00001000: 8'b00000000; //if write= 1 and writenum= 011
3'b100: regSelect= write? 8'b00010000: 8'b00000000; //if write= 1 and writenum= 100
3'b101: regSelect= write? 8'b00100000: 8'b00000000; //if write= 1 and writenum= 101
3'b110: regSelect= write? 8'b01000000: 8'b00000000; //if write= 1 and writenum= 110
3'b111: regSelect= write? 8'b10000000: 8'b00000000; //if write= 1 and writenum= 111
default: regSelect= {8{1'bx}}; //default all x
endcase
end
//Update registers on a clock
DFlipFlopAllow #(.width(width)) loadreg0Data(clk, regSelect[0], data_in, reg0);
DFlipFlopAllow #(.width(width)) loadreg1Data(clk, regSelect[1], data_in, reg1);
DFlipFlopAllow #(.width(width)) loadreg2Data(clk, regSelect[2], data_in, reg2);
DFlipFlopAllow #(.width(width)) loadreg3Data(clk, regSelect[3], data_in, reg3);
DFlipFlopAllow #(.width(width)) loadreg4Data(clk, regSelect[4], data_in, reg4);
DFlipFlopAllow #(.width(width)) loadreg5Data(clk, regSelect[5], data_in, reg5);
DFlipFlopAllow #(.width(width)) loadreg6Data(clk, regSelect[6], data_in, reg6);
DFlipFlopAllow #(.width(width)) loadreg7Data(clk, regSelect[7], data_in, reg7);
//update data_in depending on value of vsel
always @(*) begin
case(vsel)
2'b00: data_in= mdata;
2'b01: data_in= sximm8;
2'b10: data_in= {8'b00000000, PC};
2'b11: data_in= C;
default: data_in={16{1'bx}};
endcase
end
endmodule
|
/*
File: fifo_empty_block.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module fifo_empty_block (/*AUTOARG*/
// Outputs
rd_fifo_empty, rd_addr, rd_gray_pointer,
// Inputs
reset, rd_clk, rd_wr_gray_pointer, rd_read
);
parameter AW = 2; // Number of bits to access all the entries
//##########
//# INPUTS
//##########
input reset;
input rd_clk;
input [AW:0] rd_wr_gray_pointer;//from other clock domain
input rd_read;
//###########
//# OUTPUTS
//###########
output rd_fifo_empty;
output [AW-1:0] rd_addr;
output [AW:0] rd_gray_pointer;
//#########
//# REGS
//#########
reg [AW:0] rd_gray_pointer;
reg [AW:0] rd_binary_pointer;
reg rd_fifo_empty;
//##########
//# WIRES
//##########
wire rd_fifo_empty_next;
wire [AW:0] rd_binary_next;
wire [AW:0] rd_gray_next;
//Counter States
always @(posedge rd_clk or posedge reset)
if(reset)
begin
rd_binary_pointer[AW:0] <= {(AW+1){1'b0}};
rd_gray_pointer[AW:0] <= {(AW+1){1'b0}};
end
else if(rd_read)
begin
rd_binary_pointer[AW:0] <= rd_binary_next[AW:0];
rd_gray_pointer[AW:0] <= rd_gray_next[AW:0];
end
//Read Address
assign rd_addr[AW-1:0] = rd_binary_pointer[AW-1:0];
//Updating binary pointer
assign rd_binary_next[AW:0] = rd_binary_pointer[AW:0] +
{{(AW){1'b0}},rd_read};
//Gray Pointer Conversion (for more reliable synchronization)!
assign rd_gray_next[AW:0] = {1'b0,rd_binary_next[AW:1]} ^
rd_binary_next[AW:0];
//# FIFO empty indication
assign rd_fifo_empty_next = (rd_gray_next[AW:0]==rd_wr_gray_pointer[AW:0]);
always @ (posedge rd_clk or posedge reset)
if(reset)
rd_fifo_empty <= 1'b1;
else
rd_fifo_empty <= rd_fifo_empty_next;
endmodule // fifo_empty_block
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21O_LP_V
`define SKY130_FD_SC_LP__A21O_LP_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog wrapper for a21o with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a21o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21o_lp (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21o_lp (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21O_LP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2111O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__A2111O_BEHAVIORAL_PP_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a2111o (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , C1, B1, and0_out, D1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2111O_BEHAVIORAL_PP_V |
module bus_arb (
clk,
reset_,
mcs_addr,
mcs_ready,
mcs_wr_data,
mcs_wr_enable,
mcs_rd_data,
mcs_rd_enable,
mcs_byte_enable,
addr,
rnw,
req,
wr_data,
gpio_cs,
gpio_rd_data,
gpio_rdy,
disp_cs,
disp_rd_data,
disp_rdy,
uart_cs,
uart_rd_data,
uart_rdy);
input clk;
input reset_;
// Bus controller to distribute MicroBlaze IO bus to our own hardware modules.
// This circuit decodes the address bus and generates module-independent
// bus control signals to each hardware module (like display, uart, gpio)
// and provides a ready timeout function to prevent the CPU from waiting
// indefinitely for a response (as would be the case if software tried to
// access an unmapped memory location).
// MicroBlaze IO Bus
input [31:0] mcs_addr; // Address from MicroBlaze
output mcs_ready; // Request complete indicator to MicroBlaze
input [31:0] mcs_wr_data; // Write data from MicroBlaze
input mcs_wr_enable; // Write enable from MicroBlaze
output [31:0] mcs_rd_data; // Read data from hardware
input mcs_rd_enable; // Read enable from MicroBlaze
input [3:0] mcs_byte_enable; // Which byte(s) in 32-bit longword are being accessed
// Local IO Bus
output [7:0] addr; // Address to lsuc module
output rnw; // Read, not write, indicator
output req; // Bus request
output [7:0] wr_data; // Write data to lsuc module
output gpio_cs; // GPIO module chip select
input [7:0] gpio_rd_data; // Read data from GPIO module
input gpio_rdy; // Ready indicator from GPIO module
output disp_cs; // Display module chip select
input [7:0] disp_rd_data; // Read data from display module
input disp_rdy; // Ready indicator from display module
output uart_cs; // UART module chip select
input [7:0] uart_rd_data; // Read data from UART module
input uart_rdy; // Ready indicator from UART module
reg [31:0] mcs_rd_data;
reg mcs_ready;
reg [9:0] req_timeout_ctr;
assign addr = mcs_addr[7:0];
assign rnw = ~mcs_wr_enable;
assign req = mcs_rd_enable || mcs_wr_enable;
assign wr_data = mcs_wr_data[7:0];
// Top-level memory mapping
assign gpio_cs = mcs_addr[31:28] == 4'hc; // GPIO module mapped to 0x4000_00xx addresses
assign disp_cs = mcs_addr[31:28] == 4'hd; // Display module mapped to 0x4000_00xx addresses
assign uart_cs = mcs_addr[31:28] == 4'he; // UART module mapped to 0x4000_00xx addresses
// Readback generation
always@ (posedge clk or negedge reset_)
if (!reset_)
mcs_rd_data <= 32'h0000_0000;
else if (rnw && gpio_cs && gpio_rdy)
mcs_rd_data <= {4{gpio_rd_data}};
else if (rnw && disp_cs && disp_rdy)
mcs_rd_data <= {4{disp_rd_data}};
else if (rnw && uart_cs && uart_rdy)
mcs_rd_data <= {4{uart_rd_data}};
// Request ready generation
always@ (posedge clk or negedge reset_)
if (!reset_)
mcs_ready <= 1'b0;
else if (gpio_cs)
mcs_ready <= gpio_rdy;
else if (disp_cs)
mcs_ready <= disp_rdy;
else if (uart_cs)
mcs_ready <= uart_rdy;
else
mcs_ready <= &req_timeout_ctr;
// Request timeout generation (prevents CPU from locking if no harware responds to request)
always@ (posedge clk or negedge reset_)
if (!reset_)
req_timeout_ctr <= 10'd0;
else if (mcs_ready)
req_timeout_ctr <= 10'd0;
else if (req)
req_timeout_ctr <= 10'd1;
else if (req_timeout_ctr != 10'd0)
req_timeout_ctr <= req_timeout_ctr + 10'd1;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FILL_TB_V
`define SKY130_FD_SC_HD__FILL_TB_V
/**
* fill: Fill cell.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__fill.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_hd__fill dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__FILL_TB_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Thu Sep 14 11:02:39 2017
// Host : PC4719 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_0_stub.v
// Design : vio_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "vio,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_in0, probe_in1, probe_in2, probe_in3)
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_in1[0:0],probe_in2[0:0],probe_in3[0:0]" */;
input clk;
input [0:0]probe_in0;
input [0:0]probe_in1;
input [0:0]probe_in2;
input [0:0]probe_in3;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFRTN_FUNCTIONAL_V
`define SKY130_FD_SC_LP__DFRTN_FUNCTIONAL_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr/sky130_fd_sc_lp__udp_dff_pr.v"
`celldefine
module sky130_fd_sc_lp__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intclk, CLK_N );
sky130_fd_sc_lp__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, intclk, RESET);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFRTN_FUNCTIONAL_V |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_2_1_rport_7x.v
// Version : 1.8
//-- Description: 7-series solution wrapper : Root Port for PCI Express
//--
//--
//--
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module pcie_2_1_rport_7x # (
parameter CFG_VEND_ID = 16'h10ee,
parameter CFG_DEV_ID = 16'h7121,
parameter CFG_REV_ID = 8'h00,
parameter CFG_SUBSYS_VEND_ID = 16'h10ee,
parameter CFG_SUBSYS_ID = 16'h0007,
parameter PIPE_SIM_MODE = "FALSE",
// PCIE_2_1 params
parameter REF_CLK_FREQ = 0,
parameter PCIE_EXT_CLK = "FALSE",
parameter PIPE_PIPELINE_STAGES = 0,
parameter [11:0] AER_BASE_PTR = 12'h128,
parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
parameter [15:0] AER_CAP_ID = 16'h0001,
parameter AER_CAP_MULTIHEADER = "FALSE",
parameter [11:0] AER_CAP_NEXTPTR = 12'h160,
parameter AER_CAP_ON = "FALSE",
parameter [23:0] AER_CAP_OPTIONAL_ERR_SUPPORT = 24'h000000,
parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE",
parameter [3:0] AER_CAP_VERSION = 4'h1,
parameter ALLOW_X8_GEN2 = "FALSE",
parameter [31:0] BAR0 = 32'hFFFFFF00,
parameter [31:0] BAR1 = 32'hFFFF0000,
parameter [31:0] BAR2 = 32'hFFFF000C,
parameter [31:0] BAR3 = 32'hFFFFFFFF,
parameter [31:0] BAR4 = 32'h00000000,
parameter [31:0] BAR5 = 32'h00000000,
parameter C_DATA_WIDTH = 64,
parameter [7:0] CAPABILITIES_PTR = 8'h40,
parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000,
parameter CFG_ECRC_ERR_CPLSTAT = 0,
parameter [23:0] CLASS_CODE = 24'h000000,
parameter CMD_INTX_IMPLEMENTED = "TRUE",
parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE",
parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'h0,
parameter [6:0] CRM_MODULE_RSTS = 7'h00,
parameter DEV_CAP2_ARI_FORWARDING_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED = "FALSE",
parameter DEV_CAP2_CAS128_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED = "FALSE",
parameter DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED = "FALSE",
parameter DEV_CAP2_LTR_MECHANISM_SUPPORTED = "FALSE",
parameter [1:0] DEV_CAP2_MAX_ENDEND_TLP_PREFIXES = 2'h0,
parameter DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING = "FALSE",
parameter [1:0] DEV_CAP2_TPH_COMPLETER_SUPPORTED = 2'h0,
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "FALSE",
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "FALSE",
parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 0,
parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 0,
parameter DEV_CAP_EXT_TAG_SUPPORTED = "TRUE",
parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE",
parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2,
parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0,
parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE",
parameter integer DEV_CAP_RSVD_14_12 = 0,
parameter integer DEV_CAP_RSVD_17_16 = 0,
parameter integer DEV_CAP_RSVD_31_29 = 0,
parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE",
parameter DEV_CONTROL_EXT_TAG_DEFAULT = "FALSE",
parameter DISABLE_ASPM_L1_TIMER = "FALSE",
parameter DISABLE_BAR_FILTERING = "FALSE",
parameter DISABLE_ERR_MSG = "FALSE",
parameter DISABLE_ID_CHECK = "FALSE",
parameter DISABLE_LANE_REVERSAL = "FALSE",
parameter DISABLE_LOCKED_FILTER = "FALSE",
parameter DISABLE_PPM_FILTER = "FALSE",
parameter DISABLE_RX_POISONED_RESP = "FALSE",
parameter DISABLE_RX_TC_FILTER = "FALSE",
parameter DISABLE_SCRAMBLING = "FALSE",
parameter [7:0] DNSTREAM_LINK_NUM = 8'h00,
parameter [11:0] DSN_BASE_PTR = 12'h100,
parameter [15:0] DSN_CAP_ID = 16'h0003,
parameter [11:0] DSN_CAP_NEXTPTR = 12'h10C,
parameter DSN_CAP_ON = "TRUE",
parameter [3:0] DSN_CAP_VERSION = 4'h1,
parameter [10:0] ENABLE_MSG_ROUTE = 11'h000,
parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE",
parameter ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED = "FALSE",
parameter ENTER_RVRY_EI_L0 = "TRUE",
parameter EXIT_LOOPBACK_ON_EI = "TRUE",
parameter [31:0] EXPANSION_ROM = 32'hFFFFF001,
parameter [5:0] EXT_CFG_CAP_PTR = 6'h3F,
parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'h3FF,
parameter [7:0] HEADER_TYPE = 8'h01,
parameter [4:0] INFER_EI = 5'h00,
parameter [7:0] INTERRUPT_PIN = 8'h01,
parameter INTERRUPT_STAT_AUTO = "TRUE",
parameter IS_SWITCH = "FALSE",
parameter [9:0] LAST_CONFIG_DWORD = 10'h3FF,
parameter LINK_CAP_ASPM_OPTIONALITY = "TRUE",
parameter integer LINK_CAP_ASPM_SUPPORT = 1,
parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE",
parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE",
parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7,
parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7,
parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE",
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1,
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08,
parameter integer LINK_CAP_RSVD_23 = 0,
parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE",
parameter integer LINK_CONTROL_RCB = 0,
parameter LINK_CTRL2_DEEMPHASIS = "FALSE",
parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE",
parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'h2,
parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE",
parameter [14:0] LL_ACK_TIMEOUT = 15'h0000,
parameter LL_ACK_TIMEOUT_EN = "FALSE",
parameter integer LL_ACK_TIMEOUT_FUNC = 0,
parameter [14:0] LL_REPLAY_TIMEOUT = 15'h0000,
parameter LL_REPLAY_TIMEOUT_EN = "FALSE",
parameter integer LL_REPLAY_TIMEOUT_FUNC = 0,
parameter [5:0] LTSSM_MAX_LINK_WIDTH = LINK_CAP_MAX_LINK_WIDTH,
parameter MPS_FORCE = "FALSE",
parameter [7:0] MSIX_BASE_PTR = 8'h9C,
parameter [7:0] MSIX_CAP_ID = 8'h11,
parameter [7:0] MSIX_CAP_NEXTPTR = 8'h00,
parameter MSIX_CAP_ON = "FALSE",
parameter integer MSIX_CAP_PBA_BIR = 0,
parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'h000,
parameter [7:0] MSI_BASE_PTR = 8'h48,
parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE",
parameter [7:0] MSI_CAP_ID = 8'h05,
parameter integer MSI_CAP_MULTIMSGCAP = 0,
parameter integer MSI_CAP_MULTIMSG_EXTENSION = 0,
parameter [7:0] MSI_CAP_NEXTPTR = 8'h60,
parameter MSI_CAP_ON = "FALSE",
parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "TRUE",
parameter integer N_FTS_COMCLK_GEN1 = 255,
parameter integer N_FTS_COMCLK_GEN2 = 255,
parameter integer N_FTS_GEN1 = 255,
parameter integer N_FTS_GEN2 = 255,
parameter [7:0] PCIE_BASE_PTR = 8'h60,
parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'h10,
parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h2,
parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h4,
parameter [7:0] PCIE_CAP_NEXTPTR = 8'h9C,
parameter PCIE_CAP_ON = "TRUE",
parameter integer PCIE_CAP_RSVD_15_14 = 0,
parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE",
parameter integer PCIE_REVISION = 2,
parameter integer PL_AUTO_CONFIG = 0,
parameter PL_FAST_TRAIN = "FALSE",
parameter [14:0] PM_ASPML0S_TIMEOUT = 15'h0000,
parameter PM_ASPML0S_TIMEOUT_EN = "FALSE",
parameter integer PM_ASPML0S_TIMEOUT_FUNC = 0,
parameter PM_ASPM_FASTEXIT = "FALSE",
parameter [7:0] PM_BASE_PTR = 8'h40,
parameter integer PM_CAP_AUXCURRENT = 0,
parameter PM_CAP_D1SUPPORT = "TRUE",
parameter PM_CAP_D2SUPPORT = "TRUE",
parameter PM_CAP_DSI = "FALSE",
parameter [7:0] PM_CAP_ID = 8'h01,
parameter [7:0] PM_CAP_NEXTPTR = 8'h48,
parameter PM_CAP_ON = "TRUE",
parameter [4:0] PM_CAP_PMESUPPORT = 5'h0F,
parameter PM_CAP_PME_CLOCK = "FALSE",
parameter integer PM_CAP_RSVD_04 = 0,
parameter integer PM_CAP_VERSION = 3,
parameter PM_CSR_B2B3 = "FALSE",
parameter PM_CSR_BPCCEN = "FALSE",
parameter PM_CSR_NOSOFTRST = "TRUE",
parameter [7:0] PM_DATA0 = 8'h01,
parameter [7:0] PM_DATA1 = 8'h01,
parameter [7:0] PM_DATA2 = 8'h01,
parameter [7:0] PM_DATA3 = 8'h01,
parameter [7:0] PM_DATA4 = 8'h01,
parameter [7:0] PM_DATA5 = 8'h01,
parameter [7:0] PM_DATA6 = 8'h01,
parameter [7:0] PM_DATA7 = 8'h01,
parameter [1:0] PM_DATA_SCALE0 = 2'h1,
parameter [1:0] PM_DATA_SCALE1 = 2'h1,
parameter [1:0] PM_DATA_SCALE2 = 2'h1,
parameter [1:0] PM_DATA_SCALE3 = 2'h1,
parameter [1:0] PM_DATA_SCALE4 = 2'h1,
parameter [1:0] PM_DATA_SCALE5 = 2'h1,
parameter [1:0] PM_DATA_SCALE6 = 2'h1,
parameter [1:0] PM_DATA_SCALE7 = 2'h1,
parameter PM_MF = "FALSE",
parameter [11:0] RBAR_BASE_PTR = 12'h178,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR0 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR1 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR2 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR3 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR4 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR5 = 5'h00,
parameter [15:0] RBAR_CAP_ID = 16'h0015,
parameter [2:0] RBAR_CAP_INDEX0 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX1 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX2 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX3 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX4 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX5 = 3'h0,
parameter [11:0] RBAR_CAP_NEXTPTR = 12'h000,
parameter RBAR_CAP_ON = "FALSE",
parameter [31:0] RBAR_CAP_SUP0 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP1 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP2 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP3 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP4 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP5 = 32'h00000000,
parameter [3:0] RBAR_CAP_VERSION = 4'h1,
parameter [2:0] RBAR_NUM = 3'h1,
parameter integer RECRC_CHK = 0,
parameter RECRC_CHK_TRIM = "FALSE",
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1,
parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE",
parameter [1:0] RP_AUTO_SPD = 2'h1,
parameter [4:0] RP_AUTO_SPD_LOOPCNT = 5'h1f,
parameter SELECT_DLL_IF = "FALSE",
parameter SIM_VERSION = "1.0",
parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE",
parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE",
parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE",
parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE",
parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE",
parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE",
parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE",
parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000,
parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE",
parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE",
parameter integer SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0,
parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00,
parameter integer SPARE_BIT0 = 0,
parameter integer SPARE_BIT1 = 0,
parameter integer SPARE_BIT2 = 0,
parameter integer SPARE_BIT3 = 0,
parameter integer SPARE_BIT4 = 0,
parameter integer SPARE_BIT5 = 0,
parameter integer SPARE_BIT6 = 0,
parameter integer SPARE_BIT7 = 0,
parameter integer SPARE_BIT8 = 0,
parameter [7:0] SPARE_BYTE0 = 8'h00,
parameter [7:0] SPARE_BYTE1 = 8'h00,
parameter [7:0] SPARE_BYTE2 = 8'h00,
parameter [7:0] SPARE_BYTE3 = 8'h00,
parameter [31:0] SPARE_WORD0 = 32'h00000000,
parameter [31:0] SPARE_WORD1 = 32'h00000000,
parameter [31:0] SPARE_WORD2 = 32'h00000000,
parameter [31:0] SPARE_WORD3 = 32'h00000000,
parameter SSL_MESSAGE_AUTO = "FALSE",
parameter KEEP_WIDTH = C_DATA_WIDTH / 8,
parameter TECRC_EP_INV = "FALSE",
parameter TL_RBYPASS = "FALSE",
parameter integer TL_RX_RAM_RADDR_LATENCY = 0,
parameter integer TL_RX_RAM_RDATA_LATENCY = 2,
parameter integer TL_RX_RAM_WRITE_LATENCY = 0,
parameter TL_TFC_DISABLE = "FALSE",
parameter TL_TX_CHECKS_DISABLE = "FALSE",
parameter integer TL_TX_RAM_RADDR_LATENCY = 0,
parameter integer TL_TX_RAM_RDATA_LATENCY = 2,
parameter integer TL_TX_RAM_WRITE_LATENCY = 0,
parameter TRN_DW = "FALSE",
parameter TRN_NP_FC = "FALSE",
parameter UPCONFIG_CAPABLE = "TRUE",
parameter UPSTREAM_FACING = "FALSE",
parameter UR_ATOMIC = "TRUE",
parameter UR_CFG1 = "TRUE",
parameter UR_INV_REQ = "TRUE",
parameter UR_PRS_RESPONSE = "TRUE",
parameter USER_CLK2_DIV2 = "FALSE",
parameter integer USER_CLK_FREQ = 3,
parameter USE_RID_PINS = "FALSE",
parameter VC0_CPL_INFINITE = "TRUE",
parameter [12:0] VC0_RX_RAM_LIMIT = 13'h03FF,
parameter integer VC0_TOTAL_CREDITS_CD = 127,
parameter integer VC0_TOTAL_CREDITS_CH = 31,
parameter integer VC0_TOTAL_CREDITS_NPD = 24,
parameter integer VC0_TOTAL_CREDITS_NPH = 12,
parameter integer VC0_TOTAL_CREDITS_PD = 288,
parameter integer VC0_TOTAL_CREDITS_PH = 32,
parameter integer VC0_TX_LASTPACKET = 31,
parameter [11:0] VC_BASE_PTR = 12'h10C,
parameter [15:0] VC_CAP_ID = 16'h0002,
parameter [11:0] VC_CAP_NEXTPTR = 12'h128,
parameter VC_CAP_ON = "FALSE",
parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE",
parameter [3:0] VC_CAP_VERSION = 4'h1,
parameter [11:0] VSEC_BASE_PTR = 12'h160,
parameter [15:0] VSEC_CAP_HDR_ID = 16'h1234,
parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'h018,
parameter [3:0] VSEC_CAP_HDR_REVISION = 4'h1,
parameter [15:0] VSEC_CAP_ID = 16'h000B,
parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE",
parameter [11:0] VSEC_CAP_NEXTPTR = 12'h000,
parameter VSEC_CAP_ON = "FALSE",
parameter [3:0] VSEC_CAP_VERSION = 4'h1,
parameter PCIE_USE_MODE = "3.0",
parameter PCIE_GT_DEVICE = "GTX",
parameter PCIE_CHAN_BOND = 0,
parameter PCIE_PLL_SEL = "CPLL",
parameter PCIE_ASYNC_EN = "FALSE",
parameter PCIE_TXBUF_EN = "FALSE"
)
(
//-------------------------------------------------------
// 1. PCI Express (pci_exp) Interface
//-------------------------------------------------------
// Tx
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txn,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txp,
// Rx
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxn,
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxp,
//----------------------------------------------------------------------------------------------------------------//
// 2. Clock Inputs - For Partial Reconfig Support //
//----------------------------------------------------------------------------------------------------------------//
input PIPE_PCLK_IN,
input PIPE_RXUSRCLK_IN,
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PIPE_RXOUTCLK_IN,
input PIPE_DCLK_IN,
input PIPE_USERCLK1_IN,
input PIPE_USERCLK2_IN,
input PIPE_OOBCLK_IN,
input PIPE_MMCM_LOCK_IN,
output PIPE_TXOUTCLK_OUT,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PIPE_RXOUTCLK_OUT,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PIPE_PCLK_SEL_OUT,
output PIPE_GEN3_OUT,
//----------------------------------------------------------------------------------------------------------------//
// 3. AXI-S Interface //
//----------------------------------------------------------------------------------------------------------------//
// Common
output user_clk_out,
output reg user_reset_out,
output reg user_lnk_up,
// AXI TX
//-----------
output [5:0] tx_buf_av,
output tx_err_drop,
output tx_cfg_req,
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata,
input s_axis_tx_tvalid,
output s_axis_tx_tready,
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep,
input s_axis_tx_tlast,
input [3:0] s_axis_tx_tuser,
input tx_cfg_gnt,
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata,
output m_axis_rx_tvalid,
input m_axis_rx_tready,
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep,
output m_axis_rx_tlast,
output [21:0] m_axis_rx_tuser,
input rx_np_ok,
input rx_np_req,
// Flow Control
output [11:0] fc_cpld,
output [7:0] fc_cplh,
output [11:0] fc_npd,
output [7:0] fc_nph,
output [11:0] fc_pd,
output [7:0] fc_ph,
input [2:0] fc_sel,
//-------------------------------------------------------
// 4. Configuration (CFG) Interface
//-------------------------------------------------------
//------------------------------------------------//
// EP and RP //
//------------------------------------------------//
output wire [15:0] cfg_status,
output wire [15:0] cfg_command,
output wire [15:0] cfg_dstatus,
output wire [15:0] cfg_dcommand,
output wire [15:0] cfg_lstatus,
output wire [15:0] cfg_lcommand,
output wire [15:0] cfg_dcommand2,
output [2:0] cfg_pcie_link_state,
output wire cfg_pmcsr_pme_en,
output wire [1:0] cfg_pmcsr_powerstate,
output wire cfg_pmcsr_pme_status,
output wire cfg_received_func_lvl_rst,
// Management Interface
output wire [31:0] cfg_mgmt_do,
output wire cfg_mgmt_rd_wr_done,
input wire [31:0] cfg_mgmt_di,
input wire [3:0] cfg_mgmt_byte_en,
input wire [9:0] cfg_mgmt_dwaddr,
input wire cfg_mgmt_wr_en,
input wire cfg_mgmt_rd_en,
input wire cfg_mgmt_wr_readonly,
// Error Reporting Interface
input wire cfg_err_ecrc,
input wire cfg_err_ur,
input wire cfg_err_cpl_timeout,
input wire cfg_err_cpl_unexpect,
input wire cfg_err_cpl_abort,
input wire cfg_err_posted,
input wire cfg_err_cor,
input wire cfg_err_atomic_egress_blocked,
input wire cfg_err_internal_cor,
input wire cfg_err_malformed,
input wire cfg_err_mc_blocked,
input wire cfg_err_poisoned,
input wire cfg_err_norecovery,
input wire [47:0] cfg_err_tlp_cpl_header,
output wire cfg_err_cpl_rdy,
input wire cfg_err_locked,
input wire cfg_err_acs,
input wire cfg_err_internal_uncor,
input wire cfg_trn_pending,
input wire cfg_pm_halt_aspm_l0s,
input wire cfg_pm_halt_aspm_l1,
input wire cfg_pm_force_state_en,
input wire [1:0] cfg_pm_force_state,
input wire [63:0] cfg_dsn,
output cfg_msg_received,
output [15:0] cfg_msg_data,
//------------------------------------------------//
// EP Only //
//------------------------------------------------//
input wire cfg_interrupt,
output wire cfg_interrupt_rdy,
input wire cfg_interrupt_assert,
input wire [7:0] cfg_interrupt_di,
output wire [7:0] cfg_interrupt_do,
output wire [2:0] cfg_interrupt_mmenable,
output wire cfg_interrupt_msienable,
output wire cfg_interrupt_msixenable,
output wire cfg_interrupt_msixfm,
input wire cfg_interrupt_stat,
input wire [4:0] cfg_pciecap_interrupt_msgnum,
output cfg_to_turnoff,
input wire cfg_turnoff_ok,
output wire [7:0] cfg_bus_number,
output wire [4:0] cfg_device_number,
output wire [2:0] cfg_function_number,
input wire cfg_pm_wake,
output wire cfg_msg_received_pm_as_nak,
output wire cfg_msg_received_setslotpowerlimit,
//------------------------------------------------//
// RP Only //
//------------------------------------------------//
input wire cfg_pm_send_pme_to,
input wire [7:0] cfg_ds_bus_number,
input wire [4:0] cfg_ds_device_number,
input wire [2:0] cfg_ds_function_number,
input wire cfg_mgmt_wr_rw1c_as_rw,
output wire cfg_bridge_serr_en,
output wire cfg_slot_control_electromech_il_ctl_pulse,
output wire cfg_root_control_syserr_corr_err_en,
output wire cfg_root_control_syserr_non_fatal_err_en,
output wire cfg_root_control_syserr_fatal_err_en,
output wire cfg_root_control_pme_int_en,
output wire cfg_aer_rooterr_corr_err_reporting_en,
output wire cfg_aer_rooterr_non_fatal_err_reporting_en,
output wire cfg_aer_rooterr_fatal_err_reporting_en,
output wire cfg_aer_rooterr_corr_err_received,
output wire cfg_aer_rooterr_non_fatal_err_received,
output wire cfg_aer_rooterr_fatal_err_received,
output wire cfg_msg_received_err_cor,
output wire cfg_msg_received_err_non_fatal,
output wire cfg_msg_received_err_fatal,
output wire cfg_msg_received_pm_pme,
output wire cfg_msg_received_pme_to_ack,
output wire cfg_msg_received_assert_int_a,
output wire cfg_msg_received_assert_int_b,
output wire cfg_msg_received_assert_int_c,
output wire cfg_msg_received_assert_int_d,
output wire cfg_msg_received_deassert_int_a,
output wire cfg_msg_received_deassert_int_b,
output wire cfg_msg_received_deassert_int_c,
output wire cfg_msg_received_deassert_int_d,
//-------------------------------------------------------
// 5. Physical Layer Control and Status (PL) Interface
//-------------------------------------------------------
//------------------------------------------------//
// EP and RP //
//------------------------------------------------//
input wire [1:0] pl_directed_link_change,
input wire [1:0] pl_directed_link_width,
input wire pl_directed_link_speed,
input wire pl_directed_link_auton,
input wire pl_upstream_prefer_deemph,
output wire pl_sel_lnk_rate,
output wire [1:0] pl_sel_lnk_width,
output wire [5:0] pl_ltssm_state,
output wire [1:0] pl_lane_reversal_mode,
output wire pl_phy_lnk_up,
output wire [2:0] pl_tx_pm_state,
output wire [1:0] pl_rx_pm_state,
output wire pl_link_upcfg_cap,
output wire pl_link_gen2_cap,
output wire pl_link_partner_gen2_supported,
output wire [2:0] pl_initial_link_width,
output wire pl_directed_change_done,
//------------------------------------------------//
// EP Only //
//------------------------------------------------//
output wire pl_received_hot_rst,
//------------------------------------------------//
// RP Only //
//------------------------------------------------//
input wire pl_downstream_deemph_source,
input wire pl_transmit_hot_rst,
//----------------------------------------------------------------------------------------------------------------//
// 6. AER interface //
//----------------------------------------------------------------------------------------------------------------//
input wire [127:0] cfg_err_aer_headerlog,
input wire [4:0] cfg_aer_interrupt_msgnum,
output wire cfg_err_aer_headerlog_set,
output wire cfg_aer_ecrc_check_en,
output wire cfg_aer_ecrc_gen_en,
//----------------------------------------------------------------------------------------------------------------//
// 7. VC interface //
//----------------------------------------------------------------------------------------------------------------//
output wire [6:0] cfg_vc_tcvc_map,
//----------------------------------------------------------------------------------------------------------------//
// 8. System(SYS) Interface //
//----------------------------------------------------------------------------------------------------------------//
input wire sys_clk,
input wire sys_rst_n
);
wire user_clk;
wire user_clk2;
wire [15:0] cfg_vend_id = CFG_VEND_ID;
wire [15:0] cfg_dev_id = CFG_DEV_ID;
wire [7:0] cfg_rev_id = CFG_REV_ID;
wire [15:0] cfg_subsys_vend_id = CFG_SUBSYS_VEND_ID;
wire [15:0] cfg_subsys_id = CFG_SUBSYS_ID;
// PIPE Interface Wires
wire phy_rdy_n;
wire pipe_rx0_polarity_gt;
wire pipe_rx1_polarity_gt;
wire pipe_rx2_polarity_gt;
wire pipe_rx3_polarity_gt;
wire pipe_rx4_polarity_gt;
wire pipe_rx5_polarity_gt;
wire pipe_rx6_polarity_gt;
wire pipe_rx7_polarity_gt;
wire pipe_tx_deemph_gt;
wire [2:0] pipe_tx_margin_gt;
wire pipe_tx_rate_gt;
wire pipe_tx_rcvr_det_gt;
wire [1:0] pipe_tx0_char_is_k_gt;
wire pipe_tx0_compliance_gt;
wire [15:0] pipe_tx0_data_gt;
wire pipe_tx0_elec_idle_gt;
wire [1:0] pipe_tx0_powerdown_gt;
wire [1:0] pipe_tx1_char_is_k_gt;
wire pipe_tx1_compliance_gt;
wire [15:0] pipe_tx1_data_gt;
wire pipe_tx1_elec_idle_gt;
wire [1:0] pipe_tx1_powerdown_gt;
wire [1:0] pipe_tx2_char_is_k_gt;
wire pipe_tx2_compliance_gt;
wire [15:0] pipe_tx2_data_gt;
wire pipe_tx2_elec_idle_gt;
wire [1:0] pipe_tx2_powerdown_gt;
wire [1:0] pipe_tx3_char_is_k_gt;
wire pipe_tx3_compliance_gt;
wire [15:0] pipe_tx3_data_gt;
wire pipe_tx3_elec_idle_gt;
wire [1:0] pipe_tx3_powerdown_gt;
wire [1:0] pipe_tx4_char_is_k_gt;
wire pipe_tx4_compliance_gt;
wire [15:0] pipe_tx4_data_gt;
wire pipe_tx4_elec_idle_gt;
wire [1:0] pipe_tx4_powerdown_gt;
wire [1:0] pipe_tx5_char_is_k_gt;
wire pipe_tx5_compliance_gt;
wire [15:0] pipe_tx5_data_gt;
wire pipe_tx5_elec_idle_gt;
wire [1:0] pipe_tx5_powerdown_gt;
wire [1:0] pipe_tx6_char_is_k_gt;
wire pipe_tx6_compliance_gt;
wire [15:0] pipe_tx6_data_gt;
wire pipe_tx6_elec_idle_gt;
wire [1:0] pipe_tx6_powerdown_gt;
wire [1:0] pipe_tx7_char_is_k_gt;
wire pipe_tx7_compliance_gt;
wire [15:0] pipe_tx7_data_gt;
wire pipe_tx7_elec_idle_gt;
wire [1:0] pipe_tx7_powerdown_gt;
wire pipe_rx0_chanisaligned_gt;
wire [1:0] pipe_rx0_char_is_k_gt;
wire [15:0] pipe_rx0_data_gt;
wire pipe_rx0_elec_idle_gt;
wire pipe_rx0_phy_status_gt;
wire [2:0] pipe_rx0_status_gt;
wire pipe_rx0_valid_gt;
wire pipe_rx1_chanisaligned_gt;
wire [1:0] pipe_rx1_char_is_k_gt;
wire [15:0] pipe_rx1_data_gt;
wire pipe_rx1_elec_idle_gt;
wire pipe_rx1_phy_status_gt;
wire [2:0] pipe_rx1_status_gt;
wire pipe_rx1_valid_gt;
wire pipe_rx2_chanisaligned_gt;
wire [1:0] pipe_rx2_char_is_k_gt;
wire [15:0] pipe_rx2_data_gt;
wire pipe_rx2_elec_idle_gt;
wire pipe_rx2_phy_status_gt;
wire [2:0] pipe_rx2_status_gt;
wire pipe_rx2_valid_gt;
wire pipe_rx3_chanisaligned_gt;
wire [1:0] pipe_rx3_char_is_k_gt;
wire [15:0] pipe_rx3_data_gt;
wire pipe_rx3_elec_idle_gt;
wire pipe_rx3_phy_status_gt;
wire [2:0] pipe_rx3_status_gt;
wire pipe_rx3_valid_gt;
wire pipe_rx4_chanisaligned_gt;
wire [1:0] pipe_rx4_char_is_k_gt;
wire [15:0] pipe_rx4_data_gt;
wire pipe_rx4_elec_idle_gt;
wire pipe_rx4_phy_status_gt;
wire [2:0] pipe_rx4_status_gt;
wire pipe_rx4_valid_gt;
wire pipe_rx5_chanisaligned_gt;
wire [1:0] pipe_rx5_char_is_k_gt;
wire [15:0] pipe_rx5_data_gt;
wire pipe_rx5_elec_idle_gt;
wire pipe_rx5_phy_status_gt;
wire [2:0] pipe_rx5_status_gt;
wire pipe_rx5_valid_gt;
wire pipe_rx6_chanisaligned_gt;
wire [1:0] pipe_rx6_char_is_k_gt;
wire [15:0] pipe_rx6_data_gt;
wire pipe_rx6_elec_idle_gt;
wire pipe_rx6_phy_status_gt;
wire [2:0] pipe_rx6_status_gt;
wire pipe_rx6_valid_gt;
wire pipe_rx7_chanisaligned_gt;
wire [1:0] pipe_rx7_char_is_k_gt;
wire [15:0] pipe_rx7_data_gt;
wire pipe_rx7_elec_idle_gt;
wire pipe_rx7_phy_status_gt;
wire [2:0] pipe_rx7_status_gt;
wire pipe_rx7_valid_gt;
reg user_lnk_up_int;
reg user_reset_int;
wire user_rst_n;
reg pl_received_hot_rst_q;
wire pl_received_hot_rst_wire;
reg pl_phy_lnk_up_q;
wire pl_phy_lnk_up_wire;
wire sys_or_hot_rst;
wire trn_lnk_up;
// wire sys_rst_n;
wire [5:0] pl_ltssm_state_int;
localparam TCQ = 100;
// Assign outputs
assign pl_ltssm_state = pl_ltssm_state_int;
assign pl_received_hot_rst = pl_received_hot_rst_q;
assign pl_phy_lnk_up = pl_phy_lnk_up_q;
// Register block outputs pl_received_hot_rst and phy_lnk_up to ease timing on block output
assign sys_or_hot_rst = !sys_rst_n || pl_received_hot_rst_q;
always @(posedge user_clk_out)
begin
if (!sys_rst_n) begin
pl_received_hot_rst_q <= #TCQ 1'b0;
pl_phy_lnk_up_q <= #TCQ 1'b0;
end else begin
pl_received_hot_rst_q <= #TCQ pl_received_hot_rst_wire;
pl_phy_lnk_up_q <= #TCQ pl_phy_lnk_up_wire;
end
end
// Convert incomign reset from AXI required active High
// to active low as that is what is required by GT and PCIe Block
// assign sys_rst_n = ~sys_reset;
// Generate user_lnk_up
always @(posedge user_clk_out)
begin
if (!sys_rst_n) begin
user_lnk_up <= #TCQ 1'b0;
end else begin
user_lnk_up <= #TCQ user_lnk_up_int;
end
end
always @(posedge user_clk_out)
begin
if (!sys_rst_n) begin
user_lnk_up_int <= #TCQ 1'b0;
end else begin
user_lnk_up_int <= #TCQ trn_lnk_up;
end
end
// Generate user_reset_out
// Once user reset output of PCIE and Phy Layer is active, de-assert reset
// Only assert reset if system reset or hot reset is seen. Keep AXI backend/user application alive otherwise
always @(posedge user_clk_out or posedge sys_or_hot_rst)
begin
if (sys_or_hot_rst) begin
user_reset_int <= #TCQ 1'b1;
end else if (user_rst_n && pl_phy_lnk_up_q) begin
user_reset_int <= #TCQ 1'b0;
end
end
// Invert active low reset to active high AXI reset
always @(posedge user_clk_out or posedge sys_or_hot_rst)
begin
if (sys_or_hot_rst) begin
user_reset_out <= #TCQ 1'b1;
end else begin
user_reset_out <= #TCQ user_reset_int;
end
end
//--------------------------------------------------------------------------------------------------------------------//
// **** PCI Express Core Wrapper **** //
// The PCI Express Core Wrapper includes the following: //
// 1) AXI Streaming Bridge //
// 2) PCIE 2_1 Hard Block //
// 3) PCIE PIPE Interface Pipeline //
//--------------------------------------------------------------------------------------------------------------------//
pcie_core_pcie_top # (
.PIPE_PIPELINE_STAGES ( PIPE_PIPELINE_STAGES ),
.AER_BASE_PTR ( AER_BASE_PTR ),
.AER_CAP_ECRC_CHECK_CAPABLE ( AER_CAP_ECRC_CHECK_CAPABLE ),
.DEV_CAP_ROLE_BASED_ERROR ( DEV_CAP_ROLE_BASED_ERROR ),
.AER_CAP_ECRC_GEN_CAPABLE ( AER_CAP_ECRC_GEN_CAPABLE ),
.LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ( LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ),
.AER_CAP_ID ( AER_CAP_ID ),
.AER_CAP_MULTIHEADER ( AER_CAP_MULTIHEADER ),
.AER_CAP_NEXTPTR ( AER_CAP_NEXTPTR ),
.AER_CAP_ON ( AER_CAP_ON ),
.AER_CAP_OPTIONAL_ERR_SUPPORT ( AER_CAP_OPTIONAL_ERR_SUPPORT ),
.AER_CAP_PERMIT_ROOTERR_UPDATE ( AER_CAP_PERMIT_ROOTERR_UPDATE ),
.AER_CAP_VERSION ( AER_CAP_VERSION ),
.ALLOW_X8_GEN2 ( ALLOW_X8_GEN2 ),
.BAR0 ( BAR0 ),
.BAR1 ( BAR1 ),
.BAR2 ( BAR2 ),
.BAR3 ( BAR3 ),
.BAR4 ( BAR4 ),
.BAR5 ( BAR5 ),
.C_DATA_WIDTH ( C_DATA_WIDTH ),
.CAPABILITIES_PTR ( CAPABILITIES_PTR ),
.CARDBUS_CIS_POINTER ( CARDBUS_CIS_POINTER ),
.CFG_ECRC_ERR_CPLSTAT ( CFG_ECRC_ERR_CPLSTAT ),
.CLASS_CODE ( CLASS_CODE ),
.CMD_INTX_IMPLEMENTED ( CMD_INTX_IMPLEMENTED ),
.CPL_TIMEOUT_DISABLE_SUPPORTED ( CPL_TIMEOUT_DISABLE_SUPPORTED ),
.CPL_TIMEOUT_RANGES_SUPPORTED ( CPL_TIMEOUT_RANGES_SUPPORTED ),
.CRM_MODULE_RSTS ( CRM_MODULE_RSTS ),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ),
.DEV_CAP_ENDPOINT_L0S_LATENCY ( DEV_CAP_ENDPOINT_L0S_LATENCY ),
.DEV_CAP_ENDPOINT_L1_LATENCY ( DEV_CAP_ENDPOINT_L1_LATENCY ),
.DEV_CAP_EXT_TAG_SUPPORTED ( DEV_CAP_EXT_TAG_SUPPORTED ),
.DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ( DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ),
.DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ),
.DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ( DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ),
.DEV_CAP_RSVD_14_12 ( DEV_CAP_RSVD_14_12 ),
.DEV_CAP_RSVD_17_16 ( DEV_CAP_RSVD_17_16 ),
.DEV_CAP_RSVD_31_29 ( DEV_CAP_RSVD_31_29 ),
.DEV_CONTROL_AUX_POWER_SUPPORTED ( DEV_CONTROL_AUX_POWER_SUPPORTED ),
.DEV_CONTROL_EXT_TAG_DEFAULT ( DEV_CONTROL_EXT_TAG_DEFAULT ),
.DISABLE_ASPM_L1_TIMER ( DISABLE_ASPM_L1_TIMER ),
.DISABLE_BAR_FILTERING ( DISABLE_BAR_FILTERING ),
.DISABLE_ID_CHECK ( DISABLE_ID_CHECK ),
.DISABLE_LANE_REVERSAL ( DISABLE_LANE_REVERSAL ),
.DISABLE_RX_POISONED_RESP ( DISABLE_RX_POISONED_RESP ),
.DISABLE_RX_TC_FILTER ( DISABLE_RX_TC_FILTER ),
.DISABLE_SCRAMBLING ( DISABLE_SCRAMBLING ),
.DNSTREAM_LINK_NUM ( DNSTREAM_LINK_NUM ),
.DSN_BASE_PTR ( DSN_BASE_PTR ),
.DSN_CAP_ID ( DSN_CAP_ID ),
.DSN_CAP_NEXTPTR ( DSN_CAP_NEXTPTR ),
.DSN_CAP_ON ( DSN_CAP_ON ),
.DSN_CAP_VERSION ( DSN_CAP_VERSION ),
.DEV_CAP2_ARI_FORWARDING_SUPPORTED ( DEV_CAP2_ARI_FORWARDING_SUPPORTED ),
.DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED ( DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED ),
.DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED ( DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED ),
.DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED ( DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED ),
.DEV_CAP2_CAS128_COMPLETER_SUPPORTED ( DEV_CAP2_CAS128_COMPLETER_SUPPORTED ),
.DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED ( DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED ),
.DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED ( DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED ),
.DEV_CAP2_LTR_MECHANISM_SUPPORTED ( DEV_CAP2_LTR_MECHANISM_SUPPORTED ),
.DEV_CAP2_MAX_ENDEND_TLP_PREFIXES ( DEV_CAP2_MAX_ENDEND_TLP_PREFIXES ),
.DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING ( DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING ),
.DEV_CAP2_TPH_COMPLETER_SUPPORTED ( DEV_CAP2_TPH_COMPLETER_SUPPORTED ),
.DISABLE_ERR_MSG ( DISABLE_ERR_MSG ),
.DISABLE_LOCKED_FILTER ( DISABLE_LOCKED_FILTER ),
.DISABLE_PPM_FILTER ( DISABLE_PPM_FILTER ),
.ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED ( ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED ),
.ENABLE_MSG_ROUTE ( ENABLE_MSG_ROUTE ),
.ENABLE_RX_TD_ECRC_TRIM ( ENABLE_RX_TD_ECRC_TRIM ),
.ENTER_RVRY_EI_L0 ( ENTER_RVRY_EI_L0 ),
.EXIT_LOOPBACK_ON_EI ( EXIT_LOOPBACK_ON_EI ),
.EXPANSION_ROM ( EXPANSION_ROM ),
.EXT_CFG_CAP_PTR ( EXT_CFG_CAP_PTR ),
.EXT_CFG_XP_CAP_PTR ( EXT_CFG_XP_CAP_PTR ),
.HEADER_TYPE ( HEADER_TYPE ),
.INFER_EI ( INFER_EI ),
.INTERRUPT_PIN ( INTERRUPT_PIN ),
.INTERRUPT_STAT_AUTO ( INTERRUPT_STAT_AUTO ),
.IS_SWITCH ( IS_SWITCH ),
.LAST_CONFIG_DWORD ( LAST_CONFIG_DWORD ),
.LINK_CAP_ASPM_OPTIONALITY ( LINK_CAP_ASPM_OPTIONALITY ),
.LINK_CAP_ASPM_SUPPORT ( LINK_CAP_ASPM_SUPPORT ),
.LINK_CAP_CLOCK_POWER_MANAGEMENT ( LINK_CAP_CLOCK_POWER_MANAGEMENT ),
.LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ( LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ),
.LINK_CAP_L0S_EXIT_LATENCY_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_GEN1 ),
.LINK_CAP_L0S_EXIT_LATENCY_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_GEN2 ),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ),
.LINK_CAP_L1_EXIT_LATENCY_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_GEN1 ),
.LINK_CAP_L1_EXIT_LATENCY_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_GEN2 ),
.LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ( LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ),
.LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.LINK_CAP_RSVD_23 ( LINK_CAP_RSVD_23 ),
.LINK_CONTROL_RCB ( LINK_CONTROL_RCB ),
.LINK_CTRL2_DEEMPHASIS ( LINK_CTRL2_DEEMPHASIS ),
.LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ( LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ),
.LINK_CTRL2_TARGET_LINK_SPEED ( LINK_CTRL2_TARGET_LINK_SPEED ),
.LINK_STATUS_SLOT_CLOCK_CONFIG ( LINK_STATUS_SLOT_CLOCK_CONFIG ),
.LL_ACK_TIMEOUT ( LL_ACK_TIMEOUT ),
.LL_ACK_TIMEOUT_EN ( LL_ACK_TIMEOUT_EN ),
.LL_ACK_TIMEOUT_FUNC ( LL_ACK_TIMEOUT_FUNC ),
.LL_REPLAY_TIMEOUT ( LL_REPLAY_TIMEOUT ),
.LL_REPLAY_TIMEOUT_EN ( LL_REPLAY_TIMEOUT_EN ),
.LL_REPLAY_TIMEOUT_FUNC ( LL_REPLAY_TIMEOUT_FUNC ),
.LTSSM_MAX_LINK_WIDTH ( LTSSM_MAX_LINK_WIDTH ),
.MPS_FORCE ( MPS_FORCE),
.MSI_BASE_PTR ( MSI_BASE_PTR ),
.MSI_CAP_ID ( MSI_CAP_ID ),
.MSI_CAP_MULTIMSGCAP ( MSI_CAP_MULTIMSGCAP ),
.MSI_CAP_MULTIMSG_EXTENSION ( MSI_CAP_MULTIMSG_EXTENSION ),
.MSI_CAP_NEXTPTR ( MSI_CAP_NEXTPTR ),
.MSI_CAP_ON ( MSI_CAP_ON ),
.MSI_CAP_PER_VECTOR_MASKING_CAPABLE ( MSI_CAP_PER_VECTOR_MASKING_CAPABLE ),
.MSI_CAP_64_BIT_ADDR_CAPABLE ( MSI_CAP_64_BIT_ADDR_CAPABLE ),
.MSIX_BASE_PTR ( MSIX_BASE_PTR ),
.MSIX_CAP_ID ( MSIX_CAP_ID ),
.MSIX_CAP_NEXTPTR ( MSIX_CAP_NEXTPTR ),
.MSIX_CAP_ON ( MSIX_CAP_ON ),
.MSIX_CAP_PBA_BIR ( MSIX_CAP_PBA_BIR ),
.MSIX_CAP_PBA_OFFSET ( MSIX_CAP_PBA_OFFSET ),
.MSIX_CAP_TABLE_BIR ( MSIX_CAP_TABLE_BIR ),
.MSIX_CAP_TABLE_OFFSET ( MSIX_CAP_TABLE_OFFSET ),
.MSIX_CAP_TABLE_SIZE ( MSIX_CAP_TABLE_SIZE ),
.N_FTS_COMCLK_GEN1 ( N_FTS_COMCLK_GEN1 ),
.N_FTS_COMCLK_GEN2 ( N_FTS_COMCLK_GEN2 ),
.N_FTS_GEN1 ( N_FTS_GEN1 ),
.N_FTS_GEN2 ( N_FTS_GEN2 ),
.PCIE_BASE_PTR ( PCIE_BASE_PTR ),
.PCIE_CAP_CAPABILITY_ID ( PCIE_CAP_CAPABILITY_ID ),
.PCIE_CAP_CAPABILITY_VERSION ( PCIE_CAP_CAPABILITY_VERSION ),
.PCIE_CAP_DEVICE_PORT_TYPE ( PCIE_CAP_DEVICE_PORT_TYPE ),
.PCIE_CAP_NEXTPTR ( PCIE_CAP_NEXTPTR ),
.PCIE_CAP_ON ( PCIE_CAP_ON ),
.PCIE_CAP_RSVD_15_14 ( PCIE_CAP_RSVD_15_14 ),
.PCIE_CAP_SLOT_IMPLEMENTED ( PCIE_CAP_SLOT_IMPLEMENTED ),
.PCIE_REVISION ( PCIE_REVISION ),
.PL_AUTO_CONFIG ( PL_AUTO_CONFIG ),
.PL_FAST_TRAIN ( PL_FAST_TRAIN ),
.PM_ASPML0S_TIMEOUT ( PM_ASPML0S_TIMEOUT ),
.PM_ASPML0S_TIMEOUT_EN ( PM_ASPML0S_TIMEOUT_EN ),
.PM_ASPML0S_TIMEOUT_FUNC ( PM_ASPML0S_TIMEOUT_FUNC ),
.PM_ASPM_FASTEXIT ( PM_ASPM_FASTEXIT ),
.PM_BASE_PTR ( PM_BASE_PTR ),
.PM_CAP_AUXCURRENT ( PM_CAP_AUXCURRENT ),
.PM_CAP_D1SUPPORT ( PM_CAP_D1SUPPORT ),
.PM_CAP_D2SUPPORT ( PM_CAP_D2SUPPORT ),
.PM_CAP_DSI ( PM_CAP_DSI ),
.PM_CAP_ID ( PM_CAP_ID ),
.PM_CAP_NEXTPTR ( PM_CAP_NEXTPTR ),
.PM_CAP_ON ( PM_CAP_ON ),
.PM_CAP_PME_CLOCK ( PM_CAP_PME_CLOCK ),
.PM_CAP_PMESUPPORT ( PM_CAP_PMESUPPORT ),
.PM_CAP_RSVD_04 ( PM_CAP_RSVD_04 ),
.PM_CAP_VERSION ( PM_CAP_VERSION ),
.PM_CSR_B2B3 ( PM_CSR_B2B3 ),
.PM_CSR_BPCCEN ( PM_CSR_BPCCEN ),
.PM_CSR_NOSOFTRST ( PM_CSR_NOSOFTRST ),
.PM_DATA0 ( PM_DATA0 ),
.PM_DATA1 ( PM_DATA1 ),
.PM_DATA2 ( PM_DATA2 ),
.PM_DATA3 ( PM_DATA3 ),
.PM_DATA4 ( PM_DATA4 ),
.PM_DATA5 ( PM_DATA5 ),
.PM_DATA6 ( PM_DATA6 ),
.PM_DATA7 ( PM_DATA7 ),
.PM_DATA_SCALE0 ( PM_DATA_SCALE0 ),
.PM_DATA_SCALE1 ( PM_DATA_SCALE1 ),
.PM_DATA_SCALE2 ( PM_DATA_SCALE2 ),
.PM_DATA_SCALE3 ( PM_DATA_SCALE3 ),
.PM_DATA_SCALE4 ( PM_DATA_SCALE4 ),
.PM_DATA_SCALE5 ( PM_DATA_SCALE5 ),
.PM_DATA_SCALE6 ( PM_DATA_SCALE6 ),
.PM_DATA_SCALE7 ( PM_DATA_SCALE7 ),
.PM_MF ( PM_MF ),
.RBAR_BASE_PTR ( RBAR_BASE_PTR ),
.RBAR_CAP_CONTROL_ENCODEDBAR0 ( RBAR_CAP_CONTROL_ENCODEDBAR0 ),
.RBAR_CAP_CONTROL_ENCODEDBAR1 ( RBAR_CAP_CONTROL_ENCODEDBAR1 ),
.RBAR_CAP_CONTROL_ENCODEDBAR2 ( RBAR_CAP_CONTROL_ENCODEDBAR2 ),
.RBAR_CAP_CONTROL_ENCODEDBAR3 ( RBAR_CAP_CONTROL_ENCODEDBAR3 ),
.RBAR_CAP_CONTROL_ENCODEDBAR4 ( RBAR_CAP_CONTROL_ENCODEDBAR4 ),
.RBAR_CAP_CONTROL_ENCODEDBAR5 ( RBAR_CAP_CONTROL_ENCODEDBAR5 ),
.RBAR_CAP_ID ( RBAR_CAP_ID),
.RBAR_CAP_INDEX0 ( RBAR_CAP_INDEX0 ),
.RBAR_CAP_INDEX1 ( RBAR_CAP_INDEX1 ),
.RBAR_CAP_INDEX2 ( RBAR_CAP_INDEX2 ),
.RBAR_CAP_INDEX3 ( RBAR_CAP_INDEX3 ),
.RBAR_CAP_INDEX4 ( RBAR_CAP_INDEX4 ),
.RBAR_CAP_INDEX5 ( RBAR_CAP_INDEX5 ),
.RBAR_CAP_NEXTPTR ( RBAR_CAP_NEXTPTR ),
.RBAR_CAP_ON ( RBAR_CAP_ON ),
.RBAR_CAP_SUP0 ( RBAR_CAP_SUP0 ),
.RBAR_CAP_SUP1 ( RBAR_CAP_SUP1 ),
.RBAR_CAP_SUP2 ( RBAR_CAP_SUP2 ),
.RBAR_CAP_SUP3 ( RBAR_CAP_SUP3 ),
.RBAR_CAP_SUP4 ( RBAR_CAP_SUP4 ),
.RBAR_CAP_SUP5 ( RBAR_CAP_SUP5 ),
.RBAR_CAP_VERSION ( RBAR_CAP_VERSION ),
.RBAR_NUM ( RBAR_NUM ),
.RECRC_CHK ( RECRC_CHK ),
.RECRC_CHK_TRIM ( RECRC_CHK_TRIM ),
// .REF_CLK_FREQ ( REF_CLK_FREQ ),
.ROOT_CAP_CRS_SW_VISIBILITY ( ROOT_CAP_CRS_SW_VISIBILITY ),
.RP_AUTO_SPD ( RP_AUTO_SPD ),
.RP_AUTO_SPD_LOOPCNT ( RP_AUTO_SPD_LOOPCNT ),
.SELECT_DLL_IF ( SELECT_DLL_IF ),
.SLOT_CAP_ATT_BUTTON_PRESENT ( SLOT_CAP_ATT_BUTTON_PRESENT ),
.SLOT_CAP_ATT_INDICATOR_PRESENT ( SLOT_CAP_ATT_INDICATOR_PRESENT ),
.SLOT_CAP_ELEC_INTERLOCK_PRESENT ( SLOT_CAP_ELEC_INTERLOCK_PRESENT ),
.SLOT_CAP_HOTPLUG_CAPABLE ( SLOT_CAP_HOTPLUG_CAPABLE ),
.SLOT_CAP_HOTPLUG_SURPRISE ( SLOT_CAP_HOTPLUG_SURPRISE ),
.SLOT_CAP_MRL_SENSOR_PRESENT ( SLOT_CAP_MRL_SENSOR_PRESENT ),
.SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ( SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ),
.SLOT_CAP_PHYSICAL_SLOT_NUM ( SLOT_CAP_PHYSICAL_SLOT_NUM ),
.SLOT_CAP_POWER_CONTROLLER_PRESENT ( SLOT_CAP_POWER_CONTROLLER_PRESENT ),
.SLOT_CAP_POWER_INDICATOR_PRESENT ( SLOT_CAP_POWER_INDICATOR_PRESENT ),
.SLOT_CAP_SLOT_POWER_LIMIT_SCALE ( SLOT_CAP_SLOT_POWER_LIMIT_SCALE ),
.SLOT_CAP_SLOT_POWER_LIMIT_VALUE ( SLOT_CAP_SLOT_POWER_LIMIT_VALUE ),
.SPARE_BIT0 ( SPARE_BIT0 ),
.SPARE_BIT1 ( SPARE_BIT1 ),
.SPARE_BIT2 ( SPARE_BIT2 ),
.SPARE_BIT3 ( SPARE_BIT3 ),
.SPARE_BIT4 ( SPARE_BIT4 ),
.SPARE_BIT5 ( SPARE_BIT5 ),
.SPARE_BIT6 ( SPARE_BIT6 ),
.SPARE_BIT7 ( SPARE_BIT7 ),
.SPARE_BIT8 ( SPARE_BIT8 ),
.SPARE_BYTE0 ( SPARE_BYTE0 ),
.SPARE_BYTE1 ( SPARE_BYTE1 ),
.SPARE_BYTE2 ( SPARE_BYTE2 ),
.SPARE_BYTE3 ( SPARE_BYTE3 ),
.SPARE_WORD0 ( SPARE_WORD0 ),
.SPARE_WORD1 ( SPARE_WORD1 ),
.SPARE_WORD2 ( SPARE_WORD2 ),
.SPARE_WORD3 ( SPARE_WORD3 ),
.SSL_MESSAGE_AUTO ( SSL_MESSAGE_AUTO ),
.TECRC_EP_INV ( TECRC_EP_INV ),
.TL_RBYPASS ( TL_RBYPASS ),
.TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ),
.TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ),
.TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ),
.TL_TFC_DISABLE ( TL_TFC_DISABLE ),
.TL_TX_CHECKS_DISABLE ( TL_TX_CHECKS_DISABLE ),
.TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ),
.TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ),
.TL_TX_RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ),
.TRN_DW ( TRN_DW ),
.TRN_NP_FC ( TRN_NP_FC ),
.UPCONFIG_CAPABLE ( UPCONFIG_CAPABLE ),
.UPSTREAM_FACING ( UPSTREAM_FACING ),
.UR_ATOMIC ( UR_ATOMIC ),
.UR_CFG1 ( UR_CFG1 ),
.UR_INV_REQ ( UR_INV_REQ ),
.UR_PRS_RESPONSE ( UR_PRS_RESPONSE ),
.USER_CLK2_DIV2 ( USER_CLK2_DIV2 ),
.USER_CLK_FREQ ( USER_CLK_FREQ ),
.USE_RID_PINS ( USE_RID_PINS ),
.VC0_CPL_INFINITE ( VC0_CPL_INFINITE ),
.VC0_RX_RAM_LIMIT ( VC0_RX_RAM_LIMIT ),
.VC0_TOTAL_CREDITS_CD ( VC0_TOTAL_CREDITS_CD ),
.VC0_TOTAL_CREDITS_CH ( VC0_TOTAL_CREDITS_CH ),
.VC0_TOTAL_CREDITS_NPD ( VC0_TOTAL_CREDITS_NPD),
.VC0_TOTAL_CREDITS_NPH ( VC0_TOTAL_CREDITS_NPH ),
.VC0_TOTAL_CREDITS_PD ( VC0_TOTAL_CREDITS_PD ),
.VC0_TOTAL_CREDITS_PH ( VC0_TOTAL_CREDITS_PH ),
.VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ),
.VC_BASE_PTR ( VC_BASE_PTR ),
.VC_CAP_ID ( VC_CAP_ID ),
.VC_CAP_NEXTPTR ( VC_CAP_NEXTPTR ),
.VC_CAP_ON ( VC_CAP_ON ),
.VC_CAP_REJECT_SNOOP_TRANSACTIONS ( VC_CAP_REJECT_SNOOP_TRANSACTIONS ),
.VC_CAP_VERSION ( VC_CAP_VERSION ),
.VSEC_BASE_PTR ( VSEC_BASE_PTR ),
.VSEC_CAP_HDR_ID ( VSEC_CAP_HDR_ID ),
.VSEC_CAP_HDR_LENGTH ( VSEC_CAP_HDR_LENGTH ),
.VSEC_CAP_HDR_REVISION ( VSEC_CAP_HDR_REVISION ),
.VSEC_CAP_ID ( VSEC_CAP_ID ),
.VSEC_CAP_IS_LINK_VISIBLE ( VSEC_CAP_IS_LINK_VISIBLE ),
.VSEC_CAP_NEXTPTR ( VSEC_CAP_NEXTPTR ),
.VSEC_CAP_ON ( VSEC_CAP_ON ),
.VSEC_CAP_VERSION ( VSEC_CAP_VERSION )
// I/O
) pcie_top_i (
// AXI Interface
.user_clk_out ( user_clk_out ),
.user_reset ( user_reset_out ),
.user_lnk_up ( user_lnk_up ),
.user_rst_n ( user_rst_n ),
.trn_lnk_up ( trn_lnk_up ),
.tx_buf_av ( tx_buf_av ),
.tx_err_drop ( tx_err_drop ),
.tx_cfg_req ( tx_cfg_req ),
.s_axis_tx_tready ( s_axis_tx_tready ),
.s_axis_tx_tdata ( s_axis_tx_tdata ),
.s_axis_tx_tkeep ( s_axis_tx_tkeep ),
.s_axis_tx_tuser ( s_axis_tx_tuser ),
.s_axis_tx_tlast ( s_axis_tx_tlast ),
.s_axis_tx_tvalid ( s_axis_tx_tvalid ),
.tx_cfg_gnt ( trn_tcfg_gnt ),
.m_axis_rx_tdata ( m_axis_rx_tdata ),
.m_axis_rx_tkeep ( m_axis_rx_tkeep ),
.m_axis_rx_tlast ( m_axis_rx_tlast ),
.m_axis_rx_tvalid ( m_axis_rx_tvalid ),
.m_axis_rx_tready ( m_axis_rx_tready ),
.m_axis_rx_tuser ( m_axis_rx_tuser ),
.rx_np_ok ( rx_np_ok ),
.rx_np_req ( rx_np_req ),
.fc_cpld ( fc_cpld ),
.fc_cplh ( fc_cplh ),
.fc_npd ( fc_npd ),
.fc_nph ( fc_nph ),
.fc_pd ( fc_pd ),
.fc_ph ( fc_ph ),
.fc_sel ( fc_sel ),
.cfg_turnoff_ok ( cfg_turnoff_ok ),
.cfg_received_func_lvl_rst ( cfg_received_func_lvl_rst ),
.cm_rst_n ( 1'b1 ),
.func_lvl_rst_n ( 1'b1 ),
.lnk_clk_en ( ),
.cfg_dev_id ( cfg_dev_id ),
.cfg_vend_id ( cfg_vend_id ),
.cfg_rev_id ( cfg_rev_id ),
.cfg_subsys_id ( cfg_subsys_id ),
.cfg_subsys_vend_id ( cfg_subsys_vend_id ),
.cfg_pciecap_interrupt_msgnum ( cfg_pciecap_interrupt_msgnum ),
.cfg_bridge_serr_en ( cfg_bridge_serr_en ),
.cfg_command_bus_master_enable ( ),
.cfg_command_interrupt_disable ( ),
.cfg_command_io_enable ( ),
.cfg_command_mem_enable ( ),
.cfg_command_serr_en ( ),
.cfg_dev_control_aux_power_en ( ),
.cfg_dev_control_corr_err_reporting_en ( ),
.cfg_dev_control_enable_ro ( ),
.cfg_dev_control_ext_tag_en ( ),
.cfg_dev_control_fatal_err_reporting_en ( ),
.cfg_dev_control_max_payload ( ),
.cfg_dev_control_max_read_req ( ),
.cfg_dev_control_non_fatal_reporting_en ( ),
.cfg_dev_control_no_snoop_en ( ),
.cfg_dev_control_phantom_en ( ),
.cfg_dev_control_ur_err_reporting_en ( ),
.cfg_dev_control2_cpl_timeout_dis ( ),
.cfg_dev_control2_cpl_timeout_val ( ),
.cfg_dev_control2_ari_forward_en ( ),
.cfg_dev_control2_atomic_requester_en ( ),
.cfg_dev_control2_atomic_egress_block ( ),
.cfg_dev_control2_ido_req_en ( ),
.cfg_dev_control2_ido_cpl_en ( ),
.cfg_dev_control2_ltr_en ( ),
.cfg_dev_control2_tlp_prefix_block ( ),
.cfg_dev_status_corr_err_detected ( ),
.cfg_dev_status_fatal_err_detected ( ),
.cfg_dev_status_non_fatal_err_detected ( ),
.cfg_dev_status_ur_detected ( ),
.cfg_mgmt_do ( cfg_mgmt_do ),
.cfg_err_aer_headerlog_set ( cfg_err_aer_headerlog_set ),
.cfg_err_aer_headerlog ( cfg_err_aer_headerlog ),
.cfg_err_cpl_rdy ( cfg_err_cpl_rdy ),
.cfg_interrupt_do ( cfg_interrupt_do ),
.cfg_interrupt_mmenable ( cfg_interrupt_mmenable ),
.cfg_interrupt_msienable ( cfg_interrupt_msienable ),
.cfg_interrupt_msixenable ( cfg_interrupt_msixenable ),
.cfg_interrupt_msixfm ( cfg_interrupt_msixfm ),
.cfg_interrupt_rdy ( cfg_interrupt_rdy ),
.cfg_link_control_rcb ( ),
.cfg_link_control_aspm_control ( ),
.cfg_link_control_auto_bandwidth_int_en ( ),
.cfg_link_control_bandwidth_int_en ( ),
.cfg_link_control_clock_pm_en ( ),
.cfg_link_control_common_clock ( ),
.cfg_link_control_extended_sync ( ),
.cfg_link_control_hw_auto_width_dis ( ),
.cfg_link_control_link_disable ( ),
.cfg_link_control_retrain_link ( ),
.cfg_link_status_auto_bandwidth_status ( ),
.cfg_link_status_bandwidth_status ( ),
.cfg_link_status_current_speed ( ),
.cfg_link_status_dll_active ( ),
.cfg_link_status_link_training ( ),
.cfg_link_status_negotiated_width ( ),
.cfg_msg_data ( cfg_msg_data ),
.cfg_msg_received ( cfg_msg_received ),
.cfg_msg_received_assert_int_a ( cfg_msg_received_assert_int_a ),
.cfg_msg_received_assert_int_b ( cfg_msg_received_assert_int_b ),
.cfg_msg_received_assert_int_c ( cfg_msg_received_assert_int_c ),
.cfg_msg_received_assert_int_d ( cfg_msg_received_assert_int_d ),
.cfg_msg_received_deassert_int_a ( cfg_msg_received_deassert_int_a ),
.cfg_msg_received_deassert_int_b ( cfg_msg_received_deassert_int_b ),
.cfg_msg_received_deassert_int_c ( cfg_msg_received_deassert_int_c ),
.cfg_msg_received_deassert_int_d ( cfg_msg_received_deassert_int_d ),
.cfg_msg_received_err_cor ( cfg_msg_received_err_cor ),
.cfg_msg_received_err_fatal ( cfg_msg_received_err_fatal ),
.cfg_msg_received_err_non_fatal ( cfg_msg_received_err_non_fatal ),
.cfg_msg_received_pm_as_nak ( cfg_msg_received_pm_as_nak ),
.cfg_msg_received_pme_to ( ),
.cfg_msg_received_pme_to_ack ( cfg_msg_received_pme_to_ack ),
.cfg_msg_received_pm_pme ( cfg_msg_received_pm_pme ),
.cfg_msg_received_setslotpowerlimit ( cfg_msg_received_setslotpowerlimit ),
.cfg_msg_received_unlock ( ),
.cfg_to_turnoff ( cfg_to_turnoff ),
.cfg_status ( cfg_status ),
.cfg_command ( cfg_command ),
.cfg_dstatus ( cfg_dstatus ),
.cfg_dcommand ( cfg_dcommand ),
.cfg_lstatus ( cfg_lstatus ),
.cfg_lcommand ( cfg_lcommand ),
.cfg_dcommand2 ( cfg_dcommand2 ),
.cfg_pcie_link_state ( cfg_pcie_link_state ),
.cfg_pmcsr_pme_en ( cfg_pmcsr_pme_en ),
.cfg_pmcsr_powerstate ( cfg_pmcsr_powerstate ),
.cfg_pmcsr_pme_status ( cfg_pmcsr_pme_status ),
.cfg_pm_rcv_as_req_l1_n ( ),
.cfg_pm_rcv_enter_l1_n ( ),
.cfg_pm_rcv_enter_l23_n ( ),
.cfg_pm_rcv_req_ack_n ( ),
.cfg_mgmt_rd_wr_done ( cfg_mgmt_rd_wr_done ),
.cfg_slot_control_electromech_il_ctl_pulse ( cfg_slot_control_electromech_il_ctl_pulse ),
.cfg_root_control_syserr_corr_err_en ( cfg_root_control_syserr_corr_err_en ),
.cfg_root_control_syserr_non_fatal_err_en ( cfg_root_control_syserr_non_fatal_err_en ),
.cfg_root_control_syserr_fatal_err_en ( cfg_root_control_syserr_fatal_err_en ),
.cfg_root_control_pme_int_en ( cfg_root_control_pme_int_en),
.cfg_aer_ecrc_check_en ( cfg_aer_ecrc_check_en ),
.cfg_aer_ecrc_gen_en ( cfg_aer_ecrc_gen_en ),
.cfg_aer_rooterr_corr_err_reporting_en ( cfg_aer_rooterr_corr_err_reporting_en ),
.cfg_aer_rooterr_non_fatal_err_reporting_en ( cfg_aer_rooterr_non_fatal_err_reporting_en ),
.cfg_aer_rooterr_fatal_err_reporting_en ( cfg_aer_rooterr_fatal_err_reporting_en ),
.cfg_aer_rooterr_corr_err_received ( cfg_aer_rooterr_corr_err_received ),
.cfg_aer_rooterr_non_fatal_err_received ( cfg_aer_rooterr_non_fatal_err_received ),
.cfg_aer_rooterr_fatal_err_received ( cfg_aer_rooterr_fatal_err_received ),
.cfg_aer_interrupt_msgnum ( cfg_aer_interrupt_msgnum ),
.cfg_transaction ( ),
.cfg_transaction_addr ( ),
.cfg_transaction_type ( ),
.cfg_vc_tcvc_map ( cfg_vc_tcvc_map ),
.cfg_mgmt_byte_en_n ( ~cfg_mgmt_byte_en ),
.cfg_mgmt_di ( cfg_mgmt_di ),
.cfg_dsn ( cfg_dsn ),
.cfg_mgmt_dwaddr ( cfg_mgmt_dwaddr ),
.cfg_err_acs_n ( 1'b1 ),
.cfg_err_cor_n ( ~cfg_err_cor ),
.cfg_err_cpl_abort_n ( ~cfg_err_cpl_abort ),
.cfg_err_cpl_timeout_n ( ~cfg_err_cpl_timeout ),
.cfg_err_cpl_unexpect_n ( ~cfg_err_cpl_unexpect ),
.cfg_err_ecrc_n ( ~cfg_err_ecrc ),
.cfg_err_locked_n ( ~cfg_err_locked ),
.cfg_err_posted_n ( ~cfg_err_posted ),
.cfg_err_tlp_cpl_header ( cfg_err_tlp_cpl_header ),
.cfg_err_ur_n ( ~cfg_err_ur ),
.cfg_err_malformed_n ( ~cfg_err_malformed ),
.cfg_err_poisoned_n ( ~cfg_err_poisoned ),
.cfg_err_atomic_egress_blocked_n ( ~cfg_err_atomic_egress_blocked ),
.cfg_err_mc_blocked_n ( ~cfg_err_mc_blocked ),
.cfg_err_internal_uncor_n ( ~cfg_err_internal_uncor ),
.cfg_err_internal_cor_n ( ~cfg_err_internal_cor ),
.cfg_err_norecovery_n ( ~cfg_err_norecovery ),
.cfg_interrupt_assert_n ( ~cfg_interrupt_assert ),
.cfg_interrupt_di ( cfg_interrupt_di ),
.cfg_interrupt_n ( ~cfg_interrupt ),
.cfg_interrupt_stat_n ( ~cfg_interrupt_stat ),
.cfg_bus_number ( cfg_bus_number ),
.cfg_device_number ( cfg_device_number ),
.cfg_function_number ( cfg_function_number ),
.cfg_ds_bus_number ( cfg_ds_bus_number ),
.cfg_ds_device_number ( cfg_ds_device_number ),
.cfg_ds_function_number ( cfg_ds_function_number ),
.cfg_pm_send_pme_to_n ( 1'b1 ),
.cfg_pm_wake_n ( ~cfg_pm_wake ),
.cfg_pm_halt_aspm_l0s_n ( ~cfg_pm_halt_aspm_l0s ),
.cfg_pm_halt_aspm_l1_n ( ~cfg_pm_halt_aspm_l1 ),
.cfg_pm_force_state_en_n ( ~cfg_pm_force_state_en),
.cfg_pm_force_state ( cfg_pm_force_state ),
.cfg_force_mps ( 3'b0 ),
.cfg_force_common_clock_off ( 1'b0 ),
.cfg_force_extended_sync_on ( 1'b0 ),
.cfg_port_number ( 8'b0 ),
.cfg_mgmt_rd_en_n ( ~cfg_mgmt_rd_en ),
.cfg_trn_pending ( cfg_trn_pending ),
.cfg_mgmt_wr_en_n ( ~cfg_mgmt_wr_en ),
.cfg_mgmt_wr_readonly_n ( ~cfg_mgmt_wr_readonly ),
.cfg_mgmt_wr_rw1c_as_rw_n ( ~cfg_mgmt_wr_rw1c_as_rw ),
.pl_initial_link_width ( pl_initial_link_width ),
.pl_lane_reversal_mode ( pl_lane_reversal_mode ),
.pl_link_gen2_cap ( pl_link_gen2_cap ),
.pl_link_partner_gen2_supported ( pl_link_partner_gen2_supported ),
.pl_link_upcfg_cap ( pl_link_upcfg_cap ),
.pl_ltssm_state ( pl_ltssm_state_int ),
.pl_phy_lnk_up ( pl_phy_lnk_up_wire ),
.pl_received_hot_rst ( pl_received_hot_rst_wire ),
.pl_rx_pm_state ( pl_rx_pm_state ),
.pl_sel_lnk_rate ( pl_sel_lnk_rate ),
.pl_sel_lnk_width ( pl_sel_lnk_width ),
.pl_tx_pm_state ( pl_tx_pm_state ),
.pl_directed_link_auton ( pl_directed_link_auton ),
.pl_directed_link_change ( pl_directed_link_change ),
.pl_directed_link_speed ( pl_directed_link_speed ),
.pl_directed_link_width ( pl_directed_link_width ),
.pl_downstream_deemph_source ( pl_downstream_deemph_source ),
.pl_upstream_prefer_deemph ( pl_upstream_prefer_deemph ),
.pl_transmit_hot_rst ( pl_transmit_hot_rst ),
.pl_directed_ltssm_new_vld ( 1'b0 ),
.pl_directed_ltssm_new ( 6'b0 ),
.pl_directed_ltssm_stall ( 1'b0 ),
.pl_directed_change_done ( pl_directed_change_done ),
.phy_rdy_n ( phy_rdy_n ),
.dbg_sclr_a ( ),
.dbg_sclr_b ( ),
.dbg_sclr_c ( ),
.dbg_sclr_d ( ),
.dbg_sclr_e ( ),
.dbg_sclr_f ( ),
.dbg_sclr_g ( ),
.dbg_sclr_h ( ),
.dbg_sclr_i ( ),
.dbg_sclr_j ( ),
.dbg_sclr_k ( ),
.dbg_vec_a ( ),
.dbg_vec_b ( ),
.dbg_vec_c ( ),
.pl_dbg_vec ( ),
.trn_rdllp_data ( ),
.trn_rdllp_src_rdy ( ),
.dbg_mode ( ),
.dbg_sub_mode ( ),
.pl_dbg_mode ( ),
.drp_clk ( 1'b0 ),
.drp_do ( ),
.drp_rdy ( ),
.drp_addr ( 9'b0 ),
.drp_en ( 1'b0 ),
.drp_di ( 16'b0 ),
.drp_we ( 1'b0 ),
// Pipe Interface
.pipe_clk ( pipe_clk ),
.user_clk ( user_clk ),
.user_clk2 ( user_clk2 ),
.pipe_rx0_polarity_gt ( pipe_rx0_polarity_gt ),
.pipe_rx1_polarity_gt ( pipe_rx1_polarity_gt ),
.pipe_rx2_polarity_gt ( pipe_rx2_polarity_gt ),
.pipe_rx3_polarity_gt ( pipe_rx3_polarity_gt ),
.pipe_rx4_polarity_gt ( pipe_rx4_polarity_gt ),
.pipe_rx5_polarity_gt ( pipe_rx5_polarity_gt ),
.pipe_rx6_polarity_gt ( pipe_rx6_polarity_gt ),
.pipe_rx7_polarity_gt ( pipe_rx7_polarity_gt ),
.pipe_tx_deemph_gt ( pipe_tx_deemph_gt ),
.pipe_tx_margin_gt ( pipe_tx_margin_gt ),
.pipe_tx_rate_gt ( pipe_tx_rate_gt ),
.pipe_tx_rcvr_det_gt ( pipe_tx_rcvr_det_gt ),
.pipe_tx0_char_is_k_gt ( pipe_tx0_char_is_k_gt ),
.pipe_tx0_compliance_gt ( pipe_tx0_compliance_gt ),
.pipe_tx0_data_gt ( pipe_tx0_data_gt ),
.pipe_tx0_elec_idle_gt ( pipe_tx0_elec_idle_gt ),
.pipe_tx0_powerdown_gt ( pipe_tx0_powerdown_gt ),
.pipe_tx1_char_is_k_gt ( pipe_tx1_char_is_k_gt ),
.pipe_tx1_compliance_gt ( pipe_tx1_compliance_gt ),
.pipe_tx1_data_gt ( pipe_tx1_data_gt ),
.pipe_tx1_elec_idle_gt ( pipe_tx1_elec_idle_gt ),
.pipe_tx1_powerdown_gt ( pipe_tx1_powerdown_gt ),
.pipe_tx2_char_is_k_gt ( pipe_tx2_char_is_k_gt ),
.pipe_tx2_compliance_gt ( pipe_tx2_compliance_gt ),
.pipe_tx2_data_gt ( pipe_tx2_data_gt ),
.pipe_tx2_elec_idle_gt ( pipe_tx2_elec_idle_gt ),
.pipe_tx2_powerdown_gt ( pipe_tx2_powerdown_gt ),
.pipe_tx3_char_is_k_gt ( pipe_tx3_char_is_k_gt ),
.pipe_tx3_compliance_gt ( pipe_tx3_compliance_gt ),
.pipe_tx3_data_gt ( pipe_tx3_data_gt ),
.pipe_tx3_elec_idle_gt ( pipe_tx3_elec_idle_gt ),
.pipe_tx3_powerdown_gt ( pipe_tx3_powerdown_gt ),
.pipe_tx4_char_is_k_gt ( pipe_tx4_char_is_k_gt ),
.pipe_tx4_compliance_gt ( pipe_tx4_compliance_gt ),
.pipe_tx4_data_gt ( pipe_tx4_data_gt ),
.pipe_tx4_elec_idle_gt ( pipe_tx4_elec_idle_gt ),
.pipe_tx4_powerdown_gt ( pipe_tx4_powerdown_gt ),
.pipe_tx5_char_is_k_gt ( pipe_tx5_char_is_k_gt ),
.pipe_tx5_compliance_gt ( pipe_tx5_compliance_gt ),
.pipe_tx5_data_gt ( pipe_tx5_data_gt ),
.pipe_tx5_elec_idle_gt ( pipe_tx5_elec_idle_gt ),
.pipe_tx5_powerdown_gt ( pipe_tx5_powerdown_gt ),
.pipe_tx6_char_is_k_gt ( pipe_tx6_char_is_k_gt ),
.pipe_tx6_compliance_gt ( pipe_tx6_compliance_gt ),
.pipe_tx6_data_gt ( pipe_tx6_data_gt ),
.pipe_tx6_elec_idle_gt ( pipe_tx6_elec_idle_gt ),
.pipe_tx6_powerdown_gt ( pipe_tx6_powerdown_gt ),
.pipe_tx7_char_is_k_gt ( pipe_tx7_char_is_k_gt ),
.pipe_tx7_compliance_gt ( pipe_tx7_compliance_gt ),
.pipe_tx7_data_gt ( pipe_tx7_data_gt ),
.pipe_tx7_elec_idle_gt ( pipe_tx7_elec_idle_gt ),
.pipe_tx7_powerdown_gt ( pipe_tx7_powerdown_gt ),
.pipe_rx0_chanisaligned_gt ( pipe_rx0_chanisaligned_gt ),
.pipe_rx0_char_is_k_gt ( pipe_rx0_char_is_k_gt ),
.pipe_rx0_data_gt ( pipe_rx0_data_gt ),
.pipe_rx0_elec_idle_gt ( pipe_rx0_elec_idle_gt ),
.pipe_rx0_phy_status_gt ( pipe_rx0_phy_status_gt ),
.pipe_rx0_status_gt ( pipe_rx0_status_gt ),
.pipe_rx0_valid_gt ( pipe_rx0_valid_gt ),
.pipe_rx1_chanisaligned_gt ( pipe_rx1_chanisaligned_gt ),
.pipe_rx1_char_is_k_gt ( pipe_rx1_char_is_k_gt ),
.pipe_rx1_data_gt ( pipe_rx1_data_gt ),
.pipe_rx1_elec_idle_gt ( pipe_rx1_elec_idle_gt ),
.pipe_rx1_phy_status_gt ( pipe_rx1_phy_status_gt ),
.pipe_rx1_status_gt ( pipe_rx1_status_gt ),
.pipe_rx1_valid_gt ( pipe_rx1_valid_gt ),
.pipe_rx2_chanisaligned_gt ( pipe_rx2_chanisaligned_gt ),
.pipe_rx2_char_is_k_gt ( pipe_rx2_char_is_k_gt ),
.pipe_rx2_data_gt ( pipe_rx2_data_gt ),
.pipe_rx2_elec_idle_gt ( pipe_rx2_elec_idle_gt ),
.pipe_rx2_phy_status_gt ( pipe_rx2_phy_status_gt ),
.pipe_rx2_status_gt ( pipe_rx2_status_gt ),
.pipe_rx2_valid_gt ( pipe_rx2_valid_gt ),
.pipe_rx3_chanisaligned_gt ( pipe_rx3_chanisaligned_gt ),
.pipe_rx3_char_is_k_gt ( pipe_rx3_char_is_k_gt ),
.pipe_rx3_data_gt ( pipe_rx3_data_gt ),
.pipe_rx3_elec_idle_gt ( pipe_rx3_elec_idle_gt ),
.pipe_rx3_phy_status_gt ( pipe_rx3_phy_status_gt ),
.pipe_rx3_status_gt ( pipe_rx3_status_gt ),
.pipe_rx3_valid_gt ( pipe_rx3_valid_gt ),
.pipe_rx4_chanisaligned_gt ( pipe_rx4_chanisaligned_gt ),
.pipe_rx4_char_is_k_gt ( pipe_rx4_char_is_k_gt ),
.pipe_rx4_data_gt ( pipe_rx4_data_gt ),
.pipe_rx4_elec_idle_gt ( pipe_rx4_elec_idle_gt ),
.pipe_rx4_phy_status_gt ( pipe_rx4_phy_status_gt ),
.pipe_rx4_status_gt ( pipe_rx4_status_gt ),
.pipe_rx4_valid_gt ( pipe_rx4_valid_gt ),
.pipe_rx5_chanisaligned_gt ( pipe_rx5_chanisaligned_gt ),
.pipe_rx5_char_is_k_gt ( pipe_rx5_char_is_k_gt ),
.pipe_rx5_data_gt ( pipe_rx5_data_gt ),
.pipe_rx5_elec_idle_gt ( pipe_rx5_elec_idle_gt ),
.pipe_rx5_phy_status_gt ( pipe_rx5_phy_status_gt ),
.pipe_rx5_status_gt ( pipe_rx5_status_gt ),
.pipe_rx5_valid_gt ( pipe_rx5_valid_gt ),
.pipe_rx6_chanisaligned_gt ( pipe_rx6_chanisaligned_gt ),
.pipe_rx6_char_is_k_gt ( pipe_rx6_char_is_k_gt ),
.pipe_rx6_data_gt ( pipe_rx6_data_gt ),
.pipe_rx6_elec_idle_gt ( pipe_rx6_elec_idle_gt ),
.pipe_rx6_phy_status_gt ( pipe_rx6_phy_status_gt ),
.pipe_rx6_status_gt ( pipe_rx6_status_gt ),
.pipe_rx6_valid_gt ( pipe_rx6_valid_gt ),
.pipe_rx7_chanisaligned_gt ( pipe_rx7_chanisaligned_gt ),
.pipe_rx7_char_is_k_gt ( pipe_rx7_char_is_k_gt ),
.pipe_rx7_data_gt ( pipe_rx7_data_gt ),
.pipe_rx7_elec_idle_gt ( pipe_rx7_elec_idle_gt ),
.pipe_rx7_phy_status_gt ( pipe_rx7_phy_status_gt ),
.pipe_rx7_status_gt ( pipe_rx7_status_gt ),
.pipe_rx7_valid_gt ( pipe_rx7_valid_gt )
);
//--------------------------------------------------------------------------------------------------------------------//
// **** Virtex7 GTX Wrapper **** //
// The Virtex7 GTX Wrapper includes the following: //
// 1) Virtex-7 GTX //
//--------------------------------------------------------------------------------------------------------------------//
// Selection of pipe_sim should instantiate both gt_top & gt_top_pipe_mode modules, If not selected then only gt_top//
// Printed the code such a way that bydefault it will keep gt_top and gt_top & gt_top_pipe_mode on pipe_sim mode //
//------------------------------------------------------------------------------------------------------------------//
generate
if (PIPE_SIM_MODE == "FALSE")
begin : gt_top
pcie_core_gt_top #(
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.REF_CLK_FREQ ( REF_CLK_FREQ ),
.USER_CLK_FREQ ( USER_CLK_FREQ ),
.USER_CLK2_DIV2 ( USER_CLK2_DIV2 ),
.PL_FAST_TRAIN ( PL_FAST_TRAIN ),
.PCIE_EXT_CLK ( PCIE_EXT_CLK ),
.PCIE_USE_MODE ( PCIE_USE_MODE ),
.PCIE_GT_DEVICE ( PCIE_GT_DEVICE ),
.PCIE_PLL_SEL ( PCIE_PLL_SEL ),
.PCIE_ASYNC_EN ( PCIE_ASYNC_EN ),
.PCIE_TXBUF_EN ( PCIE_TXBUF_EN ),
.PCIE_CHAN_BOND ( PCIE_CHAN_BOND )
) gt_top_i (
// pl ltssm
.pl_ltssm_state ( pl_ltssm_state_int ),
// Pipe Common Signals
.pipe_tx_rcvr_det ( pipe_tx_rcvr_det_gt ),
.pipe_tx_reset ( 1'b0 ),
.pipe_tx_rate ( pipe_tx_rate_gt ),
.pipe_tx_deemph ( pipe_tx_deemph_gt ),
.pipe_tx_margin ( pipe_tx_margin_gt ),
.pipe_tx_swing ( 1'b0 ),
// Pipe Per-Lane Signals - Lane 0
.pipe_rx0_char_is_k ( pipe_rx0_char_is_k_gt),
.pipe_rx0_data ( pipe_rx0_data_gt ),
.pipe_rx0_valid ( pipe_rx0_valid_gt ),
.pipe_rx0_chanisaligned ( pipe_rx0_chanisaligned_gt ),
.pipe_rx0_status ( pipe_rx0_status_gt ),
.pipe_rx0_phy_status ( pipe_rx0_phy_status_gt ),
.pipe_rx0_elec_idle ( pipe_rx0_elec_idle_gt ),
.pipe_rx0_polarity ( pipe_rx0_polarity_gt ),
.pipe_tx0_compliance ( pipe_tx0_compliance_gt ),
.pipe_tx0_char_is_k ( pipe_tx0_char_is_k_gt ),
.pipe_tx0_data ( pipe_tx0_data_gt ),
.pipe_tx0_elec_idle ( pipe_tx0_elec_idle_gt ),
.pipe_tx0_powerdown ( pipe_tx0_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 1
.pipe_rx1_char_is_k ( pipe_rx1_char_is_k_gt),
.pipe_rx1_data ( pipe_rx1_data_gt ),
.pipe_rx1_valid ( pipe_rx1_valid_gt ),
.pipe_rx1_chanisaligned ( pipe_rx1_chanisaligned_gt ),
.pipe_rx1_status ( pipe_rx1_status_gt ),
.pipe_rx1_phy_status ( pipe_rx1_phy_status_gt ),
.pipe_rx1_elec_idle ( pipe_rx1_elec_idle_gt ),
.pipe_rx1_polarity ( pipe_rx1_polarity_gt ),
.pipe_tx1_compliance ( pipe_tx1_compliance_gt ),
.pipe_tx1_char_is_k ( pipe_tx1_char_is_k_gt ),
.pipe_tx1_data ( pipe_tx1_data_gt ),
.pipe_tx1_elec_idle ( pipe_tx1_elec_idle_gt ),
.pipe_tx1_powerdown ( pipe_tx1_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 2
.pipe_rx2_char_is_k ( pipe_rx2_char_is_k_gt),
.pipe_rx2_data ( pipe_rx2_data_gt ),
.pipe_rx2_valid ( pipe_rx2_valid_gt ),
.pipe_rx2_chanisaligned ( pipe_rx2_chanisaligned_gt ),
.pipe_rx2_status ( pipe_rx2_status_gt ),
.pipe_rx2_phy_status ( pipe_rx2_phy_status_gt ),
.pipe_rx2_elec_idle ( pipe_rx2_elec_idle_gt ),
.pipe_rx2_polarity ( pipe_rx2_polarity_gt ),
.pipe_tx2_compliance ( pipe_tx2_compliance_gt ),
.pipe_tx2_char_is_k ( pipe_tx2_char_is_k_gt ),
.pipe_tx2_data ( pipe_tx2_data_gt ),
.pipe_tx2_elec_idle ( pipe_tx2_elec_idle_gt ),
.pipe_tx2_powerdown ( pipe_tx2_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 3
.pipe_rx3_char_is_k ( pipe_rx3_char_is_k_gt),
.pipe_rx3_data ( pipe_rx3_data_gt ),
.pipe_rx3_valid ( pipe_rx3_valid_gt ),
.pipe_rx3_chanisaligned ( pipe_rx3_chanisaligned_gt ),
.pipe_rx3_status ( pipe_rx3_status_gt ),
.pipe_rx3_phy_status ( pipe_rx3_phy_status_gt ),
.pipe_rx3_elec_idle ( pipe_rx3_elec_idle_gt ),
.pipe_rx3_polarity ( pipe_rx3_polarity_gt ),
.pipe_tx3_compliance ( pipe_tx3_compliance_gt ),
.pipe_tx3_char_is_k ( pipe_tx3_char_is_k_gt ),
.pipe_tx3_data ( pipe_tx3_data_gt ),
.pipe_tx3_elec_idle ( pipe_tx3_elec_idle_gt ),
.pipe_tx3_powerdown ( pipe_tx3_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 4
.pipe_rx4_char_is_k ( pipe_rx4_char_is_k_gt),
.pipe_rx4_data ( pipe_rx4_data_gt ),
.pipe_rx4_valid ( pipe_rx4_valid_gt ),
.pipe_rx4_chanisaligned ( pipe_rx4_chanisaligned_gt ),
.pipe_rx4_status ( pipe_rx4_status_gt ),
.pipe_rx4_phy_status ( pipe_rx4_phy_status_gt ),
.pipe_rx4_elec_idle ( pipe_rx4_elec_idle_gt ),
.pipe_rx4_polarity ( pipe_rx4_polarity_gt ),
.pipe_tx4_compliance ( pipe_tx4_compliance_gt ),
.pipe_tx4_char_is_k ( pipe_tx4_char_is_k_gt ),
.pipe_tx4_data ( pipe_tx4_data_gt ),
.pipe_tx4_elec_idle ( pipe_tx4_elec_idle_gt ),
.pipe_tx4_powerdown ( pipe_tx4_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 5
.pipe_rx5_char_is_k ( pipe_rx5_char_is_k_gt),
.pipe_rx5_data ( pipe_rx5_data_gt ),
.pipe_rx5_valid ( pipe_rx5_valid_gt ),
.pipe_rx5_chanisaligned ( pipe_rx5_chanisaligned_gt ),
.pipe_rx5_status ( pipe_rx5_status_gt ),
.pipe_rx5_phy_status ( pipe_rx5_phy_status_gt ),
.pipe_rx5_elec_idle ( pipe_rx5_elec_idle_gt ),
.pipe_rx5_polarity ( pipe_rx5_polarity_gt ),
.pipe_tx5_compliance ( pipe_tx5_compliance_gt ),
.pipe_tx5_char_is_k ( pipe_tx5_char_is_k_gt ),
.pipe_tx5_data ( pipe_tx5_data_gt ),
.pipe_tx5_elec_idle ( pipe_tx5_elec_idle_gt ),
.pipe_tx5_powerdown ( pipe_tx5_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 6
.pipe_rx6_char_is_k ( pipe_rx6_char_is_k_gt),
.pipe_rx6_data ( pipe_rx6_data_gt ),
.pipe_rx6_valid ( pipe_rx6_valid_gt ),
.pipe_rx6_chanisaligned ( pipe_rx6_chanisaligned_gt ),
.pipe_rx6_status ( pipe_rx6_status_gt ),
.pipe_rx6_phy_status ( pipe_rx6_phy_status_gt ),
.pipe_rx6_elec_idle ( pipe_rx6_elec_idle_gt ),
.pipe_rx6_polarity ( pipe_rx6_polarity_gt ),
.pipe_tx6_compliance ( pipe_tx6_compliance_gt ),
.pipe_tx6_char_is_k ( pipe_tx6_char_is_k_gt ),
.pipe_tx6_data ( pipe_tx6_data_gt ),
.pipe_tx6_elec_idle ( pipe_tx6_elec_idle_gt ),
.pipe_tx6_powerdown ( pipe_tx6_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 7
.pipe_rx7_char_is_k ( pipe_rx7_char_is_k_gt),
.pipe_rx7_data ( pipe_rx7_data_gt ),
.pipe_rx7_valid ( pipe_rx7_valid_gt ),
.pipe_rx7_chanisaligned ( pipe_rx7_chanisaligned_gt ),
.pipe_rx7_status ( pipe_rx7_status_gt ),
.pipe_rx7_phy_status ( pipe_rx7_phy_status_gt ),
.pipe_rx7_elec_idle ( pipe_rx7_elec_idle_gt ),
.pipe_rx7_polarity ( pipe_rx7_polarity_gt ),
.pipe_tx7_compliance ( pipe_tx7_compliance_gt ),
.pipe_tx7_char_is_k ( pipe_tx7_char_is_k_gt ),
.pipe_tx7_data ( pipe_tx7_data_gt ),
.pipe_tx7_elec_idle ( pipe_tx7_elec_idle_gt ),
.pipe_tx7_powerdown ( pipe_tx7_powerdown_gt ),
// PCI Express Signals
.pci_exp_txn ( pci_exp_txn ),
.pci_exp_txp ( pci_exp_txp ),
.pci_exp_rxn ( pci_exp_rxn ),
.pci_exp_rxp ( pci_exp_rxp ),
// Non PIPE Signals
.sys_clk ( sys_clk ),
.sys_rst_n ( sys_rst_n ),
.pipe_clk ( pipe_clk ),
.user_clk ( user_clk ),
.user_clk2 ( user_clk2 ),
.phy_rdy_n ( phy_rdy_n ),
.PIPE_PCLK_IN ( PIPE_PCLK_IN ),
.PIPE_RXUSRCLK_IN ( PIPE_RXUSRCLK_IN ),
.PIPE_RXOUTCLK_IN ( PIPE_RXOUTCLK_IN ),
.PIPE_DCLK_IN ( PIPE_DCLK_IN ),
.PIPE_USERCLK1_IN ( PIPE_USERCLK1_IN ),
.PIPE_USERCLK2_IN ( PIPE_USERCLK2_IN ),
.PIPE_OOBCLK_IN ( PIPE_OOBCLK_IN ),
.PIPE_MMCM_LOCK_IN ( PIPE_MMCM_LOCK_IN ),
.PIPE_TXOUTCLK_OUT ( PIPE_TXOUTCLK_OUT ),
.PIPE_RXOUTCLK_OUT ( PIPE_RXOUTCLK_OUT ),
.PIPE_PCLK_SEL_OUT ( PIPE_PCLK_SEL_OUT ),
.PIPE_GEN3_OUT ( PIPE_GEN3_OUT )
);
end
else
begin : gt_top
pcie_core_gt_top_pipe_mode #(
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.REF_CLK_FREQ ( REF_CLK_FREQ ),
.USER_CLK_FREQ ( USER_CLK_FREQ ),
.USER_CLK2_DIV2 ( USER_CLK2_DIV2 ),
.PL_FAST_TRAIN ( PL_FAST_TRAIN ),
.PCIE_EXT_CLK ( PCIE_EXT_CLK ),
.PCIE_USE_MODE ( PCIE_USE_MODE ),
.PCIE_GT_DEVICE ( PCIE_GT_DEVICE ),
.PCIE_PLL_SEL ( PCIE_PLL_SEL ),
.PCIE_ASYNC_EN ( PCIE_ASYNC_EN ),
.PCIE_TXBUF_EN ( PCIE_TXBUF_EN ),
.PCIE_CHAN_BOND ( PCIE_CHAN_BOND )
) gt_top_i (
// pl ltssm
.pl_ltssm_state ( pl_ltssm_state_int ),
// Pipe Common Signals
.pipe_tx_rcvr_det ( pipe_tx_rcvr_det_gt ),
.pipe_tx_reset ( 1'b0 ),
.pipe_tx_rate ( pipe_tx_rate_gt ),
.pipe_tx_deemph ( pipe_tx_deemph_gt ),
.pipe_tx_margin ( pipe_tx_margin_gt ),
.pipe_tx_swing ( 1'b0 ),
// Pipe Per-Lane Signals - Lane 0
.pipe_rx0_char_is_k ( pipe_rx0_char_is_k_gt),
.pipe_rx0_data ( pipe_rx0_data_gt ),
.pipe_rx0_valid ( pipe_rx0_valid_gt ),
.pipe_rx0_chanisaligned ( pipe_rx0_chanisaligned_gt ),
.pipe_rx0_status ( pipe_rx0_status_gt ),
.pipe_rx0_phy_status ( pipe_rx0_phy_status_gt ),
.pipe_rx0_elec_idle ( pipe_rx0_elec_idle_gt ),
.pipe_rx0_polarity ( pipe_rx0_polarity_gt ),
.pipe_tx0_compliance ( pipe_tx0_compliance_gt ),
.pipe_tx0_char_is_k ( pipe_tx0_char_is_k_gt ),
.pipe_tx0_data ( pipe_tx0_data_gt ),
.pipe_tx0_elec_idle ( pipe_tx0_elec_idle_gt ),
.pipe_tx0_powerdown ( pipe_tx0_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 1
.pipe_rx1_char_is_k ( pipe_rx1_char_is_k_gt),
.pipe_rx1_data ( pipe_rx1_data_gt ),
.pipe_rx1_valid ( pipe_rx1_valid_gt ),
.pipe_rx1_chanisaligned ( pipe_rx1_chanisaligned_gt ),
.pipe_rx1_status ( pipe_rx1_status_gt ),
.pipe_rx1_phy_status ( pipe_rx1_phy_status_gt ),
.pipe_rx1_elec_idle ( pipe_rx1_elec_idle_gt ),
.pipe_rx1_polarity ( pipe_rx1_polarity_gt ),
.pipe_tx1_compliance ( pipe_tx1_compliance_gt ),
.pipe_tx1_char_is_k ( pipe_tx1_char_is_k_gt ),
.pipe_tx1_data ( pipe_tx1_data_gt ),
.pipe_tx1_elec_idle ( pipe_tx1_elec_idle_gt ),
.pipe_tx1_powerdown ( pipe_tx1_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 2
.pipe_rx2_char_is_k ( pipe_rx2_char_is_k_gt),
.pipe_rx2_data ( pipe_rx2_data_gt ),
.pipe_rx2_valid ( pipe_rx2_valid_gt ),
.pipe_rx2_chanisaligned ( pipe_rx2_chanisaligned_gt ),
.pipe_rx2_status ( pipe_rx2_status_gt ),
.pipe_rx2_phy_status ( pipe_rx2_phy_status_gt ),
.pipe_rx2_elec_idle ( pipe_rx2_elec_idle_gt ),
.pipe_rx2_polarity ( pipe_rx2_polarity_gt ),
.pipe_tx2_compliance ( pipe_tx2_compliance_gt ),
.pipe_tx2_char_is_k ( pipe_tx2_char_is_k_gt ),
.pipe_tx2_data ( pipe_tx2_data_gt ),
.pipe_tx2_elec_idle ( pipe_tx2_elec_idle_gt ),
.pipe_tx2_powerdown ( pipe_tx2_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 3
.pipe_rx3_char_is_k ( pipe_rx3_char_is_k_gt),
.pipe_rx3_data ( pipe_rx3_data_gt ),
.pipe_rx3_valid ( pipe_rx3_valid_gt ),
.pipe_rx3_chanisaligned ( pipe_rx3_chanisaligned_gt ),
.pipe_rx3_status ( pipe_rx3_status_gt ),
.pipe_rx3_phy_status ( pipe_rx3_phy_status_gt ),
.pipe_rx3_elec_idle ( pipe_rx3_elec_idle_gt ),
.pipe_rx3_polarity ( pipe_rx3_polarity_gt ),
.pipe_tx3_compliance ( pipe_tx3_compliance_gt ),
.pipe_tx3_char_is_k ( pipe_tx3_char_is_k_gt ),
.pipe_tx3_data ( pipe_tx3_data_gt ),
.pipe_tx3_elec_idle ( pipe_tx3_elec_idle_gt ),
.pipe_tx3_powerdown ( pipe_tx3_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 4
.pipe_rx4_char_is_k ( pipe_rx4_char_is_k_gt),
.pipe_rx4_data ( pipe_rx4_data_gt ),
.pipe_rx4_valid ( pipe_rx4_valid_gt ),
.pipe_rx4_chanisaligned ( pipe_rx4_chanisaligned_gt ),
.pipe_rx4_status ( pipe_rx4_status_gt ),
.pipe_rx4_phy_status ( pipe_rx4_phy_status_gt ),
.pipe_rx4_elec_idle ( pipe_rx4_elec_idle_gt ),
.pipe_rx4_polarity ( pipe_rx4_polarity_gt ),
.pipe_tx4_compliance ( pipe_tx4_compliance_gt ),
.pipe_tx4_char_is_k ( pipe_tx4_char_is_k_gt ),
.pipe_tx4_data ( pipe_tx4_data_gt ),
.pipe_tx4_elec_idle ( pipe_tx4_elec_idle_gt ),
.pipe_tx4_powerdown ( pipe_tx4_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 5
.pipe_rx5_char_is_k ( pipe_rx5_char_is_k_gt),
.pipe_rx5_data ( pipe_rx5_data_gt ),
.pipe_rx5_valid ( pipe_rx5_valid_gt ),
.pipe_rx5_chanisaligned ( pipe_rx5_chanisaligned_gt ),
.pipe_rx5_status ( pipe_rx5_status_gt ),
.pipe_rx5_phy_status ( pipe_rx5_phy_status_gt ),
.pipe_rx5_elec_idle ( pipe_rx5_elec_idle_gt ),
.pipe_rx5_polarity ( pipe_rx5_polarity_gt ),
.pipe_tx5_compliance ( pipe_tx5_compliance_gt ),
.pipe_tx5_char_is_k ( pipe_tx5_char_is_k_gt ),
.pipe_tx5_data ( pipe_tx5_data_gt ),
.pipe_tx5_elec_idle ( pipe_tx5_elec_idle_gt ),
.pipe_tx5_powerdown ( pipe_tx5_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 6
.pipe_rx6_char_is_k ( pipe_rx6_char_is_k_gt),
.pipe_rx6_data ( pipe_rx6_data_gt ),
.pipe_rx6_valid ( pipe_rx6_valid_gt ),
.pipe_rx6_chanisaligned ( pipe_rx6_chanisaligned_gt ),
.pipe_rx6_status ( pipe_rx6_status_gt ),
.pipe_rx6_phy_status ( pipe_rx6_phy_status_gt ),
.pipe_rx6_elec_idle ( pipe_rx6_elec_idle_gt ),
.pipe_rx6_polarity ( pipe_rx6_polarity_gt ),
.pipe_tx6_compliance ( pipe_tx6_compliance_gt ),
.pipe_tx6_char_is_k ( pipe_tx6_char_is_k_gt ),
.pipe_tx6_data ( pipe_tx6_data_gt ),
.pipe_tx6_elec_idle ( pipe_tx6_elec_idle_gt ),
.pipe_tx6_powerdown ( pipe_tx6_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 7
.pipe_rx7_char_is_k ( pipe_rx7_char_is_k_gt),
.pipe_rx7_data ( pipe_rx7_data_gt ),
.pipe_rx7_valid ( pipe_rx7_valid_gt ),
.pipe_rx7_chanisaligned ( pipe_rx7_chanisaligned_gt ),
.pipe_rx7_status ( pipe_rx7_status_gt ),
.pipe_rx7_phy_status ( pipe_rx7_phy_status_gt ),
.pipe_rx7_elec_idle ( pipe_rx7_elec_idle_gt ),
.pipe_rx7_polarity ( pipe_rx7_polarity_gt ),
.pipe_tx7_compliance ( pipe_tx7_compliance_gt ),
.pipe_tx7_char_is_k ( pipe_tx7_char_is_k_gt ),
.pipe_tx7_data ( pipe_tx7_data_gt ),
.pipe_tx7_elec_idle ( pipe_tx7_elec_idle_gt ),
.pipe_tx7_powerdown ( pipe_tx7_powerdown_gt ),
// PCI Express Signals
.pci_exp_txn ( pci_exp_txn ),
.pci_exp_txp ( pci_exp_txp ),
.pci_exp_rxn ( pci_exp_rxn ),
.pci_exp_rxp ( pci_exp_rxp ),
// Non PIPE Signals
.sys_clk ( sys_clk ),
.sys_rst_n ( sys_rst_n ),
.pipe_clk ( pipe_clk ),
.user_clk ( user_clk ),
.user_clk2 ( user_clk2 ),
.phy_rdy_n ( phy_rdy_n ),
.PIPE_PCLK_IN ( PIPE_PCLK_IN ),
.PIPE_RXUSRCLK_IN ( PIPE_RXUSRCLK_IN ),
.PIPE_RXOUTCLK_IN ( PIPE_RXOUTCLK_IN ),
.PIPE_DCLK_IN ( PIPE_DCLK_IN ),
.PIPE_USERCLK1_IN ( PIPE_USERCLK1_IN ),
.PIPE_USERCLK2_IN ( PIPE_USERCLK2_IN ),
.PIPE_OOBCLK_IN ( PIPE_OOBCLK_IN ),
.PIPE_MMCM_LOCK_IN ( PIPE_MMCM_LOCK_IN ),
.PIPE_TXOUTCLK_OUT ( PIPE_TXOUTCLK_OUT ),
.PIPE_RXOUTCLK_OUT ( PIPE_RXOUTCLK_OUT ),
.PIPE_PCLK_SEL_OUT ( PIPE_PCLK_SEL_OUT ),
.PIPE_GEN3_OUT ( PIPE_GEN3_OUT )
);
end
endgenerate
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_NANO_SOC_QSYS_jtag_uart_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input [ 7: 0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(posedge clk)
begin
if (fifo_wr)
$write("%c", fifo_wdata);
end
assign wfifo_used = {6{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_NANO_SOC_QSYS_jtag_uart_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input fifo_clear;
input [ 7: 0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
DE0_NANO_SOC_QSYS_jtag_uart_sim_scfifo_w the_DE0_NANO_SOC_QSYS_jtag_uart_sim_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 64,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 6,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_NANO_SOC_QSYS_jtag_uart_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [ 31: 0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7: 0] fifo_rdata;
wire new_rom;
wire [ 31: 0] num_bytes;
wire [ 6: 0] rfifo_entries;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end
else
begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d)
bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom)
bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
assign new_rom = 1'b0;
assign num_bytes = 32'b0;
assign fifo_rdata = 8'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_NANO_SOC_QSYS_jtag_uart_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [ 7: 0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [ 7: 0] fifo_rdata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
DE0_NANO_SOC_QSYS_jtag_uart_sim_scfifo_r the_DE0_NANO_SOC_QSYS_jtag_uart_sim_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_NANO_SOC_QSYS_jtag_uart (
// inputs:
av_address,
av_chipselect,
av_read_n,
av_write_n,
av_writedata,
clk,
rst_n,
// outputs:
av_irq,
av_readdata,
av_waitrequest,
dataavailable,
readyfordata
)
/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ;
output av_irq;
output [ 31: 0] av_readdata;
output av_waitrequest;
output dataavailable;
output readyfordata;
input av_address;
input av_chipselect;
input av_read_n;
input av_write_n;
input [ 31: 0] av_writedata;
input clk;
input rst_n;
reg ac;
wire activity;
wire av_irq;
wire [ 31: 0] av_readdata;
reg av_waitrequest;
reg dataavailable;
reg fifo_AE;
reg fifo_AF;
wire fifo_EF;
wire fifo_FF;
wire fifo_clear;
wire fifo_rd;
wire [ 7: 0] fifo_rdata;
wire [ 7: 0] fifo_wdata;
reg fifo_wr;
reg ien_AE;
reg ien_AF;
wire ipen_AE;
wire ipen_AF;
reg pause_irq;
wire [ 7: 0] r_dat;
wire r_ena;
reg r_val;
wire rd_wfifo;
reg read_0;
reg readyfordata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
reg rvalid;
reg sim_r_ena;
reg sim_t_dat;
reg sim_t_ena;
reg sim_t_pause;
wire [ 7: 0] t_dat;
reg t_dav;
wire t_ena;
wire t_pause;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
reg woverflow;
wire wr_rfifo;
//avalon_jtag_slave, which is an e_avalon_slave
assign rd_wfifo = r_ena & ~wfifo_empty;
assign wr_rfifo = t_ena & ~rfifo_full;
assign fifo_clear = ~rst_n;
DE0_NANO_SOC_QSYS_jtag_uart_scfifo_w the_DE0_NANO_SOC_QSYS_jtag_uart_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_clear (fifo_clear),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.rd_wfifo (rd_wfifo),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
DE0_NANO_SOC_QSYS_jtag_uart_scfifo_r the_DE0_NANO_SOC_QSYS_jtag_uart_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_clear (fifo_clear),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n),
.t_dat (t_dat),
.wr_rfifo (wr_rfifo)
);
assign ipen_AE = ien_AE & fifo_AE;
assign ipen_AF = ien_AF & (pause_irq | fifo_AF);
assign av_irq = ipen_AE | ipen_AF;
assign activity = t_pause | t_ena;
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
pause_irq <= 1'b0;
else // only if fifo is not empty...
if (t_pause & ~fifo_EF)
pause_irq <= 1'b1;
else if (read_0)
pause_irq <= 1'b0;
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
r_val <= 1'b0;
t_dav <= 1'b1;
end
else
begin
r_val <= r_ena & ~wfifo_empty;
t_dav <= ~rfifo_full;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
fifo_AE <= 1'b0;
fifo_AF <= 1'b0;
fifo_wr <= 1'b0;
rvalid <= 1'b0;
read_0 <= 1'b0;
ien_AE <= 1'b0;
ien_AF <= 1'b0;
ac <= 1'b0;
woverflow <= 1'b0;
av_waitrequest <= 1'b1;
end
else
begin
fifo_AE <= {fifo_FF,wfifo_used} <= 8;
fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8;
fifo_wr <= 1'b0;
read_0 <= 1'b0;
av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest);
if (activity)
ac <= 1'b1;
// write
if (av_chipselect & ~av_write_n & av_waitrequest)
// addr 1 is control; addr 0 is data
if (av_address)
begin
ien_AF <= av_writedata[0];
ien_AE <= av_writedata[1];
if (av_writedata[10] & ~activity)
ac <= 1'b0;
end
else
begin
fifo_wr <= ~fifo_FF;
woverflow <= fifo_FF;
end
// read
if (av_chipselect & ~av_read_n & av_waitrequest)
begin
// addr 1 is interrupt; addr 0 is data
if (~av_address)
rvalid <= ~fifo_EF;
read_0 <= ~av_address;
end
end
end
assign fifo_wdata = av_writedata[7 : 0];
assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0;
assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
readyfordata <= 0;
else
readyfordata <= ~fifo_FF;
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Tie off Atlantic Interface signals not used for simulation
always @(posedge clk)
begin
sim_t_pause <= 1'b0;
sim_t_ena <= 1'b0;
sim_t_dat <= t_dav ? r_dat : {8{r_val}};
sim_r_ena <= 1'b0;
end
assign r_ena = sim_r_ena;
assign t_ena = sim_t_ena;
assign t_dat = sim_t_dat;
assign t_pause = sim_t_pause;
always @(fifo_EF)
begin
dataavailable = ~fifo_EF;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// alt_jtag_atlantic DE0_NANO_SOC_QSYS_jtag_uart_alt_jtag_atlantic
// (
// .clk (clk),
// .r_dat (r_dat),
// .r_ena (r_ena),
// .r_val (r_val),
// .rst_n (rst_n),
// .t_dat (t_dat),
// .t_dav (t_dav),
// .t_ena (t_ena),
// .t_pause (t_pause)
// );
//
// defparam DE0_NANO_SOC_QSYS_jtag_uart_alt_jtag_atlantic.INSTANCE_ID = 0,
// DE0_NANO_SOC_QSYS_jtag_uart_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6,
// DE0_NANO_SOC_QSYS_jtag_uart_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,
// DE0_NANO_SOC_QSYS_jtag_uart_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";
//
// always @(posedge clk or negedge rst_n)
// begin
// if (rst_n == 0)
// dataavailable <= 0;
// else
// dataavailable <= ~fifo_EF;
// end
//
//
//synthesis read_comments_as_HDL off
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2013 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file pcie_command_rec_fifo.v when simulating
// the core, pcie_command_rec_fifo. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module pcie_command_rec_fifo(
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
almost_full,
empty,
almost_empty,
rd_data_count,
wr_data_count
);
input rst;
input wr_clk;
input rd_clk;
input [127 : 0] din;
input wr_en;
input rd_en;
output [127 : 0] dout;
output full;
output almost_full;
output empty;
output almost_empty;
output [3 : 0] rd_data_count;
output [3 : 0] wr_data_count;
// synthesis translate_off
FIFO_GENERATOR_V8_4 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(5),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(128),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(128),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("virtex6"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(1),
.C_HAS_ALMOST_FULL(1),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(1),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(1),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x72"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(5),
.C_PROG_EMPTY_TYPE_RACH(5),
.C_PROG_EMPTY_TYPE_RDCH(5),
.C_PROG_EMPTY_TYPE_WACH(5),
.C_PROG_EMPTY_TYPE_WDCH(5),
.C_PROG_EMPTY_TYPE_WRCH(5),
.C_PROG_FULL_THRESH_ASSERT_VAL(31),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(30),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(5),
.C_PROG_FULL_TYPE_RACH(5),
.C_PROG_FULL_TYPE_RDCH(5),
.C_PROG_FULL_TYPE_WACH(5),
.C_PROG_FULL_TYPE_WDCH(5),
.C_PROG_FULL_TYPE_WRCH(5),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(4),
.C_RD_DEPTH(32),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(5),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(4),
.C_WR_DEPTH(32),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(5),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.RST(rst),
.WR_CLK(wr_clk),
.RD_CLK(rd_clk),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.ALMOST_FULL(almost_full),
.EMPTY(empty),
.ALMOST_EMPTY(almost_empty),
.RD_DATA_COUNT(rd_data_count),
.WR_DATA_COUNT(wr_data_count),
.BACKUP(),
.BACKUP_MARKER(),
.CLK(),
.SRST(),
.WR_RST(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.WR_ACK(),
.OVERFLOW(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.PROG_FULL(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW()
);
// synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DECAP_3_V
`define SKY130_FD_SC_LP__DECAP_3_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog wrapper for decap with size of 3 units (invalid?).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__decap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__decap_3 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__decap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__decap_3 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__decap base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DECAP_3_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21BAI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__O21BAI_FUNCTIONAL_PP_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o21bai (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire b ;
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , b, or0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21BAI_FUNCTIONAL_PP_V |
// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "registers.v"
//include "reg_defines_reference_router.v"
module user_data_path
#(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH=DATA_WIDTH/8,
parameter UDP_REG_SRC_WIDTH = 2,
parameter NUM_OUTPUT_QUEUES = 8,
parameter NUM_INPUT_QUEUES = 8,
parameter SRAM_DATA_WIDTH = DATA_WIDTH+CTRL_WIDTH,
parameter SRAM_ADDR_WIDTH = 19,
parameter WORKER_ADDR_WIDTH = 2,
parameter TOTAL_DATA = 8
)
(
in_data_0,
in_ctrl_0,
in_wr_0,
in_rdy_0,
in_data_1,
in_ctrl_1,
in_wr_1,
in_rdy_1,
in_data_2,
in_ctrl_2,
in_wr_2,
in_rdy_2,
in_data_3,
in_ctrl_3,
in_wr_3,
in_rdy_3,
in_data_4,
in_ctrl_4,
in_wr_4,
in_rdy_4,
in_data_5,
in_ctrl_5,
in_wr_5,
in_rdy_5,
in_data_6,
in_ctrl_6,
in_wr_6,
in_rdy_6,
in_data_7,
in_ctrl_7,
in_wr_7,
in_rdy_7,
/**** not used
// --- Interface to SATA
input [DATA_WIDTH-1:0] in_data_5,
input [CTRL_WIDTH-1:0] in_ctrl_5,
input in_wr_5,
output in_rdy_5,
// --- Interface to the loopback queue
input [DATA_WIDTH-1:0] in_data_6,
input [CTRL_WIDTH-1:0] in_ctrl_6,
input in_wr_6,
output in_rdy_6,
// --- Interface to a user queue
input [DATA_WIDTH-1:0] in_data_7,
input [CTRL_WIDTH-1:0] in_ctrl_7,
input in_wr_7,
output in_rdy_7,
*****/
out_data_0,
out_ctrl_0,
out_wr_0,
out_rdy_0,
out_data_1,
out_ctrl_1,
out_wr_1,
out_rdy_1,
out_data_2,
out_ctrl_2,
out_wr_2,
out_rdy_2,
out_data_3,
out_ctrl_3,
out_wr_3,
out_rdy_3,
out_data_4,
out_ctrl_4,
out_wr_4,
out_rdy_4,
out_data_5,
out_ctrl_5,
out_wr_5,
out_rdy_5,
out_data_6,
out_ctrl_6,
out_wr_6,
out_rdy_6,
out_data_7,
out_ctrl_7,
out_wr_7,
out_rdy_7,
/**** not used
// --- Interface to SATA
output [DATA_WIDTH-1:0] out_data_5,
output [CTRL_WIDTH-1:0] out_ctrl_5,
output out_wr_5,
input out_rdy_5,
// --- Interface to the loopback queue
output [DATA_WIDTH-1:0] out_data_6,
output [CTRL_WIDTH-1:0] out_ctrl_6,
output out_wr_6,
input out_rdy_6,
// --- Interface to a user queue
output [DATA_WIDTH-1:0] out_data_7,
output [CTRL_WIDTH-1:0] out_ctrl_7,
output out_wr_7,
input out_rdy_7,
*****/
// interface to SRAM
wr_0_addr,
wr_0_req,
wr_0_ack,
wr_0_data,
rd_0_ack,
rd_0_data,
rd_0_vld,
rd_0_addr,
rd_0_req,
// interface to DRAM
/* TBD */
// register interface
reg_req,
reg_ack,
reg_rd_wr_L,
reg_addr,
reg_rd_data,
reg_wr_data,
//i/f b/w TX EXT FIFO and packet composer
tx_ext_update_0_q,
tx_ext_update_0_rdreq,
tx_ext_update_0_empty,
tx_ext_update_0_almost_full,
//i/f b/w TX EXT FIFO and packet composer
tx_ext_update_1_q,
tx_ext_update_1_rdreq,
tx_ext_update_1_empty,
tx_ext_update_1_almost_full,
//i/f b/w TX EXT FIFO and packet composer
tx_ext_update_2_q,
tx_ext_update_2_rdreq,
tx_ext_update_2_empty,
tx_ext_update_2_almost_full,
//i/f b/w TX EXT FIFO and packet composer
tx_ext_update_3_q,
tx_ext_update_3_rdreq,
tx_ext_update_3_empty,
tx_ext_update_3_almost_full,
//i/f b/w op_lut_process_sm.v and RX EXT FIFO
rx_ext_update_data,
rx_ext_update_0_full,
rx_ext_update_0_wrreq,
rx_ext_update_1_full,
rx_ext_update_1_wrreq,
rx_ext_update_2_full,
rx_ext_update_2_wrreq,
rx_ext_update_3_full,
rx_ext_update_3_wrreq,
rx_ext_update_4_full,
rx_ext_update_4_wrreq,
rx_ext_update_5_full,
rx_ext_update_5_wrreq,
rx_ext_update_6_full,
rx_ext_update_6_wrreq,
rx_ext_update_7_full,
rx_ext_update_7_wrreq,
start_update,
compute_system_reset,
flush_ddr,
start_load,
iteration_accum_value,
dram_fifo_writedata,
dram_fifo_write,
dram_fifo_full,
//read interface from DDR (used by flush data function)
dram_fifo_readdata,
dram_fifo_read,
dram_fifo_empty,
num_keys,
log_2_num_workers, //returns the log2(number of workers) - useful for mask calculation in key hashing
shard_id,
max_n_values,
filter_threshold,
max_fpga_procs,
algo_selection,
proc_bit_mask,
// misc
reset,
clk
);
output start_update;
output flush_ddr;
output start_load;
output compute_system_reset;
//i/f b/w TX EXT FIFO and packet composer
input [63:0] tx_ext_update_0_q;
output tx_ext_update_0_rdreq;
input tx_ext_update_0_empty;
input tx_ext_update_0_almost_full;
//i/f b/w TX EXT FIFO and packet composer
input [63:0] tx_ext_update_1_q;
output tx_ext_update_1_rdreq;
input tx_ext_update_1_empty;
input tx_ext_update_1_almost_full;
//i/f b/w TX EXT FIFO and packet composer
input [63:0] tx_ext_update_2_q;
output tx_ext_update_2_rdreq;
input tx_ext_update_2_empty;
input tx_ext_update_2_almost_full;
//i/f b/w TX EXT FIFO and packet composer
input [63:0] tx_ext_update_3_q;
output tx_ext_update_3_rdreq;
input tx_ext_update_3_empty;
input tx_ext_update_3_almost_full;
//i/f b/w op_lut_process_sm.v and RX EXT FIFO
output [63:0] rx_ext_update_data;
input rx_ext_update_0_full;
output rx_ext_update_0_wrreq;
input rx_ext_update_1_full;
output rx_ext_update_1_wrreq;
input rx_ext_update_2_full;
output rx_ext_update_2_wrreq;
input rx_ext_update_3_full;
output rx_ext_update_3_wrreq;
input rx_ext_update_4_full;
output rx_ext_update_4_wrreq;
input rx_ext_update_5_full;
output rx_ext_update_5_wrreq;
input rx_ext_update_6_full;
output rx_ext_update_6_wrreq;
input rx_ext_update_7_full;
output rx_ext_update_7_wrreq;
input [DATA_WIDTH-1:0] in_data_0;
input [CTRL_WIDTH-1:0] in_ctrl_0;
input in_wr_0;
output in_rdy_0;
input [DATA_WIDTH-1:0] in_data_1;
input [CTRL_WIDTH-1:0] in_ctrl_1;
input in_wr_1;
output in_rdy_1;
input [DATA_WIDTH-1:0] in_data_2;
input [CTRL_WIDTH-1:0] in_ctrl_2;
input in_wr_2;
output in_rdy_2;
input [DATA_WIDTH-1:0] in_data_3;
input [CTRL_WIDTH-1:0] in_ctrl_3;
input in_wr_3;
output in_rdy_3;
input [DATA_WIDTH-1:0] in_data_4;
input [CTRL_WIDTH-1:0] in_ctrl_4;
input in_wr_4;
output in_rdy_4;
input [DATA_WIDTH-1:0] in_data_5;
input [CTRL_WIDTH-1:0] in_ctrl_5;
input in_wr_5;
output in_rdy_5;
input [DATA_WIDTH-1:0] in_data_6;
input [CTRL_WIDTH-1:0] in_ctrl_6;
input in_wr_6;
output in_rdy_6;
input [DATA_WIDTH-1:0] in_data_7;
input [CTRL_WIDTH-1:0] in_ctrl_7;
input in_wr_7;
output in_rdy_7;
/**** not used
// --- Interface to SATA
input [DATA_WIDTH-1:0] in_data_5,
input [CTRL_WIDTH-1:0] in_ctrl_5,
input in_wr_5,
output in_rdy_5,
// --- Interface to the loopback queue
input [DATA_WIDTH-1:0] in_data_6,
input [CTRL_WIDTH-1:0] in_ctrl_6,
input in_wr_6,
output in_rdy_6,
// --- Interface to a user queue
input [DATA_WIDTH-1:0] in_data_7,
input [CTRL_WIDTH-1:0] in_ctrl_7,
input in_wr_7,
output in_rdy_7,
*****/
output [DATA_WIDTH-1:0] out_data_0;
output [CTRL_WIDTH-1:0] out_ctrl_0;
output out_wr_0;
input out_rdy_0;
output [DATA_WIDTH-1:0] out_data_1;
output [CTRL_WIDTH-1:0] out_ctrl_1;
output out_wr_1;
input out_rdy_1;
output [DATA_WIDTH-1:0] out_data_2;
output [CTRL_WIDTH-1:0] out_ctrl_2;
output out_wr_2;
input out_rdy_2;
output [DATA_WIDTH-1:0] out_data_3;
output [CTRL_WIDTH-1:0] out_ctrl_3;
output out_wr_3;
input out_rdy_3;
output [DATA_WIDTH-1:0] out_data_4;
output [CTRL_WIDTH-1:0] out_ctrl_4;
output out_wr_4;
input out_rdy_4;
output [DATA_WIDTH-1:0] out_data_5;
output [CTRL_WIDTH-1:0] out_ctrl_5;
output out_wr_5;
input out_rdy_5;
output [DATA_WIDTH-1:0] out_data_6;
output [CTRL_WIDTH-1:0] out_ctrl_6;
output out_wr_6;
input out_rdy_6;
output [DATA_WIDTH-1:0] out_data_7;
output [CTRL_WIDTH-1:0] out_ctrl_7;
output out_wr_7;
input out_rdy_7;
/**** not used
// --- Interface to SATA
output [DATA_WIDTH-1:0] out_data_5,
output [CTRL_WIDTH-1:0] out_ctrl_5,
output out_wr_5,
input out_rdy_5,
// --- Interface to the loopback queue
output [DATA_WIDTH-1:0] out_data_6,
output [CTRL_WIDTH-1:0] out_ctrl_6,
output out_wr_6,
input out_rdy_6,
// --- Interface to a user queue
output [DATA_WIDTH-1:0] out_data_7,
output [CTRL_WIDTH-1:0] out_ctrl_7,
output out_wr_7,
input out_rdy_7,
*****/
// interface to SRAM
output [SRAM_ADDR_WIDTH-1:0] wr_0_addr;
output wr_0_req;
input wr_0_ack;
output [SRAM_DATA_WIDTH-1:0] wr_0_data;
input rd_0_ack;
input [SRAM_DATA_WIDTH-1:0] rd_0_data;
input rd_0_vld;
output [SRAM_ADDR_WIDTH-1:0] rd_0_addr;
output rd_0_req;
// interface to DRAM
/* TBD */
// register interface
input reg_req;
output reg_ack;
input reg_rd_wr_L;
input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr;
output [`CPCI_NF2_DATA_WIDTH-1:0] reg_rd_data;
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_wr_data;
output [31:0] num_keys;
output [31:0] log_2_num_workers;
output [31:0] shard_id;
output [31:0] max_n_values;
output [31:0] filter_threshold;
output [3:0] max_fpga_procs;
output algo_selection;
// misc
input reset;
input clk;
input [31:0] iteration_accum_value;
//write interface to DDR (used by load data function)
output [63:0] dram_fifo_writedata;
output dram_fifo_write;
input dram_fifo_full;
//read interface from DDR (used by flush data function)
input [63:0] dram_fifo_readdata;
output dram_fifo_read;
input dram_fifo_empty;
output [7:0] proc_bit_mask;
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
//---------- Internal parameters -----------
localparam NUM_IQ_BITS = log2(NUM_INPUT_QUEUES);
localparam IN_ARB_STAGE_NUM = 2;
localparam OP_LUT_STAGE_NUM = 4;
localparam OQ_STAGE_NUM = 6;
//-------- Input arbiter wires/regs -------
wire in_arb_in_reg_req;
wire in_arb_in_reg_ack;
wire in_arb_in_reg_rd_wr_L;
wire [`UDP_REG_ADDR_WIDTH-1:0] in_arb_in_reg_addr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] in_arb_in_reg_data;
wire [UDP_REG_SRC_WIDTH-1:0] in_arb_in_reg_src;
//------- output port lut wires/regs ------
wire [CTRL_WIDTH-1:0] op_lut_in_ctrl;
wire [DATA_WIDTH-1:0] op_lut_in_data;
wire op_lut_in_wr;
wire op_lut_in_rdy;
wire op_lut_in_reg_req;
wire op_lut_in_reg_ack;
wire op_lut_in_reg_rd_wr_L;
wire [`UDP_REG_ADDR_WIDTH-1:0] op_lut_in_reg_addr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] op_lut_in_reg_data;
wire [UDP_REG_SRC_WIDTH-1:0] op_lut_in_reg_src;
wire [CTRL_WIDTH-1:0] oq_in_ctrl;
wire [DATA_WIDTH-1:0] oq_in_data;
wire oq_in_wr;
wire oq_in_rdy;
wire oq_in_reg_req;
wire oq_in_reg_ack;
wire oq_in_reg_rd_wr_L;
wire [`UDP_REG_ADDR_WIDTH-1:0] oq_in_reg_addr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] oq_in_reg_data;
wire [UDP_REG_SRC_WIDTH-1:0] oq_in_reg_src;
//-------- UDP register master wires/regs -------
wire udp_reg_req_in;
wire udp_reg_ack_in;
wire udp_reg_rd_wr_L_in;
wire [`UDP_REG_ADDR_WIDTH-1:0] udp_reg_addr_in;
wire [`CPCI_NF2_DATA_WIDTH-1:0] udp_reg_data_in;
wire [UDP_REG_SRC_WIDTH-1:0] udp_reg_src_in;
wire check_terminate;
wire [31:0] interpkt_gap_cycles;
//--------- Connect the data path -----------
input_arbiter
#(.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH),
.STAGE_NUMBER(IN_ARB_STAGE_NUM))
input_arbiter
(
.out_data (op_lut_in_data),
.out_ctrl (op_lut_in_ctrl),
.out_wr (op_lut_in_wr),
.out_rdy (op_lut_in_rdy),
// --- Interface to the input queues
.in_data_0 (in_data_0),
.in_ctrl_0 (in_ctrl_0),
.in_wr_0 (in_wr_0),
.in_rdy_0 (in_rdy_0),
.in_data_1 (in_data_1),
.in_ctrl_1 (in_ctrl_1),
.in_wr_1 (in_wr_1),
.in_rdy_1 (in_rdy_1),
.in_data_2 (in_data_2),
.in_ctrl_2 (in_ctrl_2),
.in_wr_2 (in_wr_2),
.in_rdy_2 (in_rdy_2),
.in_data_3 (in_data_3),
.in_ctrl_3 (in_ctrl_3),
.in_wr_3 (in_wr_3),
.in_rdy_3 (in_rdy_3),
.in_data_4 (in_data_4),
.in_ctrl_4 (in_ctrl_4),
.in_wr_4 (in_wr_4),
.in_rdy_4 (in_rdy_4),
.in_data_5 (in_data_5),
.in_ctrl_5 (in_ctrl_5),
.in_wr_5 (in_wr_5),
.in_rdy_5 (in_rdy_5),
.in_data_6 (in_data_6),
.in_ctrl_6 (in_ctrl_6),
.in_wr_6 (in_wr_6),
.in_rdy_6 (in_rdy_6),
.in_data_7 (in_data_7),
.in_ctrl_7 (in_ctrl_7),
.in_wr_7 (in_wr_7),
.in_rdy_7 (in_rdy_7),
// --- Register interface
.reg_req_in (in_arb_in_reg_req),
.reg_ack_in (in_arb_in_reg_ack),
.reg_rd_wr_L_in (in_arb_in_reg_rd_wr_L),
.reg_addr_in (in_arb_in_reg_addr),
.reg_data_in (in_arb_in_reg_data),
.reg_src_in (in_arb_in_reg_src),
.reg_req_out (op_lut_in_reg_req),
.reg_ack_out (op_lut_in_reg_ack),
.reg_rd_wr_L_out (op_lut_in_reg_rd_wr_L),
.reg_addr_out (op_lut_in_reg_addr),
.reg_data_out (op_lut_in_reg_data),
.reg_src_out (op_lut_in_reg_src),
// --- Misc
.reset (reset),
.clk (clk)
);
output_port_lookup
#(.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH),
.INPUT_ARBITER_STAGE_NUM(IN_ARB_STAGE_NUM),
.STAGE_NUM(OP_LUT_STAGE_NUM),
.NUM_OUTPUT_QUEUES(NUM_OUTPUT_QUEUES),
.NUM_IQ_BITS(NUM_IQ_BITS))
output_port_lookup
(
/*
.out_data (oq_in_data),
.out_ctrl (oq_in_ctrl),
.out_wr (oq_in_wr),
.out_rdy (oq_in_rdy),
*/
// --- Interface to the rx input queues
.in_data (op_lut_in_data),
.in_ctrl (op_lut_in_ctrl),
.in_wr (op_lut_in_wr),
.in_rdy (op_lut_in_rdy),
// --- Register interface
.reg_req_in (op_lut_in_reg_req),
.reg_ack_in (op_lut_in_reg_ack),
.reg_rd_wr_L_in (op_lut_in_reg_rd_wr_L),
.reg_addr_in (op_lut_in_reg_addr),
.reg_data_in (op_lut_in_reg_data),
.reg_src_in (op_lut_in_reg_src),
.reg_req_out (oq_in_reg_req),
.reg_ack_out (oq_in_reg_ack),
.reg_rd_wr_L_out (oq_in_reg_rd_wr_L),
.reg_addr_out (oq_in_reg_addr),
.reg_data_out (oq_in_reg_data),
.reg_src_out (oq_in_reg_src),
//i/f b/w op_lut_process_sm.v and RX EXT FIFO
.rx_ext_update_data (rx_ext_update_data),
.rx_ext_update_0_wrreq (rx_ext_update_0_wrreq),
.rx_ext_update_0_full (rx_ext_update_0_full),
.rx_ext_update_1_wrreq (rx_ext_update_1_wrreq),
.rx_ext_update_1_full (rx_ext_update_1_full),
.rx_ext_update_2_wrreq (rx_ext_update_2_wrreq),
.rx_ext_update_2_full (rx_ext_update_2_full),
.rx_ext_update_3_wrreq (rx_ext_update_3_wrreq),
.rx_ext_update_3_full (rx_ext_update_3_full),
.rx_ext_update_4_wrreq (rx_ext_update_4_wrreq),
.rx_ext_update_4_full (rx_ext_update_4_full),
.rx_ext_update_5_wrreq (rx_ext_update_5_wrreq),
.rx_ext_update_5_full (rx_ext_update_5_full),
.rx_ext_update_6_wrreq (rx_ext_update_6_wrreq),
.rx_ext_update_6_full (rx_ext_update_6_full),
.rx_ext_update_7_wrreq (rx_ext_update_7_wrreq),
.rx_ext_update_7_full (rx_ext_update_7_full),
.start_update (start_update),
.flush_ddr (flush_ddr),
.start_load (start_load),
.compute_system_reset (compute_system_reset),
//write interface to DDR (used by load data function)
.dram_fifo_writedata (dram_fifo_writedata),
.dram_fifo_write (dram_fifo_write),
.dram_fifo_full (dram_fifo_full),
.check_terminate (check_terminate),
.num_keys (num_keys),
.log_2_num_workers (log_2_num_workers),
.shard_id (shard_id),
.max_n_values (max_n_values),
.filter_threshold (filter_threshold),
.interpkt_gap_cycles(interpkt_gap_cycles),
.max_fpga_procs (max_fpga_procs),
.proc_bit_mask(proc_bit_mask),
.algo_selection (algo_selection),
// --- Misc
.clk (clk),
.reset (reset));
packet_composer #(
.WORKER_ADDR_WIDTH(WORKER_ADDR_WIDTH),
.TOTAL_DATA(TOTAL_DATA)
) composer (
// --- interface to next module
.out_wr (oq_in_wr),
.out_data (oq_in_data),
.out_ctrl (oq_in_ctrl), // new checksum assuming decremented TTL
.out_rdy (oq_in_rdy),
//.out_rdy (), //Deepak - TEST ONLY
.iteration_accum_value (iteration_accum_value),
.iteration_terminate_check (check_terminate),
//read interface from DDR (used by flush data function)
.dram_fifo_readdata (dram_fifo_readdata),
.dram_fifo_read (dram_fifo_read),
.dram_fifo_empty (dram_fifo_empty),
.num_keys (num_keys),
//i/f b/w TX EXT FIFO and packet composer
.tx_ext_update_0_q (tx_ext_update_0_q),
.tx_ext_update_0_rdreq (tx_ext_update_0_rdreq),
.tx_ext_update_0_empty (tx_ext_update_0_empty),
.tx_ext_update_0_almost_full (tx_ext_update_0_almost_full),
//i/f b/w TX EXT FIFO and packet composer
.tx_ext_update_1_q (tx_ext_update_1_q),
.tx_ext_update_1_rdreq (tx_ext_update_1_rdreq),
.tx_ext_update_1_empty (tx_ext_update_1_empty),
.tx_ext_update_1_almost_full (tx_ext_update_1_almost_full),
//i/f b/w TX EXT FIFO and packet composer
.tx_ext_update_2_q (tx_ext_update_2_q),
.tx_ext_update_2_rdreq (tx_ext_update_2_rdreq),
.tx_ext_update_2_empty (tx_ext_update_2_empty),
.tx_ext_update_2_almost_full (tx_ext_update_2_almost_full),
//i/f b/w TX EXT FIFO and packet composer
.tx_ext_update_3_q (tx_ext_update_3_q),
.tx_ext_update_3_rdreq (tx_ext_update_3_rdreq),
.tx_ext_update_3_empty (tx_ext_update_3_empty),
.tx_ext_update_3_almost_full (tx_ext_update_3_almost_full),
.interpkt_gap_cycles (interpkt_gap_cycles),
.shard_id (shard_id),
.log_2_num_workers_in (log_2_num_workers),
.start_update (start_update),
// misc
.reset ((reset|compute_system_reset)),//pkt composer although instantiated here must be reset along with compute system
.clk (clk)
);
output_queues
#(.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH),
.OP_LUT_STAGE_NUM(OP_LUT_STAGE_NUM),
.NUM_OUTPUT_QUEUES(NUM_OUTPUT_QUEUES),
.STAGE_NUM(OQ_STAGE_NUM),
.SRAM_ADDR_WIDTH(SRAM_ADDR_WIDTH))
output_queues
(// --- data path interface
.out_data_0 (out_data_0),
.out_ctrl_0 (out_ctrl_0),
.out_wr_0 (out_wr_0),
.out_rdy_0 (out_rdy_0),
.out_data_1 (out_data_1),
.out_ctrl_1 (out_ctrl_1),
.out_wr_1 (out_wr_1),
.out_rdy_1 (out_rdy_1),
.out_data_2 (out_data_2),
.out_ctrl_2 (out_ctrl_2),
.out_wr_2 (out_wr_2),
.out_rdy_2 (out_rdy_2),
.out_data_3 (out_data_3),
.out_ctrl_3 (out_ctrl_3),
.out_wr_3 (out_wr_3),
.out_rdy_3 (out_rdy_3),
.out_data_4 (out_data_4),
.out_ctrl_4 (out_ctrl_4),
.out_wr_4 (out_wr_4),
.out_rdy_4 (out_rdy_4),
.out_data_5 (out_data_5),
.out_ctrl_5 (out_ctrl_5),
.out_wr_5 (out_wr_5),
.out_rdy_5 (out_rdy_5),
.out_data_6 (out_data_6),
.out_ctrl_6 (out_ctrl_6),
.out_wr_6 (out_wr_6),
.out_rdy_6 (out_rdy_6),
.out_data_7 (out_data_7),
.out_ctrl_7 (out_ctrl_7),
.out_wr_7 (out_wr_7),
.out_rdy_7 (out_rdy_7),
// --- Interface to the previous module
.in_data (oq_in_data),
.in_ctrl (oq_in_ctrl),
.in_rdy (oq_in_rdy),
.in_wr (oq_in_wr),
// --- Register interface
.reg_req_in (oq_in_reg_req),
.reg_ack_in (oq_in_reg_ack),
.reg_rd_wr_L_in (oq_in_reg_rd_wr_L),
.reg_addr_in (oq_in_reg_addr),
.reg_data_in (oq_in_reg_data),
.reg_src_in (oq_in_reg_src),
.reg_req_out (udp_reg_req_in),
.reg_ack_out (udp_reg_ack_in),
.reg_rd_wr_L_out (udp_reg_rd_wr_L_in),
.reg_addr_out (udp_reg_addr_in),
.reg_data_out (udp_reg_data_in),
.reg_src_out (udp_reg_src_in),
// --- SRAM sm interface
.wr_0_addr (wr_0_addr),
.wr_0_req (wr_0_req),
.wr_0_ack (wr_0_ack),
.wr_0_data (wr_0_data),
.rd_0_ack (rd_0_ack),
.rd_0_data (rd_0_data),
.rd_0_vld (rd_0_vld),
.rd_0_addr (rd_0_addr),
.rd_0_req (rd_0_req),
// --- Misc
.clk (clk),
.reset (reset));
//--------------------------------------------------
//
// --- User data path register master
//
// Takes the register accesses from core,
// sends them around the User Data Path module
// ring and then returns the replies back
// to the core
//
//--------------------------------------------------
udp_reg_master #(
.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH)
) udp_reg_master (
// Core register interface signals
.core_reg_req (reg_req),
.core_reg_ack (reg_ack),
.core_reg_rd_wr_L (reg_rd_wr_L),
.core_reg_addr (reg_addr),
.core_reg_rd_data (reg_rd_data),
.core_reg_wr_data (reg_wr_data),
// UDP register interface signals (output)
.reg_req_out (in_arb_in_reg_req),
.reg_ack_out (in_arb_in_reg_ack),
.reg_rd_wr_L_out (in_arb_in_reg_rd_wr_L),
.reg_addr_out (in_arb_in_reg_addr),
.reg_data_out (in_arb_in_reg_data),
.reg_src_out (in_arb_in_reg_src),
// UDP register interface signals (input)
.reg_req_in (udp_reg_req_in),
.reg_ack_in (udp_reg_ack_in),
.reg_rd_wr_L_in (udp_reg_rd_wr_L_in),
.reg_addr_in (udp_reg_addr_in),
.reg_data_in (udp_reg_data_in),
.reg_src_in (udp_reg_src_in),
//
.clk (clk),
.reset (reset)
);
endmodule // user_data_path
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ccx_arbctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
//
// Module Name: ccx_arbdp.v
// Description: Datapath portion of arbiter
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
// Code start here
//
module ccx_arbctl(/*AUTOARG*/
// Outputs
scan_out, arbctl_atom, reset_d1, direction, wrptr_l, rdptr,
fifo_sel15_12, fifo_sel11_8, fifo_sel7_4, fifo_sel3_0,
fifo_bypass, fifo_bypass_l, fifo_valid, qfull, input_req_sel,
input_req_sel_d1, fifo_req_sel, current_req_sel, stall_a,
ccx_dest_data_rdy_x, ccx_dest_atom_x, arb_dp_q0_hold_a,
arb_dp_qsel0_a, arb_dp_qsel1_a, arb_dp_shift_x,
// Inputs
src7_arb_atom_q, src6_arb_atom_q, src5_arb_atom_q,
src4_arb_atom_q, src3_arb_atom_q, src2_arb_atom_q,
src1_arb_atom_q, src0_arb_atom_q, src7_arb_req_q, src6_arb_req_q,
src5_arb_req_q, src4_arb_req_q, src3_arb_req_q, src2_arb_req_q,
src1_arb_req_q, src0_arb_req_q, stall1_q, stall2_q,
ccx_dest_data_rdy_a, ccx_dest_atom_a, grant_a, req_pkt_empty,
inreg_req_vld_d1, reset_l, rclk, adbginit_l, se
);
//Outputs
//Global outs to arbdp
output reset_d1;
output direction;//bit setting direction for PE
//Outputs to FIFO section
output [15:0] wrptr_l;
output [15:0] rdptr;
output fifo_sel15_12,fifo_sel11_8, fifo_sel7_4, fifo_sel3_0;
output fifo_bypass, fifo_bypass_l;
output fifo_valid;
//Outputs to PE section
output [7:0] qfull;
output input_req_sel, input_req_sel_d1;
output fifo_req_sel, current_req_sel;
output stall_a;
//Outputs to destination.
output ccx_dest_data_rdy_x;
output ccx_dest_atom_x;
//Outputs to dp
output [7:0] arb_dp_q0_hold_a;
output [7:0] arb_dp_qsel0_a;
output [7:0] arb_dp_qsel1_a;
output [7:0] arb_dp_shift_x;
//Outputs to datapaths
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [7:0] arbctl_atom; // From atomq0 of ccx_arb_atomq.v, ...
output scan_out; // From atomq0 of ccx_arb_atomq.v, ...
// End of automatics
//INPUTS
//Inputs from sources
input src7_arb_atom_q;//
input src6_arb_atom_q;
input src5_arb_atom_q;
input src4_arb_atom_q;
input src3_arb_atom_q;
input src2_arb_atom_q;
input src1_arb_atom_q;
input src0_arb_atom_q;
input src7_arb_req_q;//i
input src6_arb_req_q;
input src5_arb_req_q;
input src4_arb_req_q;
input src3_arb_req_q;
input src2_arb_req_q;
input src1_arb_req_q;
input src0_arb_req_q;
//Inputs from destination
input stall1_q;
input stall2_q;
//Inputs from PE section of arbdp
input ccx_dest_data_rdy_a;
input ccx_dest_atom_a;
input [7:0] grant_a;
input req_pkt_empty;
input inreg_req_vld_d1;
//Global inputs
input reset_l;
// input dbginit_l;
input rclk;
// input tmb_l;
input adbginit_l;
input se;
//WIRES
//Global wires
wire reset;
wire dbginit;
//Wires in fifo control logic
wire fifo_rd_vld_d1;
wire fifo_wr_vld_d1;
// wire [15:0] vvec_wr_update_d1;
// wire [15:0] vvec_rd_update_d1;
// wire [15:0] vvec_d1, vvec_d2, vvec_unq_d1;
wire fifo_empty_d1 ;
wire fifo_empty_d1_l;
wire fifo_empty_d2 ;
wire fifo_bypass_d1,fifo_bypass, fifo_bypass_l;
wire fifo_valid ;
wire [4:0] rdptr_mux,rdptr_d1, rdptr_inc,rdptr_inc_d1;
wire [4:0] wrptr,wrptr_d1, wrptr_inc;
wire wr_en, wr_en_d1 ;
wire rd_en, rd_en_d1 ;
wire [15:0] wrptr_dcd,wrptr_l;
wire [15:0] rdptr;
wire current_req_sel_d1;
wire fifo_req_sel_d1;
wire direction_in;
wire stall1_a, stall2_a;
wire wrap_wren;
wire rdptr_dcd_3,
rdptr_dcd_7,
rdptr_dcd_11,
rdptr_dcd_15;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] atom_a; // From q0 of ccx_arb_srcq.v, ...
wire [7:0] ctl_qsel0_a; // From q0 of ccx_arb_srcq.v, ...
wire [7:0] ctl_qsel1_a_l; // From q0 of ccx_arb_srcq.v, ...
wire [7:0] ctl_shift_a; // From q0 of ccx_arb_srcq.v, ...
// End of automatics
wire ccx_reset_l_d1,ccx_reset2_l_d1;
wire dbginit_d1;
// Global signals
//assign dbginit = ~dbginit_l;
assign dbginit_d1 = ~ccx_reset2_l_d1;
// reset flop
dffrl_async ff_rstl(
.din(reset_l),
.q(ccx_reset_l_d1),
.clk(rclk),
.se(se),
.rst_l(adbginit_l));
assign reset_d1 = ~ccx_reset_l_d1;
// dff dff_ccx_arb_dbginit(
// .din (dbginit),
// .q (dbginit_d1),
// .clk (rclk),
// .se (1'd0),
// .si (1'd0),
// .so ());
dffrl_async ff_rstl2(
.din(reset_l),
.q(ccx_reset2_l_d1),
.clk(rclk),
.se(se),
.rst_l(adbginit_l));
// Generate direction bit for use in setting priority direction for
// incoming request packets.
assign direction_in = ~direction | dbginit_d1;
dff_s #(1) dff_ccx_com_dir(
.din (direction_in),
.q (direction),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
//Priority Encoder related logic
// Logic to generate selects for request mux
assign current_req_sel = ~req_pkt_empty & ~reset_d1;
assign fifo_req_sel = req_pkt_empty & (fifo_valid & ~input_req_sel_d1) & ~reset_d1;
assign input_req_sel = req_pkt_empty & ~(fifo_valid & ~input_req_sel_d1) | reset_d1;
//flop and drive data ready signal
dff_s #(1) dff_ccx_com_dr( //relocate this flop to ctl
.din (ccx_dest_data_rdy_a), //section.
.q (ccx_dest_data_rdy_x),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
dff_s #(1) dff_ccx_atom_dr(
.din (ccx_dest_atom_a),
.q (ccx_dest_atom_x),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
// generate stall signal
dff_s dff_ccx_arb_stall1(
.din (stall1_q),
.q (stall1_a),
.clk (rclk),
.se (1'd0),
.si (1'd0),
.so ());
dff_s dff_ccx_arb_stall2(
.din (stall2_q),
.q (stall2_a),
.clk (rclk),
.se (1'd0),
.si (1'd0),
.so ());
assign stall_a = stall1_a | stall2_a;
dff_s dff_ccx_arb_inpsel(
.din (input_req_sel),
.q (input_req_sel_d1),
.clk (rclk),
.se (1'd0),
.si (1'd0),
.so ());
// FIFO related logic
// setup flops for control
// dff #(16) dff_ccx_com_fifo_vvecd1(
// .din (vvec_d1[15:0]),
// .q (vvec_d2[15:0]),
// .clk (rclk),
// .se (1'b0),
// .si (16'd0),
// .so ());
// dff #(16) dff_ccx_com_fifo_wrptrd1(
dff_s #(5) dff_ccx_com_fifo_wrptrd1(
.din (wrptr[4:0]),
.q (wrptr_d1[4:0]),
.clk (rclk),
.se (1'b0),
.si (5'd0),
.so ());
// dff #(16) dff_ccx_com_fifo_rdptrd1(
// .din (rdptr[15:0]),
dff_s #(5) dff_ccx_com_fifo_rdptrd1(
.din (rdptr_mux[4:0]),
.q (rdptr_d1[4:0]),
.clk (rclk),
.se (1'b0),
.si (5'd0),
.so ());
dff_s #(1) dff_ccx_com_fifo_wrend1(
.din (wr_en),
.q (wr_en_d1),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
dff_s #(1) dff_ccx_com_fifo_rdend1(
.din (rd_en),
.q (rd_en_d1),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
dff_s #(1) dff_ccx_com_fifo_emptyd1(
.din (fifo_empty_d1),
.q (fifo_empty_d2),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
dff_s #(1) dff_ccx_com_fifo_bypassd1(
.din (fifo_bypass),
.q (fifo_bypass_d1),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
dff_s #(1) dff_ccx_com_fifo_fifoseld1(
.din (fifo_req_sel),
.q (fifo_req_sel_d1),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
dff_s #(1) dff_ccx_com_fifo_currseld1(
.din (current_req_sel),
.q (current_req_sel_d1),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
dff_s #(5) dff_ccx_rdptr_incd1(
.din (rdptr_inc[4:0]),
.q (rdptr_inc_d1[4:0]),
.clk (rclk),
.se (1'b0),
.si (5'd0),
.so ());
//see if any valid requests in flopped request packet.
// assign inreg_req_vld_d1 = |(req_d1[9:0]) ;
//compute if valid read, write ops were performed in prev cycle
assign fifo_rd_vld_d1 = rd_en_d1 & ~fifo_bypass_d1 & fifo_req_sel_d1;
assign fifo_wr_vld_d1 = wr_en_d1 & ~(fifo_bypass_d1 & fifo_req_sel_d1);
//if valid read/write ops then compute new fifo state (vvec_d1)
// assign vvec_wr_update_d1[15:0] = fifo_wr_vld_d1 ? wrptr_d1[15:0] : 16'd0;
// assign vvec_rd_update_d1[15:0] = fifo_rd_vld_d1 ? rdptr_d1[15:0] : 16'd0;
// assign vvec_unq_d1[15:0] = (vvec_wr_update_d1[15:0] | (vvec_d2[15:0] & ~vvec_rd_update_d1[15:0]));
// assign vvec_d1[15:0] = reset_d1 ? 16'd0 : vvec_unq_d1[15:0];
//Determine if fifo is empty
// assign fifo_empty_d1 =~( |(vvec_d1[15:0]));
// need extra state to detect full(overflow) condition
//--------------------------------------------------------------------------------------------
// 0 1 2 3 4 5
//--------------------------------------------------------------------------------------------
// req=1 req=1 req=1 req=1
// wrptr=0 1 2 3 0 0
// rdptr=0 0 0 0 0 0
// (empty) (full) (full)
//--------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------
// 0 1 2 3 4 5
//--------------------------------------------------------------------------------------------
// spc_req=1 fifo wr fifo rd arb(pa) px1
// wrptr=0 wrptr=1
// rdptr=0 rdptr=0 rdptr=1
// rdptr_inc=1 rdptr_inc=2
//--------------------------------------------------------------------------------------------
assign fifo_empty_d1 = &(wrptr[4:0] ~^ rdptr_mux[4:0]);
assign fifo_empty_d1_l = ~fifo_empty_d1 ;
//Determine if data needs to be bypassed around flop array.
assign fifo_bypass = inreg_req_vld_d1 & fifo_empty_d1 ;
assign fifo_bypass_l = ~fifo_bypass;
//Determine if fifo contains valid request packet.
assign fifo_valid = inreg_req_vld_d1 | fifo_empty_d1_l;
//Compute new read and write pointers
// assign rdptr_inc[15:0] = {rdptr_d1[14:0],rdptr_d1[15]};
// assign wrptr_inc[15:0] = {wrptr_d1[14:0],wrptr_d1[15]};
// increment - rdptr + 1
assign rdptr_inc[0] = ~rdptr_mux[0];
assign rdptr_inc[1] = rdptr_mux[1] ^ rdptr_mux[0];
assign rdptr_inc[2] = (~&(rdptr_mux[1:0]) ~^ rdptr_mux[2]);
assign rdptr_inc[3] = (~&(rdptr_mux[2:0]) ~^ rdptr_mux[3]);
assign rdptr_inc[4] = (~&(rdptr_mux[3:0]) ~^ rdptr_mux[4]);
// increment - wrptr + 1
assign wrptr_inc[0] = ~wrptr_d1[0];
assign wrptr_inc[1] = wrptr_d1[1] ^ wrptr_d1[0];
assign wrptr_inc[2] = (~&(wrptr_d1[1:0]) ~^ wrptr_d1[2]);
assign wrptr_inc[3] = (~&(wrptr_d1[2:0]) ~^ wrptr_d1[3]);
assign wrptr_inc[4] = (~&(wrptr_d1[3:0]) ~^ wrptr_d1[4]);
// assign wrptr[15:0]=(fifo_empty_d2 & ~fifo_wr_vld_d1| reset_d1) ? {15'd0,1'b1} : (fifo_wr_vld_d1 ? wrptr_inc[15:0] : wrptr_d1[15:0]);
// assign rdptr[15:0]=(fifo_empty_d2 & ~fifo_wr_vld_d1 | reset_d1) ? {15'd0,1'b1} : (fifo_rd_vld_d1 ? rdptr_inc[15:0] : rdptr_d1[15:0]);
assign wrptr[4:0] = (fifo_empty_d2 & ~fifo_wr_vld_d1| reset_d1) ? 5'h0 : (fifo_wr_vld_d1 ? wrptr_inc[4:0] : wrptr_d1[4:0]);
// decode write pointer
assign wrptr_dcd[0] = (~wrptr[3] & ~wrptr[2] & ~wrptr[1] & ~wrptr[0]);
assign wrptr_dcd[1] = (~wrptr[3] & ~wrptr[2] & ~wrptr[1] & wrptr[0]);
assign wrptr_dcd[2] = (~wrptr[3] & ~wrptr[2] & wrptr[1] & ~wrptr[0]);
assign wrptr_dcd[3] = (~wrptr[3] & ~wrptr[2] & wrptr[1] & wrptr[0]);
assign wrptr_dcd[4] = (~wrptr[3] & wrptr[2] & ~wrptr[1] & ~wrptr[0]);
assign wrptr_dcd[5] = (~wrptr[3] & wrptr[2] & ~wrptr[1] & wrptr[0]);
assign wrptr_dcd[6] = (~wrptr[3] & wrptr[2] & wrptr[1] & ~wrptr[0]);
assign wrptr_dcd[7] = (~wrptr[3] & wrptr[2] & wrptr[1] & wrptr[0]);
assign wrptr_dcd[8] = ( wrptr[3] & ~wrptr[2] & ~wrptr[1] & ~wrptr[0]);
assign wrptr_dcd[9] = ( wrptr[3] & ~wrptr[2] & ~wrptr[1] & wrptr[0]);
assign wrptr_dcd[10] = ( wrptr[3] & ~wrptr[2] & wrptr[1] & ~wrptr[0]);
assign wrptr_dcd[11] = ( wrptr[3] & ~wrptr[2] & wrptr[1] & wrptr[0]);
assign wrptr_dcd[12] = ( wrptr[3] & wrptr[2] & ~wrptr[1] & ~wrptr[0]);
assign wrptr_dcd[13] = ( wrptr[3] & wrptr[2] & ~wrptr[1] & wrptr[0]);
assign wrptr_dcd[14] = ( wrptr[3] & wrptr[2] & wrptr[1] & ~wrptr[0]);
assign wrptr_dcd[15] = ( wrptr[3] & wrptr[2] & wrptr[1] & wrptr[0]);
assign wrptr_l[15:0] = ~(wrptr_dcd[15:0]);
assign rdptr_mux[4:0]=(fifo_empty_d2 & ~fifo_wr_vld_d1 | reset_d1) ? 5'h0 : (fifo_rd_vld_d1 ? rdptr_inc_d1[4:0] : rdptr_d1[4:0]);
// decode read pointer
assign rdptr[0] = (~rdptr_mux[3] & ~rdptr_mux[2] & ~rdptr_mux[1] & ~rdptr_mux[0]);
assign rdptr[1] = (~rdptr_mux[3] & ~rdptr_mux[2] & ~rdptr_mux[1] & rdptr_mux[0]);
assign rdptr[2] = (~rdptr_mux[3] & ~rdptr_mux[2] & rdptr_mux[1] & ~rdptr_mux[0]);
assign rdptr[3] = ~|rdptr[2:0];
assign rdptr_dcd_3 = (~rdptr_mux[3] & ~rdptr_mux[2] & rdptr_mux[1] & rdptr_mux[0]);
assign rdptr[4] = (~rdptr_mux[3] & rdptr_mux[2] & ~rdptr_mux[1] & ~rdptr_mux[0]);
assign rdptr[5] = (~rdptr_mux[3] & rdptr_mux[2] & ~rdptr_mux[1] & rdptr_mux[0]);
assign rdptr[6] = (~rdptr_mux[3] & rdptr_mux[2] & rdptr_mux[1] & ~rdptr_mux[0]);
assign rdptr[7] = ~|rdptr[6:4];
assign rdptr_dcd_7 = (~rdptr_mux[3] & rdptr_mux[2] & rdptr_mux[1] & rdptr_mux[0]);
assign rdptr[8] = ( rdptr_mux[3] & ~rdptr_mux[2] & ~rdptr_mux[1] & ~rdptr_mux[0]);
assign rdptr[9] = ( rdptr_mux[3] & ~rdptr_mux[2] & ~rdptr_mux[1] & rdptr_mux[0]);
assign rdptr[10] = ( rdptr_mux[3] & ~rdptr_mux[2] & rdptr_mux[1] & ~rdptr_mux[0]);
assign rdptr[11] = ~|rdptr[10:8];
assign rdptr_dcd_11 = ( rdptr_mux[3] & ~rdptr_mux[2] & rdptr_mux[1] & rdptr_mux[0]);
assign rdptr[12] = ( rdptr_mux[3] & rdptr_mux[2] & ~rdptr_mux[1] & ~rdptr_mux[0]);
assign rdptr[13] = ( rdptr_mux[3] & rdptr_mux[2] & ~rdptr_mux[1] & rdptr_mux[0]);
assign rdptr[14] = ( rdptr_mux[3] & rdptr_mux[2] & rdptr_mux[1] & ~rdptr_mux[0]);
assign rdptr[15] = ~|rdptr[14:12];
assign rdptr_dcd_15 = ( rdptr_mux[3] & rdptr_mux[2] & rdptr_mux[1] & rdptr_mux[0]);
assign fifo_sel15_12 = |({rdptr_dcd_15,rdptr[14:12]});
assign fifo_sel11_8 = |({rdptr_dcd_11,rdptr[10:8]});
assign fifo_sel7_4 = |({rdptr_dcd_7, rdptr[6:4]});
assign fifo_sel3_0 = |({rdptr_dcd_3, rdptr[2:0]});
//Determine if a valid write was performed in current cycle. - wrptr will not catch up w/ rdptr 'cos the req source stalls.
// assign wrap_wren = ~(|(wrptr_inc[15:0] & rdptr_d1[15:0])) | fifo_empty_d1;
assign wrap_wren = ~(&(wrptr[3:0] ~^ rdptr_mux[3:0]) & (wrptr_inc[4] ^ rdptr_inc[4])) | fifo_empty_d1;
assign wr_en = (inreg_req_vld_d1 & (fifo_req_sel_d1 | current_req_sel_d1)) & wrap_wren & ~reset_d1;
//Determine if valid read was performed in current cycle.
assign rd_en = fifo_empty_d1_l & ~reset_d1 ;
// ARB SRC Q LOGIC
/*
ccx_arb_srcq AUTO_TEMPLATE(
// Outputs
.qfull (qfull[@]),
.qsel0 (arb_dp_qsel0_a[@]),
.qsel1 (arb_dp_qsel1_a[@]),
.shift_x (arb_dp_shift_x[@]),
.shift_a (arb_ctl_shift_a[@]),
.q0_hold_a (arb_dp_q0_hold_a[@]),
.atom_a(atom_a[@]),
.ctl_qsel0_a (ctl_qsel0_a[@]),
.ctl_qsel1_a_l (ctl_qsel1_a_l[@]),
.ctl_shift_a (ctl_shift_a[@]),
// Inputs
.req_q (src@_arb_req_q),
.atom_q (src@_arb_atom_q),
.grant_a (grant_a[@]),
.reset_d1 (reset_d1));
*/
ccx_arb_srcq q0(/*AUTOINST*/
// Outputs
.qfull (qfull[0]), // Templated
.qsel0 (arb_dp_qsel0_a[0]), // Templated
.qsel1 (arb_dp_qsel1_a[0]), // Templated
.shift_x (arb_dp_shift_x[0]), // Templated
.ctl_qsel0_a (ctl_qsel0_a[0]), // Templated
.ctl_qsel1_a_l (ctl_qsel1_a_l[0]), // Templated
.ctl_shift_a (ctl_shift_a[0]), // Templated
.q0_hold_a (arb_dp_q0_hold_a[0]), // Templated
.atom_a (atom_a[0]), // Templated
// Inputs
.req_q (src0_arb_req_q), // Templated
.atom_q (src0_arb_atom_q), // Templated
.grant_a (grant_a[0]), // Templated
.rclk (rclk),
.reset_d1 (reset_d1)); // Templated
ccx_arb_srcq q1(/*AUTOINST*/
// Outputs
.qfull (qfull[1]), // Templated
.qsel0 (arb_dp_qsel0_a[1]), // Templated
.qsel1 (arb_dp_qsel1_a[1]), // Templated
.shift_x (arb_dp_shift_x[1]), // Templated
.ctl_qsel0_a (ctl_qsel0_a[1]), // Templated
.ctl_qsel1_a_l (ctl_qsel1_a_l[1]), // Templated
.ctl_shift_a (ctl_shift_a[1]), // Templated
.q0_hold_a (arb_dp_q0_hold_a[1]), // Templated
.atom_a (atom_a[1]), // Templated
// Inputs
.req_q (src1_arb_req_q), // Templated
.atom_q (src1_arb_atom_q), // Templated
.grant_a (grant_a[1]), // Templated
.rclk (rclk),
.reset_d1 (reset_d1)); // Templated
ccx_arb_srcq q2(/*AUTOINST*/
// Outputs
.qfull (qfull[2]), // Templated
.qsel0 (arb_dp_qsel0_a[2]), // Templated
.qsel1 (arb_dp_qsel1_a[2]), // Templated
.shift_x (arb_dp_shift_x[2]), // Templated
.ctl_qsel0_a (ctl_qsel0_a[2]), // Templated
.ctl_qsel1_a_l (ctl_qsel1_a_l[2]), // Templated
.ctl_shift_a (ctl_shift_a[2]), // Templated
.q0_hold_a (arb_dp_q0_hold_a[2]), // Templated
.atom_a (atom_a[2]), // Templated
// Inputs
.req_q (src2_arb_req_q), // Templated
.atom_q (src2_arb_atom_q), // Templated
.grant_a (grant_a[2]), // Templated
.rclk (rclk),
.reset_d1 (reset_d1)); // Templated
ccx_arb_srcq q3(/*AUTOINST*/
// Outputs
.qfull (qfull[3]), // Templated
.qsel0 (arb_dp_qsel0_a[3]), // Templated
.qsel1 (arb_dp_qsel1_a[3]), // Templated
.shift_x (arb_dp_shift_x[3]), // Templated
.ctl_qsel0_a (ctl_qsel0_a[3]), // Templated
.ctl_qsel1_a_l (ctl_qsel1_a_l[3]), // Templated
.ctl_shift_a (ctl_shift_a[3]), // Templated
.q0_hold_a (arb_dp_q0_hold_a[3]), // Templated
.atom_a (atom_a[3]), // Templated
// Inputs
.req_q (src3_arb_req_q), // Templated
.atom_q (src3_arb_atom_q), // Templated
.grant_a (grant_a[3]), // Templated
.rclk (rclk),
.reset_d1 (reset_d1)); // Templated
ccx_arb_srcq q4(/*AUTOINST*/
// Outputs
.qfull (qfull[4]), // Templated
.qsel0 (arb_dp_qsel0_a[4]), // Templated
.qsel1 (arb_dp_qsel1_a[4]), // Templated
.shift_x (arb_dp_shift_x[4]), // Templated
.ctl_qsel0_a (ctl_qsel0_a[4]), // Templated
.ctl_qsel1_a_l (ctl_qsel1_a_l[4]), // Templated
.ctl_shift_a (ctl_shift_a[4]), // Templated
.q0_hold_a (arb_dp_q0_hold_a[4]), // Templated
.atom_a (atom_a[4]), // Templated
// Inputs
.req_q (src4_arb_req_q), // Templated
.atom_q (src4_arb_atom_q), // Templated
.grant_a (grant_a[4]), // Templated
.rclk (rclk),
.reset_d1 (reset_d1)); // Templated
ccx_arb_srcq q5(/*AUTOINST*/
// Outputs
.qfull (qfull[5]), // Templated
.qsel0 (arb_dp_qsel0_a[5]), // Templated
.qsel1 (arb_dp_qsel1_a[5]), // Templated
.shift_x (arb_dp_shift_x[5]), // Templated
.ctl_qsel0_a (ctl_qsel0_a[5]), // Templated
.ctl_qsel1_a_l (ctl_qsel1_a_l[5]), // Templated
.ctl_shift_a (ctl_shift_a[5]), // Templated
.q0_hold_a (arb_dp_q0_hold_a[5]), // Templated
.atom_a (atom_a[5]), // Templated
// Inputs
.req_q (src5_arb_req_q), // Templated
.atom_q (src5_arb_atom_q), // Templated
.grant_a (grant_a[5]), // Templated
.rclk (rclk),
.reset_d1 (reset_d1)); // Templated
ccx_arb_srcq q6(/*AUTOINST*/
// Outputs
.qfull (qfull[6]), // Templated
.qsel0 (arb_dp_qsel0_a[6]), // Templated
.qsel1 (arb_dp_qsel1_a[6]), // Templated
.shift_x (arb_dp_shift_x[6]), // Templated
.ctl_qsel0_a (ctl_qsel0_a[6]), // Templated
.ctl_qsel1_a_l (ctl_qsel1_a_l[6]), // Templated
.ctl_shift_a (ctl_shift_a[6]), // Templated
.q0_hold_a (arb_dp_q0_hold_a[6]), // Templated
.atom_a (atom_a[6]), // Templated
// Inputs
.req_q (src6_arb_req_q), // Templated
.atom_q (src6_arb_atom_q), // Templated
.grant_a (grant_a[6]), // Templated
.rclk (rclk),
.reset_d1 (reset_d1)); // Templated
ccx_arb_srcq q7(/*AUTOINST*/
// Outputs
.qfull (qfull[7]), // Templated
.qsel0 (arb_dp_qsel0_a[7]), // Templated
.qsel1 (arb_dp_qsel1_a[7]), // Templated
.shift_x (arb_dp_shift_x[7]), // Templated
.ctl_qsel0_a (ctl_qsel0_a[7]), // Templated
.ctl_qsel1_a_l (ctl_qsel1_a_l[7]), // Templated
.ctl_shift_a (ctl_shift_a[7]), // Templated
.q0_hold_a (arb_dp_q0_hold_a[7]), // Templated
.atom_a (atom_a[7]), // Templated
// Inputs
.req_q (src7_arb_req_q), // Templated
.atom_q (src7_arb_atom_q), // Templated
.grant_a (grant_a[7]), // Templated
.rclk (rclk),
.reset_d1 (reset_d1)); // Templated
/*
// queue to hold atomic bit - 8 instances of 2 deep entries
ccx_arb_atomq AUTO_TEMPLATE(
// Outputs
.q0_dataout(arbctl_atom[@]),
// Inputs
.ctl_qsel0_a (ctl_qsel0_a[@]),
.ctl_qsel1_a_l (ctl_qsel1_a_l[@]),
.ctl_shift_a (ctl_shift_a[@]),
.atom_a(atom_a[@]));
*/
ccx_arb_atomq atomq0(/*AUTOINST*/
// Outputs
.q0_dataout (arbctl_atom[0]), // Templated
`ifdef FPGA_SYN
.scan_out (/*scan_out*/),
`else
.scan_out (scan_out),
`endif
// Inputs
.ctl_qsel1_a_l (ctl_qsel1_a_l[0]), // Templated
.ctl_qsel0_a (ctl_qsel0_a[0]), // Templated
.ctl_shift_a (ctl_shift_a[0]), // Templated
.atom_a (atom_a[0]), // Templated
.rclk (rclk),
.reset_d1 (reset_d1));
ccx_arb_atomq atomq1(/*AUTOINST*/
// Outputs
.q0_dataout (arbctl_atom[1]), // Templated
`ifdef FPGA_SYN
.scan_out (/*scan_out*/),
`else
.scan_out (scan_out),
`endif
// Inputs
.ctl_qsel1_a_l (ctl_qsel1_a_l[1]), // Templated
.ctl_qsel0_a (ctl_qsel0_a[1]), // Templated
.ctl_shift_a (ctl_shift_a[1]), // Templated
.atom_a (atom_a[1]), // Templated
.rclk (rclk),
.reset_d1 (reset_d1));
ccx_arb_atomq atomq2(/*AUTOINST*/
// Outputs
.q0_dataout (arbctl_atom[2]), // Templated
`ifdef FPGA_SYN
.scan_out (/*scan_out*/),
`else
.scan_out (scan_out),
`endif
// Inputs
.ctl_qsel1_a_l (ctl_qsel1_a_l[2]), // Templated
.ctl_qsel0_a (ctl_qsel0_a[2]), // Templated
.ctl_shift_a (ctl_shift_a[2]), // Templated
.atom_a (atom_a[2]), // Templated
.rclk (rclk),
.reset_d1 (reset_d1));
ccx_arb_atomq atomq3(/*AUTOINST*/
// Outputs
.q0_dataout (arbctl_atom[3]), // Templated
`ifdef FPGA_SYN
.scan_out (/*scan_out*/),
`else
.scan_out (scan_out),
`endif
// Inputs
.ctl_qsel1_a_l (ctl_qsel1_a_l[3]), // Templated
.ctl_qsel0_a (ctl_qsel0_a[3]), // Templated
.ctl_shift_a (ctl_shift_a[3]), // Templated
.atom_a (atom_a[3]), // Templated
.rclk (rclk),
.reset_d1 (reset_d1));
ccx_arb_atomq atomq4(/*AUTOINST*/
// Outputs
.q0_dataout (arbctl_atom[4]), // Templated
`ifdef FPGA_SYN
.scan_out (/*scan_out*/),
`else
.scan_out (scan_out),
`endif
// Inputs
.ctl_qsel1_a_l (ctl_qsel1_a_l[4]), // Templated
.ctl_qsel0_a (ctl_qsel0_a[4]), // Templated
.ctl_shift_a (ctl_shift_a[4]), // Templated
.atom_a (atom_a[4]), // Templated
.rclk (rclk),
.reset_d1 (reset_d1));
ccx_arb_atomq atomq5(/*AUTOINST*/
// Outputs
.q0_dataout (arbctl_atom[5]), // Templated
`ifdef FPGA_SYN
.scan_out (/*scan_out*/),
`else
.scan_out (scan_out),
`endif
// Inputs
.ctl_qsel1_a_l (ctl_qsel1_a_l[5]), // Templated
.ctl_qsel0_a (ctl_qsel0_a[5]), // Templated
.ctl_shift_a (ctl_shift_a[5]), // Templated
.atom_a (atom_a[5]), // Templated
.rclk (rclk),
.reset_d1 (reset_d1));
ccx_arb_atomq atomq6(/*AUTOINST*/
// Outputs
.q0_dataout (arbctl_atom[6]), // Templated
`ifdef FPGA_SYN
.scan_out (/*scan_out*/),
`else
.scan_out (scan_out),
`endif
// Inputs
.ctl_qsel1_a_l (ctl_qsel1_a_l[6]), // Templated
.ctl_qsel0_a (ctl_qsel0_a[6]), // Templated
.ctl_shift_a (ctl_shift_a[6]), // Templated
.atom_a (atom_a[6]), // Templated
.rclk (rclk),
.reset_d1 (reset_d1));
ccx_arb_atomq atomq7(/*AUTOINST*/
// Outputs
.q0_dataout (arbctl_atom[7]), // Templated
`ifdef FPGA_SYN
.scan_out (/*scan_out*/),
`else
.scan_out (scan_out),
`endif
// Inputs
.ctl_qsel1_a_l (ctl_qsel1_a_l[7]), // Templated
.ctl_qsel0_a (ctl_qsel0_a[7]), // Templated
.ctl_shift_a (ctl_shift_a[7]), // Templated
.atom_a (atom_a[7]), // Templated
.rclk (rclk),
.reset_d1 (reset_d1));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../../../common/rtl")
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND2B_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__AND2B_PP_BLACKBOX_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__and2b (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND2B_PP_BLACKBOX_V
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
// IP Revision: 15
(* X_CORE_INFO = "axi_crossbar_v2_1_15_axi_crossbar,Vivado 2017.3" *)
(* CHECK_LICENSE_TYPE = "design_1_xbar_0,axi_crossbar_v2_1_15_axi_crossbar,{}" *)
(* CORE_GENERATION_INFO = "design_1_xbar_0,axi_crossbar_v2_1_15_axi_crossbar,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_crossbar,x_ipVersion=2.1,x_ipCoreRevision=15,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_NUM_SLAVE_SLOTS=1,C_NUM_MASTER_SLOTS=2,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_PROTOCOL=0,C_NUM_ADDR_RANGES=1,C_M_AXI_BASE_ADDR=0x00000000c00000000000000000000000,C_M_AXI_ADDR_WIDTH=0x0000000d0000001d,C_S_AXI_BASE_ID=0x00000000,C_S_AXI_THREAD_ID_\
WIDTH=0x00000000,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_M_AXI_WRITE_CONNECTIVITY=0xFFFFFFFFFFFFFFFF,C_M_AXI_READ_CONNECTIVITY=0xFFFFFFFFFFFFFFFF,C_R_REGISTER=0,C_S_AXI_SINGLE_THREAD=0x00000000,C_S_AXI_WRITE_ACCEPTANCE=0x00000002,C_S_AXI_READ_ACCEPTANCE=0x00000002,C_M_AXI_WRITE_ISSUING=0x0000000200000008,C_M_AXI_READ_ISSUING=0x0000000200000008,C_S_AXI_ARB_PRIORITY=0x00000000,C_M_AXI_SECURE=0x00000000,C_\
CONNECTIVITY_MODE=1}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xbar_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI, ASSOCIATED_RESET ARESETN" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
input wire [0 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
output wire [0 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
input wire [63 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
input wire [7 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WLAST" *)
input wire [0 : 0] s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
input wire [0 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
output wire [0 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
output wire [0 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
input wire [0 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
input wire [0 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
output wire [0 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
output wire [63 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RLAST" *)
output wire [0 : 0] s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
output wire [0 : 0] s_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
input wire [0 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32]" *)
output wire [63 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLEN [7:0] [15:8]" *)
output wire [15 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWSIZE [2:0] [5:3]" *)
output wire [5 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI AWBURST [1:0] [3:2]" *)
output wire [3 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLOCK [0:0] [1:1]" *)
output wire [1 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWCACHE [3:0] [7:4]" *)
output wire [7 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3]" *)
output wire [5 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREGION [3:0] [7:4]" *)
output wire [7 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWQOS [3:0] [7:4]" *)
output wire [7 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1]" *)
output wire [1 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1]" *)
input wire [1 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [63:0] [63:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [63:0] [127:64]" *)
output wire [127 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [7:0] [15:8]" *)
output wire [15 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WLAST [0:0] [1:1]" *)
output wire [1 : 0] m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1]" *)
output wire [1 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1]" *)
input wire [1 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2]" *)
input wire [3 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1]" *)
input wire [1 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1]" *)
output wire [1 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32]" *)
output wire [63 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLEN [7:0] [15:8]" *)
output wire [15 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARSIZE [2:0] [5:3]" *)
output wire [5 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI ARBURST [1:0] [3:2]" *)
output wire [3 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLOCK [0:0] [1:1]" *)
output wire [1 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARCACHE [3:0] [7:4]" *)
output wire [7 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3]" *)
output wire [5 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREGION [3:0] [7:4]" *)
output wire [7 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARQOS [3:0] [7:4]" *)
output wire [7 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1]" *)
output wire [1 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1]" *)
input wire [1 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [63:0] [63:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [63:0] [127:64]" *)
input wire [127 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2]" *)
input wire [3 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RLAST [0:0] [1:1]" *)
input wire [1 : 0] m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1]" *)
input wire [1 : 0] m_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M00_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 128, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 128, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1]" *)
output wire [1 : 0] m_axi_rready;
axi_crossbar_v2_1_15_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(1),
.C_NUM_MASTER_SLOTS(2),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_PROTOCOL(0),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(128'H00000000c00000000000000000000000),
.C_M_AXI_ADDR_WIDTH(64'H0000000d0000001d),
.C_S_AXI_BASE_ID(32'H00000000),
.C_S_AXI_THREAD_ID_WIDTH(32'H00000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(64'HFFFFFFFFFFFFFFFF),
.C_M_AXI_READ_CONNECTIVITY(64'HFFFFFFFFFFFFFFFF),
.C_R_REGISTER(0),
.C_S_AXI_SINGLE_THREAD(32'H00000000),
.C_S_AXI_WRITE_ACCEPTANCE(32'H00000002),
.C_S_AXI_READ_ACCEPTANCE(32'H00000002),
.C_M_AXI_WRITE_ISSUING(64'H0000000200000008),
.C_M_AXI_READ_ISSUING(64'H0000000200000008),
.C_S_AXI_ARB_PRIORITY(32'H00000000),
.C_M_AXI_SECURE(32'H00000000),
.C_CONNECTIVITY_MODE(1)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(2'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(2'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(2'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(2'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
///////////////////////////////////////////////////////
// Copyright (c) 2010 Xilinx Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / 7SERIES IN FIFO
// /__/ /\ Filename : IN_FIFO.v
// \ \ / \
// \__\/\__ \
//
// Date: Comment:
// 08MAR2010 Initial UNI/UNP/SIM version from yml
// 03JUN2010 yml update
// 29JUN2010 enable encrypted rtl
// 10AUG2010 yml, rtl update
// 29SEP2010 minor cleanup
// add width checks, full path support
// 28OCT2010 rtl update
// 05NOV2010 update defaults
// 11JAN2011 586040 correct spelling XIL_TIMING vs XIL_TIMIMG
// 15AUG2011 621681 remove SIM_SPEEDUP, make default
// 21SEP2011 625537 period checks on RDCLK, WRCLK
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module IN_FIFO (
ALMOSTEMPTY,
ALMOSTFULL,
EMPTY,
FULL,
Q0,
Q1,
Q2,
Q3,
Q4,
Q5,
Q6,
Q7,
Q8,
Q9,
D0,
D1,
D2,
D3,
D4,
D5,
D6,
D7,
D8,
D9,
RDCLK,
RDEN,
RESET,
WRCLK,
WREN
);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
parameter integer ALMOST_EMPTY_VALUE = 1;
parameter integer ALMOST_FULL_VALUE = 1;
parameter ARRAY_MODE = "ARRAY_MODE_4_X_8";
parameter SYNCHRONOUS_MODE = "FALSE";
`ifdef XIL_TIMING
localparam in_delay = 0;
localparam out_delay = 0;
`else
localparam in_delay = 1;
localparam out_delay = 10;
`endif
localparam INCLK_DELAY = 0;
localparam OUTCLK_DELAY = 0;
localparam MODULE_NAME = "IN_FIFO";
output ALMOSTEMPTY;
output ALMOSTFULL;
output EMPTY;
output FULL;
output [7:0] Q0;
output [7:0] Q1;
output [7:0] Q2;
output [7:0] Q3;
output [7:0] Q4;
output [7:0] Q5;
output [7:0] Q6;
output [7:0] Q7;
output [7:0] Q8;
output [7:0] Q9;
input RDCLK;
input RDEN;
input RESET;
input WRCLK;
input WREN;
input [3:0] D0;
input [3:0] D1;
input [3:0] D2;
input [3:0] D3;
input [3:0] D4;
input [3:0] D7;
input [3:0] D8;
input [3:0] D9;
input [7:0] D5;
input [7:0] D6;
reg [0:0] ARRAY_MODE_BINARY;
reg [0:0] SLOW_RD_CLK_BINARY;
reg [0:0] SLOW_WR_CLK_BINARY;
reg [0:0] SYNCHRONOUS_MODE_BINARY;
reg [3:0] SPARE_BINARY;
reg [7:0] ALMOST_EMPTY_VALUE_BINARY;
reg [7:0] ALMOST_FULL_VALUE_BINARY;
tri0 GSR = glbl.GSR;
`ifdef XIL_TIMING
reg notifier;
`endif
initial begin
case (ALMOST_EMPTY_VALUE)
1 : ALMOST_EMPTY_VALUE_BINARY <= 8'b01000001;
2 : ALMOST_EMPTY_VALUE_BINARY <= 8'b01100011;
default : begin
$display("Attribute Syntax Error : The Attribute ALMOST_EMPTY_VALUE on %s instance %m is set to %d. Legal values for this attribute are 1 to 2.", MODULE_NAME, ALMOST_EMPTY_VALUE);
#1 $finish;
end
endcase
case (ALMOST_FULL_VALUE)
1 : ALMOST_FULL_VALUE_BINARY <= 8'b01000001;
2 : ALMOST_FULL_VALUE_BINARY <= 8'b01100011;
default : begin
$display("Attribute Syntax Error : The Attribute ALMOST_FULL_VALUE on %s instance %m is set to %d. Legal values for this attribute are 1 to 2.", MODULE_NAME, ALMOST_FULL_VALUE);
#1 $finish;
end
endcase
case (ARRAY_MODE)
"ARRAY_MODE_4_X_8" : ARRAY_MODE_BINARY <= 1'b1;
"ARRAY_MODE_4_X_4" : ARRAY_MODE_BINARY <= 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute ARRAY_MODE on %s instance %m is set to %s. Legal values for this attribute are ARRAY_MODE_4_X_8 or ARRAY_MODE_4_X_4.", MODULE_NAME, ARRAY_MODE);
#1 $finish;
end
endcase
SLOW_RD_CLK_BINARY <= 1'b0;
SLOW_WR_CLK_BINARY <= 1'b0;
SPARE_BINARY <= 4'b0;
case (SYNCHRONOUS_MODE)
"FALSE" : SYNCHRONOUS_MODE_BINARY <= 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute SYNCHRONOUS_MODE on %s instance %m is set to %s. The legal value for this attribute is FALSE.", MODULE_NAME, SYNCHRONOUS_MODE);
#1 $finish;
end
endcase
end
wire [7:0] delay_Q0;
wire [7:0] delay_Q1;
wire [7:0] delay_Q2;
wire [7:0] delay_Q3;
wire [7:0] delay_Q4;
wire [7:0] delay_Q5;
wire [7:0] delay_Q6;
wire [7:0] delay_Q7;
wire [7:0] delay_Q8;
wire [7:0] delay_Q9;
wire delay_ALMOSTEMPTY;
wire delay_ALMOSTFULL;
wire delay_EMPTY;
wire delay_FULL;
wire [3:0] delay_SCANOUT;
wire [3:0] delay_D0;
wire [3:0] delay_D1;
wire [3:0] delay_D2;
wire [3:0] delay_D3;
wire [3:0] delay_D4;
wire [3:0] delay_D7;
wire [3:0] delay_D8;
wire [3:0] delay_D9;
wire [7:0] delay_D5;
wire [7:0] delay_D6;
wire delay_RDCLK;
wire delay_RDEN;
wire delay_RESET;
wire delay_SCANENB = 1'b1;
wire delay_TESTMODEB = 1'b1;
wire delay_TESTREADDISB = 1'b1;
wire delay_TESTWRITEDISB = 1'b1;
wire [3:0] delay_SCANIN = 4'hf;
wire delay_WRCLK;
wire delay_WREN;
wire delay_GSR;
assign #(out_delay) ALMOSTEMPTY = delay_ALMOSTEMPTY;
assign #(out_delay) ALMOSTFULL = delay_ALMOSTFULL;
assign #(out_delay) EMPTY = delay_EMPTY;
assign #(out_delay) FULL = delay_FULL;
assign #(out_delay) Q0 = delay_Q0;
assign #(out_delay) Q1 = delay_Q1;
assign #(out_delay) Q2 = delay_Q2;
assign #(out_delay) Q3 = delay_Q3;
assign #(out_delay) Q4 = delay_Q4;
assign #(out_delay) Q5 = delay_Q5;
assign #(out_delay) Q6 = delay_Q6;
assign #(out_delay) Q7 = delay_Q7;
assign #(out_delay) Q8 = delay_Q8;
assign #(out_delay) Q9 = delay_Q9;
`ifndef XIL_TIMING
assign #(INCLK_DELAY) delay_RDCLK = RDCLK;
assign #(INCLK_DELAY) delay_WRCLK = WRCLK;
assign #(in_delay) delay_D0 = D0;
assign #(in_delay) delay_D1 = D1;
assign #(in_delay) delay_D2 = D2;
assign #(in_delay) delay_D3 = D3;
assign #(in_delay) delay_D4 = D4;
assign #(in_delay) delay_D5 = D5;
assign #(in_delay) delay_D6 = D6;
assign #(in_delay) delay_D7 = D7;
assign #(in_delay) delay_D8 = D8;
assign #(in_delay) delay_D9 = D9;
assign #(in_delay) delay_RDEN = RDEN;
`endif
assign #(in_delay) delay_RESET = RESET;
`ifndef XIL_TIMING
assign #(in_delay) delay_WREN = WREN;
`endif
assign delay_GSR = GSR;
SIP_IN_FIFO IN_FIFO_INST
(
.ALMOST_EMPTY_VALUE (ALMOST_EMPTY_VALUE_BINARY),
.ALMOST_FULL_VALUE (ALMOST_FULL_VALUE_BINARY),
.ARRAY_MODE (ARRAY_MODE_BINARY),
.SLOW_RD_CLK (SLOW_RD_CLK_BINARY),
.SLOW_WR_CLK (SLOW_WR_CLK_BINARY),
.SPARE (SPARE_BINARY),
.SYNCHRONOUS_MODE (SYNCHRONOUS_MODE_BINARY),
.ALMOSTEMPTY (delay_ALMOSTEMPTY),
.ALMOSTFULL (delay_ALMOSTFULL),
.EMPTY (delay_EMPTY),
.FULL (delay_FULL),
.Q0 (delay_Q0),
.Q1 (delay_Q1),
.Q2 (delay_Q2),
.Q3 (delay_Q3),
.Q4 (delay_Q4),
.Q5 (delay_Q5),
.Q6 (delay_Q6),
.Q7 (delay_Q7),
.Q8 (delay_Q8),
.Q9 (delay_Q9),
.SCANOUT (delay_SCANOUT),
.D0 (delay_D0),
.D1 (delay_D1),
.D2 (delay_D2),
.D3 (delay_D3),
.D4 (delay_D4),
.D5 (delay_D5),
.D6 (delay_D6),
.D7 (delay_D7),
.D8 (delay_D8),
.D9 (delay_D9),
.RDCLK (delay_RDCLK),
.RDEN (delay_RDEN),
.RESET (delay_RESET),
.SCANENB (delay_SCANENB),
.SCANIN (delay_SCANIN),
.TESTMODEB (delay_TESTMODEB),
.TESTREADDISB (delay_TESTREADDISB),
.TESTWRITEDISB (delay_TESTWRITEDISB),
.WRCLK (delay_WRCLK),
.WREN (delay_WREN),
.GSR (delay_GSR)
);
`ifdef XIL_TIMING
specify
$period (negedge RDCLK, 0:0:0, notifier);
$period (negedge WRCLK, 0:0:0, notifier);
$period (posedge RDCLK, 0:0:0, notifier);
$period (posedge WRCLK, 0:0:0, notifier);
$setuphold (posedge RDCLK, negedge RDEN, 0:0:0, 0:0:0, notifier,,, delay_RDCLK, delay_RDEN);
$setuphold (posedge RDCLK, posedge RDEN, 0:0:0, 0:0:0, notifier,,, delay_RDCLK, delay_RDEN);
$setuphold (posedge WRCLK, negedge D0, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D0);
$setuphold (posedge WRCLK, negedge D1, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D1);
$setuphold (posedge WRCLK, negedge D2, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D2);
$setuphold (posedge WRCLK, negedge D3, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D3);
$setuphold (posedge WRCLK, negedge D4, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D4);
$setuphold (posedge WRCLK, negedge D5, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D5);
$setuphold (posedge WRCLK, negedge D6, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D6);
$setuphold (posedge WRCLK, negedge D7, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D7);
$setuphold (posedge WRCLK, negedge D8, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D8);
$setuphold (posedge WRCLK, negedge D9, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D9);
$setuphold (posedge WRCLK, negedge WREN, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_WREN);
$setuphold (posedge WRCLK, posedge D0, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D0);
$setuphold (posedge WRCLK, posedge D1, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D1);
$setuphold (posedge WRCLK, posedge D2, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D2);
$setuphold (posedge WRCLK, posedge D3, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D3);
$setuphold (posedge WRCLK, posedge D4, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D4);
$setuphold (posedge WRCLK, posedge D5, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D5);
$setuphold (posedge WRCLK, posedge D6, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D6);
$setuphold (posedge WRCLK, posedge D7, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D7);
$setuphold (posedge WRCLK, posedge D8, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D8);
$setuphold (posedge WRCLK, posedge D9, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D9);
$setuphold (posedge WRCLK, posedge WREN, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_WREN);
$width (negedge RDCLK, 0:0:0, 0, notifier);
$width (negedge WRCLK, 0:0:0, 0, notifier);
$width (negedge RESET, 0:0:0, 0, notifier);
$width (posedge RDCLK, 0:0:0, 0, notifier);
$width (posedge RESET, 0:0:0, 0, notifier);
$width (posedge WRCLK, 0:0:0, 0, notifier);
( RDCLK *> ALMOSTEMPTY) = (10:10:10, 10:10:10);
( RDCLK *> EMPTY) = (10:10:10, 10:10:10);
( RDCLK *> Q0) = (10:10:10, 10:10:10);
( RDCLK *> Q1) = (10:10:10, 10:10:10);
( RDCLK *> Q2) = (10:10:10, 10:10:10);
( RDCLK *> Q3) = (10:10:10, 10:10:10);
( RDCLK *> Q4) = (10:10:10, 10:10:10);
( RDCLK *> Q5) = (10:10:10, 10:10:10);
( RDCLK *> Q6) = (10:10:10, 10:10:10);
( RDCLK *> Q7) = (10:10:10, 10:10:10);
( RDCLK *> Q8) = (10:10:10, 10:10:10);
( RDCLK *> Q9) = (10:10:10, 10:10:10);
( WRCLK *> ALMOSTFULL) = (10:10:10, 10:10:10);
( WRCLK *> FULL) = (10:10:10, 10:10:10);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule // IN_FIFO
`endcelldefine
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR4B_PP_SYMBOL_V
`define SKY130_FD_SC_LS__OR4B_PP_SYMBOL_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__or4b (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D_N ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR4B_PP_SYMBOL_V
|
(** * Hoare: Hoare Logic, Part I *)
Require Export Imp.
(** In the past couple of chapters, we've begun applying the
mathematical tools developed in the first part of the course to
studying the theory of a small programming language, Imp.
- We defined a type of _abstract syntax trees_ for Imp, together
with an _evaluation relation_ (a partial function on states)
that specifies the _operational semantics_ of programs.
The language we defined, though small, captures some of the key
features of full-blown languages like C, C++, and Java,
including the fundamental notion of mutable state and some
common control structures.
- We proved a number of _metatheoretic properties_ -- "meta" in
the sense that they are properties of the language as a whole,
rather than properties of particular programs in the language.
These included:
- determinism of evaluation
- equivalence of some different ways of writing down the
definitions (e.g. functional and relational definitions of
arithmetic expression evaluation)
- guaranteed termination of certain classes of programs
- correctness (in the sense of preserving meaning) of a number
of useful program transformations
- behavioral equivalence of programs (in the [Equiv] chapter).
If we stopped here, we would already have something useful: a set
of tools for defining and discussing programming languages and
language features that are mathematically precise, flexible, and
easy to work with, applied to a set of key properties. All of
these properties are things that language designers, compiler
writers, and users might care about knowing. Indeed, many of them
are so fundamental to our understanding of the programming
languages we deal with that we might not consciously recognize
them as "theorems." But properties that seem intuitively obvious
can sometimes be quite subtle (in some cases, even subtly wrong!).
We'll return to the theme of metatheoretic properties of whole
languages later in the course when we discuss _types_ and _type
soundness_. In this chapter, though, we'll turn to a different
set of issues.
Our goal is to see how to carry out some simple examples of
_program verification_ -- i.e., using the precise definition of
Imp to prove formally that particular programs satisfy particular
specifications of their behavior. We'll develop a reasoning system
called _Floyd-Hoare Logic_ -- often shortened to just _Hoare
Logic_ -- in which each of the syntactic constructs of Imp is
equipped with a single, generic "proof rule" that can be used to
reason compositionally about the correctness of programs involving
this construct.
Hoare Logic originates in the 1960s, and it continues to be the
subject of intensive research right up to the present day. It
lies at the core of a multitude of tools that are being used in
academia and industry to specify and verify real software
systems. *)
(* ####################################################### *)
(** * Hoare Logic *)
(** Hoare Logic combines two beautiful ideas: a natural way of
writing down _specifications_ of programs, and a _compositional
proof technique_ for proving that programs are correct with
respect to such specifications -- where by "compositional" we mean
that the structure of proofs directly mirrors the structure of the
programs that they are about. *)
(* ####################################################### *)
(** ** Assertions *)
(** To talk about specifications of programs, the first thing we
need is a way of making _assertions_ about properties that hold at
particular points during a program's execution -- i.e., claims
about the current state of the memory when program execution
reaches that point. Formally, an assertion is just a family of
propositions indexed by a [state]. *)
Definition Assertion := state -> Prop.
(** **** Exercise: 1 star, optional (assertions) *)
Module ExAssertions.
(** Paraphrase the following assertions in English. *)
Definition as1 : Assertion := fun st => st X = 3.
Definition as2 : Assertion := fun st => st X <= st Y.
Definition as3 : Assertion :=
fun st => st X = 3 \/ st X <= st Y.
Definition as4 : Assertion :=
fun st => st Z * st Z <= st X /\
~ (((S (st Z)) * (S (st Z))) <= st X).
Definition as5 : Assertion := fun st => True.
Definition as6 : Assertion := fun st => False.
(* FILL IN HERE *)
End ExAssertions.
(** [] *)
(** This way of writing assertions can be a little bit heavy,
for two reasons: (1) every single assertion that we ever write is
going to begin with [fun st => ]; and (2) this state [st] is the
only one that we ever use to look up variables (we will never need
to talk about two different memory states at the same time). For
discussing examples informally, we'll adopt some simplifying
conventions: we'll drop the initial [fun st =>], and we'll write
just [X] to mean [st X]. Thus, instead of writing *)
(**
fun st => (st Z) * (st Z) <= m /\
~ ((S (st Z)) * (S (st Z)) <= m)
we'll write just
Z * Z <= m /\ ~((S Z) * (S Z) <= m).
*)
(** Given two assertions [P] and [Q], we say that [P] _implies_ [Q],
written [P ->> Q] (in ASCII, [P -][>][> Q]), if, whenever [P]
holds in some state [st], [Q] also holds. *)
Definition assert_implies (P Q : Assertion) : Prop :=
forall st, P st -> Q st.
Notation "P ->> Q" :=
(assert_implies P Q) (at level 80) : hoare_spec_scope.
Open Scope hoare_spec_scope.
(** We'll also have occasion to use the "iff" variant of implication
between assertions: *)
Notation "P <<->> Q" :=
(P ->> Q /\ Q ->> P) (at level 80) : hoare_spec_scope.
(* ####################################################### *)
(** ** Hoare Triples *)
(** Next, we need a way of making formal claims about the
behavior of commands. *)
(** Since the behavior of a command is to transform one state to
another, it is natural to express claims about commands in terms
of assertions that are true before and after the command executes:
- "If command [c] is started in a state satisfying assertion
[P], and if [c] eventually terminates in some final state,
then this final state will satisfy the assertion [Q]."
Such a claim is called a _Hoare Triple_. The property [P] is
called the _precondition_ of [c], while [Q] is the
_postcondition_. Formally: *)
Definition hoare_triple
(P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st',
c / st || st' ->
P st ->
Q st'.
(** Since we'll be working a lot with Hoare triples, it's useful to
have a compact notation:
{{P}} c {{Q}}.
*)
(** (The traditional notation is [{P} c {Q}], but single braces
are already used for other things in Coq.) *)
Notation "{{ P }} c {{ Q }}" :=
(hoare_triple P c Q) (at level 90, c at next level)
: hoare_spec_scope.
(** (The [hoare_spec_scope] annotation here tells Coq that this
notation is not global but is intended to be used in particular
contexts. The [Open Scope] tells Coq that this file is one such
context.) *)
(** **** Exercise: 1 star, optional (triples) *)
(** Paraphrase the following Hoare triples in English.
1) {{True}} c {{X = 5}}
2) {{X = m}} c {{X = m + 5)}}
3) {{X <= Y}} c {{Y <= X}}
4) {{True}} c {{False}}
5) {{X = m}}
c
{{Y = real_fact m}}.
6) {{True}}
c
{{(Z * Z) <= m /\ ~ (((S Z) * (S Z)) <= m)}}
*)
(** [] *)
(** **** Exercise: 1 star, optional (valid_triples) *)
(** Which of the following Hoare triples are _valid_ -- i.e., the
claimed relation between [P], [c], and [Q] is true?
1) {{True}} X ::= 5 {{X = 5}}
2) {{X = 2}} X ::= X + 1 {{X = 3}}
3) {{True}} X ::= 5; Y ::= 0 {{X = 5}}
4) {{X = 2 /\ X = 3}} X ::= 5 {{X = 0}}
5) {{True}} SKIP {{False}}
6) {{False}} SKIP {{True}}
7) {{True}} WHILE True DO SKIP END {{False}}
8) {{X = 0}}
WHILE X == 0 DO X ::= X + 1 END
{{X = 1}}
9) {{X = 1}}
WHILE X <> 0 DO X ::= X + 1 END
{{X = 100}}
*)
(* FILL IN HERE *)
(** [] *)
(** (Note that we're using informal mathematical notations for
expressions inside of commands, for readability, rather than their
formal [aexp] and [bexp] encodings. We'll continue doing so
throughout the chapter.) *)
(** To get us warmed up for what's coming, here are two simple
facts about Hoare triples. *)
Theorem hoare_post_true : forall (P Q : Assertion) c,
(forall st, Q st) ->
{{P}} c {{Q}}.
Proof.
intros P Q c H. unfold hoare_triple.
intros st st' Heval HP.
apply H. Qed.
Theorem hoare_pre_false : forall (P Q : Assertion) c,
(forall st, ~(P st)) ->
{{P}} c {{Q}}.
Proof.
intros P Q c H. unfold hoare_triple.
intros st st' Heval HP.
unfold not in H. apply H in HP.
inversion HP. Qed.
(* ####################################################### *)
(** ** Proof Rules *)
(** The goal of Hoare logic is to provide a _compositional_
method for proving the validity of Hoare triples. That is, the
structure of a program's correctness proof should mirror the
structure of the program itself. To this end, in the sections
below, we'll introduce one rule for reasoning about each of the
different syntactic forms of commands in Imp -- one for
assignment, one for sequencing, one for conditionals, etc. -- plus
a couple of "structural" rules that are useful for gluing things
together. We will prove programs correct using these proof rules,
without ever unfolding the definition of [hoare_triple]. *)
(* ####################################################### *)
(** *** Assignment *)
(** The rule for assignment is the most fundamental of the Hoare logic
proof rules. Here's how it works.
Consider this (valid) Hoare triple:
{{ Y = 1 }} X ::= Y {{ X = 1 }}
In English: if we start out in a state where the value of [Y]
is [1] and we assign [Y] to [X], then we'll finish in a
state where [X] is [1]. That is, the property of being equal
to [1] gets transferred from [Y] to [X].
Similarly, in
{{ Y + Z = 1 }} X ::= Y + Z {{ X = 1 }}
the same property (being equal to one) gets transferred to
[X] from the expression [Y + Z] on the right-hand side of
the assignment.
More generally, if [a] is _any_ arithmetic expression, then
{{ a = 1 }} X ::= a {{ X = 1 }}
is a valid Hoare triple.
This can be made even more general. To conclude that an
_arbitrary_ property [Q] holds after [X ::= a], we need to assume
that [Q] holds before [X ::= a], but _with all occurrences of_ [X]
replaced by [a] in [Q]. This leads to the Hoare rule for
assignment
{{ Q [X |-> a] }} X ::= a {{ Q }}
where "[Q [X |-> a]]" is pronounced "[Q] where [a] is substituted
for [X]".
For example, these are valid applications of the assignment
rule:
{{ (X <= 5) [X |-> X + 1]
i.e., X + 1 <= 5 }}
X ::= X + 1
{{ X <= 5 }}
{{ (X = 3) [X |-> 3]
i.e., 3 = 3}}
X ::= 3
{{ X = 3 }}
{{ (0 <= X /\ X <= 5) [X |-> 3]
i.e., (0 <= 3 /\ 3 <= 5)}}
X ::= 3
{{ 0 <= X /\ X <= 5 }}
*)
(** To formalize the rule, we must first formalize the idea of
"substituting an expression for an Imp variable in an assertion."
That is, given a proposition [P], a variable [X], and an
arithmetic expression [a], we want to derive another proposition
[P'] that is just the same as [P] except that, wherever [P]
mentions [X], [P'] should instead mention [a].
Since [P] is an arbitrary Coq proposition, we can't directly
"edit" its text. Instead, we can achieve the effect we want by
evaluating [P] in an updated state: *)
Definition assn_sub X a P : Assertion :=
fun (st : state) =>
P (update st X (aeval st a)).
Notation "P [ X |-> a ]" := (assn_sub X a P) (at level 10).
(** That is, [P [X |-> a]] is an assertion [P'] that is just like [P]
except that, wherever [P] looks up the variable [X] in the current
state, [P'] instead uses the value of the expression [a].
To see how this works, let's calculate what happens with a couple
of examples. First, suppose [P'] is [(X <= 5) [X |-> 3]] -- that
is, more formally, [P'] is the Coq expression
fun st =>
(fun st' => st' X <= 5)
(update st X (aeval st (ANum 3))),
which simplifies to
fun st =>
(fun st' => st' X <= 5)
(update st X 3)
and further simplifies to
fun st =>
((update st X 3) X) <= 5)
and by further simplification to
fun st =>
(3 <= 5).
That is, [P'] is the assertion that [3] is less than or equal to
[5] (as expected).
For a more interesting example, suppose [P'] is [(X <= 5) [X |->
X+1]]. Formally, [P'] is the Coq expression
fun st =>
(fun st' => st' X <= 5)
(update st X (aeval st (APlus (AId X) (ANum 1)))),
which simplifies to
fun st =>
(((update st X (aeval st (APlus (AId X) (ANum 1))))) X) <= 5
and further simplifies to
fun st =>
(aeval st (APlus (AId X) (ANum 1))) <= 5.
That is, [P'] is the assertion that [X+1] is at most [5].
*)
(** Now we can give the precise proof rule for assignment:
------------------------------ (hoare_asgn)
{{Q [X |-> a]}} X ::= a {{Q}}
*)
(** We can prove formally that this rule is indeed valid. *)
Theorem hoare_asgn : forall Q X a,
{{Q [X |-> a]}} (X ::= a) {{Q}}.
Proof.
unfold hoare_triple.
intros Q X a st st' HE HQ.
inversion HE. subst.
unfold assn_sub in HQ. assumption. Qed.
(** Here's a first formal proof using this rule. *)
Example assn_sub_example :
{{(fun st => st X = 3) [X |-> ANum 3]}}
(X ::= (ANum 3))
{{fun st => st X = 3}}.
Proof.
apply hoare_asgn. Qed.
(** **** Exercise: 2 stars (hoare_asgn_examples) *)
(** Translate these informal Hoare triples...
1) {{ (X <= 5) [X |-> X + 1] }}
X ::= X + 1
{{ X <= 5 }}
2) {{ (0 <= X /\ X <= 5) [X |-> 3] }}
X ::= 3
{{ 0 <= X /\ X <= 5 }}
...into formal statements and use [hoare_asgn] to prove them. *)
Example hoare_incr_X :
{{(fun st => st X <= 5) [X |-> APlus (AId X) (ANum 1)]}}
(X ::= APlus (AId X) (ANum 1))
{{fun st => st X <= 5}}.
Proof.
apply hoare_asgn. Qed.
Example hoare_equal_wrong :
{{(fun st => 0 <= st X /\ st X <= 5) [X |-> (ANum 3)]}}
(X ::= ANum 3)
{{fun st => 0 <= st X /\ st X <= 5}}.
Proof.
apply hoare_asgn. Qed.
(** [] *)
(** **** Exercise: 2 stars (hoare_asgn_wrong) *)
(** The assignment rule looks backward to almost everyone the first
time they see it. If it still seems backward to you, it may help
to think a little about alternative "forward" rules. Here is a
seemingly natural one:
------------------------------ (hoare_asgn_wrong)
{{ True }} X ::= a {{ X = a }}
Give a counterexample showing that this rule is incorrect
(informally). Hint: The rule universally quantifies over the
arithmetic expression [a], and your counterexample needs to
exhibit an [a] for which the rule doesn't work. *)
(* a = APlus (AId X) (ANum 1) *)
Example hoare_assgn_wrong :
~({{ fun st => True }}
(X ::= APlus (AId X) (ANum 1))
{{fun st => st X = aeval st (APlus (AId X) (ANum 1))}}).
Proof.
unfold not. unfold hoare_triple. intros.
remember empty_state as st.
remember (update st X 1) as st'.
assert ((X ::= APlus (AId X) (ANum 1)) / st || st' ->
True -> st' X = aeval st' (APlus (AId X) (ANum 1))) by
(apply H).
assert (st' X = aeval st' (APlus (AId X) (ANum 1)) -> False).
intros. simpl in H1. destruct (st' X); omega.
assert ((X ::= APlus (AId X) (ANum 1)) / st || st').
rewrite Heqst'. simpl. apply E_Ass. simpl. rewrite Heqst. simpl. reflexivity.
apply H0 in H2. apply H1. assumption. trivial.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (hoare_asgn_fwd) *)
(** However, using an auxiliary variable [m] to remember the original
value of [X] we can define a Hoare rule for assignment that does,
intuitively, "work forwards" rather than backwards.
------------------------------------------ (hoare_asgn_fwd)
{{fun st => Q st /\ st X = m}}
X ::= a
{{fun st => Q st' /\ st X = aeval st' a }}
(where st' = update st X m)
Note that we use the original value of [X] to reconstruct the
state [st'] before the assignment took place. Prove that this rule
is correct (the first hypothesis is the functional extensionality
axiom, which you will need at some point). Also note that this
rule is more complicated than [hoare_asgn].
*)
Theorem hoare_asgn_fwd :
(forall {X Y: Type} {f g : X -> Y}, (forall (x: X), f x = g x) -> f = g) ->
forall m a Q,
{{fun st => Q st /\ st X = m}}
X ::= a
{{fun st => Q (update st X m) /\ st X = aeval (update st X m) a }}.
Proof.
intros functional_extensionality v a Q.
unfold hoare_triple.
intros. inversion H. subst. inversion H0.
split.
replace (update (update st X (aeval st a)) X v) with st. assumption.
apply functional_extensionality. intros. rewrite update_shadow. symmetry. apply update_same. assumption.
replace (update (update st X (aeval st a)) X v) with st. apply update_eq.
symmetry. apply functional_extensionality. intro.
assert ({X = x} + {X <> x}) by apply eq_id_dec. inversion H3. subst. rewrite update_eq. reflexivity.
rewrite update_shadow. apply update_neq. assumption.
Qed.
(** [] *)
(* ####################################################### *)
(** *** Consequence *)
(** Sometimes the preconditions and postconditions we get from the
Hoare rules won't quite be the ones we want in the particular
situation at hand -- they may be logically equivalent but have a
different syntactic form that fails to unify with the goal we are
trying to prove, or they actually may be logically weaker (for
preconditions) or stronger (for postconditions) than what we need.
For instance, while
{{(X = 3) [X |-> 3]}} X ::= 3 {{X = 3}},
follows directly from the assignment rule,
{{True}} X ::= 3 {{X = 3}}.
does not. This triple is valid, but it is not an instance of
[hoare_asgn] because [True] and [(X = 3) [X |-> 3]] are not
syntactically equal assertions. However, they are logically
equivalent, so if one triple is valid, then the other must
certainly be as well. We might capture this observation with the
following rule:
{{P'}} c {{Q}}
P <<->> P'
----------------------------- (hoare_consequence_pre_equiv)
{{P}} c {{Q}}
Taking this line of thought a bit further, we can see that
strengthening the precondition or weakening the postcondition of a
valid triple always produces another valid triple. This
observation is captured by two _Rules of Consequence_.
{{P'}} c {{Q}}
P ->> P'
----------------------------- (hoare_consequence_pre)
{{P}} c {{Q}}
{{P}} c {{Q'}}
Q' ->> Q
----------------------------- (hoare_consequence_post)
{{P}} c {{Q}}
*)
(** Here are the formal versions: *)
Theorem hoare_consequence_pre : forall (P P' Q : Assertion) c,
{{P'}} c {{Q}} ->
P ->> P' ->
{{P}} c {{Q}}.
Proof.
intros P P' Q c Hhoare Himp.
intros st st' Hc HP. apply (Hhoare st st').
assumption. apply Himp. assumption. Qed.
Theorem hoare_consequence_post : forall (P Q Q' : Assertion) c,
{{P}} c {{Q'}} ->
Q' ->> Q ->
{{P}} c {{Q}}.
Proof.
intros P Q Q' c Hhoare Himp.
intros st st' Hc HP.
apply Himp.
apply (Hhoare st st').
assumption. assumption. Qed.
(** For example, we might use the first consequence rule like this:
{{ True }} ->>
{{ 1 = 1 }}
X ::= 1
{{ X = 1 }}
Or, formally...
*)
Example hoare_asgn_example1 :
{{fun st => True}} (X ::= (ANum 1)) {{fun st => st X = 1}}.
Proof.
apply hoare_consequence_pre
with (P' := (fun st => st X = 1) [X |-> ANum 1]).
apply hoare_asgn.
intros st H. unfold assn_sub, update. simpl. reflexivity.
Qed.
(** Finally, for convenience in some proofs, we can state a "combined"
rule of consequence that allows us to vary both the precondition
and the postcondition.
{{P'}} c {{Q'}}
P ->> P'
Q' ->> Q
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
*)
Theorem hoare_consequence : forall (P P' Q Q' : Assertion) c,
{{P'}} c {{Q'}} ->
P ->> P' ->
Q' ->> Q ->
{{P}} c {{Q}}.
Proof.
intros P P' Q Q' c Hht HPP' HQ'Q.
apply hoare_consequence_pre with (P' := P').
apply hoare_consequence_post with (Q' := Q').
assumption. assumption. assumption. Qed.
(* ####################################################### *)
(** *** Digression: The [eapply] Tactic *)
(** This is a good moment to introduce another convenient feature of
Coq. We had to write "[with (P' := ...)]" explicitly in the proof
of [hoare_asgn_example1] and [hoare_consequence] above, to make
sure that all of the metavariables in the premises to the
[hoare_consequence_pre] rule would be set to specific
values. (Since [P'] doesn't appear in the conclusion of
[hoare_consequence_pre], the process of unifying the conclusion
with the current goal doesn't constrain [P'] to a specific
assertion.)
This is a little annoying, both because the assertion is a bit
long and also because for [hoare_asgn_example1] the very next
thing we are going to do -- applying the [hoare_asgn] rule -- will
tell us exactly what it should be! We can use [eapply] instead of
[apply] to tell Coq, essentially, "Be patient: The missing part is
going to be filled in soon." *)
Example hoare_asgn_example1' :
{{fun st => True}}
(X ::= (ANum 1))
{{fun st => st X = 1}}.
Proof.
eapply hoare_consequence_pre.
apply hoare_asgn.
intros st H. reflexivity. Qed.
(** In general, [eapply H] tactic works just like [apply H] except
that, instead of failing if unifying the goal with the conclusion
of [H] does not determine how to instantiate all of the variables
appearing in the premises of [H], [eapply H] will replace these
variables with so-called _existential variables_ (written [?nnn])
as placeholders for expressions that will be determined (by
further unification) later in the proof. *)
(** In order for [Qed] to succeed, all existential variables need to
be determined by the end of the proof. Otherwise Coq
will (rightly) refuse to accept the proof. Remember that the Coq
tactics build proof objects, and proof objects containing
existential variables are not complete. *)
Lemma silly1 : forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(forall x y : nat, P x y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. eapply HQ. apply HP.
(** Coq gives a warning after [apply HP]:
No more subgoals but non-instantiated existential variables:
Existential 1 =
?171 : [P : nat -> nat -> Prop
Q : nat -> Prop
HP : forall x y : nat, P x y
HQ : forall x y : nat, P x y -> Q x |- nat]
(dependent evars: ?171 open,)
You can use Grab Existential Variables.
Trying to finish the proof with [Qed] gives an error:
<<
Error: Attempt to save a proof with existential variables still
non-instantiated
>> *)
Abort.
(** An additional constraint is that existential variables cannot be
instantiated with terms containing (ordinary) variables that did
not exist at the time the existential variable was created. *)
Lemma silly2 :
forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. eapply HQ. destruct HP as [y HP'].
(** Doing [apply HP'] above fails with the following error:
Error: Impossible to unify "?175" with "y".
In this case there is an easy fix:
doing [destruct HP] _before_ doing [eapply HQ].
*)
Abort.
Lemma silly2_fixed :
forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. destruct HP as [y HP'].
eapply HQ. apply HP'.
Qed.
(** In the last step we did [apply HP'] which unifies the existential
variable in the goal with the variable [y]. The [assumption]
tactic doesn't work in this case, since it cannot handle
existential variables. However, Coq also provides an [eassumption]
tactic that solves the goal if one of the premises matches the
goal up to instantiations of existential variables. We can use
it instead of [apply HP']. *)
Lemma silly2_eassumption : forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. destruct HP as [y HP']. eapply HQ. eassumption.
Qed.
(** **** Exercise: 2 stars (hoare_asgn_examples_2) *)
(** Translate these informal Hoare triples...
{{ X + 1 <= 5 }} X ::= X + 1 {{ X <= 5 }}
{{ 0 <= 3 /\ 3 <= 5 }} X ::= 3 {{ 0 <= X /\ X <= 5 }}
...into formal statements and use [hoare_asgn] and
[hoare_consequence_pre] to prove them. *)
Definition hoare_asgn_examples_2a :=
{{(fun st => st X <= 5) [X |-> (APlus (AId X) (ANum 1))]}}
(X ::= APlus (AId X) (ANum 1))
{{fun st => st X <= 5}}.
Definition hoare_asgn_examples_2b :=
{{ (fun st => 0 <= st X /\ st X <= 5) [X |-> (ANum 3)] }}
(X ::= ANum 3)
{{ fun st => 0 <= st X /\ st X <= 5}}.
Example hoare_asgn_examples_2a_proof : hoare_asgn_examples_2a.
Proof.
unfold hoare_asgn_examples_2a.
apply hoare_asgn.
Qed.
Example hoare_asgn_examples_2b_proof : hoare_asgn_examples_2b.
Proof.
unfold hoare_asgn_examples_2b.
apply hoare_asgn.
Qed.
(* Is this correct? *)
(** [] *)
(* ####################################################### *)
(** *** Skip *)
(** Since [SKIP] doesn't change the state, it preserves any
property P:
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
*)
Theorem hoare_skip : forall P,
{{P}} SKIP {{P}}.
Proof.
intros P st st' H HP. inversion H. subst.
assumption. Qed.
(* ####################################################### *)
(** *** Sequencing *)
(** More interestingly, if the command [c1] takes any state where
[P] holds to a state where [Q] holds, and if [c2] takes any
state where [Q] holds to one where [R] holds, then doing [c1]
followed by [c2] will take any state where [P] holds to one
where [R] holds:
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;;c2 {{ R }}
*)
Theorem hoare_seq : forall P Q R c1 c2,
{{Q}} c2 {{R}} ->
{{P}} c1 {{Q}} ->
{{P}} c1;;c2 {{R}}.
Proof.
intros P Q R c1 c2 H1 H2 st st' H12 Pre.
inversion H12; subst.
apply (H1 st'0 st'); try assumption.
apply (H2 st st'0); assumption. Qed.
(** Note that, in the formal rule [hoare_seq], the premises are
given in "backwards" order ([c2] before [c1]). This matches the
natural flow of information in many of the situations where we'll
use the rule: the natural way to construct a Hoare-logic proof is
to begin at the end of the program (with the final postcondition)
and push postconditions backwards through commands until we reach
the beginning. *)
(** Informally, a nice way of recording a proof using the sequencing
rule is as a "decorated program" where the intermediate assertion
[Q] is written between [c1] and [c2]:
{{ a = n }}
X ::= a;;
{{ X = n }} <---- decoration for Q
SKIP
{{ X = n }}
*)
Example hoare_asgn_example3 : forall a n,
{{fun st => aeval st a = n}}
(X ::= a;; SKIP)
{{fun st => st X = n}}.
Proof.
intros a n. eapply hoare_seq.
Case "right part of seq".
apply hoare_skip.
Case "left part of seq".
eapply hoare_consequence_pre. apply hoare_asgn.
intros st H. subst. reflexivity. Qed.
(** You will most often use [hoare_seq] and
[hoare_consequence_pre] in conjunction with the [eapply] tactic,
as done above. *)
(** **** Exercise: 2 stars (hoare_asgn_example4) *)
(** Translate this "decorated program" into a formal proof:
{{ True }} ->>
{{ 1 = 1 }}
X ::= 1;;
{{ X = 1 }} ->>
{{ X = 1 /\ 2 = 2 }}
Y ::= 2
{{ X = 1 /\ Y = 2 }}
*)
Example hoare_asgn_example4 :
{{fun st => True}}
(X ::= (ANum 1);; Y ::= (ANum 2))
{{fun st => st X = 1 /\ st Y = 2}}.
Proof.
eapply hoare_seq. apply hoare_asgn.
eapply hoare_consequence_pre.
apply hoare_asgn.
intro. intro. simpl.
unfold assn_sub. split. simpl. apply update_neq. unfold not. intro. inversion H0.
simpl. apply update_eq.
Qed.
(** [] *)
(** **** Exercise: 3 stars (swap_exercise) *)
(** Write an Imp program [c] that swaps the values of [X] and [Y]
and show (in Coq) that it satisfies the following
specification:
{{X <= Y}} c {{Y <= X}}
*)
Definition swap_program : com :=
(Z ::= AId X ;; X ::= AId Y ;; Y ::= AId Z).
Theorem swap_swap_exercise : forall n m,
{{fun st => st X = n /\ st Y = m}}
swap_program
{{fun st => st X = m /\ st Y = n}}.
Proof.
unfold swap_program. intros.
eapply hoare_consequence_pre. eapply hoare_seq. eapply hoare_seq.
eapply hoare_asgn. eapply hoare_asgn. eapply hoare_asgn. intros st H.
unfold assn_sub. simpl. inversion H. subst. split.
rewrite update_neq. rewrite update_eq. apply update_neq. intro Ctra. inversion Ctra. intro Ctra. inversion Ctra.
rewrite update_eq. rewrite update_neq. rewrite update_eq. reflexivity. intro Ctra. inversion Ctra.
Qed.
(* How can I solve this using the previous theorem? *)
Theorem swap_exercise :
{{fun st => st X <= st Y}}
swap_program
{{fun st => st Y <= st X}}.
Proof.
unfold swap_program. intros.
eapply hoare_consequence_pre. eapply hoare_seq. eapply hoare_seq.
eapply hoare_asgn. eapply hoare_asgn. eapply hoare_asgn. intros st H.
unfold assn_sub. simpl.
rewrite update_eq. rewrite update_neq.
rewrite update_eq. rewrite update_neq. rewrite update_eq. rewrite update_neq. assumption.
intro Ctra. inversion Ctra.
intro Ctra. inversion Ctra.
intro Ctra. inversion Ctra.
Qed.
(** [] *)
(** **** Exercise: 3 stars (hoarestate1) *)
(** Explain why the following proposition can't be proven:
forall (a : aexp) (n : nat),
{{fun st => aeval st a = n}}
(X ::= (ANum 3);; Y ::= a)
{{fun st => st Y = n}}.
*)
(*
{{ a = n [X |-> (ANum 3)] [Y |-> a]}}
(X ::= (ANum 3);; Y ::= a)
{{ Y = n }}
cannot be proven because X might well be a part of a, whose value
will have changed afterthe first assignement.
*)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** *** Conditionals *)
(** What sort of rule do we want for reasoning about conditional
commands? Certainly, if the same assertion [Q] holds after
executing either branch, then it holds after the whole
conditional. So we might be tempted to write:
{{P}} c1 {{Q}}
{{P}} c2 {{Q}}
--------------------------------
{{P}} IFB b THEN c1 ELSE c2 {{Q}}
However, this is rather weak. For example, using this rule,
we cannot show that:
{{ True }}
IFB X == 0
THEN Y ::= 2
ELSE Y ::= X + 1
FI
{{ X <= Y }}
since the rule tells us nothing about the state in which the
assignments take place in the "then" and "else" branches. *)
(** But we can actually say something more precise. In the
"then" branch, we know that the boolean expression [b] evaluates to
[true], and in the "else" branch, we know it evaluates to [false].
Making this information available in the premises of the rule gives
us more information to work with when reasoning about the behavior
of [c1] and [c2] (i.e., the reasons why they establish the
postcondition [Q]). *)
(**
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
*)
(** To interpret this rule formally, we need to do a little work.
Strictly speaking, the assertion we've written, [P /\ b], is the
conjunction of an assertion and a boolean expression -- i.e., it
doesn't typecheck. To fix this, we need a way of formally
"lifting" any bexp [b] to an assertion. We'll write [bassn b] for
the assertion "the boolean expression [b] evaluates to [true] (in
the given state)." *)
Definition bassn b : Assertion :=
fun st => (beval st b = true).
(** A couple of useful facts about [bassn]: *)
Lemma bexp_eval_true : forall b st,
beval st b = true -> (bassn b) st.
Proof.
intros b st Hbe.
unfold bassn. assumption. Qed.
Lemma bexp_eval_false : forall b st,
beval st b = false -> ~ ((bassn b) st).
Proof.
intros b st Hbe contra.
unfold bassn in contra.
rewrite -> contra in Hbe. inversion Hbe. Qed.
(** Now we can formalize the Hoare proof rule for conditionals
and prove it correct. *)
Theorem hoare_if : forall P Q b c1 c2,
{{fun st => P st /\ bassn b st}} c1 {{Q}} ->
{{fun st => P st /\ ~(bassn b st)}} c2 {{Q}} ->
{{P}} (IFB b THEN c1 ELSE c2 FI) {{Q}}.
Proof.
intros P Q b c1 c2 HTrue HFalse st st' HE HP.
(* my version
inversion HE; subst.
Case "b true".
eapply HTrue. eassumption. split. assumption. unfold bassn. assumption.
Case "b false".
eapply HFalse. eassumption. split. assumption. unfold not. intro Contra.
unfold bassn in Contra. rewrite H4 in Contra. inversion Contra.
Qed.
*)
inversion HE; subst.
Case "b is true".
apply (HTrue st st').
assumption.
split. assumption.
apply bexp_eval_true. assumption.
Case "b is false".
apply (HFalse st st').
assumption.
split. assumption.
apply bexp_eval_false. assumption. Qed.
(** Here is a formal proof that the program we used to motivate the
rule satisfies the specification we gave. *)
Example if_example :
{{fun st => True}}
IFB (BEq (AId X) (ANum 0))
THEN (Y ::= (ANum 2))
ELSE (Y ::= APlus (AId X) (ANum 1))
FI
{{fun st => st X <= st Y}}.
Proof.
(* WORKED IN CLASS *)
apply hoare_if.
Case "Then".
eapply hoare_consequence_pre. apply hoare_asgn.
unfold bassn, assn_sub, update, assert_implies.
simpl. intros st [_ H].
apply beq_nat_true in H.
rewrite H. omega.
Case "Else".
eapply hoare_consequence_pre. apply hoare_asgn.
unfold assn_sub, update, assert_implies.
simpl; intros st _. omega.
Qed.
(** **** Exercise: 2 stars (if_minus_plus) *)
(** Prove the following hoare triple using [hoare_if]: *)
Theorem if_minus_plus :
{{fun st => True}}
IFB (BLe (AId X) (AId Y))
THEN (Z ::= AMinus (AId Y) (AId X))
ELSE (Y ::= APlus (AId X) (AId Z))
FI
{{fun st => st Y = st X + st Z}}.
Proof.
apply hoare_if.
Case "Then".
eapply hoare_consequence_pre. apply hoare_asgn.
unfold bassn, assn_sub, update, assert_implies.
intros st [_ H]. apply ble_nat_true in H. simpl in H. simpl. omega.
Case "Else".
eapply hoare_consequence_pre. apply hoare_asgn.
unfold bassn, assn_sub, update, assert_implies.
intros st _. simpl. reflexivity.
Qed.
(* ####################################################### *)
(** *** Exercise: One-sided conditionals *)
(** **** Exercise: 4 stars (if1_hoare) *)
(** In this exercise we consider extending Imp with "one-sided
conditionals" of the form [IF1 b THEN c FI]. Here [b] is a
boolean expression, and [c] is a command. If [b] evaluates to
[true], then command [c] is evaluated. If [b] evaluates to
[false], then [IF1 b THEN c FI] does nothing.
We recommend that you do this exercise before the ones that
follow, as it should help solidify your understanding of the
material. *)
(** The first step is to extend the syntax of commands and introduce
the usual notations. (We've done this for you. We use a separate
module to prevent polluting the global name space.) *)
Module If1.
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CIf1 : bexp -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "CIF1" ].
Notation "'SKIP'" :=
CSkip.
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "X '::=' a" :=
(CAss X a) (at level 60).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'IF1' b 'THEN' c 'FI'" :=
(CIf1 b c) (at level 80, right associativity).
(** Next we need to extend the evaluation relation to accommodate
[IF1] branches. This is for you to do... What rule(s) need to be
added to [ceval] to evaluate one-sided conditionals? *)
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st : state, SKIP / st || st
| E_Ass : forall (st : state) (a1 : aexp) (n : nat) (X : id),
aeval st a1 = n -> (X ::= a1) / st || update st X n
| E_Seq : forall (c1 c2 : com) (st st' st'' : state),
c1 / st || st' -> c2 / st' || st'' -> (c1 ;; c2) / st || st''
| E_IfTrue : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = true ->
c1 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = false ->
c2 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall (b1 : bexp) (st : state) (c1 : com),
beval st b1 = false -> (WHILE b1 DO c1 END) / st || st
| E_WhileLoop : forall (st st' st'' : state) (b1 : bexp) (c1 : com),
beval st b1 = true ->
c1 / st || st' ->
(WHILE b1 DO c1 END) / st' || st'' ->
(WHILE b1 DO c1 END) / st || st''
| E_If1True : forall (st st' : state) (b : bexp) (c : com),
beval st b = true ->
c / st || st' -> (IF1 b THEN c FI) / st || st'
| E_If1False : forall (st : state) (b : bexp) (c : com),
beval st b = false ->
(IF1 b THEN c FI) / st || st
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
| Case_aux c "E_If1True" | Case_aux c "E_If1False"
(* FILL IN HERE *)
].
(** Now we repeat (verbatim) the definition and notation of Hoare triples. *)
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st',
c / st || st' ->
P st ->
Q st'.
Notation "{{ P }} c {{ Q }}" := (hoare_triple P c Q)
(at level 90, c at next level)
: hoare_spec_scope.
(** Finally, we (i.e., you) need to state and prove a theorem,
[hoare_if1], that expresses an appropriate Hoare logic proof rule
for one-sided conditionals. Try to come up with a rule that is
both sound and as precise as possible. *)
Theorem hoare_if1 : forall P Q b c,
{{ fun st => P st /\ bassn b st}} c {{Q}} ->
{{ fun st => P st /\ ~(bassn b st)}} SKIP {{Q}} ->
{{P}} (IF1 b THEN c FI) {{Q}}.
Proof.
intros P Q b c HTrue HFalse.
unfold hoare_triple. intros st st' HIf1 HP. inversion HIf1. subst.
unfold hoare_triple in HTrue. eapply HTrue. eassumption. split. assumption. assumption.
subst. unfold hoare_triple in HFalse. eapply HFalse. eapply E_Skip. split. assumption. unfold bassn. unfold not. intro Contra.
rewrite H3 in Contra. inversion Contra.
Qed.
(** For full credit, prove formally that your rule is precise enough
to show the following valid Hoare triple:
{{ X + Y = Z }}
IF1 Y <> 0 THEN
X ::= X + Y
FI
{{ X = Z }}
*)
(** Hint: Your proof of this triple may need to use the other proof
rules also. Because we're working in a separate module, you'll
need to copy here the rules you find necessary. *)
Axiom functional_extensionality : forall {X Y: Type} {f g : X -> Y},
(forall (x: X), f x = g x) -> f = g.
(*
Theorem hoare_consequence_pre : forall (P P' Q : Assertion) c,
{{P'}} c {{Q}} ->
P ->> P' ->
{{P}} c {{Q}}.
Theorem hoare_consequence_post : forall (P Q Q' : Assertion) c,
{{P}} c {{Q'}} ->
Q' ->> Q ->
{{P}} c {{Q}}.
*)
Lemma hoare_if1_good :
{{ fun st => st X + st Y = st Z }}
IF1 BNot (BEq (AId Y) (ANum 0)) THEN
X ::= APlus (AId X) (AId Y)
FI
{{ fun st => st X = st Z }}.
Proof.
apply hoare_if1.
Case "b true".
unfold hoare_triple. intros st st' Hass [Heq Hb].
inversion Hass. subst. rewrite update_eq. rewrite update_neq. simpl. assumption.
unfold not. intro. inversion H.
Case "b false".
unfold hoare_triple. intros st st' HSkip [Heq Hb]. inversion HSkip. subst.
unfold bassn, not in Hb. simpl in Hb.
assert ({st' Y = 0} + {st' Y <> 0}) by (apply eq_nat_dec). inversion H. rewrite H0 in Heq. rewrite plus_0_r in Heq.
assumption. clear H. apply beq_nat_false_iff in H0. rewrite H0 in Hb. simpl in Hb. contradiction Hb. reflexivity.
Qed.
End If1.
(** [] *)
(* ####################################################### *)
(** *** Loops *)
(** Finally, we need a rule for reasoning about while loops. *)
(** Suppose we have a loop
WHILE b DO c END
and we want to find a pre-condition [P] and a post-condition
[Q] such that
{{P}} WHILE b DO c END {{Q}}
is a valid triple. *)
(** First of all, let's think about the case where [b] is false at the
beginning -- i.e., let's assume that the loop body never executes
at all. In this case, the loop behaves like [SKIP], so we might
be tempted to write
{{P}} WHILE b DO c END {{P}}.
But, as we remarked above for the conditional, we know a
little more at the end -- not just [P], but also the fact
that [b] is false in the current state. So we can enrich the
postcondition a little:
{{P}} WHILE b DO c END {{P /\ ~b}}
What about the case where the loop body _does_ get executed?
In order to ensure that [P] holds when the loop finally
exits, we certainly need to make sure that the command [c]
guarantees that [P] holds whenever [c] is finished.
Moreover, since [P] holds at the beginning of the first
execution of [c], and since each execution of [c]
re-establishes [P] when it finishes, we can always assume
that [P] holds at the beginning of [c]. This leads us to the
following rule:
{{P}} c {{P}}
-----------------------------------
{{P}} WHILE b DO c END {{P /\ ~b}}
This is almost the rule we want, but again it can be improved a
little: at the beginning of the loop body, we know not only that
[P] holds, but also that the guard [b] is true in the current
state. This gives us a little more information to use in
reasoning about [c] (showing that it establishes the invariant by
the time it finishes). This gives us the final version of the rule:
{{P /\ b}} c {{P}}
----------------------------------- (hoare_while)
{{P}} WHILE b DO c END {{P /\ ~b}}
The proposition [P] is called an _invariant_ of the loop.
One subtlety in the terminology is that calling some assertion [P]
a "loop invariant" doesn't just mean that it is preserved by the
body of the loop in question (i.e., [{{P}} c {{P}}], where [c] is
the loop body), but rather that [P] _together with the fact that
the loop's guard is true_ is a sufficient precondition for [c] to
ensure [P] as a postcondition.
This is a slightly (but significantly) weaker requirement. For
example, if [P] is the assertion [X = 0], then [P] _is_ an
invariant of the loop
WHILE X = 2 DO X := 1 END
although it is clearly _not_ preserved by the body of the
loop.
*)
Lemma hoare_while : forall P b c,
{{fun st => P st /\ bassn b st}} c {{P}} ->
{{P}} WHILE b DO c END {{fun st => P st /\ ~ (bassn b st)}}.
Proof.
intros P b c Hhoare st st' He HP.
(* Like we've seen before, we need to reason by induction
on He, because, in the "keep looping" case, its hypotheses
talk about the whole loop instead of just c *)
remember (WHILE b DO c END) as wcom eqn:Heqwcom.
ceval_cases (induction He) Case;
try (inversion Heqwcom); subst; clear Heqwcom.
Case "E_WhileEnd".
split. assumption. apply bexp_eval_false. assumption.
Case "E_WhileLoop".
apply IHHe2. reflexivity.
apply (Hhoare st st'). assumption.
split. assumption. apply bexp_eval_true. assumption.
Qed.
Example while_example :
{{fun st => st X <= 3}}
WHILE (BLe (AId X) (ANum 2))
DO X ::= APlus (AId X) (ANum 1) END
{{fun st => st X = 3}}.
Proof.
eapply hoare_consequence_post.
apply hoare_while.
eapply hoare_consequence_pre.
apply hoare_asgn.
unfold bassn, assn_sub, assert_implies, update. simpl.
intros st [H1 H2]. apply ble_nat_true in H2. omega.
unfold bassn, assert_implies. intros st [Hle Hb].
simpl in Hb. destruct (ble_nat (st X) 2) eqn : Heqle.
apply ex_falso_quodlibet. apply Hb; reflexivity.
apply ble_nat_false in Heqle. omega.
Qed.
(** We can use the while rule to prove the following Hoare triple,
which may seem surprising at first... *)
Theorem always_loop_hoare : forall P Q,
{{P}} WHILE BTrue DO SKIP END {{Q}}.
Proof.
(* WORKED IN CLASS *)
intros P Q.
apply hoare_consequence_pre with (P' := fun st : state => True).
eapply hoare_consequence_post.
apply hoare_while.
Case "Loop body preserves invariant".
apply hoare_post_true. intros st. apply I.
Case "Loop invariant and negated guard imply postcondition".
simpl. intros st [Hinv Hguard].
apply ex_falso_quodlibet. apply Hguard. reflexivity.
Case "Precondition implies invariant".
intros st H. constructor. Qed.
(** Of course, this result is not surprising if we remember that
the definition of [hoare_triple] asserts that the postcondition
must hold _only_ when the command terminates. If the command
doesn't terminate, we can prove anything we like about the
post-condition. *)
(** Hoare rules that only talk about terminating commands are
often said to describe a logic of "partial" correctness. It is
also possible to give Hoare rules for "total" correctness, which
build in the fact that the commands terminate. However, in this
course we will only talk about partial correctness. *)
(* ####################################################### *)
(** *** Exercise: [REPEAT] *)
Module RepeatExercise.
(** **** Exercise: 4 stars, advanced (hoare_repeat) *)
(** In this exercise, we'll add a new command to our language of
commands: [REPEAT] c [UNTIL] a [END]. You will write the
evaluation rule for [repeat] and add a new Hoare rule to
the language for programs involving it. *)
Inductive com : Type :=
| CSkip : com
| CAsgn : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CRepeat : com -> bexp -> com.
(** [REPEAT] behaves like [WHILE], except that the loop guard is
checked _after_ each execution of the body, with the loop
repeating as long as the guard stays _false_. Because of this,
the body will always execute at least once. *)
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE"
| Case_aux c "CRepeat" ].
Notation "'SKIP'" :=
CSkip.
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "X '::=' a" :=
(CAsgn X a) (at level 60).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'REPEAT' e1 'UNTIL' b2 'END'" :=
(CRepeat e1 b2) (at level 80, right associativity).
(** Add new rules for [REPEAT] to [ceval] below. You can use the rules
for [WHILE] as a guide, but remember that the body of a [REPEAT]
should always execute at least once, and that the loop ends when
the guard becomes true. Then update the [ceval_cases] tactic to
handle these added cases. *)
Inductive ceval : state -> com -> state -> Prop :=
| E_Skip : forall st,
ceval st SKIP st
| E_Ass : forall st a1 n X,
aeval st a1 = n ->
ceval st (X ::= a1) (update st X n)
| E_Seq : forall c1 c2 st st' st'',
ceval st c1 st' ->
ceval st' c2 st'' ->
ceval st (c1 ;; c2) st''
| E_IfTrue : forall st st' b1 c1 c2,
beval st b1 = true ->
ceval st c1 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_IfFalse : forall st st' b1 c1 c2,
beval st b1 = false ->
ceval st c2 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_WhileEnd : forall b1 st c1,
beval st b1 = false ->
ceval st (WHILE b1 DO c1 END) st
| E_WhileLoop : forall st st' st'' b1 c1,
beval st b1 = true ->
ceval st c1 st' ->
ceval st' (WHILE b1 DO c1 END) st'' ->
ceval st (WHILE b1 DO c1 END) st''
| E_RepeatEnd : forall b st st' c,
ceval st c st' ->
beval st' b = true ->
ceval st (REPEAT c UNTIL b END) st'
| E_RepeatLoop : forall b st st' st'' c,
ceval st c st' ->
beval st' b = false ->
ceval st' (REPEAT c UNTIL b END) st'' ->
ceval st (REPEAT c UNTIL b END) st''
.
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass"
| Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
| Case_aux c "E_RepeatEnd" | Case_aux c "E_RepeatLoop"
].
(** A couple of definitions from above, copied here so they use the
new [ceval]. *)
Notation "c1 '/' st '||' st'" := (ceval st c1 st')
(at level 40, st at level 39).
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion)
: Prop :=
forall st st', (c / st || st') -> P st -> Q st'.
Notation "{{ P }} c {{ Q }}" :=
(hoare_triple P c Q) (at level 90, c at next level).
(** To make sure you've got the evaluation rules for [REPEAT] right,
prove that [ex1_repeat evaluates correctly. *)
Definition ex1_repeat :=
REPEAT
X ::= ANum 1;;
Y ::= APlus (AId Y) (ANum 1)
UNTIL (BEq (AId X) (ANum 1)) END.
Theorem ex1_repeat_works :
ex1_repeat / empty_state ||
update (update empty_state X 1) Y 1.
Proof.
unfold ex1_repeat.
apply E_RepeatEnd. eapply E_Seq. apply E_Ass. simpl. reflexivity.
apply E_Ass. reflexivity. reflexivity.
Qed.
Theorem hoare_consequence_pre : forall (P P' Q : Assertion) c,
{{P'}} c {{Q}} ->
P ->> P' ->
{{P}} c {{Q}}.
Admitted.
Theorem hoare_consequence_post : forall (P Q Q' : Assertion) c,
{{P}} c {{Q'}} ->
Q' ->> Q ->
{{P}} c {{Q}}.
Admitted.
Theorem hoare_consequence : forall (P P' Q Q' : Assertion) c,
{{P'}} c {{Q'}} ->
P ->> P' ->
Q' ->> Q ->
{{P}} c {{Q}}.
Admitted.
Theorem hoare_seq : forall P Q R c1 c2,
{{Q}} c2 {{R}} ->
{{P}} c1 {{Q}} ->
{{P}} c1;;c2 {{R}}.
Admitted.
Theorem hoare_asgn : forall Q X a,
{{Q [X |-> a]}} (X ::= a) {{Q}}.
Admitted.
Theorem hoare_repeat : forall P Q b c,
{{P}} c {{Q}} ->
((fun st => Q st /\ ~(bassn b st)) ->> P) ->
{{P}} REPEAT c UNTIL b END {{fun st => Q st /\ (bassn b st)}}.
Proof.
intros P Q b c Hpre Hloop st st' Hrep HP.
remember (REPEAT c UNTIL b END) as rue eqn:Hrue.
ceval_cases (induction Hrep) Case;
try (inversion Hrue); subst.
Case "E_RepeatEnd".
split; try (apply (Hpre st st')); assumption.
Case "E_RepeatLoop".
apply IHHrep2. reflexivity.
apply Hloop. split. apply (Hpre st st'). assumption. assumption. unfold not, bassn. intro. rewrite H in H0. inversion H0.
Qed.
(** For full credit, make sure (informally) that your rule can be used
to prove the following valid Hoare triple:
{{ X > 0 }}
REPEAT
Y ::= X;;
X ::= X - 1
UNTIL X = 0 END
{{ X = 0 /\ Y > 0 }}
*)
Example hoare_repeat_test :
{{ fun st : state => st X > 0 }}
(REPEAT
Y ::= (AId X);;
X ::= (AMinus (AId X) (ANum 1))
UNTIL (BEq (AId X) (ANum 0)) END)
{{ fun st : state => st X = 0 /\ st Y > 0 }}.
Proof.
(*eapply hoare_consequence*)
eapply hoare_consequence_post.
eapply hoare_repeat with
(P:=fun st : state => st X > 0)
(Q:=fun st : state => st Y = st X + 1).
Case "{{P}} c {{Q}}".
eapply hoare_seq.
apply hoare_asgn.
eapply hoare_consequence_pre.
apply hoare_asgn.
unfold assert_implies, assn_sub, update. intros st Hgt. simpl. omega.
Case "{{Q /\ ~b}} ->> {{P}}".
intros st [Heq Hb]. unfold bassn in Hb. simpl in Hb. unfold not in Hb.
destruct (st X). simpl in Hb. contradiction Hb. reflexivity. omega.
Case "Postcond implies goal".
intros st [Heq Hb]. unfold bassn in Hb. simpl in Hb. apply beq_nat_true in Hb. omega.
Qed.
(*
Ich brauche eine Invariante, die von der Schleife erhalten wird
und am Ende mit Verbindung exit condition die gewünschte Gleichung
liefert.
Das Ganze wird dadurch erschwert, dass die Eingangsbedingung nicht
zu dieser invariante gehört. Was ich brauche ist die Aussage, dass
wenn die Endbedingung erfüllt ist die Schleife nicht nochmal durchläuft.
Wie könnte ich das über die Hoare Logik abbilden?
Das Problem, das ich dabei habe ist, ist dass der Schleifenbody immer
einmal angewendet wrid, auch wenn die exit condition zu diesem Zeitpunkt
schon true ist.
Wie kann ich das griffig formulieren?
Variante 1:
{{P}} c {{Q /\ ~b}} ->
{{Q /\ ~b }} c {{Q}} ->
{{P}} REPEAT c UNTIL b END {{Q /\ b}}
I haven't been able to prove this yet. I think it says the following:
- P is initially tranformed into Q by a single application of c.
- Q is the invariant that is maintained by c.
- The initial condition P is transformed into the invariant Q plus the
exit condition b.
Variante 2:
{{P /\ ~b}} c {{P}} ->
{{P /\ ~b}} REPEAT c UNTIL b END {{P /\ b}}.
The problem I see here is that '~b' is not necessarily true in the beginning.
It seems to strict
*)
End RepeatExercise.
(** [] *)
(* ####################################################### *)
(** ** Exercise: [HAVOC] *)
(** **** Exercise: 3 stars (himp_hoare) *)
(** In this exercise, we will derive proof rules for the [HAVOC] command
which we studied in the last chapter. First, we enclose this work
in a separate module, and recall the syntax and big-step semantics
of Himp commands. *)
Module Himp.
Inductive com : Type :=
| CSkip : com
| CAsgn : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CHavoc : id -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "HAVOC" ].
Notation "'SKIP'" :=
CSkip.
Notation "X '::=' a" :=
(CAsgn X a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'HAVOC' X" := (CHavoc X) (at level 60).
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st : state, SKIP / st || st
| E_Ass : forall (st : state) (a1 : aexp) (n : nat) (X : id),
aeval st a1 = n -> (X ::= a1) / st || update st X n
| E_Seq : forall (c1 c2 : com) (st st' st'' : state),
c1 / st || st' -> c2 / st' || st'' -> (c1 ;; c2) / st || st''
| E_IfTrue : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = true ->
c1 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = false ->
c2 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall (b1 : bexp) (st : state) (c1 : com),
beval st b1 = false -> (WHILE b1 DO c1 END) / st || st
| E_WhileLoop : forall (st st' st'' : state) (b1 : bexp) (c1 : com),
beval st b1 = true ->
c1 / st || st' ->
(WHILE b1 DO c1 END) / st' || st'' ->
(WHILE b1 DO c1 END) / st || st''
| E_Havoc : forall (st : state) (X : id) (n : nat),
(HAVOC X) / st || update st X n
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
| Case_aux c "E_Havoc" ].
(** The definition of Hoare triples is exactly as before. Unlike our
notion of program equivalence, which had subtle consequences with
occassionally nonterminating commands (exercise [havoc_diverge]),
this definition is still fully satisfactory. Convince yourself of
this before proceeding. *)
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st', c / st || st' -> P st -> Q st'.
Notation "{{ P }} c {{ Q }}" := (hoare_triple P c Q)
(at level 90, c at next level)
: hoare_spec_scope.
(** Complete the Hoare rule for [HAVOC] commands below by defining
[havoc_pre] and prove that the resulting rule is correct. *)
Definition havoc_pre (X : id) (Q : Assertion) : Assertion :=
fun st => forall n, Q [ X |-> (ANum n) ] st.
Theorem hoare_havoc : forall (Q : Assertion) (X : id),
{{ havoc_pre X Q }} HAVOC X {{ Q }}.
Proof.
intros Q X st st' Heval Hhav. unfold havoc_pre, assn_sub in Hhav. simpl in Hhav.
inversion Heval. subst. apply Hhav.
Qed.
End Himp.
(** [] *)
(* ####################################################### *)
(** ** Review *)
(** Above, we've introduced Hoare Logic as a tool to reasoning
about Imp programs. In the reminder of this chapter we will
explore a systematic way to use Hoare Logic to prove properties
about programs. The rules of Hoare Logic are the following: *)
(**
------------------------------ (hoare_asgn)
{{Q [X |-> a]}} X::=a {{Q}}
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;;c2 {{ R }}
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
{{P /\ b}} c {{P}}
----------------------------------- (hoare_while)
{{P}} WHILE b DO c END {{P /\ ~b}}
{{P'}} c {{Q'}}
P ->> P'
Q' ->> Q
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
In the next chapter, we'll see how these rules are used to prove
that programs satisfy specifications of their behavior.
*)
(* $Date: 2013-07-18 09:59:22 -0400 (Thu, 18 Jul 2013) $ *)
|
`timescale 1ns/1ps
/***************************************************************************
Name:
Date: 7/11/2016
Founction: pwm capture deal
Note:
****************************************************************************/
module pwm_capture(
pwm_input,clk,rst_n,enable,tx_start,tx_data,tx_complete,capture_tx_rst,bps_start_t
);
input pwm_input;
input clk;
input rst_n;
input enable;
input tx_complete;
input capture_tx_rst;
input bps_start_t;
output tx_start;
output[7:0] tx_data;
reg ready;
reg[31:0] counter;
reg[31:0] pos_counter;
reg[31:0] neg_counter;
reg[31:0] nextpos_counter;
reg[31:0] periodcounter;
reg[31:0] dutycyclecounter;
reg pos_counter_flag;
reg neg_counter_flag;
reg nextpos_counter_flag;
wire pos_btn;
wire neg_btn;
wire tx_end;
/*******************************************************************************
*counter
*********************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n) begin
counter <= 'h0;
end
else if(enable) begin
counter <= (counter < 32'hFFFFFFFF) ? (counter + 1'b1) : 'h0 ;
end
end
/*******************************************************************************
*Instance
*********************************************************************************/
neg_capture neg_capture_instance(
.pwm_input(pwm_input),
.clk(clk),
.rst_n(rst_n),
.enable(enable),
.neg_btn(neg_btn)
);
pos_capture pos_capture_instance(
.pwm_input(pwm_input),
.clk(clk),
.rst_n(rst_n),
.enable(enable),
.pos_btn(pos_btn)
);
captuer_tx captuer_tx_instance(
.clk(clk),
.rst_n(rst_n),
.tx_start(tx_start),
.capture_ready(ready),
.periodcounter(periodcounter),
.dutycyclecounter(dutycyclecounter),
.tx_data(tx_data),
.tx_complete(tx_complete),
.capture_tx_rst(capture_tx_rst),
.tx_end(tx_end),
.bps_start_t(bps_start_t)
);
/*******************************************************************************
*Capture pos counter value
*********************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
pos_counter <= 'h0;
pos_counter_flag <= 'h0;
end
else if(pos_btn && (pos_counter_flag != 1'b1))begin
pos_counter <= counter;
pos_counter_flag <= 1'b1;
end
end
/*******************************************************************************
*Capture neg counter value
*********************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
neg_counter <= 'h0;
neg_counter_flag <= 'h0;
end
else if(neg_btn && pos_counter_flag && (neg_counter_flag != 1'b1))begin
neg_counter <= counter;
neg_counter_flag <= 1'b1;
end
end
/*******************************************************************************
*Capture next pos counter value
*********************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
nextpos_counter <= 'h0;
nextpos_counter_flag <= 'h0;
end
else if(pos_btn && pos_counter_flag && neg_counter_flag && (nextpos_counter_flag != 1'b1))begin
nextpos_counter <= counter;
nextpos_counter_flag <= 1'b1;
end
end
/*******************************************************************************
*Calculate the dutycycle
*********************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
dutycyclecounter <= 'h0;
end
else if(neg_counter_flag && pos_counter_flag)begin
dutycyclecounter <= neg_counter - pos_counter;
end
end
/*******************************************************************************
*Calculate the period
*********************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
periodcounter <= 'h0;
ready <= 'h0;
end
else if(neg_counter_flag && pos_counter_flag && nextpos_counter_flag)begin
periodcounter <= nextpos_counter - pos_counter;
ready <=(tx_end) ? 'h0:'h1;
end
end
endmodule |
//altiobuf_out CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DEVICE_FAMILY="Cyclone V" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN1="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN2="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b
//VERSION_BEGIN 14.1 cbx_altiobuf_out 2015:01:07:18:05:53:SJ cbx_mgl 2015:01:07:18:10:28:SJ cbx_stratixiii 2015:01:07:18:05:54:SJ cbx_stratixv 2015:01:07:18:05:54:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus II License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = cyclonev_io_obuf 2 cyclonev_pseudo_diff_out 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module hps_sdram_p0_clock_pair_generator
(
datain,
dataout,
dataout_b) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obuf_ba_oe;
wire [0:0] wire_obufa_o;
wire [0:0] wire_obufa_oe;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pseudo_diffa_obar;
wire [0:0] wire_pseudo_diffa_oebout;
wire [0:0] wire_pseudo_diffa_oein;
wire [0:0] wire_pseudo_diffa_oeout;
wire [0:0] oe_w;
cyclonev_io_obuf obuf_ba_0
(
.i(wire_pseudo_diffa_obar),
.o(wire_obuf_ba_o[0:0]),
.obar(),
.oe(wire_obuf_ba_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obuf_ba_0.bus_hold = "false",
obuf_ba_0.open_drain_output = "false",
obuf_ba_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obuf_ba_oe = {(~ wire_pseudo_diffa_oebout[0])};
cyclonev_io_obuf obufa_0
(
.i(wire_pseudo_diffa_o),
.o(wire_obufa_o[0:0]),
.obar(),
.oe(wire_obufa_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_0.bus_hold = "false",
obufa_0.open_drain_output = "false",
obufa_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obufa_oe = {(~ wire_pseudo_diffa_oeout[0])};
cyclonev_pseudo_diff_out pseudo_diffa_0
(
.dtc(),
.dtcbar(),
.i(datain),
.o(wire_pseudo_diffa_o[0:0]),
.obar(wire_pseudo_diffa_obar[0:0]),
.oebout(wire_pseudo_diffa_oebout[0:0]),
.oein(wire_pseudo_diffa_oein[0:0]),
.oeout(wire_pseudo_diffa_oeout[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dtcin(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
assign
wire_pseudo_diffa_oein = {(~ oe_w[0])};
assign
dataout = wire_obufa_o,
dataout_b = wire_obuf_ba_o,
oe_w = 1'b1;
endmodule //hps_sdram_p0_clock_pair_generator
//VALID FILE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAPVPWRVGND_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__TAPVPWRVGND_PP_BLACKBOX_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__tapvpwrvgnd (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAPVPWRVGND_PP_BLACKBOX_V
|
/*******************************************************************************
* Module: select_clk_buf
* Date:2015-11-07
* Author: andrey
* Description: Select one of the clock buffers primitives by parameter
*
* Copyright (c) 2015 Elphel, Inc .
* select_clk_buf.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* select_clk_buf.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
`timescale 1ns/1ps
module select_clk_buf #(
parameter BUFFER_TYPE = "BUFR" // to use clr
)(
output o,
input i,
input clr // for BUFR_only
);
generate
if (BUFFER_TYPE == "BUFG") BUFG clk1x_i (.O(o), .I(i));
else if (BUFFER_TYPE == "BUFH") BUFH clk1x_i (.O(o), .I(i));
else if (BUFFER_TYPE == "BUFR") BUFR clk1x_i (.O(o), .I(i), .CE(1'b1), .CLR(clr));
else if (BUFFER_TYPE == "BUFMR") BUFMR clk1x_i (.O(o), .I(i));
else if (BUFFER_TYPE == "BUFIO") BUFIO clk1x_i (.O(o), .I(i));
else assign o = i;
endgenerate
endmodule
|
Require Export BisimRefinement.TraceMonad.
Require Export BisimRefinement.BisimPerm.
Require Export Coq.Arith.PeanoNat.
Require Export Coq.Lists.List.
(***
*** Machine Values
***)
(* Values in our simple machine are just nats *)
Inductive SMValue := | mkSMValue (n:nat).
(* The "undefined" value *)
(* Definition undefValue := mkSMValue 0. *)
(* Values are related by the built-in Coq intensional equality *)
Instance LR_SMValue : LR SMValue := LR_eq.
(* Test equality of values *)
Definition val_eqb (v1 v2 : SMValue) : bool :=
match v1, v2 with
mkSMValue n1, mkSMValue n2 => Nat.eqb n1 n2
end.
(* Test if a value is "true", represented here as not equal to 0 *)
Definition val_true (v: SMValue) : bool :=
match v with
mkSMValue n => negb (Nat.eqb n 0)
end.
(* The lens for viewing a value as a nat *)
Program Definition SMValue_nat_lens : Lens SMValue nat :=
{| getL v := match v with mkSMValue n => n end;
putL n v := mkSMValue n; |}.
Next Obligation.
intros [ n1 ] [ n2 ] eq_v. destruct eq_v. inversion H. reflexivity.
Defined.
Next Obligation.
intros n1 n2 [ eq_n eq_n' ] v1 v2 eq_v. rewrite eq_n. reflexivity.
Defined.
Next Obligation.
destruct a. reflexivity.
Defined.
Next Obligation.
reflexivity.
Defined.
Next Obligation.
reflexivity.
Defined.
(* A tuple of 0 or more values *)
Definition SMValues n := NTuple SMValue n.
Instance LR_SMValues n : LR (SMValues n) := Build_LR _ _ _.
(***
*** Register Sets
***)
(* A set of SSA register values *)
Definition SMRegs := list SMValue.
Instance LR_SMRegs : LR SMRegs := LR_eq.
(* Read a register value *)
Definition readReg (regs:SMRegs) n : option SMValue := nth_error regs n.
(* Push a new register value *)
Definition pushReg (regs:SMRegs) val : SMRegs := val :: regs.
(* Push a list of new register values *)
Fixpoint pushRegs (regs:SMRegs) n : SMValues n -> SMRegs :=
match n return SMValues n -> SMRegs with
| 0 => fun _ => regs
| S n' => fun vals => pushRegs (pushReg regs (fst vals)) n' (snd vals)
end.
(***
*** Data Memories
***)
(* A data memory = a map from "pointers" (represented by nats) to values (which
are also nats) *)
Inductive DataMem := mkDataMem (vmap: nat -> SMValue).
(* Data memories are related by extensional functional equivalence *)
Instance LR_DataMem : LR DataMem :=
{ lr_leq := fun dmem1 dmem2 =>
match dmem1, dmem2 with
| mkDataMem vmap1, mkDataMem vmap2 => vmap1 <lr= vmap2
end;
}.
Proof.
constructor.
- intros [ vmap ]; reflexivity.
- intros [ vmap1 ] [ vmap2 ] [ vmap3 ] R12 R23; etransitivity; eassumption.
Defined.
(* Read a pointer value *)
Definition readPtr (mem:DataMem) (ptr:SMValue) : SMValue :=
match mem, ptr with
| mkDataMem vmap, mkSMValue n => vmap n
end.
Instance Proper_readPtr : Proper (lr_leq ==> lr_leq ==> lr_leq) readPtr.
Proof.
intros [ vmap1 ] [ vmap2 ] R_vmap [ n1 ] [ n2 ] Rn. simpl in Rn.
rewrite Rn. apply R_vmap.
Qed.
Instance Proper_readPtr_equiv : Proper (lr_equiv ==> lr_equiv ==> lr_equiv) readPtr.
Proof.
intros mem1 mem2 [ Rmem Rmem' ] ptr1 ptr2 [ Rptr Rptr' ].
split; apply Proper_readPtr; assumption.
Qed.
(* Write a pointer value *)
Definition writePtr (mem:DataMem) ptr val : DataMem :=
match mem, ptr with
| mkDataMem vmap, mkSMValue n =>
mkDataMem (fun n' => if Nat.eqb n n' then val else vmap n')
end.
Instance Proper_writePtr :
Proper (lr_leq ==> lr_leq ==> lr_leq ==> lr_leq) writePtr.
Proof.
intros [ vmap1 ] [ vmap2 ] R_vmap [ ptr1 ] [ ptr2 ] Rptr
[ v1 ] [ v2 ] Rv. simpl in Rptr, Rv. rewrite Rptr. rewrite Rv.
intro n. destruct (Nat.eqb ptr2 n); try reflexivity; apply R_vmap.
Qed.
Instance Proper_writePtr_equiv :
Proper (lr_equiv ==> lr_equiv ==> lr_equiv ==> lr_equiv) writePtr.
Proof.
intros mem1 mem2 [ Rmem Rmem' ] ptr1 ptr2 [ Rptr Rptr' ] v1 v2 [ Rv Rv' ].
split; apply Proper_writePtr; assumption.
Qed.
(* readPtr and writePtr form a lens *)
Program Definition ptr_dmem_lens (ptr: SMValue) : Lens DataMem SMValue :=
{| getL mem := readPtr mem ptr;
putL val mem := writePtr mem ptr val; |}.
Next Obligation.
intros mem1 mem2 eq_mem. rewrite eq_mem. reflexivity.
Defined.
Next Obligation.
intros v1 v2 eq_v mem1 mem2 eq_mem. rewrite eq_mem. rewrite eq_v. reflexivity.
Defined.
Next Obligation.
destruct a as [ vmap ]. destruct ptr as [ ptr ].
split; intro n; case_eq (Nat.eqb ptr n); intro; try reflexivity.
- rewrite Nat.eqb_eq in H. rewrite H. reflexivity.
- rewrite Nat.eqb_eq in H. rewrite H. reflexivity.
Defined.
Next Obligation.
destruct a as [ vmap ]. destruct ptr as [ ptr ]. destruct b as [ v ].
simpl. rewrite (proj2 (Nat.eqb_eq _ _) eq_refl). reflexivity.
Defined.
Next Obligation.
destruct a as [ vmap ]. destruct ptr as [ ptr ].
destruct b1 as [ v1 ]. destruct b2 as [ v2 ].
split; intro n; case_eq (Nat.eqb ptr n); intro; reflexivity.
Defined.
(***
*** Machine Expressions
***)
(* A "machine expression" is any value you can build from the registers,
possibly with an error *)
Definition SMExpr := SMRegs -> option SMValue.
Instance LR_SMExpr : LR SMExpr := Build_LR _ _ _.
(* The expression that returns an undefined value *)
(* Definition undefSMExpr : SMExpr := fun _ => undefValue. *)
(* A tuple of expressions with a fixed size *)
Definition SMExprs (n:nat) := NTuple SMExpr n.
Instance LR_SMExprs n : LR (SMExprs n) := Build_LR _ _ _.
(***
*** Machine Instructions
***)
Inductive SMInstr : nat -> Type :=
(* Assign values to the next registers *)
| SMAssign n (exprs: SMExprs n) : SMInstr n
(* Read a value from memory into the next register *)
| SMRead (ptr: SMExpr) : SMInstr 1
(* Write a value to memory *)
| SMWrite (ptr val: SMExpr) : SMInstr 0
(* Call a function pointer; calls always have 1 return value *)
| SMCall (fptr: SMExpr) : SMInstr 1
(* If-then-else, where the SSA phi node with N variables is represented as
having the two bodies return N values *)
| SMIf n (expr: SMExpr) (body1 body2: SMBlock n) : SMInstr n
(* While loop, where the SSA phi node with N variables is represented as having
the body return N values and having N default return values for the case that no
iterations happen *)
| SMWhile n (expr: SMExpr) (init:SMExprs n) (body:SMBlock n) : SMInstr n
with
SMBlock : nat -> Type :=
(* Return n values as the result of the block *)
| SMReturn n (exprs: SMExprs n) : SMBlock n
(* Run an instruction with n return values, push them into the next registers,
and then execute the remainder of the block in that extended context *)
| SMLet n (inst: SMInstr n) m (rest: SMBlock m) : SMBlock m
.
(* FIXME: using Coq intensional equality here adds a dependency on functional
extensionality to express equality of SMExprs, which is not really
necessary. Instead, these relations should be defined inductively on
instructions on blocks, using LR_SMExprs where needed. *)
Instance LR_SMInstr n : LR (SMInstr n) := LR_eq.
Instance LR_SMBlock n : LR (SMBlock n) := LR_eq.
(***
*** Instruction Memories
***)
(* An instruction memory = a partial map from "pointers" (represented by nats)
to function bodies with 1 return value *)
Inductive InstMem : Type := mkInstMem (imap:nat -> option (SMBlock 1)).
(* Instruction memories are related by the built-in Coq intensional equality *)
(* FIXME HERE: this should be an extensional equality *)
Instance LR_InstMem : LR InstMem := LR_eq.
(* Read a function pointer to get a function body, defaulting to "return undef"
if the function pointer does not have a binding *)
Definition readFunPtr (mem:InstMem) (fptr:SMValue) : option (SMBlock 1) :=
match mem, fptr with
| mkInstMem imap, mkSMValue n => imap n
end.
(***
*** Machine States
***)
(* A machine state = registers and two types of memory *)
Definition SMState : Type := (SMRegs * (DataMem * InstMem)).
Instance LR_SMState : LR SMState := LR_product.
(* Lenses for the top-level components of SMState *)
Definition regs_lens : Lens SMState SMRegs := fst_lens _ _.
Definition dmem_lens : Lens SMState DataMem :=
compose_lens (snd_lens _ _) (fst_lens _ _).
Definition imem_lens : Lens SMState InstMem :=
compose_lens (snd_lens _ _) (snd_lens _ _).
(* The lens for a pointer into the DataMem of an SMState *)
Definition ptr_lens (ptr: SMValue) : Lens SMState SMValue :=
compose_lens dmem_lens (ptr_dmem_lens ptr).
(***
*** Machine Semantics
***)
(* The monad for executing simple machines *)
Definition SMMonad A `{LR A} := TraceM SMState A.
(* Evaluate an expression in a monad *)
Definition evalExpr (expr: SMExpr) : SMMonad SMValue :=
bindM getM (fun smst =>
match expr (getL regs_lens smst) with
| Some v => returnM v
| None => errorM
end).
(* Evaluate a tuple of expressions in a monad *)
Fixpoint evalExprs {n} : SMExprs n -> SMMonad (SMValues n) :=
match n return SMExprs n -> SMMonad (SMValues n) with
| 0 => fun _ => returnM tt
| S n' =>
fun exprs =>
bindM (evalExpr (fst exprs))
(fun v =>
bindM (evalExprs (snd exprs))
(fun vs => returnM (v, vs)))
end.
(* Evaluate a machine instruction in a monad, assuming a recursive helper
function to "tie the knot" when evaluating function pointers *)
Fixpoint evalInstr' (recEval: SMBlock 1 -> SMMonad (SMValues 1))
{n} (inst: SMInstr n) : SMMonad (SMValues n) :=
match inst with
| SMAssign n exprs =>
evalExprs exprs
| SMRead ptr_expr =>
bindM (evalExpr ptr_expr)
(fun ptr =>
bindM getM (fun smst =>
returnM (getL (ptr_lens ptr) smst, tt)))
| SMWrite ptr_expr val_expr =>
bindM (evalExpr ptr_expr)
(fun ptr =>
bindM (evalExpr val_expr)
(fun val =>
bindM getM
(fun smst =>
putM (putL (ptr_lens ptr) val smst))))
| SMCall fptr_expr =>
bindM (evalExpr fptr_expr)
(fun fptr =>
bindM getM
(fun smst =>
match readFunPtr (getL imem_lens smst) fptr with
| Some block => recEval block
| None => errorM
end))
| SMIf n expr body1 body2 =>
bindM (evalExpr expr)
(fun v =>
if val_true v then
evalBlock' recEval body1
else
evalBlock' recEval body2)
| SMWhile n expr init_exprs body =>
bindM (evalExprs init_exprs)
(fun init_vs =>
fixM (fun f prev_vs =>
bindM (evalExpr expr)
(fun v =>
if val_true v then
bindM (evalBlock' recEval body)
(fun new_vs =>
f new_vs)
else
returnM prev_vs))
init_vs)
end
with
evalBlock' (recEval: SMBlock 1 -> SMMonad (SMValues 1))
{n} (block: SMBlock n) : SMMonad (SMValues n) :=
match block with
| SMReturn n exprs =>
evalExprs exprs
| SMLet n inst m rest =>
bindM (evalInstr' recEval inst)
(fun vs =>
bindM getM
(fun smst =>
bindM (putM (modifyL regs_lens
(fun regs => pushRegs regs _ vs)
smst))
(fun _ => evalBlock' recEval rest)))
end.
(* Tie the knot for evalBlock on a function body (with 1 return value) *)
Definition evalFunBody : SMBlock 1 -> SMMonad (SMValues 1) :=
fixM (fun recEval body => evalBlock' recEval body).
(* Tie the knot for evalInstr *)
Definition evalInstr {n} (inst: SMInstr n) : SMMonad (SMValues n) :=
evalInstr' evalFunBody inst.
(* Tie the knot for evalBlock *)
Definition evalBlock {n} (block: SMBlock n) : SMMonad (SMValues n) :=
evalBlock' evalFunBody block.
(***
*** Simple Machine Permissions
***)
(* A state permission is a permission to read the state as some type A *)
Definition StPerm A `{LR A} : Type := BPerm SMState A.
(* A value permission is a permission to read a value-in-state as some type A *)
Definition ValPerm A `{LR A} : Type := BPerm (SMValue * SMState) A.
(* A permission for 0 or more values *)
Definition ValsPerm n A `{LR A} : Type := BPerm (SMValues n * SMState) A.
(* A permission to view a value as a natural number *)
Definition nat_perm : ValPerm nat :=
lens_bperm (compose_lens (fst_lens _ _) SMValue_nat_lens).
(* A permission to view a value as a pointer to a (non-cyclic) linked list *)
(* FIXME HERE: define this! *)
Definition linked_list_perm A `{LR A} (bperm: ValPerm A) : ValPerm (list A).
admit.
Admitted.
(***
*** Bisimulation Abstraction
***)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRDLXTP_SYMBOL_V
`define SKY130_FD_SC_LP__SRDLXTP_SYMBOL_V
/**
* srdlxtp: ????.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__srdlxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input SLEEP_B
);
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRDLXTP_SYMBOL_V
|
module butterfly3_32(
enable,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
i_8,
i_9,
i_10,
i_11,
i_12,
i_13,
i_14,
i_15,
i_16,
i_17,
i_18,
i_19,
i_20,
i_21,
i_22,
i_23,
i_24,
i_25,
i_26,
i_27,
i_28,
i_29,
i_30,
i_31,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7,
o_8,
o_9,
o_10,
o_11,
o_12,
o_13,
o_14,
o_15,
o_16,
o_17,
o_18,
o_19,
o_20,
o_21,
o_22,
o_23,
o_24,
o_25,
o_26,
o_27,
o_28,
o_29,
o_30,
o_31
);
// ****************************************************************
//
// INPUT / OUTPUT DECLARATION
//
// ****************************************************************
input enable;
input signed [27:0] i_0;
input signed [27:0] i_1;
input signed [27:0] i_2;
input signed [27:0] i_3;
input signed [27:0] i_4;
input signed [27:0] i_5;
input signed [27:0] i_6;
input signed [27:0] i_7;
input signed [27:0] i_8;
input signed [27:0] i_9;
input signed [27:0] i_10;
input signed [27:0] i_11;
input signed [27:0] i_12;
input signed [27:0] i_13;
input signed [27:0] i_14;
input signed [27:0] i_15;
input signed [27:0] i_16;
input signed [27:0] i_17;
input signed [27:0] i_18;
input signed [27:0] i_19;
input signed [27:0] i_20;
input signed [27:0] i_21;
input signed [27:0] i_22;
input signed [27:0] i_23;
input signed [27:0] i_24;
input signed [27:0] i_25;
input signed [27:0] i_26;
input signed [27:0] i_27;
input signed [27:0] i_28;
input signed [27:0] i_29;
input signed [27:0] i_30;
input signed [27:0] i_31;
output signed [27:0] o_0;
output signed [27:0] o_1;
output signed [27:0] o_2;
output signed [27:0] o_3;
output signed [27:0] o_4;
output signed [27:0] o_5;
output signed [27:0] o_6;
output signed [27:0] o_7;
output signed [27:0] o_8;
output signed [27:0] o_9;
output signed [27:0] o_10;
output signed [27:0] o_11;
output signed [27:0] o_12;
output signed [27:0] o_13;
output signed [27:0] o_14;
output signed [27:0] o_15;
output signed [27:0] o_16;
output signed [27:0] o_17;
output signed [27:0] o_18;
output signed [27:0] o_19;
output signed [27:0] o_20;
output signed [27:0] o_21;
output signed [27:0] o_22;
output signed [27:0] o_23;
output signed [27:0] o_24;
output signed [27:0] o_25;
output signed [27:0] o_26;
output signed [27:0] o_27;
output signed [27:0] o_28;
output signed [27:0] o_29;
output signed [27:0] o_30;
output signed [27:0] o_31;
// ****************************************************************
//
// WIRE DECLARATION
//
// ****************************************************************
wire signed [27:0] b_0;
wire signed [27:0] b_1;
wire signed [27:0] b_2;
wire signed [27:0] b_3;
wire signed [27:0] b_4;
wire signed [27:0] b_5;
wire signed [27:0] b_6;
wire signed [27:0] b_7;
wire signed [27:0] b_8;
wire signed [27:0] b_9;
wire signed [27:0] b_10;
wire signed [27:0] b_11;
wire signed [27:0] b_12;
wire signed [27:0] b_13;
wire signed [27:0] b_14;
wire signed [27:0] b_15;
wire signed [27:0] b_16;
wire signed [27:0] b_17;
wire signed [27:0] b_18;
wire signed [27:0] b_19;
wire signed [27:0] b_20;
wire signed [27:0] b_21;
wire signed [27:0] b_22;
wire signed [27:0] b_23;
wire signed [27:0] b_24;
wire signed [27:0] b_25;
wire signed [27:0] b_26;
wire signed [27:0] b_27;
wire signed [27:0] b_28;
wire signed [27:0] b_29;
wire signed [27:0] b_30;
wire signed [27:0] b_31;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign b_0=i_0+i_31;
assign b_1=i_1+i_30;
assign b_2=i_2+i_29;
assign b_3=i_3+i_28;
assign b_4=i_4+i_27;
assign b_5=i_5+i_26;
assign b_6=i_6+i_25;
assign b_7=i_7+i_24;
assign b_8=i_8+i_23;
assign b_9=i_9+i_22;
assign b_10=i_10+i_21;
assign b_11=i_11+i_20;
assign b_12=i_12+i_19;
assign b_13=i_13+i_18;
assign b_14=i_14+i_17;
assign b_15=i_15+i_16;
assign b_16=i_15-i_16;
assign b_17=i_14-i_17;
assign b_18=i_13-i_18;
assign b_19=i_12-i_19;
assign b_20=i_11-i_20;
assign b_21=i_10-i_21;
assign b_22=i_9-i_22;
assign b_23=i_8-i_23;
assign b_24=i_7-i_24;
assign b_25=i_6-i_25;
assign b_26=i_5-i_26;
assign b_27=i_4-i_27;
assign b_28=i_3-i_28;
assign b_29=i_2-i_29;
assign b_30=i_1-i_30;
assign b_31=i_0-i_31;
assign o_0=enable?b_0:i_0;
assign o_1=enable?b_1:i_1;
assign o_2=enable?b_2:i_2;
assign o_3=enable?b_3:i_3;
assign o_4=enable?b_4:i_4;
assign o_5=enable?b_5:i_5;
assign o_6=enable?b_6:i_6;
assign o_7=enable?b_7:i_7;
assign o_8=enable?b_8:i_8;
assign o_9=enable?b_9:i_9;
assign o_10=enable?b_10:i_10;
assign o_11=enable?b_11:i_11;
assign o_12=enable?b_12:i_12;
assign o_13=enable?b_13:i_13;
assign o_14=enable?b_14:i_14;
assign o_15=enable?b_15:i_15;
assign o_16=enable?b_16:i_16;
assign o_17=enable?b_17:i_17;
assign o_18=enable?b_18:i_18;
assign o_19=enable?b_19:i_19;
assign o_20=enable?b_20:i_20;
assign o_21=enable?b_21:i_21;
assign o_22=enable?b_22:i_22;
assign o_23=enable?b_23:i_23;
assign o_24=enable?b_24:i_24;
assign o_25=enable?b_25:i_25;
assign o_26=enable?b_26:i_26;
assign o_27=enable?b_27:i_27;
assign o_28=enable?b_28:i_28;
assign o_29=enable?b_29:i_29;
assign o_30=enable?b_30:i_30;
assign o_31=enable?b_31:i_31;
endmodule |
`include "../rtl/adder_tree.v"
`default_nettype none
`timescale 1ms/1us
module tb_adder_tree;
parameter WORD_SIZE = 8;
parameter BANK_SIZE = 4;
reg clk;
reg rst_n;
reg [WORD_SIZE*BANK_SIZE-1:0] in;
wire [(WORD_SIZE+1)*(BANK_SIZE/2)-1:0] out;
adder_tree
#(
.WORD_SIZE(WORD_SIZE),
.BANK_SIZE(BANK_SIZE)
) _adder_tree
(
.clk ( clk ) ,
.rst_n ( rst_n ) ,
.in ( in ) ,
.out ( out )
);
parameter CLK_PERIOD = 10.0;
always #(CLK_PERIOD/2) clk = ~clk;
initial begin
$dumpfile("tb_adder_tree.vcd");
$dumpvars(0, tb_adder_tree);
#1 rst_n<=1'bx;clk<=1'bx;in<=32'hxxxx_xxxx;
#(CLK_PERIOD) rst_n<=1;
#(CLK_PERIOD*3) rst_n<=0;clk<=0;in<=0;
repeat(5) @(posedge clk);
rst_n<=1;
@(posedge clk);
in<={8'd1,8'd2,8'd3,8'd4};
repeat(2) @(posedge clk);
if(out !== {9'd3,9'd7})
$display("result == ", 9'd3, ", ", 9'd7, " expected but ", out[17:9], ", ", out[8:0]);
in<={8'd15,8'd255,8'd255,8'd255};
repeat(2) @(posedge clk);
if(out !== {9'd270,9'd510})
$display("result == ", 9'd270, ", ", 9'd510, " expected but ", out[17:9], ", ", out[8:0]);
repeat(5) @(posedge clk);
$finish(2);
end
endmodule
`default_nettype wire
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__O21A_FUNCTIONAL_PP_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__o21a (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21A_FUNCTIONAL_PP_V |
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module ddr_des
#(
parameter CLKDV = 4
)(
input wire CLK2X,
input wire CLK,
input wire WCLK,
input wire IN,
output reg [CLKDV*4-1:0] OUT,
output wire [1:0] OUT_FAST
);
wire [1:0] DDRQ;
IDDR IDDR_inst (
.Q1(DDRQ[1]), // 1-bit output for positive edge of clock
.Q2(DDRQ[0]), // 1-bit output for negative edge of clock
.C(CLK2X), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D(IN), // 1-bit DDR data input
.R(1'b0), // 1-bit reset
.S(1'b0) // 1-bit set
);
assign OUT_FAST = DDRQ;
reg [1:0] DDRQ_DLY;
always@(posedge CLK2X)
DDRQ_DLY[1:0] <= DDRQ[1:0];
reg [3:0] DDRQ_DATA;
always@(posedge CLK2X)
DDRQ_DATA[3:0] <= {DDRQ_DLY[1:0], DDRQ[1:0]};
reg [3:0] DDRQ_DATA_BUF;
always@(posedge CLK2X)
DDRQ_DATA_BUF[3:0] <= DDRQ_DATA[3:0];
reg [3:0] DATA_IN;
always@(posedge CLK)
DATA_IN[3:0] <= DDRQ_DATA_BUF[3:0];
reg [CLKDV*4-1:0] DATA_IN_SR;
always@(posedge CLK)
DATA_IN_SR <= {DATA_IN_SR[CLKDV*4-5:0],DATA_IN[3:0]};
always@(posedge WCLK)
OUT <= DATA_IN_SR;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
i2s_mclk,
i2s_bclk,
i2s_lrclk,
i2s_sdata_out,
i2s_sdata_in,
spdif,
iic_scl,
iic_sda,
iic_mux_scl,
iic_mux_sda,
otg_vbusoc,
pmod_spi_cs,
pmod_spi_miso,
pmod_spi_clk,
pmod_spi_convst,
pmod_gpio);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [31:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [15:0] hdmi_data;
output spdif;
output i2s_mclk;
output i2s_bclk;
output i2s_lrclk;
output i2s_sdata_out;
input i2s_sdata_in;
inout iic_scl;
inout iic_sda;
inout [ 1:0] iic_mux_scl;
inout [ 1:0] iic_mux_sda;
input otg_vbusoc;
output pmod_spi_cs;
input pmod_spi_miso;
output pmod_spi_clk;
output pmod_spi_convst;
input pmod_gpio;
// internal signals
wire [31:0] gpio_i;
wire [31:0] gpio_o;
wire [31:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
// instantiations
ad_iobuf #(
.DATA_WIDTH(32)
) i_iobuf (
.dio_t(gpio_t),
.dio_i(gpio_o),
.dio_o(gpio_i),
.dio_p(gpio_bd));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_scl (
.dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
.dio_i(iic_mux_scl_o_s),
.dio_o(iic_mux_scl_i_s),
.dio_p(iic_mux_scl));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_sda (
.dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
.dio_i(iic_mux_sda_o_s),
.dio_o(iic_mux_sda_i_s),
.dio_p(iic_mux_sda));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_i (iic_mux_scl_i_s),
.iic_mux_scl_o (iic_mux_scl_o_s),
.iic_mux_scl_t (iic_mux_scl_t_s),
.iic_mux_sda_i (iic_mux_sda_i_s),
.iic_mux_sda_o (iic_mux_sda_o_s),
.iic_mux_sda_t (iic_mux_sda_t_s),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_12 (1'b0),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif),
.pmod_spi_cs (pmod_spi_cs),
.pmod_spi_miso (pmod_spi_miso),
.pmod_spi_clk (pmod_spi_clk),
.pmod_spi_convst (pmod_spi_convst),
.pmod_gpio (pmod_gpio));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (win64) Build 2018833 Wed Oct 4 19:58:22 MDT 2017
// Date : Fri Nov 17 14:55:09 2017
// Host : egk-pc running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ DemoInterconnect_ila_0_0_stub.v
// Design : DemoInterconnect_ila_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a15tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "ila,Vivado 2017.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[0:0],probe1[7:0],probe2[0:0],probe3[7:0]" */;
input clk;
input [0:0]probe0;
input [7:0]probe1;
input [0:0]probe2;
input [7:0]probe3;
endmodule
|
/* This file is part of JT51.
JT51 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-10-2016
*/
`timescale 1ns / 1ps
module jt51_mmr(
input rst,
input clk, // P1
input [7:0] d_in,
input write,
input a0,
output reg busy,
// CT
output reg ct1,
output reg ct2,
// Noise
output reg ne,
output reg [4:0] nfrq,
// LFO
output reg [7:0] lfo_freq,
output reg [1:0] lfo_w,
output reg [6:0] lfo_amd,
output reg [6:0] lfo_pmd,
output reg lfo_rst,
// Timers
output reg [9:0] value_A,
output reg [7:0] value_B,
output reg load_A,
output reg load_B,
output reg enable_irq_A,
output reg enable_irq_B,
output reg clr_flag_A,
output reg clr_flag_B,
output reg clr_run_A,
output reg clr_run_B,
output reg set_run_A,
output reg set_run_B,
input overflow_A,
`ifdef TEST_SUPPORT
// Test
output reg test_eg,
output reg test_op0,
`endif
// REG
output [1:0] rl_I,
output [2:0] fb_II,
output [2:0] con_I,
output [6:0] kc_I,
output [5:0] kf_I,
output [2:0] pms_I,
output [1:0] ams_VII,
output [2:0] dt1_II,
output [3:0] mul_VI,
output [6:0] tl_VII,
output [1:0] ks_III,
output [4:0] arate_II,
output amsen_VII,
output [4:0] rate1_II,
output [1:0] dt2_I,
output [4:0] rate2_II,
output [3:0] d1l_I,
output [3:0] rrate_II,
output keyon_II,
output [1:0] cur_op,
output op31_no,
output op31_acc,
output zero,
output m1_enters,
output m2_enters,
output c1_enters,
output c2_enters,
// Operator
output use_prevprev1,
output use_internal_x,
output use_internal_y,
output use_prev2,
output use_prev1
);
reg [7:0] selected_register, din_latch;
reg up_clr;
reg up_rl, up_kc, up_kf, up_pms,
up_dt1, up_tl, up_ks, up_dt2,
up_d1l, up_keyon, up_amsen;
wire busy_reg;
`ifdef SIMULATION
reg mmr_dump;
`endif
parameter REG_TEST = 8'h01,
REG_TEST2 = 8'h02,
REG_KON = 8'h08,
REG_NOISE = 8'h0f,
REG_CLKA1 = 8'h10,
REG_CLKA2 = 8'h11,
REG_CLKB = 8'h12,
REG_TIMER = 8'h14,
REG_LFRQ = 8'h18,
REG_PMDAMD = 8'h19,
REG_CTW = 8'h1b,
REG_DUMP = 8'h1f;
reg csm;
always @(posedge clk) begin : memory_mapped_registers
if( rst ) begin
selected_register <= 8'h0;
busy <= 1'b0;
{ up_rl, up_kc, up_kf, up_pms, up_dt1, up_tl,
up_ks, up_amsen, up_dt2, up_d1l, up_keyon } <= 11'd0;
`ifdef TEST_SUPPORT
{ test_eg, test_op0 } <= 2'd0;
`endif
// timers
{ value_A, value_B } <= 18'd0;
{ clr_flag_B, clr_flag_A,
enable_irq_B, enable_irq_A, load_B, load_A } <= 6'd0;
{ clr_run_A, clr_run_B, set_run_A, set_run_B } <= 4'b1100;
up_clr <= 1'b0;
// LFO
{ lfo_amd, lfo_pmd } <= 14'h0;
lfo_freq <= 8'd0;
lfo_w <= 2'd0;
lfo_rst <= 1'b0;
{ ct2, ct1 } <= 2'd0;
csm <= 1'b0;
din_latch <= 8'd0;
`ifdef SIMULATION
mmr_dump <= 1'b0;
`endif
end else begin
// WRITE IN REGISTERS
if( write && !busy ) begin
busy <= 1'b1;
if( !a0 )
selected_register <= d_in;
else begin
din_latch <= d_in;
// Global registers
if( selected_register < 8'h20 ) begin
case( selected_register)
// registros especiales
REG_TEST: lfo_rst <= 1'b1; // regardless of d_in
`ifdef TEST_SUPPORT
REG_TEST2: { test_op0, test_eg } <= d_in[1:0];
`endif
REG_KON: up_keyon <= 1'b1;
REG_NOISE: { ne, nfrq } <= { d_in[7], d_in[4:0] };
REG_CLKA1: value_A[9:2]<= d_in;
REG_CLKA2: value_A[1:0]<= d_in[1:0];
REG_CLKB: value_B <= d_in;
REG_TIMER: begin
csm <= d_in[7];
{ clr_flag_B, clr_flag_A,
enable_irq_B, enable_irq_A,
load_B, load_A } <= d_in[5:0];
clr_run_A <= ~d_in[0];
set_run_A <= d_in[0];
clr_run_B <= ~d_in[1];
set_run_B <= d_in[1];
end
REG_LFRQ: lfo_freq <= d_in;
REG_PMDAMD: begin
if( !d_in[7] )
lfo_amd <= d_in[6:0];
else
lfo_pmd <= d_in[6:0];
end
REG_CTW: begin
{ ct2, ct1 } <= d_in[7:6];
lfo_w <= d_in[1:0];
end
`ifdef SIMULATION
REG_DUMP:
mmr_dump <= 1'b1;
`endif
endcase
end else
// channel registers
if( selected_register < 8'h40 ) begin
case( selected_register[4:3] )
2'h0: up_rl <= 1'b1;
2'h1: up_kc <= 1'b1;
2'h2: up_kf <= 1'b1;
2'h3: up_pms<= 1'b1;
endcase
end
else
// operator registers
begin
case( selected_register[7:5] )
3'h2: up_dt1 <= 1'b1;
3'h3: up_tl <= 1'b1;
3'h4: up_ks <= 1'b1;
3'h5: up_amsen <= 1'b1;
3'h6: up_dt2 <= 1'b1;
3'h7: up_d1l <= 1'b1;
endcase
end
end
end
else begin /* clear once-only bits */
`ifdef SIMULATION
mmr_dump <= 1'b0;
`endif
csm <= 1'b0;
lfo_rst <= 1'b0;
{ clr_flag_B, clr_flag_A, load_B, load_A } <= 4'd0;
{ clr_run_A, clr_run_B, set_run_A, set_run_B } <= 4'd0;
if( |{ up_rl, up_kc, up_kf, up_pms, up_dt1, up_tl,
up_ks, up_amsen, up_dt2, up_d1l, up_keyon } == 1'b0 )
busy <= busy_reg;
else
busy <= 1'b1;
if( busy_reg ) begin
up_clr <= 1'b1;
end
else begin
up_clr <= 1'b0;
if( up_clr )
{ up_rl, up_kc, up_kf, up_pms, up_dt1,
up_tl, up_ks, up_amsen, up_dt2, up_d1l,
up_keyon } <= 11'd0;
end
end
end
end
jt51_reg u_reg(
.rst ( rst ),
.clk ( clk ), // P1
.d_in ( din_latch ),
.up_rl ( up_rl ),
.up_kc ( up_kc ),
.up_kf ( up_kf ),
.up_pms ( up_pms ),
.up_dt1 ( up_dt1 ),
.up_tl ( up_tl ),
.up_ks ( up_ks ),
.up_amsen ( up_amsen ),
.up_dt2 ( up_dt2 ),
.up_d1l ( up_d1l ),
.up_keyon ( up_keyon ),
.op( selected_register[4:3] ), // operator to update
.ch( selected_register[2:0] ), // channel to update
.csm ( csm ),
.overflow_A ( overflow_A),
.busy ( busy_reg ),
.rl_I ( rl_I ),
.fb_II ( fb_II ),
.con_I ( con_I ),
.kc_I ( kc_I ),
.kf_I ( kf_I ),
.pms_I ( pms_I ),
.ams_VII ( ams_VII ),
.dt1_II ( dt1_II ),
.dt2_I ( dt2_I ),
.mul_VI ( mul_VI ),
.tl_VII ( tl_VII ),
.ks_III ( ks_III ),
.arate_II ( arate_II ),
.amsen_VII ( amsen_VII ),
.rate1_II ( rate1_II ),
.rate2_II ( rate2_II ),
.rrate_II ( rrate_II ),
.d1l_I ( d1l_I ),
.keyon_II ( keyon_II ),
.cur_op ( cur_op ),
.op31_no ( op31_no ),
.op31_acc ( op31_acc ),
.zero ( zero ),
.m1_enters ( m1_enters ),
.m2_enters ( m2_enters ),
.c1_enters ( c1_enters ),
.c2_enters ( c2_enters ),
// Operator
.use_prevprev1 ( use_prevprev1 ),
.use_internal_x ( use_internal_x ),
.use_internal_y ( use_internal_y ),
.use_prev2 ( use_prev2 ),
.use_prev1 ( use_prev1 )
);
`ifdef SIMULATION
/* verilator lint_off PINMISSING */
wire [4:0] cnt_aux;
sep32_cnt u_sep32_cnt (.clk(clk), .zero(zero), .cnt(cnt_aux));
sep32 #(.width(2),.stg(1)) sep_rl (.clk(clk),.cnt(cnt_aux),.mixed( rl_I ));
sep32 #(.width(3),.stg(2)) sep_fb (.clk(clk),.cnt(cnt_aux),.mixed( fb_II ));
sep32 #(.width(3),.stg(1)) sep_con(.clk(clk),.cnt(cnt_aux),.mixed( con_I ));
sep32 #(.width(7),.stg(1)) sep_kc (.clk(clk),.cnt(cnt_aux),.mixed( kc_I ));
sep32 #(.width(6),.stg(1)) sep_kf (.clk(clk),.cnt(cnt_aux),.mixed( kf_I ));
sep32 #(.width(3),.stg(1)) sep_pms(.clk(clk),.cnt(cnt_aux),.mixed( pms_I ));
sep32 #(.width(2),.stg(7)) sep_ams(.clk(clk),.cnt(cnt_aux),.mixed( ams_VII ));
sep32 #(.width(3),.stg(2)) sep_dt1(.clk(clk),.cnt(cnt_aux),.mixed( dt1_II ));
sep32 #(.width(2),.stg(1)) sep_dt2(.clk(clk),.cnt(cnt_aux),.mixed( dt2_I ));
sep32 #(.width(4),.stg(6)) sep_mul(.clk(clk),.cnt(cnt_aux),.mixed( mul_VI ));
sep32 #(.width(7),.stg(7)) sep_tl (.clk(clk),.cnt(cnt_aux),.mixed( tl_VII ));
sep32 #(.width(2),.stg(3)) sep_ks (.clk(clk),.cnt(cnt_aux),.mixed( ks_III ));
sep32 #(.width(5),.stg(2)) sep_ar (.clk(clk),.cnt(cnt_aux),.mixed( arate_II ));
sep32 #(.width(1),.stg(7)) sep_ame(.clk(clk),.cnt(cnt_aux),.mixed( amsen_VII));
sep32 #(.width(5),.stg(2)) sep_dr1(.clk(clk),.cnt(cnt_aux),.mixed( rate1_II ));
sep32 #(.width(5),.stg(2)) sep_dr2(.clk(clk),.cnt(cnt_aux),.mixed( rate2_II ));
sep32 #(.width(4),.stg(2)) sep_rr (.clk(clk),.cnt(cnt_aux),.mixed( rrate_II ));
sep32 #(.width(4),.stg(1)) sep_d1l(.clk(clk),.cnt(cnt_aux),.mixed( d1l_I ));
`endif
endmodule
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`define SD #1
`timescale 1ns/1ps
`include "include/mbus_def.v"
module tb_layer_ctrl();
`include "include/mbus_func.v"
parameter LC_INT_DEPTH=13;
parameter LC_MEM_DEPTH=65536;
parameter LC_RF_DEPTH=256;
localparam BULK_MEM_CTRL_REG_IDX = 242;
localparam STREAM_CH0_REG0_IDX = 236;
localparam STREAM_CH0_REG1_IDX = 237;
localparam STREAM_CH0_REG2_IDX = 238;
localparam STREAM_CH1_REG0_IDX = 232;
localparam STREAM_CH1_REG1_IDX = 233;
localparam STREAM_CH1_REG2_IDX = 234;
reg clk, resetn;
wire SCLK;
// n0 connections
reg [LC_INT_DEPTH-1:0] n0_int_vector;
wire [LC_INT_DEPTH-1:0] n0_clr_int;
// end of n0 connections
// n1 connections
reg [LC_INT_DEPTH-1:0] n1_int_vector;
wire [LC_INT_DEPTH-1:0] n1_clr_int;
// end of n1 connections
// n2 connections
reg [LC_INT_DEPTH-1:0] n2_int_vector;
wire [LC_INT_DEPTH-1:0] n2_clr_int;
// end of n2 connections
// n3 connections
reg [LC_INT_DEPTH-1:0] n3_int_vector;
wire [LC_INT_DEPTH-1:0] n3_clr_int;
// end of n3 connections
// c0 connections
reg [`ADDR_WIDTH-1:0] c0_tx_addr;
reg [`DATA_WIDTH-1:0] c0_tx_data;
reg c0_tx_req, c0_priority, c0_tx_pend, c0_tx_resp_ack, c0_req_int;
wire c0_tx_ack, c0_tx_succ, c0_tx_fail;
wire [`ADDR_WIDTH-1:0] c0_rx_addr;
wire [`DATA_WIDTH-1:0] c0_rx_data;
wire c0_rx_req, c0_rx_fail, c0_rx_pend, c0_rx_broadcast;
reg c0_rx_ack;
wire c0_lc_pwr_on, c0_lc_release_clk, c0_lc_release_rst, c0_lc_release_iso;
// end of c0 connections
// connection between nodes
wire w_n0n1, w_n1n2, w_n2n3, w_n3c0, w_c0n0;
wire w_n0_clk_out, w_n1_clk_out, w_n2_clk_out, w_n3_clk_out;
// testbench variables
reg [31:0] rand_dat, rand_dat2;
reg [4:0] state;
reg [5:0] word_counter;
reg [7:0] rf_read_length;
reg [7:0] rf_addr;
reg [29:0] mem_addr;
reg mem_ptr_set;
reg [1:0] mem_access_state;
reg [7:0] relay_addr;
reg [29:0] mem_relay_loc;
reg [7:0] rf_relay_loc;
reg [3:0] dest_short_addr;
reg [23:0] rf_data;
reg [31:0] mem_data;
reg [19:0] mem_read_length;
reg [3:0] enum_short_addr;
reg [19:0] long_addr;
reg [1:0] layer_number;
reg [LC_INT_DEPTH-1:0] int_vec;
reg [31:0] mem_w_data;
reg [3:0] functional_id;
reg [23:0] rf_w_data;
reg [1:0] stream_channel;
integer handle;
integer task_counter;
localparam TB_PROC_UP = 0;
localparam TB_QUERY = 1;
localparam TB_ENUM = 2;
localparam TB_ALL_WAKEUP = 3;
localparam TB_RF_WRITE = 4;
localparam TB_RF_READ = 5;
localparam TB_MEM_WRITE = 6;
localparam TB_MEM_READ = 7;
localparam TB_SEL_SLEEP_FULL_PREFIX = 8;
localparam TB_ALL_SLEEP = 9;
localparam TB_ALL_SHORT_ADDR_INVALID = 10;
localparam TB_SINGLE_INTERRUPT = 11;
localparam TB_MULTIPLE_INTERRUPT = 12;
localparam TB_SINGLE_MEM_WRITE = 13;
localparam TB_ARBITRARY_CMD = 14;
localparam TB_SINGLE_RF_WRITE = 15;
localparam TB_SHORT_MEM_READ = 16;
localparam TB_STREAMING = 17;
localparam TX_WAIT = 31;
reg c0_auto_rx_ack;
layer_wrapper #(.ADDRESS(20'hbbbb0), .LC_INT_DEPTH(LC_INT_DEPTH)) layer0(
.CLK(clk), .RESETn(resetn),
.INT_VECTOR(n0_int_vector),
.CLR_INT_EXTERNAL(n0_clr_int),
// mbus
.CLKIN(SCLK), .CLKOUT(w_n0_clk_out), .DIN(w_c0n0), .DOUT(w_n0n1));
layer_wrapper #(.ADDRESS(20'hbbbb1), .LC_INT_DEPTH(LC_INT_DEPTH)) layer1(
.CLK(clk), .RESETn(resetn),
.INT_VECTOR(n1_int_vector),
.CLR_INT_EXTERNAL(n1_clr_int),
// mbus
.CLKIN(w_n0_clk_out), .CLKOUT(w_n1_clk_out), .DIN(w_n0n1), .DOUT(w_n1n2));
layer_wrapper #(.ADDRESS(20'hbbbb2), .LC_INT_DEPTH(LC_INT_DEPTH)) layer2(
.CLK(clk), .RESETn(resetn),
.INT_VECTOR(n2_int_vector),
.CLR_INT_EXTERNAL(n2_clr_int),
// mbus
.CLKIN(w_n1_clk_out), .CLKOUT(w_n2_clk_out), .DIN(w_n1n2), .DOUT(w_n2n3));
layer_wrapper #(.ADDRESS(20'hbbbb2), .LC_INT_DEPTH(LC_INT_DEPTH)) layer3(
.CLK(clk), .RESETn(resetn),
.INT_VECTOR(n3_int_vector),
.CLR_INT_EXTERNAL(n3_clr_int),
// mbus
.CLKIN(w_n2_clk_out), .CLKOUT(w_n3_clk_out), .DIN(w_n2n3), .DOUT(w_n3c0));
mbus_ctrl_layer_wrapper #(.ADDRESS(20'haaaa0)) c0
(.CLK_EXT(clk), .CLKIN(w_n3_clk_out), .CLKOUT(SCLK), .RESETn(resetn), .DIN(w_n3c0), .DOUT(w_c0n0),
.TX_ADDR(c0_tx_addr), .TX_DATA(c0_tx_data), .TX_REQ(c0_tx_req), .TX_ACK(c0_tx_ack), .TX_PEND(c0_tx_pend), .TX_PRIORITY(c0_priority),
.RX_ADDR(c0_rx_addr), .RX_DATA(c0_rx_data), .RX_REQ(c0_rx_req), .RX_ACK(c0_rx_ack), .RX_FAIL(c0_rx_fail), .RX_PEND(c0_rx_pend),
.TX_SUCC(c0_tx_succ), .TX_FAIL(c0_tx_fail), .TX_RESP_ACK(c0_tx_resp_ack), .RX_BROADCAST(c0_rx_broadcast),
.LC_POWER_ON(c0_lc_pwr_on), .LC_RELEASE_CLK(c0_lc_release_clk), .LC_RELEASE_RST(c0_lc_release_rst), .LC_RELEASE_ISO(c0_lc_release_iso),
.REQ_INT(c0_req_int));
`include "tasks.v"
initial
begin
task_counter = 0;
clk = 0;
resetn = 1;
mem_addr = 0;
mem_ptr_set = 0;
mem_access_state = 0;
mem_data = 0;
mem_relay_loc = 0;
mem_read_length = 0;
rf_addr = 0;
rf_data = 0;
rf_read_length = 0;
rf_relay_loc = 0;
relay_addr = 0;
enum_short_addr = 4'h2;
long_addr = 20'haaaa0;
layer_number = 0;
int_vec = 0;
mem_w_data = 0;
functional_id = 0;
stream_channel = 0;
@ (posedge clk);
@ (posedge clk);
@ (posedge clk);
`SD resetn = 0;
@ (posedge clk);
@ (posedge clk);
`SD resetn = 1;
@ (posedge clk);
@ (posedge clk);
//VCD DUMP SECTION
//`ifdef APR
/*
`ifdef TASK4
$dumpfile("task4.vcd");
`elsif TASK5
$dumpfile("task5.vcd");
`endif
$dumpvars(0, tb_ulpb_node32);
*/
//`endif
//SDF ANNOTATION
`ifdef SYN
$sdf_annotate("../syn/layer_ctrl_v2.dc.sdf", layer0.lc0);
$sdf_annotate("../syn/layer_ctrl_v2.dc.sdf", layer1.lc0);
$sdf_annotate("../syn/layer_ctrl_v2.dc.sdf", layer2.lc0);
$sdf_annotate("../syn/layer_ctrl_v2.dc.sdf", layer3.lc0);
`endif
/*
`elsif APR
$sdf_annotate("../apr/ulpb_ctrl_wrapper/ulpb_ctrl_wrapper.apr.sdf", c0);
$sdf_annotate("../apr/ulpb_node32_ab/ulpb_node32_ab.apr.sdf", n0);
$sdf_annotate("../apr/ulpb_node32_cd/ulpb_node32_cd.apr.sdf", n1);
$sdf_annotate("../apr/ulpb_node32_ef/ulpb_node32_ef.apr.sdf", n2);
`endif
*/
//************************
//TESTBENCH BEGINS
//Calls Tasks from tasks.v
//***********************
task0();
end // initial begin
//Changed to 400K for primetime calculations
always #1250 clk = ~clk;
`include "task_list.v"
always @ (posedge layer0.lc_pwr_on)
$fdisplay(handle, "N0 LC Sleep");
always @ (posedge layer1.lc_pwr_on)
$fdisplay(handle, "N1 LC Sleep");
always @ (posedge layer2.lc_pwr_on)
$fdisplay(handle, "N2 LC Sleep");
always @ (posedge layer3.lc_pwr_on)
$fdisplay(handle, "N3 LC Sleep");
always @ (posedge c0_lc_pwr_on)
$fdisplay(handle, "Processor Sleep");
always @ (negedge layer0.lc_pwr_on)
$fdisplay(handle, "N0 LC Wakeup");
always @ (negedge layer1.lc_pwr_on)
$fdisplay(handle, "N1 LC Wakeup");
always @ (negedge layer2.lc_pwr_on)
$fdisplay(handle, "N2 LC Wakeup");
always @ (negedge layer3.lc_pwr_on)
$fdisplay(handle, "N3 LC Wakeup");
always @ (negedge c0_lc_pwr_on)
$fdisplay(handle, "Processor Wakeup");
always @ (posedge clk or negedge resetn)
begin
if (~resetn)
begin
n0_int_vector <= 0;
n1_int_vector <= 0;
n2_int_vector <= 0;
n3_int_vector <= 0;
c0_tx_addr <= 0;
c0_tx_data <= 0;
c0_tx_pend <= 0;
c0_tx_req <= 0;
c0_priority <= 0;
c0_req_int <= 0;
c0_auto_rx_ack <= 1;
word_counter <= 0;
end
else
begin
if (c0_tx_ack) c0_tx_req <= 0;
if (c0_tx_fail & c0_tx_req) c0_tx_req <= 0;
end
end
// n0 interrupt control
wire [LC_INT_DEPTH-1:0] n0_int_clr_mask = (n0_clr_int & n0_int_vector);
always @ (posedge clk)
begin
if (n0_int_clr_mask)
n0_int_vector <= `SD (n0_int_vector & (~n0_int_clr_mask));
end
always @ (posedge layer0.rx_fail)
$fdisplay(handle, "N0 RX Fail");
always @ (posedge layer0.rx_req)
begin
$fdisplay(handle, "N0 RX Success");
//$fdisplay(handle, "N0 Data out =\t32'h%h", layer0.rx_data);
end
always @ (posedge layer0.tx_succ)
$fdisplay(handle, "N0 TX Success\n");
always @ (posedge layer0.tx_fail)
$fdisplay(handle, "N0 TX Fail\n");
// end of n0 interrupt control
// n1 interrupt control
wire [LC_INT_DEPTH-1:0] n1_int_clr_mask = (n1_clr_int & n1_int_vector);
always @ (posedge clk)
begin
if (n1_int_clr_mask)
n1_int_vector <= `SD (n1_int_vector & (~n1_int_clr_mask));
end
always @ (posedge layer1.rx_fail)
$fdisplay(handle, "N1 RX Fail");
always @ (posedge layer1.rx_req)
begin
$fdisplay(handle, "N1 RX Success");
//$fdisplay(handle, "N1 Data out =\t32'h%h", layer1.rx_data);
end
always @ (posedge layer1.tx_succ)
$fdisplay(handle, "N1 TX Success\n");
always @ (posedge layer1.tx_fail)
$fdisplay(handle, "N1 TX Fail\n");
// end of n1 interrupt control
// n2 interrupt control
wire [LC_INT_DEPTH-1:0] n2_int_clr_mask = (n2_clr_int & n2_int_vector);
always @ (posedge clk)
begin
if (n2_int_clr_mask)
n2_int_vector <= `SD (n2_int_vector & (~n2_int_clr_mask));
end
always @ (posedge layer2.rx_fail)
$fdisplay(handle, "N2 RX Fail");
always @ (posedge layer2.rx_req)
begin
$fdisplay(handle, "N2 RX Success");
//$fdisplay(handle, "N2 Data out =\t32'h%h", layer2.rx_data);
end
always @ (posedge layer2.tx_succ)
$fdisplay(handle, "N2 TX Success\n");
always @ (posedge layer2.tx_fail)
$fdisplay(handle, "N2 TX Fail\n");
// end of n2 interrupt control
// n3 interrupt control
wire [LC_INT_DEPTH-1:0] n3_int_clr_mask = (n3_clr_int & n3_int_vector);
always @ (posedge clk)
begin
if (n3_int_clr_mask)
n3_int_vector <= `SD (n3_int_vector & (~n3_int_clr_mask));
end
always @ (posedge layer3.rx_fail)
$fdisplay(handle, "N3 RX Fail");
always @ (posedge layer3.rx_req)
begin
$fdisplay(handle, "N3 RX Success");
//$fdisplay(handle, "N3 Data out =\t32'h%h", layer3.rx_data);
end
always @ (posedge layer3.tx_succ)
$fdisplay(handle, "N3 TX Success\n");
always @ (posedge layer3.tx_fail)
$fdisplay(handle, "N3 TX Fail\n");
// end of n3 interrupt control
// c0 rx tx ack control
always @ (negedge resetn)
begin
c0_rx_ack <= 0;
c0_tx_resp_ack <= 0;
end
always @ (posedge c0_rx_fail)
$fdisplay(handle, "C0 RX Fail");
always @ (posedge c0_rx_req)
begin
$fdisplay(handle, "C0 RX Success");
$fdisplay(handle, "C0 Data out =\t32'h%h", c0_rx_data);
end
always @ (posedge clk)
begin
if ((c0_rx_req | c0_rx_fail) & c0_auto_rx_ack)
`SD c0_rx_ack <= 1;
if (c0_rx_ack & (~c0_rx_req))
`SD c0_rx_ack <= 0;
if (c0_rx_ack & (~c0_rx_fail))
`SD c0_rx_ack <= 0;
end
always @ (posedge c0_tx_succ)
$fdisplay(handle, "C0 TX Success");
always @ (posedge c0_tx_fail)
$fdisplay(handle, "C0 TX Fail");
always @ (posedge clk)
begin
if (c0_tx_succ | c0_tx_fail)
`SD c0_tx_resp_ack <= 1;
if (c0_tx_resp_ack & (~c0_tx_succ))
`SD c0_tx_resp_ack <= 0;
if (c0_tx_resp_ack & (~c0_tx_fail))
`SD c0_tx_resp_ack <= 0;
end
// end of c0 rx, tx ack control
always @ (posedge clk or negedge resetn) begin
if (~resetn) begin
rand_dat <= 0;
rand_dat2 <= 0;
end
else begin
rand_dat <= $random;
rand_dat2 <= $random;
end
end
// RF Write output
wire [31:0] layer0_rf0_addr = log2long(layer0.rf0.LOAD) - 1;
wire [31:0] layer1_rf0_addr = log2long(layer1.rf0.LOAD) - 1;
wire [31:0] layer2_rf0_addr = log2long(layer2.rf0.LOAD) - 1;
wire [31:0] layer3_rf0_addr = log2long(layer3.rf0.LOAD) - 1;
genvar idx;
generate
for (idx=0; idx<LC_RF_DEPTH; idx = idx+1)
begin: rf_write
always @ (posedge layer0.rf0.LOAD[idx])
$fdisplay(handle, "Layer 0, RF Write, Addr: 8'h%h,\tData: 24'h%h", layer0_rf0_addr[7:0], layer0.rf0.DIN);
always @ (posedge layer1.rf0.LOAD[idx])
$fdisplay(handle, "Layer 1, RF Write, Addr: 8'h%h,\tData: 24'h%h", layer1_rf0_addr[7:0], layer1.rf0.DIN);
always @ (posedge layer2.rf0.LOAD[idx])
$fdisplay(handle, "Layer 2, RF Write, Addr: 8'h%h,\tData: 24'h%h", layer2_rf0_addr[7:0], layer2.rf0.DIN);
always @ (posedge layer3.rf0.LOAD[idx])
$fdisplay(handle, "Layer 3, RF Write, Addr: 8'h%h,\tData: 24'h%h", layer3_rf0_addr[7:0], layer3.rf0.DIN);
end
endgenerate
// End of RF Write output
// MEM Write output
always @ (posedge layer0.mem0.MEM_ACK_OUT)
if (layer0.mem0.MEM_WRITE)
$fdisplay(handle, "Layer 0, MEM Write, Addr: 30'h%h,\tData: 32'h%h", layer0.mem0.ADDR, layer0.mem0.DATA_IN);
else
$fdisplay(handle, "Layer 0, MEM Read, Addr: 30'h%h,\tData: 32'h%h", layer0.mem0.ADDR, layer0.mem0.DATA_OUT);
always @ (posedge layer1.mem0.MEM_ACK_OUT)
if (layer1.mem0.MEM_WRITE)
$fdisplay(handle, "Layer 1, MEM Write, Addr: 30'h%h,\tData: 32'h%h", layer1.mem0.ADDR, layer1.mem0.DATA_IN);
else
$fdisplay(handle, "Layer 1, MEM Read, Addr: 30'h%h,\tData: 32'h%h", layer1.mem0.ADDR, layer1.mem0.DATA_OUT);
always @ (posedge layer2.mem0.MEM_ACK_OUT)
if (layer2.mem0.MEM_WRITE)
$fdisplay(handle, "Layer 2, MEM Write, Addr: 30'h%h,\tData: 32'h%h", layer2.mem0.ADDR, layer2.mem0.DATA_IN);
else
$fdisplay(handle, "Layer 2, MEM Read, Addr: 30'h%h,\tData: 32'h%h", layer2.mem0.ADDR, layer2.mem0.DATA_OUT);
always @ (posedge layer3.mem0.MEM_ACK_OUT)
if (layer3.mem0.MEM_WRITE)
$fdisplay(handle, "Layer 3, MEM Write, Addr: 30'h%h,\tData: 32'h%h", layer3.mem0.ADDR, layer3.mem0.DATA_IN);
else
$fdisplay(handle, "Layer 3, MEM Read, Addr: 30'h%h,\tData: 32'h%h", layer3.mem0.ADDR, layer3.mem0.DATA_OUT);
// End of MEM Write output
endmodule // tb_layer_ctrl
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_MUX_4TO2_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_MUX_4TO2_BLACKBOX_V
/**
* udp_mux_4to2: Four to one multiplexer with 2 select controls
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_mux_4to2 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_MUX_4TO2_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4BB_BLACKBOX_V
`define SKY130_FD_SC_HD__NOR4BB_BLACKBOX_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nor4bb (
Y ,
A ,
B ,
C_N,
D_N
);
output Y ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4BB_BLACKBOX_V
|
module Top(clk, reset, Segment, AN, VGA_R, VGA_G, VGA_B, hsync, vsync, kbd_clk, kbd_data, LED);
input clk;
input reset;
input kbd_clk;
input kbd_data;
output [7: 0] Segment;
output [3: 0] AN;
output [2: 0] VGA_R, VGA_G;
output [1: 0] VGA_B;
output hsync, vsync;
output [7: 0] LED;
// slow clock down
reg [5: 0] cnt = 0;
always @(posedge clk) begin
cnt <= cnt + 1;
end
wire sclk = cnt[5];
// ===========
// Wishbone IO
// ===========
// Master
wire CPU_STB, CPU_ACK, CPU_WE;
wire [31: 0] CPU_Data_I, CPU_Data_O, CPU_Addr;
// Slave
wire [16: 0] slave_ACK, slave_STB, slave_WE;
wire [31: 0] slave_DAT_I, slave_ADDR;
wire [511: 0] slave_DAT_O;
// Slave members
wire Keyboard_ACK, VGA_ACK, seven_seg_ACK, Ram_ACK, Counter_ACK;
wire [31: 0] Keyboard_DAT_O, VGA_DAT_O, seven_seg_DAT_O, Ram_DAT_O, Counter_DAT_O;
wire Ram_STB = slave_STB[1];
wire seven_seg_STB = slave_STB[0];
wire VGA_STB = slave_STB[2];
wire Keyboard_STB = slave_STB[3];
wire Counter_STB = slave_STB[4];
// ==================
// Instruction Memory
// 32 bit * 16384
// ==================
wire [31: 0] pc;
wire [31: 0] inst;
Instruction_Memory im(
.a(pc >> 2),
.spo(inst)
);
CPU cpu(
.clk(sclk),
.reset(reset),
.inst(inst),
.Data_I(CPU_Data_I),
.pc(pc),
.Addr(CPU_Addr),
.Data_O(CPU_Data_O),
.WE(CPU_WE),
.ACK(CPU_ACK),
.STB(CPU_STB)
);
// Device signal address defination:
// 0: Ram
// 1: Seven seg
// 2: VGA
// 3: Keyboard
// 4: Counter
assign slave_ACK = {10'b0,Counter_ACK, Keyboard_ACK, VGA_ACK, Ram_ACK, seven_seg_ACK};
assign slave_DAT_O = {320'b0, Counter_DAT_O, Keyboard_DAT_O, VGA_DAT_O, Ram_DAT_O, seven_seg_DAT_O};
WB_intercon intercon(
.master_STB(CPU_STB),
.master_DAT_I(CPU_Data_O),
.master_DAT_O(CPU_Data_I),
.master_ACK(CPU_ACK),
.master_WE(CPU_WE),
.master_ADDR(CPU_Addr),
.slave_STB(slave_STB),
.slave_ACK(slave_ACK),
.slave_WE(slave_WE),
.slave_DAT_O(slave_DAT_I),
.slave_DAT_I(slave_DAT_O),
.slave_ADDR(slave_ADDR)
);
// ==============
// Ram
// 32 bit * 16384
// ==============
Ram_driver ram_driver(
.clk(sclk),
.Ram_STB(Ram_STB),
.Ram_ACK(Ram_ACK)
);
Ram ram(
.clka(clk),
.addra(slave_ADDR >> 2),
.dina(slave_DAT_I),
.wea(slave_WE & Ram_STB),
.douta(Ram_DAT_O)
);
Seven_seg seven_seg(
.clk(clk),
.reset(reset),
//.DAT_I(slave_DAT_I),
.DAT_I(pc),
.DAT_O(seven_seg_DAT_O),
//.STB(seven_seg_STB),
.STB(1),
.ACK(seven_seg_ACK),
.WE(slave_WE),
.Segment(Segment),
.AN(AN)
);
Counter counter(
.clk(clk),
.reset(reset),
.DAT_O(Counter_DAT_O),
.STB(Counter_STB),
.ACK(Counter_ACK)
);
// ===
// VGA
// ===
wire [9: 0] x_ptr, y_ptr;
wire [7: 0] color;
Video_card video_card(
.clk(sclk),
.reset(reset),
.x_ptr(x_ptr),
.y_ptr(y_ptr),
.color(color),
.DAT_I(slave_DAT_I),
.DAT_O(VGA_DAT_O),
.WE(slave_WE),
.STB(VGA_STB),
.ACK(VGA_ACK),
.ADDR(slave_ADDR >> 2)
);
Vga_dev vga_dev(
.clk(clk),
.reset(reset),
.hsync(hsync),
.vsync(vsync),
.color(color),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.x_ptr(x_ptr),
.y_ptr(y_ptr)
);
// ==========
// Keyboard
// ==========
wire [7: 0] Keyboard_Data;
wire Keyboard_ready_pulse;
Keyboard_driver keyboard_driver(
.clk(clk),
.reset(reset),
.ready_pulse(Keyboard_ready_pulse),
.Keyboard_Data(Keyboard_Data),
.ACK(Keyboard_ACK),
.STB(Keyboard_STB),
.DAT_O(Keyboard_DAT_O)
);
Keyboard_dev keyboard(
.clk(clk),
.reset(reset),
.kbd_clk(kbd_clk),
.kbd_data(kbd_data),
.Keyboard_Data(Keyboard_Data),
.ready_pulse(Keyboard_ready_pulse)
);
assign LED = Keyboard_Data;
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_leds (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 7: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 7: 0] data_out;
wire [ 7: 0] out_port;
wire [ 7: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[7 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXBP_BEHAVIORAL_V
`define SKY130_FD_SC_HD__DLXBP_BEHAVIORAL_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hd__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dlxbp (
Q ,
Q_N ,
D ,
GATE
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
assign awake = ( VPWR === 1'b1 );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXBP_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__INV_2_V
`define SKY130_FD_SC_HD__INV_2_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__inv_2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__inv_2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__INV_2_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:37:23 10/06/2014
// Design Name:
// Module Name: uart
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module uart_tx(clk, reset, wren, rden, din, dout, txout, addr);
input clk, reset, wren, rden;
input [7:0] din;
output [7:0] dout;
output txout; //serial data out
input [2:0] addr;
// corgen fifo
/*module fifo(clk, rst, din, wr_en, rd_en, dout, full, empty
);
input clk;
input rst;
input [7 : 0] din;
input wr_en;
input rd_en;
output [7 : 0] dout;
output full;
output empty;*/
/*baud generator
module baudgen(wren, rden, reset, din, clk, sclr, baud, dout);
input wren, rden, reset, clk, sclr;
input [7:0] din;
output baud;
output [7:0] dout;
*/
reg [7:0] control, dout;
reg [9:0] shift_out;
reg wr_baud, rd_baud, wr_fifo, rd_fifo, wr_control;
reg ld_shift, stop, count, finish, rd_shift, bittime;
reg [3:0] bittimer, bitcounter;
reg [1:0] nstate, pstate;
parameter PERIOD = 8'h1A;
wire [7:0] to_shift, dout_baud;
wire [9:0] shift;
wire baud, full, empty;
`define period 3'b000
`define TXreg 3'b001
`define control 3'b011
`define WAIT 2'b00
`define SHIFT1 2'b01
`define SHIFT2 2'b10
`define TXFULL control[0]
`define TXDONE control[1]
baudgen #(.PERIOD(PERIOD)) baud1(
.wren (wr_baud),
.rden (rd_baud),
.reset (reset),
.din (din),
.clk (clk),
.stop (stop),
.baud (baud),
.dout (dout_baud)
);
fifo fifo1(
.clk (clk),
.rst (reset),
.din (din),
.wr_en (wr_fifo),
.rd_en (rd_fifo),
.dout (to_shift),
.full (full),
.empty (empty)
);
// assign shift_in
assign shift = ({1'b1, to_shift, 1'b0});
assign txout = shift_out[0];
// shift register
always @(posedge clk or posedge reset) begin
if(reset)
shift_out <= 10'b1111111111;
else begin
if (rd_shift)begin
//txout = shift_out[0];
shift_out <= {1'b1, shift_out[9:1]};
end
if (ld_shift)
shift_out <= shift;
end
end
// control register
always @(posedge clk or posedge reset) begin
if(reset) begin
control[7:0] = 8'b00000001;
end
else begin
`TXFULL = full;
if(finish)
`TXDONE = 1;
if(wr_control)
`TXDONE = 0;
end
end
// address mux logic
always @* begin
wr_baud = 0;
wr_fifo = 0; wr_control = 0;
case(addr)
`period: begin
if(wren)
wr_baud = 1;
end
`TXreg: begin
if(wren)
wr_fifo = 1;
end
`control: begin
if(wren)
wr_control = 1;
end
endcase
end
// out mux
always @* begin
rd_baud = 0;
dout = 8'b00000000;
case(addr)
`period: begin
if(rden)
rd_baud = 1;
dout = dout_baud;
end
`control: begin
if(rden)
dout = control;
end
endcase
end
// bittimer
always @(posedge baud or posedge reset) begin
if(reset)
bittimer <= 4'b0000;
else begin
if(bittime)
bittimer <= bittimer + 1;
end
end
// bitcounter
always @(posedge clk or posedge reset) begin
if(reset)begin
bitcounter <= 4'b0000;
end
else begin
if(count)
bitcounter <= bitcounter + 1;
if(finish)
bitcounter <= 4'b0000;
end
end
// set state during startup.
always @(posedge clk or posedge reset) begin
if (reset)
pstate <= `WAIT;
else
pstate <= nstate;
end
// fsm
always @* begin
rd_fifo = 0; ld_shift = 0;
stop = 0; count = 0; finish = 0;
bittime = 0; rd_shift = 0;
nstate = pstate;
case (pstate)
`WAIT: begin
stop = 1;
if(~empty) begin
stop = 0;
rd_fifo = 1;
ld_shift = 1;
nstate = `SHIFT1;
end
end
`SHIFT1: begin
if(bitcounter == 4'b1010) begin
nstate = `WAIT;
finish = 1;
end
else begin
if(baud)
nstate = `SHIFT2;
bittime = 1;
end
end
`SHIFT2: begin
bittime = 1;
if(~baud & (bittimer == 4'b0000)) begin
count = 1;
rd_shift = 1;
nstate = `SHIFT1;
end
end
endcase
end
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module m26_rx #(
parameter BASEADDR = 16'h0000,
parameter HIGHADDR = 16'h0000,
parameter ABUSWIDTH = 16,
parameter HEADER = 0,
parameter IDENTIFIER = 0
) (
input wire BUS_CLK,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RST,
input wire BUS_WR,
input wire BUS_RD,
input wire CLK_RX,
input wire MKD_RX,
input wire [1:0] DATA_RX,
input wire FIFO_READ,
output wire FIFO_EMPTY,
output wire [31:0] FIFO_DATA,
input wire [31:0] TIMESTAMP,
output wire LOST_ERROR,
output wire INVALID,
output wire INVALID_FLAG
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #(
.BASEADDR(BASEADDR),
.HIGHADDR(HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_bus_to_ip (
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
m26_rx_core #(
.ABUSWIDTH(ABUSWIDTH),
.IDENTIFIER(IDENTIFIER),
.HEADER(HEADER)
) i_m26_rx_core (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.CLK_RX(CLK_RX),
.MKD_RX(MKD_RX),
.DATA_RX(DATA_RX),
.FIFO_READ(FIFO_READ),
.FIFO_EMPTY(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA),
.TIMESTAMP(TIMESTAMP),
.LOST_ERROR(LOST_ERROR),
.INVALID(INVALID),
.INVALID_FLAG(INVALID_FLAG)
);
endmodule
|
(*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*)
(** Encoding and utility functions to support the result of evaluation
over CAMP patterns. *)
Require Import String.
Require Import List.
Require Import EquivDec.
Require Import Morphisms.
Require Import Utils.
Require Import DataRuntime.
Section CAMPUtil.
Local Open Scope string.
(** Evaluating a CAMP pattern returns a presult, which includes two
kinds of errors: either a match failure, which is recoverable, or a
terminal error. *)
Inductive presult A :=
| TerminalError : presult A
| RecoverableError : presult A
| Success (res:A) : presult A.
(* begin hide *)
Arguments TerminalError {A}.
Arguments RecoverableError {A}.
Arguments Success {A} res.
(* end hide *)
(** Equality between two presult is decidable *)
Global Instance presult_eqdec {A} {dec:EqDec A eq} :
EqDec (presult A) eq.
Proof.
red; unfold equiv, complement.
destruct x; destruct y; simpl;
try solve [right; inversion 1]; eauto 2.
destruct (res == res0); unfold equiv, complement in *;
[left | right; inversion 1]; congruence.
Defined.
(** Prints a presult *)
Global Instance print_presult {A} {tos:ToString A} : ToString (presult A)
:= { toString :=
fun pr =>
match pr with
| TerminalError => "TerminalError (for more info, use debug mode)"
| RecoverableError => "RecoverableError (for more info, use debug mode)"
| Success res => "Success: " ++ toString res
end
}.
(** Lifting functions used in the evaluation of patterns. Used to handle the various possible presults during evaluation. *)
Definition liftpr {A B:Type} (f:A->B) (pr:presult A) : presult B
:= match pr with
| TerminalError => TerminalError
| RecoverableError => RecoverableError
| Success a => Success (f a)
end.
Definition bindpr {A B:Type} (pr:presult A) (f:A->presult B) : presult B
:= match pr with
| TerminalError => TerminalError
| RecoverableError => RecoverableError
| Success a => (f a)
end.
Lemma liftpr_bindpr {A B:Type} (f:A->B) pr :
liftpr f pr = bindpr pr (fun x => Success (f x)).
Proof.
destruct pr; simpl; trivial.
Qed.
(** Accumulates successful evaluation, skipping match failures. A terminal error is always final. *)
Fixpoint gather_successes {A:Type} (os:list (presult A)) : presult (list A)
:= match os with
| nil => Success nil
| (TerminalError)::xs => TerminalError
| (RecoverableError)::xs => gather_successes xs
| (Success a)::xs => liftpr (cons a) (gather_successes xs)
end.
(** Accumulates successful evaluation, but propagating match failure to the top *)
Definition enforce_successes {A:Type} (os:list (presult A)) : presult (list A)
:= match os with
| nil => Success nil
| (TerminalError)::xs => TerminalError
| (RecoverableError)::xs => RecoverableError
| (Success a)::xs => liftpr (cons a) (gather_successes xs)
end.
Definition op2tpr {A:Type} (o:option A) : presult A
:= match o with
| None => TerminalError
| Some x => Success x
end.
Definition op2rpr {A:Type} (o:option A) : presult A
:= match o with
| None => RecoverableError
| Some x => Success x
end.
Section Debug.
(* If we were reasoning about this formally, we would want to use a proper
one-hole context. Since we are not, a trail of choices suffices *)
Definition camp_src_path
:= list nat.
Inductive presult_debug A :=
| TerminalError_debug (s:string) (loc:camp_src_path) : presult_debug A
| RecoverableError_debug (s:string) : presult_debug A
| Success_debug (res:A) : presult_debug A.
(* begin hide *)
Arguments TerminalError_debug {A} s loc.
Arguments RecoverableError_debug {A} s.
Arguments Success_debug {A} res.
(* end hide *)
(* Not a ToString instance since it requires the top level pattern *)
Definition print_presult_debug {A} {B} {tos:ToString A} (p:B)
(pPrint:B -> camp_src_path -> string) (pr:presult_debug A)
:= match pr with
| TerminalError_debug s loc => "TerminalError: " ++ s ++ ". This error occurred in the bracketed code: \n" ++ (pPrint p (rev loc))
| RecoverableError_debug s => "RecoverableError: " ++ s
| Success_debug res => "Success: " ++ toString res
end.
(** Useful lifting functions used in the evaluation of patterns. Used to handle the various possible presults *)
Definition liftpr_debug {A B:Type} (f:A->B) (pr:presult_debug A) : presult_debug B
:= match pr with
| TerminalError_debug s loc => TerminalError_debug s loc
| RecoverableError_debug s => RecoverableError_debug s
| Success_debug a => Success_debug (f a)
end.
Definition bindpr_debug {A B:Type} (pr:presult_debug A) (f:A->presult_debug B) : presult_debug B
:= match pr with
| TerminalError_debug s loc => TerminalError_debug s loc
| RecoverableError_debug s => RecoverableError_debug s
| Success_debug a => (f a)
end.
Lemma liftpr_debug_bindpr_debug {A B:Type} (f:A->B) pr :
liftpr_debug f pr = bindpr_debug pr (fun x => Success_debug (f x)).
Proof.
destruct pr; simpl; trivial.
Qed.
Fixpoint gather_successes_debug {A:Type} (os:list (presult_debug A)) : presult_debug (list A)
:= match os with
| nil => Success_debug nil
| (TerminalError_debug s loc)::xs => TerminalError_debug s loc
| (RecoverableError_debug s)::xs => gather_successes_debug xs
| (Success_debug a)::xs => liftpr_debug (cons a) (gather_successes_debug xs)
end.
Definition enforce_successes_debug {A:Type} (os:list (presult_debug A)) : presult_debug (list A)
:= match os with
| nil => Success_debug nil
| (TerminalError_debug s loc)::xs => TerminalError_debug s loc
| (RecoverableError_debug s)::xs => RecoverableError_debug s
| (Success_debug a)::xs => liftpr_debug (cons a) (gather_successes_debug xs)
end.
Definition op2tpr_debug {A:Type} (err:string) (loc:camp_src_path) (o:option A) : presult_debug A
:= match o with
| None => TerminalError_debug err loc
| Some x => Success_debug x
end.
Definition op2rpr_debug {A:Type} (err:string) (o:option A) : presult_debug A
:= match o with
| None => RecoverableError_debug err
| Some x => Success_debug x
end.
Definition presult_same {A} (res:presult A) (res_debug:presult_debug A) :=
match res, res_debug with
| TerminalError, TerminalError_debug _ _ => True
| RecoverableError, RecoverableError_debug _ => True
| Success x, Success_debug y => x = y
| _, _ => False
end.
Lemma liftpr_presult_same {A B} (f:A->B) d1 d2 :
presult_same d1 d2 ->
presult_same (liftpr f d1) (liftpr_debug f d2).
Proof.
unfold presult_same.
destruct d1; destruct d2; simpl; congruence.
Qed.
Lemma gather_successes_presult_same {A} d1 d2 :
Forall2 (@presult_same A) d1 d2 ->
presult_same (gather_successes d1) (gather_successes_debug d2).
Proof.
unfold presult_same.
induction 1; simpl; trivial.
destruct x; destruct y; destruct (gather_successes l); destruct (gather_successes_debug l'); simpl in *; subst; intuition.
Qed.
Lemma bindpr_presult_same {A B} d1 d2 f1 f2:
presult_same d1 d2 ->
(forall x, presult_same (f1 x) (f2 x)) ->
presult_same (@bindpr A B d1 f1) (bindpr_debug d2 f2).
Proof.
destruct d1; destruct d2; simpl in *; try tauto.
intros; subst; auto.
Qed.
End Debug.
(** Maps the input/output(s) between NNRC and CAMP *)
Definition pr2op {A:Type} (pr:presult A) : option A
:= match pr with
| Success a => Some a
| _ => None
end.
Lemma pr2op_op2tpr {A:Type} (op:option A) :
pr2op (op2tpr op) = op.
Proof.
destruct op; trivial.
Qed.
Lemma pr2op_op2rpr {A:Type} (op:option A) :
pr2op (op2rpr op) = op.
Proof.
destruct op; trivial.
Qed.
Definition isRecoverableError {A:Type} (pr:presult A)
:= match pr with
| RecoverableError => true
| _ => false
end.
Lemma op2tpr_not_recoverable {A:Type} (op:option A) :
isRecoverableError (op2tpr op) = false.
Proof.
destruct op; trivial.
Qed.
Lemma isRecoverableError_liftpr {A B:Type} (f:A->B) (pr:presult A)
: isRecoverableError (liftpr f pr) = isRecoverableError pr.
Proof.
destruct pr; trivial.
Qed.
End CAMPUtil.
(* begin hide *)
Arguments TerminalError {A}.
Arguments RecoverableError {A}.
Arguments Success {A} res.
Arguments TerminalError {A}.
Arguments RecoverableError {A}.
Arguments Success {A} res.
Arguments TerminalError_debug {A} s loc.
Arguments RecoverableError_debug {A} s.
Arguments Success_debug {A} res.
(* end hide *)
|
module ascii (
input clk,
input scan_ready,
input [7:0] scan_code,
output [7:0] ascii
);
reg [7:0] r_ascii;
reg [1:0] scan_ready_edge_detect = 2'b00;
assign ascii = r_ascii;
//reg keyup = 0;
reg extended = 0;
reg shift = 0;
reg [1:0] caps = 2'b00;
wire caps_lock;
reg [7:0] code;
reg [7:0] key_code [2:0];
reg [1:0] key_mem_index = 2'b00;
reg [1:0] key_current_index = 2'b00;
reg key_clear = 0;
reg [7:0] current_code;
reg [7:0] break_code;
reg [7:0] state_code;
reg [2:0] state_reg = 2'b00;
// state machine parameters
parameter st_idle = 3'b000;
parameter st_code_1 = 3'b001;
parameter st_code_2 = 3'b010;
parameter st_code_3 = 3'b011;
parameter st_break = 3'b100;
parameter st_extended = 3'b101;
parameter st_ready = 3'b110;
assign caps_lock = caps[0]; // odd number of presses
// posedge of the ps2 clock
always @(posedge clk) begin
scan_ready_edge_detect <= {scan_ready_edge_detect[0], scan_ready};
end
always @(posedge clk) begin
case (state_reg)
st_idle:
begin
if (scan_ready_edge_detect == 2'b01) begin
current_code <= scan_code;
state_reg <= st_code_1;
end
end
st_code_1:
begin
state_code <= current_code;
state_reg <= st_code_2;
end
st_code_2:
begin
// break code
if (state_code == 8'hf0) begin
state_reg <= st_break;
end else begin
state_reg <= st_code_3;
end
end
st_code_3:
begin
state_reg <= st_ready;
end
st_break:
begin
// key up
code <= 8'h00;
if (scan_ready_edge_detect == 2'b01) begin
state_reg <= st_idle;
break_code <= scan_code;
end
end
st_extended:
begin
end
st_ready:
begin
code <= state_code;
state_reg <= st_idle;
end
default:
begin
end
endcase
end
// Caps lock
always @(posedge clk) begin
if (scan_ready_edge_detect == 2'b01 && code == 8'h58) begin
caps <= caps + 2'b1;
end
end
// LEFT SHIFT || RIGHT SHIFT
always @(posedge clk) begin
if (code == 8'h12 || code == 8'h59) begin
shift <= 1;
end else if (break_code == 8'h12 || break_code == 8'h59) begin
shift <= 0;
end
end
always @(posedge clk) begin
if (extended) begin
//extended <= 0;
case (code)
// nand2tetris special codes
8'h6b: r_ascii <= 8'd130; // L ARROW
8'h75: r_ascii <= 8'd131; // UP ARROW
8'h74: r_ascii <= 8'd132; // R ARROW
8'h72: r_ascii <= 8'd133; // DOWN ARROW
8'h6c: r_ascii <= 8'd134; // HOME
8'h69: r_ascii <= 8'd135; // END
8'h7d: r_ascii <= 8'd136; // PAGE UP
8'h7a: r_ascii <= 8'd137; // PAGE DOWN
8'h70: r_ascii <= 8'd138; // INSERT
8'h71: r_ascii <= 8'd139; // DELETE
default: r_ascii <= 8'd0; // null
endcase
end else
if ((shift && !caps_lock) || (caps_lock && !shift)) begin
case (code)
8'h29: r_ascii <= 8'd32; // [space]
8'h16: r_ascii <= 8'd33; // !
8'h52: r_ascii <= 8'd34; // "
8'h26: r_ascii <= 8'd35; // #
8'h25: r_ascii <= 8'd36; // $
8'h2e: r_ascii <= 8'd37; // %
8'h3d: r_ascii <= 8'd38; // &
8'h46: r_ascii <= 8'd40; // (
8'h45: r_ascii <= 8'd41; // )
8'h3e: r_ascii <= 8'd42; // *
8'h55: r_ascii <= 8'd43; // +
8'h4c: r_ascii <= 8'd58; // :
8'h41: r_ascii <= 8'd60; // <
8'h49: r_ascii <= 8'd62; // >
8'h4a: r_ascii <= 8'd63; // ?
8'h1e: r_ascii <= 8'd64; // @
8'h1c: r_ascii <= 8'd65; // A
8'h32: r_ascii <= 8'd66; // B
8'h21: r_ascii <= 8'd67; // C
8'h23: r_ascii <= 8'd68; // D
8'h24: r_ascii <= 8'd69; // E
8'h2b: r_ascii <= 8'd70; // F
8'h34: r_ascii <= 8'd71; // G
8'h33: r_ascii <= 8'd72; // H
8'h43: r_ascii <= 8'd73; // I
8'h3b: r_ascii <= 8'd74; // J
8'h42: r_ascii <= 8'd75; // K
8'h4b: r_ascii <= 8'd76; // L
8'h3a: r_ascii <= 8'd77; // M
8'h31: r_ascii <= 8'd78; // N
8'h44: r_ascii <= 8'd79; // O
8'h4d: r_ascii <= 8'd80; // P
8'h15: r_ascii <= 8'd81; // Q
8'h2d: r_ascii <= 8'd82; // R
8'h1b: r_ascii <= 8'd83; // S
8'h2c: r_ascii <= 8'd84; // T
8'h3c: r_ascii <= 8'd85; // U
8'h2a: r_ascii <= 8'd86; // V
8'h1d: r_ascii <= 8'd87; // W
8'h22: r_ascii <= 8'd88; // X
8'h35: r_ascii <= 8'd89; // Y
8'h1a: r_ascii <= 8'd90; // Z
8'h36: r_ascii <= 8'd94; // ^
8'h4e: r_ascii <= 8'd95; // _
8'h54: r_ascii <= 8'd123; // {
8'h5d: r_ascii <= 8'd124; // |
8'h5b: r_ascii <= 8'd125; // }
8'h0e: r_ascii <= 8'd126; // ~
default: r_ascii <= 8'd0; // null
endcase
end else begin
case (code)
8'h0d: r_ascii <= 8'd9; // [tab]
//8'h14: r_ascii <= L CTRL
//8'h11: r_ascii <= L ALT
//8'h7e: r_ascii <= SCROLL
//8'h77: r_ascii <= NUM
8'h29: r_ascii <= 8'd32; // [space]
8'h52: r_ascii <= 8'd39; // '
8'h7c: r_ascii <= 8'd42; // KP *
8'h79: r_ascii <= 8'd43; // KP +
8'h41: r_ascii <= 8'd44; // ,
8'h49: r_ascii <= 8'd46; // .
8'h71: r_ascii <= 8'd46; // KP .
8'h4e: r_ascii <= 8'd45; // -
8'h7b: r_ascii <= 8'd45; // KP -
8'h4a: r_ascii <= 8'd47; // /
8'h45: r_ascii <= 8'd48; // 0
8'h70: r_ascii <= 8'd48; // KP 0
8'h16: r_ascii <= 8'd49; // 1
8'h69: r_ascii <= 8'd49; // KP 1
8'h1e: r_ascii <= 8'd50; // 2
8'h72: r_ascii <= 8'd50; // KP 2
8'h26: r_ascii <= 8'd51; // 3
8'h7a: r_ascii <= 8'd51; // KP 3
8'h25: r_ascii <= 8'd52; // 4
8'h6b: r_ascii <= 8'd52; // KP 4
8'h2e: r_ascii <= 8'd53; // 5
8'h73: r_ascii <= 8'd53; // KP 5
8'h36: r_ascii <= 8'd54; // 6
8'h74: r_ascii <= 8'd54; // KP 6
8'h3d: r_ascii <= 8'd55; // 7
8'h6c: r_ascii <= 8'd55; // KP 7
8'h3e: r_ascii <= 8'd56; // 8
8'h75: r_ascii <= 8'd56; // KP 8
8'h46: r_ascii <= 8'd57; // 9
8'h7d: r_ascii <= 8'd57; // KP 9
8'h4c: r_ascii <= 8'd59; // ;
8'h55: r_ascii <= 8'd61; // =
8'h54: r_ascii <= 8'd91; // [
8'h5d: r_ascii <= 8'd92; // \
8'h5b: r_ascii <= 8'd93; // ]
8'h0e: r_ascii <= 8'd96; // `
8'h1c: r_ascii <= 8'd97; // a
8'h32: r_ascii <= 8'd98; // b
8'h21: r_ascii <= 8'd99; // c
8'h23: r_ascii <= 8'd100; // d
8'h24: r_ascii <= 8'd101; // e
8'h2b: r_ascii <= 8'd102; // f
8'h34: r_ascii <= 8'd103; // g
8'h33: r_ascii <= 8'd104; // h
8'h43: r_ascii <= 8'd105; // i
8'h3b: r_ascii <= 8'd106; // j
8'h42: r_ascii <= 8'd107; // k
8'h4b: r_ascii <= 8'd108; // l
8'h3a: r_ascii <= 8'd109; // m
8'h31: r_ascii <= 8'd110; // n
8'h44: r_ascii <= 8'd111; // o
8'h4d: r_ascii <= 8'd112; // p
8'h15: r_ascii <= 8'd113; // q
8'h2d: r_ascii <= 8'd114; // r
8'h1b: r_ascii <= 8'd115; // s
8'h2c: r_ascii <= 8'd116; // t
8'h3c: r_ascii <= 8'd117; // u
8'h2a: r_ascii <= 8'd118; // v
8'h1d: r_ascii <= 8'd119; // w
8'h22: r_ascii <= 8'd120; // x
8'h35: r_ascii <= 8'd121; // y
8'h1a: r_ascii <= 8'd122; // z
// nand2tetris special codes
8'h5a: r_ascii <= 8'd128; // [enter]
8'h66: r_ascii <= 8'd129; // [back space]
8'h76: r_ascii <= 8'd140; // ESCAPE
8'h05: r_ascii <= 8'd141; // F1
8'h06: r_ascii <= 8'd142; // F2
8'h04: r_ascii <= 8'd143; // F3
8'h0c: r_ascii <= 8'd144; // F4
8'h03: r_ascii <= 8'd145; // F5
8'h0b: r_ascii <= 8'd146; // F6
8'h83: r_ascii <= 8'd147; // F7
8'h0a: r_ascii <= 8'd148; // F8
8'h01: r_ascii <= 8'd149; // F9
8'h09: r_ascii <= 8'd150; // F10
8'h78: r_ascii <= 8'd151; // F11
8'h07: r_ascii <= 8'd152; // F12
default: r_ascii <= 8'd0; // null
endcase
end
end
endmodule
|
//local memory controller
module lmcnt
(
input CLK,
input RESET_X,
//cpu
input SOFT_RESET,
input START,
output reg FINISH,
input [1:0] MSEL_INPUTA_SEL,
input [1:0] MSEL_INPUTB_SEL,
input [1:0] MSEL_OUTPUTC_SEL,
input [9:0] M1POS,
input [9:0] M1SIZE,
input [9:0] M2POS,
input [9:0] M3POS,
//local mem
input [7:0] M0_RDATA,
output M1_WR,
output [9:0] M1_WADR,
output [7:0] M1_WDATA,
output [9:0] M1_RADR,
input [7:0] M1_RDATA,
output M2_WR,
output [9:0] M2_WADR,
output [7:0] M2_WDATA,
output [9:0] M2_RADR,
input [7:0] M2_RDATA,
output M3_WR,
output [9:0] M3_WADR,
output [7:0] M3_WDATA,
output [9:0] M3_RADR,
input [7:0] M3_RDATA,
//npu
output reg NPU_EN,
output reg [7:0] A_RDATA,
output reg [7:0] B_RDATA,
input LM_EN,
input [7:0] C_WDATA
);
wire rst_x;
assign rst_x = RESET_X & ~SOFT_RESET;
reg npu_en_r;
wire npu_en_w;
assign npu_en_w = START | npu_en_r;
reg [9:0] rcnt;
reg [9:0] wcnt;
always @ (posedge CLK or negedge rst_x)begin
if (rst_x == 0)begin
rcnt <= 0;
end else begin
if ((rcnt == 0) && (START == 1))begin
rcnt <= 1;
end else if((rcnt != 0) && (rcnt != 10'h3FF))begin
rcnt <= rcnt + 1;
end
end
end
always @ (posedge CLK or negedge rst_x)begin
if (rst_x == 0)begin
NPU_EN <= 0;
npu_en_r <= 0;
end else begin
NPU_EN <= npu_en_w;
if (START == 1)begin
npu_en_r <= 1;
end else if(rcnt == 10'h3FF)begin
npu_en_r <= 0;
end
end
end
always @ (posedge CLK or negedge rst_x)begin
if (rst_x == 0)begin
wcnt <= 0;
end else begin
if(LM_EN)begin
wcnt <= wcnt + 1;
end
end
end
always @ (posedge CLK or negedge rst_x)begin
if (rst_x == 0)begin
FINISH <= 0;
end else begin
if(wcnt == 10'h3FF)begin
FINISH <= 1;
end
end
end
//read
assign M1_RADR = rcnt;
assign M2_RADR = rcnt;
assign M3_RADR = rcnt;
always @ (posedge CLK or negedge rst_x)begin
if (rst_x == 0)begin
A_RDATA <= 0;
end else begin
case (MSEL_INPUTA_SEL)
2'b00: A_RDATA <= M0_RDATA;
2'b01: A_RDATA <= M1_RDATA;
2'b10: A_RDATA <= M2_RDATA;
2'b11: A_RDATA <= M3_RDATA;
endcase // case (MSEL_INPUTA_SEL)
end
end
always @ (posedge CLK or negedge rst_x)begin
if (rst_x == 0)begin
B_RDATA <= 0;
end else begin
case (MSEL_INPUTB_SEL)
2'b00: B_RDATA <= M0_RDATA;
2'b01: B_RDATA <= M1_RDATA;
2'b10: B_RDATA <= M2_RDATA;
2'b11: B_RDATA <= M3_RDATA;
endcase // case (MSEL_INPUTB_SEL)
end
end
//write
assign M1_WR = (MSEL_OUTPUTC_SEL == 2'b01) ? LM_EN : 0;
assign M2_WR = (MSEL_OUTPUTC_SEL == 2'b10) ? LM_EN : 0;
assign M3_WR = (MSEL_OUTPUTC_SEL == 2'b11) ? LM_EN : 0;
assign M1_WADR = wcnt;
assign M2_WADR = wcnt;
assign M3_WADR = wcnt;
assign M1_WDATA = C_WDATA;
assign M2_WDATA = C_WDATA;
assign M3_WDATA = C_WDATA;
endmodule // lmcnt
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND3B_LP_V
`define SKY130_FD_SC_LP__NAND3B_LP_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog wrapper for nand3b with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand3b_lp (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand3b_lp (
Y ,
A_N,
B ,
C
);
output Y ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND3B_LP_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_3_gt_top.v
// Version : 1.3
//-- Description: GTX module for 7-series Integrated PCIe Block
//--
//--
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module pcie_7x_v1_3_gt_top #
(
parameter LINK_CAP_MAX_LINK_WIDTH = 8, // 1 - x1 , 2 - x2 , 4 - x4 , 8 - x8
parameter REF_CLK_FREQ = 0, // 0 - 100 MHz , 1 - 125 MHz , 2 - 250 MHz
parameter USER_CLK2_DIV2 = "FALSE", // "FALSE" => user_clk2 = user_clk
// "TRUE" => user_clk2 = user_clk/2, where user_clk = 500 or 250 MHz.
parameter integer USER_CLK_FREQ = 3, // 0 - 31.25 MHz , 1 - 62.5 MHz , 2 - 125 MHz , 3 - 250 MHz , 4 - 500Mhz
parameter PL_FAST_TRAIN = "FALSE", // Simulation Speedup
parameter PCIE_EXT_CLK = "FALSE", // Use External Clocking
parameter PCIE_USE_MODE = "1.0" // 1.0 = K325T IES, 1.1 = VX485T IES, 3.0 = K325T GES
)
(
//-----------------------------------------------------------------------------------------------------------------//
// pl ltssm
input wire [5:0] pl_ltssm_state ,
// Pipe Per-Link Signals
input wire pipe_tx_rcvr_det ,
input wire pipe_tx_reset ,
input wire pipe_tx_rate ,
input wire pipe_tx_deemph ,
input wire [2:0] pipe_tx_margin ,
input wire pipe_tx_swing ,
//-----------------------------------------------------------------------------------------------------------------//
// Clock Inputs //
//-----------------------------------------------------------------------------------------------------------------//
input PIPE_PCLK_IN,
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PIPE_RXUSRCLK_IN,
input PIPE_RXOUTCLK_IN,
input PIPE_DCLK_IN,
input PIPE_USERCLK1_IN,
input PIPE_USERCLK2_IN,
input PIPE_OOBCLK_IN,
input PIPE_MMCM_LOCK_IN,
output PIPE_TXOUTCLK_OUT,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PIPE_RXOUTCLK_OUT,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PIPE_PCLK_SEL_OUT,
output PIPE_GEN3_OUT,
// Pipe Per-Lane Signals - Lane 0
output wire [ 1:0] pipe_rx0_char_is_k ,
output wire [15:0] pipe_rx0_data ,
output wire pipe_rx0_valid ,
output wire pipe_rx0_chanisaligned ,
output wire [ 2:0] pipe_rx0_status ,
output wire pipe_rx0_phy_status ,
output wire pipe_rx0_elec_idle ,
input wire pipe_rx0_polarity ,
input wire pipe_tx0_compliance ,
input wire [ 1:0] pipe_tx0_char_is_k ,
input wire [15:0] pipe_tx0_data ,
input wire pipe_tx0_elec_idle ,
input wire [ 1:0] pipe_tx0_powerdown ,
// Pipe Per-Lane Signals - Lane 1
output wire [ 1:0] pipe_rx1_char_is_k ,
output wire [15:0] pipe_rx1_data ,
output wire pipe_rx1_valid ,
output wire pipe_rx1_chanisaligned ,
output wire [ 2:0] pipe_rx1_status ,
output wire pipe_rx1_phy_status ,
output wire pipe_rx1_elec_idle ,
input wire pipe_rx1_polarity ,
input wire pipe_tx1_compliance ,
input wire [ 1:0] pipe_tx1_char_is_k ,
input wire [15:0] pipe_tx1_data ,
input wire pipe_tx1_elec_idle ,
input wire [ 1:0] pipe_tx1_powerdown ,
// Pipe Per-Lane Signals - Lane 2
output wire [ 1:0] pipe_rx2_char_is_k ,
output wire [15:0] pipe_rx2_data ,
output wire pipe_rx2_valid ,
output wire pipe_rx2_chanisaligned ,
output wire [ 2:0] pipe_rx2_status ,
output wire pipe_rx2_phy_status ,
output wire pipe_rx2_elec_idle ,
input wire pipe_rx2_polarity ,
input wire pipe_tx2_compliance ,
input wire [ 1:0] pipe_tx2_char_is_k ,
input wire [15:0] pipe_tx2_data ,
input wire pipe_tx2_elec_idle ,
input wire [ 1:0] pipe_tx2_powerdown ,
// Pipe Per-Lane Signals - Lane 3
output wire [ 1:0] pipe_rx3_char_is_k ,
output wire [15:0] pipe_rx3_data ,
output wire pipe_rx3_valid ,
output wire pipe_rx3_chanisaligned ,
output wire [ 2:0] pipe_rx3_status ,
output wire pipe_rx3_phy_status ,
output wire pipe_rx3_elec_idle ,
input wire pipe_rx3_polarity ,
input wire pipe_tx3_compliance ,
input wire [ 1:0] pipe_tx3_char_is_k ,
input wire [15:0] pipe_tx3_data ,
input wire pipe_tx3_elec_idle ,
input wire [ 1:0] pipe_tx3_powerdown ,
// Pipe Per-Lane Signals - Lane 4
output wire [ 1:0] pipe_rx4_char_is_k ,
output wire [15:0] pipe_rx4_data ,
output wire pipe_rx4_valid ,
output wire pipe_rx4_chanisaligned ,
output wire [ 2:0] pipe_rx4_status ,
output wire pipe_rx4_phy_status ,
output wire pipe_rx4_elec_idle ,
input wire pipe_rx4_polarity ,
input wire pipe_tx4_compliance ,
input wire [ 1:0] pipe_tx4_char_is_k ,
input wire [15:0] pipe_tx4_data ,
input wire pipe_tx4_elec_idle ,
input wire [ 1:0] pipe_tx4_powerdown ,
// Pipe Per-Lane Signals - Lane 5
output wire [ 1:0] pipe_rx5_char_is_k ,
output wire [15:0] pipe_rx5_data ,
output wire pipe_rx5_valid ,
output wire pipe_rx5_chanisaligned ,
output wire [ 2:0] pipe_rx5_status ,
output wire pipe_rx5_phy_status ,
output wire pipe_rx5_elec_idle ,
input wire pipe_rx5_polarity ,
input wire pipe_tx5_compliance ,
input wire [ 1:0] pipe_tx5_char_is_k ,
input wire [15:0] pipe_tx5_data ,
input wire pipe_tx5_elec_idle ,
input wire [ 1:0] pipe_tx5_powerdown ,
// Pipe Per-Lane Signals - Lane 6
output wire [ 1:0] pipe_rx6_char_is_k ,
output wire [15:0] pipe_rx6_data ,
output wire pipe_rx6_valid ,
output wire pipe_rx6_chanisaligned ,
output wire [ 2:0] pipe_rx6_status ,
output wire pipe_rx6_phy_status ,
output wire pipe_rx6_elec_idle ,
input wire pipe_rx6_polarity ,
input wire pipe_tx6_compliance ,
input wire [ 1:0] pipe_tx6_char_is_k ,
input wire [15:0] pipe_tx6_data ,
input wire pipe_tx6_elec_idle ,
input wire [ 1:0] pipe_tx6_powerdown ,
// Pipe Per-Lane Signals - Lane 7
output wire [ 1:0] pipe_rx7_char_is_k ,
output wire [15:0] pipe_rx7_data ,
output wire pipe_rx7_valid ,
output wire pipe_rx7_chanisaligned ,
output wire [ 2:0] pipe_rx7_status ,
output wire pipe_rx7_phy_status ,
output wire pipe_rx7_elec_idle ,
input wire pipe_rx7_polarity ,
input wire pipe_tx7_compliance ,
input wire [ 1:0] pipe_tx7_char_is_k ,
input wire [15:0] pipe_tx7_data ,
input wire pipe_tx7_elec_idle ,
input wire [ 1:0] pipe_tx7_powerdown ,
// PCI Express signals
output wire [ (LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_txn ,
output wire [ (LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_txp ,
input wire [ (LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_rxn ,
input wire [ (LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_rxp ,
// Non PIPE signals
input wire sys_clk ,
input wire sys_rst_n ,
output wire pipe_clk ,
output wire user_clk ,
output wire user_clk2 ,
output wire phy_rdy_n
);
parameter TCQ = 1; // clock to out delay model
localparam USERCLK2_FREQ = (USER_CLK2_DIV2 == "TRUE") ? (USER_CLK_FREQ == 4) ? 3 :
(USER_CLK_FREQ == 3) ? 2 : USER_CLK_FREQ
: USER_CLK_FREQ;
wire [ 7:0] gt_rx_phy_status_wire ;
wire [ 7:0] gt_rxchanisaligned_wire ;
wire [ 31:0] gt_rx_data_k_wire ;
wire [255:0] gt_rx_data_wire ;
wire [ 7:0] gt_rx_elec_idle_wire ;
wire [ 23:0] gt_rx_status_wire ;
wire [ 7:0] gt_rx_valid_wire ;
wire [ 7:0] gt_rx_polarity ;
wire [ 15:0] gt_power_down ;
wire [ 7:0] gt_tx_char_disp_mode ;
wire [ 31:0] gt_tx_data_k ;
wire [255:0] gt_tx_data ;
wire gt_tx_detect_rx_loopback ;
wire [ 7:0] gt_tx_elec_idle ;
wire [ 7:0] gt_rx_elec_idle_reset ;
wire [LINK_CAP_MAX_LINK_WIDTH-1:0] plllkdet ;
wire [LINK_CAP_MAX_LINK_WIDTH-1:0] phystatus_rst ;
wire clock_locked ;
wire [ 7:0] gt_rx_phy_status_wire_filter ;
wire [ 31:0] gt_rx_data_k_wire_filter ;
wire [255:0] gt_rx_data_wire_filter ;
wire [ 7:0] gt_rx_elec_idle_wire_filter ;
wire [ 23:0] gt_rx_status_wire_filter ;
wire [ 7:0] gt_rx_valid_wire_filter ;
wire pipe_clk_int;
wire phy_rdy_n_int;
reg [5:0] pl_ltssm_state_q;
always @(posedge pipe_clk_int or negedge clock_locked) begin
if (!clock_locked)
pl_ltssm_state_q <= #TCQ 6'b0;
else
pl_ltssm_state_q <= #TCQ pl_ltssm_state;
end
assign pipe_clk = pipe_clk_int ;
wire plm_in_l0 = (pl_ltssm_state_q == 6'h16);
wire plm_in_rl = (pl_ltssm_state_q == 6'h1c);
wire plm_in_dt = (pl_ltssm_state_q == 6'h2d);
wire plm_in_rs = (pl_ltssm_state_q == 6'h1f);
//-------------RX FILTER Instantiation----------------------------------------------------------//
genvar i;
generate for (i=0; i<LINK_CAP_MAX_LINK_WIDTH; i=i+1)
begin : gt_rx_valid_filter
pcie_7x_v1_3_gt_rx_valid_filter_7x # (
.CLK_COR_MIN_LAT(28)
)
GT_RX_VALID_FILTER_7x_inst (
.USER_RXCHARISK ( gt_rx_data_k_wire [(2*i)+1 + (2*i):(2*i)+ (2*i)] ), //O
.USER_RXDATA ( gt_rx_data_wire [(16*i)+15+(16*i) :(16*i)+0 + (16*i)] ), //O
.USER_RXVALID ( gt_rx_valid_wire [i] ), //O
.USER_RXELECIDLE ( gt_rx_elec_idle_wire [i] ), //O
.USER_RX_STATUS ( gt_rx_status_wire [(3*i)+2:(3*i)] ), //O
.USER_RX_PHY_STATUS ( gt_rx_phy_status_wire [i] ), //O
.GT_RXCHARISK ( gt_rx_data_k_wire_filter [(2*i)+1+ (2*i):2*i+ (2*i)] ), //I
.GT_RXDATA ( gt_rx_data_wire_filter [(16*i)+15+(16*i) :(16*i)+0+(16*i)] ), //I
.GT_RXVALID ( gt_rx_valid_wire_filter [i] ), //I
.GT_RXELECIDLE ( gt_rx_elec_idle_wire_filter [i] ), //I
.GT_RX_STATUS ( gt_rx_status_wire_filter [(3*i)+2:(3*i)] ), //I
.GT_RX_PHY_STATUS ( gt_rx_phy_status_wire_filter [i] ),
.PLM_IN_L0 ( plm_in_l0 ), //I
.PLM_IN_RS ( plm_in_rs ), //I
.USER_CLK ( pipe_clk_int ), //I
.RESET ( phy_rdy_n_int ) //I
);
end
endgenerate
//---------- GT Instantiation ---------------------------------------------------------------
pcie_7x_v1_3_pipe_wrapper #
(
.PCIE_SIM_MODE ( PL_FAST_TRAIN ),
.PCIE_EXT_CLK ( PCIE_EXT_CLK ),
.PCIE_TXBUF_EN ( "FALSE" ),
.PCIE_CHAN_BOND ( 0 ),
.PCIE_PLL_SEL ( "CPLL" ),
.PCIE_USE_MODE ( PCIE_USE_MODE ),
`ifdef SIMULATION
.PCIE_LPM_DFE ( "DFE" ),
`else
.PCIE_LPM_DFE ( "LPM" ),
`endif
.PCIE_LANE ( LINK_CAP_MAX_LINK_WIDTH ),
`ifdef SIMULATION
.PCIE_LINK_SPEED ( 2 ),
`else
.PCIE_LINK_SPEED ( 3 ),
`endif
.PCIE_REFCLK_FREQ ( REF_CLK_FREQ ),
.PCIE_USERCLK1_FREQ ( USER_CLK_FREQ +1 ),
.PCIE_USERCLK2_FREQ ( USERCLK2_FREQ +1 )
) pipe_wrapper_i (
//---------- PIPE Clock & Reset Ports ------------------
.PIPE_CLK ( sys_clk ),
.PIPE_RESET_N ( sys_rst_n ),
.PIPE_PCLK ( pipe_clk_int ),
//---------- PIPE TX Data Ports ------------------
.PIPE_TXDATA ( gt_tx_data[((32*LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_TXDATAK ( gt_tx_data_k[((4*LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_TXP ( pci_exp_txp[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_TXN ( pci_exp_txn[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
//---------- PIPE RX Data Ports ------------------
.PIPE_RXP ( pci_exp_rxp[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXN ( pci_exp_rxn[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXDATA ( gt_rx_data_wire_filter[((32*LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXDATAK ( gt_rx_data_k_wire_filter[((4*LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
//---------- PIPE Command Ports ------------------
.PIPE_TXDETECTRX ( gt_tx_detect_rx_loopback ),
.PIPE_TXELECIDLE ( gt_tx_elec_idle[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_TXCOMPLIANCE ( gt_tx_char_disp_mode[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXPOLARITY ( gt_rx_polarity[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_POWERDOWN ( gt_power_down[((2*LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RATE ( {1'b0,pipe_tx_rate} ),
//---------- PIPE Electrical Command Ports ------------------
.PIPE_TXMARGIN ( pipe_tx_margin[2] ),
.PIPE_TXSWING ( pipe_tx_swing ),
.PIPE_TXDEEMPH ( {1*LINK_CAP_MAX_LINK_WIDTH{{5'd0,pipe_tx_deemph}}} ),
.PIPE_TXEQ_CONTROL ( {2*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_TXEQ_PRESET ( {4*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_TXEQ_PRESET_DEFAULT ( {4*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_RXEQ_CONTROL ( {2*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_RXEQ_PRESET ( {4*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_RXEQ_LFFS ( {6*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_RXEQ_TXPRESET ( {4*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_TXEQ_FS ( ),
.PIPE_TXEQ_LF ( ),
.PIPE_TXEQ_DEEMPH ( ),
.PIPE_TXEQ_DONE ( ),
.PIPE_RXEQ_NEW_TXCOEFF ( ),
.PIPE_RXEQ_LFFS_SEL ( ),
.PIPE_RXEQ_ADAPT_DONE ( ),
.PIPE_RXEQ_DONE ( ),
//---------- PIPE Status Ports -------------------
.PIPE_RXVALID ( gt_rx_valid_wire_filter[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_PHYSTATUS ( gt_rx_phy_status_wire_filter[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_PHYSTATUS_RST ( phystatus_rst ),
.PIPE_RXELECIDLE ( gt_rx_elec_idle_wire_filter[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXSTATUS ( gt_rx_status_wire_filter[((3*LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXBUFSTATUS ( ),
//---------- PIPE User Ports ---------------------------
.PIPE_RXSLIDE ( {1*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_CPLL_LOCK ( plllkdet ),
.PIPE_QPLL_LOCK ( ),
.PIPE_PCLK_LOCK ( clock_locked ),
.PIPE_RXCDRLOCK ( ),
.PIPE_USERCLK1 ( user_clk ),
.PIPE_USERCLK2 ( user_clk2 ),
.PIPE_RXUSRCLK ( ),
.PIPE_RXOUTCLK ( ),
.PIPE_TXSYNC_DONE ( ),
.PIPE_RXSYNC_DONE ( ),
.PIPE_GEN3_RDY ( ),
.PIPE_RXCHANISALIGNED ( gt_rxchanisaligned_wire ),
.PIPE_ACTIVE_LANE ( ),
//---------- External Clock Ports ---------------------------
.PIPE_PCLK_IN ( PIPE_PCLK_IN ),
.PIPE_RXUSRCLK_IN ( PIPE_RXUSRCLK_IN ),
.PIPE_RXOUTCLK_IN ( PIPE_RXOUTCLK_IN ),
.PIPE_DCLK_IN ( PIPE_DCLK_IN ),
.PIPE_USERCLK1_IN ( PIPE_USERCLK1_IN ),
.PIPE_USERCLK2_IN ( PIPE_USERCLK2_IN ),
.PIPE_MMCM_LOCK_IN ( PIPE_MMCM_LOCK_IN ),
.PIPE_TXOUTCLK_OUT ( PIPE_TXOUTCLK_OUT ),
.PIPE_RXOUTCLK_OUT ( PIPE_RXOUTCLK_OUT ),
.PIPE_PCLK_SEL_OUT ( PIPE_PCLK_SEL_OUT ),
.PIPE_GEN3_OUT ( PIPE_GEN3_OUT ),
//---------- PRBS/Loopback Ports ---------------------------
.PIPE_TXPRBSSEL ( 3'b0 ),
.PIPE_RXPRBSSEL ( 3'b0 ),
.PIPE_TXPRBSFORCEERR ( 1'b0 ),
.PIPE_RXPRBSCNTRESET ( 1'b0 ),
.PIPE_LOOPBACK ( 3'b0 ),
.PIPE_RXPRBSERR ( ),
//---------- FSM Ports ---------------------------
.PIPE_RST_FSM ( ),
.PIPE_QRST_FSM ( ),
.PIPE_RATE_FSM ( ),
.PIPE_SYNC_FSM_TX ( ),
.PIPE_SYNC_FSM_RX ( ),
.PIPE_DRP_FSM ( ),
.PIPE_TXEQ_FSM ( ),
.PIPE_RXEQ_FSM ( ),
.PIPE_QDRP_FSM ( ),
.PIPE_RST_IDLE ( ),
.PIPE_QRST_IDLE ( ),
.PIPE_RATE_IDLE ( ),
//---------- DEBUG Ports ---------------------------
.PIPE_DEBUG_0 ( ),
.PIPE_DEBUG_1 ( ),
.PIPE_DEBUG_2 ( ),
.PIPE_DEBUG_3 ( ),
.PIPE_DEBUG_4 ( ),
.PIPE_DEBUG_5 ( ),
.PIPE_DEBUG_6 ( ),
.PIPE_DEBUG_7 ( ),
.PIPE_DEBUG_8 ( ),
.PIPE_DEBUG_9 ( ),
.PIPE_DEBUG ( ),
.PIPE_DMONITOROUT ( )
);
assign pipe_rx0_phy_status = gt_rx_phy_status_wire[0] ;
assign pipe_rx1_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rx_phy_status_wire[1] : 1'b0;
assign pipe_rx2_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_phy_status_wire[2] : 1'b0;
assign pipe_rx3_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_phy_status_wire[3] : 1'b0;
assign pipe_rx4_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_phy_status_wire[4] : 1'b0;
assign pipe_rx5_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_phy_status_wire[5] : 1'b0;
assign pipe_rx6_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_phy_status_wire[6] : 1'b0;
assign pipe_rx7_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_phy_status_wire[7] : 1'b0;
assign pipe_rx0_chanisaligned = gt_rxchanisaligned_wire[0];
assign pipe_rx1_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rxchanisaligned_wire[1] : 1'b0 ;
assign pipe_rx2_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rxchanisaligned_wire[2] : 1'b0 ;
assign pipe_rx3_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rxchanisaligned_wire[3] : 1'b0 ;
assign pipe_rx4_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rxchanisaligned_wire[4] : 1'b0 ;
assign pipe_rx5_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rxchanisaligned_wire[5] : 1'b0 ;
assign pipe_rx6_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rxchanisaligned_wire[6] : 1'b0 ;
assign pipe_rx7_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rxchanisaligned_wire[7] : 1'b0 ;
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
assign pipe_rx0_char_is_k = {gt_rx_data_k_wire[1], gt_rx_data_k_wire[0]};
assign pipe_rx1_char_is_k = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? {gt_rx_data_k_wire[5], gt_rx_data_k_wire[4]} : 2'b0 ;
assign pipe_rx2_char_is_k = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? {gt_rx_data_k_wire[9], gt_rx_data_k_wire[8]} : 2'b0 ;
assign pipe_rx3_char_is_k = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? {gt_rx_data_k_wire[13], gt_rx_data_k_wire[12]} : 2'b0 ;
assign pipe_rx4_char_is_k = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_k_wire[17], gt_rx_data_k_wire[16]} : 2'b0 ;
assign pipe_rx5_char_is_k = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_k_wire[21], gt_rx_data_k_wire[20]} : 2'b0 ;
assign pipe_rx6_char_is_k = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_k_wire[25], gt_rx_data_k_wire[24]} : 2'b0 ;
assign pipe_rx7_char_is_k = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_k_wire[29], gt_rx_data_k_wire[28]} : 2'b0 ;
assign pipe_rx0_data = {gt_rx_data_wire[ 15: 8], gt_rx_data_wire[ 7: 0]};
assign pipe_rx1_data = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? {gt_rx_data_wire[47:40], gt_rx_data_wire[39:32]} : 16'h0 ;
assign pipe_rx2_data = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? {gt_rx_data_wire[79:72], gt_rx_data_wire[71:64]} : 16'h0 ;
assign pipe_rx3_data = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? {gt_rx_data_wire[111:104], gt_rx_data_wire[103:96]} : 16'h0 ;
assign pipe_rx4_data = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_wire[143:136], gt_rx_data_wire[135:128]} : 16'h0 ;
assign pipe_rx5_data = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_wire[175:168], gt_rx_data_wire[167:160]} : 16'h0 ;
assign pipe_rx6_data = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_wire[207:200], gt_rx_data_wire[199:192]} : 16'h0 ;
assign pipe_rx7_data = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_wire[239:232], gt_rx_data_wire[231:224]} : 16'h0 ;
assign pipe_rx0_status = gt_rx_status_wire[ 2: 0];
assign pipe_rx1_status = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rx_status_wire[ 5: 3] : 3'b0 ;
assign pipe_rx2_status = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_status_wire[ 8: 6] : 3'b0 ;
assign pipe_rx3_status = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_status_wire[11: 9] : 3'b0 ;
assign pipe_rx4_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_status_wire[14:12] : 3'b0 ;
assign pipe_rx5_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_status_wire[17:15] : 3'b0 ;
assign pipe_rx6_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_status_wire[20:18] : 3'b0 ;
assign pipe_rx7_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_status_wire[23:21] : 3'b0 ;
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
assign pipe_rx0_elec_idle = gt_rx_elec_idle_wire[0];
assign pipe_rx1_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rx_elec_idle_wire[1] : 1'b1 ;
assign pipe_rx2_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_elec_idle_wire[2] : 1'b1 ;
assign pipe_rx3_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_elec_idle_wire[3] : 1'b1 ;
assign pipe_rx4_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_elec_idle_wire[4] : 1'b1 ;
assign pipe_rx5_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_elec_idle_wire[5] : 1'b1 ;
assign pipe_rx6_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_elec_idle_wire[6] : 1'b1 ;
assign pipe_rx7_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_elec_idle_wire[7] : 1'b1 ;
assign pipe_rx0_valid = gt_rx_valid_wire[0];
assign pipe_rx1_valid = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rx_valid_wire[1] : 1'b0 ;
assign pipe_rx2_valid = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_valid_wire[2] : 1'b0 ;
assign pipe_rx3_valid = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_valid_wire[3] : 1'b0 ;
assign pipe_rx4_valid = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_valid_wire[4] : 1'b0 ;
assign pipe_rx5_valid = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_valid_wire[5] : 1'b0 ;
assign pipe_rx6_valid = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_valid_wire[6] : 1'b0 ;
assign pipe_rx7_valid = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_valid_wire[7] : 1'b0 ;
assign gt_rx_polarity[0] = pipe_rx0_polarity;
assign gt_rx_polarity[1] = pipe_rx1_polarity;
assign gt_rx_polarity[2] = pipe_rx2_polarity;
assign gt_rx_polarity[3] = pipe_rx3_polarity;
assign gt_rx_polarity[4] = pipe_rx4_polarity;
assign gt_rx_polarity[5] = pipe_rx5_polarity;
assign gt_rx_polarity[6] = pipe_rx6_polarity;
assign gt_rx_polarity[7] = pipe_rx7_polarity;
assign gt_power_down[ 1: 0] = pipe_tx0_powerdown;
assign gt_power_down[ 3: 2] = pipe_tx1_powerdown;
assign gt_power_down[ 5: 4] = pipe_tx2_powerdown;
assign gt_power_down[ 7: 6] = pipe_tx3_powerdown;
assign gt_power_down[ 9: 8] = pipe_tx4_powerdown;
assign gt_power_down[11:10] = pipe_tx5_powerdown;
assign gt_power_down[13:12] = pipe_tx6_powerdown;
assign gt_power_down[15:14] = pipe_tx7_powerdown;
assign gt_tx_char_disp_mode = {pipe_tx7_compliance,
pipe_tx6_compliance,
pipe_tx5_compliance,
pipe_tx4_compliance,
pipe_tx3_compliance,
pipe_tx2_compliance,
pipe_tx1_compliance,
pipe_tx0_compliance};
assign gt_tx_data_k = {2'd0,
pipe_tx7_char_is_k,
2'd0,
pipe_tx6_char_is_k,
2'd0,
pipe_tx5_char_is_k,
2'd0,
pipe_tx4_char_is_k,
2'd0,
pipe_tx3_char_is_k,
2'd0,
pipe_tx2_char_is_k,
2'd0,
pipe_tx1_char_is_k,
2'd0,
pipe_tx0_char_is_k};
assign gt_tx_data = {16'd0,
pipe_tx7_data,
16'd0,
pipe_tx6_data,
16'd0,
pipe_tx5_data,
16'd0,
pipe_tx4_data,
16'd0,
pipe_tx3_data,
16'd0,
pipe_tx2_data,
16'd0,
pipe_tx1_data,
16'd0,
pipe_tx0_data};
assign gt_tx_detect_rx_loopback = pipe_tx_rcvr_det;
assign gt_tx_elec_idle = {pipe_tx7_elec_idle,
pipe_tx6_elec_idle,
pipe_tx5_elec_idle,
pipe_tx4_elec_idle,
pipe_tx3_elec_idle,
pipe_tx2_elec_idle,
pipe_tx1_elec_idle,
pipe_tx0_elec_idle};
assign phy_rdy_n_int = (&phystatus_rst[LINK_CAP_MAX_LINK_WIDTH-1:0] & clock_locked);
assign phy_rdy_n = phy_rdy_n_int;
endmodule
|
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: PLL_100M.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.0.2 Build 222 07/20/2016 SJ Standard Edition
// ************************************************************
//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module PLL_100M (
inclk0,
c0,
locked);
input inclk0;
output c0;
output locked;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "10.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "PLL_100M.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "100000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL_100M.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL_100M.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL_100M.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL_100M.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL_100M.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL_100M_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL_100M_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
`timescale 1ns / 1ps
`define clkperiodby2 10
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 07:55:53 05/09/2015
// Design Name: multi_MAC_Base
// Module Name: /home/jayant/devel/ise_projects/mac/tb_mac_base.v
// Project Name: mac
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: multi_MAC_Base
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_mac_base;
// Inputs
reg clk;
reg sof;
reg [79:0] A;
reg [15:0] B;
// Outputs
wire [179:0] C;
wire [4:0] valid;
// Instantiate the Unit Under Test (UUT)
multi_MAC_Base uut (
.clk(clk),
.sof(sof),
.A(A),
.B(B),
.C(C),
.valid(valid)
);
initial begin
// Initialize Inputs
clk = 0;
sof = 0;
A = 0;
B = 0;
#310
A = 80'h00020007000900030005; B = 16'h0004;
#20
sof = 1'b1;
#200
#100
$stop;
end
always
#`clkperiodby2 clk <= ~clk;
endmodule
|
module ad9361_1t1r
(
AD9361_RX_Frame_P,
AD9361_RX_Frame_N,
AD9361_DATA_CLK_P,
AD9361_DATA_CLK_N,
AD9361_RX_DATA_P,
AD9361_RX_DATA_N,
AD9361_TX_Frame_P,
AD9361_TX_Frame_N,
AD9361_FB_CLK_P,
AD9361_FB_CLK_N,
AD9361_TX_DATA_P,
AD9361_TX_DATA_N,
clk,
rst,
rx_I,
rx_Q,
tx_I,
tx_Q,
rx_ce,
tx_ce
);
input AD9361_RX_Frame_P; // : in std_logic;
input AD9361_RX_Frame_N; // : in std_logic;
input AD9361_DATA_CLK_P; // : in std_logic;
input AD9361_DATA_CLK_N; // : in std_logic;
input [5:0]AD9361_RX_DATA_P; // : in std_logic_vector(5 downto 0);
input [5:0]AD9361_RX_DATA_N; // : in std_logic_vector(5 downto 0);
output AD9361_TX_Frame_P; // : out std_logic;
output AD9361_TX_Frame_N; // : out std_logic;
output AD9361_FB_CLK_P; // : out std_logic;
output AD9361_FB_CLK_N; // : out std_logic;
output [5:0]AD9361_TX_DATA_P; // : out std_logic_vector(5 downto 0);
output [5:0]AD9361_TX_DATA_N; // : out std_logic_vector(5 downto 0);
output clk;
input rst;
output reg [11:0]rx_I;
output reg [11:0]rx_Q;
input [11:0]tx_I;
input [11:0]tx_Q;
output reg rx_ce;
output reg tx_ce;
wire clk_out;
wire [13:0]rx;
reg [13:0]rx_h;
reg [13:0]tx;
reg [11:0]tx_I_reg;
reg [11:0]tx_Q_reg;
ddr_rx rx_if (
.data_in_from_pins_p({AD9361_RX_Frame_P,AD9361_RX_DATA_P}), // input wire [6 : 0] data_in_from_pins_p
.data_in_from_pins_n({AD9361_RX_Frame_N,AD9361_RX_DATA_N}), // input wire [6 : 0] data_in_from_pins_n
.clk_in_p(AD9361_DATA_CLK_P), // input wire clk_in_p
.clk_in_n(AD9361_DATA_CLK_N), // input wire clk_in_n
.io_reset(rst), // input wire io_reset
.clk_out(clk_out), // output wire clk_out
.data_in_to_device(rx) // output wire [13 : 0] data_in_to_device
);
ddr_tx tx_if (
.data_out_to_pins_p({AD9361_TX_Frame_P,AD9361_TX_DATA_P}), // output wire [6 : 0] data_out_to_pins_p
.data_out_to_pins_n({AD9361_TX_Frame_N,AD9361_TX_DATA_N}), // output wire [6 : 0] data_out_to_pins_n
.clk_in(clk_out), // input wire clk_in
.data_out_from_device(tx), // input wire [13 : 0] data_out_from_device
.clk_reset(rst), // input wire clk_reset
.io_reset(rst), // input wire io_reset
.clk_to_pins_p(AD9361_FB_CLK_P), // output wire clk_to_pins_p
.clk_to_pins_n(AD9361_FB_CLK_N) // output wire clk_to_pins_n
);
always @(posedge clk_out or posedge rst) begin
if (rst) begin
rx_h <= 14'h0;
rx_I <= 12'h0;
rx_Q <= 12'h0;
rx_ce <= 1'b0;
end
else if (rx[13]==1'b1) begin
rx_ce <= 1'b1;
rx_h <= rx;
end
else if(rx_ce==1'b1) begin
rx_ce <= 1'b0;
rx_I[11:6] = rx_h[5:0];
rx_Q[11:6] = rx_h[12:7];
rx_I[5:0] = rx[5:0];
rx_Q[5:0] = rx[12:7];
end
end
assign clk = clk_out;
always @(posedge clk_out or posedge rst) begin
if (rst) begin
tx_ce <= 1'b0;
tx <= 14'h0;
tx_I_reg <= 12'h0;
tx_Q_reg <= 12'h0;
end
else if (tx_ce==1'b1) begin
tx_ce <= 1'b0;
tx_I_reg <= tx_I;
tx_Q_reg <= tx_Q;
tx[5:0] <= tx_I[11:6];
tx[12:7] <= tx_Q[11:6];
tx[6] <= 1'b1;
tx[13] <= 1'b1;
end
else begin
tx_ce <= 1'b1;
tx[5:0] <= tx_I_reg[5:0];
tx[12:7] <= tx_Q_reg[5:0];
tx[6] <= 1'b0;
tx[13] <= 1'b0;
end
end
endmodule
|
module alt_mem_ddrx_ecc_decoder #
( parameter
CFG_DATA_WIDTH = 40,
CFG_ECC_CODE_WIDTH = 8,
CFG_ECC_DEC_REG = 1,
CFG_ECC_RDATA_REG = 0,
CFG_MMR_DRAM_DATA_WIDTH = 7,
CFG_MMR_LOCAL_DATA_WIDTH = 7,
CFG_PORT_WIDTH_ENABLE_ECC = 1
)
(
ctl_clk,
ctl_reset_n,
cfg_local_data_width,
cfg_dram_data_width,
cfg_enable_ecc,
input_data,
input_data_valid,
output_data,
output_data_valid,
output_ecc_code,
err_corrected,
err_detected,
err_fatal,
err_sbe
);
localparam CFG_ECC_DATA_WIDTH = (CFG_DATA_WIDTH > 8) ? (CFG_DATA_WIDTH - CFG_ECC_CODE_WIDTH) : (CFG_DATA_WIDTH);
input ctl_clk;
input ctl_reset_n;
input [CFG_MMR_DRAM_DATA_WIDTH - 1 : 0] cfg_local_data_width;
input [CFG_MMR_LOCAL_DATA_WIDTH - 1 : 0] cfg_dram_data_width;
input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
input [CFG_DATA_WIDTH - 1 : 0] input_data;
input input_data_valid;
output [CFG_DATA_WIDTH - 1 : 0] output_data;
output output_data_valid;
output [CFG_ECC_CODE_WIDTH - 1 : 0] output_ecc_code;
output err_corrected;
output err_detected;
output err_fatal;
output err_sbe;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
reg [CFG_DATA_WIDTH - 1 : 0] int_decoder_input;
reg [CFG_DATA_WIDTH - 1 : 0] int_decoder_input_data;
reg [CFG_DATA_WIDTH - 1 : 0] int_decoder_input_ecc_code;
reg [CFG_DATA_WIDTH - 1 : 0] or_int_decoder_input_ecc_code;
reg [CFG_DATA_WIDTH - 1 : 0] output_data;
reg output_data_valid;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] output_ecc_code;
reg err_corrected;
reg err_detected;
reg err_fatal;
reg err_sbe;
wire int_err_corrected;
wire int_err_detected;
wire int_err_fatal;
wire int_err_sbe;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] int_output_ecc_code;
wire [CFG_DATA_WIDTH - 1 : 0] decoder_input;
wire [CFG_ECC_DATA_WIDTH - 1 : 0] decoder_output;
reg decoder_output_valid;
reg [CFG_ECC_DATA_WIDTH - 1 : 0] decoder_output_r;
reg decoder_output_valid_r;
reg int_err_corrected_r;
reg int_err_detected_r;
reg int_err_fatal_r;
reg int_err_sbe_r;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] int_output_ecc_code_r;
wire zero = 1'b0;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Common Logic
//
//--------------------------------------------------------------------------------------------------------
// Input data splitting/masking logic:
// change
// <Empty data> - <ECC code> - <Data>
// into
// <ECC code> - <Empty data> - <Data>
generate
genvar i_data;
for (i_data = 0;i_data < CFG_DATA_WIDTH;i_data = i_data + 1)
begin : decoder_input_per_data_width
always @ (*)
begin
int_decoder_input_data [i_data] = input_data [i_data];
end
end
endgenerate
generate
if (CFG_ECC_RDATA_REG)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_decoder_input <= 0;
end
else
begin
int_decoder_input <= int_decoder_input_data;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
decoder_output_valid <= 0;
end
else
begin
decoder_output_valid <= input_data_valid;
end
end
end
else
begin
always @ (*)
begin
int_decoder_input = int_decoder_input_data;
end
always @ (*)
begin
decoder_output_valid = input_data_valid;
end
end
endgenerate
// Decoder input assignment
assign decoder_input = int_decoder_input;
// Decoder output, registered
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
decoder_output_r <= {CFG_ECC_DATA_WIDTH{1'b0}};
decoder_output_valid_r <= 1'b0;
int_err_corrected_r <= 1'b0;
int_err_detected_r <= 1'b0;
int_err_fatal_r <= 1'b0;
int_err_sbe_r <= 1'b0;
int_output_ecc_code_r <= {CFG_ECC_CODE_WIDTH{1'b0}};
end
else
begin
decoder_output_r <= decoder_output;
decoder_output_valid_r <= decoder_output_valid;
int_err_corrected_r <= int_err_corrected;
int_err_detected_r <= int_err_detected;
int_err_fatal_r <= int_err_fatal;
int_err_sbe_r <= int_err_sbe;
int_output_ecc_code_r <= int_output_ecc_code;
end
end
// Decoder output ecc code
generate
if (CFG_DATA_WIDTH <= 8)
begin
// No support for ECC case
always @ (*)
begin
int_output_ecc_code = {CFG_ECC_CODE_WIDTH{zero}};
end
end
else
begin
always @ (*)
begin
if (cfg_enable_ecc)
int_output_ecc_code = int_decoder_input_data [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH];
else
int_output_ecc_code = 0;
end
end
endgenerate
// Decoder wrapper output assignment
generate
begin : gen_decoder_output_reg_select
if (CFG_ECC_DEC_REG)
begin
always @ (*)
begin
if (cfg_enable_ecc)
begin
output_data = {{CFG_ECC_CODE_WIDTH{1'b0}}, decoder_output_r}; // Assign '0' to ECC code portions
output_data_valid = decoder_output_valid_r;
err_corrected = int_err_corrected_r;
err_detected = int_err_detected_r;
err_fatal = int_err_fatal_r;
err_sbe = int_err_sbe_r;
output_ecc_code = int_output_ecc_code_r;
end
else
begin
output_data = input_data;
output_data_valid = input_data_valid;
err_corrected = 1'b0;
err_detected = 1'b0;
err_fatal = 1'b0;
err_sbe = 1'b0;
output_ecc_code = int_output_ecc_code;
end
end
end
else
begin
always @ (*)
begin
if (cfg_enable_ecc)
begin
output_data = {{CFG_ECC_CODE_WIDTH{1'b0}}, decoder_output}; // Assign '0' to ECC code portions
output_data_valid = decoder_output_valid;
err_corrected = int_err_corrected;
err_detected = int_err_detected;
err_fatal = int_err_fatal;
err_sbe = int_err_sbe;
output_ecc_code = int_output_ecc_code;
end
else
begin
output_data = input_data;
output_data_valid = input_data_valid;
err_corrected = 1'b0;
err_detected = 1'b0;
err_fatal = 1'b0;
err_sbe = 1'b0;
output_ecc_code = int_output_ecc_code;
end
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Common Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Instantiation
//
//--------------------------------------------------------------------------------------------------------
generate
begin
if (CFG_ECC_DATA_WIDTH == 8 && CFG_DATA_WIDTH > 8) // Make sure this is an ECC case else it will cause compilation error
begin
wire [39 : 0] int_decoder_input;
wire [32 : 0] int_decoder_output;
// Assign decoder output
assign int_decoder_input = {decoder_input [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH], 24'd0, decoder_input [CFG_ECC_DATA_WIDTH - 1 : 0]};
// Assign decoder output
assign decoder_output = int_decoder_output [CFG_ECC_DATA_WIDTH - 1 : 0];
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_32 decoder_inst
(
.data (int_decoder_input [38 : 0]),
.err_corrected (int_err_corrected ),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.err_sbe (int_err_sbe ),
.q (int_decoder_output )
);
end
else if (CFG_ECC_DATA_WIDTH == 16)
begin
wire [39 : 0] int_decoder_input;
wire [32 : 0] int_decoder_output;
// Assign decoder output
assign int_decoder_input = {decoder_input [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH], 16'd0, decoder_input [CFG_ECC_DATA_WIDTH - 1 : 0]};
// Assign decoder output
assign decoder_output = int_decoder_output [CFG_ECC_DATA_WIDTH - 1 : 0];
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_32 decoder_inst
(
.data (int_decoder_input [38 : 0]),
.err_corrected (int_err_corrected ),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.err_sbe (int_err_sbe ),
.q (int_decoder_output )
);
end
else if (CFG_ECC_DATA_WIDTH == 32)
begin
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_32 decoder_inst
(
.data (decoder_input [38 : 0]),
.err_corrected (int_err_corrected ),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.err_sbe (int_err_sbe ),
.q (decoder_output )
);
end
else if (CFG_ECC_DATA_WIDTH == 64)
begin
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_64 decoder_inst
(
.data (decoder_input ),
.err_corrected (int_err_corrected),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.err_sbe (int_err_sbe ),
.q (decoder_output )
);
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Instantiation
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module Block_Mat_exit1573_p (
ap_clk,
ap_rst,
ap_start,
start_full_n,
ap_done,
ap_continue,
ap_idle,
ap_ready,
start_out,
start_write,
height,
width,
sat,
img0_rows_V_out_din,
img0_rows_V_out_full_n,
img0_rows_V_out_write,
img0_cols_V_out_din,
img0_cols_V_out_full_n,
img0_cols_V_out_write,
img2_rows_V_out_din,
img2_rows_V_out_full_n,
img2_rows_V_out_write,
img2_cols_V_out_din,
img2_cols_V_out_full_n,
img2_cols_V_out_write,
img3_rows_V_out_din,
img3_rows_V_out_full_n,
img3_rows_V_out_write,
img3_cols_V_out_din,
img3_cols_V_out_full_n,
img3_cols_V_out_write,
p_cols_assign_cast_out_out_din,
p_cols_assign_cast_out_out_full_n,
p_cols_assign_cast_out_out_write,
p_rows_assign_cast_out_out_din,
p_rows_assign_cast_out_out_full_n,
p_rows_assign_cast_out_out_write,
sat_out_din,
sat_out_full_n,
sat_out_write
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
input start_full_n;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
output start_out;
output start_write;
input [15:0] height;
input [15:0] width;
input [7:0] sat;
output [15:0] img0_rows_V_out_din;
input img0_rows_V_out_full_n;
output img0_rows_V_out_write;
output [15:0] img0_cols_V_out_din;
input img0_cols_V_out_full_n;
output img0_cols_V_out_write;
output [15:0] img2_rows_V_out_din;
input img2_rows_V_out_full_n;
output img2_rows_V_out_write;
output [15:0] img2_cols_V_out_din;
input img2_cols_V_out_full_n;
output img2_cols_V_out_write;
output [15:0] img3_rows_V_out_din;
input img3_rows_V_out_full_n;
output img3_rows_V_out_write;
output [15:0] img3_cols_V_out_din;
input img3_cols_V_out_full_n;
output img3_cols_V_out_write;
output [11:0] p_cols_assign_cast_out_out_din;
input p_cols_assign_cast_out_out_full_n;
output p_cols_assign_cast_out_out_write;
output [11:0] p_rows_assign_cast_out_out_din;
input p_rows_assign_cast_out_out_full_n;
output p_rows_assign_cast_out_out_write;
output [7:0] sat_out_din;
input sat_out_full_n;
output sat_out_write;
reg ap_done;
reg ap_idle;
reg start_write;
reg img0_rows_V_out_write;
reg img0_cols_V_out_write;
reg img2_rows_V_out_write;
reg img2_cols_V_out_write;
reg img3_rows_V_out_write;
reg img3_cols_V_out_write;
reg p_cols_assign_cast_out_out_write;
reg p_rows_assign_cast_out_out_write;
reg sat_out_write;
reg real_start;
reg start_once_reg;
reg ap_done_reg;
(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg internal_ap_ready;
reg img0_rows_V_out_blk_n;
reg img0_cols_V_out_blk_n;
reg img2_rows_V_out_blk_n;
reg img2_cols_V_out_blk_n;
reg img3_rows_V_out_blk_n;
reg img3_cols_V_out_blk_n;
reg p_cols_assign_cast_out_out_blk_n;
reg p_rows_assign_cast_out_out_blk_n;
reg sat_out_blk_n;
reg ap_block_state1;
reg [0:0] ap_NS_fsm;
// power-on initialization
initial begin
#0 start_once_reg = 1'b0;
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((sat_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
start_once_reg <= 1'b0;
end else begin
if (((internal_ap_ready == 1'b0) & (real_start == 1'b1))) begin
start_once_reg <= 1'b1;
end else if ((internal_ap_ready == 1'b1)) begin
start_once_reg <= 1'b0;
end
end
end
always @ (*) begin
if ((~((sat_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @ (*) begin
if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
img0_cols_V_out_blk_n = img0_cols_V_out_full_n;
end else begin
img0_cols_V_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((sat_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img0_cols_V_out_write = 1'b1;
end else begin
img0_cols_V_out_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
img0_rows_V_out_blk_n = img0_rows_V_out_full_n;
end else begin
img0_rows_V_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((sat_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img0_rows_V_out_write = 1'b1;
end else begin
img0_rows_V_out_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
img2_cols_V_out_blk_n = img2_cols_V_out_full_n;
end else begin
img2_cols_V_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((sat_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img2_cols_V_out_write = 1'b1;
end else begin
img2_cols_V_out_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
img2_rows_V_out_blk_n = img2_rows_V_out_full_n;
end else begin
img2_rows_V_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((sat_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img2_rows_V_out_write = 1'b1;
end else begin
img2_rows_V_out_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
img3_cols_V_out_blk_n = img3_cols_V_out_full_n;
end else begin
img3_cols_V_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((sat_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img3_cols_V_out_write = 1'b1;
end else begin
img3_cols_V_out_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
img3_rows_V_out_blk_n = img3_rows_V_out_full_n;
end else begin
img3_rows_V_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((sat_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img3_rows_V_out_write = 1'b1;
end else begin
img3_rows_V_out_write = 1'b0;
end
end
always @ (*) begin
if ((~((sat_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
internal_ap_ready = 1'b1;
end else begin
internal_ap_ready = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
p_cols_assign_cast_out_out_blk_n = p_cols_assign_cast_out_out_full_n;
end else begin
p_cols_assign_cast_out_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((sat_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_cols_assign_cast_out_out_write = 1'b1;
end else begin
p_cols_assign_cast_out_out_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
p_rows_assign_cast_out_out_blk_n = p_rows_assign_cast_out_out_full_n;
end else begin
p_rows_assign_cast_out_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((sat_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_rows_assign_cast_out_out_write = 1'b1;
end else begin
p_rows_assign_cast_out_out_write = 1'b0;
end
end
always @ (*) begin
if (((start_full_n == 1'b0) & (start_once_reg == 1'b0))) begin
real_start = 1'b0;
end else begin
real_start = ap_start;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
sat_out_blk_n = sat_out_full_n;
end else begin
sat_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((sat_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
sat_out_write = 1'b1;
end else begin
sat_out_write = 1'b0;
end
end
always @ (*) begin
if (((start_once_reg == 1'b0) & (real_start == 1'b1))) begin
start_write = 1'b1;
end else begin
start_write = 1'b0;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @ (*) begin
ap_block_state1 = ((sat_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1));
end
assign ap_ready = internal_ap_ready;
assign img0_cols_V_out_din = width;
assign img0_rows_V_out_din = height;
assign img2_cols_V_out_din = width;
assign img2_rows_V_out_din = height;
assign img3_cols_V_out_din = width;
assign img3_rows_V_out_din = height;
assign p_cols_assign_cast_out_out_din = width[11:0];
assign p_rows_assign_cast_out_out_din = height[11:0];
assign sat_out_din = sat;
assign start_out = real_start;
endmodule //Block_Mat_exit1573_p
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_MUX_2TO1_N_TB_V
`define SKY130_FD_SC_MS__UDP_MUX_2TO1_N_TB_V
/**
* udp_mux_2to1_N: Two to one multiplexer with inverting output
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__udp_mux_2to1_n.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg S;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
S = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 S = 1'b0;
#80 A0 = 1'b1;
#100 A1 = 1'b1;
#120 S = 1'b1;
#140 A0 = 1'b0;
#160 A1 = 1'b0;
#180 S = 1'b0;
#200 S = 1'b1;
#220 A1 = 1'b1;
#240 A0 = 1'b1;
#260 S = 1'bx;
#280 A1 = 1'bx;
#300 A0 = 1'bx;
end
sky130_fd_sc_ms__udp_mux_2to1_N dut (.A0(A0), .A1(A1), .S(S), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_MUX_2TO1_N_TB_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Muhammad Ijaz
//
// Create Date: 08/08/2017 06:03:02 PM
// Design Name:
// Module Name: DUAL_PORT_MEMORY_SIMULATION
// Project Name: RISC-V
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module DUAL_PORT_MEMORY_SIMULATION();
parameter MEMORY_WIDTH = 512 ;
parameter MEMORY_DEPTH = 512 ;
parameter MEMORY_LATENCY = "LOW_LATENCY" ;
parameter INIT_FILE = "" ;
// Inputs
reg clk ;
reg [$clog2(MEMORY_DEPTH-1) - 1 : 0] write_address ;
reg [MEMORY_WIDTH-1 : 0] data_in ;
reg write_enable ;
reg [$clog2(MEMORY_DEPTH-1)-1 : 0] read_address ;
reg read_enble ;
// Outputs
wire [MEMORY_WIDTH-1 : 0] data_out ;
// Instantiate the Unit Under Test (UUT)
DUAL_PORT_MEMORY uut(
.CLK(clk),
.WRITE_ADDRESS(write_address),
.DATA_IN(data_in),
.WRITE_ENABLE(write_enable),
.READ_ADDRESS(read_address),
.READ_ENBLE(read_enble),
.DATA_OUT(data_out)
);
initial
begin
// Initialize Inputs
clk = 1'b0 ;
write_address = 9'b1 ;
data_in = 512'b11 ;
write_enable = 1'b1 ;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
clk = 1'b1 ;
#100;
clk = 1'b0 ;
write_address = 9'b0 ;
data_in = 512'b1 ;
write_enable = 1'b1 ;
#100;
clk = 1'b1 ;
#100;
clk = 1'b0 ;
write_address = 9'b0 ;
data_in = 512'b0 ;
write_enable = 1'b0 ;
read_address = 9'b0 ;
read_enble = 1'b1 ;
#100;
clk = 1'b1 ;
#100;
clk = 1'b0 ;
read_enble = 1'b0 ;
#100;
clk = 1'b1 ;
#100;
clk = 1'b0 ;
end
endmodule
|
`ifndef _SPI_MASTER_V
`define _SPI_MASTER_V
module spi_master #(
parameter CLK_DIVIDE=3 // divide clk by 2^CLK_DIVIDE to get spi_sclk
) (
input clk, // 50 MHz system clk
input reset,
input spi_start,
input [7:0] spi_data,
output spi_fin,
output spi_csn,
output spi_sdo,
output spi_sclk // max 10 MHz clk
);
`define SPI_MASTER_SM_W 2
localparam STATE_IDLE = `SPI_MASTER_SM_W'h0;
localparam STATE_SEND = `SPI_MASTER_SM_W'h1;
localparam STATE_HOLD = `SPI_MASTER_SM_W'h2;
localparam STATE_DONE = `SPI_MASTER_SM_W'h3;
reg [`SPI_MASTER_SM_W-1:0] spi_sm_state;
reg [CLK_DIVIDE-1:0] clk_divider;
reg [7:0] spi_data_shift;
reg [2:0] shift_counter;
assign spi_csn = ((spi_sm_state==STATE_IDLE) && (spi_start==1'b0)) ? 1'b1 : 1'b0;
assign spi_sdo = spi_data_shift[7];
assign spi_sclk = ((spi_sm_state==STATE_SEND) && (clk_divider[CLK_DIVIDE-1]==1'b1)) ? 1'b1 : 1'b0;
assign spi_fin = (spi_sm_state==STATE_DONE) ? 1'b1 : 1'b0;
always @(posedge clk or posedge reset) begin
if (reset) begin
spi_sm_state <= STATE_IDLE;
spi_data_shift <= 'b0;
clk_divider <= 'b0;
shift_counter <= 'b0;
end else begin
case (spi_sm_state)
STATE_IDLE: begin
if (spi_start==1'b1) begin
spi_sm_state <= STATE_SEND;
spi_data_shift <= spi_data;
clk_divider <= 'b0;
shift_counter <= 'b0;
end
end
STATE_SEND: begin
clk_divider <= clk_divider + 1;
if (clk_divider == {CLK_DIVIDE{1'b1}}) begin
shift_counter <= shift_counter + 1;
spi_data_shift <= {spi_data_shift[6:0], 1'b0};
if (shift_counter==3'b111) begin
spi_sm_state <= STATE_HOLD;
end
end
end
STATE_HOLD: begin
clk_divider <= clk_divider + 1;
if (clk_divider == {CLK_DIVIDE{1'b1}}) begin
spi_sm_state <= STATE_DONE;
end
end
STATE_DONE: begin
if (spi_start==1'b0) begin
spi_sm_state <= STATE_IDLE;
end
end
default:
spi_sm_state <= STATE_IDLE;
endcase
end
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKBUF_SYMBOL_V
`define SKY130_FD_SC_HD__CLKBUF_SYMBOL_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__clkbuf (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKBUF_SYMBOL_V
|
//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
module sdr_data_path(
CLK,
RESET_N,
DATAIN,
DM,
DQOUT,
DQM
);
//`include "Sdram_Params.h"
input CLK; // System Clock
input RESET_N; // System Reset
input [`DSIZE-1:0] DATAIN; // Data input from the host
input [`DSIZE/8-1:0] DM; // byte data masks
output [`DSIZE-1:0] DQOUT;
output [`DSIZE/8-1:0] DQM; // SDRAM data mask ouputs
reg [`DSIZE/8-1:0] DQM;
// internal
reg [`DSIZE-1:0] DIN1;
reg [`DSIZE-1:0] DIN2;
reg [`DSIZE/8-1:0] DM1;
// Allign the input and output data to the SDRAM control path
always @(posedge CLK or negedge RESET_N)
begin
if (RESET_N == 0)
begin
DIN1 <= 0;
DIN2 <= 0;
DM1 <= 0;
end
else
begin
DIN1 <= DATAIN;
DIN2 <= DIN1;
DQM <= DM;
end
end
assign DQOUT = DIN2;
endmodule
|
//*******************************************************************************************************************************************************/
// Module Name: user_interface
// Module Type: User Interface and External Communications Module
// Author: Shreyas Vinod
// Purpose: User Interface and External Communications Module for Neptune I v3.0
// Description: A simplistic User Interface and Front Panel Communications and Translation Module that takes a small number of inputs from Neptune I's
// Front Panel and converts it into a multitude of signals to communicate in perfect harmony with Neptune I's Control Matrix. It's able
// to request for IO and Bus Access as well. It is also capable of driving two sets of five 7-segment displays with binary outputs that
// can later be externally decoded into BCD or hexadecimal.
//*******************************************************************************************************************************************************/
module user_interface(clk, rst, dma_req, dma_appr, wr, add_wr, incr_add, clk_sel, entity_sel, pc_rd, mar_rd, rf_rd1, rf_rd2, ram_rd, stk_rd, alu_rd, data_in, sys_clk, sys_rst, sys_hrd_rst, sys_dma_req, mar_incr, we_out, d_out, add_out, data_out);
// Parameter Definitions
parameter width = 'd16; // Data Width
parameter add_width = 'd13; // Address Width
parameter disp_output_width = 'd20; // Display Driver Data Width
// Inputs
input wire clk /* External Clock */, rst /* External Reset Request */, dma_req /* External Direct Memory Access (DMA) Request */; // Management Interfaces
input wire dma_appr /* External Direct Memory Access (DMA) Request Approval Notification */; // Notification Interfaces
input wire wr /* External Write Request */, add_wr /* External Address Write Request */;
input wire incr_add /* Increment Address Request */, clk_sel /* Clock Select Toggle */;
input wire [2:0] entity_sel /* Read/Write Processor Entity Select */;
input wire [add_width-1:0] mar_rd /* Memory Address Register (MAR) Read */;
input wire [width-1:0] pc_rd /* Program Counter (PC) Read */, rf_rd1 /* Register File Port (RF) I Read */, rf_rd2 /* Register File (RF) Port II Read */, ram_rd /* Random Access Memory (RAM) Read */;
input wire [width-1:0] stk_rd /* Stack Read */, alu_rd /* ALU Result Read */;
input wire [width-1:0] data_in /* External Data Input Port */;
// Outputs
output wire sys_clk /* System Clock Output */, sys_rst /* System Reset Output */, sys_hrd_rst /* System Hard Reset Output */, sys_dma_req /* Request Direct Memory Access (DMA) from System */;
output wire mar_incr /* Increment MAR Request */;
output wire [2:0] we_out /* Control Matrix Write Enable Request */;
output wire [width-1:0] d_out /* Data Output for Direct Memory Access (DMA) Write Requests */;
output wire [disp_output_width-1:0] add_out /* External Address Output Port */;
output wire [disp_output_width:0] data_out /* External Data Output Port */;
// Internals
reg sclk /* Slow Clock Driver */, rst_buf /* External Reset Request Buffer */, dma_req_buf /* External Direct Memory Access (DMA) Request Buffer */, wr_buf /* External Write Request Buffer */;
reg add_wr_buf /* External Address Write Request Buffer */, incr_add_buf /* Increment Address Request Buffer */, incr_c /* Incrementation Complete Notification */;
reg [2:0] entity_sel_buf /* Read/Write Processor Entity Select Buffer */, entity_sel_buf_t /* True Entity Select Buffer */;
reg [3:0] stclk /* Reset LED State Clock */;
reg [width-1:0] data_in_buf /* Data Input Buffer */, data_conv_buf /* Hex Conversion Data Buffer */;
reg [disp_output_width:0] a_bus_disp; // Binary to Hex (Extended Binary, decoded by Display Driver) converted Address Output signal. Extra bit ignored.
reg [disp_output_width:0] d_bus_disp; // Binary to Hex (Extended Binary, decoded by Display Driver) converted Data Output signals. One extra bit for sign notation.
reg [23:0] counter /* Slow Clock Driver Counter */;
// Initialization
initial begin
sclk <= 1'b0;
stclk [3;0] <= 4'b0;
counter [23:0] <= 24'b0;
end
// Slow Clock Driver Block
always@(posedge clk) begin
if(counter [23:0] < 5000000) counter [23:0] <= counter [23:0] + 1'b1;
else begin
sclk <= !sclk;
counter [23:0] <= 24'b0;
end
end
// Write Request
assign we_out [2:0] = (wr_buf && dma_appr)?entity_sel_buf [2:0]:3'b0;
// Output Logic
assign sys_clk = (clk_sel)?sclk:clk; // System Clock Select
assign sys_rst = (rst_buf)?1'b1:1'b0; // Reset Enable
assign sys_hrd_rst = (rst_buf && wr_buf && add_wr_buf && incr_add_buf && (entity_sel_buf == 3'b0))?1'b1:1'b0; // Hard Reset Enable Logic
assign sys_dma_req = dma_req_buf; // Request Direct Memory Access (DMA) from Control Matrix
assign mar_incr = incr_add_buf; // Increment MAR contents.
assign d_out [width-1:0] = data_in_buf [width-1:0]; // Assigns the Direct Memory Access (DMA) Write Request Data Line based on input.
assign add_out [disp_output_width-1:0] = a_bus_disp [disp_output_width-1:0]; // Assigns the Address Output Port the value of the Address Output buffer.
assign data_out [disp_output_width:0] = d_bus_disp [disp_output_width:0]; // Assigns the Data Output Port the value of the Data Output buffer.
// Buffer Logic
always@(posedge sclk) begin
rst_buf <= rst; // External Reset Request Buffer
dma_req_buf <= dma_req; // External Direct Memory Access (DMA) Request Buffer
wr_buf <= wr; // External Write Request Buffer
add_wr_buf <= add_wr; // External Address Write Request Buffer
data_in_buf <= data_in; // External Data Input Buffer
// Entity Select
entity_sel_buf_t [2:0] <= entity_sel [2:0]; // True Entity Select Buffer based on input.
if(add_wr_buf) entity_sel_buf [2:0] <= 3'b101; // Select MAR to write address.
else entity_sel_buf [2:0] <= entity_sel [2:0]; // Select Entity based on input.
end
// Data Conversion Buffer
always@(entity_sel_buf_t, rf_rd1, rf_rd2, ram_rd, pc_rd, mar_rd, stk_rd, alu_rd) begin
case(entity_sel_buf_t) // synthesis parallel_case
3'b000: data_conv_buf [width-1:0] = {width{1'b0}};
3'b001: data_conv_buf [width-1:0] = rf_rd1 [width-1:0];
3'b010: data_conv_buf [width-1:0] = rf_rd2 [width-1:0];
3'b011: data_conv_buf [width-1:0] = ram_rd [width-1:0];
3'b100: data_conv_buf [width-1:0] = pc_rd [width-1:0];
3'b101: data_conv_buf [width-1:0] = {{width-add_width{1'b0}}, mar_rd [add_width-1:0]};
3'b110: data_conv_buf [width-1:0] = stk_rd [width-1:0];
3'b111: data_conv_buf [width-1:0] = alu_rd [width-1:0];
default: data_conv_buf [width-1:0] = {width{1'b0}};
endcase
end
// Incrementation Logic and signal buffer
// This block ensures that incrementation takes place only once for every increment request by using the 'Incrementation Complete (incr_c)' notification.
always@(posedge sclk) begin
if(!incr_add_buf && incr_add && !incr_c) incr_add_buf <= 1'b1;
else if(incr_add_buf && incr_add) begin
incr_add_buf <= 1'b0;
incr_c <= 1'b1;
end else if(!incr_add) begin
incr_add_buf <= 1'b0;
incr_c <= 1'b0;
end
end
// Binary to Hex (Extended Binary, decoded by Display Driver) Conversion Block
// Address Bus
always@(mar_rd) begin
a_bus_disp [disp_output_width:0] = {7'b0, mar_rd [add_width-1:0]};
end
// Data Bus
always@(data_conv_buf) begin
d_bus_disp [disp_output_width:0] = {data_conv_buf[width-1], 4'b0, data_conv_buf [width-2:0]};
end
endmodule
|
(** * Types: Type Systems *)
Require Export Smallstep.
Hint Constructors multi.
(** Our next major topic is _type systems_ -- static program
analyses that classify expressions according to the "shapes" of
their results. We'll begin with a typed version of a very simple
language with just booleans and numbers, to introduce the basic
ideas of types, typing rules, and the fundamental theorems about
type systems: _type preservation_ and _progress_. Then we'll move
on to the _simply typed lambda-calculus_, which lives at the core
of every modern functional programming language (including
Coq). *)
(* ###################################################################### *)
(** * Typed Arithmetic Expressions *)
(** To motivate the discussion of type systems, let's begin as
usual with an extremely simple toy language. We want it to have
the potential for programs "going wrong" because of runtime type
errors, so we need something a tiny bit more complex than the
language of constants and addition that we used in chapter
[Smallstep]: a single kind of data (just numbers) is too simple,
but just two kinds (numbers and booleans) already gives us enough
material to tell an interesting story.
The language definition is completely routine. *)
(* ###################################################################### *)
(** ** Syntax *)
(** Informally:
t ::= true
| false
| if t then t else t
| 0
| succ t
| pred t
| iszero t
Formally:
*)
Inductive tm : Type :=
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm
| tzero : tm
| tsucc : tm -> tm
| tpred : tm -> tm
| tiszero : tm -> tm.
(** _Values_ are [true], [false], and numeric values... *)
Inductive bvalue : tm -> Prop :=
| bv_true : bvalue ttrue
| bv_false : bvalue tfalse.
Inductive nvalue : tm -> Prop :=
| nv_zero : nvalue tzero
| nv_succ : forall t, nvalue t -> nvalue (tsucc t).
Definition value (t:tm) := bvalue t \/ nvalue t.
Hint Constructors bvalue nvalue.
Hint Unfold value.
Hint Unfold extend.
(* ###################################################################### *)
(** ** Operational Semantics *)
(** Informally: *)
(**
------------------------------ (ST_IfTrue)
if true then t1 else t2 ==> t1
------------------------------- (ST_IfFalse)
if false then t1 else t2 ==> t2
t1 ==> t1'
------------------------- (ST_If)
if t1 then t2 else t3 ==>
if t1' then t2 else t3
t1 ==> t1'
-------------------- (ST_Succ)
succ t1 ==> succ t1'
------------ (ST_PredZero)
pred 0 ==> 0
numeric value v1
--------------------- (ST_PredSucc)
pred (succ v1) ==> v1
t1 ==> t1'
-------------------- (ST_Pred)
pred t1 ==> pred t1'
----------------- (ST_IszeroZero)
iszero 0 ==> true
numeric value v1
-------------------------- (ST_IszeroSucc)
iszero (succ v1) ==> false
t1 ==> t1'
------------------------ (ST_Iszero)
iszero t1 ==> iszero t1'
*)
(** Formally: *)
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
(tif ttrue t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tif tfalse t1 t2) ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tif t1 t2 t3) ==> (tif t1' t2 t3)
| ST_Succ : forall t1 t1',
t1 ==> t1' ->
(tsucc t1) ==> (tsucc t1')
| ST_PredZero :
(tpred tzero) ==> tzero
| ST_PredSucc : forall t1,
nvalue t1 ->
(tpred (tsucc t1)) ==> t1
| ST_Pred : forall t1 t1',
t1 ==> t1' ->
(tpred t1) ==> (tpred t1')
| ST_IszeroZero :
(tiszero tzero) ==> ttrue
| ST_IszeroSucc : forall t1,
nvalue t1 ->
(tiszero (tsucc t1)) ==> tfalse
| ST_Iszero : forall t1 t1',
t1 ==> t1' ->
(tiszero t1) ==> (tiszero t1')
where "t1 '==>' t2" := (step t1 t2).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_IfTrue" | Case_aux c "ST_IfFalse" | Case_aux c "ST_If"
| Case_aux c "ST_Succ" | Case_aux c "ST_PredZero"
| Case_aux c "ST_PredSucc" | Case_aux c "ST_Pred"
| Case_aux c "ST_IszeroZero" | Case_aux c "ST_IszeroSucc"
| Case_aux c "ST_Iszero" ].
Hint Constructors step.
(** Notice that the [step] relation doesn't care about whether
expressions make global sense -- it just checks that the operation
in the _next_ reduction step is being applied to the right kinds
of operands.
For example, the term [succ true] (i.e., [tsucc ttrue] in the
formal syntax) cannot take a step, but the almost as obviously
nonsensical term
succ (if true then true else true)
can take a step (once, before becoming stuck). *)
(* ###################################################################### *)
(** ** Normal Forms and Values *)
(** The first interesting thing about the [step] relation in this
language is that the strong progress theorem from the Smallstep
chapter fails! That is, there are terms that are normal
forms (they can't take a step) but not values (because we have not
included them in our definition of possible "results of
evaluation"). Such terms are _stuck_. *)
Notation step_normal_form := (normal_form step).
Definition stuck (t:tm) : Prop :=
step_normal_form t /\ ~ value t.
Hint Unfold stuck.
(** **** Exercise: 2 stars (some_term_is_stuck) *)
Example some_term_is_stuck :
exists t, stuck t.
Proof.
exists (tsucc ttrue).
unfold stuck. split.
unfold normal_form.
intro contra. inversion contra.
inversion H. inversion H1.
intro contra.
unfold value in contra.
inversion contra; inversion H. inversion H1.
Qed.
(** [] *)
(** However, although values and normal forms are not the same in this
language, the former set is included in the latter. This is
important because it shows we did not accidentally define things
so that some value could still take a step. *)
(** **** Exercise: 3 stars, advanced (value_is_nf) *)
(** Hint: You will reach a point in this proof where you need to
use an induction to reason about a term that is known to be a
numeric value. This induction can be performed either over the
term itself or over the evidence that it is a numeric value. The
proof goes through in either case, but you will find that one way
is quite a bit shorter than the other. For the sake of the
exercise, try to complete the proof both ways. *)
Lemma value_is_nf : forall t,
value t -> step_normal_form t.
Proof.
unfold normal_form, value.
intros.
inversion H.
inversion H0; intro contra; inversion contra; inversion H2.
induction t; intro contra; inversion contra;
try inversion H1; try inversion H0.
subst.
apply IHt; auto.
exists t1'. assumption.
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (step_deterministic) *)
(** Using [value_is_nf], we can show that the [step] relation is
also deterministic... *)
Theorem step_deterministic:
deterministic step.
Proof with eauto.
unfold deterministic.
intros.
generalize dependent y2.
step_cases (induction H) Case; intros; inversion H0; subst.
Case "ST_IfTrue". reflexivity. solve by inversion.
Case "ST_IfFalse". reflexivity. solve by inversion.
Case "ST_If".
solve by inversion. solve by inversion.
apply IHstep in H5; subst. reflexivity.
Case "ST_Succ". apply IHstep in H2; subst. reflexivity.
Case "ST_PredZero".
reflexivity. solve by inversion.
Case "ST_PredSucc".
reflexivity.
assert (step_normal_form (tsucc t1)) by (apply value_is_nf; auto).
exfalso. apply H1. exists t1'. assumption.
Case "ST_Pred".
solve by inversion.
assert (step_normal_form (tsucc y2)) by (apply value_is_nf; auto).
exfalso. apply H1. exists t1'. assumption.
apply IHstep in H2; subst. reflexivity.
Case "ST_IszeroZero". reflexivity. inversion H1.
Case "ST_IszeroSucc".
reflexivity.
assert (step_normal_form (tsucc t1)) by (apply value_is_nf; auto).
exfalso. apply H1. exists t1'. assumption.
Case "ST_Iszero".
inversion H.
assert (step_normal_form (tsucc t0)) by (apply value_is_nf; auto).
exfalso. apply H1. exists t1'. assumption.
apply IHstep in H2; subst. reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** ** Typing *)
(** The next critical observation about this language is that,
although there are stuck terms, they are all "nonsensical", mixing
booleans and numbers in a way that we don't even _want_ to have a
meaning. We can easily exclude such ill-typed terms by defining a
_typing relation_ that relates terms to the types (either numeric
or boolean) of their final results. *)
Inductive ty : Type :=
| TBool : ty
| TNat : ty.
(** In informal notation, the typing relation is often written
[|- t \in T], pronounced "[t] has type [T]." The [|-] symbol is
called a "turnstile". (Below, we're going to see richer typing
relations where an additional "context" argument is written to the
left of the turnstile. Here, the context is always empty.) *)
(**
---------------- (T_True)
|- true \in Bool
----------------- (T_False)
|- false \in Bool
|- t1 \in Bool |- t2 \in T |- t3 \in T
-------------------------------------------- (T_If)
|- if t1 then t2 else t3 \in T
------------ (T_Zero)
|- 0 \in Nat
|- t1 \in Nat
------------------ (T_Succ)
|- succ t1 \in Nat
|- t1 \in Nat
------------------ (T_Pred)
|- pred t1 \in Nat
|- t1 \in Nat
--------------------- (T_IsZero)
|- iszero t1 \in Bool
*)
Reserved Notation "'|-' t '\in' T" (at level 40).
Inductive has_type : tm -> ty -> Prop :=
| T_True :
|- ttrue \in TBool
| T_False :
|- tfalse \in TBool
| T_If : forall t1 t2 t3 T,
|- t1 \in TBool ->
|- t2 \in T ->
|- t3 \in T ->
|- tif t1 t2 t3 \in T
| T_Zero :
|- tzero \in TNat
| T_Succ : forall t1,
|- t1 \in TNat ->
|- tsucc t1 \in TNat
| T_Pred : forall t1,
|- t1 \in TNat ->
|- tpred t1 \in TNat
| T_Iszero : forall t1,
|- t1 \in TNat ->
|- tiszero t1 \in TBool
where "'|-' t '\in' T" := (has_type t T).
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_True" | Case_aux c "T_False" | Case_aux c "T_If"
| Case_aux c "T_Zero" | Case_aux c "T_Succ" | Case_aux c "T_Pred"
| Case_aux c "T_Iszero" ].
Hint Constructors has_type.
(* ###################################################################### *)
(** *** Examples *)
(** It's important to realize that the typing relation is a
_conservative_ (or _static_) approximation: it does not calculate
the type of the normal form of a term. *)
Example has_type_1 :
|- tif tfalse tzero (tsucc tzero) \in TNat.
Proof.
apply T_If.
apply T_False.
apply T_Zero.
apply T_Succ.
apply T_Zero.
Qed.
(** (Since we've included all the constructors of the typing relation
in the hint database, the [auto] tactic can actually find this
proof automatically.) *)
Example has_type_not :
~ (|- tif tfalse tzero ttrue \in TBool).
Proof.
intros Contra. solve by inversion 2. Qed.
(** **** Exercise: 1 star, optional (succ_hastype_nat__hastype_nat) *)
Example succ_hastype_nat__hastype_nat : forall t,
|- tsucc t \in TNat ->
|- t \in TNat.
Proof.
intros. inversion H; subst. assumption.
Qed.
(** [] *)
(* ###################################################################### *)
(** ** Canonical forms *)
(** The following two lemmas capture the basic property that defines
the shape of well-typed values. They say that the definition of value
and the typing relation agree. *)
Lemma bool_canonical : forall t,
|- t \in TBool -> value t -> bvalue t.
Proof.
intros t HT HV.
inversion HV; auto.
induction H; inversion HT; auto.
Qed.
Lemma nat_canonical : forall t,
|- t \in TNat -> value t -> nvalue t.
Proof.
intros t HT HV.
inversion HV.
inversion H; subst; inversion HT.
auto.
Qed.
(* ###################################################################### *)
(** ** Progress *)
(** The typing relation enjoys two critical properties. The first is
that well-typed normal forms are values (i.e., not stuck). *)
Theorem progress : forall t T,
|- t \in T ->
value t \/ exists t', t ==> t'.
(** **** Exercise: 3 stars (finish_progress) *)
(** Complete the formal proof of the [progress] property. (Make sure
you understand the informal proof fragment in the following
exercise before starting -- this will save you a lot of time.) *)
Proof with auto.
intros t T HT.
has_type_cases (induction HT) Case...
(* The cases that were obviously values, like T_True and
T_False, were eliminated immediately by auto *)
Case "T_If".
right. inversion IHHT1; clear IHHT1.
SCase "t1 is a value".
apply (bool_canonical t1 HT1) in H.
inversion H; subst; clear H.
exists t2...
exists t3...
SCase "t1 can take a step".
inversion H as [t1' H1].
exists (tif t1' t2 t3)...
(* following by myself... *)
Case "T_Succ".
inversion IHHT; clear IHHT.
left. apply (nat_canonical t1 HT) in H. auto.
right. inversion H. exists (tsucc x)...
Case "T_Pred".
right. inversion IHHT; clear IHHT.
apply (nat_canonical t1 HT) in H.
inversion H; subst. clear H.
exists tzero... exists t...
inversion H; subst. clear H.
exists (tpred x)...
Case "T_Iszero".
right. inversion IHHT; clear IHHT.
apply (nat_canonical t1 HT) in H.
inversion H; subst. clear H.
exists ttrue... exists tfalse...
inversion H; subst. clear H.
exists (tiszero x)...
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (finish_progress_informal) *)
(** Complete the corresponding informal proof: *)
(** _Theorem_: If [|- t \in T], then either [t] is a value or else
[t ==> t'] for some [t']. *)
(** _Proof_: By induction on a derivation of [|- t \in T].
- If the last rule in the derivation is [T_If], then [t = if t1
then t2 else t3], with [|- t1 \in Bool], [|- t2 \in T] and [|- t3
\in T]. By the IH, either [t1] is a value or else [t1] can step
to some [t1'].
- If [t1] is a value, then by the canonical forms lemmas
and the fact that [|- t1 \in Bool] we have that [t1]
is a [bvalue] -- i.e., it is either [true] or [false].
If [t1 = true], then [t] steps to [t2] by [ST_IfTrue],
while if [t1 = false], then [t] steps to [t3] by
[ST_IfFalse]. Either way, [t] can step, which is what
we wanted to show.
- If [t1] itself can take a step, then, by [ST_If], so can
[t].
(* TODO: FILL IN HERE *)
[] *)
(** This is more interesting than the strong progress theorem that we
saw in the Smallstep chapter, where _all_ normal forms were
values. Here, a term can be stuck, but only if it is ill
typed. *)
(** **** Exercise: 1 star (step_review) *)
(** Quick review. Answer _true_ or _false_. In this language...
- Every well-typed normal form is a value.
Yes.
- Every value is a normal form.
No.
- The single-step evaluation relation is
a partial function (i.e., it is deterministic).
Yes.
- The single-step evaluation relation is a _total_ function.
Yes.
*)
(** [] *)
(* ###################################################################### *)
(** ** Type Preservation *)
(** The second critical property of typing is that, when a well-typed
term takes a step, the result is also a well-typed term.
This theorem is often called the _subject reduction_ property,
because it tells us what happens when the "subject" of the typing
relation is reduced. This terminology comes from thinking of
typing statements as sentences, where the term is the subject and
the type is the predicate. *)
Theorem preservation : forall t t' T,
|- t \in T ->
t ==> t' ->
|- t' \in T.
(** **** Exercise: 2 stars (finish_preservation) *)
(** Complete the formal proof of the [preservation] property. (Again,
make sure you understand the informal proof fragment in the
following exercise first.) *)
Proof with auto.
intros t t' T HT HE.
generalize dependent t'.
has_type_cases (induction HT) Case;
(* every case needs to introduce a couple of things *)
intros t' HE;
(* and we can deal with several impossible
cases all at once *)
try (solve by inversion).
Case "T_If". inversion HE; subst; clear HE.
SCase "ST_IFTrue". assumption.
SCase "ST_IfFalse". assumption.
SCase "ST_If". apply T_If; try assumption.
apply IHHT1; assumption.
Case "T_Succ".
inversion HE; subst; clear HE.
constructor. apply IHHT. assumption.
Case "T_Pred".
inversion HE; subst; clear HE. assumption.
inversion HT; subst. assumption.
auto.
Case "T_Iszero".
inversion HE; subst; clear HE; auto.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (finish_preservation_informal) *)
(** Complete the following proof: *)
(** _Theorem_: If [|- t \in T] and [t ==> t'], then [|- t' \in T]. *)
(** _Proof_: By induction on a derivation of [|- t \in T].
- If the last rule in the derivation is [T_If], then [t = if t1
then t2 else t3], with [|- t1 \in Bool], [|- t2 \in T] and [|- t3
\in T].
Inspecting the rules for the small-step reduction relation and
remembering that [t] has the form [if ...], we see that the
only ones that could have been used to prove [t ==> t'] are
[ST_IfTrue], [ST_IfFalse], or [ST_If].
- If the last rule was [ST_IfTrue], then [t' = t2]. But we
know that [|- t2 \in T], so we are done.
- If the last rule was [ST_IfFalse], then [t' = t3]. But we
know that [|- t3 \in T], so we are done.
- If the last rule was [ST_If], then [t' = if t1' then t2
else t3], where [t1 ==> t1']. We know [|- t1 \in Bool] so,
by the IH, [|- t1' \in Bool]. The [T_If] rule then gives us
[|- if t1' then t2 else t3 \in T], as required.
(* TODO: FILL IN HERE *)
[] *)
(** **** Exercise: 3 stars (preservation_alternate_proof) *)
(** Now prove the same property again by induction on the
_evaluation_ derivation instead of on the typing derivation.
Begin by carefully reading and thinking about the first few
lines of the above proof to make sure you understand what
each one is doing. The set-up for this proof is similar, but
not exactly the same. *)
Theorem preservation' : forall t t' T,
|- t \in T ->
t ==> t' ->
|- t' \in T.
Proof with eauto.
intros t t' T HT HE.
generalize dependent T.
step_cases (induction HE) Case;
intros; inversion HT; subst; auto.
inversion H1. assumption.
Qed.
(** [] *)
(* ###################################################################### *)
(** ** Type Soundness *)
(** Putting progress and preservation together, we can see that a
well-typed term can _never_ reach a stuck state. *)
Definition multistep := (multi step).
Notation "t1 '==>*' t2" := (multistep t1 t2) (at level 40).
Corollary soundness : forall t t' T,
|- t \in T ->
t ==>* t' ->
~(stuck t').
Proof.
intros t t' T HT P. induction P; intros [R S].
destruct (progress x T HT); auto.
apply IHP. apply (preservation x y T HT H).
unfold stuck. split; auto. Qed.
(* ###################################################################### *)
(** * Aside: the [normalize] Tactic *)
(** When experimenting with definitions of programming languages in
Coq, we often want to see what a particular concrete term steps
to -- i.e., we want to find proofs for goals of the form [t ==>*
t'], where [t] is a completely concrete term and [t'] is unknown.
These proofs are simple but repetitive to do by hand. Consider for
example reducing an arithmetic expression using the small-step
relation [astep]. *)
Definition amultistep st := multi (astep st).
Notation " t '/' st '==>a*' t' " := (amultistep st t t')
(at level 40, st at level 39).
Example astep_example1 :
(APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state
==>a* (ANum 15).
Proof.
apply multi_step with (APlus (ANum 3) (ANum 12)).
apply AS_Plus2.
apply av_num.
apply AS_Mult.
apply multi_step with (ANum 15).
apply AS_Plus.
apply multi_refl.
Qed.
(** We repeatedly apply [multi_step] until we get to a normal
form. The proofs that the intermediate steps are possible are
simple enough that [auto], with appropriate hints, can solve
them. *)
Hint Constructors astep aval.
Example astep_example1' :
(APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state
==>a* (ANum 15).
Proof.
eapply multi_step. auto. simpl.
eapply multi_step. auto. simpl.
apply multi_refl.
Qed.
(** The following custom [Tactic Notation] definition captures this
pattern. In addition, before each [multi_step] we print out the
current goal, so that the user can follow how the term is being
evaluated. *)
Tactic Notation "print_goal" := match goal with |- ?x => idtac x end.
Tactic Notation "normalize" :=
repeat (print_goal; eapply multi_step ;
[ (eauto 10; fail) | (instantiate; simpl)]);
apply multi_refl.
Example astep_example1'' :
(APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state
==>a* (ANum 15).
Proof.
normalize.
(* At this point in the proof script, the Coq response shows
a trace of how the expression evaluated.
(APlus (ANum 3) (AMult (ANum 3) (ANum 4)) / empty_state ==>a* ANum 15)
(multi (astep empty_state) (APlus (ANum 3) (ANum 12)) (ANum 15))
(multi (astep empty_state) (ANum 15) (ANum 15))
*)
Qed.
(** The [normalize] tactic also provides a simple way to calculate
what the normal form of a term is, by proving a goal with an
existential variable in it. *)
Example astep_example1''' : exists e',
(APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state
==>a* e'.
Proof.
eapply ex_intro. normalize.
(* This time, the trace will be:
(APlus (ANum 3) (AMult (ANum 3) (ANum 4)) / empty_state ==>a* ??)
(multi (astep empty_state) (APlus (ANum 3) (ANum 12)) ??)
(multi (astep empty_state) (ANum 15) ??)
where ?? is the variable ``guessed'' by eapply.
*)
Qed.
(** **** Exercise: 1 star (normalize_ex) *)
Theorem normalize_ex : exists e',
(AMult (ANum 3) (AMult (ANum 2) (ANum 1))) / empty_state
==>a* e'.
Proof.
eapply ex_intro. normalize.
Qed.
(** [] *)
(** **** Exercise: 1 star, optional (normalize_ex') *)
(** For comparison, prove it using [apply] instead of [eapply]. *)
Theorem normalize_ex' : exists e',
(AMult (ANum 3) (AMult (ANum 2) (ANum 1))) / empty_state
==>a* e'.
Proof.
apply ex_intro with (ANum 6). normalize.
Qed.
(** [] *)
(* ###################################################################### *)
(** ** Additional Exercises *)
(** **** Exercise: 2 stars (subject_expansion) *)
(** Having seen the subject reduction property, it is reasonable to
wonder whether the opposity property -- subject _expansion_ --
also holds. That is, is it always the case that, if [t ==> t']
and [|- t' \in T], then [|- t \in T]? If so, prove it. If
not, give a counter-example. (You do not need to prove your
counter-example in Coq, but feel free to do so if you like.)
*)
Theorem subject_expansion_fail : exists t t' T,
|- t' \in T ->
t ==> t' ->
~ |- t \in T.
Proof.
exists (tif ttrue ttrue tzero); exists (ttrue); exists (TBool).
intros. intro contra. inversion contra; subst. solve by inversion.
Qed.
(** [] *)
(** **** Exercise: 2 stars (variation1) *)
(** Suppose, that we add this new rule to the typing relation:
| T_SuccBool : forall t,
|- t \in TBool ->
|- tsucc t \in TBool
Which of the following properties remain true in the presence of
this rule? For each one, write either "remains true" or
else "becomes false." If a property becomes false, give a
counterexample.
- Determinism of [step]
Remain true. [step] is not modified.
- Progress
Becomes false. [tsucc true] is not value and also cannot be reduced.
- Preservation
Remain true. Works for this rule.
[] *)
(** **** Exercise: 2 stars (variation2) *)
(** Suppose, instead, that we add this new rule to the [step] relation:
| ST_Funny1 : forall t2 t3,
(tif ttrue t2 t3) ==> t3
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
- Determinism of [step]
if ttrue tzero ttrue ==> tzero
if ttrue tzero ttrue ==> ttrue
- Preservation
|- if ttrue tzero ttrue \in TNat
ttrue tzero ttrue ==> ttrue
|- ttrue \in TBool
[] *)
(** **** Exercise: 2 stars, optional (variation3) *)
(** Suppose instead that we add this rule:
| ST_Funny2 : forall t1 t2 t2' t3,
t2 ==> t2' ->
(tif t1 t2 t3) ==> (tif t1 t2' t3)
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
- Determinism of [step]
if (if ttrue ttrue ttrue) (if ttrue ttrue ttrue) ttrue ==>
if ttrue (if ttrue ttrue ttrue) ttrue
&
if (if ttrue ttrue ttrue) (if ttrue ttrue ttrue) ttrue ==>
if (if ttrue ttrue ttrue) ttrue ttrue
[] *)
(** **** Exercise: 2 stars, optional (variation4) *)
(** Suppose instead that we add this rule:
| ST_Funny3 :
(tpred tfalse) ==> (tpred (tpred tfalse))
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
All remain true. Mostly because this is not well-typed.
[] *)
(** **** Exercise: 2 stars, optional (variation5) *)
(** Suppose instead that we add this rule:
| T_Funny4 :
|- tzero \in TBool
]]
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
- Progress
[if tzero then tzero tzero] is not value and cannot be reduced.
- Preservation
|- if ttrue tzero tzero \in TNat
if ttrue tzero tzero ==> tzero
|- tzero \in TBool
[] *)
(** **** Exercise: 2 stars, optional (variation6) *)
(** Suppose instead that we add this rule:
| T_Funny5 :
|- tpred tzero \in TBool
]]
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
- Progress
[if (tpred tzero) then tzero tzero] is not value and cannot be reduced.
- Preservation
|- tpred tzero \in TBool
tpred tzero ==> tzero
|- tzero \in TNat
[] *)
(** **** Exercise: 3 stars, optional (more_variations) *)
(** Make up some exercises of your own along the same lines as
the ones above. Try to find ways of selectively breaking
properties -- i.e., ways of changing the definitions that
break just one of the properties and leave the others alone.
(* TODO: FILL IN HERE *)
[] *)
(** **** Exercise: 1 star (remove_predzero) *)
(** The evaluation rule [E_PredZero] is a bit counter-intuitive: we
might feel that it makes more sense for the predecessor of zero to
be undefined, rather than being defined to be zero. Can we
achieve this simply by removing the rule from the definition of
[step]? Would doing so create any problems elsewhere?
This will break the _progress_. [tpred tzero] is not a value and will be not able to be reduced.
[] *)
(** **** Exercise: 4 stars, advanced (prog_pres_bigstep) *)
(** Suppose our evaluation relation is defined in the big-step style.
What are the appropriate analogs of the progress and preservation
properties?
[progress] maybe something like [SKIP or ceval further]?
[preservation] and [hoare_consequence_pre] are pretty the same.
[] *)
(* $Date: 2014-11-13 13:12:50 -0500 (Thu, 13 Nov 2014) $ *)
|
`timescale 1ns / 1ps
module control_unit();
parameter ADDR_SIZE = 12;
parameter WORD_SIZE = 16;
reg sysclk;
initial begin //clock
sysclk <= 1'b1;
forever #1 sysclk = ~sysclk;
end
initial begin
$dumpfile("control_unit.vcd");
$dumpvars;
end
/*
* Instructions:
* 0: ACC := [S]
* 1: [S] := ACC
* 2: ACC:= ACC + [S]
* 3: ACC := ACC - [S]
* 4: PC := S
* 5: PC := S if ACC >=0
* 6: PC :=S if ACC != 0
* 7: HALT
* 8: [SP] := ACC, SP := SP + 1
* 9: ACC := [SP], SP := SP - 1
* a: IP := S, [SP] := IP, SP := SP + 1
* b: IP := [SP - 1], SP := SP - 1
* /
/*
* Specifications:
* posedge: exec
* negedge: fetch
*/
//Registers
reg [WORD_SIZE-1:0] acc;
reg [ADDR_SIZE-1:0] ip;
reg [WORD_SIZE-1:0] ir;
reg [ADDR_SIZE-1:0] sp;
//Memory
reg [ADDR_SIZE-1:0] mem_addr;
reg [WORD_SIZE-1:0] mem_in;
wire [WORD_SIZE-1:0] mem_out;
wire [WORD_SIZE-1:0] rom_out;
reg mem_write;
ram ram_blk(
.clk(sysclk),
.addr(mem_addr),
.data_in(mem_in),
.write_en(mem_write),
.data_out(mem_out),
.rom_addr(ip),
.rom_out(rom_out)
);
initial begin //default register values
ir <= 16'h4000;
ip <= 0;
sp <= 12'd191; //64 word stack
mem_addr <= 0;
mem_in <= 0;
mem_write <= 0;
acc <= 0;
end
//0/1 -> Fetch/Exec
reg state = 1;
//Determine pop operations
wire pop_op;
assign pop_op = (rom_out[WORD_SIZE-1:WORD_SIZE-4] == 4'h9)
| (rom_out[WORD_SIZE-1:WORD_SIZE-4] == 4'hb);
always @(posedge sysclk) begin
state <= ~state; //Alternate state
if (state) begin //Exec
case (ir[WORD_SIZE-1:WORD_SIZE-4])
4'h0: begin //ACC := [S]
acc <= mem_out;
end
4'h1: begin //[S] := ACC
mem_in <= acc;
mem_addr <= ir[WORD_SIZE-5:0];
mem_write <= 1;
end
4'h2: begin //ACC:= ACC + [S]
acc <= acc + mem_out;
end
4'h3: begin //ACC := ACC - [S]
acc <= acc - mem_out;
end
4'h4: begin // PC := S
ip <= ir[WORD_SIZE-5:0];
end
4'h5: begin //PC := S if ACC >=0
if (acc[WORD_SIZE-1] == 1'b0)
ip <= ir[WORD_SIZE-5:0];
end
4'h6: begin //PC := S if ACC != 0
if (acc != 8'd0)
ip <= ir[WORD_SIZE-5:0];
end
4'h7: begin // HALT
$finish;
end
4'h8: begin // [SP] := ACC, SP := SP + 1
mem_addr <= sp;
mem_in <= acc;
mem_write <= 1;
sp <= sp + 12'b1;
end
4'h9: begin // ACC := [SP - 1], SP := SP - 1
acc <= mem_out;
sp <= sp - 12'b1;
end
4'ha: begin // IP := S, [SP] := IP, SP := SP + 1
ip <= mem_addr ;
mem_addr <= sp;
mem_in <= ip;
mem_write <= 1;
sp <= sp + 12'b1;
end
4'hb: begin // IP := [SP - 1], SP := SP - 1
ip <= mem_out;
sp <= sp - 12'b1;
end
default: $finish;
endcase
end
else begin //Fetch
ir <= rom_out;
ip <= ip + 1;
mem_write <= 0;
//Get stack if pop/return
if (pop_op) //
mem_addr <= (sp - 12'b1);
else //Get memory
mem_addr <= rom_out[WORD_SIZE-5:0];
end
end
endmodule |
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: COMMAND_RAM.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module COMMAND_RAM (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [15:0] data;
input [10:0] rdaddress;
input [11:0] wraddress;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({32{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.numwords_b = 2048,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 12,
altsyncram_component.widthad_b = 11,
altsyncram_component.width_a = 16,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "65536"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 11 0 INPUT NODEFVAL "rdaddress[10..0]"
// Retrieval info: USED_PORT: wraddress 0 0 12 0 INPUT NODEFVAL "wraddress[11..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 12 0 wraddress 0 0 12 0
// Retrieval info: CONNECT: @address_b 0 0 11 0 rdaddress 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL COMMAND_RAM.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL COMMAND_RAM.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL COMMAND_RAM.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL COMMAND_RAM.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL COMMAND_RAM_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL COMMAND_RAM_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR3B_2_V
`define SKY130_FD_SC_LP__NOR3B_2_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog wrapper for nor3b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor3b_2 (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor3b_2 (
Y ,
A ,
B ,
C_N
);
output Y ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR3B_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND2_FUNCTIONAL_V
`define SKY130_FD_SC_LP__NAND2_FUNCTIONAL_V
/**
* nand2: 2-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__nand2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, B, A );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND2_FUNCTIONAL_V |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dbl_buf.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: dbl_buf
// Description: A simple double buffer
// First-in first-out. Asserts full when both entries
// are occupied.
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which
// contains the time scale definition
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module dbl_buf (/*AUTOARG*/
// Outputs
dout, vld, full,
// Inputs
clk, rst_l, wr, rd, din
);
// synopsys template
parameter BUF_WIDTH = 64; // width of the buffer
// Globals
input clk;
input rst_l;
// Buffer Input
input wr;
input rd;
input [BUF_WIDTH-1:0] din;
// Buffer Output
output [BUF_WIDTH-1:0] dout;
output vld;
output full;
// Buffer Output
wire wr_buf0;
wire wr_buf1;
wire buf0_vld;
wire buf1_vld;
wire buf1_older;
wire rd_buf0;
wire rd_buf1;
wire rd_buf;
wire en_vld0;
wire en_vld1;
wire [BUF_WIDTH-1:0] buf0_obj;
wire [BUF_WIDTH-1:0] buf1_obj;
////////////////////////////////////////////////////////////////////////
// Code starts here
////////////////////////////////////////////////////////////////////////
// if both entries are empty, write to entry pointed to by the older pointer
// if only one entry is empty, then write to the empty entry (duh!)
assign wr_buf0 = wr &
(buf1_vld | (~buf0_vld & ~buf1_older));
assign wr_buf1 = wr &
(buf0_vld | (~buf1_vld & buf1_older));
// read from the older entry
assign rd_buf0 = rd & ~buf1_older;
assign rd_buf1 = rd & buf1_older;
// flip older pointer when an entry is read
assign rd_buf = rd & (buf0_vld | buf1_vld);
dffrle_ns buf1_older_ff (.din(~buf1_older),
.rst_l(rst_l),
.en(rd_buf),
.clk(clk),
.q(buf1_older));
// set valid bit for writes and reset for reads
assign en_vld0 = wr_buf0 | rd_buf0;
assign en_vld1 = wr_buf1 | rd_buf1;
// the actual buffers
dffrle_ns buf0_vld_ff (.din(wr_buf0),
.rst_l(rst_l),
.en(en_vld0),
.clk(clk),
.q(buf0_vld));
dffrle_ns buf1_vld_ff (.din(wr_buf1),
.rst_l(rst_l),
.en(en_vld1),
.clk(clk),
.q(buf1_vld));
dffe_ns #(BUF_WIDTH) buf0_obj_ff (.din(din),
.en(wr_buf0),
.clk(clk),
.q(buf0_obj));
dffe_ns #(BUF_WIDTH) buf1_obj_ff (.din(din),
.en(wr_buf1),
.clk(clk),
.q(buf1_obj));
// mux out the older entry
assign dout = (buf1_older) ? buf1_obj:buf0_obj;
assign vld = buf0_vld | buf1_vld;
assign full = buf0_vld & buf1_vld;
endmodule // dbl_buf
// Local Variables:
// verilog-library-directories:(".")
// End:
|
// Listing 5.6
module debouncer
(
input wire clk, reset,
input wire sw,
output reg db
);
// symbolic state declaration
localparam [2:0]
zero = 3'b000,
wait1_1 = 3'b001,
wait1_2 = 3'b010,
wait1_3 = 3'b011,
one = 3'b100,
wait0_1 = 3'b101,
wait0_2 = 3'b110,
wait0_3 = 3'b111;
// number of counter bits (2^N * 20ns = 10ms tick)
localparam N =19;
// signal declaration
reg [N-1:0] q_reg;
wire [N-1:0] q_next;
wire m_tick;
reg [2:0] state_reg, state_next;
// body
//=============================================
// counter to generate 10 ms tick
//=============================================
always @(posedge clk)
q_reg <= q_next;
// next-state logic
assign q_next = q_reg + 1;
// output tick
assign m_tick = (q_reg==0) ? 1'b1 : 1'b0;
//=============================================
// debouncing FSM
//=============================================
// state register
always @(posedge clk, posedge reset)
if (reset)
state_reg <= zero;
else
state_reg <= state_next;
// next-state logic and output logic
always @*
begin
state_next = state_reg; // default state: the same
db = 1'b0; // default output: 0
case (state_reg)
zero:
if (sw)
state_next = wait1_1;
wait1_1:
if (~sw)
state_next = zero;
else
if (m_tick)
state_next = wait1_2;
wait1_2:
if (~sw)
state_next = zero;
else
if (m_tick)
state_next = wait1_3;
wait1_3:
if (~sw)
state_next = zero;
else
if (m_tick)
state_next = one;
one:
begin
db = 1'b1;
if (~sw)
state_next = wait0_1;
end
wait0_1:
begin
db = 1'b1;
if (sw)
state_next = one;
else
if (m_tick)
state_next = wait0_2;
end
wait0_2:
begin
db = 1'b1;
if (sw)
state_next = one;
else
if (m_tick)
state_next = wait0_3;
end
wait0_3:
begin
db = 1'b1;
if (sw)
state_next = one;
else
if (m_tick)
state_next = zero;
end
default: state_next = zero;
endcase
end
endmodule |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jun 04 00:41:32 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_rgb565_to_rgb888_0_0 -prefix
// system_rgb565_to_rgb888_0_0_ system_rgb565_to_rgb888_0_0_sim_netlist.v
// Design : system_rgb565_to_rgb888_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module system_rgb565_to_rgb888_0_0_rgb565_to_rgb888
(rgb_888,
rgb_565,
clk);
output [15:0]rgb_888;
input [15:0]rgb_565;
input clk;
wire clk;
wire [15:0]rgb_565;
wire [15:0]rgb_888;
FDRE \rgb_888_reg[10]
(.C(clk),
.CE(1'b1),
.D(rgb_565[5]),
.Q(rgb_888[5]),
.R(1'b0));
FDRE \rgb_888_reg[11]
(.C(clk),
.CE(1'b1),
.D(rgb_565[6]),
.Q(rgb_888[6]),
.R(1'b0));
FDRE \rgb_888_reg[12]
(.C(clk),
.CE(1'b1),
.D(rgb_565[7]),
.Q(rgb_888[7]),
.R(1'b0));
FDRE \rgb_888_reg[13]
(.C(clk),
.CE(1'b1),
.D(rgb_565[8]),
.Q(rgb_888[8]),
.R(1'b0));
FDRE \rgb_888_reg[14]
(.C(clk),
.CE(1'b1),
.D(rgb_565[9]),
.Q(rgb_888[9]),
.R(1'b0));
FDRE \rgb_888_reg[15]
(.C(clk),
.CE(1'b1),
.D(rgb_565[10]),
.Q(rgb_888[10]),
.R(1'b0));
FDRE \rgb_888_reg[19]
(.C(clk),
.CE(1'b1),
.D(rgb_565[11]),
.Q(rgb_888[11]),
.R(1'b0));
FDRE \rgb_888_reg[20]
(.C(clk),
.CE(1'b1),
.D(rgb_565[12]),
.Q(rgb_888[12]),
.R(1'b0));
FDRE \rgb_888_reg[21]
(.C(clk),
.CE(1'b1),
.D(rgb_565[13]),
.Q(rgb_888[13]),
.R(1'b0));
FDRE \rgb_888_reg[22]
(.C(clk),
.CE(1'b1),
.D(rgb_565[14]),
.Q(rgb_888[14]),
.R(1'b0));
FDRE \rgb_888_reg[23]
(.C(clk),
.CE(1'b1),
.D(rgb_565[15]),
.Q(rgb_888[15]),
.R(1'b0));
FDRE \rgb_888_reg[3]
(.C(clk),
.CE(1'b1),
.D(rgb_565[0]),
.Q(rgb_888[0]),
.R(1'b0));
FDRE \rgb_888_reg[4]
(.C(clk),
.CE(1'b1),
.D(rgb_565[1]),
.Q(rgb_888[1]),
.R(1'b0));
FDRE \rgb_888_reg[5]
(.C(clk),
.CE(1'b1),
.D(rgb_565[2]),
.Q(rgb_888[2]),
.R(1'b0));
FDRE \rgb_888_reg[6]
(.C(clk),
.CE(1'b1),
.D(rgb_565[3]),
.Q(rgb_888[3]),
.R(1'b0));
FDRE \rgb_888_reg[7]
(.C(clk),
.CE(1'b1),
.D(rgb_565[4]),
.Q(rgb_888[4]),
.R(1'b0));
endmodule
(* CHECK_LICENSE_TYPE = "system_rgb565_to_rgb888_0_0,rgb565_to_rgb888,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "rgb565_to_rgb888,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_rgb565_to_rgb888_0_0
(clk,
rgb_565,
rgb_888);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
input [15:0]rgb_565;
output [23:0]rgb_888;
wire \<const0> ;
wire clk;
wire [15:0]rgb_565;
wire [20:3]\^rgb_888 ;
assign rgb_888[23:21] = \^rgb_888 [18:16];
assign rgb_888[20:16] = \^rgb_888 [20:16];
assign rgb_888[15:14] = \^rgb_888 [9:8];
assign rgb_888[13:3] = \^rgb_888 [13:3];
assign rgb_888[2] = \<const0> ;
assign rgb_888[1] = \<const0> ;
assign rgb_888[0] = \<const0> ;
GND GND
(.G(\<const0> ));
system_rgb565_to_rgb888_0_0_rgb565_to_rgb888 U0
(.clk(clk),
.rgb_565(rgb_565),
.rgb_888({\^rgb_888 [18:16],\^rgb_888 [20:19],\^rgb_888 [9:8],\^rgb_888 [13:10],\^rgb_888 [7:3]}));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_int_example_driver (
// inputs:
clk,
local_rdata,
local_rdata_valid,
local_ready,
reset_n,
// outputs:
local_bank_addr,
local_be,
local_burstbegin,
local_col_addr,
local_cs_addr,
local_read_req,
local_row_addr,
local_size,
local_wdata,
local_write_req,
pnf_per_byte,
pnf_persist,
test_complete,
test_status
)
/* synthesis ALTERA_ATTRIBUTE = "MESSAGE_DISABLE=14130;MESSAGE_DISABLE=14110" */ ;
output [ 2: 0] local_bank_addr;
output [ 15: 0] local_be;
output local_burstbegin;
output [ 9: 0] local_col_addr;
output local_cs_addr;
output local_read_req;
output [ 13: 0] local_row_addr;
output [ 5: 0] local_size;
output [127: 0] local_wdata;
output local_write_req;
output [ 15: 0] pnf_per_byte;
output pnf_persist;
output test_complete;
output [ 7: 0] test_status;
input clk;
input [127: 0] local_rdata;
input local_rdata_valid;
input local_ready;
input reset_n;
wire [ 19: 0] COUNTER_VALUE;
wire [ 5: 0] LOCAL_BURST_LEN_s;
wire [ 2: 0] MAX_BANK;
wire MAX_CHIPSEL;
wire [ 9: 0] MAX_COL;
wire [ 13: 0] MAX_ROW;
wire [ 13: 0] MAX_ROW_PIN;
wire MIN_CHIPSEL;
wire [ 7: 0] addr_value;
wire avalon_burst_mode;
reg [ 2: 0] bank_addr;
reg [ 15: 0] be;
reg [ 5: 0] burst_beat_count;
reg burst_begin;
reg [ 9: 0] col_addr;
wire [ 15: 0] compare;
reg [ 15: 0] compare_reg;
reg [ 15: 0] compare_valid;
reg [ 15: 0] compare_valid_reg;
reg cs_addr;
wire [127: 0] dgen_data;
reg dgen_enable;
reg [127: 0] dgen_ldata;
reg dgen_load;
wire dgen_pause;
wire enable_be;
reg full_burst_on;
reg last_rdata_valid;
reg last_wdata_req;
wire [ 2: 0] local_bank_addr;
wire [ 15: 0] local_be;
wire local_burstbegin;
wire [ 9: 0] local_col_addr;
wire local_cs_addr;
wire local_read_req;
wire [ 13: 0] local_row_addr;
wire [ 5: 0] local_size;
wire [127: 0] local_wdata;
wire local_write_req;
wire [ 9: 0] max_col_value;
wire p_burst_begin;
wire p_read_req;
reg p_state_on;
wire pause_be;
wire [ 15: 0] pnf_per_byte;
reg pnf_persist;
reg pnf_persist1;
wire pnf_persist_compare;
wire powerdn_on;
reg rdata_valid_flag;
reg rdata_valid_flag_reg;
reg rdata_valid_flag_reg_2;
wire reached_max_address;
reg read_req;
reg [ 7: 0] reads_remaining;
reg reset_address;
reg reset_be;
reg reset_data;
wire restart_LFSR_n;
reg [ 13: 0] row_addr;
wire selfrfsh_on;
wire [ 5: 0] size;
reg [ 4: 0] state;
reg test_addr_pin;
reg test_addr_pin_mode;
wire test_addr_pin_on;
reg test_complete;
reg test_dm_pin;
reg test_dm_pin_mode;
wire test_dm_pin_on;
reg test_incomplete_writes;
reg test_incomplete_writes_mode;
wire test_incomplete_writes_on;
reg test_seq_addr;
reg test_seq_addr_mode;
wire test_seq_addr_on;
wire [ 7: 0] test_status;
reg wait_first_write_data;
wire [127: 0] wdata;
wire wdata_req;
reg write_req;
reg [ 7: 0] writes_remaining;
//
//Turn on this mode to test sequential address
assign test_seq_addr_on = 1'b1;
//Turn on this mode to test all address pins by a One-hot pattern address generator
assign test_addr_pin_on = 1'b1;
//Turn on this mode to make use of dm pins
assign test_dm_pin_on = 1'b1;
//This mode can only be used when LOCAL_BURST_LEN_s = 2
assign test_incomplete_writes_on = 1'b0;
//restart_LFSR_n is an active low signal, set it to 1'b0 to restart LFSR data generator after a complete test
assign restart_LFSR_n = 1'b1;
//Change COUNTER_VALUE to control the period of power down and self refresh mode
assign COUNTER_VALUE = 150;
//Change MAX_ROW to test more or lesser row address in test_seq_addr_mode, maximum value is 2^(row bits) -1, while minimum value is 0
assign MAX_ROW = 3;
//Change MAX_COL to test more or lesser column address in test_seq_addr_mode, maximum value is 2^(column bits) - (LOCAL_BURST_LEN_s * dwidth_ratio (aka half-rate (4) or full-rate (2))), while minimum value is 0 for Half rate and (LOCAL_BURST_LEN_s * dwidth_ratio) for Full rate
assign MAX_COL = 16;
//Decrease MAX_BANK to test lesser bank address, minimum value is 0
assign MAX_BANK = 7;
//Decrease MAX_CHIPSEL to test lesser memory chip, minimum value is MIN_CHIPSEL
assign MAX_CHIPSEL = 0;
//
assign MIN_CHIPSEL = 0;
assign MAX_ROW_PIN = {14{1'b1}};
assign max_col_value = ((addr_value == 4) == 0)? MAX_COL :
(MAX_COL + 4);
assign powerdn_on = 1'b0;
assign selfrfsh_on = 1'b0;
assign local_burstbegin = burst_begin | p_burst_begin;
assign avalon_burst_mode = 1;
//
//One hot decoder for test_status signal
assign test_status[0] = test_seq_addr_mode;
assign test_status[1] = test_incomplete_writes_mode;
assign test_status[2] = test_dm_pin_mode;
assign test_status[3] = test_addr_pin_mode;
assign test_status[4] = 0;
assign test_status[5] = 0;
assign test_status[6] = 0;
assign test_status[7] = test_complete;
assign p_read_req = 0;
assign p_burst_begin = 0;
assign local_cs_addr = cs_addr;
assign local_row_addr = row_addr;
assign local_bank_addr = bank_addr;
assign local_col_addr = col_addr;
assign local_write_req = write_req;
assign local_wdata = wdata;
assign local_read_req = read_req | p_read_req;
assign wdata = (reset_data == 0)? dgen_data :
128'd0;
//The LOCAL_BURST_LEN_s is a signal used insted of the parameter LOCAL_BURST_LEN
assign LOCAL_BURST_LEN_s = 2;
//LOCAL INTERFACE (AVALON)
assign wdata_req = write_req & local_ready;
// Generate new data (enable lfsr) when writing or reading valid data
assign dgen_pause = ~ ((wdata_req & ~reset_data) | (local_rdata_valid));
assign enable_be = (wdata_req & test_dm_pin_mode & ~reset_data) | (test_dm_pin_mode & local_rdata_valid);
assign pnf_per_byte = compare_valid_reg;
assign pause_be = (reset_data & test_dm_pin_mode) | ~test_dm_pin_mode;
assign local_be = be;
assign local_size = size;
assign size = (full_burst_on == 0)? 1'd1 :
LOCAL_BURST_LEN_s[5 : 0];
assign reached_max_address = ((test_dm_pin_mode | test_addr_pin_mode | state == 5'd9) & (row_addr == MAX_ROW_PIN)) || ((test_seq_addr_mode | test_incomplete_writes_mode) & (col_addr == (max_col_value)) & (row_addr == MAX_ROW) & (bank_addr == MAX_BANK) & (cs_addr == MAX_CHIPSEL));
assign addr_value = ((test_incomplete_writes_mode & write_req & ~full_burst_on) == 0)? 8 :
4;
assign pnf_persist_compare = (rdata_valid_flag_reg_2 == 0)? 1'd1 :
pnf_persist1;
ddr3_int_ex_lfsr8 LFSRGEN_0_lfsr_inst
(
.clk (clk),
.data (dgen_data[7 : 0]),
.enable (dgen_enable),
.ldata (dgen_ldata[7 : 0]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_0_lfsr_inst.seed = 1;
// 8 bit comparator per local byte lane
assign compare[0] = (dgen_data[7 : 0] & {8 {be[0]}}) === local_rdata[7 : 0];
ddr3_int_ex_lfsr8 LFSRGEN_1_lfsr_inst
(
.clk (clk),
.data (dgen_data[15 : 8]),
.enable (dgen_enable),
.ldata (dgen_ldata[15 : 8]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_1_lfsr_inst.seed = 11;
// 8 bit comparator per local byte lane
assign compare[1] = (dgen_data[15 : 8] & {8 {be[1]}}) === local_rdata[15 : 8];
ddr3_int_ex_lfsr8 LFSRGEN_2_lfsr_inst
(
.clk (clk),
.data (dgen_data[23 : 16]),
.enable (dgen_enable),
.ldata (dgen_ldata[23 : 16]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_2_lfsr_inst.seed = 21;
// 8 bit comparator per local byte lane
assign compare[2] = (dgen_data[23 : 16] & {8 {be[2]}}) === local_rdata[23 : 16];
ddr3_int_ex_lfsr8 LFSRGEN_3_lfsr_inst
(
.clk (clk),
.data (dgen_data[31 : 24]),
.enable (dgen_enable),
.ldata (dgen_ldata[31 : 24]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_3_lfsr_inst.seed = 31;
// 8 bit comparator per local byte lane
assign compare[3] = (dgen_data[31 : 24] & {8 {be[3]}}) === local_rdata[31 : 24];
ddr3_int_ex_lfsr8 LFSRGEN_4_lfsr_inst
(
.clk (clk),
.data (dgen_data[39 : 32]),
.enable (dgen_enable),
.ldata (dgen_ldata[39 : 32]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_4_lfsr_inst.seed = 41;
// 8 bit comparator per local byte lane
assign compare[4] = (dgen_data[39 : 32] & {8 {be[4]}}) === local_rdata[39 : 32];
ddr3_int_ex_lfsr8 LFSRGEN_5_lfsr_inst
(
.clk (clk),
.data (dgen_data[47 : 40]),
.enable (dgen_enable),
.ldata (dgen_ldata[47 : 40]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_5_lfsr_inst.seed = 51;
// 8 bit comparator per local byte lane
assign compare[5] = (dgen_data[47 : 40] & {8 {be[5]}}) === local_rdata[47 : 40];
ddr3_int_ex_lfsr8 LFSRGEN_6_lfsr_inst
(
.clk (clk),
.data (dgen_data[55 : 48]),
.enable (dgen_enable),
.ldata (dgen_ldata[55 : 48]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_6_lfsr_inst.seed = 61;
// 8 bit comparator per local byte lane
assign compare[6] = (dgen_data[55 : 48] & {8 {be[6]}}) === local_rdata[55 : 48];
ddr3_int_ex_lfsr8 LFSRGEN_7_lfsr_inst
(
.clk (clk),
.data (dgen_data[63 : 56]),
.enable (dgen_enable),
.ldata (dgen_ldata[63 : 56]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_7_lfsr_inst.seed = 71;
// 8 bit comparator per local byte lane
assign compare[7] = (dgen_data[63 : 56] & {8 {be[7]}}) === local_rdata[63 : 56];
ddr3_int_ex_lfsr8 LFSRGEN_8_lfsr_inst
(
.clk (clk),
.data (dgen_data[71 : 64]),
.enable (dgen_enable),
.ldata (dgen_ldata[71 : 64]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_8_lfsr_inst.seed = 81;
// 8 bit comparator per local byte lane
assign compare[8] = (dgen_data[71 : 64] & {8 {be[8]}}) === local_rdata[71 : 64];
ddr3_int_ex_lfsr8 LFSRGEN_9_lfsr_inst
(
.clk (clk),
.data (dgen_data[79 : 72]),
.enable (dgen_enable),
.ldata (dgen_ldata[79 : 72]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_9_lfsr_inst.seed = 91;
// 8 bit comparator per local byte lane
assign compare[9] = (dgen_data[79 : 72] & {8 {be[9]}}) === local_rdata[79 : 72];
ddr3_int_ex_lfsr8 LFSRGEN_10_lfsr_inst
(
.clk (clk),
.data (dgen_data[87 : 80]),
.enable (dgen_enable),
.ldata (dgen_ldata[87 : 80]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_10_lfsr_inst.seed = 101;
// 8 bit comparator per local byte lane
assign compare[10] = (dgen_data[87 : 80] & {8 {be[10]}}) === local_rdata[87 : 80];
ddr3_int_ex_lfsr8 LFSRGEN_11_lfsr_inst
(
.clk (clk),
.data (dgen_data[95 : 88]),
.enable (dgen_enable),
.ldata (dgen_ldata[95 : 88]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_11_lfsr_inst.seed = 111;
// 8 bit comparator per local byte lane
assign compare[11] = (dgen_data[95 : 88] & {8 {be[11]}}) === local_rdata[95 : 88];
ddr3_int_ex_lfsr8 LFSRGEN_12_lfsr_inst
(
.clk (clk),
.data (dgen_data[103 : 96]),
.enable (dgen_enable),
.ldata (dgen_ldata[103 : 96]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_12_lfsr_inst.seed = 121;
// 8 bit comparator per local byte lane
assign compare[12] = (dgen_data[103 : 96] & {8 {be[12]}}) === local_rdata[103 : 96];
ddr3_int_ex_lfsr8 LFSRGEN_13_lfsr_inst
(
.clk (clk),
.data (dgen_data[111 : 104]),
.enable (dgen_enable),
.ldata (dgen_ldata[111 : 104]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_13_lfsr_inst.seed = 131;
// 8 bit comparator per local byte lane
assign compare[13] = (dgen_data[111 : 104] & {8 {be[13]}}) === local_rdata[111 : 104];
ddr3_int_ex_lfsr8 LFSRGEN_14_lfsr_inst
(
.clk (clk),
.data (dgen_data[119 : 112]),
.enable (dgen_enable),
.ldata (dgen_ldata[119 : 112]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_14_lfsr_inst.seed = 141;
// 8 bit comparator per local byte lane
assign compare[14] = (dgen_data[119 : 112] & {8 {be[14]}}) === local_rdata[119 : 112];
ddr3_int_ex_lfsr8 LFSRGEN_15_lfsr_inst
(
.clk (clk),
.data (dgen_data[127 : 120]),
.enable (dgen_enable),
.ldata (dgen_ldata[127 : 120]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_15_lfsr_inst.seed = 151;
// 8 bit comparator per local byte lane
assign compare[15] = (dgen_data[127 : 120] & {8 {be[15]}}) === local_rdata[127 : 120];
//
//-----------------------------------------------------------------
//Main clocked process
//-----------------------------------------------------------------
//Read / Write control state machine & address counter
//-----------------------------------------------------------------
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
//Reset - asynchronously force all register outputs LOW
state <= 5'd0;
write_req <= 1'b0;
read_req <= 1'b0;
burst_begin <= 1'b0;
burst_beat_count <= 0;
dgen_load <= 1'b0;
wait_first_write_data <= 1'b0;
test_complete <= 1'b0;
reset_data <= 1'b0;
reset_be <= 1'b0;
writes_remaining <= 0;
reads_remaining <= 0;
test_addr_pin <= 1'b0;
test_dm_pin <= 1'b0;
test_seq_addr <= 1'b0;
test_incomplete_writes <= 1'b0;
test_addr_pin_mode <= 1'b0;
test_dm_pin_mode <= 1'b0;
test_seq_addr_mode <= 1'b0;
test_incomplete_writes_mode <= 1'b0;
full_burst_on <= 1'b1;
p_state_on <= 1'b0;
dgen_enable <= 1'b1;
end
else
begin
if (write_req & local_ready)
begin
if (wdata_req)
writes_remaining <= writes_remaining + (size - 1);
else
writes_remaining <= writes_remaining + size;
end
else if ((wdata_req) & (writes_remaining > 0))
//size
writes_remaining <= writes_remaining - 1'b1;
else
writes_remaining <= writes_remaining;
if ((read_req | p_read_req) & local_ready)
begin
if (local_rdata_valid)
reads_remaining <= reads_remaining + (size - 1);
else
reads_remaining <= reads_remaining + size;
end
else if ((local_rdata_valid) & (reads_remaining > 0))
reads_remaining <= reads_remaining - 1'b1;
else
reads_remaining <= reads_remaining;
case (state)
5'd0: begin
test_addr_pin <= test_addr_pin_on;
test_dm_pin <= test_dm_pin_on;
test_seq_addr <= test_seq_addr_on;
test_incomplete_writes <= test_incomplete_writes_on;
test_complete <= 1'b0;
state <= 5'd1;
end // 5'd0
5'd1: begin
//Reset just in case!
reset_address <= 1'b0;
reset_be <= 1'b0;
write_req <= 1'b1;
writes_remaining <= 1'b0;
reads_remaining <= 1'b0;
wait_first_write_data <= 1'b1;
dgen_enable <= 1'b1;
if (test_seq_addr == 1'b1)
begin
test_seq_addr_mode <= 1;
if (avalon_burst_mode == 0)
begin
state <= 5'd5;
burst_begin <= 1'b1;
end
else if (avalon_burst_mode == 1)
begin
state <= 5'd13;
burst_begin <= 1'b1;
end
end
else if (test_incomplete_writes == 1'b1)
begin
full_burst_on <= 1'b0;
test_incomplete_writes_mode <= 1;
state <= 5'd5;
if (avalon_burst_mode == 1)
burst_begin <= 1'b1;
end
else if (test_dm_pin == 1'b1)
begin
reset_data <= 1'b1;
test_dm_pin_mode <= 1;
if (avalon_burst_mode == 0)
begin
burst_begin <= 1'b1;
state <= 5'd2;
end
else
begin
burst_begin <= 1'b1;
state <= 5'd10;
end
end
else if (test_addr_pin == 1'b1)
begin
test_addr_pin_mode <= 1;
if (avalon_burst_mode == 0)
begin
burst_begin <= 1'b1;
state <= 5'd5;
end
else if (avalon_burst_mode == 1)
begin
state <= 5'd13;
burst_begin <= 1'b1;
end
end
else
begin
write_req <= 1'b0;
wait_first_write_data <= 1'b0;
state <= 5'd9;
end
end // 5'd1
5'd10: begin
wait_first_write_data <= 1'b0;
burst_begin <= 1'b0;
if (write_req & local_ready)
begin
burst_beat_count <= burst_beat_count + 1'b1;
state <= 5'd11;
end
end // 5'd10
5'd11: begin
if (write_req & local_ready)
if (burst_beat_count == size - 1'b1)
begin
burst_beat_count <= 0;
burst_begin <= 1'b1;
if (reached_max_address)
state <= 5'd12;
else
state <= 5'd10;
end
else
burst_beat_count <= burst_beat_count + 1'b1;
end // 5'd11
5'd12: begin
burst_begin <= 1'b0;
if (write_req & local_ready)
state <= 5'd3;
end // 5'd12
5'd13: begin
wait_first_write_data <= 1'b0;
burst_begin <= 1'b0;
reset_be <= 1'b0;
if (write_req & local_ready)
begin
burst_beat_count <= burst_beat_count + 1'b1;
state <= 5'd14;
end
end // 5'd13
5'd14: begin
if (write_req & local_ready)
if (burst_beat_count == size - 1'b1)
begin
burst_beat_count <= 0;
burst_begin <= 1'b1;
if (reached_max_address)
state <= 5'd15;
else
state <= 5'd13;
end
else
burst_beat_count <= burst_beat_count + 1'b1;
end // 5'd14
5'd15: begin
if (write_req & local_ready)
begin
reset_address <= 1'b1;
burst_begin <= 1'b0;
state <= 5'd6;
end
end // 5'd15
5'd16: begin
dgen_load <= 1'b0;
reset_be <= 1'b0;
if (local_ready & read_req)
if (reached_max_address)
begin
read_req <= 1'b0;
burst_begin <= 1'b0;
state <= 5'd8;
end
end // 5'd16
5'd2: begin
wait_first_write_data <= 1'b0;
if (write_req & local_ready)
if (reached_max_address)
begin
write_req <= 1'b0;
burst_begin <= 1'b0;
state <= 5'd3;
end
end // 5'd2
5'd3: begin
if (avalon_burst_mode == 0)
begin
if (!wdata_req)
if (writes_remaining == 0)
begin
reset_be <= 1'b1;
reset_address <= 1'b1;
dgen_load <= 1'b1;
state <= 5'd4;
end
end
else if (write_req & local_ready)
begin
reset_be <= 1'b1;
write_req <= 1'b0;
reset_address <= 1'b1;
dgen_load <= 1'b1;
state <= 5'd4;
end
end // 5'd3
5'd4: begin
reset_address <= 1'b0;
dgen_load <= 1'b0;
reset_be <= 1'b0;
reset_data <= 1'b0;
write_req <= 1'b1;
if (avalon_burst_mode == 0)
begin
burst_begin <= 1'b1;
state <= 5'd5;
end
else
begin
burst_begin <= 1'b1;
state <= 5'd13;
end
end // 5'd4
5'd5: begin
wait_first_write_data <= 1'b0;
if (write_req & local_ready)
if (reached_max_address)
begin
reset_address <= 1'b1;
write_req <= 1'b0;
burst_begin <= 1'b0;
state <= 5'd6;
if (test_incomplete_writes_mode)
full_burst_on <= 1'b1;
end
end // 5'd5
5'd6: begin
reset_address <= 1'b0;
if (avalon_burst_mode == 0)
begin
if (writes_remaining == 0)
begin
dgen_load <= 1'b1;
reset_be <= 1'b1;
read_req <= 1'b1;
burst_begin <= 1'b1;
state <= 5'd7;
end
end
else if (test_incomplete_writes_mode)
begin
dgen_load <= 1'b1;
read_req <= 1'b1;
burst_begin <= 1'b1;
state <= 5'd16;
end
else if (write_req & local_ready)
begin
write_req <= 1'b0;
dgen_load <= 1'b1;
reset_be <= 1'b1;
read_req <= 1'b1;
burst_begin <= 1'b1;
state <= 5'd16;
end
end // 5'd6
5'd7: begin
dgen_load <= 1'b0;
reset_be <= 1'b0;
if (local_ready & read_req)
if (reached_max_address)
begin
read_req <= 1'b0;
burst_begin <= 1'b0;
state <= 5'd8;
end
end // 5'd7
5'd8: begin
if (reads_remaining == 1'b0)
begin
reset_address <= 1'b1;
if (test_seq_addr)
begin
test_seq_addr <= 1'b0;
test_seq_addr_mode <= 1'b0;
state <= 5'd1;
end
else if (test_incomplete_writes)
begin
test_incomplete_writes <= 1'b0;
test_incomplete_writes_mode <= 1'b0;
state <= 5'd1;
end
else if (test_dm_pin)
begin
test_dm_pin <= 1'b0;
test_dm_pin_mode <= 1'b0;
state <= 5'd1;
end
else if (test_addr_pin)
begin
test_addr_pin_mode <= 1'b0;
dgen_load <= 1'b1;
state <= 5'd9;
end
else
state <= 5'd9;
end
end // 5'd8
5'd9: begin
reset_address <= 1'b0;
reset_be <= 1'b0;
dgen_load <= 1'b0;
if (powerdn_on == 1'b0 & selfrfsh_on == 1'b0)
begin
test_complete <= 1'b1;
p_state_on <= 1'b0;
dgen_enable <= restart_LFSR_n;
state <= 5'd0;
end
else if (reached_max_address & reads_remaining == 0)
begin
p_state_on <= 1'b1;
reset_address <= 1'b1;
reset_be <= 1'b1;
dgen_load <= 1'b1;
end
end // 5'd9
endcase // state
end
end
//
//-----------------------------------------------------------------
//Logics that detect the first read data
//-----------------------------------------------------------------
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rdata_valid_flag <= 1'b0;
else if (local_rdata_valid)
rdata_valid_flag <= 1'b1;
end
//
//-----------------------------------------------------------------
//Address Generator Process
//-----------------------------------------------------------------
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
cs_addr <= 0;
bank_addr <= 0;
row_addr <= 0;
col_addr <= 0;
end
else if (reset_address)
begin
cs_addr <= MIN_CHIPSEL;
row_addr <= 0;
bank_addr <= 0;
col_addr <= 0;
end
else if (((local_ready & write_req & (test_dm_pin_mode | test_addr_pin_mode)) & (state == 5'd2 | state == 5'd5 | state == 5'd10 | state == 5'd13)) | ((local_ready & read_req & (test_dm_pin_mode | test_addr_pin_mode)) & (state == 5'd7 | state == 5'd16)) | ((local_ready & p_read_req) & (state == 5'd9)))
begin
col_addr[9 : 3] <= {col_addr[8 : 3],col_addr[9]};
row_addr[13 : 0] <= {row_addr[12 : 0],row_addr[13]};
if (row_addr == 14'd0)
begin
col_addr <= 10'd8;
row_addr <= 14'd1;
end
else if (row_addr == {1'b1,{13{1'b0}}})
begin
col_addr <= {{6{1'b1}},{4{1'b0}}};
row_addr <= {{13{1'b1}},1'b0};
end
else if (row_addr == {1'b0,{13{1'b1}}})
begin
col_addr <= {{7{1'b1}},{3{1'b0}}};
row_addr <= {14{1'b1}};
end
if (bank_addr == MAX_BANK)
bank_addr <= 0;
else
bank_addr <= bank_addr + 1'b1;
if (cs_addr == MAX_CHIPSEL)
cs_addr <= MIN_CHIPSEL;
else
cs_addr <= cs_addr + 1'b1;
end
else if ((local_ready & write_req & (test_seq_addr_mode | test_incomplete_writes_mode) & (state == 5'd2 | state == 5'd5 | state == 5'd10 | state == 5'd13)) | ((local_ready & read_req & (test_seq_addr_mode | test_incomplete_writes_mode)) & (state == 5'd7 | state == 5'd16)))
if (col_addr >= max_col_value)
begin
col_addr <= 0;
if (row_addr == MAX_ROW)
begin
row_addr <= 0;
if (bank_addr == MAX_BANK)
begin
bank_addr <= 0;
if (cs_addr == MAX_CHIPSEL)
//reached_max_count <= TRUE
//(others => '0')
cs_addr <= MIN_CHIPSEL;
else
cs_addr <= cs_addr + 1'b1;
end
else
bank_addr <= bank_addr + 1'b1;
end
else
row_addr <= row_addr + 1'b1;
end
else
col_addr <= col_addr + addr_value;
end
//
//-----------------------------------------------------------------
//Byte Enable Generator Process
//-----------------------------------------------------------------
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
be <= {16{1'b1}};
else if (reset_be)
be <= 16'd1;
else if (enable_be)
be[15 : 0] <= {be[14 : 0],be[15]};
else if (pause_be)
be <= {16{1'b1}};
else
be <= be;
end
//------------------------------------------------------------
//LFSR re-load data storage
//Comparator masking and test pass signal generation
//------------------------------------------------------------
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
dgen_ldata <= 0;
last_wdata_req <= 1'b0;
//all ones
compare_valid <= {16 {1'b1}};
//all ones
compare_valid_reg <= {16 {1'b1}};
pnf_persist <= 1'b0;
pnf_persist1 <= 1'b0;
//all ones
compare_reg <= {16 {1'b1}};
last_rdata_valid <= 1'b0;
rdata_valid_flag_reg <= 1'b0;
rdata_valid_flag_reg_2 <= 1'b0;
end
else
begin
last_wdata_req <= wdata_req;
last_rdata_valid <= local_rdata_valid;
rdata_valid_flag_reg <= rdata_valid_flag;
rdata_valid_flag_reg_2 <= rdata_valid_flag_reg;
compare_reg <= compare;
if (wait_first_write_data)
dgen_ldata <= dgen_data;
//Enable the comparator result when read data is valid
if (last_rdata_valid)
compare_valid <= compare_reg;
//Create the overall persistent passnotfail output
if (&compare_valid & rdata_valid_flag_reg & pnf_persist_compare)
pnf_persist1 <= 1'b1;
else
pnf_persist1 <= 1'b0;
//Extra register stage to help Tco / Fmax on comparator output pins
compare_valid_reg <= compare_valid;
pnf_persist <= pnf_persist1;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR3_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__NOR3_PP_BLACKBOX_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nor3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR3_PP_BLACKBOX_V
|
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