input
stringlengths 144
489k
| output
stringlengths 45
339k
| shard
stringclasses 16
values | filename
stringlengths 135
135
| line_num
int64 0
2.62k
| context
list |
|---|---|---|---|---|---|
{"name": "gen_op_tsub_ccTV", "code": "unsigned __int64 __fastcall gen_op_tsub_ccTV ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; tcg_gen_mov_i64 ( cpu_cc_src , @@a2@@ ) ; tcg_gen_mov_i64 ( cpu_cc_src2 , @@a3@@ ) ; gen_tag_tv ( cpu_cc_src , cpu_cc_src2 ) ; tcg_gen_sub_i64 ( cpu_cc_dst , cpu_cc_src , cpu_cc_src2 ) ; gen_sub_tv ( cpu_cc_dst , cpu_cc_src , cpu_cc_src2 ) ; tcg_gen_mov_i64 ( @@a1@@ , cpu_cc_dst ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v5", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "src2", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r16"}, {"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src1", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 244 |
[
"{\"name\": \"tcg_gen_mov_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_mov_i64 ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; if ( @@a1@@ != @@a2@@ ) tcg_gen_op2_i64 ( Number , @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_sub_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_sub_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_tag_tv\", \"code\": \"unsigned __int64 __fastcall gen_tag_tv ( int @@a1@@ , int @@a2@@ ) { int @@v3@@ ; unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v3@@ = gen_new_label ( ) ; tcg_gen_or_i64 ( cpu_tmp0 , @@a1@@ , @@a2@@ ) ; tcg_gen_andi_i64 ( cpu_tmp0 , cpu_tmp0 , Number L ) ; tcg_gen_brcondi_i64 ( Number , cpu_tmp0 , Number L , @@v3@@ ) ; @@v4@@ = tcg_const_i32 ( Number L ) ; gen_helper_raise_exception ( @@v4@@ ) ; tcg_temp_free_i32 ( @@v4@@ ) ; gen_set_label ( @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_sub_tv\", \"code\": \"unsigned __int64 __fastcall gen_sub_tv ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { int @@v5@@ ; unsigned int @@v6@@ ; unsigned int @@v7@@ ; unsigned __int64 @@v8@@ ; @@v8@@ = __readfsqword ( Number ) ; @@v5@@ = gen_new_label ( ) ; @@v6@@ = tcg_temp_new_i64 ( ) ; tcg_gen_xor_i64 ( @@v6@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_xor_i64 ( cpu_tmp0 , @@a2@@ , @@a1@@ ) ; tcg_gen_and_i64 ( @@v6@@ , @@v6@@ , cpu_tmp0 ) ; tcg_gen_andi_i64 ( @@v6@@ , @@v6@@ , Number ) ; tcg_gen_brcondi_i64 ( Number , @@v6@@ , Number L , @@v5@@ ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; gen_helper_raise_exception ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; gen_set_label ( @@v5@@ ) ; tcg_temp_free_i64 ( @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v8@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s20\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_tsub_cc\", \"code\": \"unsigned __int64 __fastcall gen_op_tsub_cc ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; tcg_gen_mov_i64 ( cpu_cc_src , @@a2@@ ) ; tcg_gen_mov_i64 ( cpu_cc_src2 , @@a3@@ ) ; tcg_gen_sub_i64 ( cpu_cc_dst , cpu_cc_src , cpu_cc_src2 ) ; tcg_gen_mov_i64 ( @@a1@@ , cpu_cc_dst ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_mulscc", "code": "unsigned __int64 __fastcall gen_op_mulscc ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { int @@v5@@ ; unsigned int @@v6@@ ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v5@@ = gen_new_label ( ) ; @@v6@@ = tcg_temp_new_i64 ( ) ; tcg_gen_andi_i64 ( cpu_cc_src , @@a2@@ , Number ) ; tcg_gen_andi_i64 ( @@v6@@ , cpu_y , Number L ) ; tcg_gen_andi_i64 ( cpu_cc_src2 , @@a3@@ , Number ) ; tcg_gen_brcondi_i64 ( Number , @@v6@@ , Number L , @@v5@@ ) ; tcg_gen_movi_i64 ( cpu_cc_src2 , Number L ) ; gen_set_label ( @@v5@@ ) ; tcg_gen_andi_i64 ( @@v6@@ , cpu_cc_src , Number L ) ; tcg_gen_shli_i64 ( @@v6@@ , @@v6@@ , Number L ) ; tcg_gen_shri_i64 ( cpu_tmp0 , cpu_y , Number L ) ; tcg_gen_andi_i64 ( cpu_tmp0 , cpu_tmp0 , Number ) ; tcg_gen_or_i64 ( cpu_tmp0 , cpu_tmp0 , @@v6@@ ) ; tcg_gen_andi_i64 ( cpu_y , cpu_tmp0 , Number ) ; gen_mov_reg_N ( cpu_tmp0 , cpu_psr ) ; gen_mov_reg_V ( @@v6@@ , cpu_psr ) ; tcg_gen_xor_i64 ( cpu_tmp0 , cpu_tmp0 , @@v6@@ ) ; tcg_temp_free_i64 ( @@v6@@ ) ; tcg_gen_shli_i64 ( cpu_tmp0 , cpu_tmp0 , Number L ) ; tcg_gen_shri_i64 ( cpu_cc_src , cpu_cc_src , Number L ) ; tcg_gen_or_i64 ( cpu_cc_src , cpu_cc_src , cpu_tmp0 ) ; tcg_gen_add_i64 ( cpu_cc_dst , cpu_cc_src , cpu_cc_src2 ) ; tcg_gen_mov_i64 ( @@a1@@ , cpu_cc_dst ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v6", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "v5", "t": {"T": 1, "n": "int", "s": 4}, "location": "s16"}, {"n": "v7", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "src2", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r16"}, {"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src1", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "r_temp", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "l1", "t": {"T": 1, "n": "int", "s": 4}, "location": "s16"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 245 |
[
"{\"name\": \"gen_set_label\", \"code\": \"unsigned __int64 __fastcall gen_set_label ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_op1i ( Number , @@a1@@ ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_br\", \"code\": \"unsigned __int64 __fastcall tcg_gen_br ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_op1i ( Number , @@a1@@ ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_mov_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_mov_i64 ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; if ( @@a1@@ != @@a2@@ ) tcg_gen_op2_i64 ( Number , @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_movi_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_movi_i64 ( int @@a1@@ , __int64 @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; tcg_gen_op2i_i64 ( Number , @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_add_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_add_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_andi_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_andi_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_and_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_or_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_or_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; if ( @@a2@@ == @@a3@@ ) tcg_gen_mov_i64 ( @@a1@@ , @@a2@@ ) ; else tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_xor_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_xor_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; if ( @@a2@@ == @@a3@@ ) tcg_gen_movi_i64 ( @@a1@@ , Number L ) ; else tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_shli_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_shli_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; if ( @@a3@@ ) { @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_shl_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; } else { tcg_gen_mov_i64 ( @@a1@@ , @@a2@@ ) ; } return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_shri_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_shri_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; if ( @@a3@@ ) { @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_shr_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; } else { tcg_gen_mov_i64 ( @@a1@@ , @@a2@@ ) ; } return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_brcondi_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_brcondi_i64 ( unsigned int @@a1@@ , int @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { unsigned int @@v6@@ ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_brcond_i64 ( @@a1@@ , @@a2@@ , @@v6@@ , @@a4@@ ) ; tcg_temp_free_i64 ( @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_N\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_N ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_extu_i32_i64 ( @@a1@@ , @@a2@@ ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a1@@ , Number L ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_V\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_V ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_extu_i32_i64 ( @@a1@@ , @@a2@@ ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a1@@ , Number L ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_multiply", "code": "unsigned __int64 __fastcall gen_op_multiply ( int @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ ) { unsigned int @@v7@@ ; unsigned int @@v8@@ ; unsigned int @@v9@@ ; unsigned int @@v10@@ ; unsigned __int64 @@v11@@ ; @@v11@@ = __readfsqword ( Number ) ; @@v7@@ = tcg_temp_new_i32 ( ) ; @@v8@@ = tcg_temp_new_i32 ( ) ; tcg_gen_trunc_i64_i32 ( @@v7@@ , @@a2@@ ) ; tcg_gen_trunc_i64_i32 ( @@v8@@ , @@a3@@ ) ; @@v9@@ = tcg_temp_new_i64 ( ) ; @@v10@@ = tcg_temp_new_i64 ( ) ; if ( @@a4@@ ) { tcg_gen_ext_i32_i64 ( @@v9@@ , @@v8@@ ) ; tcg_gen_ext_i32_i64 ( @@v10@@ , @@v7@@ ) ; } else { tcg_gen_extu_i32_i64 ( @@v9@@ , @@v8@@ ) ; tcg_gen_extu_i32_i64 ( @@v10@@ , @@v7@@ ) ; } tcg_gen_mul_i64 ( @@v10@@ , @@v9@@ , @@v10@@ ) ; tcg_gen_shri_i64 ( @@v9@@ , @@v10@@ , Number L ) ; tcg_gen_mov_i64 ( cpu_tmp0 , @@v9@@ ) ; tcg_temp_free_i64 ( @@v9@@ ) ; tcg_gen_andi_i64 ( cpu_y , cpu_tmp0 , Number ) ; tcg_gen_mov_i64 ( @@a1@@ , @@v10@@ ) ; tcg_temp_free_i64 ( @@v10@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v11@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v10", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "v9", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s16"}, {"n": "v8", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s20"}, {"n": "v7", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s24"}, {"n": "v11", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "src2", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r16"}, {"n": "sign_ext", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src1", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "r_temp2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "r_temp", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s16"}, {"n": "r_src2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s20"}, {"n": "r_src1", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s24"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 246 |
[
"{\"name\": \"tcg_gen_mov_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_mov_i64 ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; if ( @@a1@@ != @@a2@@ ) tcg_gen_op2_i64 ( Number , @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_andi_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_andi_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_and_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_shri_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_shri_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; if ( @@a3@@ ) { @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_shr_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; } else { tcg_gen_mov_i64 ( @@a1@@ , @@a2@@ ) ; } return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_mul_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_mul_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_trunc_i64_i32\", \"code\": \"unsigned __int64 __fastcall tcg_gen_trunc_i64_i32 ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; tcg_gen_mov_i32 ( @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_extu_i32_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_extu_i32_i64 ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; tcg_gen_ext32u_i64 ( @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_ext_i32_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_ext_i32_i64 ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; tcg_gen_ext32s_i64 ( @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_umul", "code": "unsigned __int64 __fastcall gen_op_umul ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; gen_op_multiply ( @@a1@@ , @@a2@@ , @@a3@@ , Number ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "src2", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r16"}, {"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src1", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 247 |
[
"{\"name\": \"gen_op_multiply\", \"code\": \"unsigned __int64 __fastcall gen_op_multiply ( int @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ ) { unsigned int @@v7@@ ; unsigned int @@v8@@ ; unsigned int @@v9@@ ; unsigned int @@v10@@ ; unsigned __int64 @@v11@@ ; @@v11@@ = __readfsqword ( Number ) ; @@v7@@ = tcg_temp_new_i32 ( ) ; @@v8@@ = tcg_temp_new_i32 ( ) ; tcg_gen_trunc_i64_i32 ( @@v7@@ , @@a2@@ ) ; tcg_gen_trunc_i64_i32 ( @@v8@@ , @@a3@@ ) ; @@v9@@ = tcg_temp_new_i64 ( ) ; @@v10@@ = tcg_temp_new_i64 ( ) ; if ( @@a4@@ ) { tcg_gen_ext_i32_i64 ( @@v9@@ , @@v8@@ ) ; tcg_gen_ext_i32_i64 ( @@v10@@ , @@v7@@ ) ; } else { tcg_gen_extu_i32_i64 ( @@v9@@ , @@v8@@ ) ; tcg_gen_extu_i32_i64 ( @@v10@@ , @@v7@@ ) ; } tcg_gen_mul_i64 ( @@v10@@ , @@v9@@ , @@v10@@ ) ; tcg_gen_shri_i64 ( @@v9@@ , @@v10@@ , Number L ) ; tcg_gen_mov_i64 ( cpu_tmp0 , @@v9@@ ) ; tcg_temp_free_i64 ( @@v9@@ ) ; tcg_gen_andi_i64 ( cpu_y , cpu_tmp0 , Number ) ; tcg_gen_mov_i64 ( @@a1@@ , @@v10@@ ) ; tcg_temp_free_i64 ( @@v10@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v11@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s20\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s24\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_smul", "code": "unsigned __int64 __fastcall gen_op_smul ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; gen_op_multiply ( @@a1@@ , @@a2@@ , @@a3@@ , Number ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "src2", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r16"}, {"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src1", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 248 |
[
"{\"name\": \"gen_op_multiply\", \"code\": \"unsigned __int64 __fastcall gen_op_multiply ( int @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ ) { unsigned int @@v7@@ ; unsigned int @@v8@@ ; unsigned int @@v9@@ ; unsigned int @@v10@@ ; unsigned __int64 @@v11@@ ; @@v11@@ = __readfsqword ( Number ) ; @@v7@@ = tcg_temp_new_i32 ( ) ; @@v8@@ = tcg_temp_new_i32 ( ) ; tcg_gen_trunc_i64_i32 ( @@v7@@ , @@a2@@ ) ; tcg_gen_trunc_i64_i32 ( @@v8@@ , @@a3@@ ) ; @@v9@@ = tcg_temp_new_i64 ( ) ; @@v10@@ = tcg_temp_new_i64 ( ) ; if ( @@a4@@ ) { tcg_gen_ext_i32_i64 ( @@v9@@ , @@v8@@ ) ; tcg_gen_ext_i32_i64 ( @@v10@@ , @@v7@@ ) ; } else { tcg_gen_extu_i32_i64 ( @@v9@@ , @@v8@@ ) ; tcg_gen_extu_i32_i64 ( @@v10@@ , @@v7@@ ) ; } tcg_gen_mul_i64 ( @@v10@@ , @@v9@@ , @@v10@@ ) ; tcg_gen_shri_i64 ( @@v9@@ , @@v10@@ , Number L ) ; tcg_gen_mov_i64 ( cpu_tmp0 , @@v9@@ ) ; tcg_temp_free_i64 ( @@v9@@ ) ; tcg_gen_andi_i64 ( cpu_y , cpu_tmp0 , Number ) ; tcg_gen_mov_i64 ( @@a1@@ , @@v10@@ ) ; tcg_temp_free_i64 ( @@v10@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v11@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s20\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s24\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_trap_ifdivzero_tl", "code": "unsigned __int64 __fastcall gen_trap_ifdivzero_tl ( int @@a1@@ ) { int @@v2@@ ; unsigned int @@v3@@ ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v2@@ = gen_new_label ( ) ; tcg_gen_brcondi_i64 ( Number , @@a1@@ , Number L , @@v2@@ ) ; @@v3@@ = tcg_const_i32 ( Number L ) ; gen_helper_raise_exception ( @@v3@@ ) ; tcg_temp_free_i32 ( @@v3@@ ) ; gen_set_label ( @@v2@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "v3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "s16"}, {"n": "v4", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "divisor", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "r_const", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "l1", "t": {"T": 1, "n": "int", "s": 4}, "location": "s16"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 249 |
[
"{\"name\": \"gen_set_label\", \"code\": \"unsigned __int64 __fastcall gen_set_label ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_op1i ( Number , @@a1@@ ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_br\", \"code\": \"unsigned __int64 __fastcall tcg_gen_br ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_op1i ( Number , @@a1@@ ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_brcondi_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_brcondi_i64 ( unsigned int @@a1@@ , int @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { unsigned int @@v6@@ ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_brcond_i64 ( @@a1@@ , @@a2@@ , @@v6@@ , @@a4@@ ) ; tcg_temp_free_i64 ( @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_raise_exception\", \"code\": \"unsigned __int64 __fastcall gen_helper_raise_exception ( int @@a1@@ ) { __int64 @@v2@@ ; unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; @@v2@@ = @@a1@@ ; tcg_gen_helperN ( ( __int64 ) & helper_raise_exception , Number , Number , Number , Number , ( __int64 ) & @@v2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_sdivx", "code": "unsigned __int64 __fastcall gen_op_sdivx ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { int @@v5@@ ; int @@v6@@ ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v5@@ = gen_new_label ( ) ; @@v6@@ = gen_new_label ( ) ; tcg_gen_mov_i64 ( cpu_cc_src , @@a2@@ ) ; tcg_gen_mov_i64 ( cpu_cc_src2 , @@a3@@ ) ; gen_trap_ifdivzero_tl ( cpu_cc_src2 ) ; tcg_gen_brcondi_i64 ( Number , cpu_cc_src , Number , @@v5@@ ) ; tcg_gen_brcondi_i64 ( Number , cpu_cc_src2 , Number , @@v5@@ ) ; tcg_gen_movi_i64 ( @@a1@@ , Number ) ; tcg_gen_br ( @@v6@@ ) ; gen_set_label ( @@v5@@ ) ; tcg_gen_div_i64 ( @@a1@@ , cpu_cc_src , cpu_cc_src2 ) ; gen_set_label ( @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v6", "t": {"T": 1, "n": "int", "s": 4}, "location": "s12"}, {"n": "v5", "t": {"T": 1, "n": "int", "s": 4}, "location": "s16"}, {"n": "v7", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "src2", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r16"}, {"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src1", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "l2", "t": {"T": 1, "n": "int", "s": 4}, "location": "s12"}, {"n": "l1", "t": {"T": 1, "n": "int", "s": 4}, "location": "s16"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 250 |
[
"{\"name\": \"gen_set_label\", \"code\": \"unsigned __int64 __fastcall gen_set_label ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_op1i ( Number , @@a1@@ ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_br\", \"code\": \"unsigned __int64 __fastcall tcg_gen_br ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_op1i ( Number , @@a1@@ ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_mov_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_mov_i64 ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; if ( @@a1@@ != @@a2@@ ) tcg_gen_op2_i64 ( Number , @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_movi_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_movi_i64 ( int @@a1@@ , __int64 @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; tcg_gen_op2i_i64 ( Number , @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_div_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_div_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned int @@v5@@ ; unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; @@v5@@ = tcg_temp_new_i64 ( ) ; tcg_gen_sari_i64 ( @@v5@@ , @@a2@@ , Number L ) ; tcg_gen_op5_i64 ( Number , @@a1@@ , @@v5@@ , @@a2@@ , @@v5@@ , @@a3@@ ) ; tcg_temp_free_i64 ( @@v5@@ ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_brcondi_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_brcondi_i64 ( unsigned int @@a1@@ , int @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { unsigned int @@v6@@ ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_brcond_i64 ( @@a1@@ , @@a2@@ , @@v6@@ , @@a4@@ ) ; tcg_temp_free_i64 ( @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_trap_ifdivzero_tl\", \"code\": \"unsigned __int64 __fastcall gen_trap_ifdivzero_tl ( int @@a1@@ ) { int @@v2@@ ; unsigned int @@v3@@ ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v2@@ = gen_new_label ( ) ; tcg_gen_brcondi_i64 ( Number , @@a1@@ , Number L , @@v2@@ ) ; @@v3@@ = tcg_const_i32 ( Number L ) ; gen_helper_raise_exception ( @@v3@@ ) ; tcg_temp_free_i32 ( @@v3@@ ) ; gen_set_label ( @@v2@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s16\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_eval_ba", "code": "unsigned __int64 __fastcall gen_op_eval_ba ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_movi_i64 ( @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "v2", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 251 |
[
"{\"name\": \"tcg_gen_movi_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_movi_i64 ( int @@a1@@ , __int64 @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; tcg_gen_op2i_i64 ( Number , @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_eval_be", "code": "unsigned __int64 __fastcall gen_op_eval_be ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; gen_mov_reg_Z ( @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src", "t": {"T": 1, "n": "TCGv_i32", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 252 |
[
"{\"name\": \"gen_mov_reg_Z\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_Z ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_extu_i32_i64 ( @@a1@@ , @@a2@@ ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a1@@ , Number L ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_eval_ble", "code": "unsigned __int64 __fastcall gen_op_eval_ble ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; gen_mov_reg_N ( cpu_tmp0 , @@a2@@ ) ; gen_mov_reg_V ( @@a1@@ , @@a2@@ ) ; tcg_gen_xor_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; gen_mov_reg_Z ( cpu_tmp0 , @@a2@@ ) ; tcg_gen_or_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src", "t": {"T": 1, "n": "TCGv_i32", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 253 |
[
"{\"name\": \"tcg_gen_or_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_or_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; if ( @@a2@@ == @@a3@@ ) tcg_gen_mov_i64 ( @@a1@@ , @@a2@@ ) ; else tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_xor_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_xor_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; if ( @@a2@@ == @@a3@@ ) tcg_gen_movi_i64 ( @@a1@@ , Number L ) ; else tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_N\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_N ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_extu_i32_i64 ( @@a1@@ , @@a2@@ ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a1@@ , Number L ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_Z\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_Z ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_extu_i32_i64 ( @@a1@@ , @@a2@@ ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a1@@ , Number L ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_V\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_V ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_extu_i32_i64 ( @@a1@@ , @@a2@@ ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a1@@ , Number L ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_bl\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_bl ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; gen_mov_reg_V ( cpu_tmp0 , @@a2@@ ) ; gen_mov_reg_N ( @@a1@@ , @@a2@@ ) ; tcg_gen_xor_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_eval_bl", "code": "unsigned __int64 __fastcall gen_op_eval_bl ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; gen_mov_reg_V ( cpu_tmp0 , @@a2@@ ) ; gen_mov_reg_N ( @@a1@@ , @@a2@@ ) ; tcg_gen_xor_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src", "t": {"T": 1, "n": "TCGv_i32", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 254 |
[
"{\"name\": \"tcg_gen_xor_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_xor_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; if ( @@a2@@ == @@a3@@ ) tcg_gen_movi_i64 ( @@a1@@ , Number L ) ; else tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_N\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_N ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_extu_i32_i64 ( @@a1@@ , @@a2@@ ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a1@@ , Number L ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_V\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_V ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_extu_i32_i64 ( @@a1@@ , @@a2@@ ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a1@@ , Number L ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_eval_bleu", "code": "unsigned __int64 __fastcall gen_op_eval_bleu ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; gen_mov_reg_Z ( cpu_tmp0 , @@a2@@ ) ; gen_mov_reg_C ( @@a1@@ , @@a2@@ ) ; tcg_gen_or_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src", "t": {"T": 1, "n": "TCGv_i32", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 255 |
[
"{\"name\": \"tcg_gen_or_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_or_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; if ( @@a2@@ == @@a3@@ ) tcg_gen_mov_i64 ( @@a1@@ , @@a2@@ ) ; else tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_Z\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_Z ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_extu_i32_i64 ( @@a1@@ , @@a2@@ ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a1@@ , Number L ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_C\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_C ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_extu_i32_i64 ( @@a1@@ , @@a2@@ ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a1@@ , Number L ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_ble\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_ble ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; gen_mov_reg_N ( cpu_tmp0 , @@a2@@ ) ; gen_mov_reg_V ( @@a1@@ , @@a2@@ ) ; tcg_gen_xor_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; gen_mov_reg_Z ( cpu_tmp0 , @@a2@@ ) ; tcg_gen_or_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_bl\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_bl ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; gen_mov_reg_V ( cpu_tmp0 , @@a2@@ ) ; gen_mov_reg_N ( @@a1@@ , @@a2@@ ) ; tcg_gen_xor_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_eval_bcs", "code": "unsigned __int64 __fastcall gen_op_eval_bcs ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; gen_mov_reg_C ( @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src", "t": {"T": 1, "n": "TCGv_i32", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 256 |
[
"{\"name\": \"gen_mov_reg_C\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_C ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_extu_i32_i64 ( @@a1@@ , @@a2@@ ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a1@@ , Number L ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_eval_bvs", "code": "unsigned __int64 __fastcall gen_op_eval_bvs ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; gen_mov_reg_V ( @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src", "t": {"T": 1, "n": "TCGv_i32", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 257 |
[
"{\"name\": \"gen_mov_reg_V\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_V ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_extu_i32_i64 ( @@a1@@ , @@a2@@ ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a1@@ , Number L ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_eval_bn", "code": "unsigned __int64 __fastcall gen_op_eval_bn ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_movi_i64 ( @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "v2", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 258 |
[
"{\"name\": \"tcg_gen_movi_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_movi_i64 ( int @@a1@@ , __int64 @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; tcg_gen_op2i_i64 ( Number , @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_eval_bneg", "code": "unsigned __int64 __fastcall gen_op_eval_bneg ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; gen_mov_reg_N ( @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src", "t": {"T": 1, "n": "TCGv_i32", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 259 |
[
"{\"name\": \"gen_mov_reg_N\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_N ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_extu_i32_i64 ( @@a1@@ , @@a2@@ ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a1@@ , Number L ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_bn\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_bn ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_movi_i64 ( @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_bne\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_bne ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; gen_mov_reg_Z ( @@a1@@ , @@a2@@ ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_eval_bne", "code": "unsigned __int64 __fastcall gen_op_eval_bne ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; gen_mov_reg_Z ( @@a1@@ , @@a2@@ ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src", "t": {"T": 1, "n": "TCGv_i32", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 260 |
[
"{\"name\": \"tcg_gen_xori_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_xori_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_xor_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_Z\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_Z ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_extu_i32_i64 ( @@a1@@ , @@a2@@ ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a1@@ , Number L ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_bn\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_bn ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_movi_i64 ( @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_eval_bg", "code": "unsigned __int64 __fastcall gen_op_eval_bg ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; gen_mov_reg_N ( cpu_tmp0 , @@a2@@ ) ; gen_mov_reg_V ( @@a1@@ , @@a2@@ ) ; tcg_gen_xor_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; gen_mov_reg_Z ( cpu_tmp0 , @@a2@@ ) ; tcg_gen_or_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src", "t": {"T": 1, "n": "TCGv_i32", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 261 |
[
"{\"name\": \"tcg_gen_or_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_or_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; if ( @@a2@@ == @@a3@@ ) tcg_gen_mov_i64 ( @@a1@@ , @@a2@@ ) ; else tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_xor_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_xor_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; if ( @@a2@@ == @@a3@@ ) tcg_gen_movi_i64 ( @@a1@@ , Number L ) ; else tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_xori_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_xori_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_xor_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_N\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_N ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_extu_i32_i64 ( @@a1@@ , @@a2@@ ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a1@@ , Number L ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_Z\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_Z ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_extu_i32_i64 ( @@a1@@ , @@a2@@ ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a1@@ , Number L ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_V\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_V ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_extu_i32_i64 ( @@a1@@ , @@a2@@ ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a1@@ , Number L ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_eval_bge", "code": "unsigned __int64 __fastcall gen_op_eval_bge ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; gen_mov_reg_V ( cpu_tmp0 , @@a2@@ ) ; gen_mov_reg_N ( @@a1@@ , @@a2@@ ) ; tcg_gen_xor_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src", "t": {"T": 1, "n": "TCGv_i32", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 262 |
[
"{\"name\": \"tcg_gen_xor_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_xor_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; if ( @@a2@@ == @@a3@@ ) tcg_gen_movi_i64 ( @@a1@@ , Number L ) ; else tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_xori_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_xori_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_xor_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_N\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_N ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_extu_i32_i64 ( @@a1@@ , @@a2@@ ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a1@@ , Number L ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_V\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_V ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_extu_i32_i64 ( @@a1@@ , @@a2@@ ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a1@@ , Number L ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_bg\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_bg ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; gen_mov_reg_N ( cpu_tmp0 , @@a2@@ ) ; gen_mov_reg_V ( @@a1@@ , @@a2@@ ) ; tcg_gen_xor_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; gen_mov_reg_Z ( cpu_tmp0 , @@a2@@ ) ; tcg_gen_or_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_eval_bgu", "code": "unsigned __int64 __fastcall gen_op_eval_bgu ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; gen_mov_reg_Z ( cpu_tmp0 , @@a2@@ ) ; gen_mov_reg_C ( @@a1@@ , @@a2@@ ) ; tcg_gen_or_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src", "t": {"T": 1, "n": "TCGv_i32", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 263 |
[
"{\"name\": \"tcg_gen_or_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_or_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; if ( @@a2@@ == @@a3@@ ) tcg_gen_mov_i64 ( @@a1@@ , @@a2@@ ) ; else tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_xori_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_xori_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_xor_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_Z\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_Z ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_extu_i32_i64 ( @@a1@@ , @@a2@@ ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a1@@ , Number L ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_C\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_C ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_extu_i32_i64 ( @@a1@@ , @@a2@@ ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a1@@ , Number L ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_bg\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_bg ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; gen_mov_reg_N ( cpu_tmp0 , @@a2@@ ) ; gen_mov_reg_V ( @@a1@@ , @@a2@@ ) ; tcg_gen_xor_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; gen_mov_reg_Z ( cpu_tmp0 , @@a2@@ ) ; tcg_gen_or_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_eval_bcc", "code": "unsigned __int64 __fastcall gen_op_eval_bcc ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; gen_mov_reg_C ( @@a1@@ , @@a2@@ ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src", "t": {"T": 1, "n": "TCGv_i32", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 264 |
[
"{\"name\": \"tcg_gen_xori_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_xori_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_xor_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_C\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_C ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_extu_i32_i64 ( @@a1@@ , @@a2@@ ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a1@@ , Number L ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_eval_bpos", "code": "unsigned __int64 __fastcall gen_op_eval_bpos ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; gen_mov_reg_N ( @@a1@@ , @@a2@@ ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src", "t": {"T": 1, "n": "TCGv_i32", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 265 |
[
"{\"name\": \"tcg_gen_xori_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_xori_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_xor_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_N\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_N ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_extu_i32_i64 ( @@a1@@ , @@a2@@ ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a1@@ , Number L ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_eval_bvc", "code": "unsigned __int64 __fastcall gen_op_eval_bvc ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; gen_mov_reg_V ( @@a1@@ , @@a2@@ ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src", "t": {"T": 1, "n": "TCGv_i32", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 266 |
[
"{\"name\": \"tcg_gen_xori_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_xori_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_xor_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_V\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_V ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_extu_i32_i64 ( @@a1@@ , @@a2@@ ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a1@@ , Number L ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_mov_reg_FCC0", "code": "unsigned __int64 __fastcall gen_mov_reg_FCC0 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a2@@ , ( unsigned int ) ( @@a3@@ + Number ) ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "fcc_offset", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "reg", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 267 |
[
"{\"name\": \"tcg_gen_andi_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_andi_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_and_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_shri_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_shri_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; if ( @@a3@@ ) { @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_shr_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; } else { tcg_gen_mov_i64 ( @@a1@@ , @@a2@@ ) ; } return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_mov_reg_FCC1", "code": "unsigned __int64 __fastcall gen_mov_reg_FCC1 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a2@@ , ( unsigned int ) ( @@a3@@ + Number ) ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "fcc_offset", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "reg", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 268 |
[
"{\"name\": \"tcg_gen_andi_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_andi_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_and_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_shri_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_shri_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; if ( @@a3@@ ) { @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_shr_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; } else { tcg_gen_mov_i64 ( @@a1@@ , @@a2@@ ) ; } return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_eval_fbne", "code": "unsigned __int64 __fastcall gen_op_eval_fbne ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC0 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; gen_mov_reg_FCC1 ( cpu_tmp0 , @@a2@@ , @@a3@@ ) ; tcg_gen_or_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v5", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "fcc_offset", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 269 |
[
"{\"name\": \"tcg_gen_or_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_or_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; if ( @@a2@@ == @@a3@@ ) tcg_gen_mov_i64 ( @@a1@@ , @@a2@@ ) ; else tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_FCC0\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_FCC0 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a2@@ , ( unsigned int ) ( @@a3@@ + Number ) ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_FCC1\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_FCC1 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a2@@ , ( unsigned int ) ( @@a3@@ + Number ) ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_eval_fblg", "code": "unsigned __int64 __fastcall gen_op_eval_fblg ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC0 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; gen_mov_reg_FCC1 ( cpu_tmp0 , @@a2@@ , @@a3@@ ) ; tcg_gen_xor_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v5", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "fcc_offset", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 270 |
[
"{\"name\": \"tcg_gen_xor_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_xor_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; if ( @@a2@@ == @@a3@@ ) tcg_gen_movi_i64 ( @@a1@@ , Number L ) ; else tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_FCC0\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_FCC0 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a2@@ , ( unsigned int ) ( @@a3@@ + Number ) ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_FCC1\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_FCC1 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a2@@ , ( unsigned int ) ( @@a3@@ + Number ) ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_fbl\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_fbl ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC0 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; gen_mov_reg_FCC1 ( cpu_tmp0 , @@a2@@ , @@a3@@ ) ; tcg_gen_xori_i64 ( cpu_tmp0 , cpu_tmp0 , Number L ) ; tcg_gen_and_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_eval_fbul", "code": "unsigned __int64 __fastcall gen_op_eval_fbul ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC0 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "fcc_offset", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 271 |
[
"{\"name\": \"gen_mov_reg_FCC0\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_FCC0 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a2@@ , ( unsigned int ) ( @@a3@@ + Number ) ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_fbu\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_fbu ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC0 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; gen_mov_reg_FCC1 ( cpu_tmp0 , @@a2@@ , @@a3@@ ) ; tcg_gen_and_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_eval_fbl", "code": "unsigned __int64 __fastcall gen_op_eval_fbl ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC0 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; gen_mov_reg_FCC1 ( cpu_tmp0 , @@a2@@ , @@a3@@ ) ; tcg_gen_xori_i64 ( cpu_tmp0 , cpu_tmp0 , Number L ) ; tcg_gen_and_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v5", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "fcc_offset", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 272 |
[
"{\"name\": \"tcg_gen_and_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_and_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; if ( @@a2@@ == @@a3@@ ) tcg_gen_mov_i64 ( @@a1@@ , @@a2@@ ) ; else tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_xori_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_xori_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_xor_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_FCC0\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_FCC0 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a2@@ , ( unsigned int ) ( @@a3@@ + Number ) ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_FCC1\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_FCC1 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a2@@ , ( unsigned int ) ( @@a3@@ + Number ) ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_eval_fbug", "code": "unsigned __int64 __fastcall gen_op_eval_fbug ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC1 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "fcc_offset", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 273 |
[
"{\"name\": \"gen_mov_reg_FCC1\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_FCC1 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a2@@ , ( unsigned int ) ( @@a3@@ + Number ) ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_fbu\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_fbu ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC0 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; gen_mov_reg_FCC1 ( cpu_tmp0 , @@a2@@ , @@a3@@ ) ; tcg_gen_and_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_eval_fbg", "code": "unsigned __int64 __fastcall gen_op_eval_fbg ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC0 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; gen_mov_reg_FCC1 ( cpu_tmp0 , @@a2@@ , @@a3@@ ) ; tcg_gen_and_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v6", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "fcc_offset", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 274 |
[
"{\"name\": \"tcg_gen_and_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_and_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; if ( @@a2@@ == @@a3@@ ) tcg_gen_mov_i64 ( @@a1@@ , @@a2@@ ) ; else tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_xori_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_xori_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_xor_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_FCC0\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_FCC0 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a2@@ , ( unsigned int ) ( @@a3@@ + Number ) ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_FCC1\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_FCC1 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a2@@ , ( unsigned int ) ( @@a3@@ + Number ) ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_eval_fbu", "code": "unsigned __int64 __fastcall gen_op_eval_fbu ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC0 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; gen_mov_reg_FCC1 ( cpu_tmp0 , @@a2@@ , @@a3@@ ) ; tcg_gen_and_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v5", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "fcc_offset", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 275 |
[
"{\"name\": \"tcg_gen_and_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_and_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; if ( @@a2@@ == @@a3@@ ) tcg_gen_mov_i64 ( @@a1@@ , @@a2@@ ) ; else tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_FCC0\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_FCC0 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a2@@ , ( unsigned int ) ( @@a3@@ + Number ) ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_FCC1\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_FCC1 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a2@@ , ( unsigned int ) ( @@a3@@ + Number ) ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_eval_fbe", "code": "unsigned __int64 __fastcall gen_op_eval_fbe ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC0 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; gen_mov_reg_FCC1 ( cpu_tmp0 , @@a2@@ , @@a3@@ ) ; tcg_gen_or_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v6", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "fcc_offset", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 276 |
[
"{\"name\": \"tcg_gen_or_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_or_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; if ( @@a2@@ == @@a3@@ ) tcg_gen_mov_i64 ( @@a1@@ , @@a2@@ ) ; else tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_xori_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_xori_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_xor_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_FCC0\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_FCC0 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a2@@ , ( unsigned int ) ( @@a3@@ + Number ) ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_FCC1\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_FCC1 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a2@@ , ( unsigned int ) ( @@a3@@ + Number ) ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_eval_fbue", "code": "unsigned __int64 __fastcall gen_op_eval_fbue ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC0 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; gen_mov_reg_FCC1 ( cpu_tmp0 , @@a2@@ , @@a3@@ ) ; tcg_gen_xor_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v6", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "fcc_offset", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 277 |
[
"{\"name\": \"tcg_gen_xor_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_xor_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; if ( @@a2@@ == @@a3@@ ) tcg_gen_movi_i64 ( @@a1@@ , Number L ) ; else tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_xori_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_xori_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_xor_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_FCC0\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_FCC0 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a2@@ , ( unsigned int ) ( @@a3@@ + Number ) ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_FCC1\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_FCC1 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a2@@ , ( unsigned int ) ( @@a3@@ + Number ) ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_fbu\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_fbu ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC0 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; gen_mov_reg_FCC1 ( cpu_tmp0 , @@a2@@ , @@a3@@ ) ; tcg_gen_and_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_eval_fbge", "code": "unsigned __int64 __fastcall gen_op_eval_fbge ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC0 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "fcc_offset", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 278 |
[
"{\"name\": \"tcg_gen_xori_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_xori_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_xor_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_FCC0\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_FCC0 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a2@@ , ( unsigned int ) ( @@a3@@ + Number ) ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_fbg\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_fbg ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC0 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; gen_mov_reg_FCC1 ( cpu_tmp0 , @@a2@@ , @@a3@@ ) ; tcg_gen_and_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_eval_fbuge", "code": "unsigned __int64 __fastcall gen_op_eval_fbuge ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC0 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; gen_mov_reg_FCC1 ( cpu_tmp0 , @@a2@@ , @@a3@@ ) ; tcg_gen_xori_i64 ( cpu_tmp0 , cpu_tmp0 , Number L ) ; tcg_gen_and_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v6", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "fcc_offset", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 279 |
[
"{\"name\": \"tcg_gen_and_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_and_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; if ( @@a2@@ == @@a3@@ ) tcg_gen_mov_i64 ( @@a1@@ , @@a2@@ ) ; else tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_xori_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_xori_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_xor_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_FCC0\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_FCC0 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a2@@ , ( unsigned int ) ( @@a3@@ + Number ) ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_FCC1\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_FCC1 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a2@@ , ( unsigned int ) ( @@a3@@ + Number ) ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_fbug\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_fbug ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC1 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_fbu\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_fbu ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC0 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; gen_mov_reg_FCC1 ( cpu_tmp0 , @@a2@@ , @@a3@@ ) ; tcg_gen_and_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_eval_fble", "code": "unsigned __int64 __fastcall gen_op_eval_fble ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC1 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "fcc_offset", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 280 |
[
"{\"name\": \"tcg_gen_xori_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_xori_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_xor_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_FCC1\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_FCC1 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a2@@ , ( unsigned int ) ( @@a3@@ + Number ) ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_fbl\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_fbl ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC0 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; gen_mov_reg_FCC1 ( cpu_tmp0 , @@a2@@ , @@a3@@ ) ; tcg_gen_xori_i64 ( cpu_tmp0 , cpu_tmp0 , Number L ) ; tcg_gen_and_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_eval_fbule", "code": "unsigned __int64 __fastcall gen_op_eval_fbule ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC0 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; gen_mov_reg_FCC1 ( cpu_tmp0 , @@a2@@ , @@a3@@ ) ; tcg_gen_and_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v6", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "fcc_offset", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 281 |
[
"{\"name\": \"tcg_gen_and_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_and_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; if ( @@a2@@ == @@a3@@ ) tcg_gen_mov_i64 ( @@a1@@ , @@a2@@ ) ; else tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_xori_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_xori_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_xor_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_FCC0\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_FCC0 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a2@@ , ( unsigned int ) ( @@a3@@ + Number ) ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_FCC1\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_FCC1 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a2@@ , ( unsigned int ) ( @@a3@@ + Number ) ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_fbul\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_fbul ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC0 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_fbu\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_fbu ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC0 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; gen_mov_reg_FCC1 ( cpu_tmp0 , @@a2@@ , @@a3@@ ) ; tcg_gen_and_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_eval_fbo", "code": "unsigned __int64 __fastcall gen_op_eval_fbo ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC0 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; gen_mov_reg_FCC1 ( cpu_tmp0 , @@a2@@ , @@a3@@ ) ; tcg_gen_and_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v6", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "fcc_offset", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "src", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 282 |
[
"{\"name\": \"tcg_gen_and_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_and_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; if ( @@a2@@ == @@a3@@ ) tcg_gen_mov_i64 ( @@a1@@ , @@a2@@ ) ; else tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_xori_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_xori_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_xor_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_FCC0\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_FCC0 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a2@@ , ( unsigned int ) ( @@a3@@ + Number ) ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_reg_FCC1\", \"code\": \"unsigned __int64 __fastcall gen_mov_reg_FCC1 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_shri_i64 ( @@a1@@ , @@a2@@ , ( unsigned int ) ( @@a3@@ + Number ) ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_branch2", "code": "unsigned __int64 __fastcall gen_branch2 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { int @@v7@@ ; unsigned __int64 @@v8@@ ; @@v8@@ = __readfsqword ( Number ) ; @@v7@@ = gen_new_label ( ) ; tcg_gen_brcondi_i64 ( Number , @@a4@@ , Number L , @@v7@@ ) ; gen_goto_tb ( @@a1@@ , Number , @@a2@@ , @@a2@@ + Number ) ; gen_set_label ( @@v7@@ ) ; gen_goto_tb ( @@a1@@ , Number , @@a3@@ , @@a3@@ + Number ) ; return __readfsqword ( Number ) ^ @@v8@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v7", "t": {"T": 1, "n": "int", "s": 4}, "location": "s12"}, {"n": "v8", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "pc2", "t": {"T": 1, "n": "target_ulong", "s": 8}, "location": "r16"}, {"n": "r_cond", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r24"}, {"n": "dc", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "pc1", "t": {"T": 1, "n": "target_ulong", "s": 8}, "location": "r64"}, {"n": "l1", "t": {"T": 1, "n": "int", "s": 4}, "location": "s12"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 283 |
[
"{\"name\": \"gen_set_label\", \"code\": \"unsigned __int64 __fastcall gen_set_label ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_op1i ( Number , @@a1@@ ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_br\", \"code\": \"unsigned __int64 __fastcall tcg_gen_br ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_op1i ( Number , @@a1@@ ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_brcondi_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_brcondi_i64 ( unsigned int @@a1@@ , int @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { unsigned int @@v6@@ ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_brcond_i64 ( @@a1@@ , @@a2@@ , @@v6@@ , @@a4@@ ) ; tcg_temp_free_i64 ( @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_goto_tb\", \"code\": \"unsigned __int64 __fastcall gen_goto_tb ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { _QWORD * @@v7@@ ; unsigned __int64 @@v8@@ ; @@v8@@ = __readfsqword ( Number ) ; @@v7@@ = * ( _QWORD * * ) ( @@a1@@ + Number ) ; if ( ( ( @@a3@@ ^ * @@v7@@ ) & Number ) != Number || ( ( @@a4@@ ^ * @@v7@@ ) & Number ) != Number || * ( _DWORD * ) ( @@a1@@ + Number ) ) { tcg_gen_movi_i64 ( cpu_pc , @@a3@@ ) ; tcg_gen_movi_i64 ( cpu_npc , @@a4@@ ) ; tcg_gen_exit_tb ( Number L ) ; } else { tcg_gen_goto_tb ( @@a2@@ ) ; tcg_gen_movi_i64 ( cpu_pc , @@a3@@ ) ; tcg_gen_movi_i64 ( cpu_npc , @@a4@@ ) ; tcg_gen_exit_tb ( ( __int64 ) @@v7@@ + @@a2@@ ) ; } return __readfsqword ( Number ) ^ @@v8@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 3, \"t\": \"_QWORD\"}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_branch_a", "code": "unsigned __int64 __fastcall gen_branch_a ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { int @@v7@@ ; unsigned __int64 @@v8@@ ; @@v8@@ = __readfsqword ( Number ) ; @@v7@@ = gen_new_label ( ) ; tcg_gen_brcondi_i64 ( Number , @@a4@@ , Number L , @@v7@@ ) ; gen_goto_tb ( @@a1@@ , Number , @@a3@@ , @@a2@@ ) ; gen_set_label ( @@v7@@ ) ; gen_goto_tb ( @@a1@@ , Number , @@a3@@ + Number , @@a3@@ + Number ) ; return __readfsqword ( Number ) ^ @@v8@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v7", "t": {"T": 1, "n": "int", "s": 4}, "location": "s12"}, {"n": "v8", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "pc2", "t": {"T": 1, "n": "target_ulong", "s": 8}, "location": "r16"}, {"n": "r_cond", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r24"}, {"n": "dc", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "pc1", "t": {"T": 1, "n": "target_ulong", "s": 8}, "location": "r64"}, {"n": "l1", "t": {"T": 1, "n": "int", "s": 4}, "location": "s12"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 284 |
[
"{\"name\": \"gen_set_label\", \"code\": \"unsigned __int64 __fastcall gen_set_label ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_op1i ( Number , @@a1@@ ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_br\", \"code\": \"unsigned __int64 __fastcall tcg_gen_br ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_op1i ( Number , @@a1@@ ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_brcondi_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_brcondi_i64 ( unsigned int @@a1@@ , int @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { unsigned int @@v6@@ ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_brcond_i64 ( @@a1@@ , @@a2@@ , @@v6@@ , @@a4@@ ) ; tcg_temp_free_i64 ( @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_goto_tb\", \"code\": \"unsigned __int64 __fastcall gen_goto_tb ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { _QWORD * @@v7@@ ; unsigned __int64 @@v8@@ ; @@v8@@ = __readfsqword ( Number ) ; @@v7@@ = * ( _QWORD * * ) ( @@a1@@ + Number ) ; if ( ( ( @@a3@@ ^ * @@v7@@ ) & Number ) != Number || ( ( @@a4@@ ^ * @@v7@@ ) & Number ) != Number || * ( _DWORD * ) ( @@a1@@ + Number ) ) { tcg_gen_movi_i64 ( cpu_pc , @@a3@@ ) ; tcg_gen_movi_i64 ( cpu_npc , @@a4@@ ) ; tcg_gen_exit_tb ( Number L ) ; } else { tcg_gen_goto_tb ( @@a2@@ ) ; tcg_gen_movi_i64 ( cpu_pc , @@a3@@ ) ; tcg_gen_movi_i64 ( cpu_npc , @@a4@@ ) ; tcg_gen_exit_tb ( ( __int64 ) @@v7@@ + @@a2@@ ) ; } return __readfsqword ( Number ) ^ @@v8@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 3, \"t\": \"_QWORD\"}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_generic_branch", "code": "unsigned __int64 __fastcall gen_generic_branch ( __int64 @@a1@@ , __int64 @@a2@@ , int @@a3@@ ) { int @@v5@@ ; int @@v6@@ ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v5@@ = gen_new_label ( ) ; @@v6@@ = gen_new_label ( ) ; tcg_gen_brcondi_i64 ( Number , @@a3@@ , Number L , @@v5@@ ) ; tcg_gen_movi_i64 ( cpu_npc , @@a1@@ ) ; tcg_gen_br ( @@v6@@ ) ; gen_set_label ( @@v5@@ ) ; tcg_gen_movi_i64 ( cpu_npc , @@a2@@ ) ; gen_set_label ( @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v6", "t": {"T": 1, "n": "int", "s": 4}, "location": "s12"}, {"n": "v5", "t": {"T": 1, "n": "int", "s": 4}, "location": "s16"}, {"n": "v7", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "r_cond", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r16"}, {"n": "npc1", "t": {"T": 1, "n": "target_ulong", "s": 8}, "location": "r56"}, {"n": "npc2", "t": {"T": 1, "n": "target_ulong", "s": 8}, "location": "r64"}, {"n": "l2", "t": {"T": 1, "n": "int", "s": 4}, "location": "s12"}, {"n": "l1", "t": {"T": 1, "n": "int", "s": 4}, "location": "s16"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 285 |
[
"{\"name\": \"gen_set_label\", \"code\": \"unsigned __int64 __fastcall gen_set_label ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_op1i ( Number , @@a1@@ ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_br\", \"code\": \"unsigned __int64 __fastcall tcg_gen_br ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_op1i ( Number , @@a1@@ ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_movi_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_movi_i64 ( int @@a1@@ , __int64 @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; tcg_gen_op2i_i64 ( Number , @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_brcondi_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_brcondi_i64 ( unsigned int @@a1@@ , int @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { unsigned int @@v6@@ ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_brcond_i64 ( @@a1@@ , @@a2@@ , @@v6@@ , @@a4@@ ) ; tcg_temp_free_i64 ( @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "flush_cond", "code": "unsigned __int64 __fastcall flush_cond ( _QWORD * @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; if ( @@a1@@ [ Number ] == Number L ) { gen_generic_branch ( @@a1@@ [ Number ] , @@a1@@ [ Number ] , @@a2@@ ) ; @@a1@@ [ Number ] = Number L ; } return __readfsqword ( Number ) ^ @@v3@@ ; }", "source": [{"n": "a1", "t": {"T": 3, "t": "_QWORD"}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "dc", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "cond", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 286 |
[
"{\"name\": \"gen_generic_branch\", \"code\": \"unsigned __int64 __fastcall gen_generic_branch ( __int64 @@a1@@ , __int64 @@a2@@ , int @@a3@@ ) { int @@v5@@ ; int @@v6@@ ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v5@@ = gen_new_label ( ) ; @@v6@@ = gen_new_label ( ) ; tcg_gen_brcondi_i64 ( Number , @@a3@@ , Number L , @@v5@@ ) ; tcg_gen_movi_i64 ( cpu_npc , @@a1@@ ) ; tcg_gen_br ( @@v6@@ ) ; gen_set_label ( @@v5@@ ) ; tcg_gen_movi_i64 ( cpu_npc , @@a2@@ ) ; gen_set_label ( @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "save_npc", "code": "unsigned __int64 __fastcall save_npc ( __int64 * @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; if ( @@a1@@ [ Number ] == Number ) { gen_generic_branch ( @@a1@@ [ Number ] , @@a1@@ [ Number ] , @@a2@@ ) ; @@a1@@ [ Number ] = Number L ; } else if ( @@a1@@ [ Number ] != Number ) { tcg_gen_movi_i64 ( cpu_npc , @@a1@@ [ Number ] ) ; } return __readfsqword ( Number ) ^ @@v3@@ ; }", "source": [{"n": "a1", "t": {"T": 3, "t": "__int64"}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "dc", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "cond", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 287 |
[
"{\"name\": \"tcg_gen_movi_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_movi_i64 ( int @@a1@@ , __int64 @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; tcg_gen_op2i_i64 ( Number , @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_generic_branch\", \"code\": \"unsigned __int64 __fastcall gen_generic_branch ( __int64 @@a1@@ , __int64 @@a2@@ , int @@a3@@ ) { int @@v5@@ ; int @@v6@@ ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v5@@ = gen_new_label ( ) ; @@v6@@ = gen_new_label ( ) ; tcg_gen_brcondi_i64 ( Number , @@a3@@ , Number L , @@v5@@ ) ; tcg_gen_movi_i64 ( cpu_npc , @@a1@@ ) ; tcg_gen_br ( @@v6@@ ) ; gen_set_label ( @@v5@@ ) ; tcg_gen_movi_i64 ( cpu_npc , @@a2@@ ) ; gen_set_label ( @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "save_state", "code": "unsigned __int64 __fastcall save_state ( __int64 @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; tcg_gen_movi_i64 ( cpu_pc , * ( _QWORD * ) @@a1@@ ) ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) != Number ) { * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; gen_helper_compute_psr ( ) ; } save_npc ( ( __int64 * ) @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "dc", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "cond", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 288 |
[
"{\"name\": \"tcg_gen_movi_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_movi_i64 ( int @@a1@@ , __int64 @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; tcg_gen_op2i_i64 ( Number , @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_compute_psr\", \"code\": \"unsigned __int64 gen_helper_compute_psr ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_compute_psr , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"save_npc\", \"code\": \"unsigned __int64 __fastcall save_npc ( __int64 * @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; if ( @@a1@@ [ Number ] == Number ) { gen_generic_branch ( @@a1@@ [ Number ] , @@a1@@ [ Number ] , @@a2@@ ) ; @@a1@@ [ Number ] = Number L ; } else if ( @@a1@@ [ Number ] != Number ) { tcg_gen_movi_i64 ( cpu_npc , @@a1@@ [ Number ] ) ; } return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 3, \"t\": \"__int64\"}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_mov_pc_npc", "code": "unsigned __int64 __fastcall gen_mov_pc_npc ( _QWORD * @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; if ( @@a1@@ [ Number ] == Number L ) { gen_generic_branch ( @@a1@@ [ Number ] , @@a1@@ [ Number ] , @@a2@@ ) ; tcg_gen_mov_i64 ( cpu_pc , cpu_npc ) ; * @@a1@@ = Number L ; } else if ( @@a1@@ [ Number ] == Number L ) { tcg_gen_mov_i64 ( cpu_pc , cpu_npc ) ; * @@a1@@ = Number L ; } else { * @@a1@@ = @@a1@@ [ Number ] ; } return __readfsqword ( Number ) ^ @@v3@@ ; }", "source": [{"n": "a1", "t": {"T": 3, "t": "_QWORD"}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "dc", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "cond", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 289 |
[
"{\"name\": \"tcg_gen_mov_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_mov_i64 ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; if ( @@a1@@ != @@a2@@ ) tcg_gen_op2_i64 ( Number , @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_generic_branch\", \"code\": \"unsigned __int64 __fastcall gen_generic_branch ( __int64 @@a1@@ , __int64 @@a2@@ , int @@a3@@ ) { int @@v5@@ ; int @@v6@@ ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v5@@ = gen_new_label ( ) ; @@v6@@ = gen_new_label ( ) ; tcg_gen_brcondi_i64 ( Number , @@a3@@ , Number L , @@v5@@ ) ; tcg_gen_movi_i64 ( cpu_npc , @@a1@@ ) ; tcg_gen_br ( @@v6@@ ) ; gen_set_label ( @@v5@@ ) ; tcg_gen_movi_i64 ( cpu_npc , @@a2@@ ) ; gen_set_label ( @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_next_insn", "code": "unsigned __int64 gen_op_next_insn ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_mov_i64 ( cpu_pc , cpu_npc ) ; tcg_gen_addi_i64 ( cpu_npc , cpu_npc , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }", "source": [{"n": "v1", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 290 |
[
"{\"name\": \"tcg_gen_mov_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_mov_i64 ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; if ( @@a1@@ != @@a2@@ ) tcg_gen_op2_i64 ( Number , @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_addi_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_addi_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; if ( @@a3@@ ) { @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_add_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; } else { tcg_gen_mov_i64 ( @@a1@@ , @@a2@@ ) ; } return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_cond", "code": "unsigned __int64 __fastcall gen_cond ( int @@a1@@ , int @@a2@@ , int @@a3@@ , __int64 @@a4@@ ) { int @@v7@@ ; unsigned __int64 @@v8@@ ; @@v8@@ = __readfsqword ( Number ) ; if ( @@a2@@ ) @@v7@@ = cpu_xcc ; else @@v7@@ = cpu_psr ; if ( * ( _DWORD * ) ( @@a4@@ + Number ) != Number ) { gen_helper_compute_psr ( ) ; * ( _DWORD * ) ( @@a4@@ + Number ) = Number ; } switch ( @@a3@@ ) { case Number : gen_op_eval_bn ( @@a1@@ ) ; break ; case Number : gen_op_eval_be ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_ble ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bl ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bleu ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bcs ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bneg ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bvs ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_ba ( @@a1@@ ) ; break ; case Number : gen_op_eval_bne ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bg ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bge ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bgu ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bcc ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bpos ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bvc ( @@a1@@ , @@v7@@ ) ; break ; default : return __readfsqword ( Number ) ^ @@v8@@ ; } return __readfsqword ( Number ) ^ @@v8@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v7", "t": {"T": 1, "n": "int", "s": 4}, "location": "s12"}, {"n": "v8", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "cond", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "dc", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r24"}, {"n": "r_dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "cc", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "r_src", "t": {"T": 1, "n": "TCGv_i32", "s": 4}, "location": "s12"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 291 |
[
"{\"name\": \"gen_helper_compute_psr\", \"code\": \"unsigned __int64 gen_helper_compute_psr ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_compute_psr , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_ba\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_ba ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_movi_i64 ( @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_be\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_be ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; gen_mov_reg_Z ( @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_ble\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_ble ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; gen_mov_reg_N ( cpu_tmp0 , @@a2@@ ) ; gen_mov_reg_V ( @@a1@@ , @@a2@@ ) ; tcg_gen_xor_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; gen_mov_reg_Z ( cpu_tmp0 , @@a2@@ ) ; tcg_gen_or_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_bl\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_bl ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; gen_mov_reg_V ( cpu_tmp0 , @@a2@@ ) ; gen_mov_reg_N ( @@a1@@ , @@a2@@ ) ; tcg_gen_xor_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_bleu\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_bleu ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; gen_mov_reg_Z ( cpu_tmp0 , @@a2@@ ) ; gen_mov_reg_C ( @@a1@@ , @@a2@@ ) ; tcg_gen_or_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_bcs\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_bcs ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; gen_mov_reg_C ( @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_bvs\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_bvs ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; gen_mov_reg_V ( @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_bn\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_bn ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_movi_i64 ( @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_bneg\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_bneg ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; gen_mov_reg_N ( @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_bne\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_bne ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; gen_mov_reg_Z ( @@a1@@ , @@a2@@ ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_bg\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_bg ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; gen_mov_reg_N ( cpu_tmp0 , @@a2@@ ) ; gen_mov_reg_V ( @@a1@@ , @@a2@@ ) ; tcg_gen_xor_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; gen_mov_reg_Z ( cpu_tmp0 , @@a2@@ ) ; tcg_gen_or_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_bge\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_bge ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; gen_mov_reg_V ( cpu_tmp0 , @@a2@@ ) ; gen_mov_reg_N ( @@a1@@ , @@a2@@ ) ; tcg_gen_xor_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_bgu\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_bgu ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; gen_mov_reg_Z ( cpu_tmp0 , @@a2@@ ) ; gen_mov_reg_C ( @@a1@@ , @@a2@@ ) ; tcg_gen_or_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_bcc\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_bcc ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; gen_mov_reg_C ( @@a1@@ , @@a2@@ ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_bpos\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_bpos ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; gen_mov_reg_N ( @@a1@@ , @@a2@@ ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_bvc\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_bvc ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; gen_mov_reg_V ( @@a1@@ , @@a2@@ ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_fcond", "code": "unsigned __int64 __fastcall gen_fcond ( int @@a1@@ , unsigned int @@a2@@ , int @@a3@@ ) { int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; if ( @@a2@@ == Number ) { @@v4@@ = Number ; } else { if ( @@a2@@ > Number ) { LABEL_5 : @@v4@@ = Number ; goto LABEL_9 ; } if ( @@a2@@ == Number ) { @@v4@@ = Number ; } else { if ( @@a2@@ != Number ) goto LABEL_5 ; @@v4@@ = Number ; } } LABEL_9 : switch ( @@a3@@ ) { case Number : gen_op_eval_bn ( @@a1@@ ) ; break ; case Number : gen_op_eval_fbne ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fblg ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fbul ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fbl ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fbug ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fbg ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fbu ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_ba ( @@a1@@ ) ; break ; case Number : gen_op_eval_fbe ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fbue ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fbge ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fbuge ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fble ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fbule ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fbo ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; default : return __readfsqword ( Number ) ^ @@v5@@ ; } return __readfsqword ( Number ) ^ @@v5@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "int", "s": 4}, "location": "s12"}, {"n": "v5", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "cond", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "r_dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "cc", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "offset", "t": {"T": 1, "n": "int", "s": 4}, "location": "s12"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 292 |
[
"{\"name\": \"gen_op_eval_ba\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_ba ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_movi_i64 ( @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_bn\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_bn ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_movi_i64 ( @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_fbne\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_fbne ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC0 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; gen_mov_reg_FCC1 ( cpu_tmp0 , @@a2@@ , @@a3@@ ) ; tcg_gen_or_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_fblg\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_fblg ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC0 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; gen_mov_reg_FCC1 ( cpu_tmp0 , @@a2@@ , @@a3@@ ) ; tcg_gen_xor_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_fbul\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_fbul ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC0 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_fbl\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_fbl ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC0 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; gen_mov_reg_FCC1 ( cpu_tmp0 , @@a2@@ , @@a3@@ ) ; tcg_gen_xori_i64 ( cpu_tmp0 , cpu_tmp0 , Number L ) ; tcg_gen_and_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_fbug\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_fbug ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC1 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_fbg\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_fbg ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC0 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; gen_mov_reg_FCC1 ( cpu_tmp0 , @@a2@@ , @@a3@@ ) ; tcg_gen_and_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_fbu\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_fbu ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC0 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; gen_mov_reg_FCC1 ( cpu_tmp0 , @@a2@@ , @@a3@@ ) ; tcg_gen_and_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_fbe\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_fbe ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC0 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; gen_mov_reg_FCC1 ( cpu_tmp0 , @@a2@@ , @@a3@@ ) ; tcg_gen_or_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_fbue\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_fbue ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC0 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; gen_mov_reg_FCC1 ( cpu_tmp0 , @@a2@@ , @@a3@@ ) ; tcg_gen_xor_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_fbge\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_fbge ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC0 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_fbuge\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_fbuge ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC0 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; gen_mov_reg_FCC1 ( cpu_tmp0 , @@a2@@ , @@a3@@ ) ; tcg_gen_xori_i64 ( cpu_tmp0 , cpu_tmp0 , Number L ) ; tcg_gen_and_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_fble\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_fble ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC1 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_fbule\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_fbule ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC0 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; gen_mov_reg_FCC1 ( cpu_tmp0 , @@a2@@ , @@a3@@ ) ; tcg_gen_and_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_eval_fbo\", \"code\": \"unsigned __int64 __fastcall gen_op_eval_fbo ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; gen_mov_reg_FCC0 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; gen_mov_reg_FCC1 ( cpu_tmp0 , @@a2@@ , @@a3@@ ) ; tcg_gen_and_i64 ( @@a1@@ , @@a1@@ , cpu_tmp0 ) ; tcg_gen_xori_i64 ( @@a1@@ , @@a1@@ , Number L ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_cond_reg", "code": "unsigned __int64 __fastcall gen_cond_reg ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { int @@v5@@ ; unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; @@v5@@ = gen_new_label ( ) ; tcg_gen_movi_i64 ( @@a1@@ , Number L ) ; tcg_gen_brcondi_i64 ( gen_tcg_cond_reg [ @@a2@@ ] , @@a3@@ , Number L , @@v5@@ ) ; tcg_gen_movi_i64 ( @@a1@@ , Number L ) ; gen_set_label ( @@v5@@ ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v5", "t": {"T": 1, "n": "int", "s": 4}, "location": "s12"}, {"n": "v6", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "r_src", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r16"}, {"n": "r_dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "cond", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "l1", "t": {"T": 1, "n": "int", "s": 4}, "location": "s12"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 293 |
[
"{\"name\": \"gen_set_label\", \"code\": \"unsigned __int64 __fastcall gen_set_label ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_op1i ( Number , @@a1@@ ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_br\", \"code\": \"unsigned __int64 __fastcall tcg_gen_br ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_op1i ( Number , @@a1@@ ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_movi_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_movi_i64 ( int @@a1@@ , __int64 @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; tcg_gen_op2i_i64 ( Number , @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_brcondi_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_brcondi_i64 ( unsigned int @@a1@@ , int @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { unsigned int @@v6@@ ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_brcond_i64 ( @@a1@@ , @@a2@@ , @@v6@@ , @@a4@@ ) ; tcg_temp_free_i64 ( @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_cond\", \"code\": \"unsigned __int64 __fastcall gen_cond ( int @@a1@@ , int @@a2@@ , int @@a3@@ , __int64 @@a4@@ ) { int @@v7@@ ; unsigned __int64 @@v8@@ ; @@v8@@ = __readfsqword ( Number ) ; if ( @@a2@@ ) @@v7@@ = cpu_xcc ; else @@v7@@ = cpu_psr ; if ( * ( _DWORD * ) ( @@a4@@ + Number ) != Number ) { gen_helper_compute_psr ( ) ; * ( _DWORD * ) ( @@a4@@ + Number ) = Number ; } switch ( @@a3@@ ) { case Number : gen_op_eval_bn ( @@a1@@ ) ; break ; case Number : gen_op_eval_be ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_ble ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bl ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bleu ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bcs ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bneg ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bvs ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_ba ( @@a1@@ ) ; break ; case Number : gen_op_eval_bne ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bg ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bge ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bgu ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bcc ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bpos ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bvc ( @@a1@@ , @@v7@@ ) ; break ; default : return __readfsqword ( Number ) ^ @@v8@@ ; } return __readfsqword ( Number ) ^ @@v8@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "do_branch", "code": "unsigned __int64 __fastcall do_branch ( __int64 @@a1@@ , int @@a2@@ , unsigned int @@a3@@ , int @@a4@@ , int @@a5@@ ) { int @@v8@@ ; int @@v9@@ ; __int64 @@v10@@ ; unsigned __int64 @@v11@@ ; @@v11@@ = __readfsqword ( Number ) ; @@v8@@ = ( @@a3@@ >> Number ) & Number ; @@v9@@ = @@a3@@ & Number ; @@v10@@ = * ( _QWORD * ) @@a1@@ + @@a2@@ ; if ( @@v8@@ ) { if ( @@v8@@ == Number ) { if ( @@v9@@ ) { * ( _QWORD * ) @@a1@@ = @@v10@@ ; * ( _QWORD * ) ( @@a1@@ + Number ) = * ( _QWORD * ) @@a1@@ + Number L ; } else { * ( _QWORD * ) @@a1@@ = * ( _QWORD * ) ( @@a1@@ + Number ) ; * ( _QWORD * ) ( @@a1@@ + Number ) = @@v10@@ ; tcg_gen_mov_i64 ( cpu_pc , cpu_npc ) ; } } else { flush_cond ( ( _QWORD * ) @@a1@@ , @@a5@@ ) ; gen_cond ( @@a5@@ , @@a4@@ , @@v8@@ , @@a1@@ ) ; if ( @@v9@@ ) { gen_branch_a ( @@a1@@ , @@v10@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , @@a5@@ ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } else { * ( _QWORD * ) @@a1@@ = * ( _QWORD * ) ( @@a1@@ + Number ) ; * ( _QWORD * ) ( @@a1@@ + Number ) = @@v10@@ ; * ( _QWORD * ) ( @@a1@@ + Number ) = * ( _QWORD * ) ( @@a1@@ + Number ) + Number L ; * ( _QWORD * ) ( @@a1@@ + Number ) = Number L ; } } } else { if ( @@v9@@ ) * ( _QWORD * ) @@a1@@ = * ( _QWORD * ) ( @@a1@@ + Number ) + Number L ; else * ( _QWORD * ) @@a1@@ = * ( _QWORD * ) ( @@a1@@ + Number ) ; * ( _QWORD * ) ( @@a1@@ + Number ) = * ( _QWORD * ) @@a1@@ + Number L ; } return __readfsqword ( Number ) ^ @@v11@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "a5", "t": {"T": 1, "n": "int", "s": 4}, "location": "r72"}, {"n": "v10", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v9", "t": {"T": 1, "n": "int", "s": 4}, "location": "s20"}, {"n": "v8", "t": {"T": 1, "n": "int", "s": 4}, "location": "s24"}, {"n": "v11", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "insn", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r16"}, {"n": "cc", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "dc", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "offset", "t": {"T": 1, "n": "int32_t", "s": 4}, "location": "r64"}, {"n": "r_cond", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r72"}, {"n": "target", "t": {"T": 1, "n": "target_ulong", "s": 8}, "location": "s16"}, {"n": "a", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s20"}, {"n": "cond", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "s24"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 294 |
[
"{\"name\": \"tcg_gen_mov_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_mov_i64 ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; if ( @@a1@@ != @@a2@@ ) tcg_gen_op2_i64 ( Number , @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_branch_a\", \"code\": \"unsigned __int64 __fastcall gen_branch_a ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { int @@v7@@ ; unsigned __int64 @@v8@@ ; @@v8@@ = __readfsqword ( Number ) ; @@v7@@ = gen_new_label ( ) ; tcg_gen_brcondi_i64 ( Number , @@a4@@ , Number L , @@v7@@ ) ; gen_goto_tb ( @@a1@@ , Number , @@a3@@ , @@a2@@ ) ; gen_set_label ( @@v7@@ ) ; gen_goto_tb ( @@a1@@ , Number , @@a3@@ + Number , @@a3@@ + Number ) ; return __readfsqword ( Number ) ^ @@v8@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"flush_cond\", \"code\": \"unsigned __int64 __fastcall flush_cond ( _QWORD * @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; if ( @@a1@@ [ Number ] == Number L ) { gen_generic_branch ( @@a1@@ [ Number ] , @@a1@@ [ Number ] , @@a2@@ ) ; @@a1@@ [ Number ] = Number L ; } return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 3, \"t\": \"_QWORD\"}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_cond\", \"code\": \"unsigned __int64 __fastcall gen_cond ( int @@a1@@ , int @@a2@@ , int @@a3@@ , __int64 @@a4@@ ) { int @@v7@@ ; unsigned __int64 @@v8@@ ; @@v8@@ = __readfsqword ( Number ) ; if ( @@a2@@ ) @@v7@@ = cpu_xcc ; else @@v7@@ = cpu_psr ; if ( * ( _DWORD * ) ( @@a4@@ + Number ) != Number ) { gen_helper_compute_psr ( ) ; * ( _DWORD * ) ( @@a4@@ + Number ) = Number ; } switch ( @@a3@@ ) { case Number : gen_op_eval_bn ( @@a1@@ ) ; break ; case Number : gen_op_eval_be ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_ble ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bl ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bleu ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bcs ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bneg ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bvs ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_ba ( @@a1@@ ) ; break ; case Number : gen_op_eval_bne ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bg ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bge ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bgu ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bcc ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bpos ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bvc ( @@a1@@ , @@v7@@ ) ; break ; default : return __readfsqword ( Number ) ^ @@v8@@ ; } return __readfsqword ( Number ) ^ @@v8@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "do_fbranch", "code": "unsigned __int64 __fastcall do_fbranch ( __int64 @@a1@@ , int @@a2@@ , unsigned int @@a3@@ , unsigned int @@a4@@ , int @@a5@@ ) { int @@v8@@ ; int @@v9@@ ; __int64 @@v10@@ ; unsigned __int64 @@v11@@ ; @@v11@@ = __readfsqword ( Number ) ; @@v8@@ = ( @@a3@@ >> Number ) & Number ; @@v9@@ = @@a3@@ & Number ; @@v10@@ = * ( _QWORD * ) @@a1@@ + @@a2@@ ; if ( @@v8@@ ) { if ( @@v8@@ == Number ) { if ( @@v9@@ ) { * ( _QWORD * ) @@a1@@ = @@v10@@ ; * ( _QWORD * ) ( @@a1@@ + Number ) = * ( _QWORD * ) @@a1@@ + Number L ; } else { * ( _QWORD * ) @@a1@@ = * ( _QWORD * ) ( @@a1@@ + Number ) ; * ( _QWORD * ) ( @@a1@@ + Number ) = @@v10@@ ; tcg_gen_mov_i64 ( cpu_pc , cpu_npc ) ; } } else { flush_cond ( ( _QWORD * ) @@a1@@ , @@a5@@ ) ; gen_fcond ( @@a5@@ , @@a4@@ , @@v8@@ ) ; if ( @@v9@@ ) { gen_branch_a ( @@a1@@ , @@v10@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , @@a5@@ ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } else { * ( _QWORD * ) @@a1@@ = * ( _QWORD * ) ( @@a1@@ + Number ) ; * ( _QWORD * ) ( @@a1@@ + Number ) = @@v10@@ ; * ( _QWORD * ) ( @@a1@@ + Number ) = * ( _QWORD * ) ( @@a1@@ + Number ) + Number L ; * ( _QWORD * ) ( @@a1@@ + Number ) = Number L ; } } } else { if ( @@v9@@ ) * ( _QWORD * ) @@a1@@ = * ( _QWORD * ) ( @@a1@@ + Number ) + Number L ; else * ( _QWORD * ) @@a1@@ = * ( _QWORD * ) ( @@a1@@ + Number ) ; * ( _QWORD * ) ( @@a1@@ + Number ) = * ( _QWORD * ) @@a1@@ + Number L ; } return __readfsqword ( Number ) ^ @@v11@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "a5", "t": {"T": 1, "n": "int", "s": 4}, "location": "r72"}, {"n": "v10", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v9", "t": {"T": 1, "n": "int", "s": 4}, "location": "s20"}, {"n": "v8", "t": {"T": 1, "n": "int", "s": 4}, "location": "s24"}, {"n": "v11", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "insn", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r16"}, {"n": "cc", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "dc", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "offset", "t": {"T": 1, "n": "int32_t", "s": 4}, "location": "r64"}, {"n": "r_cond", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r72"}, {"n": "target", "t": {"T": 1, "n": "target_ulong", "s": 8}, "location": "s16"}, {"n": "a", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s20"}, {"n": "cond", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "s24"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 295 |
[
"{\"name\": \"tcg_gen_mov_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_mov_i64 ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; if ( @@a1@@ != @@a2@@ ) tcg_gen_op2_i64 ( Number , @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_branch_a\", \"code\": \"unsigned __int64 __fastcall gen_branch_a ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { int @@v7@@ ; unsigned __int64 @@v8@@ ; @@v8@@ = __readfsqword ( Number ) ; @@v7@@ = gen_new_label ( ) ; tcg_gen_brcondi_i64 ( Number , @@a4@@ , Number L , @@v7@@ ) ; gen_goto_tb ( @@a1@@ , Number , @@a3@@ , @@a2@@ ) ; gen_set_label ( @@v7@@ ) ; gen_goto_tb ( @@a1@@ , Number , @@a3@@ + Number , @@a3@@ + Number ) ; return __readfsqword ( Number ) ^ @@v8@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"flush_cond\", \"code\": \"unsigned __int64 __fastcall flush_cond ( _QWORD * @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; if ( @@a1@@ [ Number ] == Number L ) { gen_generic_branch ( @@a1@@ [ Number ] , @@a1@@ [ Number ] , @@a2@@ ) ; @@a1@@ [ Number ] = Number L ; } return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 3, \"t\": \"_QWORD\"}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_fcond\", \"code\": \"unsigned __int64 __fastcall gen_fcond ( int @@a1@@ , unsigned int @@a2@@ , int @@a3@@ ) { int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; if ( @@a2@@ == Number ) { @@v4@@ = Number ; } else { if ( @@a2@@ > Number ) { LABEL_5 : @@v4@@ = Number ; goto LABEL_9 ; } if ( @@a2@@ == Number ) { @@v4@@ = Number ; } else { if ( @@a2@@ != Number ) goto LABEL_5 ; @@v4@@ = Number ; } } LABEL_9 : switch ( @@a3@@ ) { case Number : gen_op_eval_bn ( @@a1@@ ) ; break ; case Number : gen_op_eval_fbne ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fblg ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fbul ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fbl ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fbug ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fbg ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fbu ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_ba ( @@a1@@ ) ; break ; case Number : gen_op_eval_fbe ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fbue ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fbge ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fbuge ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fble ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fbule ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fbo ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; default : return __readfsqword ( Number ) ^ @@v5@@ ; } return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "do_branch_reg", "code": "unsigned __int64 __fastcall do_branch_reg ( __int64 @@a1@@ , int @@a2@@ , unsigned int @@a3@@ , int @@a4@@ , int @@a5@@ ) { int @@v8@@ ; int @@v9@@ ; __int64 @@v10@@ ; unsigned __int64 @@v11@@ ; @@v11@@ = __readfsqword ( Number ) ; @@v8@@ = ( @@a3@@ >> Number ) & Number ; @@v9@@ = @@a3@@ & Number ; @@v10@@ = * ( _QWORD * ) @@a1@@ + @@a2@@ ; flush_cond ( ( _QWORD * ) @@a1@@ , @@a4@@ ) ; gen_cond_reg ( @@a4@@ , @@v8@@ , @@a5@@ ) ; if ( @@v9@@ ) { gen_branch_a ( @@a1@@ , @@v10@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , @@a4@@ ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } else { * ( _QWORD * ) @@a1@@ = * ( _QWORD * ) ( @@a1@@ + Number ) ; * ( _QWORD * ) ( @@a1@@ + Number ) = @@v10@@ ; * ( _QWORD * ) ( @@a1@@ + Number ) = * ( _QWORD * ) ( @@a1@@ + Number ) + Number L ; * ( _QWORD * ) ( @@a1@@ + Number ) = Number L ; } return __readfsqword ( Number ) ^ @@v11@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "a5", "t": {"T": 1, "n": "int", "s": 4}, "location": "r72"}, {"n": "v10", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v9", "t": {"T": 1, "n": "int", "s": 4}, "location": "s20"}, {"n": "v8", "t": {"T": 1, "n": "int", "s": 4}, "location": "s24"}, {"n": "v11", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "insn", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r16"}, {"n": "r_cond", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r24"}, {"n": "dc", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "offset", "t": {"T": 1, "n": "int32_t", "s": 4}, "location": "r64"}, {"n": "r_reg", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r72"}, {"n": "target", "t": {"T": 1, "n": "target_ulong", "s": 8}, "location": "s16"}, {"n": "a", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s20"}, {"n": "cond", "t": {"T": 1, "n": "int", "s": 4}, "location": "s24"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 296 |
[
"{\"name\": \"gen_branch_a\", \"code\": \"unsigned __int64 __fastcall gen_branch_a ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { int @@v7@@ ; unsigned __int64 @@v8@@ ; @@v8@@ = __readfsqword ( Number ) ; @@v7@@ = gen_new_label ( ) ; tcg_gen_brcondi_i64 ( Number , @@a4@@ , Number L , @@v7@@ ) ; gen_goto_tb ( @@a1@@ , Number , @@a3@@ , @@a2@@ ) ; gen_set_label ( @@v7@@ ) ; gen_goto_tb ( @@a1@@ , Number , @@a3@@ + Number , @@a3@@ + Number ) ; return __readfsqword ( Number ) ^ @@v8@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"flush_cond\", \"code\": \"unsigned __int64 __fastcall flush_cond ( _QWORD * @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; if ( @@a1@@ [ Number ] == Number L ) { gen_generic_branch ( @@a1@@ [ Number ] , @@a1@@ [ Number ] , @@a2@@ ) ; @@a1@@ [ Number ] = Number L ; } return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 3, \"t\": \"_QWORD\"}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_cond\", \"code\": \"unsigned __int64 __fastcall gen_cond ( int @@a1@@ , int @@a2@@ , int @@a3@@ , __int64 @@a4@@ ) { int @@v7@@ ; unsigned __int64 @@v8@@ ; @@v8@@ = __readfsqword ( Number ) ; if ( @@a2@@ ) @@v7@@ = cpu_xcc ; else @@v7@@ = cpu_psr ; if ( * ( _DWORD * ) ( @@a4@@ + Number ) != Number ) { gen_helper_compute_psr ( ) ; * ( _DWORD * ) ( @@a4@@ + Number ) = Number ; } switch ( @@a3@@ ) { case Number : gen_op_eval_bn ( @@a1@@ ) ; break ; case Number : gen_op_eval_be ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_ble ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bl ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bleu ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bcs ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bneg ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bvs ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_ba ( @@a1@@ ) ; break ; case Number : gen_op_eval_bne ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bg ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bge ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bgu ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bcc ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bpos ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bvc ( @@a1@@ , @@v7@@ ) ; break ; default : return __readfsqword ( Number ) ^ @@v8@@ ; } return __readfsqword ( Number ) ^ @@v8@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_cond_reg\", \"code\": \"unsigned __int64 __fastcall gen_cond_reg ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { int @@v5@@ ; unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; @@v5@@ = gen_new_label ( ) ; tcg_gen_movi_i64 ( @@a1@@ , Number L ) ; tcg_gen_brcondi_i64 ( gen_tcg_cond_reg [ @@a2@@ ] , @@a3@@ , Number L , @@v5@@ ) ; tcg_gen_movi_i64 ( @@a1@@ , Number L ) ; gen_set_label ( @@v5@@ ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"do_branch\", \"code\": \"unsigned __int64 __fastcall do_branch ( __int64 @@a1@@ , int @@a2@@ , unsigned int @@a3@@ , int @@a4@@ , int @@a5@@ ) { int @@v8@@ ; int @@v9@@ ; __int64 @@v10@@ ; unsigned __int64 @@v11@@ ; @@v11@@ = __readfsqword ( Number ) ; @@v8@@ = ( @@a3@@ >> Number ) & Number ; @@v9@@ = @@a3@@ & Number ; @@v10@@ = * ( _QWORD * ) @@a1@@ + @@a2@@ ; if ( @@v8@@ ) { if ( @@v8@@ == Number ) { if ( @@v9@@ ) { * ( _QWORD * ) @@a1@@ = @@v10@@ ; * ( _QWORD * ) ( @@a1@@ + Number ) = * ( _QWORD * ) @@a1@@ + Number L ; } else { * ( _QWORD * ) @@a1@@ = * ( _QWORD * ) ( @@a1@@ + Number ) ; * ( _QWORD * ) ( @@a1@@ + Number ) = @@v10@@ ; tcg_gen_mov_i64 ( cpu_pc , cpu_npc ) ; } } else { flush_cond ( ( _QWORD * ) @@a1@@ , @@a5@@ ) ; gen_cond ( @@a5@@ , @@a4@@ , @@v8@@ , @@a1@@ ) ; if ( @@v9@@ ) { gen_branch_a ( @@a1@@ , @@v10@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , @@a5@@ ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } else { * ( _QWORD * ) @@a1@@ = * ( _QWORD * ) ( @@a1@@ + Number ) ; * ( _QWORD * ) ( @@a1@@ + Number ) = @@v10@@ ; * ( _QWORD * ) ( @@a1@@ + Number ) = * ( _QWORD * ) ( @@a1@@ + Number ) + Number L ; * ( _QWORD * ) ( @@a1@@ + Number ) = Number L ; } } } else { if ( @@v9@@ ) * ( _QWORD * ) @@a1@@ = * ( _QWORD * ) ( @@a1@@ + Number ) + Number L ; else * ( _QWORD * ) @@a1@@ = * ( _QWORD * ) ( @@a1@@ + Number ) ; * ( _QWORD * ) ( @@a1@@ + Number ) = * ( _QWORD * ) @@a1@@ + Number L ; } return __readfsqword ( Number ) ^ @@v11@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s20\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s24\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_fcmps", "code": "unsigned __int64 __fastcall gen_op_fcmps ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; if ( @@a1@@ == Number ) { gen_helper_fcmps_fcc3 ( @@a2@@ , @@a3@@ ) ; } else if ( @@a1@@ <= Number ) { if ( @@a1@@ == Number ) { gen_helper_fcmps_fcc2 ( @@a2@@ , @@a3@@ ) ; } else if ( @@a1@@ ) { if ( @@a1@@ == Number ) gen_helper_fcmps_fcc1 ( @@a2@@ , @@a3@@ ) ; } else { gen_helper_fcmps ( @@a2@@ , @@a3@@ ) ; } } return __readfsqword ( Number ) ^ @@v4@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "r_rs2", "t": {"T": 1, "n": "TCGv_i32", "s": 4}, "location": "r16"}, {"n": "fccno", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "r_rs1", "t": {"T": 1, "n": "TCGv_i32", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 297 |
[
"{\"name\": \"gen_helper_fcmps\", \"code\": \"unsigned __int64 __fastcall gen_helper_fcmps ( int @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = @@a1@@ ; @@v3@@ [ Number ] = @@a2@@ ; tcg_gen_helperN ( ( __int64 ) & helper_fcmps , Number , Number , Number , Number , ( __int64 ) @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fcmps_fcc1\", \"code\": \"unsigned __int64 __fastcall gen_helper_fcmps_fcc1 ( int @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = @@a1@@ ; @@v3@@ [ Number ] = @@a2@@ ; tcg_gen_helperN ( ( __int64 ) & helper_fcmps_fcc1 , Number , Number , Number , Number , ( __int64 ) @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fcmps_fcc2\", \"code\": \"unsigned __int64 __fastcall gen_helper_fcmps_fcc2 ( int @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = @@a1@@ ; @@v3@@ [ Number ] = @@a2@@ ; tcg_gen_helperN ( ( __int64 ) & helper_fcmps_fcc2 , Number , Number , Number , Number , ( __int64 ) @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fcmps_fcc3\", \"code\": \"unsigned __int64 __fastcall gen_helper_fcmps_fcc3 ( int @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = @@a1@@ ; @@v3@@ [ Number ] = @@a2@@ ; tcg_gen_helperN ( ( __int64 ) & helper_fcmps_fcc3 , Number , Number , Number , Number , ( __int64 ) @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_fcmpd", "code": "unsigned __int64 __fastcall gen_op_fcmpd ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; if ( @@a1@@ == Number ) { gen_helper_fcmpd_fcc3 ( ) ; } else if ( @@a1@@ <= Number ) { if ( @@a1@@ == Number ) { gen_helper_fcmpd_fcc2 ( ) ; } else if ( @@a1@@ ) { if ( @@a1@@ == Number ) gen_helper_fcmpd_fcc1 ( ) ; } else { gen_helper_fcmpd ( ) ; } } return __readfsqword ( Number ) ^ @@v2@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "v2", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "fccno", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 298 |
[
"{\"name\": \"gen_helper_fcmpd\", \"code\": \"unsigned __int64 gen_helper_fcmpd ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fcmpd , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fcmpd_fcc1\", \"code\": \"unsigned __int64 gen_helper_fcmpd_fcc1 ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fcmpd_fcc1 , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fcmpd_fcc2\", \"code\": \"unsigned __int64 gen_helper_fcmpd_fcc2 ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fcmpd_fcc2 , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fcmpd_fcc3\", \"code\": \"unsigned __int64 gen_helper_fcmpd_fcc3 ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fcmpd_fcc3 , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_fcmpq", "code": "unsigned __int64 __fastcall gen_op_fcmpq ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; if ( @@a1@@ == Number ) { gen_helper_fcmpq_fcc3 ( ) ; } else if ( @@a1@@ <= Number ) { if ( @@a1@@ == Number ) { gen_helper_fcmpq_fcc2 ( ) ; } else if ( @@a1@@ ) { if ( @@a1@@ == Number ) gen_helper_fcmpq_fcc1 ( ) ; } else { gen_helper_fcmpq ( ) ; } } return __readfsqword ( Number ) ^ @@v2@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "v2", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "fccno", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 299 |
[
"{\"name\": \"gen_helper_fcmpq\", \"code\": \"unsigned __int64 gen_helper_fcmpq ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fcmpq , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fcmpq_fcc1\", \"code\": \"unsigned __int64 gen_helper_fcmpq_fcc1 ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fcmpq_fcc1 , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fcmpq_fcc2\", \"code\": \"unsigned __int64 gen_helper_fcmpq_fcc2 ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fcmpq_fcc2 , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fcmpq_fcc3\", \"code\": \"unsigned __int64 gen_helper_fcmpq_fcc3 ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fcmpq_fcc3 , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_fcmpes", "code": "unsigned __int64 __fastcall gen_op_fcmpes ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; if ( @@a1@@ == Number ) { gen_helper_fcmpes_fcc3 ( @@a2@@ , @@a3@@ ) ; } else if ( @@a1@@ <= Number ) { if ( @@a1@@ == Number ) { gen_helper_fcmpes_fcc2 ( @@a2@@ , @@a3@@ ) ; } else if ( @@a1@@ ) { if ( @@a1@@ == Number ) gen_helper_fcmpes_fcc1 ( @@a2@@ , @@a3@@ ) ; } else { gen_helper_fcmpes ( @@a2@@ , @@a3@@ ) ; } } return __readfsqword ( Number ) ^ @@v4@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "r_rs2", "t": {"T": 1, "n": "TCGv_i32", "s": 4}, "location": "r16"}, {"n": "fccno", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "r_rs1", "t": {"T": 1, "n": "TCGv_i32", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 300 |
[
"{\"name\": \"gen_helper_fcmpes\", \"code\": \"unsigned __int64 __fastcall gen_helper_fcmpes ( int @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = @@a1@@ ; @@v3@@ [ Number ] = @@a2@@ ; tcg_gen_helperN ( ( __int64 ) & helper_fcmpes , Number , Number , Number , Number , ( __int64 ) @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fcmpes_fcc1\", \"code\": \"unsigned __int64 __fastcall gen_helper_fcmpes_fcc1 ( int @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = @@a1@@ ; @@v3@@ [ Number ] = @@a2@@ ; tcg_gen_helperN ( ( __int64 ) & helper_fcmpes_fcc1 , Number , Number , Number , Number , ( __int64 ) @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fcmpes_fcc2\", \"code\": \"unsigned __int64 __fastcall gen_helper_fcmpes_fcc2 ( int @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = @@a1@@ ; @@v3@@ [ Number ] = @@a2@@ ; tcg_gen_helperN ( ( __int64 ) & helper_fcmpes_fcc2 , Number , Number , Number , Number , ( __int64 ) @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fcmpes_fcc3\", \"code\": \"unsigned __int64 __fastcall gen_helper_fcmpes_fcc3 ( int @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = @@a1@@ ; @@v3@@ [ Number ] = @@a2@@ ; tcg_gen_helperN ( ( __int64 ) & helper_fcmpes_fcc3 , Number , Number , Number , Number , ( __int64 ) @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_fcmped", "code": "unsigned __int64 __fastcall gen_op_fcmped ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; if ( @@a1@@ == Number ) { gen_helper_fcmped_fcc3 ( ) ; } else if ( @@a1@@ <= Number ) { if ( @@a1@@ == Number ) { gen_helper_fcmped_fcc2 ( ) ; } else if ( @@a1@@ ) { if ( @@a1@@ == Number ) gen_helper_fcmped_fcc1 ( ) ; } else { gen_helper_fcmped ( ) ; } } return __readfsqword ( Number ) ^ @@v2@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "v2", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "fccno", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 301 |
[
"{\"name\": \"gen_helper_fcmped\", \"code\": \"unsigned __int64 gen_helper_fcmped ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fcmped , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fcmped_fcc1\", \"code\": \"unsigned __int64 gen_helper_fcmped_fcc1 ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fcmped_fcc1 , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fcmped_fcc2\", \"code\": \"unsigned __int64 gen_helper_fcmped_fcc2 ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fcmped_fcc2 , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fcmped_fcc3\", \"code\": \"unsigned __int64 gen_helper_fcmped_fcc3 ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fcmped_fcc3 , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_fcmpeq", "code": "unsigned __int64 __fastcall gen_op_fcmpeq ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; if ( @@a1@@ == Number ) { gen_helper_fcmpeq_fcc3 ( ) ; } else if ( @@a1@@ <= Number ) { if ( @@a1@@ == Number ) { gen_helper_fcmpeq_fcc2 ( ) ; } else if ( @@a1@@ ) { if ( @@a1@@ == Number ) gen_helper_fcmpeq_fcc1 ( ) ; } else { gen_helper_fcmpeq ( ) ; } } return __readfsqword ( Number ) ^ @@v2@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "v2", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "fccno", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 302 |
[
"{\"name\": \"gen_helper_fcmpeq\", \"code\": \"unsigned __int64 gen_helper_fcmpeq ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fcmpeq , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fcmpeq_fcc1\", \"code\": \"unsigned __int64 gen_helper_fcmpeq_fcc1 ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fcmpeq_fcc1 , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fcmpeq_fcc2\", \"code\": \"unsigned __int64 gen_helper_fcmpeq_fcc2 ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fcmpeq_fcc2 , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fcmpeq_fcc3\", \"code\": \"unsigned __int64 gen_helper_fcmpeq_fcc3 ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fcmpeq_fcc3 , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_fpexception_im", "code": "unsigned __int64 __fastcall gen_op_fpexception_im ( int @@a1@@ ) { unsigned int @@v2@@ ; unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; tcg_gen_andi_i64 ( cpu_fsr , cpu_fsr , Number ) ; tcg_gen_ori_i64 ( cpu_fsr , cpu_fsr , @@a1@@ ) ; @@v2@@ = tcg_const_i32 ( Number L ) ; gen_helper_raise_exception ( @@v2@@ ) ; tcg_temp_free_i32 ( @@v2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "v2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "v3", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "fsr_flags", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "r_const", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 303 |
[
"{\"name\": \"tcg_gen_andi_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_andi_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_and_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_ori_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_ori_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_or_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_raise_exception\", \"code\": \"unsigned __int64 __fastcall gen_helper_raise_exception ( int @@a1@@ ) { __int64 @@v2@@ ; unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; @@v2@@ = @@a1@@ ; tcg_gen_helperN ( ( __int64 ) & helper_raise_exception , Number , Number , Number , Number , ( __int64 ) & @@v2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_op_clear_ieee_excp_and_FTT", "code": "unsigned __int64 gen_op_clear_ieee_excp_and_FTT ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_andi_i64 ( cpu_fsr , cpu_fsr , Number ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }", "source": [{"n": "v1", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 304 |
[
"{\"name\": \"tcg_gen_andi_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_andi_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_and_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_clear_float_exceptions", "code": "unsigned __int64 gen_clear_float_exceptions ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; gen_helper_clear_float_exceptions ( ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }", "source": [{"n": "v1", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 305 |
[
"{\"name\": \"gen_helper_clear_float_exceptions\", \"code\": \"unsigned __int64 gen_helper_clear_float_exceptions ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_clear_float_exceptions , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_get_asi", "code": "__int64 __fastcall gen_get_asi ( int @@a1@@ ) { unsigned int @@v2@@ ; if ( ( @@a1@@ & Number ) == Number ) return ( unsigned int ) tcg_const_i32 ( ( unsigned __int8 ) ( @@a1@@ >> Number ) ) ; @@v2@@ = tcg_temp_new_i32 ( ) ; tcg_gen_mov_i32 ( @@v2@@ , cpu_asi ) ; return @@v2@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "v2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s16"}]}
|
[{"n": "insn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "r_asi", "t": {"T": 1, "n": "TCGv_i32", "s": 4}, "location": "s16"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 306 |
[
"{\"name\": \"tcg_gen_mov_i32\", \"code\": \"unsigned __int64 __fastcall tcg_gen_mov_i32 ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; if ( @@a1@@ != @@a2@@ ) tcg_gen_op2_i32 ( Number , @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_ld_asi", "code": "unsigned __int64 __fastcall gen_ld_asi ( int @@a1@@ , int @@a2@@ , int @@a3@@ , unsigned int @@a4@@ , unsigned int @@a5@@ ) { unsigned int @@v8@@ ; unsigned int @@v9@@ ; unsigned int @@v10@@ ; unsigned __int64 @@v11@@ ; @@v11@@ = __readfsqword ( Number ) ; @@v8@@ = gen_get_asi ( @@a3@@ ) ; @@v9@@ = tcg_const_i32 ( @@a4@@ ) ; @@v10@@ = tcg_const_i32 ( @@a5@@ ) ; gen_helper_ld_asi ( @@a1@@ , @@a2@@ , @@v8@@ , @@v9@@ , @@v10@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v11@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "a5", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r72"}, {"n": "v10", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "v9", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s16"}, {"n": "v8", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s20"}, {"n": "v11", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "insn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "size", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "addr", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "sign", "t": {"T": 1, "n": "int", "s": 4}, "location": "r72"}, {"n": "r_sign", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "r_size", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s16"}, {"n": "r_asi", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s20"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 307 |
[
"{\"name\": \"gen_helper_ld_asi\", \"code\": \"unsigned __int64 __fastcall gen_helper_ld_asi ( int @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ , int @@a5@@ ) { __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = @@a2@@ ; @@v6@@ [ Number ] = @@a3@@ ; @@v6@@ [ Number ] = @@a4@@ ; @@v6@@ [ Number ] = @@a5@@ ; tcg_gen_helperN ( ( __int64 ) & helper_ld_asi , Number , Number , @@a1@@ , Number , ( __int64 ) @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_get_asi\", \"code\": \"__int64 __fastcall gen_get_asi ( int @@a1@@ ) { unsigned int @@v2@@ ; if ( ( @@a1@@ & Number ) == Number ) return ( unsigned int ) tcg_const_i32 ( ( unsigned __int8 ) ( @@a1@@ >> Number ) ) ; @@v2@@ = tcg_temp_new_i32 ( ) ; tcg_gen_mov_i32 ( @@v2@@ , cpu_asi ) ; return @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s16\"}]}"
] |
{"name": "gen_st_asi", "code": "unsigned __int64 __fastcall gen_st_asi ( int @@a1@@ , int @@a2@@ , int @@a3@@ , unsigned int @@a4@@ ) { unsigned int @@v6@@ ; unsigned int @@v7@@ ; unsigned __int64 @@v8@@ ; @@v8@@ = __readfsqword ( Number ) ; @@v6@@ = gen_get_asi ( @@a3@@ ) ; @@v7@@ = tcg_const_i32 ( @@a4@@ ) ; gen_helper_st_asi ( @@a2@@ , @@a1@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v8@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v7", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "v6", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s16"}, {"n": "v8", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "insn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "size", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "src", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "addr", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "r_size", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "r_asi", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s16"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 308 |
[
"{\"name\": \"gen_helper_st_asi\", \"code\": \"unsigned __int64 __fastcall gen_helper_st_asi ( int @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int64 @@v5@@ [ Number ] ; unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; @@v5@@ [ Number ] = @@a1@@ ; @@v5@@ [ Number ] = @@a2@@ ; @@v5@@ [ Number ] = @@a3@@ ; @@v5@@ [ Number ] = @@a4@@ ; tcg_gen_helperN ( ( __int64 ) & helper_st_asi , Number , Number , Number , Number , ( __int64 ) @@v5@@ ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_get_asi\", \"code\": \"__int64 __fastcall gen_get_asi ( int @@a1@@ ) { unsigned int @@v2@@ ; if ( ( @@a1@@ & Number ) == Number ) return ( unsigned int ) tcg_const_i32 ( ( unsigned __int8 ) ( @@a1@@ >> Number ) ) ; @@v2@@ = tcg_temp_new_i32 ( ) ; tcg_gen_mov_i32 ( @@v2@@ , cpu_asi ) ; return @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s16\"}]}"
] |
{"name": "gen_ldf_asi", "code": "unsigned __int64 __fastcall gen_ldf_asi ( int @@a1@@ , int @@a2@@ , unsigned int @@a3@@ , unsigned int @@a4@@ ) { unsigned int @@v7@@ ; unsigned int @@v8@@ ; unsigned int @@v9@@ ; unsigned __int64 @@v10@@ ; @@v10@@ = __readfsqword ( Number ) ; @@v7@@ = gen_get_asi ( @@a2@@ ) ; @@v8@@ = tcg_const_i32 ( @@a3@@ ) ; @@v9@@ = tcg_const_i32 ( @@a4@@ ) ; gen_helper_ldf_asi ( @@a1@@ , @@v7@@ , @@v8@@ , @@v9@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; return __readfsqword ( Number ) ^ @@v10@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v9", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "v8", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s16"}, {"n": "v7", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s20"}, {"n": "v10", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "size", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "rd", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "addr", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "insn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "r_rd", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "r_size", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s16"}, {"n": "r_asi", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s20"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 309 |
[
"{\"name\": \"gen_helper_ldf_asi\", \"code\": \"unsigned __int64 __fastcall gen_helper_ldf_asi ( int @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int64 @@v5@@ [ Number ] ; unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; @@v5@@ [ Number ] = @@a1@@ ; @@v5@@ [ Number ] = @@a2@@ ; @@v5@@ [ Number ] = @@a3@@ ; @@v5@@ [ Number ] = @@a4@@ ; tcg_gen_helperN ( ( __int64 ) & helper_ldf_asi , Number , Number , Number , Number , ( __int64 ) @@v5@@ ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_get_asi\", \"code\": \"__int64 __fastcall gen_get_asi ( int @@a1@@ ) { unsigned int @@v2@@ ; if ( ( @@a1@@ & Number ) == Number ) return ( unsigned int ) tcg_const_i32 ( ( unsigned __int8 ) ( @@a1@@ >> Number ) ) ; @@v2@@ = tcg_temp_new_i32 ( ) ; tcg_gen_mov_i32 ( @@v2@@ , cpu_asi ) ; return @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s16\"}]}"
] |
{"name": "gen_stf_asi", "code": "unsigned __int64 __fastcall gen_stf_asi ( int @@a1@@ , int @@a2@@ , unsigned int @@a3@@ , unsigned int @@a4@@ ) { unsigned int @@v7@@ ; unsigned int @@v8@@ ; unsigned int @@v9@@ ; unsigned __int64 @@v10@@ ; @@v10@@ = __readfsqword ( Number ) ; @@v7@@ = gen_get_asi ( @@a2@@ ) ; @@v8@@ = tcg_const_i32 ( @@a3@@ ) ; @@v9@@ = tcg_const_i32 ( @@a4@@ ) ; gen_helper_stf_asi ( @@a1@@ , @@v7@@ , @@v8@@ , @@v9@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; return __readfsqword ( Number ) ^ @@v10@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v9", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "v8", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s16"}, {"n": "v7", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s20"}, {"n": "v10", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "size", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "rd", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "addr", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "insn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "r_rd", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "r_size", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s16"}, {"n": "r_asi", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s20"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 310 |
[
"{\"name\": \"gen_helper_stf_asi\", \"code\": \"unsigned __int64 __fastcall gen_helper_stf_asi ( int @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int64 @@v5@@ [ Number ] ; unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; @@v5@@ [ Number ] = @@a1@@ ; @@v5@@ [ Number ] = @@a2@@ ; @@v5@@ [ Number ] = @@a3@@ ; @@v5@@ [ Number ] = @@a4@@ ; tcg_gen_helperN ( ( __int64 ) & helper_stf_asi , Number , Number , Number , Number , ( __int64 ) @@v5@@ ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_get_asi\", \"code\": \"__int64 __fastcall gen_get_asi ( int @@a1@@ ) { unsigned int @@v2@@ ; if ( ( @@a1@@ & Number ) == Number ) return ( unsigned int ) tcg_const_i32 ( ( unsigned __int8 ) ( @@a1@@ >> Number ) ) ; @@v2@@ = tcg_temp_new_i32 ( ) ; tcg_gen_mov_i32 ( @@v2@@ , cpu_asi ) ; return @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s16\"}]}"
] |
{"name": "gen_swap_asi", "code": "unsigned __int64 __fastcall gen_swap_asi ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned int @@v4@@ ; unsigned int @@v5@@ ; unsigned int @@v6@@ ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v4@@ = gen_get_asi ( @@a3@@ ) ; @@v5@@ = tcg_const_i32 ( Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; gen_helper_ld_asi ( cpu_tmp64 , @@a2@@ , @@v4@@ , @@v5@@ , @@v6@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; gen_helper_st_asi ( @@a2@@ , @@a1@@ , @@v4@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; tcg_temp_free_i32 ( @@v4@@ ) ; tcg_gen_mov_i64 ( @@a1@@ , cpu_tmp64 ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v6", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "v5", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s16"}, {"n": "v4", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s20"}, {"n": "v7", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "insn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "addr", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "r_sign", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "r_size", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s16"}, {"n": "r_asi", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s20"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 311 |
[
"{\"name\": \"tcg_gen_mov_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_mov_i64 ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; if ( @@a1@@ != @@a2@@ ) tcg_gen_op2_i64 ( Number , @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_ld_asi\", \"code\": \"unsigned __int64 __fastcall gen_helper_ld_asi ( int @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ , int @@a5@@ ) { __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = @@a2@@ ; @@v6@@ [ Number ] = @@a3@@ ; @@v6@@ [ Number ] = @@a4@@ ; @@v6@@ [ Number ] = @@a5@@ ; tcg_gen_helperN ( ( __int64 ) & helper_ld_asi , Number , Number , @@a1@@ , Number , ( __int64 ) @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_st_asi\", \"code\": \"unsigned __int64 __fastcall gen_helper_st_asi ( int @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int64 @@v5@@ [ Number ] ; unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; @@v5@@ [ Number ] = @@a1@@ ; @@v5@@ [ Number ] = @@a2@@ ; @@v5@@ [ Number ] = @@a3@@ ; @@v5@@ [ Number ] = @@a4@@ ; tcg_gen_helperN ( ( __int64 ) & helper_st_asi , Number , Number , Number , Number , ( __int64 ) @@v5@@ ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_get_asi\", \"code\": \"__int64 __fastcall gen_get_asi ( int @@a1@@ ) { unsigned int @@v2@@ ; if ( ( @@a1@@ & Number ) == Number ) return ( unsigned int ) tcg_const_i32 ( ( unsigned __int8 ) ( @@a1@@ >> Number ) ) ; @@v2@@ = tcg_temp_new_i32 ( ) ; tcg_gen_mov_i32 ( @@v2@@ , cpu_asi ) ; return @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s16\"}]}"
] |
{"name": "gen_ldda_asi", "code": "unsigned __int64 __fastcall gen_ldda_asi ( __int64 @@a1@@ , int @@a2@@ , int @@a3@@ , unsigned int @@a4@@ ) { unsigned int @@v6@@ ; unsigned int @@v7@@ ; unsigned __int64 @@v8@@ ; @@v8@@ = __readfsqword ( Number ) ; @@v6@@ = gen_get_asi ( @@a3@@ ) ; @@v7@@ = tcg_const_i32 ( @@a4@@ ) ; gen_helper_ldda_asi ( @@a2@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v8@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v7", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "v6", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s16"}, {"n": "v8", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "insn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "rd", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "hi", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "addr", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "r_rd", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "r_asi", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s16"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 312 |
[
"{\"name\": \"gen_helper_ldda_asi\", \"code\": \"unsigned __int64 __fastcall gen_helper_ldda_asi ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { __int64 @@v4@@ [ Number ] ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ [ Number ] = @@a1@@ ; @@v4@@ [ Number ] = @@a2@@ ; @@v4@@ [ Number ] = @@a3@@ ; tcg_gen_helperN ( ( __int64 ) & helper_ldda_asi , Number , Number , Number , Number , ( __int64 ) @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_get_asi\", \"code\": \"__int64 __fastcall gen_get_asi ( int @@a1@@ ) { unsigned int @@v2@@ ; if ( ( @@a1@@ & Number ) == Number ) return ( unsigned int ) tcg_const_i32 ( ( unsigned __int8 ) ( @@a1@@ >> Number ) ) ; @@v2@@ = tcg_temp_new_i32 ( ) ; tcg_gen_mov_i32 ( @@v2@@ , cpu_asi ) ; return @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s16\"}]}"
] |
{"name": "gen_stda_asi", "code": "unsigned __int64 __fastcall gen_stda_asi ( int @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ ) { unsigned int @@v6@@ ; unsigned int @@v7@@ ; unsigned __int64 @@v8@@ ; @@v8@@ = __readfsqword ( Number ) ; gen_movl_reg_TN ( @@a4@@ + Number , cpu_tmp0 ) ; tcg_gen_concat32_i64 ( cpu_tmp64 , cpu_tmp0 , @@a1@@ ) ; @@v6@@ = gen_get_asi ( @@a3@@ ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; gen_helper_st_asi ( @@a2@@ , cpu_tmp64 , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v8@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v7", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "v6", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s16"}, {"n": "v8", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "insn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "rd", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "hi", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "addr", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "r_size", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "r_asi", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s16"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 313 |
[
"{\"name\": \"tcg_gen_concat32_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_concat32_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned int @@v5@@ ; unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; @@v5@@ = tcg_temp_new_i64 ( ) ; tcg_gen_ext32u_i64 ( @@a1@@ , @@a2@@ ) ; tcg_gen_shli_i64 ( @@v5@@ , @@a3@@ , Number L ) ; tcg_gen_or_i64 ( @@a1@@ , @@a1@@ , @@v5@@ ) ; tcg_temp_free_i64 ( @@v5@@ ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_st_asi\", \"code\": \"unsigned __int64 __fastcall gen_helper_st_asi ( int @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int64 @@v5@@ [ Number ] ; unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; @@v5@@ [ Number ] = @@a1@@ ; @@v5@@ [ Number ] = @@a2@@ ; @@v5@@ [ Number ] = @@a3@@ ; @@v5@@ [ Number ] = @@a4@@ ; tcg_gen_helperN ( ( __int64 ) & helper_st_asi , Number , Number , Number , Number , ( __int64 ) @@v5@@ ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_movl_reg_TN\", \"code\": \"unsigned __int64 __fastcall gen_movl_reg_TN ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; if ( @@a1@@ ) { if ( @@a1@@ > Number ) tcg_gen_ld_i64 ( @@a2@@ , cpu_regwptr , Number L * ( @@a1@@ - Number ) ) ; else tcg_gen_mov_i64 ( @@a2@@ , cpu_gregs [ @@a1@@ ] ) ; } else { tcg_gen_movi_i64 ( @@a2@@ , Number L ) ; } return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_get_asi\", \"code\": \"__int64 __fastcall gen_get_asi ( int @@a1@@ ) { unsigned int @@v2@@ ; if ( ( @@a1@@ & Number ) == Number ) return ( unsigned int ) tcg_const_i32 ( ( unsigned __int8 ) ( @@a1@@ >> Number ) ) ; @@v2@@ = tcg_temp_new_i32 ( ) ; tcg_gen_mov_i32 ( @@v2@@ , cpu_asi ) ; return @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s16\"}]}"
] |
{"name": "gen_cas_asi", "code": "unsigned __int64 __fastcall gen_cas_asi ( int @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ , int @@a5@@ ) { unsigned int @@v9@@ ; unsigned int @@v10@@ ; unsigned __int64 @@v11@@ ; @@v11@@ = __readfsqword ( Number ) ; @@v9@@ = tcg_temp_new_i64 ( ) ; gen_movl_reg_TN ( @@a5@@ , @@v9@@ ) ; @@v10@@ = gen_get_asi ( @@a4@@ ) ; gen_helper_cas_asi ( @@a1@@ , @@a2@@ , @@v9@@ , @@a3@@ , @@v10@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_i64 ( @@v9@@ ) ; return __readfsqword ( Number ) ^ @@v11@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "a5", "t": {"T": 1, "n": "int", "s": 4}, "location": "r72"}, {"n": "v10", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "v9", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s16"}, {"n": "v11", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "val2", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r16"}, {"n": "insn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "addr", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "rd", "t": {"T": 1, "n": "int", "s": 4}, "location": "r72"}, {"n": "r_asi", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "r_val1", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s16"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 314 |
[
"{\"name\": \"gen_helper_cas_asi\", \"code\": \"unsigned __int64 __fastcall gen_helper_cas_asi ( int @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ , int @@a5@@ ) { __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = @@a2@@ ; @@v6@@ [ Number ] = @@a3@@ ; @@v6@@ [ Number ] = @@a4@@ ; @@v6@@ [ Number ] = @@a5@@ ; tcg_gen_helperN ( ( __int64 ) & helper_cas_asi , Number , Number , @@a1@@ , Number , ( __int64 ) @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_movl_reg_TN\", \"code\": \"unsigned __int64 __fastcall gen_movl_reg_TN ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; if ( @@a1@@ ) { if ( @@a1@@ > Number ) tcg_gen_ld_i64 ( @@a2@@ , cpu_regwptr , Number L * ( @@a1@@ - Number ) ) ; else tcg_gen_mov_i64 ( @@a2@@ , cpu_gregs [ @@a1@@ ] ) ; } else { tcg_gen_movi_i64 ( @@a2@@ , Number L ) ; } return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_get_asi\", \"code\": \"__int64 __fastcall gen_get_asi ( int @@a1@@ ) { unsigned int @@v2@@ ; if ( ( @@a1@@ & Number ) == Number ) return ( unsigned int ) tcg_const_i32 ( ( unsigned __int8 ) ( @@a1@@ >> Number ) ) ; @@v2@@ = tcg_temp_new_i32 ( ) ; tcg_gen_mov_i32 ( @@v2@@ , cpu_asi ) ; return @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s16\"}]}"
] |
{"name": "gen_casx_asi", "code": "unsigned __int64 __fastcall gen_casx_asi ( int @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ , int @@a5@@ ) { unsigned int @@v8@@ ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; gen_movl_reg_TN ( @@a5@@ , cpu_tmp64 ) ; @@v8@@ = gen_get_asi ( @@a4@@ ) ; gen_helper_casx_asi ( @@a1@@ , @@a2@@ , cpu_tmp64 , @@a3@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "a5", "t": {"T": 1, "n": "int", "s": 4}, "location": "r72"}, {"n": "v8", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "v9", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "val2", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r16"}, {"n": "insn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "addr", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "rd", "t": {"T": 1, "n": "int", "s": 4}, "location": "r72"}, {"n": "r_asi", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 315 |
[
"{\"name\": \"gen_helper_casx_asi\", \"code\": \"unsigned __int64 __fastcall gen_helper_casx_asi ( int @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ , int @@a5@@ ) { __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = @@a2@@ ; @@v6@@ [ Number ] = @@a3@@ ; @@v6@@ [ Number ] = @@a4@@ ; @@v6@@ [ Number ] = @@a5@@ ; tcg_gen_helperN ( ( __int64 ) & helper_casx_asi , Number , Number , @@a1@@ , Number , ( __int64 ) @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_movl_reg_TN\", \"code\": \"unsigned __int64 __fastcall gen_movl_reg_TN ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; if ( @@a1@@ ) { if ( @@a1@@ > Number ) tcg_gen_ld_i64 ( @@a2@@ , cpu_regwptr , Number L * ( @@a1@@ - Number ) ) ; else tcg_gen_mov_i64 ( @@a2@@ , cpu_gregs [ @@a1@@ ] ) ; } else { tcg_gen_movi_i64 ( @@a2@@ , Number L ) ; } return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_get_asi\", \"code\": \"__int64 __fastcall gen_get_asi ( int @@a1@@ ) { unsigned int @@v2@@ ; if ( ( @@a1@@ & Number ) == Number ) return ( unsigned int ) tcg_const_i32 ( ( unsigned __int8 ) ( @@a1@@ >> Number ) ) ; @@v2@@ = tcg_temp_new_i32 ( ) ; tcg_gen_mov_i32 ( @@v2@@ , cpu_asi ) ; return @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s16\"}]}"
] |
{"name": "gen_ldstub_asi", "code": "unsigned __int64 __fastcall gen_ldstub_asi ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned int @@v5@@ ; unsigned int @@v6@@ ; unsigned int @@v7@@ ; unsigned __int64 @@v8@@ ; @@v8@@ = __readfsqword ( Number ) ; gen_ld_asi ( @@a1@@ , @@a2@@ , @@a3@@ , Number , Number ) ; @@v5@@ = tcg_const_i64 ( Number L ) ; @@v6@@ = tcg_const_i32 ( ( unsigned __int8 ) ( @@a3@@ >> Number ) ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; gen_helper_st_asi ( @@a2@@ , @@v5@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; tcg_temp_free_i64 ( @@v5@@ ) ; return __readfsqword ( Number ) ^ @@v8@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v7", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "v6", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s16"}, {"n": "v5", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s20"}, {"n": "v8", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "insn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "dst", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r56"}, {"n": "addr", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "r_size", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "r_asi", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s16"}, {"n": "r_val", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s20"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 316 |
[
"{\"name\": \"gen_helper_st_asi\", \"code\": \"unsigned __int64 __fastcall gen_helper_st_asi ( int @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int64 @@v5@@ [ Number ] ; unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; @@v5@@ [ Number ] = @@a1@@ ; @@v5@@ [ Number ] = @@a2@@ ; @@v5@@ [ Number ] = @@a3@@ ; @@v5@@ [ Number ] = @@a4@@ ; tcg_gen_helperN ( ( __int64 ) & helper_st_asi , Number , Number , Number , Number , ( __int64 ) @@v5@@ ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_ld_asi\", \"code\": \"unsigned __int64 __fastcall gen_ld_asi ( int @@a1@@ , int @@a2@@ , int @@a3@@ , unsigned int @@a4@@ , unsigned int @@a5@@ ) { unsigned int @@v8@@ ; unsigned int @@v9@@ ; unsigned int @@v10@@ ; unsigned __int64 @@v11@@ ; @@v11@@ = __readfsqword ( Number ) ; @@v8@@ = gen_get_asi ( @@a3@@ ) ; @@v9@@ = tcg_const_i32 ( @@a4@@ ) ; @@v10@@ = tcg_const_i32 ( @@a5@@ ) ; gen_helper_ld_asi ( @@a1@@ , @@a2@@ , @@v8@@ , @@v9@@ , @@v10@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v11@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s20\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "get_src1", "code": "__int64 __fastcall get_src1 ( unsigned int @@a1@@ , int @@a2@@ ) { unsigned int @@v3@@ ; unsigned int @@v4@@ ; @@v3@@ = @@a2@@ ; @@v4@@ = ( @@a1@@ >> Number ) & Number ; if ( @@v4@@ ) { if ( @@v4@@ > Number ) tcg_gen_ld_i64 ( @@a2@@ , cpu_regwptr , Number L * ( @@v4@@ - Number ) ) ; else @@v3@@ = cpu_gregs [ @@v4@@ ] ; } else { tcg_gen_movi_i64 ( @@a2@@ , Number L ) ; } return @@v3@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "v3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s16"}]}
|
[{"n": "insn", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r56"}, {"n": "def", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "rs1", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "r_rs1", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "s16"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 317 |
[
"{\"name\": \"tcg_gen_movi_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_movi_i64 ( int @@a1@@ , __int64 @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; tcg_gen_op2i_i64 ( Number , @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_ld_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_ld_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_ldst_op_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "get_src2", "code": "__int64 __fastcall get_src2 ( __int16 @@a1@@ , int @@a2@@ ) { unsigned int @@v3@@ ; unsigned int @@v4@@ ; __int64 @@v5@@ ; @@v3@@ = @@a2@@ ; if ( ( @@a1@@ & Number ) != Number ) { @@v5@@ = ( int ) sign_extend ( @@a1@@ & Number , Number ) ; tcg_gen_movi_i64 ( @@a2@@ , @@v5@@ ) ; } else { @@v4@@ = @@a1@@ & Number ; if ( ( @@a1@@ & Number ) != Number ) { if ( @@v4@@ > Number ) tcg_gen_ld_i64 ( @@a2@@ , cpu_regwptr , Number L * ( @@v4@@ - Number ) ) ; else @@v3@@ = cpu_gregs [ @@a1@@ & Number ] ; } else { tcg_gen_movi_i64 ( @@a2@@ , Number L ) ; } } return @@v3@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int16", "s": 2}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v4", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s20"}, {"n": "v3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s24"}]}
|
[{"n": "insn", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r56"}, {"n": "def", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "r64"}, {"n": "simm", "t": {"T": 1, "n": "int64_t", "s": 8}, "location": "s16"}, {"n": "rs2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s20"}, {"n": "r_rs2", "t": {"T": 1, "n": "TCGv_i64", "s": 4}, "location": "s24"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 318 |
[
"{\"name\": \"tcg_gen_movi_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_movi_i64 ( int @@a1@@ , __int64 @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; tcg_gen_op2i_i64 ( Number , @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_ld_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_ld_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_ldst_op_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"sign_extend\", \"code\": \"__int64 __fastcall sign_extend ( int @@a1@@ , char @@a2@@ ) { return ( unsigned int ) ( @@a1@@ << ( Number - @@a2@@ ) >> ( Number - @@a2@@ ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}"
] |
{"name": "disas_sparc_insn", "code": "unsigned __int64 __fastcall disas_sparc_insn ( _QWORD * @@a1@@ ) { unsigned int @@v2@@ ; unsigned int @@v3@@ ; int @@v4@@ ; int v5 ; int v6 ; int v7 ; int v8 ; int v9 ; int v10 ; int v11 ; int v12 ; int v13 ; int v14 ; int v15 ; int v16 ; int v17 ; int v18 ; int v19 ; int v20 ; int v21 ; int v22 ; int v23 ; int v24 ; unsigned int @@v25@@ ; int v26 ; int v27 ; int v28 ; int v29 ; unsigned int @@v30@@ ; unsigned int @@v31@@ ; int @@v32@@ ; unsigned int @@v33@@ ; unsigned int @@v34@@ ; unsigned int @@v35@@ ; unsigned int @@v36@@ ; unsigned int @@v37@@ ; unsigned int @@v38@@ ; unsigned int @@v39@@ ; unsigned int @@v40@@ ; unsigned int v41 ; unsigned int v42 ; unsigned int @@v43@@ ; unsigned int @@v44@@ ; unsigned int @@v45@@ ; unsigned int @@v46@@ ; int v47 ; int v48 ; int v49 ; unsigned int @@v50@@ ; unsigned int @@v51@@ ; unsigned int @@v52@@ ; int @@v53@@ ; unsigned int @@v54@@ ; int @@v55@@ ; int @@v56@@ ; unsigned int @@v57@@ ; int @@v58@@ ; unsigned int @@v59@@ ; unsigned int @@v60@@ ; int @@v61@@ ; unsigned int @@v62@@ ; int @@v63@@ ; unsigned int @@v64@@ ; int @@v65@@ ; unsigned int @@v66@@ ; int @@v67@@ ; unsigned int @@v68@@ ; int @@v69@@ ; unsigned int @@v70@@ ; int @@v71@@ ; unsigned int @@v72@@ ; int @@v73@@ ; unsigned int @@v74@@ ; int @@v75@@ ; unsigned int @@v76@@ ; int @@v77@@ ; unsigned int @@v78@@ ; int @@v79@@ ; unsigned int @@v80@@ ; int @@v81@@ ; unsigned int @@v82@@ ; int @@v83@@ ; unsigned int @@v84@@ ; int @@v85@@ ; unsigned int @@v86@@ ; int @@v87@@ ; unsigned int @@v88@@ ; int @@v89@@ ; unsigned int @@v90@@ ; int @@v91@@ ; unsigned int @@v92@@ ; int @@v93@@ ; unsigned int @@v94@@ ; int @@v95@@ ; unsigned int @@v96@@ ; int @@v97@@ ; int @@v98@@ ; int @@v99@@ ; unsigned int @@v100@@ ; unsigned int @@v101@@ ; unsigned int @@v102@@ ; int @@v103@@ ; unsigned int @@v104@@ ; int @@v105@@ ; int @@v106@@ ; unsigned int @@v107@@ ; int v108 ; int v109 ; int v110 ; int v111 ; int v112 ; unsigned int @@v113@@ ; int @@v114@@ ; unsigned int @@v115@@ ; __int64 v116 ; __int64 v117 ; char v118 ; char v119 ; char v120 ; __int64 v121 ; __int64 v122 ; __int64 v123 ; __int64 v124 ; __int64 v125 ; __int64 v126 ; __int64 v127 ; __int64 v128 ; __int64 v129 ; __int64 v130 ; __int64 v131 ; __int64 v132 ; __int64 v133 ; __int64 v134 ; __int64 v135 ; __int64 v136 ; unsigned __int64 @@v137@@ ; @@v137@@ = __readfsqword ( Number ) ; if ( ( loglevel & Number ) != Number ) tcg_gen_debug_insn_start ( * @@a1@@ ) ; @@v2@@ = ldl_be_p ( ( unsigned int * ) ( * @@a1@@ + guest_base ) ) ; @@v3@@ = @@v2@@ >> Number ; @@v4@@ = ( @@v2@@ >> Number ) & Number ; v5 = tcg_temp_new_i64 ( ) ; @@v25@@ = v5 ; v26 = tcg_temp_new_i64 ( ) ; @@v30@@ = v26 ; if ( @@v2@@ >> Number == Number ) { @@v31@@ = ( @@v2@@ >> Number ) & Number ; if ( * ( ( _DWORD * ) @@a1@@ + Number ) != Number ) { * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; gen_helper_compute_psr ( ) ; } v24 = get_src1 ( @@v2@@ , v5 ) ; if ( @@v31@@ == Number || @@v31@@ == Number ) { gen_movl_reg_TN ( @@v2@@ & Number , v26 ) ; tcg_gen_mov_i64 ( cpu_addr , v24 ) ; } else if ( ( @@v2@@ & Number ) != Number ) { v134 = ( int ) sign_extend ( @@v2@@ & Number , Number ) ; tcg_gen_addi_i64 ( cpu_addr , v24 , v134 ) ; } else if ( ( @@v2@@ & Number ) != Number ) { gen_movl_reg_TN ( @@v2@@ & Number , v26 ) ; tcg_gen_add_i64 ( cpu_addr , v24 , v26 ) ; } else { tcg_gen_mov_i64 ( cpu_addr , v24 ) ; } if ( @@v31@@ <= Number || @@v31@@ > Number && @@v31@@ <= Number && @@v31@@ != Number || @@v31@@ > Number && @@v31@@ <= Number || @@v31@@ > Number && @@v31@@ <= Number || @@v31@@ == Number || @@v31@@ == Number ) { switch ( @@v31@@ ) { case Number : gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; tcg_gen_qemu_ld32u ( cpu_val , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; goto LABEL_513 ; case Number : gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; tcg_gen_qemu_ld8u ( cpu_val , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; goto LABEL_513 ; case Number : gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; tcg_gen_qemu_ld16u ( cpu_val , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; goto LABEL_513 ; case Number : if ( ( @@v2@@ & Number ) != Number ) goto LABEL_580 ; save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; @@v40@@ = tcg_const_i32 ( Number L ) ; gen_helper_check_align ( cpu_addr , @@v40@@ ) ; tcg_temp_free_i32 ( @@v40@@ ) ; gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; tcg_gen_qemu_ld64 ( cpu_tmp64 , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; tcg_gen_mov_i64 ( cpu_tmp0 , cpu_tmp64 ) ; tcg_gen_andi_i64 ( cpu_tmp0 , cpu_tmp0 , Number ) ; gen_movl_TN_reg ( @@v4@@ + Number , cpu_tmp0 ) ; tcg_gen_shri_i64 ( cpu_tmp64 , cpu_tmp64 , Number L ) ; tcg_gen_mov_i64 ( cpu_val , cpu_tmp64 ) ; tcg_gen_andi_i64 ( cpu_val , cpu_val , Number ) ; goto LABEL_513 ; case Number : gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; tcg_gen_qemu_ld32s ( cpu_val , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; goto LABEL_513 ; case Number : gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; tcg_gen_qemu_ld8s ( cpu_val , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; goto LABEL_513 ; case Number : gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; tcg_gen_qemu_ld16s ( cpu_val , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; goto LABEL_513 ; case Number : gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; tcg_gen_qemu_ld64 ( cpu_val , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; goto LABEL_513 ; case Number : gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; tcg_gen_qemu_ld8s ( cpu_val , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; @@v39@@ = tcg_const_i64 ( Number L ) ; tcg_gen_qemu_st8 ( @@v39@@ , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; tcg_temp_free_i64 ( @@v39@@ ) ; goto LABEL_513 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_580 ; gen_movl_reg_TN ( @@v4@@ , cpu_val ) ; gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; tcg_gen_qemu_ld32u ( cpu_tmp0 , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; tcg_gen_qemu_st32 ( cpu_val , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; tcg_gen_mov_i64 ( cpu_val , cpu_tmp0 ) ; goto LABEL_513 ; case Number : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_ld_asi ( cpu_val , cpu_addr , @@v2@@ , Number , Number ) ; goto LABEL_513 ; case Number : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_ld_asi ( cpu_val , cpu_addr , @@v2@@ , Number , Number ) ; goto LABEL_513 ; case Number : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_ld_asi ( cpu_val , cpu_addr , @@v2@@ , Number , Number ) ; goto LABEL_513 ; case Number : if ( ( @@v2@@ & Number ) != Number ) goto LABEL_580 ; save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_ldda_asi ( ( unsigned int ) cpu_val , cpu_addr , @@v2@@ , @@v4@@ ) ; goto LABEL_566 ; case Number : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_ld_asi ( cpu_val , cpu_addr , @@v2@@ , Number , Number ) ; goto LABEL_513 ; case Number : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_ld_asi ( cpu_val , cpu_addr , @@v2@@ , Number , Number ) ; goto LABEL_513 ; case Number : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_ld_asi ( cpu_val , cpu_addr , @@v2@@ , Number , Number ) ; goto LABEL_513 ; case Number : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_ld_asi ( cpu_val , cpu_addr , @@v2@@ , Number , Number ) ; goto LABEL_513 ; case Number : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_ldstub_asi ( cpu_val , cpu_addr , @@v2@@ ) ; goto LABEL_513 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_580 ; save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_movl_reg_TN ( @@v4@@ , cpu_val ) ; gen_swap_asi ( cpu_val , cpu_addr , @@v2@@ ) ; LABEL_513 : gen_movl_TN_reg ( @@v4@@ , cpu_val ) ; break ; case Number : case Number : goto LABEL_566 ; case Number : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_ldf_asi ( cpu_addr , @@v2@@ , Number , @@v4@@ ) ; goto LABEL_566 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_ldf_asi ( cpu_addr , @@v2@@ , Number , ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_ldf_asi ( cpu_addr , @@v2@@ , Number , ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; goto LABEL_566 ; default : goto LABEL_580 ; } goto LABEL_566 ; } if ( @@v31@@ <= Number || @@v31@@ > Number ) { if ( @@v31@@ <= Number || @@v31@@ > Number && @@v31@@ <= Number || @@v31@@ == Number || @@v31@@ == Number ) { gen_movl_reg_TN ( @@v4@@ , cpu_val ) ; switch ( @@v31@@ ) { case Number : gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; tcg_gen_qemu_st32 ( cpu_val , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; goto LABEL_566 ; case Number : gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; tcg_gen_qemu_st8 ( cpu_val , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; goto LABEL_566 ; case Number : gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; tcg_gen_qemu_st16 ( cpu_val , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; goto LABEL_566 ; case Number : if ( ( @@v2@@ & Number ) != Number ) goto LABEL_580 ; save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; @@v38@@ = tcg_const_i32 ( Number L ) ; gen_helper_check_align ( cpu_addr , @@v38@@ ) ; tcg_temp_free_i32 ( @@v38@@ ) ; gen_movl_reg_TN ( @@v4@@ + Number , cpu_tmp0 ) ; tcg_gen_concat32_i64 ( cpu_tmp64 , cpu_tmp0 , cpu_val ) ; tcg_gen_qemu_st64 ( cpu_tmp64 , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; break ; case Number : gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; tcg_gen_qemu_st64 ( cpu_val , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; goto LABEL_566 ; case Number : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_st_asi ( cpu_val , cpu_addr , @@v2@@ , Number ) ; @@a1@@ [ Number ] = Number L ; goto LABEL_566 ; case Number : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_st_asi ( cpu_val , cpu_addr , @@v2@@ , Number ) ; @@a1@@ [ Number ] = Number L ; goto LABEL_566 ; case Number : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_st_asi ( cpu_val , cpu_addr , @@v2@@ , Number ) ; @@a1@@ [ Number ] = Number L ; goto LABEL_566 ; case Number : if ( ( @@v2@@ & Number ) != Number ) goto LABEL_580 ; save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_stda_asi ( cpu_val , cpu_addr , @@v2@@ , @@v4@@ ) ; break ; case Number : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_st_asi ( cpu_val , cpu_addr , @@v2@@ , Number ) ; @@a1@@ [ Number ] = Number L ; goto LABEL_566 ; default : goto LABEL_580 ; } goto LABEL_566 ; } if ( @@v31@@ > Number ) { if ( @@v31@@ <= Number || ( ( @@v2@@ >> Number ) & Number ) == Number ) goto LABEL_580 ; save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; switch ( @@v31@@ ) { case String : gen_stf_asi ( cpu_addr , @@v2@@ , Number , @@v4@@ ) ; break ; case String : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; @@v37@@ = tcg_const_i32 ( Number L ) ; gen_helper_check_align ( cpu_addr , @@v37@@ ) ; tcg_temp_free_i32 ( @@v37@@ ) ; gen_op_load_fpr_QT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_stf_asi ( cpu_addr , @@v2@@ , Number , ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case String : gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_stf_asi ( cpu_addr , @@v2@@ , Number , ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case String : gen_cas_asi ( cpu_val , cpu_addr , v26 , @@v2@@ , @@v4@@ ) ; gen_movl_TN_reg ( @@v4@@ , cpu_val ) ; break ; case String : gen_casx_asi ( cpu_val , cpu_addr , v26 , @@v2@@ , @@v4@@ ) ; gen_movl_TN_reg ( @@v4@@ , cpu_val ) ; break ; default : goto LABEL_580 ; } } else { if ( ( unsigned int ) gen_trap_ifnofpu ( @@a1@@ , ( unsigned int ) cpu_cond ) ) goto LABEL_583 ; save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; if ( @@v31@@ == Number ) { gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; @@v35@@ = tcg_const_i32 ( * ( ( unsigned int * ) @@a1@@ + Number ) ) ; gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; gen_helper_stdf ( cpu_addr , @@v35@@ ) ; tcg_temp_free_i32 ( @@v35@@ ) ; } else { if ( @@v31@@ != Number ) { if ( @@v31@@ == Number ) { gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; tcg_gen_ext_i32_i64 ( cpu_tmp0 , cpu_fpr [ @@v4@@ ] ) ; tcg_gen_qemu_st32 ( cpu_tmp0 , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; } else { gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; tcg_gen_ld_i64 ( cpu_tmp64 , cpu_env , Number L ) ; if ( @@v4@@ == Number ) tcg_gen_qemu_st64 ( cpu_tmp64 , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; else tcg_gen_qemu_st32 ( cpu_tmp64 , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; } goto LABEL_566 ; } if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_QT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; @@v36@@ = tcg_const_i32 ( * ( ( unsigned int * ) @@a1@@ + Number ) ) ; gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; gen_helper_stqf ( cpu_addr , @@v36@@ ) ; tcg_temp_free_i32 ( @@v36@@ ) ; } } } else { if ( ( unsigned int ) gen_trap_ifnofpu ( @@a1@@ , ( unsigned int ) cpu_cond ) ) goto LABEL_583 ; save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; if ( @@v31@@ == Number ) { @@v33@@ = tcg_const_i32 ( * ( ( unsigned int * ) @@a1@@ + Number ) ) ; gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; gen_helper_lddf ( cpu_addr , @@v33@@ ) ; tcg_temp_free_i32 ( @@v33@@ ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; } else { if ( @@v31@@ != Number ) { if ( @@v31@@ == Number ) { gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; tcg_gen_qemu_ld32u ( cpu_tmp0 , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; tcg_gen_trunc_i64_i32 ( cpu_fpr [ @@v4@@ ] , cpu_tmp0 ) ; } else { gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; if ( @@v4@@ == Number ) { tcg_gen_qemu_ld64 ( cpu_tmp64 , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; gen_helper_ldxfsr ( cpu_tmp64 ) ; } else { tcg_gen_qemu_ld32u ( cpu_tmp0 , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; tcg_gen_trunc_i64_i32 ( cpu_tmp32 , cpu_tmp0 ) ; gen_helper_ldfsr ( cpu_tmp32 ) ; } } goto LABEL_566 ; } if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; @@v34@@ = tcg_const_i32 ( * ( ( unsigned int * ) @@a1@@ + Number ) ) ; gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; gen_helper_ldqf ( cpu_addr , @@v34@@ ) ; tcg_temp_free_i32 ( @@v34@@ ) ; gen_op_store_QT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; } } LABEL_566 : if ( @@a1@@ [ Number ] == Number L ) { * @@a1@@ = Number L ; gen_op_next_insn ( ) ; } else if ( @@a1@@ [ Number ] == Number L ) { gen_branch2 ( ( __int64 ) @@a1@@ , @@a1@@ [ Number ] , @@a1@@ [ Number ] , cpu_cond ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; } else { * @@a1@@ = @@a1@@ [ Number ] ; @@a1@@ [ Number ] += Number L ; } goto LABEL_583 ; } if ( @@v3@@ == Number ) { v41 = ( @@v2@@ >> Number ) & Number ; switch ( v41 ) { case String : v7 = get_src1 ( @@v2@@ , v5 ) ; if ( ( @@v2@@ & Number ) != Number ) { tcg_gen_addi_i64 ( cpu_dst , v7 , @@v2@@ & Number ) ; } else if ( ( @@v2@@ & Number ) != Number ) { gen_movl_reg_TN ( @@v2@@ & Number , v26 ) ; tcg_gen_add_i64 ( cpu_dst , v7 , v26 ) ; } else { tcg_gen_mov_i64 ( cpu_dst , v7 ) ; } @@v103@@ = ( @@v2@@ >> Number ) & Number ; if ( @@v103@@ == Number ) { save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; tcg_gen_andi_i64 ( cpu_dst , cpu_dst , Number L ) ; tcg_gen_addi_i64 ( cpu_dst , cpu_dst , Number L ) ; tcg_gen_trunc_i64_i32 ( cpu_tmp32 , cpu_dst ) ; gen_helper_raise_exception ( cpu_tmp32 ) ; LABEL_35 : gen_op_next_insn ( ) ; tcg_gen_exit_tb ( Number L ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; goto LABEL_583 ; } if ( ! @@v103@@ ) goto LABEL_35 ; @@v104@@ = tcg_temp_new_i64 ( ) ; @@v105@@ = ( @@v2@@ >> Number ) & Number ; save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; if ( ! @@v105@@ ) { gen_cond ( @@v104@@ , Number , @@v103@@ , ( __int64 ) @@a1@@ ) ; LABEL_34 : @@v106@@ = gen_new_label ( ) ; tcg_gen_brcondi_i64 ( Number , @@v104@@ , Number L , @@v106@@ ) ; tcg_gen_andi_i64 ( cpu_dst , cpu_dst , Number L ) ; tcg_gen_addi_i64 ( cpu_dst , cpu_dst , Number L ) ; tcg_gen_trunc_i64_i32 ( cpu_tmp32 , cpu_dst ) ; gen_helper_raise_exception ( cpu_tmp32 ) ; gen_set_label ( @@v106@@ ) ; tcg_temp_free_i64 ( @@v104@@ ) ; goto LABEL_35 ; } if ( @@v105@@ == Number ) { gen_cond ( @@v104@@ , Number , @@v103@@ , ( __int64 ) @@a1@@ ) ; goto LABEL_34 ; } LABEL_580 : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; @@v115@@ = tcg_const_i32 ( Number L ) ; gen_helper_raise_exception ( @@v115@@ ) ; tcg_temp_free_i32 ( @@v115@@ ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; goto LABEL_583 ; case String : switch ( ( @@v2@@ >> Number ) & Number ) { case Number : gen_movl_TN_reg ( @@v4@@ , cpu_y ) ; goto LABEL_566 ; case Number : gen_helper_compute_psr ( ) ; gen_helper_rdccr ( cpu_dst ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; goto LABEL_566 ; case Number : tcg_gen_ext_i32_i64 ( cpu_dst , cpu_asi ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; goto LABEL_566 ; case Number : @@v102@@ = tcg_temp_new_i64 ( ) ; tcg_gen_ld_i64 ( @@v102@@ , cpu_env , Number L ) ; gen_helper_tick_get_count ( cpu_dst , @@v102@@ ) ; tcg_temp_free_i64 ( @@v102@@ ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; goto LABEL_566 ; case Number : @@v101@@ = tcg_const_i64 ( * @@a1@@ ) ; gen_movl_TN_reg ( @@v4@@ , @@v101@@ ) ; tcg_temp_free_i64 ( @@v101@@ ) ; goto LABEL_566 ; case Number : tcg_gen_ext_i32_i64 ( cpu_dst , cpu_fprs ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; goto LABEL_566 ; case Number : goto LABEL_566 ; case Number : if ( ( unsigned int ) gen_trap_ifnofpu ( @@a1@@ , ( unsigned int ) cpu_cond ) ) goto LABEL_583 ; gen_movl_TN_reg ( @@v4@@ , cpu_gsr ) ; break ; case Number : tcg_gen_ext_i32_i64 ( cpu_dst , cpu_softint ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; goto LABEL_566 ; case Number : gen_movl_TN_reg ( @@v4@@ , cpu_tick_cmpr ) ; goto LABEL_566 ; case Number : @@v100@@ = tcg_temp_new_i64 ( ) ; tcg_gen_ld_i64 ( @@v100@@ , cpu_env , Number L ) ; gen_helper_tick_get_count ( cpu_dst , @@v100@@ ) ; tcg_temp_free_i64 ( @@v100@@ ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; goto LABEL_566 ; case Number : gen_movl_TN_reg ( @@v4@@ , cpu_stick_cmpr ) ; goto LABEL_566 ; default : goto LABEL_580 ; } goto LABEL_566 ; case String : if ( ( unsigned int ) gen_trap_ifnofpu ( @@a1@@ , ( unsigned int ) cpu_cond ) ) goto LABEL_583 ; gen_op_clear_ieee_excp_and_FTT ( ) ; v47 = ( @@v2@@ >> Number ) & Number ; @@v32@@ = @@v2@@ & Number ; save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; switch ( ( @@v2@@ >> Number ) & Number ) { case Number : goto LABEL_53 ; case Number : tcg_gen_mov_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; goto LABEL_566 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_mov_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; break ; case Number : gen_helper_fnegs ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ @@v2@@ & Number ] ) ; goto LABEL_566 ; case Number : gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fnegd ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; goto LABEL_566 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_QT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fnegq ( ) ; gen_op_store_QT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : gen_helper_fabss ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ @@v2@@ & Number ] ) ; goto LABEL_566 ; case Number : gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fabsd ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; goto LABEL_566 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_QT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fabsq ( ) ; gen_op_store_QT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_clear_float_exceptions ( ) ; gen_helper_fsqrts ( cpu_tmp32 , cpu_fpr [ @@v2@@ & Number ] ) ; gen_helper_check_ieee_exceptions ( ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_tmp32 ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fsqrtd ( ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_QT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fsqrtq ( ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_QT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : gen_clear_float_exceptions ( ) ; gen_helper_fadds ( cpu_tmp32 , cpu_fpr [ v47 ] , cpu_fpr [ @@v2@@ & Number ] ) ; gen_helper_check_ieee_exceptions ( ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_tmp32 ) ; goto LABEL_566 ; case Number : gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_faddd ( ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; goto LABEL_566 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_QT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_QT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_faddq ( ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_QT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : gen_clear_float_exceptions ( ) ; gen_helper_fsubs ( cpu_tmp32 , cpu_fpr [ v47 ] , cpu_fpr [ @@v2@@ & Number ] ) ; gen_helper_check_ieee_exceptions ( ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_tmp32 ) ; goto LABEL_566 ; case Number : gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fsubd ( ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; goto LABEL_566 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_QT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_QT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fsubq ( ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_QT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_clear_float_exceptions ( ) ; gen_helper_fmuls ( cpu_tmp32 , cpu_fpr [ v47 ] , cpu_fpr [ @@v2@@ & Number ] ) ; gen_helper_check_ieee_exceptions ( ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_tmp32 ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fmuld ( ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number || ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_QT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_QT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fmulq ( ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_QT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : gen_clear_float_exceptions ( ) ; gen_helper_fdivs ( cpu_tmp32 , cpu_fpr [ v47 ] , cpu_fpr [ @@v2@@ & Number ] ) ; gen_helper_check_ieee_exceptions ( ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_tmp32 ) ; goto LABEL_566 ; case Number : gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fdivd ( ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; goto LABEL_566 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_QT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_QT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fdivq ( ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_QT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_clear_float_exceptions ( ) ; gen_helper_fsmuld ( cpu_fpr [ v47 ] , cpu_fpr [ @@v2@@ & Number ] ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fdmulq ( ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_QT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : gen_clear_float_exceptions ( ) ; gen_helper_fstox ( cpu_fpr [ @@v2@@ & Number ] ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; goto LABEL_566 ; case Number : gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fdtox ( ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; goto LABEL_566 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_QT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fqtox ( ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fxtos ( cpu_tmp32 ) ; gen_helper_check_ieee_exceptions ( ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_tmp32 ) ; goto LABEL_566 ; case Number : gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fxtod ( ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; goto LABEL_566 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fxtoq ( ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_QT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : gen_clear_float_exceptions ( ) ; gen_helper_fitos ( cpu_tmp32 , cpu_fpr [ @@v2@@ & Number ] ) ; gen_helper_check_ieee_exceptions ( ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_tmp32 ) ; goto LABEL_566 ; case Number : gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fdtos ( cpu_tmp32 ) ; gen_helper_check_ieee_exceptions ( ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_tmp32 ) ; goto LABEL_566 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_QT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fqtos ( cpu_tmp32 ) ; gen_helper_check_ieee_exceptions ( ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_tmp32 ) ; break ; case Number : gen_helper_fitod ( cpu_fpr [ @@v2@@ & Number ] ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; goto LABEL_566 ; case Number : gen_helper_fstod ( cpu_fpr [ @@v2@@ & Number ] ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; goto LABEL_566 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_QT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fqtod ( ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_helper_fitoq ( cpu_fpr [ @@v2@@ & Number ] ) ; gen_op_store_QT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_helper_fstoq ( cpu_fpr [ @@v2@@ & Number ] ) ; gen_op_store_QT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fdtoq ( ) ; gen_op_store_QT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : gen_clear_float_exceptions ( ) ; gen_helper_fstoi ( cpu_tmp32 , cpu_fpr [ @@v2@@ & Number ] ) ; gen_helper_check_ieee_exceptions ( ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_tmp32 ) ; goto LABEL_566 ; case Number : gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fdtoi ( cpu_tmp32 ) ; gen_helper_check_ieee_exceptions ( ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_tmp32 ) ; goto LABEL_566 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_QT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fqtoi ( cpu_tmp32 ) ; gen_helper_check_ieee_exceptions ( ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_tmp32 ) ; break ; default : goto LABEL_580 ; } goto LABEL_566 ; } if ( v41 != Number ) { switch ( v41 ) { case Number : if ( ( ( @@v2@@ >> Number ) & Number ) != Number ) { v11 = get_src1 ( @@v2@@ , v5 ) ; if ( ( @@v2@@ & Number ) != Number ) { v117 = ( int ) sign_extend ( @@v2@@ & Number , Number ) ; tcg_gen_ori_i64 ( cpu_dst , v11 , v117 ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; } else if ( ( @@v2@@ & Number ) != Number ) { gen_movl_reg_TN ( @@v2@@ & Number , v26 ) ; tcg_gen_or_i64 ( cpu_dst , v11 , v26 ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; } else { gen_movl_TN_reg ( @@v4@@ , v11 ) ; } } else if ( ( @@v2@@ & Number ) != Number ) { v116 = ( int ) sign_extend ( @@v2@@ & Number , Number ) ; @@v60@@ = tcg_const_i64 ( v116 ) ; gen_movl_TN_reg ( @@v4@@ , @@v60@@ ) ; tcg_temp_free_i64 ( @@v60@@ ) ; } else { gen_movl_reg_TN ( @@v2@@ & Number , cpu_dst ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; } goto LABEL_566 ; case Number : v12 = get_src1 ( @@v2@@ , v5 ) ; if ( ( @@v2@@ & Number ) != Number ) { v118 = sign_extend ( @@v2@@ & Number , Number ) ; if ( ( @@v2@@ & Number ) != Number ) tcg_gen_shli_i64 ( cpu_dst , v12 , v118 & Number ) ; else tcg_gen_shli_i64 ( cpu_dst , v12 , v118 & Number ) ; } else { gen_movl_reg_TN ( @@v2@@ & Number , v26 ) ; if ( ( @@v2@@ & Number ) != Number ) tcg_gen_andi_i64 ( cpu_tmp0 , v26 , Number L ) ; else tcg_gen_andi_i64 ( cpu_tmp0 , v26 , Number L ) ; tcg_gen_shl_i64 ( cpu_dst , v12 , cpu_tmp0 ) ; } break ; case Number : v13 = get_src1 ( @@v2@@ , v5 ) ; if ( ( @@v2@@ & Number ) != Number ) { v119 = sign_extend ( @@v2@@ & Number , Number ) ; if ( ( @@v2@@ & Number ) != Number ) { tcg_gen_shri_i64 ( cpu_dst , v13 , v119 & Number ) ; } else { tcg_gen_andi_i64 ( cpu_dst , v13 , Number ) ; tcg_gen_shri_i64 ( cpu_dst , cpu_dst , v119 & Number ) ; } } else { gen_movl_reg_TN ( @@v2@@ & Number , v26 ) ; if ( ( @@v2@@ & Number ) != Number ) { tcg_gen_andi_i64 ( cpu_tmp0 , v26 , Number L ) ; tcg_gen_shr_i64 ( cpu_dst , v13 , cpu_tmp0 ) ; } else { tcg_gen_andi_i64 ( cpu_tmp0 , v26 , Number L ) ; tcg_gen_andi_i64 ( cpu_dst , v13 , Number ) ; tcg_gen_shr_i64 ( cpu_dst , cpu_dst , cpu_tmp0 ) ; } } break ; case Number : v14 = get_src1 ( @@v2@@ , v5 ) ; if ( ( @@v2@@ & Number ) != Number ) { v120 = sign_extend ( @@v2@@ & Number , Number ) ; if ( ( @@v2@@ & Number ) != Number ) { tcg_gen_sari_i64 ( cpu_dst , v14 , v120 & Number ) ; } else { tcg_gen_andi_i64 ( cpu_dst , v14 , Number ) ; tcg_gen_ext32s_i64 ( cpu_dst , cpu_dst ) ; tcg_gen_sari_i64 ( cpu_dst , cpu_dst , v120 & Number ) ; } } else { gen_movl_reg_TN ( @@v2@@ & Number , v26 ) ; if ( ( @@v2@@ & Number ) != Number ) { tcg_gen_andi_i64 ( cpu_tmp0 , v26 , Number L ) ; tcg_gen_sar_i64 ( cpu_dst , v14 , cpu_tmp0 ) ; } else { tcg_gen_andi_i64 ( cpu_tmp0 , v26 , Number L ) ; tcg_gen_andi_i64 ( cpu_dst , v14 , Number ) ; tcg_gen_ext32s_i64 ( cpu_dst , cpu_dst ) ; tcg_gen_sar_i64 ( cpu_dst , cpu_dst , cpu_tmp0 ) ; } } break ; default : if ( v41 > Number ) { switch ( v41 ) { case String : v49 = ( @@v2@@ >> Number ) & Number ; @@v32@@ = @@v2@@ & Number ; if ( ( unsigned int ) gen_trap_ifnofpu ( @@a1@@ , ( unsigned int ) cpu_cond ) ) goto LABEL_583 ; switch ( ( @@v2@@ >> Number ) & Number ) { case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; v18 = get_src1 ( @@v2@@ , v5 ) ; gen_movl_reg_TN ( @@v32@@ , v26 ) ; gen_helper_array8 ( cpu_dst , v18 , v26 ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; v19 = get_src1 ( @@v2@@ , v5 ) ; gen_movl_reg_TN ( @@v32@@ , v26 ) ; gen_helper_array8 ( cpu_dst , v19 , v26 ) ; tcg_gen_shli_i64 ( cpu_dst , cpu_dst , Number L ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; v20 = get_src1 ( @@v2@@ , v5 ) ; gen_movl_reg_TN ( @@v32@@ , v26 ) ; gen_helper_array8 ( cpu_dst , v20 , v26 ) ; tcg_gen_shli_i64 ( cpu_dst , cpu_dst , Number L ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; v21 = get_src1 ( @@v2@@ , v5 ) ; gen_movl_reg_TN ( @@v32@@ , v26 ) ; gen_helper_alignaddr ( cpu_dst , v21 , v26 ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fcmple16 ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fcmpne16 ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fcmple32 ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fcmpne32 ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fcmpgt16 ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fcmpeq16 ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fcmpgt32 ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fcmpeq32 ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fmul8x16 ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fmul8x16au ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fmul8x16al ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fmul8sux16 ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fmul8ulx16 ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fmuld8sux16 ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fmuld8ulx16 ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_faligndata ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fpmerge ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fexpand ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fpadd16 ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_helper_fpadd16s ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ v49 ] , cpu_fpr [ @@v2@@ & Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fpadd32 ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_helper_fpadd32s ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ v49 ] , cpu_fpr [ @@v2@@ & Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fpsub16 ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_helper_fpsub16s ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ v49 ] , cpu_fpr [ @@v2@@ & Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fpsub32 ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_helper_fpsub32s ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ v49 ] , cpu_fpr [ @@v2@@ & Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_movi_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , Number ) ; tcg_gen_movi_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_movi_i32 ( cpu_fpr [ @@v4@@ ] , Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_nor_i32 ( cpu_tmp32 , cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_nor_i32 ( cpu_tmp32 , cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_nor_i32 ( cpu_tmp32 , cpu_fpr [ v49 ] , cpu_fpr [ @@v2@@ & Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_andc_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_andc_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_andc_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ v49 ] , cpu_fpr [ @@v2@@ & Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_not_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_not_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_not_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ @@v2@@ & Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_andc_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] , cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] ) ; tcg_gen_andc_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] , cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_andc_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ @@v2@@ & Number ] , cpu_fpr [ v49 ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_not_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] ) ; tcg_gen_not_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_not_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ v49 ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_xor_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_xor_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_xor_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ v49 ] , cpu_fpr [ @@v2@@ & Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_nand_i32 ( cpu_tmp32 , cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_nand_i32 ( cpu_tmp32 , cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_nand_i32 ( cpu_tmp32 , cpu_fpr [ v49 ] , cpu_fpr [ @@v2@@ & Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_and_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_and_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_and_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ v49 ] , cpu_fpr [ @@v2@@ & Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_xori_i32 ( cpu_tmp32 , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] , Number ) ; tcg_gen_xor_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_tmp32 , cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] ) ; tcg_gen_xori_i32 ( cpu_tmp32 , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] , Number ) ; tcg_gen_xor_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_tmp32 , cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_xori_i32 ( cpu_tmp32 , cpu_fpr [ @@v2@@ & Number ] , Number ) ; tcg_gen_xor_i32 ( cpu_fpr [ @@v4@@ ] , cpu_tmp32 , cpu_fpr [ v49 ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_mov_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ v49 ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_orc_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_orc_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_orc_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ v49 ] , cpu_fpr [ @@v2@@ & Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; LABEL_53 : tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ @@v32@@ ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_orc_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] , cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] ) ; tcg_gen_orc_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] , cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_orc_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ @@v2@@ & Number ] , cpu_fpr [ v49 ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_or_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_or_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_or_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ v49 ] , cpu_fpr [ @@v2@@ & Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_movi_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , Number ) ; tcg_gen_movi_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_movi_i32 ( cpu_fpr [ @@v4@@ ] , Number ) ; break ; default : goto LABEL_580 ; } break ; case String : goto LABEL_580 ; case String : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; v22 = get_src1 ( @@v2@@ , v5 ) ; if ( ( @@v2@@ & Number ) != Number ) { v132 = ( int ) sign_extend ( @@v2@@ & Number , Number ) ; tcg_gen_addi_i64 ( cpu_dst , v22 , v132 ) ; } else if ( ( @@v2@@ & Number ) != Number ) { gen_movl_reg_TN ( @@v2@@ & Number , v26 ) ; tcg_gen_add_i64 ( cpu_dst , v22 , v26 ) ; } else { tcg_gen_mov_i64 ( cpu_dst , v22 ) ; } gen_helper_restore ( ) ; gen_mov_pc_npc ( @@a1@@ , cpu_cond ) ; @@v46@@ = tcg_const_i32 ( Number L ) ; gen_helper_check_align ( cpu_dst , @@v46@@ ) ; tcg_temp_free_i32 ( @@v46@@ ) ; tcg_gen_mov_i64 ( cpu_npc , cpu_dst ) ; @@a1@@ [ Number ] = Number L ; goto LABEL_583 ; default : v23 = get_src1 ( @@v2@@ , v5 ) ; if ( ( @@v2@@ & Number ) != Number ) { v133 = ( int ) sign_extend ( @@v2@@ & Number , Number ) ; tcg_gen_addi_i64 ( cpu_dst , v23 , v133 ) ; } else if ( ( @@v2@@ & Number ) != Number ) { gen_movl_reg_TN ( @@v2@@ & Number , v26 ) ; tcg_gen_add_i64 ( cpu_dst , v23 , v26 ) ; } else { tcg_gen_mov_i64 ( cpu_dst , v23 ) ; } if ( v41 == Number ) { save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_helper_restore ( ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; } else { if ( v41 > Number ) goto LABEL_580 ; if ( v41 == Number ) { save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_helper_save ( ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; } else { if ( v41 == Number ) { @@v44@@ = tcg_const_i64 ( * @@a1@@ ) ; gen_movl_TN_reg ( @@v4@@ , @@v44@@ ) ; tcg_temp_free_i64 ( @@v44@@ ) ; gen_mov_pc_npc ( @@a1@@ , cpu_cond ) ; @@v45@@ = tcg_const_i32 ( Number L ) ; gen_helper_check_align ( cpu_dst , @@v45@@ ) ; tcg_temp_free_i32 ( @@v45@@ ) ; tcg_gen_mov_i64 ( cpu_npc , cpu_dst ) ; @@a1@@ [ Number ] = Number L ; goto LABEL_583 ; } if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) { save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; @@v43@@ = tcg_const_i32 ( Number L ) ; gen_helper_raise_exception ( @@v43@@ ) ; tcg_temp_free_i32 ( @@v43@@ ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; goto LABEL_583 ; } gen_helper_flush ( cpu_dst ) ; } } break ; } goto LABEL_566 ; } if ( v41 > Number ) { v16 = get_src1 ( @@v2@@ , v5 ) ; v28 = get_src2 ( @@v2@@ , v26 ) ; switch ( v41 ) { case String : gen_op_tadd_cc ( cpu_dst , v16 , v28 ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; tcg_gen_movi_i32 ( cpu_cc_op , Number ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; goto LABEL_566 ; case String : gen_op_tsub_cc ( cpu_dst , v16 , v28 ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; tcg_gen_movi_i32 ( cpu_cc_op , Number ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; goto LABEL_566 ; case String : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_op_tadd_ccTV ( cpu_dst , v16 , v28 ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; tcg_gen_movi_i32 ( cpu_cc_op , Number ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; goto LABEL_566 ; case String : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_op_tsub_ccTV ( cpu_dst , v16 , v28 ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; tcg_gen_movi_i32 ( cpu_cc_op , Number ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; goto LABEL_566 ; case String : gen_helper_compute_psr ( ) ; gen_op_mulscc ( cpu_dst , v16 , v28 ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; tcg_gen_movi_i32 ( cpu_cc_op , Number ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; goto LABEL_566 ; case String : @@v55@@ = ( @@v2@@ >> Number ) & Number ; @@v56@@ = ( @@v2@@ >> Number ) & Number ; @@v57@@ = tcg_temp_new_i64 ( ) ; if ( ( @@v2@@ & Number ) != Number ) { if ( @@v55@@ ) { if ( @@v55@@ != Number ) goto LABEL_580 ; gen_cond ( @@v57@@ , Number , @@v56@@ , ( __int64 ) @@a1@@ ) ; } else { gen_cond ( @@v57@@ , Number , @@v56@@ , ( __int64 ) @@a1@@ ) ; } } else { gen_fcond ( @@v57@@ , @@v55@@ , @@v56@@ ) ; } @@v58@@ = gen_new_label ( ) ; tcg_gen_brcondi_i64 ( Number , @@v57@@ , Number L , @@v58@@ ) ; if ( ( @@v2@@ & Number ) != Number ) { v130 = ( int ) sign_extend ( @@v2@@ & Number , Number ) ; @@v59@@ = tcg_const_i64 ( v130 ) ; gen_movl_TN_reg ( @@v4@@ , @@v59@@ ) ; tcg_temp_free_i64 ( @@v59@@ ) ; } else { gen_movl_reg_TN ( @@v2@@ & Number , cpu_tmp0 ) ; gen_movl_TN_reg ( @@v4@@ , cpu_tmp0 ) ; } gen_set_label ( @@v58@@ ) ; tcg_temp_free_i64 ( @@v57@@ ) ; break ; case String : gen_op_sdivx ( cpu_dst , v16 , v28 ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; goto LABEL_566 ; case String : v29 = get_src2 ( @@v2@@ , v28 ) ; gen_helper_popc ( cpu_dst , v29 ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; goto LABEL_311 ; case String : LABEL_311 : v17 = get_src1 ( @@v2@@ , v16 ) ; @@v53@@ = gen_new_label ( ) ; tcg_gen_brcondi_i64 ( gen_tcg_cond_reg [ ( @@v2@@ >> Number ) & Number ] , v17 , Number L , @@v53@@ ) ; if ( ( @@v2@@ & Number ) != Number ) { v131 = ( int ) sign_extend ( @@v2@@ & Number , Number ) ; @@v54@@ = tcg_const_i64 ( v131 ) ; gen_movl_TN_reg ( @@v4@@ , @@v54@@ ) ; tcg_temp_free_i64 ( @@v54@@ ) ; } else { gen_movl_reg_TN ( @@v2@@ & Number , cpu_tmp0 ) ; gen_movl_TN_reg ( @@v4@@ , cpu_tmp0 ) ; } gen_set_label ( @@v53@@ ) ; goto LABEL_566 ; case String : switch ( @@v4@@ ) { case Number : tcg_gen_xor_i64 ( cpu_tmp0 , v16 , v28 ) ; tcg_gen_andi_i64 ( cpu_y , cpu_tmp0 , Number ) ; goto LABEL_566 ; case Number : tcg_gen_xor_i64 ( cpu_dst , v16 , v28 ) ; gen_helper_wrccr ( cpu_dst ) ; tcg_gen_movi_i32 ( cpu_cc_op , Number ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; goto LABEL_566 ; case Number : tcg_gen_xor_i64 ( cpu_dst , v16 , v28 ) ; tcg_gen_andi_i64 ( cpu_dst , cpu_dst , Number L ) ; tcg_gen_trunc_i64_i32 ( cpu_asi , cpu_dst ) ; goto LABEL_566 ; case Number : tcg_gen_xor_i64 ( cpu_dst , v16 , v28 ) ; tcg_gen_trunc_i64_i32 ( cpu_fprs , cpu_dst ) ; save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_op_next_insn ( ) ; tcg_gen_exit_tb ( Number L ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; goto LABEL_566 ; case Number : goto LABEL_566 ; case Number : if ( ( unsigned int ) gen_trap_ifnofpu ( @@a1@@ , ( unsigned int ) cpu_cond ) ) goto LABEL_583 ; tcg_gen_xor_i64 ( cpu_gsr , v16 , v28 ) ; break ; case Number : tcg_gen_xor_i64 ( cpu_tick_cmpr , v16 , v28 ) ; @@v52@@ = tcg_temp_new_i64 ( ) ; tcg_gen_ld_i64 ( @@v52@@ , cpu_env , Number L ) ; gen_helper_tick_set_limit ( @@v52@@ , cpu_tick_cmpr ) ; tcg_temp_free_i64 ( @@v52@@ ) ; goto LABEL_566 ; case Number : tcg_gen_xor_i64 ( cpu_dst , v16 , v28 ) ; @@v51@@ = tcg_temp_new_i64 ( ) ; tcg_gen_ld_i64 ( @@v51@@ , cpu_env , Number L ) ; gen_helper_tick_set_count ( @@v51@@ , cpu_dst ) ; tcg_temp_free_i64 ( @@v51@@ ) ; goto LABEL_566 ; case Number : tcg_gen_xor_i64 ( cpu_stick_cmpr , v16 , v28 ) ; @@v50@@ = tcg_temp_new_i64 ( ) ; tcg_gen_ld_i64 ( @@v50@@ , cpu_env , Number L ) ; gen_helper_tick_set_limit ( @@v50@@ , cpu_stick_cmpr ) ; tcg_temp_free_i64 ( @@v50@@ ) ; goto LABEL_566 ; default : goto LABEL_580 ; } goto LABEL_566 ; default : goto LABEL_580 ; } goto LABEL_566 ; } v15 = get_src1 ( @@v2@@ , v5 ) ; v27 = get_src2 ( @@v2@@ , v26 ) ; switch ( ( @@v2@@ >> Number ) & Number ) { case Number : if ( ( @@v2@@ & Number ) != Number ) { v121 = ( int ) sign_extend ( @@v2@@ & Number , Number ) ; if ( ( ( @@v2@@ >> Number ) & Number ) != Number ) { gen_op_addi_cc ( cpu_dst , v15 , v121 ) ; tcg_gen_movi_i32 ( cpu_cc_op , Number ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; } else { tcg_gen_addi_i64 ( cpu_dst , v15 , v121 ) ; } } else if ( ( ( @@v2@@ >> Number ) & Number ) != Number ) { gen_op_add_cc ( cpu_dst , v15 , v27 ) ; tcg_gen_movi_i32 ( cpu_cc_op , Number ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; } else { tcg_gen_add_i64 ( cpu_dst , v15 , v27 ) ; } goto LABEL_216 ; case Number : if ( ( @@v2@@ & Number ) != Number ) { v122 = ( int ) sign_extend ( @@v2@@ & Number , Number ) ; tcg_gen_andi_i64 ( cpu_dst , v15 , v122 ) ; } else { tcg_gen_and_i64 ( cpu_dst , v15 , v27 ) ; } if ( ( ( @@v2@@ >> Number ) & Number ) == Number ) goto LABEL_216 ; goto LABEL_273 ; case Number : if ( ( @@v2@@ & Number ) != Number ) { v123 = ( int ) sign_extend ( @@v2@@ & Number , Number ) ; tcg_gen_ori_i64 ( cpu_dst , v15 , v123 ) ; } else { tcg_gen_or_i64 ( cpu_dst , v15 , v27 ) ; } if ( ( ( @@v2@@ >> Number ) & Number ) == Number ) goto LABEL_216 ; goto LABEL_273 ; case Number : if ( ( @@v2@@ & Number ) != Number ) { v124 = ( int ) sign_extend ( @@v2@@ & Number , Number ) ; tcg_gen_xori_i64 ( cpu_dst , v15 , v124 ) ; } else { tcg_gen_xor_i64 ( cpu_dst , v15 , v27 ) ; } if ( ( ( @@v2@@ >> Number ) & Number ) == Number ) goto LABEL_216 ; goto LABEL_273 ; case Number : if ( ( @@v2@@ & Number ) != Number ) { v125 = ( int ) sign_extend ( @@v2@@ & Number , Number ) ; if ( ( ( @@v2@@ >> Number ) & Number ) != Number ) gen_op_subi_cc ( cpu_dst , v15 , v125 , ( __int64 ) @@a1@@ ) ; else tcg_gen_subi_i64 ( cpu_dst , v15 , v125 ) ; } else if ( ( ( @@v2@@ >> Number ) & Number ) != Number ) { gen_op_sub_cc ( cpu_dst , v15 , v27 ) ; tcg_gen_movi_i32 ( cpu_cc_op , Number ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; } else { tcg_gen_sub_i64 ( cpu_dst , v15 , v27 ) ; } goto LABEL_216 ; case Number : if ( ( @@v2@@ & Number ) != Number ) { v126 = ( int ) sign_extend ( @@v2@@ & Number , Number ) ; tcg_gen_andi_i64 ( cpu_dst , v15 , ~ v126 ) ; } else { tcg_gen_andc_i64 ( cpu_dst , v15 , v27 ) ; } if ( ( ( @@v2@@ >> Number ) & Number ) == Number ) goto LABEL_216 ; goto LABEL_273 ; case Number : if ( ( @@v2@@ & Number ) != Number ) { v127 = ( int ) sign_extend ( @@v2@@ & Number , Number ) ; tcg_gen_ori_i64 ( cpu_dst , v15 , ~ v127 ) ; } else { tcg_gen_orc_i64 ( cpu_dst , v15 , v27 ) ; } if ( ( ( @@v2@@ >> Number ) & Number ) == Number ) goto LABEL_216 ; goto LABEL_273 ; case Number : if ( ( @@v2@@ & Number ) != Number ) { v128 = ( int ) sign_extend ( @@v2@@ & Number , Number ) ; tcg_gen_xori_i64 ( cpu_dst , v15 , ~ v128 ) ; } else { tcg_gen_not_i64 ( cpu_tmp0 , v27 ) ; tcg_gen_xor_i64 ( cpu_dst , v15 , cpu_tmp0 ) ; } if ( ( ( @@v2@@ >> Number ) & Number ) == Number ) goto LABEL_216 ; goto LABEL_273 ; case Number : gen_op_addx_int ( ( __int64 ) @@a1@@ , cpu_dst , v15 , v27 , ( @@v2@@ >> Number ) & Number ) ; goto LABEL_216 ; case Number : if ( ( @@v2@@ & Number ) != Number ) { v129 = ( int ) sign_extend ( @@v2@@ & Number , Number ) ; tcg_gen_muli_i64 ( cpu_dst , v15 , v129 ) ; } else { tcg_gen_mul_i64 ( cpu_dst , v15 , v27 ) ; } goto LABEL_216 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_580 ; gen_op_umul ( cpu_dst , v15 , v27 ) ; if ( ( ( @@v2@@ >> Number ) & Number ) != Number ) goto LABEL_273 ; goto LABEL_216 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_580 ; gen_op_smul ( cpu_dst , v15 , v27 ) ; if ( ( ( @@v2@@ >> Number ) & Number ) != Number ) { LABEL_273 : tcg_gen_mov_i64 ( cpu_cc_dst , cpu_dst ) ; tcg_gen_movi_i32 ( cpu_cc_op , Number ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; } break ; case Number : gen_op_subx_int ( ( __int64 ) @@a1@@ , cpu_dst , v15 , v27 , ( @@v2@@ >> Number ) & Number ) ; goto LABEL_216 ; case Number : tcg_gen_mov_i64 ( cpu_cc_src , v15 ) ; tcg_gen_mov_i64 ( cpu_cc_src2 , v27 ) ; gen_trap_ifdivzero_tl ( cpu_cc_src2 ) ; tcg_gen_divu_i64 ( cpu_dst , cpu_cc_src , cpu_cc_src2 ) ; goto LABEL_216 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_580 ; gen_helper_udiv ( cpu_dst , v15 , v27 ) ; if ( ( ( @@v2@@ >> Number ) & Number ) != Number ) { tcg_gen_mov_i64 ( cpu_cc_dst , cpu_dst ) ; tcg_gen_movi_i32 ( cpu_cc_op , Number ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; } break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_580 ; gen_helper_sdiv ( cpu_dst , v15 , v27 ) ; if ( ( ( @@v2@@ >> Number ) & Number ) != Number ) { tcg_gen_mov_i64 ( cpu_cc_dst , cpu_dst ) ; tcg_gen_movi_i32 ( cpu_cc_op , Number ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; } break ; default : goto LABEL_580 ; } break ; } LABEL_216 : gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; goto LABEL_566 ; } if ( ( unsigned int ) gen_trap_ifnofpu ( @@a1@@ , ( unsigned int ) cpu_cond ) ) goto LABEL_583 ; gen_op_clear_ieee_excp_and_FTT ( ) ; v48 = ( @@v2@@ >> Number ) & Number ; v42 = ( @@v2@@ >> Number ) & Number ; save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; switch ( ( @@v2@@ >> Number ) & Number ) { case Number : @@v99@@ = gen_new_label ( ) ; v8 = get_src1 ( @@v2@@ , v5 ) ; tcg_gen_brcondi_i64 ( gen_tcg_cond_reg [ ( @@v2@@ >> Number ) & Number ] , v8 , Number L , @@v99@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ @@v2@@ & Number ] ) ; gen_set_label ( @@v99@@ ) ; goto LABEL_566 ; case Number : @@v98@@ = gen_new_label ( ) ; v9 = get_src1 ( @@v2@@ , v5 ) ; tcg_gen_brcondi_i64 ( gen_tcg_cond_reg [ ( @@v2@@ >> Number ) & Number ] , v9 , Number L , @@v98@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; gen_set_label ( @@v98@@ ) ; goto LABEL_566 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) != Number ) { @@v97@@ = gen_new_label ( ) ; v10 = get_src1 ( @@v2@@ , v5 ) ; tcg_gen_brcondi_i64 ( gen_tcg_cond_reg [ ( @@v2@@ >> Number ) & Number ] , v10 , Number L , @@v97@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; gen_set_label ( @@v97@@ ) ; goto LABEL_566 ; } LABEL_582 : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_op_fpexception_im ( Number ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; goto LABEL_583 ; } if ( v42 == Number ) { if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; @@v61@@ = gen_new_label ( ) ; @@v62@@ = tcg_temp_new_i64 ( ) ; gen_cond ( @@v62@@ , Number , ( @@v2@@ >> Number ) & Number , ( __int64 ) @@a1@@ ) ; tcg_gen_brcondi_i64 ( Number , @@v62@@ , Number L , @@v61@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; gen_set_label ( @@v61@@ ) ; tcg_temp_free_i64 ( @@v62@@ ) ; goto LABEL_566 ; } if ( v42 > Number ) goto LABEL_580 ; if ( v42 == Number ) { @@v63@@ = gen_new_label ( ) ; @@v64@@ = tcg_temp_new_i64 ( ) ; gen_cond ( @@v64@@ , Number , ( @@v2@@ >> Number ) & Number , ( __int64 ) @@a1@@ ) ; tcg_gen_brcondi_i64 ( Number , @@v64@@ , Number L , @@v63@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; gen_set_label ( @@v63@@ ) ; tcg_temp_free_i64 ( @@v64@@ ) ; goto LABEL_566 ; } if ( v42 == Number ) { @@v65@@ = gen_new_label ( ) ; @@v66@@ = tcg_temp_new_i64 ( ) ; gen_cond ( @@v66@@ , Number , ( @@v2@@ >> Number ) & Number , ( __int64 ) @@a1@@ ) ; tcg_gen_brcondi_i64 ( Number , @@v66@@ , Number L , @@v65@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ @@v2@@ & Number ] ) ; gen_set_label ( @@v65@@ ) ; tcg_temp_free_i64 ( @@v66@@ ) ; goto LABEL_566 ; } if ( v42 != Number ) { if ( v42 > Number ) goto LABEL_580 ; if ( v42 != Number ) { if ( v42 == Number ) { @@v71@@ = gen_new_label ( ) ; @@v72@@ = tcg_temp_new_i64 ( ) ; gen_cond ( @@v72@@ , Number , ( @@v2@@ >> Number ) & Number , ( __int64 ) @@a1@@ ) ; tcg_gen_brcondi_i64 ( Number , @@v72@@ , Number L , @@v71@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ @@v2@@ & Number ] ) ; gen_set_label ( @@v71@@ ) ; tcg_temp_free_i64 ( @@v72@@ ) ; } else if ( v42 == Number ) { if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; @@v73@@ = gen_new_label ( ) ; @@v74@@ = tcg_temp_new_i64 ( ) ; gen_fcond ( @@v74@@ , Number , ( @@v2@@ >> Number ) & Number ) ; tcg_gen_brcondi_i64 ( Number , @@v74@@ , Number L , @@v73@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; gen_set_label ( @@v73@@ ) ; tcg_temp_free_i64 ( @@v74@@ ) ; } else { if ( v42 > Number ) goto LABEL_580 ; if ( v42 == Number ) { @@v75@@ = gen_new_label ( ) ; @@v76@@ = tcg_temp_new_i64 ( ) ; gen_fcond ( @@v76@@ , Number , ( @@v2@@ >> Number ) & Number ) ; tcg_gen_brcondi_i64 ( Number , @@v76@@ , Number L , @@v75@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; gen_set_label ( @@v75@@ ) ; tcg_temp_free_i64 ( @@v76@@ ) ; } else if ( v42 == Number ) { @@v77@@ = gen_new_label ( ) ; @@v78@@ = tcg_temp_new_i64 ( ) ; gen_fcond ( @@v78@@ , Number , ( @@v2@@ >> Number ) & Number ) ; tcg_gen_brcondi_i64 ( Number , @@v78@@ , Number L , @@v77@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ @@v2@@ & Number ] ) ; gen_set_label ( @@v77@@ ) ; tcg_temp_free_i64 ( @@v78@@ ) ; } else { if ( v42 > Number ) goto LABEL_580 ; if ( v42 >= Number ) { switch ( v42 ) { case Number : @@v89@@ = gen_new_label ( ) ; @@v90@@ = tcg_temp_new_i64 ( ) ; gen_fcond ( @@v90@@ , Number , ( @@v2@@ >> Number ) & Number ) ; tcg_gen_brcondi_i64 ( Number , @@v90@@ , Number L , @@v89@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ @@v2@@ & Number ] ) ; gen_set_label ( @@v89@@ ) ; tcg_temp_free_i64 ( @@v90@@ ) ; goto LABEL_566 ; case Number : @@v87@@ = gen_new_label ( ) ; @@v88@@ = tcg_temp_new_i64 ( ) ; gen_fcond ( @@v88@@ , Number , ( @@v2@@ >> Number ) & Number ) ; tcg_gen_brcondi_i64 ( Number , @@v88@@ , Number L , @@v87@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; gen_set_label ( @@v87@@ ) ; tcg_temp_free_i64 ( @@v88@@ ) ; goto LABEL_566 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; @@v85@@ = gen_new_label ( ) ; @@v86@@ = tcg_temp_new_i64 ( ) ; gen_fcond ( @@v86@@ , Number , ( @@v2@@ >> Number ) & Number ) ; tcg_gen_brcondi_i64 ( Number , @@v86@@ , Number L , @@v85@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; gen_set_label ( @@v85@@ ) ; tcg_temp_free_i64 ( @@v86@@ ) ; break ; case Number : gen_op_fcmps ( ( @@v2@@ >> Number ) & Number , cpu_fpr [ v48 ] , cpu_fpr [ @@v2@@ & Number ] ) ; goto LABEL_566 ; case Number : gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_op_fcmpd ( ( @@v2@@ >> Number ) & Number ) ; goto LABEL_566 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_QT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_QT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_op_fcmpq ( ( @@v2@@ >> Number ) & Number ) ; break ; case Number : gen_op_fcmpes ( ( @@v2@@ >> Number ) & Number , cpu_fpr [ v48 ] , cpu_fpr [ @@v2@@ & Number ] ) ; goto LABEL_566 ; case Number : gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_op_fcmped ( ( @@v2@@ >> Number ) & Number ) ; goto LABEL_566 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_QT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_QT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_op_fcmpeq ( ( @@v2@@ >> Number ) & Number ) ; break ; case Number : @@v83@@ = gen_new_label ( ) ; @@v84@@ = tcg_temp_new_i64 ( ) ; gen_fcond ( @@v84@@ , Number , ( @@v2@@ >> Number ) & Number ) ; tcg_gen_brcondi_i64 ( Number , @@v84@@ , Number L , @@v83@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ @@v2@@ & Number ] ) ; gen_set_label ( @@v83@@ ) ; tcg_temp_free_i64 ( @@v84@@ ) ; goto LABEL_566 ; case Number : @@v81@@ = gen_new_label ( ) ; @@v82@@ = tcg_temp_new_i64 ( ) ; gen_fcond ( @@v82@@ , Number , ( @@v2@@ >> Number ) & Number ) ; tcg_gen_brcondi_i64 ( Number , @@v82@@ , Number L , @@v81@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; gen_set_label ( @@v81@@ ) ; tcg_temp_free_i64 ( @@v82@@ ) ; goto LABEL_566 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; @@v79@@ = gen_new_label ( ) ; @@v80@@ = tcg_temp_new_i64 ( ) ; gen_fcond ( @@v80@@ , Number , ( @@v2@@ >> Number ) & Number ) ; tcg_gen_brcondi_i64 ( Number , @@v80@@ , Number L , @@v79@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; gen_set_label ( @@v79@@ ) ; tcg_temp_free_i64 ( @@v80@@ ) ; break ; default : goto LABEL_580 ; } goto LABEL_566 ; } if ( v42 == Number ) { if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; @@v91@@ = gen_new_label ( ) ; @@v92@@ = tcg_temp_new_i64 ( ) ; gen_fcond ( @@v92@@ , Number , ( @@v2@@ >> Number ) & Number ) ; tcg_gen_brcondi_i64 ( Number , @@v92@@ , Number L , @@v91@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; gen_set_label ( @@v91@@ ) ; tcg_temp_free_i64 ( @@v92@@ ) ; } else { if ( v42 > Number ) goto LABEL_580 ; if ( v42 == Number ) { @@v95@@ = gen_new_label ( ) ; @@v96@@ = tcg_temp_new_i64 ( ) ; gen_fcond ( @@v96@@ , Number , ( @@v2@@ >> Number ) & Number ) ; tcg_gen_brcondi_i64 ( Number , @@v96@@ , Number L , @@v95@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ @@v2@@ & Number ] ) ; gen_set_label ( @@v95@@ ) ; tcg_temp_free_i64 ( @@v96@@ ) ; } else { if ( v42 != Number ) goto LABEL_580 ; @@v93@@ = gen_new_label ( ) ; @@v94@@ = tcg_temp_new_i64 ( ) ; gen_fcond ( @@v94@@ , Number , ( @@v2@@ >> Number ) & Number ) ; tcg_gen_brcondi_i64 ( Number , @@v94@@ , Number L , @@v93@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; gen_set_label ( @@v93@@ ) ; tcg_temp_free_i64 ( @@v94@@ ) ; } } } } goto LABEL_566 ; } @@v67@@ = gen_new_label ( ) ; @@v68@@ = tcg_temp_new_i64 ( ) ; gen_cond ( @@v68@@ , Number , ( @@v2@@ >> Number ) & Number , ( __int64 ) @@a1@@ ) ; tcg_gen_brcondi_i64 ( Number , @@v68@@ , Number L , @@v67@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; gen_set_label ( @@v67@@ ) ; tcg_temp_free_i64 ( @@v68@@ ) ; } if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; @@v69@@ = gen_new_label ( ) ; @@v70@@ = tcg_temp_new_i64 ( ) ; gen_cond ( @@v70@@ , Number , ( @@v2@@ >> Number ) & Number , ( __int64 ) @@a1@@ ) ; tcg_gen_brcondi_i64 ( Number , @@v70@@ , Number L , @@v69@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; gen_set_label ( @@v69@@ ) ; tcg_temp_free_i64 ( @@v70@@ ) ; goto LABEL_566 ; } if ( @@v3@@ ) { v135 = ( int ) ( Number * sign_extend ( @@v2@@ & Number , Number ) ) ; @@v107@@ = tcg_const_i64 ( * @@a1@@ ) ; gen_movl_TN_reg ( Number , @@v107@@ ) ; tcg_temp_free_i64 ( @@v107@@ ) ; v136 = * @@a1@@ + v135 ; gen_mov_pc_npc ( @@a1@@ , cpu_cond ) ; @@a1@@ [ Number ] = v136 ; } else { switch ( ( @@v2@@ >> Number ) & Number ) { case Number : v108 = Number * sign_extend ( @@v2@@ & Number , Number ) ; @@v114@@ = ( @@v2@@ >> Number ) & Number ; if ( ! @@v114@@ ) { do_branch ( ( __int64 ) @@a1@@ , v108 , @@v2@@ , Number , cpu_cond ) ; break ; } if ( @@v114@@ != Number ) goto LABEL_580 ; do_branch ( ( __int64 ) @@a1@@ , v108 , @@v2@@ , Number , cpu_cond ) ; break ; case Number : v111 = Number * sign_extend ( @@v2@@ & Number , Number ) ; do_branch ( ( __int64 ) @@a1@@ , v111 , @@v2@@ , Number , cpu_cond ) ; break ; case Number : v109 = Number * sign_extend ( @@v2@@ & Number | ( unsigned __int16 ) ( @@v2@@ >> Number << Number ) , Number ) ; v6 = get_src1 ( @@v2@@ , v5 ) ; do_branch_reg ( ( __int64 ) @@a1@@ , v109 , @@v2@@ , cpu_cond , v6 ) ; break ; case Number : if ( @@v4@@ ) { @@v113@@ = tcg_const_i64 ( @@v2@@ << Number ) ; gen_movl_TN_reg ( @@v4@@ , @@v113@@ ) ; tcg_temp_free_i64 ( @@v113@@ ) ; } goto LABEL_566 ; case Number : if ( ! ( unsigned int ) gen_trap_ifnofpu ( @@a1@@ , ( unsigned int ) cpu_cond ) ) { v110 = Number * sign_extend ( @@v2@@ & Number , Number ) ; do_fbranch ( ( __int64 ) @@a1@@ , v110 , @@v2@@ , ( @@v2@@ >> Number ) & Number , cpu_cond ) ; } break ; case Number : if ( ! ( unsigned int ) gen_trap_ifnofpu ( @@a1@@ , ( unsigned int ) cpu_cond ) ) { v112 = Number * sign_extend ( @@v2@@ & Number , Number ) ; do_fbranch ( ( __int64 ) @@a1@@ , v112 , @@v2@@ , Number , cpu_cond ) ; } break ; default : goto LABEL_580 ; } } LABEL_583 : tcg_temp_free_i64 ( @@v25@@ ) ; tcg_temp_free_i64 ( @@v30@@ ) ; return __readfsqword ( Number ) ^ @@v137@@ ; }", "source": [{"n": "a1", "t": {"T": 3, "t": "_QWORD"}, "location": "r56"}, {"n": "v96", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s100"}, {"n": "v95", "t": {"T": 1, "n": "int", "s": 4}, "location": "s104"}, {"n": "v94", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s108"}, {"n": "v93", "t": {"T": 1, "n": "int", "s": 4}, "location": "s112"}, {"n": "v92", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s116"}, {"n": "v91", "t": {"T": 1, "n": "int", "s": 4}, "location": "s120"}, {"n": "v90", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s124"}, {"n": "v89", "t": {"T": 1, "n": "int", "s": 4}, "location": "s128"}, {"n": "v88", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s132"}, {"n": "v87", "t": {"T": 1, "n": "int", "s": 4}, "location": "s136"}, {"n": "v86", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s140"}, {"n": "v85", "t": {"T": 1, "n": "int", "s": 4}, "location": "s144"}, {"n": "v84", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s148"}, {"n": "v83", "t": {"T": 1, "n": "int", "s": 4}, "location": "s152"}, {"n": "v82", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s156"}, {"n": "v81", "t": {"T": 1, "n": "int", "s": 4}, "location": "s160"}, {"n": "v80", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s164"}, {"n": "v79", "t": {"T": 1, "n": "int", "s": 4}, "location": "s168"}, {"n": "v78", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s172"}, {"n": "v77", "t": {"T": 1, "n": "int", "s": 4}, "location": "s176"}, {"n": "v76", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s180"}, {"n": "v75", "t": {"T": 1, "n": "int", "s": 4}, "location": "s184"}, {"n": "v74", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s188"}, {"n": "v73", "t": {"T": 1, "n": "int", "s": 4}, "location": "s192"}, {"n": "v72", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s196"}, {"n": "v71", "t": {"T": 1, "n": "int", "s": 4}, "location": "s200"}, {"n": "v70", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s204"}, {"n": "v69", "t": {"T": 1, "n": "int", "s": 4}, "location": "s208"}, {"n": "v68", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s212"}, {"n": "v67", "t": {"T": 1, "n": "int", "s": 4}, "location": "s216"}, {"n": "v66", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s220"}, {"n": "v65", "t": {"T": 1, "n": "int", "s": 4}, "location": "s224"}, {"n": "v64", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s228"}, {"n": "v63", "t": {"T": 1, "n": "int", "s": 4}, "location": "s232"}, {"n": "v62", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s240"}, {"n": "v61", "t": {"T": 1, "n": "int", "s": 4}, "location": "s244"}, {"n": "v60", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s248"}, {"n": "v59", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s252"}, {"n": "v58", "t": {"T": 1, "n": "int", "s": 4}, "location": "s256"}, {"n": "v57", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s260"}, {"n": "v56", "t": {"T": 1, "n": "int", "s": 4}, "location": "s264"}, {"n": "v55", "t": {"T": 1, "n": "int", "s": 4}, "location": "s268"}, {"n": "v54", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s272"}, {"n": "v53", "t": {"T": 1, "n": "int", "s": 4}, "location": "s276"}, {"n": "v115", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s28"}, {"n": "v52", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s284"}, {"n": "v51", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s288"}, {"n": "v50", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s292"}, {"n": "v46", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s304"}, {"n": "v45", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s308"}, {"n": "v44", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s312"}, {"n": "v43", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s316"}, {"n": "v114", "t": {"T": 1, "n": "int", "s": 4}, "location": "s32"}, {"n": "v40", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s324"}, {"n": "v39", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s328"}, {"n": "v38", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s332"}, {"n": "v37", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s336"}, {"n": "v36", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s340"}, {"n": "v35", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s344"}, {"n": "v34", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s348"}, {"n": "v33", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s352"}, {"n": "v32", "t": {"T": 1, "n": "int", "s": 4}, "location": "s356"}, {"n": "v113", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s36"}, {"n": "v31", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s360"}, {"n": "v30", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s364"}, {"n": "v25", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s372"}, {"n": "v4", "t": {"T": 1, "n": "int", "s": 4}, "location": "s380"}, {"n": "v3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s384"}, {"n": "v2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s388"}, {"n": "v107", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s56"}, {"n": "v106", "t": {"T": 1, "n": "int", "s": 4}, "location": "s60"}, {"n": "v105", "t": {"T": 1, "n": "int", "s": 4}, "location": "s64"}, {"n": "v104", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s68"}, {"n": "v103", "t": {"T": 1, "n": "int", "s": 4}, "location": "s72"}, {"n": "v102", "t": {"T": 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|
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|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 319 |
[
"{\"name\": \"ldl_be_p\", \"code\": \"__int64 __fastcall ldl_be_p ( unsigned int * @@a1@@ ) { return _byteswap_ulong ( * @@a1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 3, \"t\": \"unsigned int\"}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_set_label\", \"code\": \"unsigned __int64 __fastcall gen_set_label ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_op1i ( Number , @@a1@@ ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_br\", \"code\": \"unsigned __int64 __fastcall tcg_gen_br ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_op1i ( Number , @@a1@@ ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_mov_i32\", \"code\": \"unsigned __int64 __fastcall tcg_gen_mov_i32 ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; if ( @@a1@@ != @@a2@@ ) tcg_gen_op2_i32 ( Number , @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_movi_i32\", \"code\": \"unsigned __int64 __fastcall tcg_gen_movi_i32 ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; tcg_gen_op2i_i32 ( Number , @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_and_i32\", \"code\": \"unsigned __int64 __fastcall tcg_gen_and_i32 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; if ( @@a2@@ == @@a3@@ ) tcg_gen_mov_i32 ( @@a1@@ , @@a2@@ ) ; else tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_or_i32\", \"code\": \"unsigned __int64 __fastcall tcg_gen_or_i32 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; if ( @@a2@@ == @@a3@@ ) tcg_gen_mov_i32 ( @@a1@@ , @@a2@@ ) ; else tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_xor_i32\", \"code\": \"unsigned __int64 __fastcall tcg_gen_xor_i32 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; if ( @@a2@@ == @@a3@@ ) tcg_gen_movi_i32 ( @@a1@@ , Number ) ; else tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_xori_i32\", \"code\": \"unsigned __int64 __fastcall tcg_gen_xori_i32 ( int @@a1@@ , int @@a2@@ , unsigned int @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; if ( @@a3@@ ) { @@v4@@ = tcg_const_i32 ( @@a3@@ ) ; tcg_gen_xor_i32 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i32 ( @@v4@@ ) ; } else { tcg_gen_mov_i32 ( @@a1@@ , @@a2@@ ) ; } return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_mov_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_mov_i64 ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; if ( @@a1@@ != @@a2@@ ) tcg_gen_op2_i64 ( Number , @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_ld_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_ld_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_ldst_op_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
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"{\"name\": \"tcg_gen_sub_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_sub_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
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"{\"name\": \"tcg_gen_or_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_or_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; if ( @@a2@@ == @@a3@@ ) tcg_gen_mov_i64 ( @@a1@@ , @@a2@@ ) ; else tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_ori_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_ori_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_or_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_xor_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_xor_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; if ( @@a2@@ == @@a3@@ ) tcg_gen_movi_i64 ( @@a1@@ , Number L ) ; else tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_xori_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_xori_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_xor_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_shl_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_shl_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_shli_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_shli_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; if ( @@a3@@ ) { @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_shl_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; } else { tcg_gen_mov_i64 ( @@a1@@ , @@a2@@ ) ; } return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_shr_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_shr_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_shri_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_shri_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; if ( @@a3@@ ) { @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_shr_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; } else { tcg_gen_mov_i64 ( @@a1@@ , @@a2@@ ) ; } return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_sar_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_sar_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_sari_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_sari_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; if ( @@a3@@ ) { @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_sar_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; } else { tcg_gen_mov_i64 ( @@a1@@ , @@a2@@ ) ; } return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_mul_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_mul_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_divu_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_divu_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned int @@v5@@ ; unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; @@v5@@ = tcg_temp_new_i64 ( ) ; tcg_gen_movi_i64 ( @@v5@@ , Number L ) ; tcg_gen_op5_i64 ( Number , @@a1@@ , @@v5@@ , @@a2@@ , @@v5@@ , @@a3@@ ) ; tcg_temp_free_i64 ( @@v5@@ ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_addi_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_addi_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; if ( @@a3@@ ) { @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_add_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; } else { tcg_gen_mov_i64 ( @@a1@@ , @@a2@@ ) ; } return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_subi_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_subi_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; if ( @@a3@@ ) { @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_sub_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; } else { tcg_gen_mov_i64 ( @@a1@@ , @@a2@@ ) ; } return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_brcondi_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_brcondi_i64 ( unsigned int @@a1@@ , int @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { unsigned int @@v6@@ ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_brcond_i64 ( @@a1@@ , @@a2@@ , @@v6@@ , @@a4@@ ) ; tcg_temp_free_i64 ( @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_muli_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_muli_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_mul_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_ext32s_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_ext32s_i64 ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; tcg_gen_op2_i64 ( Number , @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_trunc_i64_i32\", \"code\": \"unsigned __int64 __fastcall tcg_gen_trunc_i64_i32 ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; tcg_gen_mov_i32 ( @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_ext_i32_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_ext_i32_i64 ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; tcg_gen_ext32s_i64 ( @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_not_i32\", \"code\": \"unsigned __int64 __fastcall tcg_gen_not_i32 ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; tcg_gen_op2_i32 ( Number , @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_not_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_not_i64 ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; tcg_gen_op2_i64 ( Number , @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_concat32_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_concat32_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned int @@v5@@ ; unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; @@v5@@ = tcg_temp_new_i64 ( ) ; tcg_gen_ext32u_i64 ( @@a1@@ , @@a2@@ ) ; tcg_gen_shli_i64 ( @@v5@@ , @@a3@@ , Number L ) ; tcg_gen_or_i64 ( @@a1@@ , @@a1@@ , @@v5@@ ) ; tcg_temp_free_i64 ( @@v5@@ ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_andc_i32\", \"code\": \"unsigned __int64 __fastcall tcg_gen_andc_i32 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned int @@v5@@ ; unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_not_i32 ( @@v5@@ , @@a3@@ ) ; tcg_gen_and_i32 ( @@a1@@ , @@a2@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_andc_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_andc_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned int @@v5@@ ; unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; @@v5@@ = tcg_temp_new_i64 ( ) ; tcg_gen_not_i64 ( @@v5@@ , @@a3@@ ) ; tcg_gen_and_i64 ( @@a1@@ , @@a2@@ , @@v5@@ ) ; tcg_temp_free_i64 ( @@v5@@ ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_nand_i32\", \"code\": \"unsigned __int64 __fastcall tcg_gen_nand_i32 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_and_i32 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_not_i32 ( @@a1@@ , @@a1@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_nor_i32\", \"code\": \"unsigned __int64 __fastcall tcg_gen_nor_i32 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_or_i32 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_not_i32 ( @@a1@@ , @@a1@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_orc_i32\", \"code\": \"unsigned __int64 __fastcall tcg_gen_orc_i32 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned int @@v5@@ ; unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_not_i32 ( @@v5@@ , @@a3@@ ) ; tcg_gen_or_i32 ( @@a1@@ , @@a2@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_orc_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_orc_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned int @@v5@@ ; unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; @@v5@@ = tcg_temp_new_i64 ( ) ; tcg_gen_not_i64 ( @@v5@@ , @@a3@@ ) ; tcg_gen_or_i64 ( @@a1@@ , @@a2@@ , @@v5@@ ) ; tcg_temp_free_i64 ( @@v5@@ ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_debug_insn_start\", \"code\": \"unsigned __int64 __fastcall tcg_gen_debug_insn_start ( __int64 @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_op1i ( Number , @@a1@@ ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_exit_tb\", \"code\": \"unsigned __int64 __fastcall tcg_gen_exit_tb ( __int64 @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_op1i ( Number , @@a1@@ ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_qemu_ld8u\", \"code\": \"unsigned __int64 __fastcall tcg_gen_qemu_ld8u ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_op3i_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_qemu_ld8s\", \"code\": \"unsigned __int64 __fastcall tcg_gen_qemu_ld8s ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_op3i_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_qemu_ld16u\", \"code\": \"unsigned __int64 __fastcall tcg_gen_qemu_ld16u ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_op3i_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_qemu_ld16s\", \"code\": \"unsigned __int64 __fastcall tcg_gen_qemu_ld16s ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_op3i_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_qemu_ld32u\", \"code\": \"unsigned __int64 __fastcall tcg_gen_qemu_ld32u ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_op3i_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_qemu_ld32s\", \"code\": \"unsigned __int64 __fastcall tcg_gen_qemu_ld32s ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_op3i_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_qemu_ld64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_qemu_ld64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_qemu_ldst_op_i64_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_qemu_st8\", \"code\": \"unsigned __int64 __fastcall tcg_gen_qemu_st8 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_op3i_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_qemu_st16\", \"code\": \"unsigned __int64 __fastcall tcg_gen_qemu_st16 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_op3i_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_qemu_st32\", \"code\": \"unsigned __int64 __fastcall tcg_gen_qemu_st32 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_op3i_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_qemu_st64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_qemu_st64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_qemu_ldst_op_i64_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_rdccr\", \"code\": \"unsigned __int64 __fastcall gen_helper_rdccr ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_rdccr , Number , Number , @@a1@@ , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_wrccr\", \"code\": \"unsigned __int64 __fastcall gen_helper_wrccr ( int @@a1@@ ) { __int64 @@v2@@ ; unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; @@v2@@ = @@a1@@ ; tcg_gen_helperN ( ( __int64 ) & helper_wrccr , Number , Number , Number , Number , ( __int64 ) & @@v2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_array8\", \"code\": \"unsigned __int64 __fastcall gen_helper_array8 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { __int64 @@v4@@ [ Number ] ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ [ Number ] = @@a2@@ ; @@v4@@ [ Number ] = @@a3@@ ; tcg_gen_helperN ( ( __int64 ) & helper_array8 , Number , Number , @@a1@@ , Number , ( __int64 ) @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_alignaddr\", \"code\": \"unsigned __int64 __fastcall gen_helper_alignaddr ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { __int64 @@v4@@ [ Number ] ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ [ Number ] = @@a2@@ ; @@v4@@ [ Number ] = @@a3@@ ; tcg_gen_helperN ( ( __int64 ) & helper_alignaddr , Number , Number , @@a1@@ , Number , ( __int64 ) @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_popc\", \"code\": \"unsigned __int64 __fastcall gen_helper_popc ( int @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ = @@a2@@ ; tcg_gen_helperN ( ( __int64 ) & helper_popc , Number , Number , @@a1@@ , Number , ( __int64 ) & @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_tick_set_count\", \"code\": \"unsigned __int64 __fastcall gen_helper_tick_set_count ( int @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = @@a1@@ ; @@v3@@ [ Number ] = @@a2@@ ; tcg_gen_helperN ( ( __int64 ) & helper_tick_set_count , Number , Number , Number , Number , ( __int64 ) @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_tick_get_count\", \"code\": \"unsigned __int64 __fastcall gen_helper_tick_get_count ( int @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ = @@a2@@ ; tcg_gen_helperN ( ( __int64 ) & helper_tick_get_count , Number , Number , @@a1@@ , Number , ( __int64 ) & @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_tick_set_limit\", \"code\": \"unsigned __int64 __fastcall gen_helper_tick_set_limit ( int @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = @@a1@@ ; @@v3@@ [ Number ] = @@a2@@ ; tcg_gen_helperN ( ( __int64 ) & helper_tick_set_limit , Number , Number , Number , Number , ( __int64 ) @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_check_align\", \"code\": \"unsigned __int64 __fastcall gen_helper_check_align ( int @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = @@a1@@ ; @@v3@@ [ Number ] = @@a2@@ ; tcg_gen_helperN ( ( __int64 ) & helper_check_align , Number , Number , Number , Number , ( __int64 ) @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_save\", \"code\": \"unsigned __int64 gen_helper_save ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_save , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_restore\", \"code\": \"unsigned __int64 gen_helper_restore ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_restore , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_flush\", \"code\": \"unsigned __int64 __fastcall gen_helper_flush ( int @@a1@@ ) { __int64 @@v2@@ ; unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; @@v2@@ = @@a1@@ ; tcg_gen_helperN ( ( __int64 ) & helper_flush , Number , Number , Number , Number , ( __int64 ) & @@v2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_udiv\", \"code\": \"unsigned __int64 __fastcall gen_helper_udiv ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { __int64 @@v4@@ [ Number ] ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ [ Number ] = @@a2@@ ; @@v4@@ [ Number ] = @@a3@@ ; tcg_gen_helperN ( ( __int64 ) & helper_udiv , Number , Number , @@a1@@ , Number , ( __int64 ) @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_sdiv\", \"code\": \"unsigned __int64 __fastcall gen_helper_sdiv ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { __int64 @@v4@@ [ Number ] ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ [ Number ] = @@a2@@ ; @@v4@@ [ Number ] = @@a3@@ ; tcg_gen_helperN ( ( __int64 ) & helper_sdiv , Number , Number , @@a1@@ , Number , ( __int64 ) @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_stdf\", \"code\": \"unsigned __int64 __fastcall gen_helper_stdf ( int @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = @@a1@@ ; @@v3@@ [ Number ] = @@a2@@ ; tcg_gen_helperN ( ( __int64 ) & helper_stdf , Number , Number , Number , Number , ( __int64 ) @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_lddf\", \"code\": \"unsigned __int64 __fastcall gen_helper_lddf ( int @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = @@a1@@ ; @@v3@@ [ Number ] = @@a2@@ ; tcg_gen_helperN ( ( __int64 ) & helper_lddf , Number , Number , Number , Number , ( __int64 ) @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_ldqf\", \"code\": \"unsigned __int64 __fastcall gen_helper_ldqf ( int @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = @@a1@@ ; @@v3@@ [ Number ] = @@a2@@ ; tcg_gen_helperN ( ( __int64 ) & helper_ldqf , Number , Number , Number , Number , ( __int64 ) @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_stqf\", \"code\": \"unsigned __int64 __fastcall gen_helper_stqf ( int @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = @@a1@@ ; @@v3@@ [ Number ] = @@a2@@ ; tcg_gen_helperN ( ( __int64 ) & helper_stqf , Number , Number , Number , Number , ( __int64 ) @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_ldfsr\", \"code\": \"unsigned __int64 __fastcall gen_helper_ldfsr ( int @@a1@@ ) { __int64 @@v2@@ ; unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; @@v2@@ = @@a1@@ ; tcg_gen_helperN ( ( __int64 ) & helper_ldfsr , Number , Number , Number , Number , ( __int64 ) & @@v2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_check_ieee_exceptions\", \"code\": \"unsigned __int64 gen_helper_check_ieee_exceptions ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_check_ieee_exceptions , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fabss\", \"code\": \"unsigned __int64 __fastcall gen_helper_fabss ( int @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ = @@a2@@ ; tcg_gen_helperN ( ( __int64 ) & helper_fabss , Number , Number , @@a1@@ , Number , ( __int64 ) & @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fsqrts\", \"code\": \"unsigned __int64 __fastcall gen_helper_fsqrts ( int @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ = @@a2@@ ; tcg_gen_helperN ( ( __int64 ) & helper_fsqrts , Number , Number , @@a1@@ , Number , ( __int64 ) & @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fsqrtd\", \"code\": \"unsigned __int64 gen_helper_fsqrtd ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fsqrtd , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fsqrtq\", \"code\": \"unsigned __int64 gen_helper_fsqrtq ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fsqrtq , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fcmpeq\", \"code\": \"unsigned __int64 gen_helper_fcmpeq ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fcmpeq , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_ldxfsr\", \"code\": \"unsigned __int64 __fastcall gen_helper_ldxfsr ( int @@a1@@ ) { __int64 @@v2@@ ; unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; @@v2@@ = @@a1@@ ; tcg_gen_helperN ( ( __int64 ) & helper_ldxfsr , Number , Number , Number , Number , ( __int64 ) & @@v2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fabsd\", \"code\": \"unsigned __int64 gen_helper_fabsd ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fabsd , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fabsq\", \"code\": \"unsigned __int64 gen_helper_fabsq ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fabsq , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_raise_exception\", \"code\": \"unsigned __int64 __fastcall gen_helper_raise_exception ( int @@a1@@ ) { __int64 @@v2@@ ; unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; @@v2@@ = @@a1@@ ; tcg_gen_helperN ( ( __int64 ) & helper_raise_exception , Number , Number , Number , Number , ( __int64 ) & @@v2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_faddd\", \"code\": \"unsigned __int64 gen_helper_faddd ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_faddd , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_faddq\", \"code\": \"unsigned __int64 gen_helper_faddq ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_faddq , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fsubd\", \"code\": \"unsigned __int64 gen_helper_fsubd ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fsubd , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fsubq\", \"code\": \"unsigned __int64 gen_helper_fsubq ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fsubq , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fmuld\", \"code\": \"unsigned __int64 gen_helper_fmuld ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fmuld , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fmulq\", \"code\": \"unsigned __int64 gen_helper_fmulq ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fmulq , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fdivd\", \"code\": \"unsigned __int64 gen_helper_fdivd ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fdivd , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fdivq\", \"code\": \"unsigned __int64 gen_helper_fdivq ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fdivq , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fadds\", \"code\": \"unsigned __int64 __fastcall gen_helper_fadds ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { __int64 @@v4@@ [ Number ] ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ [ Number ] = @@a2@@ ; @@v4@@ [ Number ] = @@a3@@ ; tcg_gen_helperN ( ( __int64 ) & helper_fadds , Number , Number , @@a1@@ , Number , ( __int64 ) @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fsubs\", \"code\": \"unsigned __int64 __fastcall gen_helper_fsubs ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { __int64 @@v4@@ [ Number ] ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ [ Number ] = @@a2@@ ; @@v4@@ [ Number ] = @@a3@@ ; tcg_gen_helperN ( ( __int64 ) & helper_fsubs , Number , Number , @@a1@@ , Number , ( __int64 ) @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fmuls\", \"code\": \"unsigned __int64 __fastcall gen_helper_fmuls ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { __int64 @@v4@@ [ Number ] ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ [ Number ] = @@a2@@ ; @@v4@@ [ Number ] = @@a3@@ ; tcg_gen_helperN ( ( __int64 ) & helper_fmuls , Number , Number , @@a1@@ , Number , ( __int64 ) @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fdivs\", \"code\": \"unsigned __int64 __fastcall gen_helper_fdivs ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { __int64 @@v4@@ [ Number ] ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ [ Number ] = @@a2@@ ; @@v4@@ [ Number ] = @@a3@@ ; tcg_gen_helperN ( ( __int64 ) & helper_fdivs , Number , Number , @@a1@@ , Number , ( __int64 ) @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fsmuld\", \"code\": \"unsigned __int64 __fastcall gen_helper_fsmuld ( int @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = @@a1@@ ; @@v3@@ [ Number ] = @@a2@@ ; tcg_gen_helperN ( ( __int64 ) & helper_fsmuld , Number , Number , Number , Number , ( __int64 ) @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fdmulq\", \"code\": \"unsigned __int64 gen_helper_fdmulq ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fdmulq , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fnegs\", \"code\": \"unsigned __int64 __fastcall gen_helper_fnegs ( int @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ = @@a2@@ ; tcg_gen_helperN ( ( __int64 ) & helper_fnegs , Number , Number , @@a1@@ , Number , ( __int64 ) & @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fitod\", \"code\": \"unsigned __int64 __fastcall gen_helper_fitod ( int @@a1@@ ) { __int64 @@v2@@ ; unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; @@v2@@ = @@a1@@ ; tcg_gen_helperN ( ( __int64 ) & helper_fitod , Number , Number , Number , Number , ( __int64 ) & @@v2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fitoq\", \"code\": \"unsigned __int64 __fastcall gen_helper_fitoq ( int @@a1@@ ) { __int64 @@v2@@ ; unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; @@v2@@ = @@a1@@ ; tcg_gen_helperN ( ( __int64 ) & helper_fitoq , Number , Number , Number , Number , ( __int64 ) & @@v2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fitos\", \"code\": \"unsigned __int64 __fastcall gen_helper_fitos ( int @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ = @@a2@@ ; tcg_gen_helperN ( ( __int64 ) & helper_fitos , Number , Number , @@a1@@ , Number , ( __int64 ) & @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fnegd\", \"code\": \"unsigned __int64 gen_helper_fnegd ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fnegd , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fnegq\", \"code\": \"unsigned __int64 gen_helper_fnegq ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fnegq , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fxtos\", \"code\": \"unsigned __int64 __fastcall gen_helper_fxtos ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fxtos , Number , Number , @@a1@@ , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fxtod\", \"code\": \"unsigned __int64 gen_helper_fxtod ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fxtod , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fxtoq\", \"code\": \"unsigned __int64 gen_helper_fxtoq ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fxtoq , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fdtos\", \"code\": \"unsigned __int64 __fastcall gen_helper_fdtos ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fdtos , Number , Number , @@a1@@ , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fstod\", \"code\": \"unsigned __int64 __fastcall gen_helper_fstod ( int @@a1@@ ) { __int64 @@v2@@ ; unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; @@v2@@ = @@a1@@ ; tcg_gen_helperN ( ( __int64 ) & helper_fstod , Number , Number , Number , Number , ( __int64 ) & @@v2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fqtos\", \"code\": \"unsigned __int64 __fastcall gen_helper_fqtos ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fqtos , Number , Number , @@a1@@ , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fstoq\", \"code\": \"unsigned __int64 __fastcall gen_helper_fstoq ( int @@a1@@ ) { __int64 @@v2@@ ; unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; @@v2@@ = @@a1@@ ; tcg_gen_helperN ( ( __int64 ) & helper_fstoq , Number , Number , Number , Number , ( __int64 ) & @@v2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fqtod\", \"code\": \"unsigned __int64 gen_helper_fqtod ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fqtod , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fdtoq\", \"code\": \"unsigned __int64 gen_helper_fdtoq ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fdtoq , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fstoi\", \"code\": \"unsigned __int64 __fastcall gen_helper_fstoi ( int @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ = @@a2@@ ; tcg_gen_helperN ( ( __int64 ) & helper_fstoi , Number , Number , @@a1@@ , Number , ( __int64 ) & @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fdtoi\", \"code\": \"unsigned __int64 __fastcall gen_helper_fdtoi ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fdtoi , Number , Number , @@a1@@ , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fqtoi\", \"code\": \"unsigned __int64 __fastcall gen_helper_fqtoi ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fqtoi , Number , Number , @@a1@@ , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fstox\", \"code\": \"unsigned __int64 __fastcall gen_helper_fstox ( int @@a1@@ ) { __int64 @@v2@@ ; unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; @@v2@@ = @@a1@@ ; tcg_gen_helperN ( ( __int64 ) & helper_fstox , Number , Number , Number , Number , ( __int64 ) & @@v2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fdtox\", \"code\": \"unsigned __int64 gen_helper_fdtox ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fdtox , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fqtox\", \"code\": \"unsigned __int64 gen_helper_fqtox ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fqtox , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_faligndata\", \"code\": \"unsigned __int64 gen_helper_faligndata ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_faligndata , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fpmerge\", \"code\": \"unsigned __int64 gen_helper_fpmerge ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fpmerge , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fmul8x16\", \"code\": \"unsigned __int64 gen_helper_fmul8x16 ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fmul8x16 , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fmul8x16al\", \"code\": \"unsigned __int64 gen_helper_fmul8x16al ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fmul8x16al , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fmul8x16au\", \"code\": \"unsigned __int64 gen_helper_fmul8x16au ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fmul8x16au , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fmul8sux16\", \"code\": \"unsigned __int64 gen_helper_fmul8sux16 ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fmul8sux16 , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fmul8ulx16\", \"code\": \"unsigned __int64 gen_helper_fmul8ulx16 ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fmul8ulx16 , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fmuld8sux16\", \"code\": \"unsigned __int64 gen_helper_fmuld8sux16 ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fmuld8sux16 , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fmuld8ulx16\", \"code\": \"unsigned __int64 gen_helper_fmuld8ulx16 ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fmuld8ulx16 , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fexpand\", \"code\": \"unsigned __int64 gen_helper_fexpand ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fexpand , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fpadd16\", \"code\": \"unsigned __int64 gen_helper_fpadd16 ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fpadd16 , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fpadd16s\", \"code\": \"unsigned __int64 __fastcall gen_helper_fpadd16s ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { __int64 @@v4@@ [ Number ] ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ [ Number ] = @@a2@@ ; @@v4@@ [ Number ] = @@a3@@ ; tcg_gen_helperN ( ( __int64 ) & helper_fpadd16s , Number , Number , @@a1@@ , Number , ( __int64 ) @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fpadd32\", \"code\": \"unsigned __int64 gen_helper_fpadd32 ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fpadd32 , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fpadd32s\", \"code\": \"unsigned __int64 __fastcall gen_helper_fpadd32s ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { __int64 @@v4@@ [ Number ] ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ [ Number ] = @@a2@@ ; @@v4@@ [ Number ] = @@a3@@ ; tcg_gen_helperN ( ( __int64 ) & helper_fpadd32s , Number , Number , @@a1@@ , Number , ( __int64 ) @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fpsub16\", \"code\": \"unsigned __int64 gen_helper_fpsub16 ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fpsub16 , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fpsub16s\", \"code\": \"unsigned __int64 __fastcall gen_helper_fpsub16s ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { __int64 @@v4@@ [ Number ] ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ [ Number ] = @@a2@@ ; @@v4@@ [ Number ] = @@a3@@ ; tcg_gen_helperN ( ( __int64 ) & helper_fpsub16s , Number , Number , @@a1@@ , Number , ( __int64 ) @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fpsub32\", \"code\": \"unsigned __int64 gen_helper_fpsub32 ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fpsub32 , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fpsub32s\", \"code\": \"unsigned __int64 __fastcall gen_helper_fpsub32s ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { __int64 @@v4@@ [ Number ] ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ [ Number ] = @@a2@@ ; @@v4@@ [ Number ] = @@a3@@ ; tcg_gen_helperN ( ( __int64 ) & helper_fpsub32s , Number , Number , @@a1@@ , Number , ( __int64 ) @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fcmpgt16\", \"code\": \"unsigned __int64 gen_helper_fcmpgt16 ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fcmpgt16 , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fcmpgt32\", \"code\": \"unsigned __int64 gen_helper_fcmpgt32 ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fcmpgt32 , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fcmpeq16\", \"code\": \"unsigned __int64 gen_helper_fcmpeq16 ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fcmpeq16 , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fcmpeq32\", \"code\": \"unsigned __int64 gen_helper_fcmpeq32 ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fcmpeq32 , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fcmple16\", \"code\": \"unsigned __int64 gen_helper_fcmple16 ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fcmple16 , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fcmple32\", \"code\": \"unsigned __int64 gen_helper_fcmple32 ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fcmple32 , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fcmpne16\", \"code\": \"unsigned __int64 gen_helper_fcmpne16 ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fcmpne16 , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_fcmpne32\", \"code\": \"unsigned __int64 gen_helper_fcmpne32 ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_fcmpne32 , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_compute_psr\", \"code\": \"unsigned __int64 gen_helper_compute_psr ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_compute_psr , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"sign_extend\", \"code\": \"__int64 __fastcall sign_extend ( int @@a1@@ , char @@a2@@ ) { return ( unsigned int ) ( @@a1@@ << ( Number - @@a2@@ ) >> ( Number - @@a2@@ ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_op_load_fpr_DT0\", \"code\": \"unsigned __int64 __fastcall gen_op_load_fpr_DT0 ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_st_i32 ( cpu_fpr [ @@a1@@ ] , cpu_env , Number L ) ; tcg_gen_st_i32 ( cpu_fpr [ @@a1@@ + Number ] , cpu_env , Number L ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_load_fpr_DT1\", \"code\": \"unsigned __int64 __fastcall gen_op_load_fpr_DT1 ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_st_i32 ( cpu_fpr [ @@a1@@ ] , cpu_env , Number L ) ; tcg_gen_st_i32 ( cpu_fpr [ @@a1@@ + Number ] , cpu_env , Number L ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_store_DT0_fpr\", \"code\": \"unsigned __int64 __fastcall gen_op_store_DT0_fpr ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_ld_i32 ( cpu_fpr [ @@a1@@ ] , cpu_env , Number L ) ; tcg_gen_ld_i32 ( cpu_fpr [ @@a1@@ + Number ] , cpu_env , Number L ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_load_fpr_QT0\", \"code\": \"unsigned __int64 __fastcall gen_op_load_fpr_QT0 ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_st_i32 ( cpu_fpr [ @@a1@@ ] , cpu_env , Number L ) ; tcg_gen_st_i32 ( cpu_fpr [ @@a1@@ + Number ] , cpu_env , Number L ) ; tcg_gen_st_i32 ( cpu_fpr [ @@a1@@ + Number ] , cpu_env , Number L ) ; tcg_gen_st_i32 ( cpu_fpr [ @@a1@@ + Number ] , cpu_env , Number L ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_load_fpr_QT1\", \"code\": \"unsigned __int64 __fastcall gen_op_load_fpr_QT1 ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_st_i32 ( cpu_fpr [ @@a1@@ ] , cpu_env , Number L ) ; tcg_gen_st_i32 ( cpu_fpr [ @@a1@@ + Number ] , cpu_env , Number L ) ; tcg_gen_st_i32 ( cpu_fpr [ @@a1@@ + Number ] , cpu_env , Number L ) ; tcg_gen_st_i32 ( cpu_fpr [ @@a1@@ + Number ] , cpu_env , Number L ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_store_QT0_fpr\", \"code\": \"unsigned __int64 __fastcall gen_op_store_QT0_fpr ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_ld_i32 ( cpu_fpr [ @@a1@@ ] , cpu_env , Number L ) ; tcg_gen_ld_i32 ( cpu_fpr [ @@a1@@ + Number ] , cpu_env , Number L ) ; tcg_gen_ld_i32 ( cpu_fpr [ @@a1@@ + Number ] , cpu_env , Number L ) ; tcg_gen_ld_i32 ( cpu_fpr [ @@a1@@ + Number ] , cpu_env , Number L ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_address_mask\", \"code\": \"unsigned __int64 __fastcall gen_address_mask ( __int64 @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) tcg_gen_andi_i64 ( @@a2@@ , @@a2@@ , Number ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_movl_reg_TN\", \"code\": \"unsigned __int64 __fastcall gen_movl_reg_TN ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; if ( @@a1@@ ) { if ( @@a1@@ > Number ) tcg_gen_ld_i64 ( @@a2@@ , cpu_regwptr , Number L * ( @@a1@@ - Number ) ) ; else tcg_gen_mov_i64 ( @@a2@@ , cpu_gregs [ @@a1@@ ] ) ; } else { tcg_gen_movi_i64 ( @@a2@@ , Number L ) ; } return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_movl_TN_reg\", \"code\": \"unsigned __int64 __fastcall gen_movl_TN_reg ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; if ( @@a1@@ ) { if ( @@a1@@ > Number ) tcg_gen_st_i64 ( @@a2@@ , cpu_regwptr , Number L * ( @@a1@@ - Number ) ) ; else tcg_gen_mov_i64 ( cpu_gregs [ @@a1@@ ] , @@a2@@ ) ; } return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_addi_cc\", \"code\": \"unsigned __int64 __fastcall gen_op_addi_cc ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; tcg_gen_mov_i64 ( cpu_cc_src , @@a2@@ ) ; tcg_gen_movi_i64 ( cpu_cc_src2 , @@a3@@ ) ; tcg_gen_addi_i64 ( cpu_cc_dst , cpu_cc_src , @@a3@@ ) ; tcg_gen_mov_i64 ( @@a1@@ , cpu_cc_dst ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_add_cc\", \"code\": \"unsigned __int64 __fastcall gen_op_add_cc ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; tcg_gen_mov_i64 ( cpu_cc_src , @@a2@@ ) ; tcg_gen_mov_i64 ( cpu_cc_src2 , @@a3@@ ) ; tcg_gen_add_i64 ( cpu_cc_dst , cpu_cc_src , cpu_cc_src2 ) ; tcg_gen_mov_i64 ( @@a1@@ , cpu_cc_dst ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_addx_int\", \"code\": \"unsigned __int64 __fastcall gen_op_addx_int ( __int64 @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ , int @@a5@@ ) { unsigned int @@v9@@ ; unsigned int @@v10@@ ; unsigned __int64 @@v11@@ ; @@v11@@ = __readfsqword ( Number ) ; switch ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { case Number : case Number : if ( @@a5@@ ) gen_op_add_cc ( @@a2@@ , @@a3@@ , @@a4@@ ) ; else tcg_gen_add_i64 ( @@a2@@ , @@a3@@ , @@a4@@ ) ; return __readfsqword ( Number ) ^ @@v11@@ ; case Number : case Number : case Number : @@v9@@ = gen_add32_carry32 ( ) ; goto LABEL_8 ; case Number : case Number : case Number : @@v9@@ = gen_sub32_carry32 ( ) ; goto LABEL_8 ; default : @@v9@@ = tcg_temp_new_i32 ( ) ; gen_helper_compute_C_icc ( @@v9@@ ) ; LABEL_8 : @@v10@@ = tcg_temp_new_i64 ( ) ; tcg_gen_extu_i32_i64 ( @@v10@@ , @@v9@@ ) ; tcg_gen_add_i64 ( @@a2@@ , @@a3@@ , @@a4@@ ) ; tcg_gen_add_i64 ( @@a2@@ , @@a2@@ , @@v10@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; tcg_temp_free_i64 ( @@v10@@ ) ; if ( @@a5@@ ) { tcg_gen_mov_i64 ( cpu_cc_src , @@a3@@ ) ; tcg_gen_mov_i64 ( cpu_cc_src2 , @@a4@@ ) ; tcg_gen_mov_i64 ( cpu_cc_dst , @@a2@@ ) ; tcg_gen_movi_i32 ( cpu_cc_op , Number ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } return __readfsqword ( Number ) ^ @@v11@@ ; } }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s16\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_tadd_cc\", \"code\": \"unsigned __int64 __fastcall gen_op_tadd_cc ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; tcg_gen_mov_i64 ( cpu_cc_src , @@a2@@ ) ; tcg_gen_mov_i64 ( cpu_cc_src2 , @@a3@@ ) ; tcg_gen_add_i64 ( cpu_cc_dst , cpu_cc_src , cpu_cc_src2 ) ; tcg_gen_mov_i64 ( @@a1@@ , cpu_cc_dst ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_tadd_ccTV\", \"code\": \"unsigned __int64 __fastcall gen_op_tadd_ccTV ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; tcg_gen_mov_i64 ( cpu_cc_src , @@a2@@ ) ; tcg_gen_mov_i64 ( cpu_cc_src2 , @@a3@@ ) ; gen_tag_tv ( cpu_cc_src , cpu_cc_src2 ) ; tcg_gen_add_i64 ( cpu_cc_dst , cpu_cc_src , cpu_cc_src2 ) ; gen_add_tv ( cpu_cc_dst , cpu_cc_src , cpu_cc_src2 ) ; tcg_gen_mov_i64 ( @@a1@@ , cpu_cc_dst ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_subi_cc\", \"code\": \"unsigned __int64 __fastcall gen_op_subi_cc ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; tcg_gen_mov_i64 ( cpu_cc_src , @@a2@@ ) ; tcg_gen_movi_i64 ( cpu_cc_src2 , @@a3@@ ) ; if ( @@a3@@ ) { tcg_gen_subi_i64 ( cpu_cc_dst , cpu_cc_src , @@a3@@ ) ; tcg_gen_movi_i32 ( cpu_cc_op , Number ) ; * ( _DWORD * ) ( @@a4@@ + Number ) = Number ; } else { tcg_gen_mov_i64 ( cpu_cc_dst , @@a2@@ ) ; tcg_gen_movi_i32 ( cpu_cc_op , Number ) ; * ( _DWORD * ) ( @@a4@@ + Number ) = Number ; } tcg_gen_mov_i64 ( @@a1@@ , cpu_cc_dst ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_sub_cc\", \"code\": \"unsigned __int64 __fastcall gen_op_sub_cc ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; tcg_gen_mov_i64 ( cpu_cc_src , @@a2@@ ) ; tcg_gen_mov_i64 ( cpu_cc_src2 , @@a3@@ ) ; tcg_gen_sub_i64 ( cpu_cc_dst , cpu_cc_src , cpu_cc_src2 ) ; tcg_gen_mov_i64 ( @@a1@@ , cpu_cc_dst ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_subx_int\", \"code\": \"unsigned __int64 __fastcall gen_op_subx_int ( __int64 @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ , int @@a5@@ ) { unsigned int @@v9@@ ; unsigned int @@v10@@ ; unsigned __int64 @@v11@@ ; @@v11@@ = __readfsqword ( Number ) ; switch ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { case Number : case Number : if ( @@a5@@ ) gen_op_sub_cc ( @@a2@@ , @@a3@@ , @@a4@@ ) ; else tcg_gen_sub_i64 ( @@a2@@ , @@a3@@ , @@a4@@ ) ; return __readfsqword ( Number ) ^ @@v11@@ ; case Number : case Number : case Number : @@v9@@ = gen_add32_carry32 ( ) ; goto LABEL_8 ; case Number : case Number : case Number : @@v9@@ = gen_sub32_carry32 ( ) ; goto LABEL_8 ; default : @@v9@@ = tcg_temp_new_i32 ( ) ; gen_helper_compute_C_icc ( @@v9@@ ) ; LABEL_8 : @@v10@@ = tcg_temp_new_i64 ( ) ; tcg_gen_extu_i32_i64 ( @@v10@@ , @@v9@@ ) ; tcg_gen_sub_i64 ( @@a2@@ , @@a3@@ , @@a4@@ ) ; tcg_gen_sub_i64 ( @@a2@@ , @@a2@@ , @@v10@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; tcg_temp_free_i64 ( @@v10@@ ) ; if ( @@a5@@ ) { tcg_gen_mov_i64 ( cpu_cc_src , @@a3@@ ) ; tcg_gen_mov_i64 ( cpu_cc_src2 , @@a4@@ ) ; tcg_gen_mov_i64 ( cpu_cc_dst , @@a2@@ ) ; tcg_gen_movi_i32 ( cpu_cc_op , Number ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } return __readfsqword ( Number ) ^ @@v11@@ ; } }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s16\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_tsub_cc\", \"code\": \"unsigned __int64 __fastcall gen_op_tsub_cc ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; tcg_gen_mov_i64 ( cpu_cc_src , @@a2@@ ) ; tcg_gen_mov_i64 ( cpu_cc_src2 , @@a3@@ ) ; tcg_gen_sub_i64 ( cpu_cc_dst , cpu_cc_src , cpu_cc_src2 ) ; tcg_gen_mov_i64 ( @@a1@@ , cpu_cc_dst ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_tsub_ccTV\", \"code\": \"unsigned __int64 __fastcall gen_op_tsub_ccTV ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; tcg_gen_mov_i64 ( cpu_cc_src , @@a2@@ ) ; tcg_gen_mov_i64 ( cpu_cc_src2 , @@a3@@ ) ; gen_tag_tv ( cpu_cc_src , cpu_cc_src2 ) ; tcg_gen_sub_i64 ( cpu_cc_dst , cpu_cc_src , cpu_cc_src2 ) ; gen_sub_tv ( cpu_cc_dst , cpu_cc_src , cpu_cc_src2 ) ; tcg_gen_mov_i64 ( @@a1@@ , cpu_cc_dst ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_mulscc\", \"code\": \"unsigned __int64 __fastcall gen_op_mulscc ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { int @@v5@@ ; unsigned int @@v6@@ ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v5@@ = gen_new_label ( ) ; @@v6@@ = tcg_temp_new_i64 ( ) ; tcg_gen_andi_i64 ( cpu_cc_src , @@a2@@ , Number ) ; tcg_gen_andi_i64 ( @@v6@@ , cpu_y , Number L ) ; tcg_gen_andi_i64 ( cpu_cc_src2 , @@a3@@ , Number ) ; tcg_gen_brcondi_i64 ( Number , @@v6@@ , Number L , @@v5@@ ) ; tcg_gen_movi_i64 ( cpu_cc_src2 , Number L ) ; gen_set_label ( @@v5@@ ) ; tcg_gen_andi_i64 ( @@v6@@ , cpu_cc_src , Number L ) ; tcg_gen_shli_i64 ( @@v6@@ , @@v6@@ , Number L ) ; tcg_gen_shri_i64 ( cpu_tmp0 , cpu_y , Number L ) ; tcg_gen_andi_i64 ( cpu_tmp0 , cpu_tmp0 , Number ) ; tcg_gen_or_i64 ( cpu_tmp0 , cpu_tmp0 , @@v6@@ ) ; tcg_gen_andi_i64 ( cpu_y , cpu_tmp0 , Number ) ; gen_mov_reg_N ( cpu_tmp0 , cpu_psr ) ; gen_mov_reg_V ( @@v6@@ , cpu_psr ) ; tcg_gen_xor_i64 ( cpu_tmp0 , cpu_tmp0 , @@v6@@ ) ; tcg_temp_free_i64 ( @@v6@@ ) ; tcg_gen_shli_i64 ( cpu_tmp0 , cpu_tmp0 , Number L ) ; tcg_gen_shri_i64 ( cpu_cc_src , cpu_cc_src , Number L ) ; tcg_gen_or_i64 ( cpu_cc_src , cpu_cc_src , cpu_tmp0 ) ; tcg_gen_add_i64 ( cpu_cc_dst , cpu_cc_src , cpu_cc_src2 ) ; tcg_gen_mov_i64 ( @@a1@@ , cpu_cc_dst ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_umul\", \"code\": \"unsigned __int64 __fastcall gen_op_umul ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; gen_op_multiply ( @@a1@@ , @@a2@@ , @@a3@@ , Number ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_smul\", \"code\": \"unsigned __int64 __fastcall gen_op_smul ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; gen_op_multiply ( @@a1@@ , @@a2@@ , @@a3@@ , Number ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_trap_ifdivzero_tl\", \"code\": \"unsigned __int64 __fastcall gen_trap_ifdivzero_tl ( int @@a1@@ ) { int @@v2@@ ; unsigned int @@v3@@ ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v2@@ = gen_new_label ( ) ; tcg_gen_brcondi_i64 ( Number , @@a1@@ , Number L , @@v2@@ ) ; @@v3@@ = tcg_const_i32 ( Number L ) ; gen_helper_raise_exception ( @@v3@@ ) ; tcg_temp_free_i32 ( @@v3@@ ) ; gen_set_label ( @@v2@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s16\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_sdivx\", \"code\": \"unsigned __int64 __fastcall gen_op_sdivx ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { int @@v5@@ ; int @@v6@@ ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v5@@ = gen_new_label ( ) ; @@v6@@ = gen_new_label ( ) ; tcg_gen_mov_i64 ( cpu_cc_src , @@a2@@ ) ; tcg_gen_mov_i64 ( cpu_cc_src2 , @@a3@@ ) ; gen_trap_ifdivzero_tl ( cpu_cc_src2 ) ; tcg_gen_brcondi_i64 ( Number , cpu_cc_src , Number , @@v5@@ ) ; tcg_gen_brcondi_i64 ( Number , cpu_cc_src2 , Number , @@v5@@ ) ; tcg_gen_movi_i64 ( @@a1@@ , Number ) ; tcg_gen_br ( @@v6@@ ) ; gen_set_label ( @@v5@@ ) ; tcg_gen_div_i64 ( @@a1@@ , cpu_cc_src , cpu_cc_src2 ) ; gen_set_label ( @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_branch2\", \"code\": \"unsigned __int64 __fastcall gen_branch2 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { int @@v7@@ ; unsigned __int64 @@v8@@ ; @@v8@@ = __readfsqword ( Number ) ; @@v7@@ = gen_new_label ( ) ; tcg_gen_brcondi_i64 ( Number , @@a4@@ , Number L , @@v7@@ ) ; gen_goto_tb ( @@a1@@ , Number , @@a2@@ , @@a2@@ + Number ) ; gen_set_label ( @@v7@@ ) ; gen_goto_tb ( @@a1@@ , Number , @@a3@@ , @@a3@@ + Number ) ; return __readfsqword ( Number ) ^ @@v8@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"save_state\", \"code\": \"unsigned __int64 __fastcall save_state ( __int64 @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; tcg_gen_movi_i64 ( cpu_pc , * ( _QWORD * ) @@a1@@ ) ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) != Number ) { * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; gen_helper_compute_psr ( ) ; } save_npc ( ( __int64 * ) @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mov_pc_npc\", \"code\": \"unsigned __int64 __fastcall gen_mov_pc_npc ( _QWORD * @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; if ( @@a1@@ [ Number ] == Number L ) { gen_generic_branch ( @@a1@@ [ Number ] , @@a1@@ [ Number ] , @@a2@@ ) ; tcg_gen_mov_i64 ( cpu_pc , cpu_npc ) ; * @@a1@@ = Number L ; } else if ( @@a1@@ [ Number ] == Number L ) { tcg_gen_mov_i64 ( cpu_pc , cpu_npc ) ; * @@a1@@ = Number L ; } else { * @@a1@@ = @@a1@@ [ Number ] ; } return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 3, \"t\": \"_QWORD\"}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_next_insn\", \"code\": \"unsigned __int64 gen_op_next_insn ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_mov_i64 ( cpu_pc , cpu_npc ) ; tcg_gen_addi_i64 ( cpu_npc , cpu_npc , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_cond\", \"code\": \"unsigned __int64 __fastcall gen_cond ( int @@a1@@ , int @@a2@@ , int @@a3@@ , __int64 @@a4@@ ) { int @@v7@@ ; unsigned __int64 @@v8@@ ; @@v8@@ = __readfsqword ( Number ) ; if ( @@a2@@ ) @@v7@@ = cpu_xcc ; else @@v7@@ = cpu_psr ; if ( * ( _DWORD * ) ( @@a4@@ + Number ) != Number ) { gen_helper_compute_psr ( ) ; * ( _DWORD * ) ( @@a4@@ + Number ) = Number ; } switch ( @@a3@@ ) { case Number : gen_op_eval_bn ( @@a1@@ ) ; break ; case Number : gen_op_eval_be ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_ble ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bl ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bleu ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bcs ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bneg ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bvs ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_ba ( @@a1@@ ) ; break ; case Number : gen_op_eval_bne ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bg ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bge ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bgu ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bcc ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bpos ( @@a1@@ , @@v7@@ ) ; break ; case Number : gen_op_eval_bvc ( @@a1@@ , @@v7@@ ) ; break ; default : return __readfsqword ( Number ) ^ @@v8@@ ; } return __readfsqword ( Number ) ^ @@v8@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_fcond\", \"code\": \"unsigned __int64 __fastcall gen_fcond ( int @@a1@@ , unsigned int @@a2@@ , int @@a3@@ ) { int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; if ( @@a2@@ == Number ) { @@v4@@ = Number ; } else { if ( @@a2@@ > Number ) { LABEL_5 : @@v4@@ = Number ; goto LABEL_9 ; } if ( @@a2@@ == Number ) { @@v4@@ = Number ; } else { if ( @@a2@@ != Number ) goto LABEL_5 ; @@v4@@ = Number ; } } LABEL_9 : switch ( @@a3@@ ) { case Number : gen_op_eval_bn ( @@a1@@ ) ; break ; case Number : gen_op_eval_fbne ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fblg ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fbul ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fbl ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fbug ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fbg ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fbu ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_ba ( @@a1@@ ) ; break ; case Number : gen_op_eval_fbe ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fbue ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fbge ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fbuge ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fble ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fbule ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; case Number : gen_op_eval_fbo ( @@a1@@ , cpu_fsr , @@v4@@ ) ; break ; default : return __readfsqword ( Number ) ^ @@v5@@ ; } return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"do_branch\", \"code\": \"unsigned __int64 __fastcall do_branch ( __int64 @@a1@@ , int @@a2@@ , unsigned int @@a3@@ , int @@a4@@ , int @@a5@@ ) { int @@v8@@ ; int @@v9@@ ; __int64 @@v10@@ ; unsigned __int64 @@v11@@ ; @@v11@@ = __readfsqword ( Number ) ; @@v8@@ = ( @@a3@@ >> Number ) & Number ; @@v9@@ = @@a3@@ & Number ; @@v10@@ = * ( _QWORD * ) @@a1@@ + @@a2@@ ; if ( @@v8@@ ) { if ( @@v8@@ == Number ) { if ( @@v9@@ ) { * ( _QWORD * ) @@a1@@ = @@v10@@ ; * ( _QWORD * ) ( @@a1@@ + Number ) = * ( _QWORD * ) @@a1@@ + Number L ; } else { * ( _QWORD * ) @@a1@@ = * ( _QWORD * ) ( @@a1@@ + Number ) ; * ( _QWORD * ) ( @@a1@@ + Number ) = @@v10@@ ; tcg_gen_mov_i64 ( cpu_pc , cpu_npc ) ; } } else { flush_cond ( ( _QWORD * ) @@a1@@ , @@a5@@ ) ; gen_cond ( @@a5@@ , @@a4@@ , @@v8@@ , @@a1@@ ) ; if ( @@v9@@ ) { gen_branch_a ( @@a1@@ , @@v10@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , @@a5@@ ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } else { * ( _QWORD * ) @@a1@@ = * ( _QWORD * ) ( @@a1@@ + Number ) ; * ( _QWORD * ) ( @@a1@@ + Number ) = @@v10@@ ; * ( _QWORD * ) ( @@a1@@ + Number ) = * ( _QWORD * ) ( @@a1@@ + Number ) + Number L ; * ( _QWORD * ) ( @@a1@@ + Number ) = Number L ; } } } else { if ( @@v9@@ ) * ( _QWORD * ) @@a1@@ = * ( _QWORD * ) ( @@a1@@ + Number ) + Number L ; else * ( _QWORD * ) @@a1@@ = * ( _QWORD * ) ( @@a1@@ + Number ) ; * ( _QWORD * ) ( @@a1@@ + Number ) = * ( _QWORD * ) @@a1@@ + Number L ; } return __readfsqword ( Number ) ^ @@v11@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s20\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s24\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"do_fbranch\", \"code\": \"unsigned __int64 __fastcall do_fbranch ( __int64 @@a1@@ , int @@a2@@ , unsigned int @@a3@@ , unsigned int @@a4@@ , int @@a5@@ ) { int @@v8@@ ; int @@v9@@ ; __int64 @@v10@@ ; unsigned __int64 @@v11@@ ; @@v11@@ = __readfsqword ( Number ) ; @@v8@@ = ( @@a3@@ >> Number ) & Number ; @@v9@@ = @@a3@@ & Number ; @@v10@@ = * ( _QWORD * ) @@a1@@ + @@a2@@ ; if ( @@v8@@ ) { if ( @@v8@@ == Number ) { if ( @@v9@@ ) { * ( _QWORD * ) @@a1@@ = @@v10@@ ; * ( _QWORD * ) ( @@a1@@ + Number ) = * ( _QWORD * ) @@a1@@ + Number L ; } else { * ( _QWORD * ) @@a1@@ = * ( _QWORD * ) ( @@a1@@ + Number ) ; * ( _QWORD * ) ( @@a1@@ + Number ) = @@v10@@ ; tcg_gen_mov_i64 ( cpu_pc , cpu_npc ) ; } } else { flush_cond ( ( _QWORD * ) @@a1@@ , @@a5@@ ) ; gen_fcond ( @@a5@@ , @@a4@@ , @@v8@@ ) ; if ( @@v9@@ ) { gen_branch_a ( @@a1@@ , @@v10@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , @@a5@@ ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } else { * ( _QWORD * ) @@a1@@ = * ( _QWORD * ) ( @@a1@@ + Number ) ; * ( _QWORD * ) ( @@a1@@ + Number ) = @@v10@@ ; * ( _QWORD * ) ( @@a1@@ + Number ) = * ( _QWORD * ) ( @@a1@@ + Number ) + Number L ; * ( _QWORD * ) ( @@a1@@ + Number ) = Number L ; } } } else { if ( @@v9@@ ) * ( _QWORD * ) @@a1@@ = * ( _QWORD * ) ( @@a1@@ + Number ) + Number L ; else * ( _QWORD * ) @@a1@@ = * ( _QWORD * ) ( @@a1@@ + Number ) ; * ( _QWORD * ) ( @@a1@@ + Number ) = * ( _QWORD * ) @@a1@@ + Number L ; } return __readfsqword ( Number ) ^ @@v11@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s20\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s24\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"do_branch_reg\", \"code\": \"unsigned __int64 __fastcall do_branch_reg ( __int64 @@a1@@ , int @@a2@@ , unsigned int @@a3@@ , int @@a4@@ , int @@a5@@ ) { int @@v8@@ ; int @@v9@@ ; __int64 @@v10@@ ; unsigned __int64 @@v11@@ ; @@v11@@ = __readfsqword ( Number ) ; @@v8@@ = ( @@a3@@ >> Number ) & Number ; @@v9@@ = @@a3@@ & Number ; @@v10@@ = * ( _QWORD * ) @@a1@@ + @@a2@@ ; flush_cond ( ( _QWORD * ) @@a1@@ , @@a4@@ ) ; gen_cond_reg ( @@a4@@ , @@v8@@ , @@a5@@ ) ; if ( @@v9@@ ) { gen_branch_a ( @@a1@@ , @@v10@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , @@a4@@ ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } else { * ( _QWORD * ) @@a1@@ = * ( _QWORD * ) ( @@a1@@ + Number ) ; * ( _QWORD * ) ( @@a1@@ + Number ) = @@v10@@ ; * ( _QWORD * ) ( @@a1@@ + Number ) = * ( _QWORD * ) ( @@a1@@ + Number ) + Number L ; * ( _QWORD * ) ( @@a1@@ + Number ) = Number L ; } return __readfsqword ( Number ) ^ @@v11@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s20\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s24\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_fcmps\", \"code\": \"unsigned __int64 __fastcall gen_op_fcmps ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; if ( @@a1@@ == Number ) { gen_helper_fcmps_fcc3 ( @@a2@@ , @@a3@@ ) ; } else if ( @@a1@@ <= Number ) { if ( @@a1@@ == Number ) { gen_helper_fcmps_fcc2 ( @@a2@@ , @@a3@@ ) ; } else if ( @@a1@@ ) { if ( @@a1@@ == Number ) gen_helper_fcmps_fcc1 ( @@a2@@ , @@a3@@ ) ; } else { gen_helper_fcmps ( @@a2@@ , @@a3@@ ) ; } } return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_fcmpd\", \"code\": \"unsigned __int64 __fastcall gen_op_fcmpd ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; if ( @@a1@@ == Number ) { gen_helper_fcmpd_fcc3 ( ) ; } else if ( @@a1@@ <= Number ) { if ( @@a1@@ == Number ) { gen_helper_fcmpd_fcc2 ( ) ; } else if ( @@a1@@ ) { if ( @@a1@@ == Number ) gen_helper_fcmpd_fcc1 ( ) ; } else { gen_helper_fcmpd ( ) ; } } return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_fcmpq\", \"code\": \"unsigned __int64 __fastcall gen_op_fcmpq ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; if ( @@a1@@ == Number ) { gen_helper_fcmpq_fcc3 ( ) ; } else if ( @@a1@@ <= Number ) { if ( @@a1@@ == Number ) { gen_helper_fcmpq_fcc2 ( ) ; } else if ( @@a1@@ ) { if ( @@a1@@ == Number ) gen_helper_fcmpq_fcc1 ( ) ; } else { gen_helper_fcmpq ( ) ; } } return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_fcmpes\", \"code\": \"unsigned __int64 __fastcall gen_op_fcmpes ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; if ( @@a1@@ == Number ) { gen_helper_fcmpes_fcc3 ( @@a2@@ , @@a3@@ ) ; } else if ( @@a1@@ <= Number ) { if ( @@a1@@ == Number ) { gen_helper_fcmpes_fcc2 ( @@a2@@ , @@a3@@ ) ; } else if ( @@a1@@ ) { if ( @@a1@@ == Number ) gen_helper_fcmpes_fcc1 ( @@a2@@ , @@a3@@ ) ; } else { gen_helper_fcmpes ( @@a2@@ , @@a3@@ ) ; } } return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_fcmped\", \"code\": \"unsigned __int64 __fastcall gen_op_fcmped ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; if ( @@a1@@ == Number ) { gen_helper_fcmped_fcc3 ( ) ; } else if ( @@a1@@ <= Number ) { if ( @@a1@@ == Number ) { gen_helper_fcmped_fcc2 ( ) ; } else if ( @@a1@@ ) { if ( @@a1@@ == Number ) gen_helper_fcmped_fcc1 ( ) ; } else { gen_helper_fcmped ( ) ; } } return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_fcmpeq\", \"code\": \"unsigned __int64 __fastcall gen_op_fcmpeq ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; if ( @@a1@@ == Number ) { gen_helper_fcmpeq_fcc3 ( ) ; } else if ( @@a1@@ <= Number ) { if ( @@a1@@ == Number ) { gen_helper_fcmpeq_fcc2 ( ) ; } else if ( @@a1@@ ) { if ( @@a1@@ == Number ) gen_helper_fcmpeq_fcc1 ( ) ; } else { gen_helper_fcmpeq ( ) ; } } return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_fpexception_im\", \"code\": \"unsigned __int64 __fastcall gen_op_fpexception_im ( int @@a1@@ ) { unsigned int @@v2@@ ; unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; tcg_gen_andi_i64 ( cpu_fsr , cpu_fsr , Number ) ; tcg_gen_ori_i64 ( cpu_fsr , cpu_fsr , @@a1@@ ) ; @@v2@@ = tcg_const_i32 ( Number L ) ; gen_helper_raise_exception ( @@v2@@ ) ; tcg_temp_free_i32 ( @@v2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_clear_ieee_excp_and_FTT\", \"code\": \"unsigned __int64 gen_op_clear_ieee_excp_and_FTT ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_andi_i64 ( cpu_fsr , cpu_fsr , Number ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_clear_float_exceptions\", \"code\": \"unsigned __int64 gen_clear_float_exceptions ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; gen_helper_clear_float_exceptions ( ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_ld_asi\", \"code\": \"unsigned __int64 __fastcall gen_ld_asi ( int @@a1@@ , int @@a2@@ , int @@a3@@ , unsigned int @@a4@@ , unsigned int @@a5@@ ) { unsigned int @@v8@@ ; unsigned int @@v9@@ ; unsigned int @@v10@@ ; unsigned __int64 @@v11@@ ; @@v11@@ = __readfsqword ( Number ) ; @@v8@@ = gen_get_asi ( @@a3@@ ) ; @@v9@@ = tcg_const_i32 ( @@a4@@ ) ; @@v10@@ = tcg_const_i32 ( @@a5@@ ) ; gen_helper_ld_asi ( @@a1@@ , @@a2@@ , @@v8@@ , @@v9@@ , @@v10@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v11@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s20\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_st_asi\", \"code\": \"unsigned __int64 __fastcall gen_st_asi ( int @@a1@@ , int @@a2@@ , int @@a3@@ , unsigned int @@a4@@ ) { unsigned int @@v6@@ ; unsigned int @@v7@@ ; unsigned __int64 @@v8@@ ; @@v8@@ = __readfsqword ( Number ) ; @@v6@@ = gen_get_asi ( @@a3@@ ) ; @@v7@@ = tcg_const_i32 ( @@a4@@ ) ; gen_helper_st_asi ( @@a2@@ , @@a1@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v8@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_ldf_asi\", \"code\": \"unsigned __int64 __fastcall gen_ldf_asi ( int @@a1@@ , int @@a2@@ , unsigned int @@a3@@ , unsigned int @@a4@@ ) { unsigned int @@v7@@ ; unsigned int @@v8@@ ; unsigned int @@v9@@ ; unsigned __int64 @@v10@@ ; @@v10@@ = __readfsqword ( Number ) ; @@v7@@ = gen_get_asi ( @@a2@@ ) ; @@v8@@ = tcg_const_i32 ( @@a3@@ ) ; @@v9@@ = tcg_const_i32 ( @@a4@@ ) ; gen_helper_ldf_asi ( @@a1@@ , @@v7@@ , @@v8@@ , @@v9@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; return __readfsqword ( Number ) ^ @@v10@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s20\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_stf_asi\", \"code\": \"unsigned __int64 __fastcall gen_stf_asi ( int @@a1@@ , int @@a2@@ , unsigned int @@a3@@ , unsigned int @@a4@@ ) { unsigned int @@v7@@ ; unsigned int @@v8@@ ; unsigned int @@v9@@ ; unsigned __int64 @@v10@@ ; @@v10@@ = __readfsqword ( Number ) ; @@v7@@ = gen_get_asi ( @@a2@@ ) ; @@v8@@ = tcg_const_i32 ( @@a3@@ ) ; @@v9@@ = tcg_const_i32 ( @@a4@@ ) ; gen_helper_stf_asi ( @@a1@@ , @@v7@@ , @@v8@@ , @@v9@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; return __readfsqword ( Number ) ^ @@v10@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s20\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_swap_asi\", \"code\": \"unsigned __int64 __fastcall gen_swap_asi ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned int @@v4@@ ; unsigned int @@v5@@ ; unsigned int @@v6@@ ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v4@@ = gen_get_asi ( @@a3@@ ) ; @@v5@@ = tcg_const_i32 ( Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; gen_helper_ld_asi ( cpu_tmp64 , @@a2@@ , @@v4@@ , @@v5@@ , @@v6@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; gen_helper_st_asi ( @@a2@@ , @@a1@@ , @@v4@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; tcg_temp_free_i32 ( @@v4@@ ) ; tcg_gen_mov_i64 ( @@a1@@ , cpu_tmp64 ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s16\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s20\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_ldda_asi\", \"code\": \"unsigned __int64 __fastcall gen_ldda_asi ( __int64 @@a1@@ , int @@a2@@ , int @@a3@@ , unsigned int @@a4@@ ) { unsigned int @@v6@@ ; unsigned int @@v7@@ ; unsigned __int64 @@v8@@ ; @@v8@@ = __readfsqword ( Number ) ; @@v6@@ = gen_get_asi ( @@a3@@ ) ; @@v7@@ = tcg_const_i32 ( @@a4@@ ) ; gen_helper_ldda_asi ( @@a2@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v8@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_stda_asi\", \"code\": \"unsigned __int64 __fastcall gen_stda_asi ( int @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ ) { unsigned int @@v6@@ ; unsigned int @@v7@@ ; unsigned __int64 @@v8@@ ; @@v8@@ = __readfsqword ( Number ) ; gen_movl_reg_TN ( @@a4@@ + Number , cpu_tmp0 ) ; tcg_gen_concat32_i64 ( cpu_tmp64 , cpu_tmp0 , @@a1@@ ) ; @@v6@@ = gen_get_asi ( @@a3@@ ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; gen_helper_st_asi ( @@a2@@ , cpu_tmp64 , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v8@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_cas_asi\", \"code\": \"unsigned __int64 __fastcall gen_cas_asi ( int @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ , int @@a5@@ ) { unsigned int @@v9@@ ; unsigned int @@v10@@ ; unsigned __int64 @@v11@@ ; @@v11@@ = __readfsqword ( Number ) ; @@v9@@ = tcg_temp_new_i64 ( ) ; gen_movl_reg_TN ( @@a5@@ , @@v9@@ ) ; @@v10@@ = gen_get_asi ( @@a4@@ ) ; gen_helper_cas_asi ( @@a1@@ , @@a2@@ , @@v9@@ , @@a3@@ , @@v10@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_i64 ( @@v9@@ ) ; return __readfsqword ( Number ) ^ @@v11@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s16\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_casx_asi\", \"code\": \"unsigned __int64 __fastcall gen_casx_asi ( int @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ , int @@a5@@ ) { unsigned int @@v8@@ ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; gen_movl_reg_TN ( @@a5@@ , cpu_tmp64 ) ; @@v8@@ = gen_get_asi ( @@a4@@ ) ; gen_helper_casx_asi ( @@a1@@ , @@a2@@ , cpu_tmp64 , @@a3@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_ldstub_asi\", \"code\": \"unsigned __int64 __fastcall gen_ldstub_asi ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned int @@v5@@ ; unsigned int @@v6@@ ; unsigned int @@v7@@ ; unsigned __int64 @@v8@@ ; @@v8@@ = __readfsqword ( Number ) ; gen_ld_asi ( @@a1@@ , @@a2@@ , @@a3@@ , Number , Number ) ; @@v5@@ = tcg_const_i64 ( Number L ) ; @@v6@@ = tcg_const_i32 ( ( unsigned __int8 ) ( @@a3@@ >> Number ) ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; gen_helper_st_asi ( @@a2@@ , @@v5@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; tcg_temp_free_i64 ( @@v5@@ ) ; return __readfsqword ( Number ) ^ @@v8@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s20\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"get_src1\", \"code\": \"__int64 __fastcall get_src1 ( unsigned int @@a1@@ , int @@a2@@ ) { unsigned int @@v3@@ ; unsigned int @@v4@@ ; @@v3@@ = @@a2@@ ; @@v4@@ = ( @@a1@@ >> Number ) & Number ; if ( @@v4@@ ) { if ( @@v4@@ > Number ) tcg_gen_ld_i64 ( @@a2@@ , cpu_regwptr , Number L * ( @@v4@@ - Number ) ) ; else @@v3@@ = cpu_gregs [ @@v4@@ ] ; } else { tcg_gen_movi_i64 ( @@a2@@ , Number L ) ; } return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s16\"}]}",
"{\"name\": \"get_src2\", \"code\": \"__int64 __fastcall get_src2 ( __int16 @@a1@@ , int @@a2@@ ) { unsigned int @@v3@@ ; unsigned int @@v4@@ ; __int64 @@v5@@ ; @@v3@@ = @@a2@@ ; if ( ( @@a1@@ & Number ) != Number ) { @@v5@@ = ( int ) sign_extend ( @@a1@@ & Number , Number ) ; tcg_gen_movi_i64 ( @@a2@@ , @@v5@@ ) ; } else { @@v4@@ = @@a1@@ & Number ; if ( ( @@a1@@ & Number ) != Number ) { if ( @@v4@@ > Number ) tcg_gen_ld_i64 ( @@a2@@ , cpu_regwptr , Number L * ( @@v4@@ - Number ) ) ; else @@v3@@ = cpu_gregs [ @@a1@@ & Number ] ; } else { tcg_gen_movi_i64 ( @@a2@@ , Number L ) ; } } return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s20\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s24\"}]}"
] |
{"name": "gen_intermediate_code_internal", "code": "unsigned __int64 __fastcall gen_intermediate_code_internal ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { _BOOL4 v3 ; int v4 ; int v5 ; const char * v6 ; int v9 ; int j ; int @@v11@@ ; int @@v12@@ ; int v13 ; int v14 ; __int64 @@v15@@ ; _QWORD * @@i@@ ; __int64 @@v17@@ ; __int64 @@v18@@ [ Number ] ; unsigned __int64 @@v19@@ ; @@v19@@ = __readfsqword ( Number ) ; v9 = Number ; memset ( @@v18@@ , Number , sizeof ( @@v18@@ ) ) ; @@v18@@ [ Number ] = @@a1@@ ; @@v17@@ = * ( _QWORD * ) @@a1@@ ; @@v18@@ [ Number ] = * ( _QWORD * ) @@a1@@ ; @@v15@@ = @@v18@@ [ Number ] ; @@v18@@ [ Number ] = * ( _QWORD * ) ( @@a1@@ + Number ) ; HIDWORD ( @@v18@@ [ Number ] ) = Number ; HIDWORD ( @@v18@@ [ Number ] ) = cpu_mmu_index ( @@a3@@ ) ; @@v18@@ [ Number ] = * ( _QWORD * ) ( @@a3@@ + Number ) ; if ( ( * ( _DWORD * ) ( @@v18@@ [ Number ] + Number ) & Number ) != Number ) LODWORD ( @@v18@@ [ Number ] ) = cpu_fpu_enabled ( @@a3@@ ) ; else LODWORD ( @@v18@@ [ Number ] ) = Number ; HIDWORD ( @@v18@@ [ Number ] ) = * ( _DWORD * ) ( @@a3@@ + Number ) & Number ; v3 = * ( _DWORD * ) ( @@a3@@ + Number ) || singlestep ; LODWORD ( @@v18@@ [ Number ] ) = v3 ; cpu_tmp0 = tcg_temp_new_i64 ( ) ; cpu_tmp32 = tcg_temp_new_i32 ( ) ; cpu_tmp64 = tcg_temp_new_i64 ( ) ; cpu_dst = tcg_temp_local_new_i64 ( ) ; cpu_val = tcg_temp_local_new_i64 ( ) ; cpu_addr = tcg_temp_local_new_i64 ( ) ; @@v11@@ = Number ; @@v12@@ = * ( _WORD * ) ( @@a1@@ + Number ) & Number ; if ( ( * ( _WORD * ) ( @@a1@@ + Number ) & Number ) == Number ) @@v12@@ = Number ; gen_icount_start ( ) ; do { if ( * ( _QWORD * ) ( @@a3@@ + Number ) ) { for ( @@i@@ = * ( _QWORD * * ) ( @@a3@@ + Number ) ; @@i@@ ; @@i@@ = ( _QWORD * ) @@i@@ [ Number ] ) { if ( * @@i@@ == @@v18@@ [ Number ] ) { if ( @@v17@@ != @@v18@@ [ Number ] ) save_state ( ( __int64 ) @@v18@@ , cpu_cond ) ; gen_helper_debug ( ) ; tcg_gen_exit_tb ( Number L ) ; LODWORD ( @@v18@@ [ Number ] ) = Number ; goto LABEL_37 ; } } } if ( @@a2@@ ) { if ( logfile ) fwrite ( String , Number , Number , logfile ) ; v13 = ( __int64 ) ( gen_opc_ptr - ( _QWORD ) & gen_opc_buf ) >> Number ; if ( v9 < v13 ) { ++ v9 ; while ( v9 < v13 ) { v4 = v9 ++ ; * ( ( _BYTE * ) & gen_opc_instr_start + v4 ) = Number ; } * ( ( _QWORD * ) & gen_opc_pc + v9 ) = @@v18@@ [ Number ] ; gen_opc_npc [ v9 ] = @@v18@@ [ Number ] ; * ( ( _BYTE * ) & gen_opc_instr_start + v9 ) = Number ; * ( ( _WORD * ) & gen_opc_icount + v9 ) = @@v11@@ ; } } if ( @@v12@@ == @@v11@@ + Number && * ( __int16 * ) ( @@a1@@ + Number ) < Number ) gen_io_start ( ) ; @@v15@@ = @@v18@@ [ Number ] ; disas_sparc_insn ( @@v18@@ ) ; ++ @@v11@@ ; } while ( ! LODWORD ( @@v18@@ [ Number ] ) && @@v18@@ [ Number ] == @@v15@@ + Number && ( @@v18@@ [ Number ] & Number ) != Number && ! LODWORD ( @@v18@@ [ Number ] ) && ( unsigned __int64 ) & gen_opc_buf + Number > gen_opc_ptr && ( unsigned __int64 ) ( @@v18@@ [ Number ] - @@v17@@ ) <= Number && @@v11@@ < @@v12@@ ) ; LABEL_37 : tcg_temp_free_i64 ( ( unsigned int ) cpu_addr ) ; tcg_temp_free_i64 ( ( unsigned int ) cpu_val ) ; tcg_temp_free_i64 ( ( unsigned int ) cpu_dst ) ; tcg_temp_free_i64 ( ( unsigned int ) cpu_tmp64 ) ; tcg_temp_free_i32 ( ( unsigned int ) cpu_tmp32 ) ; tcg_temp_free_i64 ( ( unsigned int ) cpu_tmp0 ) ; if ( * ( __int16 * ) ( @@a1@@ + Number ) < Number ) gen_io_end ( ) ; if ( ! LODWORD ( @@v18@@ [ Number ] ) ) { if ( @@v18@@ [ Number ] == Number || @@v18@@ [ Number ] == Number ) { if ( @@v18@@ [ Number ] != Number ) tcg_gen_movi_i64 ( cpu_pc , @@v18@@ [ Number ] ) ; save_npc ( @@v18@@ , cpu_cond ) ; tcg_gen_exit_tb ( Number L ) ; } else { gen_goto_tb ( ( __int64 ) @@v18@@ , Number , @@v18@@ [ Number ] , @@v18@@ [ Number ] ) ; } } gen_icount_end ( @@a1@@ , @@v11@@ ) ; * gen_opc_ptr = Number ; if ( @@a2@@ ) { v14 = ( __int64 ) ( gen_opc_ptr - ( _QWORD ) & gen_opc_buf ) >> Number ; for ( j = v9 + Number ; j <= v14 ; ++ j ) { v5 = j ; * ( ( _BYTE * ) & gen_opc_instr_start + v5 ) = Number ; } gen_opc_jump_pc = @@v18@@ [ Number ] ; qword_14F48 = @@v18@@ [ Number ] ; } else { * ( _WORD * ) ( @@a1@@ + Number ) = @@v15@@ - @@v17@@ + Number ; * ( _DWORD * ) ( @@a1@@ + Number ) = @@v11@@ ; } if ( ( loglevel & Number ) != Number ) { if ( logfile ) fwrite ( String , Number , Number , logfile ) ; if ( logfile ) { v6 = ( const char * ) lookup_symbol ( @@v17@@ ) ; fprintf ( logfile , String , v6 ) ; } target_disas ( logfile , @@v17@@ , @@v15@@ - @@v17@@ + Number , Number L ) ; if ( logfile ) fputc ( Number , logfile ) ; } return __readfsqword ( Number ) ^ @@v19@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "i", "t": {"T": 3, "t": "_QWORD"}, "location": "s112"}, {"n": "v15", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s120"}, {"n": "v12", "t": {"T": 1, "n": "int", "s": 4}, "location": "s128"}, {"n": "v11", "t": {"T": 1, "n": "int", "s": 4}, "location": "s132"}, {"n": "v19", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}, {"n": "v18", "t": {"T": 2, "n": 9, "s": 8, "t": "__int64"}, "location": "s80"}, {"n": "v17", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s96"}]}
|
[{"n": "env", "t": {"T": 3, "t": "CPUSPARCState_0"}, "location": "r16"}, {"n": "tb", "t": {"T": 3, "t": "TranslationBlock_0"}, "location": "r56"}, {"n": "spc", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "bp_0", "t": {"T": 3, "t": "CPUBreakpoint"}, "location": "s112"}, {"n": "last_pc", "t": {"T": 1, "n": "target_ulong", "s": 8}, "location": "s120"}, {"n": "max_insns", "t": {"T": 1, "n": "int", "s": 4}, "location": "s128"}, {"n": "num_insns", "t": {"T": 1, "n": "int", "s": 4}, "location": "s132"}, {"n": "v18", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}, {"n": "dc1", "t": {"T": 6, "n": "DisasContext_0", "l": [{"T": 4, "n": "pc", "t": "target_ulong", "s": 8}, {"T": 4, "n": "npc", "t": "target_ulong", "s": 8}, {"T": 4, "n": "jump_pc", "t": "target_ulong[2]", "s": 16}, {"T": 4, "n": "is_br", "t": "int", "s": 4}, {"T": 4, "n": "mem_idx", "t": "int", "s": 4}, {"T": 4, "n": "fpu_enabled", "t": "int", "s": 4}, {"T": 4, "n": "address_mask_32bit", "t": "int", "s": 4}, {"T": 4, "n": "singlestep", "t": "int", "s": 4}, {"T": 4, "n": "cc_op", "t": "uint32_t", "s": 4}, {"T": 4, "n": "tb", "t": "TranslationBlock *", "s": 8}, {"T": 4, "n": "def", "t": "sparc_def_t_0 *", "s": 8}]}, "location": "s80"}, {"n": "pc_start", "t": {"T": 1, "n": "target_ulong", "s": 8}, "location": "s96"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 320 |
[
"{\"name\": \"tcg_gen_movi_i64\", \"code\": \"unsigned __int64 __fastcall tcg_gen_movi_i64 ( int @@a1@@ , __int64 @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; tcg_gen_op2i_i64 ( Number , @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_exit_tb\", \"code\": \"unsigned __int64 __fastcall tcg_gen_exit_tb ( __int64 @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_op1i ( Number , @@a1@@ ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_debug\", \"code\": \"unsigned __int64 gen_helper_debug ( ) { unsigned __int64 @@v1@@ ; @@v1@@ = __readfsqword ( Number ) ; tcg_gen_helperN ( ( __int64 ) & helper_debug , Number , Number , Number , Number , Number L ) ; return __readfsqword ( Number ) ^ @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_icount_start\", \"code\": \"unsigned __int64 gen_icount_start ( ) { unsigned int @@v1@@ ; unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; if ( use_icount ) { icount_label = gen_new_label ( ) ; @@v1@@ = tcg_temp_local_new_i32 ( ) ; tcg_gen_ld_i32 ( @@v1@@ , cpu_env , Number L ) ; icount_arg = gen_opparam_ptr + Number L ; tcg_gen_subi_i32 ( @@v1@@ , @@v1@@ , Number ) ; tcg_gen_brcondi_i32 ( Number , @@v1@@ , Number , icount_label ) ; tcg_gen_st16_i32 ( @@v1@@ , cpu_env , Number L ) ; tcg_temp_free_i32 ( @@v1@@ ) ; } return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_icount_end\", \"code\": \"unsigned __int64 __fastcall gen_icount_end ( __int64 @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; if ( use_icount ) { * ( _QWORD * ) icount_arg = @@a2@@ ; gen_set_label ( icount_label ) ; tcg_gen_exit_tb ( @@a1@@ + Number ) ; } return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_io_start\", \"code\": \"unsigned __int64 gen_io_start ( ) { unsigned int @@v1@@ ; unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; @@v1@@ = tcg_const_i32 ( Number L ) ; tcg_gen_st_i32 ( @@v1@@ , cpu_env , Number L ) ; tcg_temp_free_i32 ( @@v1@@ ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_io_end\", \"code\": \"unsigned __int64 gen_io_end ( ) { unsigned int @@v1@@ ; unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; @@v1@@ = tcg_const_i32 ( Number L ) ; tcg_gen_st_i32 ( @@v1@@ , cpu_env , Number L ) ; tcg_temp_free_i32 ( @@v1@@ ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_goto_tb\", \"code\": \"unsigned __int64 __fastcall gen_goto_tb ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { _QWORD * @@v7@@ ; unsigned __int64 @@v8@@ ; @@v8@@ = __readfsqword ( Number ) ; @@v7@@ = * ( _QWORD * * ) ( @@a1@@ + Number ) ; if ( ( ( @@a3@@ ^ * @@v7@@ ) & Number ) != Number || ( ( @@a4@@ ^ * @@v7@@ ) & Number ) != Number || * ( _DWORD * ) ( @@a1@@ + Number ) ) { tcg_gen_movi_i64 ( cpu_pc , @@a3@@ ) ; tcg_gen_movi_i64 ( cpu_npc , @@a4@@ ) ; tcg_gen_exit_tb ( Number L ) ; } else { tcg_gen_goto_tb ( @@a2@@ ) ; tcg_gen_movi_i64 ( cpu_pc , @@a3@@ ) ; tcg_gen_movi_i64 ( cpu_npc , @@a4@@ ) ; tcg_gen_exit_tb ( ( __int64 ) @@v7@@ + @@a2@@ ) ; } return __readfsqword ( Number ) ^ @@v8@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 3, \"t\": \"_QWORD\"}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"save_npc\", \"code\": \"unsigned __int64 __fastcall save_npc ( __int64 * @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; if ( @@a1@@ [ Number ] == Number ) { gen_generic_branch ( @@a1@@ [ Number ] , @@a1@@ [ Number ] , @@a2@@ ) ; @@a1@@ [ Number ] = Number L ; } else if ( @@a1@@ [ Number ] != Number ) { tcg_gen_movi_i64 ( cpu_npc , @@a1@@ [ Number ] ) ; } return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 3, \"t\": \"__int64\"}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"save_state\", \"code\": \"unsigned __int64 __fastcall save_state ( __int64 @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; tcg_gen_movi_i64 ( cpu_pc , * ( _QWORD * ) @@a1@@ ) ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) != Number ) { * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; gen_helper_compute_psr ( ) ; } save_npc ( ( __int64 * ) @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"disas_sparc_insn\", \"code\": \"unsigned __int64 __fastcall disas_sparc_insn ( _QWORD * @@a1@@ ) { unsigned int @@v2@@ ; unsigned int @@v3@@ ; int @@v4@@ ; int v5 ; int v6 ; int v7 ; int v8 ; int v9 ; int v10 ; int v11 ; int v12 ; int v13 ; int v14 ; int v15 ; int v16 ; int v17 ; int v18 ; int v19 ; int v20 ; int v21 ; int v22 ; int v23 ; int v24 ; unsigned int @@v25@@ ; int v26 ; int v27 ; int v28 ; int v29 ; unsigned int @@v30@@ ; unsigned int @@v31@@ ; int @@v32@@ ; unsigned int @@v33@@ ; unsigned int @@v34@@ ; unsigned int @@v35@@ ; unsigned int @@v36@@ ; unsigned int @@v37@@ ; unsigned int @@v38@@ ; unsigned int @@v39@@ ; unsigned int @@v40@@ ; unsigned int v41 ; unsigned int v42 ; unsigned int @@v43@@ ; unsigned int @@v44@@ ; unsigned int @@v45@@ ; unsigned int @@v46@@ ; int v47 ; int v48 ; int v49 ; unsigned int @@v50@@ ; unsigned int @@v51@@ ; unsigned int @@v52@@ ; int @@v53@@ ; unsigned int @@v54@@ ; int @@v55@@ ; int @@v56@@ ; unsigned int @@v57@@ ; int @@v58@@ ; unsigned int @@v59@@ ; unsigned int @@v60@@ ; int @@v61@@ ; unsigned int @@v62@@ ; int @@v63@@ ; unsigned int @@v64@@ ; int @@v65@@ ; unsigned int @@v66@@ ; int @@v67@@ ; unsigned int @@v68@@ ; int @@v69@@ ; unsigned int @@v70@@ ; int @@v71@@ ; unsigned int @@v72@@ ; int @@v73@@ ; unsigned int @@v74@@ ; int @@v75@@ ; unsigned int @@v76@@ ; int @@v77@@ ; unsigned int @@v78@@ ; int @@v79@@ ; unsigned int @@v80@@ ; int @@v81@@ ; unsigned int @@v82@@ ; int @@v83@@ ; unsigned int @@v84@@ ; int @@v85@@ ; unsigned int @@v86@@ ; int @@v87@@ ; unsigned int @@v88@@ ; int @@v89@@ ; unsigned int @@v90@@ ; int @@v91@@ ; unsigned int @@v92@@ ; int @@v93@@ ; unsigned int @@v94@@ ; int @@v95@@ ; unsigned int @@v96@@ ; int @@v97@@ ; int @@v98@@ ; int @@v99@@ ; unsigned int @@v100@@ ; unsigned int @@v101@@ ; unsigned int @@v102@@ ; int @@v103@@ ; unsigned int @@v104@@ ; int @@v105@@ ; int @@v106@@ ; unsigned int @@v107@@ ; int v108 ; int v109 ; int v110 ; int v111 ; int v112 ; unsigned int @@v113@@ ; int @@v114@@ ; unsigned int @@v115@@ ; __int64 v116 ; __int64 v117 ; char v118 ; char v119 ; char v120 ; __int64 v121 ; __int64 v122 ; __int64 v123 ; __int64 v124 ; __int64 v125 ; __int64 v126 ; __int64 v127 ; __int64 v128 ; __int64 v129 ; __int64 v130 ; __int64 v131 ; __int64 v132 ; __int64 v133 ; __int64 v134 ; __int64 v135 ; __int64 v136 ; unsigned __int64 @@v137@@ ; @@v137@@ = __readfsqword ( Number ) ; if ( ( loglevel & Number ) != Number ) tcg_gen_debug_insn_start ( * @@a1@@ ) ; @@v2@@ = ldl_be_p ( ( unsigned int * ) ( * @@a1@@ + guest_base ) ) ; @@v3@@ = @@v2@@ >> Number ; @@v4@@ = ( @@v2@@ >> Number ) & Number ; v5 = tcg_temp_new_i64 ( ) ; @@v25@@ = v5 ; v26 = tcg_temp_new_i64 ( ) ; @@v30@@ = v26 ; if ( @@v2@@ >> Number == Number ) { @@v31@@ = ( @@v2@@ >> Number ) & Number ; if ( * ( ( _DWORD * ) @@a1@@ + Number ) != Number ) { * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; gen_helper_compute_psr ( ) ; } v24 = get_src1 ( @@v2@@ , v5 ) ; if ( @@v31@@ == Number || @@v31@@ == Number ) { gen_movl_reg_TN ( @@v2@@ & Number , v26 ) ; tcg_gen_mov_i64 ( cpu_addr , v24 ) ; } else if ( ( @@v2@@ & Number ) != Number ) { v134 = ( int ) sign_extend ( @@v2@@ & Number , Number ) ; tcg_gen_addi_i64 ( cpu_addr , v24 , v134 ) ; } else if ( ( @@v2@@ & Number ) != Number ) { gen_movl_reg_TN ( @@v2@@ & Number , v26 ) ; tcg_gen_add_i64 ( cpu_addr , v24 , v26 ) ; } else { tcg_gen_mov_i64 ( cpu_addr , v24 ) ; } if ( @@v31@@ <= Number || @@v31@@ > Number && @@v31@@ <= Number && @@v31@@ != Number || @@v31@@ > Number && @@v31@@ <= Number || @@v31@@ > Number && @@v31@@ <= Number || @@v31@@ == Number || @@v31@@ == Number ) { switch ( @@v31@@ ) { case Number : gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; tcg_gen_qemu_ld32u ( cpu_val , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; goto LABEL_513 ; case Number : gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; tcg_gen_qemu_ld8u ( cpu_val , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; goto LABEL_513 ; case Number : gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; tcg_gen_qemu_ld16u ( cpu_val , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; goto LABEL_513 ; case Number : if ( ( @@v2@@ & Number ) != Number ) goto LABEL_580 ; save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; @@v40@@ = tcg_const_i32 ( Number L ) ; gen_helper_check_align ( cpu_addr , @@v40@@ ) ; tcg_temp_free_i32 ( @@v40@@ ) ; gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; tcg_gen_qemu_ld64 ( cpu_tmp64 , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; tcg_gen_mov_i64 ( cpu_tmp0 , cpu_tmp64 ) ; tcg_gen_andi_i64 ( cpu_tmp0 , cpu_tmp0 , Number ) ; gen_movl_TN_reg ( @@v4@@ + Number , cpu_tmp0 ) ; tcg_gen_shri_i64 ( cpu_tmp64 , cpu_tmp64 , Number L ) ; tcg_gen_mov_i64 ( cpu_val , cpu_tmp64 ) ; tcg_gen_andi_i64 ( cpu_val , cpu_val , Number ) ; goto LABEL_513 ; case Number : gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; tcg_gen_qemu_ld32s ( cpu_val , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; goto LABEL_513 ; case Number : gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; tcg_gen_qemu_ld8s ( cpu_val , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; goto LABEL_513 ; case Number : gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; tcg_gen_qemu_ld16s ( cpu_val , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; goto LABEL_513 ; case Number : gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; tcg_gen_qemu_ld64 ( cpu_val , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; goto LABEL_513 ; case Number : gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; tcg_gen_qemu_ld8s ( cpu_val , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; @@v39@@ = tcg_const_i64 ( Number L ) ; tcg_gen_qemu_st8 ( @@v39@@ , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; tcg_temp_free_i64 ( @@v39@@ ) ; goto LABEL_513 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_580 ; gen_movl_reg_TN ( @@v4@@ , cpu_val ) ; gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; tcg_gen_qemu_ld32u ( cpu_tmp0 , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; tcg_gen_qemu_st32 ( cpu_val , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; tcg_gen_mov_i64 ( cpu_val , cpu_tmp0 ) ; goto LABEL_513 ; case Number : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_ld_asi ( cpu_val , cpu_addr , @@v2@@ , Number , Number ) ; goto LABEL_513 ; case Number : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_ld_asi ( cpu_val , cpu_addr , @@v2@@ , Number , Number ) ; goto LABEL_513 ; case Number : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_ld_asi ( cpu_val , cpu_addr , @@v2@@ , Number , Number ) ; goto LABEL_513 ; case Number : if ( ( @@v2@@ & Number ) != Number ) goto LABEL_580 ; save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_ldda_asi ( ( unsigned int ) cpu_val , cpu_addr , @@v2@@ , @@v4@@ ) ; goto LABEL_566 ; case Number : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_ld_asi ( cpu_val , cpu_addr , @@v2@@ , Number , Number ) ; goto LABEL_513 ; case Number : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_ld_asi ( cpu_val , cpu_addr , @@v2@@ , Number , Number ) ; goto LABEL_513 ; case Number : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_ld_asi ( cpu_val , cpu_addr , @@v2@@ , Number , Number ) ; goto LABEL_513 ; case Number : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_ld_asi ( cpu_val , cpu_addr , @@v2@@ , Number , Number ) ; goto LABEL_513 ; case Number : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_ldstub_asi ( cpu_val , cpu_addr , @@v2@@ ) ; goto LABEL_513 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_580 ; save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_movl_reg_TN ( @@v4@@ , cpu_val ) ; gen_swap_asi ( cpu_val , cpu_addr , @@v2@@ ) ; LABEL_513 : gen_movl_TN_reg ( @@v4@@ , cpu_val ) ; break ; case Number : case Number : goto LABEL_566 ; case Number : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_ldf_asi ( cpu_addr , @@v2@@ , Number , @@v4@@ ) ; goto LABEL_566 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_ldf_asi ( cpu_addr , @@v2@@ , Number , ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_ldf_asi ( cpu_addr , @@v2@@ , Number , ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; goto LABEL_566 ; default : goto LABEL_580 ; } goto LABEL_566 ; } if ( @@v31@@ <= Number || @@v31@@ > Number ) { if ( @@v31@@ <= Number || @@v31@@ > Number && @@v31@@ <= Number || @@v31@@ == Number || @@v31@@ == Number ) { gen_movl_reg_TN ( @@v4@@ , cpu_val ) ; switch ( @@v31@@ ) { case Number : gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; tcg_gen_qemu_st32 ( cpu_val , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; goto LABEL_566 ; case Number : gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; tcg_gen_qemu_st8 ( cpu_val , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; goto LABEL_566 ; case Number : gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; tcg_gen_qemu_st16 ( cpu_val , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; goto LABEL_566 ; case Number : if ( ( @@v2@@ & Number ) != Number ) goto LABEL_580 ; save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; @@v38@@ = tcg_const_i32 ( Number L ) ; gen_helper_check_align ( cpu_addr , @@v38@@ ) ; tcg_temp_free_i32 ( @@v38@@ ) ; gen_movl_reg_TN ( @@v4@@ + Number , cpu_tmp0 ) ; tcg_gen_concat32_i64 ( cpu_tmp64 , cpu_tmp0 , cpu_val ) ; tcg_gen_qemu_st64 ( cpu_tmp64 , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; break ; case Number : gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; tcg_gen_qemu_st64 ( cpu_val , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; goto LABEL_566 ; case Number : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_st_asi ( cpu_val , cpu_addr , @@v2@@ , Number ) ; @@a1@@ [ Number ] = Number L ; goto LABEL_566 ; case Number : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_st_asi ( cpu_val , cpu_addr , @@v2@@ , Number ) ; @@a1@@ [ Number ] = Number L ; goto LABEL_566 ; case Number : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_st_asi ( cpu_val , cpu_addr , @@v2@@ , Number ) ; @@a1@@ [ Number ] = Number L ; goto LABEL_566 ; case Number : if ( ( @@v2@@ & Number ) != Number ) goto LABEL_580 ; save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_stda_asi ( cpu_val , cpu_addr , @@v2@@ , @@v4@@ ) ; break ; case Number : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_st_asi ( cpu_val , cpu_addr , @@v2@@ , Number ) ; @@a1@@ [ Number ] = Number L ; goto LABEL_566 ; default : goto LABEL_580 ; } goto LABEL_566 ; } if ( @@v31@@ > Number ) { if ( @@v31@@ <= Number || ( ( @@v2@@ >> Number ) & Number ) == Number ) goto LABEL_580 ; save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; switch ( @@v31@@ ) { case String : gen_stf_asi ( cpu_addr , @@v2@@ , Number , @@v4@@ ) ; break ; case String : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; @@v37@@ = tcg_const_i32 ( Number L ) ; gen_helper_check_align ( cpu_addr , @@v37@@ ) ; tcg_temp_free_i32 ( @@v37@@ ) ; gen_op_load_fpr_QT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_stf_asi ( cpu_addr , @@v2@@ , Number , ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case String : gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_stf_asi ( cpu_addr , @@v2@@ , Number , ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case String : gen_cas_asi ( cpu_val , cpu_addr , v26 , @@v2@@ , @@v4@@ ) ; gen_movl_TN_reg ( @@v4@@ , cpu_val ) ; break ; case String : gen_casx_asi ( cpu_val , cpu_addr , v26 , @@v2@@ , @@v4@@ ) ; gen_movl_TN_reg ( @@v4@@ , cpu_val ) ; break ; default : goto LABEL_580 ; } } else { if ( ( unsigned int ) gen_trap_ifnofpu ( @@a1@@ , ( unsigned int ) cpu_cond ) ) goto LABEL_583 ; save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; if ( @@v31@@ == Number ) { gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; @@v35@@ = tcg_const_i32 ( * ( ( unsigned int * ) @@a1@@ + Number ) ) ; gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; gen_helper_stdf ( cpu_addr , @@v35@@ ) ; tcg_temp_free_i32 ( @@v35@@ ) ; } else { if ( @@v31@@ != Number ) { if ( @@v31@@ == Number ) { gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; tcg_gen_ext_i32_i64 ( cpu_tmp0 , cpu_fpr [ @@v4@@ ] ) ; tcg_gen_qemu_st32 ( cpu_tmp0 , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; } else { gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; tcg_gen_ld_i64 ( cpu_tmp64 , cpu_env , Number L ) ; if ( @@v4@@ == Number ) tcg_gen_qemu_st64 ( cpu_tmp64 , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; else tcg_gen_qemu_st32 ( cpu_tmp64 , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; } goto LABEL_566 ; } if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_QT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; @@v36@@ = tcg_const_i32 ( * ( ( unsigned int * ) @@a1@@ + Number ) ) ; gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; gen_helper_stqf ( cpu_addr , @@v36@@ ) ; tcg_temp_free_i32 ( @@v36@@ ) ; } } } else { if ( ( unsigned int ) gen_trap_ifnofpu ( @@a1@@ , ( unsigned int ) cpu_cond ) ) goto LABEL_583 ; save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; if ( @@v31@@ == Number ) { @@v33@@ = tcg_const_i32 ( * ( ( unsigned int * ) @@a1@@ + Number ) ) ; gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; gen_helper_lddf ( cpu_addr , @@v33@@ ) ; tcg_temp_free_i32 ( @@v33@@ ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; } else { if ( @@v31@@ != Number ) { if ( @@v31@@ == Number ) { gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; tcg_gen_qemu_ld32u ( cpu_tmp0 , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; tcg_gen_trunc_i64_i32 ( cpu_fpr [ @@v4@@ ] , cpu_tmp0 ) ; } else { gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; if ( @@v4@@ == Number ) { tcg_gen_qemu_ld64 ( cpu_tmp64 , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; gen_helper_ldxfsr ( cpu_tmp64 ) ; } else { tcg_gen_qemu_ld32u ( cpu_tmp0 , cpu_addr , * ( ( _DWORD * ) @@a1@@ + Number ) ) ; tcg_gen_trunc_i64_i32 ( cpu_tmp32 , cpu_tmp0 ) ; gen_helper_ldfsr ( cpu_tmp32 ) ; } } goto LABEL_566 ; } if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; @@v34@@ = tcg_const_i32 ( * ( ( unsigned int * ) @@a1@@ + Number ) ) ; gen_address_mask ( ( __int64 ) @@a1@@ , cpu_addr ) ; gen_helper_ldqf ( cpu_addr , @@v34@@ ) ; tcg_temp_free_i32 ( @@v34@@ ) ; gen_op_store_QT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; } } LABEL_566 : if ( @@a1@@ [ Number ] == Number L ) { * @@a1@@ = Number L ; gen_op_next_insn ( ) ; } else if ( @@a1@@ [ Number ] == Number L ) { gen_branch2 ( ( __int64 ) @@a1@@ , @@a1@@ [ Number ] , @@a1@@ [ Number ] , cpu_cond ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; } else { * @@a1@@ = @@a1@@ [ Number ] ; @@a1@@ [ Number ] += Number L ; } goto LABEL_583 ; } if ( @@v3@@ == Number ) { v41 = ( @@v2@@ >> Number ) & Number ; switch ( v41 ) { case String : v7 = get_src1 ( @@v2@@ , v5 ) ; if ( ( @@v2@@ & Number ) != Number ) { tcg_gen_addi_i64 ( cpu_dst , v7 , @@v2@@ & Number ) ; } else if ( ( @@v2@@ & Number ) != Number ) { gen_movl_reg_TN ( @@v2@@ & Number , v26 ) ; tcg_gen_add_i64 ( cpu_dst , v7 , v26 ) ; } else { tcg_gen_mov_i64 ( cpu_dst , v7 ) ; } @@v103@@ = ( @@v2@@ >> Number ) & Number ; if ( @@v103@@ == Number ) { save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; tcg_gen_andi_i64 ( cpu_dst , cpu_dst , Number L ) ; tcg_gen_addi_i64 ( cpu_dst , cpu_dst , Number L ) ; tcg_gen_trunc_i64_i32 ( cpu_tmp32 , cpu_dst ) ; gen_helper_raise_exception ( cpu_tmp32 ) ; LABEL_35 : gen_op_next_insn ( ) ; tcg_gen_exit_tb ( Number L ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; goto LABEL_583 ; } if ( ! @@v103@@ ) goto LABEL_35 ; @@v104@@ = tcg_temp_new_i64 ( ) ; @@v105@@ = ( @@v2@@ >> Number ) & Number ; save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; if ( ! @@v105@@ ) { gen_cond ( @@v104@@ , Number , @@v103@@ , ( __int64 ) @@a1@@ ) ; LABEL_34 : @@v106@@ = gen_new_label ( ) ; tcg_gen_brcondi_i64 ( Number , @@v104@@ , Number L , @@v106@@ ) ; tcg_gen_andi_i64 ( cpu_dst , cpu_dst , Number L ) ; tcg_gen_addi_i64 ( cpu_dst , cpu_dst , Number L ) ; tcg_gen_trunc_i64_i32 ( cpu_tmp32 , cpu_dst ) ; gen_helper_raise_exception ( cpu_tmp32 ) ; gen_set_label ( @@v106@@ ) ; tcg_temp_free_i64 ( @@v104@@ ) ; goto LABEL_35 ; } if ( @@v105@@ == Number ) { gen_cond ( @@v104@@ , Number , @@v103@@ , ( __int64 ) @@a1@@ ) ; goto LABEL_34 ; } LABEL_580 : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; @@v115@@ = tcg_const_i32 ( Number L ) ; gen_helper_raise_exception ( @@v115@@ ) ; tcg_temp_free_i32 ( @@v115@@ ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; goto LABEL_583 ; case String : switch ( ( @@v2@@ >> Number ) & Number ) { case Number : gen_movl_TN_reg ( @@v4@@ , cpu_y ) ; goto LABEL_566 ; case Number : gen_helper_compute_psr ( ) ; gen_helper_rdccr ( cpu_dst ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; goto LABEL_566 ; case Number : tcg_gen_ext_i32_i64 ( cpu_dst , cpu_asi ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; goto LABEL_566 ; case Number : @@v102@@ = tcg_temp_new_i64 ( ) ; tcg_gen_ld_i64 ( @@v102@@ , cpu_env , Number L ) ; gen_helper_tick_get_count ( cpu_dst , @@v102@@ ) ; tcg_temp_free_i64 ( @@v102@@ ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; goto LABEL_566 ; case Number : @@v101@@ = tcg_const_i64 ( * @@a1@@ ) ; gen_movl_TN_reg ( @@v4@@ , @@v101@@ ) ; tcg_temp_free_i64 ( @@v101@@ ) ; goto LABEL_566 ; case Number : tcg_gen_ext_i32_i64 ( cpu_dst , cpu_fprs ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; goto LABEL_566 ; case Number : goto LABEL_566 ; case Number : if ( ( unsigned int ) gen_trap_ifnofpu ( @@a1@@ , ( unsigned int ) cpu_cond ) ) goto LABEL_583 ; gen_movl_TN_reg ( @@v4@@ , cpu_gsr ) ; break ; case Number : tcg_gen_ext_i32_i64 ( cpu_dst , cpu_softint ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; goto LABEL_566 ; case Number : gen_movl_TN_reg ( @@v4@@ , cpu_tick_cmpr ) ; goto LABEL_566 ; case Number : @@v100@@ = tcg_temp_new_i64 ( ) ; tcg_gen_ld_i64 ( @@v100@@ , cpu_env , Number L ) ; gen_helper_tick_get_count ( cpu_dst , @@v100@@ ) ; tcg_temp_free_i64 ( @@v100@@ ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; goto LABEL_566 ; case Number : gen_movl_TN_reg ( @@v4@@ , cpu_stick_cmpr ) ; goto LABEL_566 ; default : goto LABEL_580 ; } goto LABEL_566 ; case String : if ( ( unsigned int ) gen_trap_ifnofpu ( @@a1@@ , ( unsigned int ) cpu_cond ) ) goto LABEL_583 ; gen_op_clear_ieee_excp_and_FTT ( ) ; v47 = ( @@v2@@ >> Number ) & Number ; @@v32@@ = @@v2@@ & Number ; save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; switch ( ( @@v2@@ >> Number ) & Number ) { case Number : goto LABEL_53 ; case Number : tcg_gen_mov_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; goto LABEL_566 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_mov_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; break ; case Number : gen_helper_fnegs ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ @@v2@@ & Number ] ) ; goto LABEL_566 ; case Number : gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fnegd ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; goto LABEL_566 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_QT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fnegq ( ) ; gen_op_store_QT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : gen_helper_fabss ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ @@v2@@ & Number ] ) ; goto LABEL_566 ; case Number : gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fabsd ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; goto LABEL_566 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_QT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fabsq ( ) ; gen_op_store_QT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_clear_float_exceptions ( ) ; gen_helper_fsqrts ( cpu_tmp32 , cpu_fpr [ @@v2@@ & Number ] ) ; gen_helper_check_ieee_exceptions ( ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_tmp32 ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fsqrtd ( ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_QT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fsqrtq ( ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_QT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : gen_clear_float_exceptions ( ) ; gen_helper_fadds ( cpu_tmp32 , cpu_fpr [ v47 ] , cpu_fpr [ @@v2@@ & Number ] ) ; gen_helper_check_ieee_exceptions ( ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_tmp32 ) ; goto LABEL_566 ; case Number : gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_faddd ( ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; goto LABEL_566 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_QT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_QT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_faddq ( ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_QT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : gen_clear_float_exceptions ( ) ; gen_helper_fsubs ( cpu_tmp32 , cpu_fpr [ v47 ] , cpu_fpr [ @@v2@@ & Number ] ) ; gen_helper_check_ieee_exceptions ( ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_tmp32 ) ; goto LABEL_566 ; case Number : gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fsubd ( ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; goto LABEL_566 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_QT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_QT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fsubq ( ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_QT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_clear_float_exceptions ( ) ; gen_helper_fmuls ( cpu_tmp32 , cpu_fpr [ v47 ] , cpu_fpr [ @@v2@@ & Number ] ) ; gen_helper_check_ieee_exceptions ( ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_tmp32 ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fmuld ( ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number || ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_QT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_QT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fmulq ( ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_QT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : gen_clear_float_exceptions ( ) ; gen_helper_fdivs ( cpu_tmp32 , cpu_fpr [ v47 ] , cpu_fpr [ @@v2@@ & Number ] ) ; gen_helper_check_ieee_exceptions ( ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_tmp32 ) ; goto LABEL_566 ; case Number : gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fdivd ( ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; goto LABEL_566 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_QT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_QT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fdivq ( ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_QT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_clear_float_exceptions ( ) ; gen_helper_fsmuld ( cpu_fpr [ v47 ] , cpu_fpr [ @@v2@@ & Number ] ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fdmulq ( ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_QT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : gen_clear_float_exceptions ( ) ; gen_helper_fstox ( cpu_fpr [ @@v2@@ & Number ] ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; goto LABEL_566 ; case Number : gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fdtox ( ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; goto LABEL_566 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_QT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fqtox ( ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fxtos ( cpu_tmp32 ) ; gen_helper_check_ieee_exceptions ( ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_tmp32 ) ; goto LABEL_566 ; case Number : gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fxtod ( ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; goto LABEL_566 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fxtoq ( ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_QT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : gen_clear_float_exceptions ( ) ; gen_helper_fitos ( cpu_tmp32 , cpu_fpr [ @@v2@@ & Number ] ) ; gen_helper_check_ieee_exceptions ( ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_tmp32 ) ; goto LABEL_566 ; case Number : gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fdtos ( cpu_tmp32 ) ; gen_helper_check_ieee_exceptions ( ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_tmp32 ) ; goto LABEL_566 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_QT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fqtos ( cpu_tmp32 ) ; gen_helper_check_ieee_exceptions ( ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_tmp32 ) ; break ; case Number : gen_helper_fitod ( cpu_fpr [ @@v2@@ & Number ] ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; goto LABEL_566 ; case Number : gen_helper_fstod ( cpu_fpr [ @@v2@@ & Number ] ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; goto LABEL_566 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_QT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fqtod ( ) ; gen_helper_check_ieee_exceptions ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_helper_fitoq ( cpu_fpr [ @@v2@@ & Number ] ) ; gen_op_store_QT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_helper_fstoq ( cpu_fpr [ @@v2@@ & Number ] ) ; gen_op_store_QT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fdtoq ( ) ; gen_op_store_QT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : gen_clear_float_exceptions ( ) ; gen_helper_fstoi ( cpu_tmp32 , cpu_fpr [ @@v2@@ & Number ] ) ; gen_helper_check_ieee_exceptions ( ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_tmp32 ) ; goto LABEL_566 ; case Number : gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fdtoi ( cpu_tmp32 ) ; gen_helper_check_ieee_exceptions ( ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_tmp32 ) ; goto LABEL_566 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_QT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_clear_float_exceptions ( ) ; gen_helper_fqtoi ( cpu_tmp32 ) ; gen_helper_check_ieee_exceptions ( ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_tmp32 ) ; break ; default : goto LABEL_580 ; } goto LABEL_566 ; } if ( v41 != Number ) { switch ( v41 ) { case Number : if ( ( ( @@v2@@ >> Number ) & Number ) != Number ) { v11 = get_src1 ( @@v2@@ , v5 ) ; if ( ( @@v2@@ & Number ) != Number ) { v117 = ( int ) sign_extend ( @@v2@@ & Number , Number ) ; tcg_gen_ori_i64 ( cpu_dst , v11 , v117 ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; } else if ( ( @@v2@@ & Number ) != Number ) { gen_movl_reg_TN ( @@v2@@ & Number , v26 ) ; tcg_gen_or_i64 ( cpu_dst , v11 , v26 ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; } else { gen_movl_TN_reg ( @@v4@@ , v11 ) ; } } else if ( ( @@v2@@ & Number ) != Number ) { v116 = ( int ) sign_extend ( @@v2@@ & Number , Number ) ; @@v60@@ = tcg_const_i64 ( v116 ) ; gen_movl_TN_reg ( @@v4@@ , @@v60@@ ) ; tcg_temp_free_i64 ( @@v60@@ ) ; } else { gen_movl_reg_TN ( @@v2@@ & Number , cpu_dst ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; } goto LABEL_566 ; case Number : v12 = get_src1 ( @@v2@@ , v5 ) ; if ( ( @@v2@@ & Number ) != Number ) { v118 = sign_extend ( @@v2@@ & Number , Number ) ; if ( ( @@v2@@ & Number ) != Number ) tcg_gen_shli_i64 ( cpu_dst , v12 , v118 & Number ) ; else tcg_gen_shli_i64 ( cpu_dst , v12 , v118 & Number ) ; } else { gen_movl_reg_TN ( @@v2@@ & Number , v26 ) ; if ( ( @@v2@@ & Number ) != Number ) tcg_gen_andi_i64 ( cpu_tmp0 , v26 , Number L ) ; else tcg_gen_andi_i64 ( cpu_tmp0 , v26 , Number L ) ; tcg_gen_shl_i64 ( cpu_dst , v12 , cpu_tmp0 ) ; } break ; case Number : v13 = get_src1 ( @@v2@@ , v5 ) ; if ( ( @@v2@@ & Number ) != Number ) { v119 = sign_extend ( @@v2@@ & Number , Number ) ; if ( ( @@v2@@ & Number ) != Number ) { tcg_gen_shri_i64 ( cpu_dst , v13 , v119 & Number ) ; } else { tcg_gen_andi_i64 ( cpu_dst , v13 , Number ) ; tcg_gen_shri_i64 ( cpu_dst , cpu_dst , v119 & Number ) ; } } else { gen_movl_reg_TN ( @@v2@@ & Number , v26 ) ; if ( ( @@v2@@ & Number ) != Number ) { tcg_gen_andi_i64 ( cpu_tmp0 , v26 , Number L ) ; tcg_gen_shr_i64 ( cpu_dst , v13 , cpu_tmp0 ) ; } else { tcg_gen_andi_i64 ( cpu_tmp0 , v26 , Number L ) ; tcg_gen_andi_i64 ( cpu_dst , v13 , Number ) ; tcg_gen_shr_i64 ( cpu_dst , cpu_dst , cpu_tmp0 ) ; } } break ; case Number : v14 = get_src1 ( @@v2@@ , v5 ) ; if ( ( @@v2@@ & Number ) != Number ) { v120 = sign_extend ( @@v2@@ & Number , Number ) ; if ( ( @@v2@@ & Number ) != Number ) { tcg_gen_sari_i64 ( cpu_dst , v14 , v120 & Number ) ; } else { tcg_gen_andi_i64 ( cpu_dst , v14 , Number ) ; tcg_gen_ext32s_i64 ( cpu_dst , cpu_dst ) ; tcg_gen_sari_i64 ( cpu_dst , cpu_dst , v120 & Number ) ; } } else { gen_movl_reg_TN ( @@v2@@ & Number , v26 ) ; if ( ( @@v2@@ & Number ) != Number ) { tcg_gen_andi_i64 ( cpu_tmp0 , v26 , Number L ) ; tcg_gen_sar_i64 ( cpu_dst , v14 , cpu_tmp0 ) ; } else { tcg_gen_andi_i64 ( cpu_tmp0 , v26 , Number L ) ; tcg_gen_andi_i64 ( cpu_dst , v14 , Number ) ; tcg_gen_ext32s_i64 ( cpu_dst , cpu_dst ) ; tcg_gen_sar_i64 ( cpu_dst , cpu_dst , cpu_tmp0 ) ; } } break ; default : if ( v41 > Number ) { switch ( v41 ) { case String : v49 = ( @@v2@@ >> Number ) & Number ; @@v32@@ = @@v2@@ & Number ; if ( ( unsigned int ) gen_trap_ifnofpu ( @@a1@@ , ( unsigned int ) cpu_cond ) ) goto LABEL_583 ; switch ( ( @@v2@@ >> Number ) & Number ) { case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; v18 = get_src1 ( @@v2@@ , v5 ) ; gen_movl_reg_TN ( @@v32@@ , v26 ) ; gen_helper_array8 ( cpu_dst , v18 , v26 ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; v19 = get_src1 ( @@v2@@ , v5 ) ; gen_movl_reg_TN ( @@v32@@ , v26 ) ; gen_helper_array8 ( cpu_dst , v19 , v26 ) ; tcg_gen_shli_i64 ( cpu_dst , cpu_dst , Number L ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; v20 = get_src1 ( @@v2@@ , v5 ) ; gen_movl_reg_TN ( @@v32@@ , v26 ) ; gen_helper_array8 ( cpu_dst , v20 , v26 ) ; tcg_gen_shli_i64 ( cpu_dst , cpu_dst , Number L ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; v21 = get_src1 ( @@v2@@ , v5 ) ; gen_movl_reg_TN ( @@v32@@ , v26 ) ; gen_helper_alignaddr ( cpu_dst , v21 , v26 ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fcmple16 ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fcmpne16 ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fcmple32 ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fcmpne32 ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fcmpgt16 ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fcmpeq16 ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fcmpgt32 ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fcmpeq32 ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fmul8x16 ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fmul8x16au ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fmul8x16al ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fmul8sux16 ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fmul8ulx16 ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fmuld8sux16 ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fmuld8ulx16 ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_faligndata ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fpmerge ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fexpand ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fpadd16 ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_helper_fpadd16s ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ v49 ] , cpu_fpr [ @@v2@@ & Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fpadd32 ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_helper_fpadd32s ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ v49 ] , cpu_fpr [ @@v2@@ & Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fpsub16 ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_helper_fpsub16s ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ v49 ] , cpu_fpr [ @@v2@@ & Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_helper_fpsub32 ( ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_helper_fpsub32s ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ v49 ] , cpu_fpr [ @@v2@@ & Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_movi_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , Number ) ; tcg_gen_movi_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_movi_i32 ( cpu_fpr [ @@v4@@ ] , Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_nor_i32 ( cpu_tmp32 , cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_nor_i32 ( cpu_tmp32 , cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_nor_i32 ( cpu_tmp32 , cpu_fpr [ v49 ] , cpu_fpr [ @@v2@@ & Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_andc_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_andc_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_andc_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ v49 ] , cpu_fpr [ @@v2@@ & Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_not_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_not_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_not_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ @@v2@@ & Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_andc_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] , cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] ) ; tcg_gen_andc_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] , cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_andc_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ @@v2@@ & Number ] , cpu_fpr [ v49 ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_not_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] ) ; tcg_gen_not_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_not_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ v49 ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_xor_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_xor_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_xor_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ v49 ] , cpu_fpr [ @@v2@@ & Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_nand_i32 ( cpu_tmp32 , cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_nand_i32 ( cpu_tmp32 , cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_nand_i32 ( cpu_tmp32 , cpu_fpr [ v49 ] , cpu_fpr [ @@v2@@ & Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_and_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_and_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_and_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ v49 ] , cpu_fpr [ @@v2@@ & Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_xori_i32 ( cpu_tmp32 , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] , Number ) ; tcg_gen_xor_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_tmp32 , cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] ) ; tcg_gen_xori_i32 ( cpu_tmp32 , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] , Number ) ; tcg_gen_xor_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_tmp32 , cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_xori_i32 ( cpu_tmp32 , cpu_fpr [ @@v2@@ & Number ] , Number ) ; tcg_gen_xor_i32 ( cpu_fpr [ @@v4@@ ] , cpu_tmp32 , cpu_fpr [ v49 ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_mov_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ v49 ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_orc_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_orc_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_orc_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ v49 ] , cpu_fpr [ @@v2@@ & Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_DT0 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_op_store_DT0_fpr ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; LABEL_53 : tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ @@v32@@ ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_orc_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] , cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] ) ; tcg_gen_orc_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] , cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_orc_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ @@v2@@ & Number ] , cpu_fpr [ v49 ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_or_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_or_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_or_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ v49 ] , cpu_fpr [ @@v2@@ & Number ] ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_movi_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , Number ) ; tcg_gen_movi_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , Number ) ; break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; tcg_gen_movi_i32 ( cpu_fpr [ @@v4@@ ] , Number ) ; break ; default : goto LABEL_580 ; } break ; case String : goto LABEL_580 ; case String : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; v22 = get_src1 ( @@v2@@ , v5 ) ; if ( ( @@v2@@ & Number ) != Number ) { v132 = ( int ) sign_extend ( @@v2@@ & Number , Number ) ; tcg_gen_addi_i64 ( cpu_dst , v22 , v132 ) ; } else if ( ( @@v2@@ & Number ) != Number ) { gen_movl_reg_TN ( @@v2@@ & Number , v26 ) ; tcg_gen_add_i64 ( cpu_dst , v22 , v26 ) ; } else { tcg_gen_mov_i64 ( cpu_dst , v22 ) ; } gen_helper_restore ( ) ; gen_mov_pc_npc ( @@a1@@ , cpu_cond ) ; @@v46@@ = tcg_const_i32 ( Number L ) ; gen_helper_check_align ( cpu_dst , @@v46@@ ) ; tcg_temp_free_i32 ( @@v46@@ ) ; tcg_gen_mov_i64 ( cpu_npc , cpu_dst ) ; @@a1@@ [ Number ] = Number L ; goto LABEL_583 ; default : v23 = get_src1 ( @@v2@@ , v5 ) ; if ( ( @@v2@@ & Number ) != Number ) { v133 = ( int ) sign_extend ( @@v2@@ & Number , Number ) ; tcg_gen_addi_i64 ( cpu_dst , v23 , v133 ) ; } else if ( ( @@v2@@ & Number ) != Number ) { gen_movl_reg_TN ( @@v2@@ & Number , v26 ) ; tcg_gen_add_i64 ( cpu_dst , v23 , v26 ) ; } else { tcg_gen_mov_i64 ( cpu_dst , v23 ) ; } if ( v41 == Number ) { save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_helper_restore ( ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; } else { if ( v41 > Number ) goto LABEL_580 ; if ( v41 == Number ) { save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_helper_save ( ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; } else { if ( v41 == Number ) { @@v44@@ = tcg_const_i64 ( * @@a1@@ ) ; gen_movl_TN_reg ( @@v4@@ , @@v44@@ ) ; tcg_temp_free_i64 ( @@v44@@ ) ; gen_mov_pc_npc ( @@a1@@ , cpu_cond ) ; @@v45@@ = tcg_const_i32 ( Number L ) ; gen_helper_check_align ( cpu_dst , @@v45@@ ) ; tcg_temp_free_i32 ( @@v45@@ ) ; tcg_gen_mov_i64 ( cpu_npc , cpu_dst ) ; @@a1@@ [ Number ] = Number L ; goto LABEL_583 ; } if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) { save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; @@v43@@ = tcg_const_i32 ( Number L ) ; gen_helper_raise_exception ( @@v43@@ ) ; tcg_temp_free_i32 ( @@v43@@ ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; goto LABEL_583 ; } gen_helper_flush ( cpu_dst ) ; } } break ; } goto LABEL_566 ; } if ( v41 > Number ) { v16 = get_src1 ( @@v2@@ , v5 ) ; v28 = get_src2 ( @@v2@@ , v26 ) ; switch ( v41 ) { case String : gen_op_tadd_cc ( cpu_dst , v16 , v28 ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; tcg_gen_movi_i32 ( cpu_cc_op , Number ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; goto LABEL_566 ; case String : gen_op_tsub_cc ( cpu_dst , v16 , v28 ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; tcg_gen_movi_i32 ( cpu_cc_op , Number ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; goto LABEL_566 ; case String : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_op_tadd_ccTV ( cpu_dst , v16 , v28 ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; tcg_gen_movi_i32 ( cpu_cc_op , Number ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; goto LABEL_566 ; case String : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_op_tsub_ccTV ( cpu_dst , v16 , v28 ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; tcg_gen_movi_i32 ( cpu_cc_op , Number ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; goto LABEL_566 ; case String : gen_helper_compute_psr ( ) ; gen_op_mulscc ( cpu_dst , v16 , v28 ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; tcg_gen_movi_i32 ( cpu_cc_op , Number ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; goto LABEL_566 ; case String : @@v55@@ = ( @@v2@@ >> Number ) & Number ; @@v56@@ = ( @@v2@@ >> Number ) & Number ; @@v57@@ = tcg_temp_new_i64 ( ) ; if ( ( @@v2@@ & Number ) != Number ) { if ( @@v55@@ ) { if ( @@v55@@ != Number ) goto LABEL_580 ; gen_cond ( @@v57@@ , Number , @@v56@@ , ( __int64 ) @@a1@@ ) ; } else { gen_cond ( @@v57@@ , Number , @@v56@@ , ( __int64 ) @@a1@@ ) ; } } else { gen_fcond ( @@v57@@ , @@v55@@ , @@v56@@ ) ; } @@v58@@ = gen_new_label ( ) ; tcg_gen_brcondi_i64 ( Number , @@v57@@ , Number L , @@v58@@ ) ; if ( ( @@v2@@ & Number ) != Number ) { v130 = ( int ) sign_extend ( @@v2@@ & Number , Number ) ; @@v59@@ = tcg_const_i64 ( v130 ) ; gen_movl_TN_reg ( @@v4@@ , @@v59@@ ) ; tcg_temp_free_i64 ( @@v59@@ ) ; } else { gen_movl_reg_TN ( @@v2@@ & Number , cpu_tmp0 ) ; gen_movl_TN_reg ( @@v4@@ , cpu_tmp0 ) ; } gen_set_label ( @@v58@@ ) ; tcg_temp_free_i64 ( @@v57@@ ) ; break ; case String : gen_op_sdivx ( cpu_dst , v16 , v28 ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; goto LABEL_566 ; case String : v29 = get_src2 ( @@v2@@ , v28 ) ; gen_helper_popc ( cpu_dst , v29 ) ; gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; goto LABEL_311 ; case String : LABEL_311 : v17 = get_src1 ( @@v2@@ , v16 ) ; @@v53@@ = gen_new_label ( ) ; tcg_gen_brcondi_i64 ( gen_tcg_cond_reg [ ( @@v2@@ >> Number ) & Number ] , v17 , Number L , @@v53@@ ) ; if ( ( @@v2@@ & Number ) != Number ) { v131 = ( int ) sign_extend ( @@v2@@ & Number , Number ) ; @@v54@@ = tcg_const_i64 ( v131 ) ; gen_movl_TN_reg ( @@v4@@ , @@v54@@ ) ; tcg_temp_free_i64 ( @@v54@@ ) ; } else { gen_movl_reg_TN ( @@v2@@ & Number , cpu_tmp0 ) ; gen_movl_TN_reg ( @@v4@@ , cpu_tmp0 ) ; } gen_set_label ( @@v53@@ ) ; goto LABEL_566 ; case String : switch ( @@v4@@ ) { case Number : tcg_gen_xor_i64 ( cpu_tmp0 , v16 , v28 ) ; tcg_gen_andi_i64 ( cpu_y , cpu_tmp0 , Number ) ; goto LABEL_566 ; case Number : tcg_gen_xor_i64 ( cpu_dst , v16 , v28 ) ; gen_helper_wrccr ( cpu_dst ) ; tcg_gen_movi_i32 ( cpu_cc_op , Number ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; goto LABEL_566 ; case Number : tcg_gen_xor_i64 ( cpu_dst , v16 , v28 ) ; tcg_gen_andi_i64 ( cpu_dst , cpu_dst , Number L ) ; tcg_gen_trunc_i64_i32 ( cpu_asi , cpu_dst ) ; goto LABEL_566 ; case Number : tcg_gen_xor_i64 ( cpu_dst , v16 , v28 ) ; tcg_gen_trunc_i64_i32 ( cpu_fprs , cpu_dst ) ; save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_op_next_insn ( ) ; tcg_gen_exit_tb ( Number L ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; goto LABEL_566 ; case Number : goto LABEL_566 ; case Number : if ( ( unsigned int ) gen_trap_ifnofpu ( @@a1@@ , ( unsigned int ) cpu_cond ) ) goto LABEL_583 ; tcg_gen_xor_i64 ( cpu_gsr , v16 , v28 ) ; break ; case Number : tcg_gen_xor_i64 ( cpu_tick_cmpr , v16 , v28 ) ; @@v52@@ = tcg_temp_new_i64 ( ) ; tcg_gen_ld_i64 ( @@v52@@ , cpu_env , Number L ) ; gen_helper_tick_set_limit ( @@v52@@ , cpu_tick_cmpr ) ; tcg_temp_free_i64 ( @@v52@@ ) ; goto LABEL_566 ; case Number : tcg_gen_xor_i64 ( cpu_dst , v16 , v28 ) ; @@v51@@ = tcg_temp_new_i64 ( ) ; tcg_gen_ld_i64 ( @@v51@@ , cpu_env , Number L ) ; gen_helper_tick_set_count ( @@v51@@ , cpu_dst ) ; tcg_temp_free_i64 ( @@v51@@ ) ; goto LABEL_566 ; case Number : tcg_gen_xor_i64 ( cpu_stick_cmpr , v16 , v28 ) ; @@v50@@ = tcg_temp_new_i64 ( ) ; tcg_gen_ld_i64 ( @@v50@@ , cpu_env , Number L ) ; gen_helper_tick_set_limit ( @@v50@@ , cpu_stick_cmpr ) ; tcg_temp_free_i64 ( @@v50@@ ) ; goto LABEL_566 ; default : goto LABEL_580 ; } goto LABEL_566 ; default : goto LABEL_580 ; } goto LABEL_566 ; } v15 = get_src1 ( @@v2@@ , v5 ) ; v27 = get_src2 ( @@v2@@ , v26 ) ; switch ( ( @@v2@@ >> Number ) & Number ) { case Number : if ( ( @@v2@@ & Number ) != Number ) { v121 = ( int ) sign_extend ( @@v2@@ & Number , Number ) ; if ( ( ( @@v2@@ >> Number ) & Number ) != Number ) { gen_op_addi_cc ( cpu_dst , v15 , v121 ) ; tcg_gen_movi_i32 ( cpu_cc_op , Number ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; } else { tcg_gen_addi_i64 ( cpu_dst , v15 , v121 ) ; } } else if ( ( ( @@v2@@ >> Number ) & Number ) != Number ) { gen_op_add_cc ( cpu_dst , v15 , v27 ) ; tcg_gen_movi_i32 ( cpu_cc_op , Number ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; } else { tcg_gen_add_i64 ( cpu_dst , v15 , v27 ) ; } goto LABEL_216 ; case Number : if ( ( @@v2@@ & Number ) != Number ) { v122 = ( int ) sign_extend ( @@v2@@ & Number , Number ) ; tcg_gen_andi_i64 ( cpu_dst , v15 , v122 ) ; } else { tcg_gen_and_i64 ( cpu_dst , v15 , v27 ) ; } if ( ( ( @@v2@@ >> Number ) & Number ) == Number ) goto LABEL_216 ; goto LABEL_273 ; case Number : if ( ( @@v2@@ & Number ) != Number ) { v123 = ( int ) sign_extend ( @@v2@@ & Number , Number ) ; tcg_gen_ori_i64 ( cpu_dst , v15 , v123 ) ; } else { tcg_gen_or_i64 ( cpu_dst , v15 , v27 ) ; } if ( ( ( @@v2@@ >> Number ) & Number ) == Number ) goto LABEL_216 ; goto LABEL_273 ; case Number : if ( ( @@v2@@ & Number ) != Number ) { v124 = ( int ) sign_extend ( @@v2@@ & Number , Number ) ; tcg_gen_xori_i64 ( cpu_dst , v15 , v124 ) ; } else { tcg_gen_xor_i64 ( cpu_dst , v15 , v27 ) ; } if ( ( ( @@v2@@ >> Number ) & Number ) == Number ) goto LABEL_216 ; goto LABEL_273 ; case Number : if ( ( @@v2@@ & Number ) != Number ) { v125 = ( int ) sign_extend ( @@v2@@ & Number , Number ) ; if ( ( ( @@v2@@ >> Number ) & Number ) != Number ) gen_op_subi_cc ( cpu_dst , v15 , v125 , ( __int64 ) @@a1@@ ) ; else tcg_gen_subi_i64 ( cpu_dst , v15 , v125 ) ; } else if ( ( ( @@v2@@ >> Number ) & Number ) != Number ) { gen_op_sub_cc ( cpu_dst , v15 , v27 ) ; tcg_gen_movi_i32 ( cpu_cc_op , Number ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; } else { tcg_gen_sub_i64 ( cpu_dst , v15 , v27 ) ; } goto LABEL_216 ; case Number : if ( ( @@v2@@ & Number ) != Number ) { v126 = ( int ) sign_extend ( @@v2@@ & Number , Number ) ; tcg_gen_andi_i64 ( cpu_dst , v15 , ~ v126 ) ; } else { tcg_gen_andc_i64 ( cpu_dst , v15 , v27 ) ; } if ( ( ( @@v2@@ >> Number ) & Number ) == Number ) goto LABEL_216 ; goto LABEL_273 ; case Number : if ( ( @@v2@@ & Number ) != Number ) { v127 = ( int ) sign_extend ( @@v2@@ & Number , Number ) ; tcg_gen_ori_i64 ( cpu_dst , v15 , ~ v127 ) ; } else { tcg_gen_orc_i64 ( cpu_dst , v15 , v27 ) ; } if ( ( ( @@v2@@ >> Number ) & Number ) == Number ) goto LABEL_216 ; goto LABEL_273 ; case Number : if ( ( @@v2@@ & Number ) != Number ) { v128 = ( int ) sign_extend ( @@v2@@ & Number , Number ) ; tcg_gen_xori_i64 ( cpu_dst , v15 , ~ v128 ) ; } else { tcg_gen_not_i64 ( cpu_tmp0 , v27 ) ; tcg_gen_xor_i64 ( cpu_dst , v15 , cpu_tmp0 ) ; } if ( ( ( @@v2@@ >> Number ) & Number ) == Number ) goto LABEL_216 ; goto LABEL_273 ; case Number : gen_op_addx_int ( ( __int64 ) @@a1@@ , cpu_dst , v15 , v27 , ( @@v2@@ >> Number ) & Number ) ; goto LABEL_216 ; case Number : if ( ( @@v2@@ & Number ) != Number ) { v129 = ( int ) sign_extend ( @@v2@@ & Number , Number ) ; tcg_gen_muli_i64 ( cpu_dst , v15 , v129 ) ; } else { tcg_gen_mul_i64 ( cpu_dst , v15 , v27 ) ; } goto LABEL_216 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_580 ; gen_op_umul ( cpu_dst , v15 , v27 ) ; if ( ( ( @@v2@@ >> Number ) & Number ) != Number ) goto LABEL_273 ; goto LABEL_216 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_580 ; gen_op_smul ( cpu_dst , v15 , v27 ) ; if ( ( ( @@v2@@ >> Number ) & Number ) != Number ) { LABEL_273 : tcg_gen_mov_i64 ( cpu_cc_dst , cpu_dst ) ; tcg_gen_movi_i32 ( cpu_cc_op , Number ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; } break ; case Number : gen_op_subx_int ( ( __int64 ) @@a1@@ , cpu_dst , v15 , v27 , ( @@v2@@ >> Number ) & Number ) ; goto LABEL_216 ; case Number : tcg_gen_mov_i64 ( cpu_cc_src , v15 ) ; tcg_gen_mov_i64 ( cpu_cc_src2 , v27 ) ; gen_trap_ifdivzero_tl ( cpu_cc_src2 ) ; tcg_gen_divu_i64 ( cpu_dst , cpu_cc_src , cpu_cc_src2 ) ; goto LABEL_216 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_580 ; gen_helper_udiv ( cpu_dst , v15 , v27 ) ; if ( ( ( @@v2@@ >> Number ) & Number ) != Number ) { tcg_gen_mov_i64 ( cpu_cc_dst , cpu_dst ) ; tcg_gen_movi_i32 ( cpu_cc_op , Number ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; } break ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_580 ; gen_helper_sdiv ( cpu_dst , v15 , v27 ) ; if ( ( ( @@v2@@ >> Number ) & Number ) != Number ) { tcg_gen_mov_i64 ( cpu_cc_dst , cpu_dst ) ; tcg_gen_movi_i32 ( cpu_cc_op , Number ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; } break ; default : goto LABEL_580 ; } break ; } LABEL_216 : gen_movl_TN_reg ( @@v4@@ , cpu_dst ) ; goto LABEL_566 ; } if ( ( unsigned int ) gen_trap_ifnofpu ( @@a1@@ , ( unsigned int ) cpu_cond ) ) goto LABEL_583 ; gen_op_clear_ieee_excp_and_FTT ( ) ; v48 = ( @@v2@@ >> Number ) & Number ; v42 = ( @@v2@@ >> Number ) & Number ; save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; switch ( ( @@v2@@ >> Number ) & Number ) { case Number : @@v99@@ = gen_new_label ( ) ; v8 = get_src1 ( @@v2@@ , v5 ) ; tcg_gen_brcondi_i64 ( gen_tcg_cond_reg [ ( @@v2@@ >> Number ) & Number ] , v8 , Number L , @@v99@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ @@v2@@ & Number ] ) ; gen_set_label ( @@v99@@ ) ; goto LABEL_566 ; case Number : @@v98@@ = gen_new_label ( ) ; v9 = get_src1 ( @@v2@@ , v5 ) ; tcg_gen_brcondi_i64 ( gen_tcg_cond_reg [ ( @@v2@@ >> Number ) & Number ] , v9 , Number L , @@v98@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; gen_set_label ( @@v98@@ ) ; goto LABEL_566 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) != Number ) { @@v97@@ = gen_new_label ( ) ; v10 = get_src1 ( @@v2@@ , v5 ) ; tcg_gen_brcondi_i64 ( gen_tcg_cond_reg [ ( @@v2@@ >> Number ) & Number ] , v10 , Number L , @@v97@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; gen_set_label ( @@v97@@ ) ; goto LABEL_566 ; } LABEL_582 : save_state ( ( __int64 ) @@a1@@ , cpu_cond ) ; gen_op_fpexception_im ( Number ) ; * ( ( _DWORD * ) @@a1@@ + Number ) = Number ; goto LABEL_583 ; } if ( v42 == Number ) { if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; @@v61@@ = gen_new_label ( ) ; @@v62@@ = tcg_temp_new_i64 ( ) ; gen_cond ( @@v62@@ , Number , ( @@v2@@ >> Number ) & Number , ( __int64 ) @@a1@@ ) ; tcg_gen_brcondi_i64 ( Number , @@v62@@ , Number L , @@v61@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; gen_set_label ( @@v61@@ ) ; tcg_temp_free_i64 ( @@v62@@ ) ; goto LABEL_566 ; } if ( v42 > Number ) goto LABEL_580 ; if ( v42 == Number ) { @@v63@@ = gen_new_label ( ) ; @@v64@@ = tcg_temp_new_i64 ( ) ; gen_cond ( @@v64@@ , Number , ( @@v2@@ >> Number ) & Number , ( __int64 ) @@a1@@ ) ; tcg_gen_brcondi_i64 ( Number , @@v64@@ , Number L , @@v63@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; gen_set_label ( @@v63@@ ) ; tcg_temp_free_i64 ( @@v64@@ ) ; goto LABEL_566 ; } if ( v42 == Number ) { @@v65@@ = gen_new_label ( ) ; @@v66@@ = tcg_temp_new_i64 ( ) ; gen_cond ( @@v66@@ , Number , ( @@v2@@ >> Number ) & Number , ( __int64 ) @@a1@@ ) ; tcg_gen_brcondi_i64 ( Number , @@v66@@ , Number L , @@v65@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ @@v2@@ & Number ] ) ; gen_set_label ( @@v65@@ ) ; tcg_temp_free_i64 ( @@v66@@ ) ; goto LABEL_566 ; } if ( v42 != Number ) { if ( v42 > Number ) goto LABEL_580 ; if ( v42 != Number ) { if ( v42 == Number ) { @@v71@@ = gen_new_label ( ) ; @@v72@@ = tcg_temp_new_i64 ( ) ; gen_cond ( @@v72@@ , Number , ( @@v2@@ >> Number ) & Number , ( __int64 ) @@a1@@ ) ; tcg_gen_brcondi_i64 ( Number , @@v72@@ , Number L , @@v71@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ @@v2@@ & Number ] ) ; gen_set_label ( @@v71@@ ) ; tcg_temp_free_i64 ( @@v72@@ ) ; } else if ( v42 == Number ) { if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; @@v73@@ = gen_new_label ( ) ; @@v74@@ = tcg_temp_new_i64 ( ) ; gen_fcond ( @@v74@@ , Number , ( @@v2@@ >> Number ) & Number ) ; tcg_gen_brcondi_i64 ( Number , @@v74@@ , Number L , @@v73@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; gen_set_label ( @@v73@@ ) ; tcg_temp_free_i64 ( @@v74@@ ) ; } else { if ( v42 > Number ) goto LABEL_580 ; if ( v42 == Number ) { @@v75@@ = gen_new_label ( ) ; @@v76@@ = tcg_temp_new_i64 ( ) ; gen_fcond ( @@v76@@ , Number , ( @@v2@@ >> Number ) & Number ) ; tcg_gen_brcondi_i64 ( Number , @@v76@@ , Number L , @@v75@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; gen_set_label ( @@v75@@ ) ; tcg_temp_free_i64 ( @@v76@@ ) ; } else if ( v42 == Number ) { @@v77@@ = gen_new_label ( ) ; @@v78@@ = tcg_temp_new_i64 ( ) ; gen_fcond ( @@v78@@ , Number , ( @@v2@@ >> Number ) & Number ) ; tcg_gen_brcondi_i64 ( Number , @@v78@@ , Number L , @@v77@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ @@v2@@ & Number ] ) ; gen_set_label ( @@v77@@ ) ; tcg_temp_free_i64 ( @@v78@@ ) ; } else { if ( v42 > Number ) goto LABEL_580 ; if ( v42 >= Number ) { switch ( v42 ) { case Number : @@v89@@ = gen_new_label ( ) ; @@v90@@ = tcg_temp_new_i64 ( ) ; gen_fcond ( @@v90@@ , Number , ( @@v2@@ >> Number ) & Number ) ; tcg_gen_brcondi_i64 ( Number , @@v90@@ , Number L , @@v89@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ @@v2@@ & Number ] ) ; gen_set_label ( @@v89@@ ) ; tcg_temp_free_i64 ( @@v90@@ ) ; goto LABEL_566 ; case Number : @@v87@@ = gen_new_label ( ) ; @@v88@@ = tcg_temp_new_i64 ( ) ; gen_fcond ( @@v88@@ , Number , ( @@v2@@ >> Number ) & Number ) ; tcg_gen_brcondi_i64 ( Number , @@v88@@ , Number L , @@v87@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; gen_set_label ( @@v87@@ ) ; tcg_temp_free_i64 ( @@v88@@ ) ; goto LABEL_566 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; @@v85@@ = gen_new_label ( ) ; @@v86@@ = tcg_temp_new_i64 ( ) ; gen_fcond ( @@v86@@ , Number , ( @@v2@@ >> Number ) & Number ) ; tcg_gen_brcondi_i64 ( Number , @@v86@@ , Number L , @@v85@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; gen_set_label ( @@v85@@ ) ; tcg_temp_free_i64 ( @@v86@@ ) ; break ; case Number : gen_op_fcmps ( ( @@v2@@ >> Number ) & Number , cpu_fpr [ v48 ] , cpu_fpr [ @@v2@@ & Number ] ) ; goto LABEL_566 ; case Number : gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_op_fcmpd ( ( @@v2@@ >> Number ) & Number ) ; goto LABEL_566 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_QT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_QT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_op_fcmpq ( ( @@v2@@ >> Number ) & Number ) ; break ; case Number : gen_op_fcmpes ( ( @@v2@@ >> Number ) & Number , cpu_fpr [ v48 ] , cpu_fpr [ @@v2@@ & Number ] ) ; goto LABEL_566 ; case Number : gen_op_load_fpr_DT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_DT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_op_fcmped ( ( @@v2@@ >> Number ) & Number ) ; goto LABEL_566 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; gen_op_load_fpr_QT0 ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) ; gen_op_load_fpr_QT1 ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) ; gen_op_fcmpeq ( ( @@v2@@ >> Number ) & Number ) ; break ; case Number : @@v83@@ = gen_new_label ( ) ; @@v84@@ = tcg_temp_new_i64 ( ) ; gen_fcond ( @@v84@@ , Number , ( @@v2@@ >> Number ) & Number ) ; tcg_gen_brcondi_i64 ( Number , @@v84@@ , Number L , @@v83@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ @@v2@@ & Number ] ) ; gen_set_label ( @@v83@@ ) ; tcg_temp_free_i64 ( @@v84@@ ) ; goto LABEL_566 ; case Number : @@v81@@ = gen_new_label ( ) ; @@v82@@ = tcg_temp_new_i64 ( ) ; gen_fcond ( @@v82@@ , Number , ( @@v2@@ >> Number ) & Number ) ; tcg_gen_brcondi_i64 ( Number , @@v82@@ , Number L , @@v81@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; gen_set_label ( @@v81@@ ) ; tcg_temp_free_i64 ( @@v82@@ ) ; goto LABEL_566 ; case Number : if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; @@v79@@ = gen_new_label ( ) ; @@v80@@ = tcg_temp_new_i64 ( ) ; gen_fcond ( @@v80@@ , Number , ( @@v2@@ >> Number ) & Number ) ; tcg_gen_brcondi_i64 ( Number , @@v80@@ , Number L , @@v79@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; gen_set_label ( @@v79@@ ) ; tcg_temp_free_i64 ( @@v80@@ ) ; break ; default : goto LABEL_580 ; } goto LABEL_566 ; } if ( v42 == Number ) { if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; @@v91@@ = gen_new_label ( ) ; @@v92@@ = tcg_temp_new_i64 ( ) ; gen_fcond ( @@v92@@ , Number , ( @@v2@@ >> Number ) & Number ) ; tcg_gen_brcondi_i64 ( Number , @@v92@@ , Number L , @@v91@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; gen_set_label ( @@v91@@ ) ; tcg_temp_free_i64 ( @@v92@@ ) ; } else { if ( v42 > Number ) goto LABEL_580 ; if ( v42 == Number ) { @@v95@@ = gen_new_label ( ) ; @@v96@@ = tcg_temp_new_i64 ( ) ; gen_fcond ( @@v96@@ , Number , ( @@v2@@ >> Number ) & Number ) ; tcg_gen_brcondi_i64 ( Number , @@v96@@ , Number L , @@v95@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ @@v4@@ ] , cpu_fpr [ @@v2@@ & Number ] ) ; gen_set_label ( @@v95@@ ) ; tcg_temp_free_i64 ( @@v96@@ ) ; } else { if ( v42 != Number ) goto LABEL_580 ; @@v93@@ = gen_new_label ( ) ; @@v94@@ = tcg_temp_new_i64 ( ) ; gen_fcond ( @@v94@@ , Number , ( @@v2@@ >> Number ) & Number ) ; tcg_gen_brcondi_i64 ( Number , @@v94@@ , Number L , @@v93@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; gen_set_label ( @@v93@@ ) ; tcg_temp_free_i64 ( @@v94@@ ) ; } } } } goto LABEL_566 ; } @@v67@@ = gen_new_label ( ) ; @@v68@@ = tcg_temp_new_i64 ( ) ; gen_cond ( @@v68@@ , Number , ( @@v2@@ >> Number ) & Number , ( __int64 ) @@a1@@ ) ; tcg_gen_brcondi_i64 ( Number , @@v68@@ , Number L , @@v67@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; gen_set_label ( @@v67@@ ) ; tcg_temp_free_i64 ( @@v68@@ ) ; } if ( ( * ( _DWORD * ) ( @@a1@@ [ Number ] + Number L ) & Number ) == Number ) goto LABEL_582 ; @@v69@@ = gen_new_label ( ) ; @@v70@@ = tcg_temp_new_i64 ( ) ; gen_cond ( @@v70@@ , Number , ( @@v2@@ >> Number ) & Number , ( __int64 ) @@a1@@ ) ; tcg_gen_brcondi_i64 ( Number , @@v70@@ , Number L , @@v69@@ ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ] , cpu_fpr [ ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; tcg_gen_mov_i32 ( cpu_fpr [ ( ( Number * ( ( @@v2@@ >> Number ) & Number ) ) & Number | ( @@v2@@ >> Number ) & Number ) + Number ] , cpu_fpr [ ( ( Number * ( @@v2@@ & Number ) ) & Number | @@v2@@ & Number ) + Number ] ) ; gen_set_label ( @@v69@@ ) ; tcg_temp_free_i64 ( @@v70@@ ) ; goto LABEL_566 ; } if ( @@v3@@ ) { v135 = ( int ) ( Number * sign_extend ( @@v2@@ & Number , Number ) ) ; @@v107@@ = tcg_const_i64 ( * @@a1@@ ) ; gen_movl_TN_reg ( Number , @@v107@@ ) ; tcg_temp_free_i64 ( @@v107@@ ) ; v136 = * @@a1@@ + v135 ; gen_mov_pc_npc ( @@a1@@ , cpu_cond ) ; @@a1@@ [ Number ] = v136 ; } else { switch ( ( @@v2@@ >> Number ) & Number ) { case Number : v108 = Number * sign_extend ( @@v2@@ & Number , Number ) ; @@v114@@ = ( @@v2@@ >> Number ) & Number ; if ( ! @@v114@@ ) { do_branch ( ( __int64 ) @@a1@@ , v108 , @@v2@@ , Number , cpu_cond ) ; break ; } if ( @@v114@@ != Number ) goto LABEL_580 ; do_branch ( ( __int64 ) @@a1@@ , v108 , @@v2@@ , Number , cpu_cond ) ; break ; case Number : v111 = Number * sign_extend ( @@v2@@ & Number , Number ) ; do_branch ( ( __int64 ) @@a1@@ , v111 , @@v2@@ , Number , cpu_cond ) ; break ; case Number : v109 = Number * sign_extend ( @@v2@@ & Number | ( unsigned __int16 ) ( @@v2@@ >> Number << Number ) , Number ) ; v6 = get_src1 ( @@v2@@ , v5 ) ; do_branch_reg ( ( __int64 ) @@a1@@ , v109 , @@v2@@ , cpu_cond , v6 ) ; break ; case Number : if ( @@v4@@ ) { @@v113@@ = tcg_const_i64 ( @@v2@@ << Number ) ; gen_movl_TN_reg ( @@v4@@ , @@v113@@ ) ; tcg_temp_free_i64 ( @@v113@@ ) ; } goto LABEL_566 ; case Number : if ( ! ( unsigned int ) gen_trap_ifnofpu ( @@a1@@ , ( unsigned int ) cpu_cond ) ) { v110 = Number * sign_extend ( @@v2@@ & Number , Number ) ; do_fbranch ( ( __int64 ) @@a1@@ , v110 , @@v2@@ , ( @@v2@@ >> Number ) & Number , cpu_cond ) ; } break ; case Number : if ( ! ( unsigned int ) gen_trap_ifnofpu ( @@a1@@ , ( unsigned int ) cpu_cond ) ) { v112 = Number * sign_extend ( @@v2@@ & Number , Number ) ; do_fbranch ( ( __int64 ) @@a1@@ , v112 , @@v2@@ , Number , cpu_cond ) ; } break ; default : goto LABEL_580 ; } } LABEL_583 : tcg_temp_free_i64 ( @@v25@@ ) ; tcg_temp_free_i64 ( @@v30@@ ) ; return __readfsqword ( Number ) ^ @@v137@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 3, \"t\": \"_QWORD\"}, \"location\": \"r56\"}, {\"n\": \"v96\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s100\"}, {\"n\": \"v95\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s104\"}, {\"n\": \"v94\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s108\"}, {\"n\": \"v93\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s112\"}, {\"n\": \"v92\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s116\"}, {\"n\": \"v91\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s120\"}, {\"n\": \"v90\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s124\"}, {\"n\": \"v89\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s128\"}, {\"n\": \"v88\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s132\"}, {\"n\": \"v87\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s136\"}, {\"n\": \"v86\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s140\"}, {\"n\": \"v85\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s144\"}, {\"n\": \"v84\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s148\"}, {\"n\": \"v83\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s152\"}, {\"n\": \"v82\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s156\"}, {\"n\": \"v81\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s160\"}, {\"n\": \"v80\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s164\"}, {\"n\": \"v79\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s168\"}, {\"n\": \"v78\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s172\"}, {\"n\": \"v77\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s176\"}, {\"n\": \"v76\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s180\"}, {\"n\": \"v75\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s184\"}, {\"n\": \"v74\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s188\"}, {\"n\": \"v73\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s192\"}, {\"n\": \"v72\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s196\"}, {\"n\": \"v71\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s200\"}, {\"n\": \"v70\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s204\"}, {\"n\": \"v69\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s208\"}, {\"n\": \"v68\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s212\"}, {\"n\": \"v67\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s216\"}, {\"n\": \"v66\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s220\"}, {\"n\": \"v65\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s224\"}, {\"n\": \"v64\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s228\"}, {\"n\": \"v63\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s232\"}, {\"n\": \"v62\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s240\"}, {\"n\": \"v61\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s244\"}, {\"n\": \"v60\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s248\"}, {\"n\": \"v59\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s252\"}, {\"n\": \"v58\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s256\"}, {\"n\": \"v57\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s260\"}, {\"n\": \"v56\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s264\"}, {\"n\": \"v55\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s268\"}, {\"n\": \"v54\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s272\"}, {\"n\": \"v53\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s276\"}, {\"n\": \"v115\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s28\"}, {\"n\": \"v52\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s284\"}, {\"n\": \"v51\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s288\"}, {\"n\": \"v50\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s292\"}, {\"n\": \"v46\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s304\"}, {\"n\": \"v45\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s308\"}, {\"n\": \"v44\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s312\"}, {\"n\": \"v43\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s316\"}, {\"n\": \"v114\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s32\"}, {\"n\": \"v40\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s324\"}, {\"n\": \"v39\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s328\"}, {\"n\": \"v38\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s332\"}, {\"n\": \"v37\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s336\"}, {\"n\": \"v36\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s340\"}, {\"n\": \"v35\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s344\"}, {\"n\": \"v34\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s348\"}, {\"n\": \"v33\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s352\"}, {\"n\": \"v32\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s356\"}, {\"n\": \"v113\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s36\"}, {\"n\": \"v31\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s360\"}, {\"n\": \"v30\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s364\"}, {\"n\": \"v25\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s372\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s380\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s384\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s388\"}, {\"n\": \"v107\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s56\"}, {\"n\": \"v106\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s60\"}, {\"n\": \"v105\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s64\"}, {\"n\": \"v104\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s68\"}, {\"n\": \"v103\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s72\"}, {\"n\": \"v102\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s76\"}, {\"n\": \"v137\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}, {\"n\": \"v101\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s80\"}, {\"n\": \"v100\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s84\"}, {\"n\": \"v99\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s88\"}, {\"n\": \"v98\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s92\"}, {\"n\": \"v97\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s96\"}]}",
"{\"name\": \"gen_intermediate_code\", \"code\": \"unsigned __int64 __fastcall gen_intermediate_code ( __int64 @@a1@@ , __int64 @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; gen_intermediate_code_internal ( @@a2@@ , Number , @@a1@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_intermediate_code", "code": "unsigned __int64 __fastcall gen_intermediate_code ( __int64 @@a1@@ , __int64 @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; gen_intermediate_code_internal ( @@a2@@ , Number , @@a1@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "env", "t": {"T": 3, "t": "CPUSPARCState_0"}, "location": "r56"}, {"n": "tb", "t": {"T": 3, "t": "TranslationBlock_0"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 321 |
[
"{\"name\": \"gen_intermediate_code_internal\", \"code\": \"unsigned __int64 __fastcall gen_intermediate_code_internal ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { _BOOL4 v3 ; int v4 ; int v5 ; const char * v6 ; int v9 ; int j ; int @@v11@@ ; int @@v12@@ ; int v13 ; int v14 ; __int64 @@v15@@ ; _QWORD * @@i@@ ; __int64 @@v17@@ ; __int64 @@v18@@ [ Number ] ; unsigned __int64 @@v19@@ ; @@v19@@ = __readfsqword ( Number ) ; v9 = Number ; memset ( @@v18@@ , Number , sizeof ( @@v18@@ ) ) ; @@v18@@ [ Number ] = @@a1@@ ; @@v17@@ = * ( _QWORD * ) @@a1@@ ; @@v18@@ [ Number ] = * ( _QWORD * ) @@a1@@ ; @@v15@@ = @@v18@@ [ Number ] ; @@v18@@ [ Number ] = * ( _QWORD * ) ( @@a1@@ + Number ) ; HIDWORD ( @@v18@@ [ Number ] ) = Number ; HIDWORD ( @@v18@@ [ Number ] ) = cpu_mmu_index ( @@a3@@ ) ; @@v18@@ [ Number ] = * ( _QWORD * ) ( @@a3@@ + Number ) ; if ( ( * ( _DWORD * ) ( @@v18@@ [ Number ] + Number ) & Number ) != Number ) LODWORD ( @@v18@@ [ Number ] ) = cpu_fpu_enabled ( @@a3@@ ) ; else LODWORD ( @@v18@@ [ Number ] ) = Number ; HIDWORD ( @@v18@@ [ Number ] ) = * ( _DWORD * ) ( @@a3@@ + Number ) & Number ; v3 = * ( _DWORD * ) ( @@a3@@ + Number ) || singlestep ; LODWORD ( @@v18@@ [ Number ] ) = v3 ; cpu_tmp0 = tcg_temp_new_i64 ( ) ; cpu_tmp32 = tcg_temp_new_i32 ( ) ; cpu_tmp64 = tcg_temp_new_i64 ( ) ; cpu_dst = tcg_temp_local_new_i64 ( ) ; cpu_val = tcg_temp_local_new_i64 ( ) ; cpu_addr = tcg_temp_local_new_i64 ( ) ; @@v11@@ = Number ; @@v12@@ = * ( _WORD * ) ( @@a1@@ + Number ) & Number ; if ( ( * ( _WORD * ) ( @@a1@@ + Number ) & Number ) == Number ) @@v12@@ = Number ; gen_icount_start ( ) ; do { if ( * ( _QWORD * ) ( @@a3@@ + Number ) ) { for ( @@i@@ = * ( _QWORD * * ) ( @@a3@@ + Number ) ; @@i@@ ; @@i@@ = ( _QWORD * ) @@i@@ [ Number ] ) { if ( * @@i@@ == @@v18@@ [ Number ] ) { if ( @@v17@@ != @@v18@@ [ Number ] ) save_state ( ( __int64 ) @@v18@@ , cpu_cond ) ; gen_helper_debug ( ) ; tcg_gen_exit_tb ( Number L ) ; LODWORD ( @@v18@@ [ Number ] ) = Number ; goto LABEL_37 ; } } } if ( @@a2@@ ) { if ( logfile ) fwrite ( String , Number , Number , logfile ) ; v13 = ( __int64 ) ( gen_opc_ptr - ( _QWORD ) & gen_opc_buf ) >> Number ; if ( v9 < v13 ) { ++ v9 ; while ( v9 < v13 ) { v4 = v9 ++ ; * ( ( _BYTE * ) & gen_opc_instr_start + v4 ) = Number ; } * ( ( _QWORD * ) & gen_opc_pc + v9 ) = @@v18@@ [ Number ] ; gen_opc_npc [ v9 ] = @@v18@@ [ Number ] ; * ( ( _BYTE * ) & gen_opc_instr_start + v9 ) = Number ; * ( ( _WORD * ) & gen_opc_icount + v9 ) = @@v11@@ ; } } if ( @@v12@@ == @@v11@@ + Number && * ( __int16 * ) ( @@a1@@ + Number ) < Number ) gen_io_start ( ) ; @@v15@@ = @@v18@@ [ Number ] ; disas_sparc_insn ( @@v18@@ ) ; ++ @@v11@@ ; } while ( ! LODWORD ( @@v18@@ [ Number ] ) && @@v18@@ [ Number ] == @@v15@@ + Number && ( @@v18@@ [ Number ] & Number ) != Number && ! LODWORD ( @@v18@@ [ Number ] ) && ( unsigned __int64 ) & gen_opc_buf + Number > gen_opc_ptr && ( unsigned __int64 ) ( @@v18@@ [ Number ] - @@v17@@ ) <= Number && @@v11@@ < @@v12@@ ) ; LABEL_37 : tcg_temp_free_i64 ( ( unsigned int ) cpu_addr ) ; tcg_temp_free_i64 ( ( unsigned int ) cpu_val ) ; tcg_temp_free_i64 ( ( unsigned int ) cpu_dst ) ; tcg_temp_free_i64 ( ( unsigned int ) cpu_tmp64 ) ; tcg_temp_free_i32 ( ( unsigned int ) cpu_tmp32 ) ; tcg_temp_free_i64 ( ( unsigned int ) cpu_tmp0 ) ; if ( * ( __int16 * ) ( @@a1@@ + Number ) < Number ) gen_io_end ( ) ; if ( ! LODWORD ( @@v18@@ [ Number ] ) ) { if ( @@v18@@ [ Number ] == Number || @@v18@@ [ Number ] == Number ) { if ( @@v18@@ [ Number ] != Number ) tcg_gen_movi_i64 ( cpu_pc , @@v18@@ [ Number ] ) ; save_npc ( @@v18@@ , cpu_cond ) ; tcg_gen_exit_tb ( Number L ) ; } else { gen_goto_tb ( ( __int64 ) @@v18@@ , Number , @@v18@@ [ Number ] , @@v18@@ [ Number ] ) ; } } gen_icount_end ( @@a1@@ , @@v11@@ ) ; * gen_opc_ptr = Number ; if ( @@a2@@ ) { v14 = ( __int64 ) ( gen_opc_ptr - ( _QWORD ) & gen_opc_buf ) >> Number ; for ( j = v9 + Number ; j <= v14 ; ++ j ) { v5 = j ; * ( ( _BYTE * ) & gen_opc_instr_start + v5 ) = Number ; } gen_opc_jump_pc = @@v18@@ [ Number ] ; qword_14F48 = @@v18@@ [ Number ] ; } else { * ( _WORD * ) ( @@a1@@ + Number ) = @@v15@@ - @@v17@@ + Number ; * ( _DWORD * ) ( @@a1@@ + Number ) = @@v11@@ ; } if ( ( loglevel & Number ) != Number ) { if ( logfile ) fwrite ( String , Number , Number , logfile ) ; if ( logfile ) { v6 = ( const char * ) lookup_symbol ( @@v17@@ ) ; fprintf ( logfile , String , v6 ) ; } target_disas ( logfile , @@v17@@ , @@v15@@ - @@v17@@ + Number , Number L ) ; if ( logfile ) fputc ( Number , logfile ) ; } return __readfsqword ( Number ) ^ @@v19@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"i\", \"t\": {\"T\": 3, \"t\": \"_QWORD\"}, \"location\": \"s112\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s120\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s128\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s132\"}, {\"n\": \"v19\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}, {\"n\": \"v18\", \"t\": {\"T\": 2, \"n\": 9, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s80\"}, {\"n\": \"v17\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s96\"}]}"
] |
{"name": "gen_intermediate_code_pc", "code": "unsigned __int64 __fastcall gen_intermediate_code_pc ( __int64 @@a1@@ , __int64 @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; gen_intermediate_code_internal ( @@a2@@ , Number , @@a1@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "env", "t": {"T": 3, "t": "CPUSPARCState_0"}, "location": "r56"}, {"n": "tb", "t": {"T": 3, "t": "TranslationBlock_0"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 322 |
[
"{\"name\": \"gen_intermediate_code_internal\", \"code\": \"unsigned __int64 __fastcall gen_intermediate_code_internal ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { _BOOL4 v3 ; int v4 ; int v5 ; const char * v6 ; int v9 ; int j ; int @@v11@@ ; int @@v12@@ ; int v13 ; int v14 ; __int64 @@v15@@ ; _QWORD * @@i@@ ; __int64 @@v17@@ ; __int64 @@v18@@ [ Number ] ; unsigned __int64 @@v19@@ ; @@v19@@ = __readfsqword ( Number ) ; v9 = Number ; memset ( @@v18@@ , Number , sizeof ( @@v18@@ ) ) ; @@v18@@ [ Number ] = @@a1@@ ; @@v17@@ = * ( _QWORD * ) @@a1@@ ; @@v18@@ [ Number ] = * ( _QWORD * ) @@a1@@ ; @@v15@@ = @@v18@@ [ Number ] ; @@v18@@ [ Number ] = * ( _QWORD * ) ( @@a1@@ + Number ) ; HIDWORD ( @@v18@@ [ Number ] ) = Number ; HIDWORD ( @@v18@@ [ Number ] ) = cpu_mmu_index ( @@a3@@ ) ; @@v18@@ [ Number ] = * ( _QWORD * ) ( @@a3@@ + Number ) ; if ( ( * ( _DWORD * ) ( @@v18@@ [ Number ] + Number ) & Number ) != Number ) LODWORD ( @@v18@@ [ Number ] ) = cpu_fpu_enabled ( @@a3@@ ) ; else LODWORD ( @@v18@@ [ Number ] ) = Number ; HIDWORD ( @@v18@@ [ Number ] ) = * ( _DWORD * ) ( @@a3@@ + Number ) & Number ; v3 = * ( _DWORD * ) ( @@a3@@ + Number ) || singlestep ; LODWORD ( @@v18@@ [ Number ] ) = v3 ; cpu_tmp0 = tcg_temp_new_i64 ( ) ; cpu_tmp32 = tcg_temp_new_i32 ( ) ; cpu_tmp64 = tcg_temp_new_i64 ( ) ; cpu_dst = tcg_temp_local_new_i64 ( ) ; cpu_val = tcg_temp_local_new_i64 ( ) ; cpu_addr = tcg_temp_local_new_i64 ( ) ; @@v11@@ = Number ; @@v12@@ = * ( _WORD * ) ( @@a1@@ + Number ) & Number ; if ( ( * ( _WORD * ) ( @@a1@@ + Number ) & Number ) == Number ) @@v12@@ = Number ; gen_icount_start ( ) ; do { if ( * ( _QWORD * ) ( @@a3@@ + Number ) ) { for ( @@i@@ = * ( _QWORD * * ) ( @@a3@@ + Number ) ; @@i@@ ; @@i@@ = ( _QWORD * ) @@i@@ [ Number ] ) { if ( * @@i@@ == @@v18@@ [ Number ] ) { if ( @@v17@@ != @@v18@@ [ Number ] ) save_state ( ( __int64 ) @@v18@@ , cpu_cond ) ; gen_helper_debug ( ) ; tcg_gen_exit_tb ( Number L ) ; LODWORD ( @@v18@@ [ Number ] ) = Number ; goto LABEL_37 ; } } } if ( @@a2@@ ) { if ( logfile ) fwrite ( String , Number , Number , logfile ) ; v13 = ( __int64 ) ( gen_opc_ptr - ( _QWORD ) & gen_opc_buf ) >> Number ; if ( v9 < v13 ) { ++ v9 ; while ( v9 < v13 ) { v4 = v9 ++ ; * ( ( _BYTE * ) & gen_opc_instr_start + v4 ) = Number ; } * ( ( _QWORD * ) & gen_opc_pc + v9 ) = @@v18@@ [ Number ] ; gen_opc_npc [ v9 ] = @@v18@@ [ Number ] ; * ( ( _BYTE * ) & gen_opc_instr_start + v9 ) = Number ; * ( ( _WORD * ) & gen_opc_icount + v9 ) = @@v11@@ ; } } if ( @@v12@@ == @@v11@@ + Number && * ( __int16 * ) ( @@a1@@ + Number ) < Number ) gen_io_start ( ) ; @@v15@@ = @@v18@@ [ Number ] ; disas_sparc_insn ( @@v18@@ ) ; ++ @@v11@@ ; } while ( ! LODWORD ( @@v18@@ [ Number ] ) && @@v18@@ [ Number ] == @@v15@@ + Number && ( @@v18@@ [ Number ] & Number ) != Number && ! LODWORD ( @@v18@@ [ Number ] ) && ( unsigned __int64 ) & gen_opc_buf + Number > gen_opc_ptr && ( unsigned __int64 ) ( @@v18@@ [ Number ] - @@v17@@ ) <= Number && @@v11@@ < @@v12@@ ) ; LABEL_37 : tcg_temp_free_i64 ( ( unsigned int ) cpu_addr ) ; tcg_temp_free_i64 ( ( unsigned int ) cpu_val ) ; tcg_temp_free_i64 ( ( unsigned int ) cpu_dst ) ; tcg_temp_free_i64 ( ( unsigned int ) cpu_tmp64 ) ; tcg_temp_free_i32 ( ( unsigned int ) cpu_tmp32 ) ; tcg_temp_free_i64 ( ( unsigned int ) cpu_tmp0 ) ; if ( * ( __int16 * ) ( @@a1@@ + Number ) < Number ) gen_io_end ( ) ; if ( ! LODWORD ( @@v18@@ [ Number ] ) ) { if ( @@v18@@ [ Number ] == Number || @@v18@@ [ Number ] == Number ) { if ( @@v18@@ [ Number ] != Number ) tcg_gen_movi_i64 ( cpu_pc , @@v18@@ [ Number ] ) ; save_npc ( @@v18@@ , cpu_cond ) ; tcg_gen_exit_tb ( Number L ) ; } else { gen_goto_tb ( ( __int64 ) @@v18@@ , Number , @@v18@@ [ Number ] , @@v18@@ [ Number ] ) ; } } gen_icount_end ( @@a1@@ , @@v11@@ ) ; * gen_opc_ptr = Number ; if ( @@a2@@ ) { v14 = ( __int64 ) ( gen_opc_ptr - ( _QWORD ) & gen_opc_buf ) >> Number ; for ( j = v9 + Number ; j <= v14 ; ++ j ) { v5 = j ; * ( ( _BYTE * ) & gen_opc_instr_start + v5 ) = Number ; } gen_opc_jump_pc = @@v18@@ [ Number ] ; qword_14F48 = @@v18@@ [ Number ] ; } else { * ( _WORD * ) ( @@a1@@ + Number ) = @@v15@@ - @@v17@@ + Number ; * ( _DWORD * ) ( @@a1@@ + Number ) = @@v11@@ ; } if ( ( loglevel & Number ) != Number ) { if ( logfile ) fwrite ( String , Number , Number , logfile ) ; if ( logfile ) { v6 = ( const char * ) lookup_symbol ( @@v17@@ ) ; fprintf ( logfile , String , v6 ) ; } target_disas ( logfile , @@v17@@ , @@v15@@ - @@v17@@ + Number , Number L ) ; if ( logfile ) fputc ( Number , logfile ) ; } return __readfsqword ( Number ) ^ @@v19@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"i\", \"t\": {\"T\": 3, \"t\": \"_QWORD\"}, \"location\": \"s112\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s120\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s128\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s132\"}, {\"n\": \"v19\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}, {\"n\": \"v18\", \"t\": {\"T\": 2, \"n\": 9, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s80\"}, {\"n\": \"v17\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s96\"}]}",
"{\"name\": \"gen_intermediate_code\", \"code\": \"unsigned __int64 __fastcall gen_intermediate_code ( __int64 @@a1@@ , __int64 @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; gen_intermediate_code_internal ( @@a2@@ , Number , @@a1@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_intermediate_code_init", "code": "unsigned __int64 gen_intermediate_code_init ( ) { unsigned int i ; unsigned int j ; unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; if ( ! inited_10511 ) { inited_10511 = Number ; cpu_env = tcg_global_reg_new_i64 ( Number L , String ) ; cpu_regwptr = tcg_global_mem_new_i64 ( Number L , Number L , String ) ; cpu_xcc = tcg_global_mem_new_i32 ( Number L , Number L , String ) ; cpu_asi = tcg_global_mem_new_i32 ( Number L , Number L , String ) ; cpu_fprs = tcg_global_mem_new_i32 ( Number L , Number L , String ) ; cpu_gsr = tcg_global_mem_new_i64 ( Number L , Number L , String ) ; cpu_tick_cmpr = tcg_global_mem_new_i64 ( Number L , Number L , String ) ; cpu_stick_cmpr = tcg_global_mem_new_i64 ( Number L , Number L , String ) ; cpu_hstick_cmpr = tcg_global_mem_new_i64 ( Number L , Number L , String ) ; cpu_hintp = tcg_global_mem_new_i64 ( Number L , Number L , String ) ; cpu_htba = tcg_global_mem_new_i64 ( Number L , Number L , String ) ; cpu_hver = tcg_global_mem_new_i64 ( Number L , Number L , String ) ; cpu_ssr = tcg_global_mem_new_i64 ( Number L , Number L , String ) ; cpu_ver = tcg_global_mem_new_i64 ( Number L , Number L , String ) ; cpu_softint = tcg_global_mem_new_i32 ( Number L , Number L , String ) ; cpu_cond = tcg_global_mem_new_i64 ( Number L , Number L , String ) ; cpu_cc_src = tcg_global_mem_new_i64 ( Number L , Number L , String ) ; cpu_cc_src2 = tcg_global_mem_new_i64 ( Number L , Number L , String ) ; cpu_cc_dst = tcg_global_mem_new_i64 ( Number L , Number L , String ) ; cpu_cc_op = tcg_global_mem_new_i32 ( Number L , Number L , String ) ; cpu_psr = tcg_global_mem_new_i32 ( Number L , Number L , String ) ; cpu_fsr = tcg_global_mem_new_i64 ( Number L , Number L , String ) ; cpu_pc = tcg_global_mem_new_i64 ( Number L , Number L , String ) ; cpu_npc = tcg_global_mem_new_i64 ( Number L , Number L , String ) ; cpu_y = tcg_global_mem_new_i64 ( Number L , Number L , String ) ; for ( i = Number ; i <= Number ; ++ i ) cpu_gregs [ i ] = tcg_global_mem_new_i64 ( Number L , Number L * i , gregnames_10512 [ i ] ) ; for ( j = Number ; j <= Number ; ++ j ) cpu_fpr [ j ] = tcg_global_mem_new_i32 ( Number L , Number * ( j + Number L ) , * ( & fregnames_10513 + j ) ) ; tcg_register_helper ( & helper_wrpil , String ) ; tcg_register_helper ( & helper_wrpstate , String ) ; tcg_register_helper ( & helper_done , String ) ; tcg_register_helper ( & helper_retry , String ) ; tcg_register_helper ( & helper_flushw , String ) ; tcg_register_helper ( & helper_saved , String ) ; tcg_register_helper ( & helper_restored , String ) ; tcg_register_helper ( & helper_rdccr , String ) ; tcg_register_helper ( & helper_wrccr , String ) ; tcg_register_helper ( & helper_rdcwp , String ) ; tcg_register_helper ( & helper_wrcwp , String ) ; tcg_register_helper ( & helper_array8 , String ) ; tcg_register_helper ( & helper_alignaddr , String ) ; tcg_register_helper ( & helper_popc , String ) ; tcg_register_helper ( & helper_ldda_asi , String ) ; tcg_register_helper ( & helper_ldf_asi , String ) ; tcg_register_helper ( & helper_stf_asi , String ) ; tcg_register_helper ( & helper_cas_asi , String ) ; tcg_register_helper ( & helper_casx_asi , String ) ; tcg_register_helper ( & helper_set_softint , String ) ; tcg_register_helper ( & helper_clear_softint , String ) ; tcg_register_helper ( & helper_write_softint , String ) ; tcg_register_helper ( & helper_tick_set_count , String ) ; tcg_register_helper ( & helper_tick_get_count , String ) ; tcg_register_helper ( & helper_tick_set_limit , String ) ; tcg_register_helper ( & helper_check_align , String ) ; tcg_register_helper ( & helper_debug , String ) ; tcg_register_helper ( & helper_save , String ) ; tcg_register_helper ( & helper_restore , String ) ; tcg_register_helper ( & helper_flush , String ) ; tcg_register_helper ( & helper_udiv , String ) ; tcg_register_helper ( & helper_sdiv , String ) ; tcg_register_helper ( & helper_stdf , String ) ; tcg_register_helper ( & helper_lddf , String ) ; tcg_register_helper ( & helper_ldqf , String ) ; tcg_register_helper ( & helper_stqf , String ) ; tcg_register_helper ( & helper_ld_asi , String ) ; tcg_register_helper ( & helper_st_asi , String ) ; tcg_register_helper ( & helper_ldfsr , String ) ; tcg_register_helper ( & helper_check_ieee_exceptions , String ) ; tcg_register_helper ( & helper_clear_float_exceptions , String ) ; tcg_register_helper ( & helper_fabss , String ) ; tcg_register_helper ( & helper_fsqrts , String ) ; tcg_register_helper ( & helper_fsqrtd , String ) ; tcg_register_helper ( & helper_fcmps , String ) ; tcg_register_helper ( & helper_fcmpd , String ) ; tcg_register_helper ( & helper_fcmpes , String ) ; tcg_register_helper ( & helper_fcmped , String ) ; tcg_register_helper ( & helper_fsqrtq , String ) ; tcg_register_helper ( & helper_fcmpq , String ) ; tcg_register_helper ( & helper_fcmpeq , String ) ; tcg_register_helper ( & helper_ldxfsr , String ) ; tcg_register_helper ( & helper_fabsd , String ) ; tcg_register_helper ( & helper_fcmps_fcc1 , String ) ; tcg_register_helper ( & helper_fcmps_fcc2 , String ) ; tcg_register_helper ( & helper_fcmps_fcc3 , String ) ; tcg_register_helper ( & helper_fcmpd_fcc1 , String ) ; tcg_register_helper ( & helper_fcmpd_fcc2 , String ) ; tcg_register_helper ( & helper_fcmpd_fcc3 , String ) ; tcg_register_helper ( & helper_fcmpes_fcc1 , String ) ; tcg_register_helper ( & helper_fcmpes_fcc2 , String ) ; tcg_register_helper ( & helper_fcmpes_fcc3 , String ) ; tcg_register_helper ( & helper_fcmped_fcc1 , String ) ; tcg_register_helper ( & helper_fcmped_fcc2 , String ) ; tcg_register_helper ( & helper_fcmped_fcc3 , String ) ; tcg_register_helper ( & helper_fabsq , String ) ; tcg_register_helper ( & helper_fcmpq_fcc1 , String ) ; tcg_register_helper ( & helper_fcmpq_fcc2 , String ) ; tcg_register_helper ( & helper_fcmpq_fcc3 , String ) ; tcg_register_helper ( & helper_fcmpeq_fcc1 , String ) ; tcg_register_helper ( & helper_fcmpeq_fcc2 , String ) ; tcg_register_helper ( & helper_fcmpeq_fcc3 , String ) ; tcg_register_helper ( & helper_raise_exception , String ) ; tcg_register_helper ( & helper_faddd , String ) ; tcg_register_helper ( & helper_faddq , String ) ; tcg_register_helper ( & helper_fsubd , String ) ; tcg_register_helper ( & helper_fsubq , String ) ; tcg_register_helper ( & helper_fmuld , String ) ; tcg_register_helper ( & helper_fmulq , String ) ; tcg_register_helper ( & helper_fdivd , String ) ; tcg_register_helper ( & helper_fdivq , String ) ; tcg_register_helper ( & helper_fadds , String ) ; tcg_register_helper ( & helper_fsubs , String ) ; tcg_register_helper ( & helper_fmuls , String ) ; tcg_register_helper ( & helper_fdivs , String ) ; tcg_register_helper ( & helper_fsmuld , String ) ; tcg_register_helper ( & helper_fdmulq , String ) ; tcg_register_helper ( & helper_fnegs , String ) ; tcg_register_helper ( & helper_fitod , String ) ; tcg_register_helper ( & helper_fitoq , String ) ; tcg_register_helper ( & helper_fitos , String ) ; tcg_register_helper ( & helper_fnegd , String ) ; tcg_register_helper ( & helper_fnegq , String ) ; tcg_register_helper ( & helper_fxtos , String ) ; tcg_register_helper ( & helper_fxtod , String ) ; tcg_register_helper ( & helper_fxtoq , String ) ; tcg_register_helper ( & helper_fdtos , String ) ; tcg_register_helper ( & helper_fstod , String ) ; tcg_register_helper ( & helper_fqtos , String ) ; tcg_register_helper ( & helper_fstoq , String ) ; tcg_register_helper ( & helper_fqtod , String ) ; tcg_register_helper ( & helper_fdtoq , String ) ; tcg_register_helper ( & helper_fstoi , String ) ; tcg_register_helper ( & helper_fdtoi , String ) ; tcg_register_helper ( & helper_fqtoi , String ) ; tcg_register_helper ( & helper_fstox , String ) ; tcg_register_helper ( & helper_fdtox , String ) ; tcg_register_helper ( & helper_fqtox , String ) ; tcg_register_helper ( & helper_faligndata , String ) ; tcg_register_helper ( & helper_fpmerge , String ) ; tcg_register_helper ( & helper_fmul8x16 , String ) ; tcg_register_helper ( & helper_fmul8x16al , String ) ; tcg_register_helper ( & helper_fmul8x16au , String ) ; tcg_register_helper ( & helper_fmul8sux16 , String ) ; tcg_register_helper ( & helper_fmul8ulx16 , String ) ; tcg_register_helper ( & helper_fmuld8sux16 , String ) ; tcg_register_helper ( & helper_fmuld8ulx16 , String ) ; tcg_register_helper ( & helper_fexpand , String ) ; tcg_register_helper ( & helper_fpadd16 , String ) ; tcg_register_helper ( & helper_fpadd16s , String ) ; tcg_register_helper ( & helper_fpadd32 , String ) ; tcg_register_helper ( & helper_fpadd32s , String ) ; tcg_register_helper ( & helper_fpsub16 , String ) ; tcg_register_helper ( & helper_fpsub16s , String ) ; tcg_register_helper ( & helper_fpsub32 , String ) ; tcg_register_helper ( & helper_fpsub32s , String ) ; tcg_register_helper ( & helper_fcmpgt16 , String ) ; tcg_register_helper ( & helper_fcmpgt32 , String ) ; tcg_register_helper ( & helper_fcmpeq16 , String ) ; tcg_register_helper ( & helper_fcmpeq32 , String ) ; tcg_register_helper ( & helper_fcmple16 , String ) ; tcg_register_helper ( & helper_fcmple32 , String ) ; tcg_register_helper ( & helper_fcmpne16 , String ) ; tcg_register_helper ( & helper_fcmpne32 , String ) ; tcg_register_helper ( & helper_compute_psr , String ) ; tcg_register_helper ( & helper_compute_C_icc , String ) ; } return __readfsqword ( Number ) ^ @@v3@@ ; }", "source": [{"n": "v3", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 323 |
[
"{\"name\": \"gen_intermediate_code\", \"code\": \"unsigned __int64 __fastcall gen_intermediate_code ( __int64 @@a1@@ , __int64 @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; gen_intermediate_code_internal ( @@a2@@ , Number , @@a1@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_pc_load", "code": "unsigned __int64 __fastcall gen_pc_load ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { __int64 @@v5@@ ; unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; * ( _QWORD * ) ( @@a1@@ + Number ) = * ( ( _QWORD * ) & gen_opc_pc + @@a4@@ ) ; @@v5@@ = gen_opc_npc [ @@a4@@ ] ; if ( @@v5@@ != Number ) { if ( @@v5@@ == Number ) { if ( * ( _QWORD * ) ( @@a1@@ + Number ) ) * ( _QWORD * ) ( @@a1@@ + Number ) = gen_opc_jump_pc ; else * ( _QWORD * ) ( @@a1@@ + Number ) = qword_14F48 ; } else { * ( _QWORD * ) ( @@a1@@ + Number ) = @@v5@@ ; } } if ( * ( _DWORD * ) ( @@a1@@ + Number ) != Number ) helper_compute_psr ( ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v6", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "searched_pc", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "r16"}, {"n": "pc_pos", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "env", "t": {"T": 3, "t": "CPUSPARCState"}, "location": "r56"}, {"n": "tb", "t": {"T": 3, "t": "TranslationBlock_0"}, "location": "r64"}, {"n": "npc", "t": {"T": 1, "n": "target_ulong", "s": 8}, "location": "s16"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc_574048dcc2d88da254c1bd1dfa5e27bb24b691454eaceee0aa3c363223312bdc.jsonl
| 324 |
[] |
{"name": "scnprintf", "code": "__int64 scnprintf ( char * @@a1@@ , signed __int64 @@a2@@ , const char * @@a3@@ , __int64 @@a4@@ , __int64 @@a5@@ , __int64 @@a6@@ , ... ) { __int64 @@result@@ ; int @@v7@@ ; gcc_va_list @@arg@@ ; unsigned __int64 @@v9@@ ; __int64 @@v10@@ ; __int64 @@v11@@ ; __int64 @@v12@@ ; va_start ( @@arg@@ , @@a6@@ ) ; @@v10@@ = @@a4@@ ; @@v11@@ = @@a5@@ ; @@v12@@ = @@a6@@ ; @@v9@@ = __readfsqword ( Number ) ; @@arg@@ [ Number ] . gp_offset = Number ; @@v7@@ = vsnprintf ( @@a1@@ , @@a2@@ , @@a3@@ , @@arg@@ ) ; if ( @@a2@@ > @@v7@@ ) @@result@@ = ( unsigned int ) @@v7@@ ; else @@result@@ = ( unsigned int ) ( @@a2@@ - Number ) ; return @@result@@ ; }", "source": [{"n": "a3", "t": {"T": 3, "t": "const char"}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r24"}, {"n": "a1", "t": {"T": 3, "t": "char"}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "signed __int64", "s": 8}, "location": "r64"}, {"n": "a5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r72"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}, {"n": "a6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r80"}, {"n": "v12", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s136"}, {"n": "v11", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s144"}, {"n": "v10", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s152"}, {"n": "v9", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s184"}, {"n": "arg", "t": {"T": 2, "n": 1, "s": 24, "t": "__va_list_tag"}, "location": "s208"}, {"n": "v7", "t": {"T": 1, "n": "int", "s": 4}, "location": "s220"}]}
|
[{"n": "fmt", "t": {"T": 3, "t": "const char"}, "location": "r16"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r24"}, {"n": "buf", "t": {"T": 3, "t": "char"}, "location": "r56"}, {"n": "size", "t": {"T": 1, "n": "size_t", "s": 8}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r72"}, {"n": "result", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r80"}, {"n": "v12", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s136"}, {"n": "v11", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s144"}, {"n": "v10", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s152"}, {"n": "v9", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s184"}, {"n": "args", "t": {"T": 2, "n": 1, "s": 24, "t": "__va_list_tag"}, "location": "s208"}, {"n": "i", "t": {"T": 1, "n": "int", "s": 4}, "location": "s220"}]
|
data1/train-shard-10.tar
|
077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f_077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f.jsonl
| 0 |
[] |
{"name": "zalloc", "code": "void * __fastcall zalloc ( size_t @@a1@@ ) { return calloc ( Number , @@a1@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "size_t", "s": 8}, "location": "r56"}]}
|
[{"n": "size", "t": {"T": 1, "n": "size_t", "s": 8}, "location": "r56"}]
|
data1/train-shard-10.tar
|
077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f_077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f.jsonl
| 1 |
[] |
{"name": "__list_del", "code": "unsigned __int64 __fastcall _list_del ( _QWORD * @@a1@@ , __int64 @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; * ( _QWORD * ) ( @@a2@@ + Number ) = @@a1@@ ; * @@a1@@ = @@a2@@ ; return __readfsqword ( Number ) ^ @@v3@@ ; }", "source": [{"n": "a1", "t": {"T": 3, "t": "_QWORD"}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "prev", "t": {"T": 3, "t": "list_head"}, "location": "r56"}, {"n": "next", "t": {"T": 3, "t": "list_head"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f_077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f.jsonl
| 2 |
[
"{\"name\": \"list_del\", \"code\": \"unsigned __int64 __fastcall list_del ( __int64 @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; _list_del ( * ( _QWORD * * ) ( @@a1@@ + Number ) , * ( _QWORD * ) @@a1@@ ) ; * ( _QWORD * ) @@a1@@ = Number L ; * ( _QWORD * ) ( @@a1@@ + Number ) = Number L ; return __readfsqword ( Number ) ^ @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "list_del", "code": "unsigned __int64 __fastcall list_del ( __int64 @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; _list_del ( * ( _QWORD * * ) ( @@a1@@ + Number ) , * ( _QWORD * ) @@a1@@ ) ; * ( _QWORD * ) @@a1@@ = Number L ; * ( _QWORD * ) ( @@a1@@ + Number ) = Number L ; return __readfsqword ( Number ) ^ @@v2@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "v2", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "entry", "t": {"T": 3, "t": "list_head"}, "location": "r56"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f_077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f.jsonl
| 3 |
[] |
{"name": "rb_link_node", "code": "unsigned __int64 __fastcall rb_link_node ( _QWORD * @@a1@@ , __int64 @@a2@@ , _QWORD * @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; * @@a1@@ = @@a2@@ ; @@a1@@ [ Number ] = Number L ; @@a1@@ [ Number ] = @@a1@@ [ Number ] ; * @@a3@@ = @@a1@@ ; return __readfsqword ( Number ) ^ @@v4@@ ; }", "source": [{"n": "a3", "t": {"T": 3, "t": "_QWORD"}, "location": "r16"}, {"n": "a1", "t": {"T": 3, "t": "_QWORD"}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "rb_link", "t": {"T": 3, "t": "rb_node *"}, "location": "r16"}, {"n": "node", "t": {"T": 3, "t": "rb_node"}, "location": "r56"}, {"n": "parent", "t": {"T": 3, "t": "rb_node"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-10.tar
|
077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f_077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f.jsonl
| 4 |
[] |
{"name": "symbol__size", "code": "__int64 __fastcall symbol__size ( __int64 @@a1@@ ) { return * ( _QWORD * ) ( @@a1@@ + Number ) - * ( _QWORD * ) ( @@a1@@ + Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}]}
|
[{"n": "sym", "t": {"T": 3, "t": "const symbol"}, "location": "r56"}]
|
data1/train-shard-10.tar
|
077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f_077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f.jsonl
| 5 |
[] |
{"name": "perf_evsel__is_group_leader", "code": "bool __fastcall perf_evsel__is_group_leader ( __int64 @@a1@@ ) { return @@a1@@ == * ( _QWORD * ) ( @@a1@@ + Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}]}
|
[{"n": "evsel", "t": {"T": 3, "t": "const perf_evsel"}, "location": "r56"}]
|
data1/train-shard-10.tar
|
077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f_077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f.jsonl
| 6 |
[] |
{"name": "perf_evsel__is_group_event", "code": "_BOOL8 __fastcall perf_evsel__is_group_event ( __int64 @@a1@@ ) { if ( symbol_conf [ Number ] != Number ) return Number L ; return perf_evsel__is_group_leader ( @@a1@@ ) && * ( int * ) ( @@a1@@ + Number ) > Number ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}]}
|
[{"n": "evsel", "t": {"T": 3, "t": "perf_evsel"}, "location": "r56"}]
|
data1/train-shard-10.tar
|
077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f_077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f.jsonl
| 7 |
[
"{\"name\": \"perf_evsel__is_group_leader\", \"code\": \"bool __fastcall perf_evsel__is_group_leader ( __int64 @@a1@@ ) { return @@a1@@ == * ( _QWORD * ) ( @@a1@@ + Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}"
] |
{"name": "disasm_line__has_offset", "code": "bool __fastcall disasm_line__has_offset ( __int64 @@a1@@ ) { return * ( _QWORD * ) ( @@a1@@ + Number ) != Number ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}]}
|
[{"n": "dl_0", "t": {"T": 3, "t": "const disasm_line"}, "location": "r56"}]
|
data1/train-shard-10.tar
|
077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f_077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f.jsonl
| 8 |
[] |
{"name": "symbol__annotation", "code": "__int64 __fastcall symbol__annotation ( __int64 @@a1@@ ) { return @@a1@@ - Number ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}]}
|
[{"n": "sym", "t": {"T": 3, "t": "symbol"}, "location": "r56"}]
|
data1/train-shard-10.tar
|
077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f_077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f.jsonl
| 9 |
[] |
{"name": "disasm_line__browser", "code": "__int64 __fastcall disasm_line__browser ( __int64 @@a1@@ ) { return @@a1@@ + Number ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}]}
|
[{"n": "dl_0", "t": {"T": 3, "t": "disasm_line"}, "location": "r56"}]
|
data1/train-shard-10.tar
|
077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f_077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f.jsonl
| 10 |
[] |
{"name": "disasm_line__filter", "code": "bool __fastcall disasm_line__filter ( __int64 @@a1@@ , __int64 @@a2@@ ) { bool @@result@@ ; if ( annotate_browser__opts ) @@result@@ = * ( _QWORD * ) ( @@a2@@ + Number ) == Number ; else @@result@@ = Number ; return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}]}
|
[{"n": "browser", "t": {"T": 3, "t": "ui_browser"}, "location": "r56"}, {"n": "entry", "t": {"T": 3, "t": "void"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}]
|
data1/train-shard-10.tar
|
077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f_077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f.jsonl
| 11 |
[] |
{"name": "annotate_browser__jumps_percent_color", "code": "__int64 __fastcall annotate_browser__jumps_percent_color ( __int64 @@a1@@ , int @@a2@@ , char @@a3@@ ) { if ( @@a3@@ && ( * ( _BYTE * ) ( @@a1@@ + Number ) != Number || * ( _BYTE * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@a2@@ == * ( _DWORD * ) ( @@a1@@ + Number ) ) return Number L ; if ( @@a2@@ <= Number ) return Number L ; return Number L ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "char", "s": 1}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}]}
|
[{"n": "current", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r16"}, {"n": "browser", "t": {"T": 3, "t": "annotate_browser"}, "location": "r56"}, {"n": "nr", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}]
|
data1/train-shard-10.tar
|
077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f_077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f.jsonl
| 12 |
[
"{\"name\": \"annotate_browser__jump\", \"code\": \"__int64 __fastcall annotate_browser__jump ( __int64 @@a1@@ ) { __int64 @@v2@@ ; _QWORD * @@v3@@ ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ = * ( _QWORD * * ) ( @@a1@@ + Number ) ; if ( ( unsigned __int8 ) ins__is_jump ( @@v3@@ [ Number ] ) != Number ) return Number L ; @@v3@@ = annotate_browser__find_offset ( @@a1@@ , @@v3@@ [ Number ] , & @@v2@@ ) ; if ( @@v3@@ ) annotate_browser__set_top ( @@a1@@ , ( __int64 ) @@v3@@ , @@v2@@ ) ; else ui_helpline__puts ( String ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v3\", \"t\": {\"T\": 3, \"t\": \"_QWORD\"}, \"location\": \"s16\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "annotate_browser__set_jumps_percent_color", "code": "__int64 __fastcall annotate_browser__set_jumps_percent_color ( __int64 @@a1@@ , int @@a2@@ , char @@a3@@ ) { unsigned int @@v3@@ ; @@v3@@ = annotate_browser__jumps_percent_color ( @@a1@@ , @@a2@@ , @@a3@@ ) ; return ui_browser__set_color ( @@a1@@ , @@v3@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "char", "s": 1}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r8"}]}
|
[{"n": "current", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r16"}, {"n": "browser", "t": {"T": 3, "t": "annotate_browser"}, "location": "r56"}, {"n": "nr", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-10.tar
|
077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f_077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f.jsonl
| 13 |
[
"{\"name\": \"annotate_browser__jumps_percent_color\", \"code\": \"__int64 __fastcall annotate_browser__jumps_percent_color ( __int64 @@a1@@ , int @@a2@@ , char @@a3@@ ) { if ( @@a3@@ && ( * ( _BYTE * ) ( @@a1@@ + Number ) != Number || * ( _BYTE * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@a2@@ == * ( _DWORD * ) ( @@a1@@ + Number ) ) return Number L ; if ( @@a2@@ <= Number ) return Number L ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"annotate_browser__jump\", \"code\": \"__int64 __fastcall annotate_browser__jump ( __int64 @@a1@@ ) { __int64 @@v2@@ ; _QWORD * @@v3@@ ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ = * ( _QWORD * * ) ( @@a1@@ + Number ) ; if ( ( unsigned __int8 ) ins__is_jump ( @@v3@@ [ Number ] ) != Number ) return Number L ; @@v3@@ = annotate_browser__find_offset ( @@a1@@ , @@v3@@ [ Number ] , & @@v2@@ ) ; if ( @@v3@@ ) annotate_browser__set_top ( @@a1@@ , ( __int64 ) @@v3@@ , @@v2@@ ) ; else ui_helpline__puts ( String ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v3\", \"t\": {\"T\": 3, \"t\": \"_QWORD\"}, \"location\": \"s16\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "annotate_browser__write", "code": "unsigned __int64 __fastcall annotate_browser__write ( __int64 @@a1@@ , __int64 @@a2@@ , unsigned int @@a3@@ ) { bool @@v3@@ ; __int64 @@v4@@ ; __int64 @@v5@@ ; unsigned int v6 ; unsigned __int8 @@v9@@ ; bool @@v10@@ ; int @@v11@@ ; unsigned int v12 ; unsigned int v13 ; unsigned int v14 ; int i ; int j ; unsigned int @@v17@@ ; unsigned int @@v18@@ ; unsigned int @@v19@@ ; double @@v20@@ ; __int64 @@v21@@ ; __int64 @@v22@@ ; char @@v23@@ [ Number ] ; unsigned __int64 @@v24@@ ; @@v24@@ = __readfsqword ( Number ) ; @@v22@@ = disasm_line__browser ( @@a2@@ ) ; @@v9@@ = ui_browser__is_current_entry ( @@a1@@ , @@a3@@ ) ; @@v3@@ = annotate_browser__opts != Number && ( @@v9@@ != Number || * ( _BYTE * ) ( @@a1@@ + Number ) && * ( _BYTE * ) ( @@a1@@ + Number ) != Number ) ; @@v10@@ = @@v3@@ ; @@v11@@ = * ( unsigned __int16 * ) ( @@a1@@ + Number ) ; @@v18@@ = Number * * ( _DWORD * ) ( @@a1@@ + Number ) ; @@v20@@ = Number ; for ( i = Number ; i < * ( _DWORD * ) ( @@a1@@ + Number ) ; ++ i ) { if ( * ( double * ) ( @@v22@@ + Number * ( i + Number L ) + Number ) > @@v20@@ ) @@v20@@ = * ( double * ) ( @@v22@@ + Number * ( i + Number L ) + Number ) ; } if ( * ( _QWORD * ) ( @@a2@@ + Number ) == Number || @@v20@@ == Number ) { ui_browser__set_percent_color ( @@a1@@ , @@v9@@ , Number ) ; SLsmg_write_nstring ( String , @@v18@@ ) ; } else { for ( j = Number ; j < * ( _DWORD * ) ( @@a1@@ + Number ) ; ++ j ) { ui_browser__set_percent_color ( @@a1@@ , @@v9@@ , * ( double * ) ( @@v22@@ + Number * ( j + Number L ) + Number ) ) ; SLsmg_printf ( String , * ( double * ) ( @@v22@@ + Number * ( j + Number L ) + Number ) ) ; } } SLsmg_write_char ( Number L ) ; if ( * ( _BYTE * ) ( @@a1@@ + Number ) != Number ) ++ @@v11@@ ; if ( ! * * ( _BYTE * * ) ( @@a2@@ + Number ) ) { SLsmg_write_nstring ( String , @@v11@@ - @@v18@@ ) ; goto LABEL_52 ; } if ( * ( _QWORD * ) ( @@a2@@ + Number ) == Number ) { v12 = scnprintf ( @@v23@@ , Number L , String , * ( unsigned __int8 * ) ( @@a1@@ + Number ) , ( __int64 ) String , @@v5@@ ) ; SLsmg_write_nstring ( @@v23@@ , v12 ) ; SLsmg_write_nstring ( * ( _QWORD * ) ( @@a2@@ + Number ) , @@v11@@ - v12 - @@v18@@ + Number ) ; goto LABEL_52 ; } @@v21@@ = * ( _QWORD * ) ( @@a2@@ + Number ) ; @@v17@@ = Number ; if ( byte_3101 != Number ) @@v21@@ += * ( _QWORD * ) ( @@a1@@ + Number ) ; if ( byte_3101 != Number ) { v13 = scnprintf ( @@v23@@ , Number L , String , @@v21@@ , @@v4@@ , @@v5@@ ) ; } else if ( * ( _DWORD * ) ( @@v22@@ + Number ) ) { if ( byte_3103 ) { v14 = scnprintf ( @@v23@@ , Number L , String , * ( unsigned __int8 * ) ( @@a1@@ + Number ) , * ( unsigned int * ) ( @@v22@@ + Number ) , @@v5@@ ) ; @@v19@@ = annotate_browser__set_jumps_percent_color ( @@a1@@ , * ( _DWORD * ) ( @@v22@@ + Number ) , @@v9@@ ) ; SLsmg_write_nstring ( @@v23@@ , v14 ) ; ui_browser__set_color ( @@a1@@ , @@v19@@ ) ; } v13 = scnprintf ( @@v23@@ , Number L , String , * ( unsigned __int8 * ) ( @@a1@@ + Number ) , @@v21@@ , @@v5@@ ) ; } else { v13 = scnprintf ( @@v23@@ , Number L , String , * ( unsigned __int8 * ) ( @@a1@@ + Number ) , ( __int64 ) String , @@v5@@ ) ; } if ( @@v10@@ ) @@v17@@ = ui_browser__set_color ( @@a1@@ , Number L ) ; SLsmg_write_nstring ( @@v23@@ , v13 ) ; if ( @@v10@@ ) ui_browser__set_color ( @@a1@@ , @@v17@@ ) ; if ( ! * ( _QWORD * ) ( @@a2@@ + Number ) || ! * ( _QWORD * ) ( * ( _QWORD * ) ( * ( _QWORD * ) ( @@a2@@ + Number ) + Number L ) + Number L ) ) { if ( ! strcmp ( * ( const char * * ) ( @@a2@@ + Number ) , String ) ) { ui_browser__write_graph ( @@a1@@ , Number L ) ; SLsmg_write_char ( Number L ) ; goto LABEL_51 ; } goto LABEL_49 ; } if ( ( unsigned __int8 ) ins__is_jump ( * ( _QWORD * ) ( @@a2@@ + Number ) ) ) { if ( * ( _QWORD * ) ( @@a2@@ + Number ) <= * ( _QWORD * ) ( @@a2@@ + Number ) ) v6 = Number ; else v6 = Number ; ui_browser__write_graph ( @@a1@@ , v6 ) ; SLsmg_write_char ( Number L ) ; goto LABEL_51 ; } if ( ! ( unsigned __int8 ) ins__is_call ( * ( _QWORD * ) ( @@a2@@ + Number ) ) ) { LABEL_49 : SLsmg_write_nstring ( String , Number L ) ; goto LABEL_51 ; } ui_browser__write_graph ( @@a1@@ , Number L ) ; SLsmg_write_char ( Number L ) ; LABEL_51 : disasm_line__scnprintf ( @@a2@@ , @@v23@@ , Number L , byte_3101 == Number ) ; SLsmg_write_nstring ( @@v23@@ , @@v11@@ - @@v18@@ - Number - v13 ) ; LABEL_52 : if ( @@v9@@ ) * ( _QWORD * ) ( @@a1@@ + Number ) = @@a2@@ ; return __readfsqword ( Number ) ^ @@v24@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r72"}, {"n": "v3", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r80"}, {"n": "v23", "t": {"T": 2, "n": 264, "s": 1, "t": "char"}, "location": "s272"}, {"n": "v22", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s280"}, {"n": "v21", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s320"}, {"n": "v20", "t": {"T": 1, "n": "double", "s": 8}, "location": "s328"}, {"n": "v19", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s332"}, {"n": "v18", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s336"}, {"n": "v17", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s340"}, {"n": "v11", "t": {"T": 1, "n": "int", "s": 4}, "location": "s352"}, {"n": "v10", "t": {"T": 1, "n": "bool", "s": 1}, "location": "s354"}, {"n": "v9", "t": {"T": 1, "n": "unsigned __int8", "s": 1}, "location": "s355"}, {"n": "v24", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "row", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "browser", "t": {"T": 3, "t": "ui_browser"}, "location": "r56"}, {"n": "entry", "t": {"T": 3, "t": "void"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r72"}, {"n": "v3", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}, {"n": "", "t": {"T": 10}, "location": "r80"}, {"n": "bf", "t": {"T": 2, "n": 256, "s": 1, "t": "char"}, "location": "s272"}, {"n": "bdl", "t": {"T": 3, "t": "browser_disasm_line"}, "location": "s280"}, {"n": "addr", "t": {"T": 1, "n": "u64", "s": 8}, "location": "s320"}, {"n": "percent_max", "t": {"T": 1, "n": "double", "s": 8}, "location": "s328"}, {"n": "prev", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s332"}, {"n": "pcnt_width", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s336"}, {"n": "color", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s340"}, {"n": "width", "t": {"T": 1, "n": "int", "s": 4}, "location": "s352"}, {"n": "change_color", "t": {"T": 1, "n": "bool", "s": 1}, "location": "s354"}, {"n": "current_entry", "t": {"T": 1, "n": "unsigned __int8", "s": 1}, "location": "s355"}, {"n": "v21", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]
|
data1/train-shard-10.tar
|
077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f_077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f.jsonl
| 14 |
[
"{\"name\": \"scnprintf\", \"code\": \"__int64 scnprintf ( char * @@a1@@ , signed __int64 @@a2@@ , const char * @@a3@@ , __int64 @@a4@@ , __int64 @@a5@@ , __int64 @@a6@@ , ... ) { __int64 @@result@@ ; int @@v7@@ ; gcc_va_list @@arg@@ ; unsigned __int64 @@v9@@ ; __int64 @@v10@@ ; __int64 @@v11@@ ; __int64 @@v12@@ ; va_start ( @@arg@@ , @@a6@@ ) ; @@v10@@ = @@a4@@ ; @@v11@@ = @@a5@@ ; @@v12@@ = @@a6@@ ; @@v9@@ = __readfsqword ( Number ) ; @@arg@@ [ Number ] . gp_offset = Number ; @@v7@@ = vsnprintf ( @@a1@@ , @@a2@@ , @@a3@@ , @@arg@@ ) ; if ( @@a2@@ > @@v7@@ ) @@result@@ = ( unsigned int ) @@v7@@ ; else @@result@@ = ( unsigned int ) ( @@a2@@ - Number ) ; return @@result@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 3, \"t\": \"const char\"}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 3, \"t\": \"char\"}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"signed __int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r72\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"a6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r80\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s136\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s144\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s152\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s184\"}, {\"n\": \"arg\", \"t\": {\"T\": 2, \"n\": 1, \"s\": 24, \"t\": \"__va_list_tag\"}, \"location\": \"s208\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s220\"}]}",
"{\"name\": \"disasm_line__browser\", \"code\": \"__int64 __fastcall disasm_line__browser ( __int64 @@a1@@ ) { return @@a1@@ + Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"annotate_browser__set_jumps_percent_color\", \"code\": \"__int64 __fastcall annotate_browser__set_jumps_percent_color ( __int64 @@a1@@ , int @@a2@@ , char @@a3@@ ) { unsigned int @@v3@@ ; @@v3@@ = annotate_browser__jumps_percent_color ( @@a1@@ , @@a2@@ , @@a3@@ ) ; return ui_browser__set_color ( @@a1@@ , @@v3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}"
] |
{"name": "disasm_line__is_valid_jump", "code": "_BOOL8 __fastcall disasm_line__is_valid_jump ( __int64 @@a1@@ , __int64 @@a2@@ ) { unsigned __int64 @@v2@@ ; _BOOL8 @@result@@ ; @@result@@ = Number ; if ( @@a1@@ ) { if ( * ( _QWORD * ) ( @@a1@@ + Number ) ) { if ( ( unsigned __int8 ) ins__is_jump ( * ( _QWORD * ) ( @@a1@@ + Number ) ) == Number && disasm_line__has_offset ( @@a1@@ ) ) { @@v2@@ = * ( _QWORD * ) ( @@a1@@ + Number ) ; if ( @@v2@@ < symbol__size ( @@a2@@ ) ) @@result@@ = Number ; } } } return @@result@@ ; }", "source": [{"n": "v2", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "r32"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "_BOOL8", "s": 8}, "location": "r8"}]}
|
[{"n": "v2", "t": {"T": 1, "n": "size_t", "s": 8}, "location": "r32"}, {"n": "dl_0", "t": {"T": 3, "t": "disasm_line"}, "location": "r56"}, {"n": "sym", "t": {"T": 3, "t": "symbol"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}]
|
data1/train-shard-10.tar
|
077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f_077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f.jsonl
| 15 |
[
"{\"name\": \"symbol__size\", \"code\": \"__int64 __fastcall symbol__size ( __int64 @@a1@@ ) { return * ( _QWORD * ) ( @@a1@@ + Number ) - * ( _QWORD * ) ( @@a1@@ + Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"disasm_line__has_offset\", \"code\": \"bool __fastcall disasm_line__has_offset ( __int64 @@a1@@ ) { return * ( _QWORD * ) ( @@a1@@ + Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}"
] |
{"name": "annotate_browser__draw_current_jump", "code": "unsigned __int64 __fastcall annotate_browser__draw_current_jump ( __int64 @@a1@@ ) { unsigned __int8 @@v2@@ ; unsigned int @@v3@@ ; unsigned int @@v4@@ ; __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; unsigned __int64 @@v10@@ ; @@v10@@ = __readfsqword ( Number ) ; @@v5@@ = * ( _QWORD * ) ( @@a1@@ + Number ) ; @@v6@@ = * ( _QWORD * ) ( * ( _QWORD * ) ( @@a1@@ + Number ) + Number L ) ; if ( ! strstr ( ( const char * ) ( @@v6@@ + Number ) , String ) && disasm_line__is_valid_jump ( @@v5@@ , @@v6@@ ) ) { @@v7@@ = * ( _QWORD * ) ( * ( _QWORD * ) ( @@a1@@ + Number ) + Number L * * ( _QWORD * ) ( @@v5@@ + Number ) ) ; if ( @@v7@@ ) { @@v8@@ = disasm_line__browser ( @@v5@@ ) ; @@v9@@ = disasm_line__browser ( @@v7@@ ) ; if ( annotate_browser__opts ) { @@v3@@ = * ( _DWORD * ) ( @@v8@@ + Number ) ; @@v4@@ = * ( _DWORD * ) ( @@v9@@ + Number ) ; } else { @@v3@@ = * ( _DWORD * ) ( @@v8@@ + Number ) ; @@v4@@ = * ( _DWORD * ) ( @@v9@@ + Number ) ; } @@v2@@ = Number * * ( _DWORD * ) ( @@a1@@ + Number ) ; ui_browser__set_color ( @@a1@@ , Number L ) ; _ui_browser__line_arrow ( @@a1@@ , @@v2@@ + Number + ( unsigned int ) * ( unsigned __int8 * ) ( @@a1@@ + Number ) , @@v3@@ , @@v4@@ ) ; } } return __readfsqword ( Number ) ^ @@v10@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "v9", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v8", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s32"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s40"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s56"}, {"n": "v4", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s76"}, {"n": "v10", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}, {"n": "v3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s80"}, {"n": "v2", "t": {"T": 1, "n": "unsigned __int8", "s": 1}, "location": "s81"}]}
|
[{"n": "browser", "t": {"T": 3, "t": "ui_browser"}, "location": "r56"}, {"n": "btarget", "t": {"T": 3, "t": "browser_disasm_line"}, "location": "s16"}, {"n": "bcursor", "t": {"T": 3, "t": "browser_disasm_line"}, "location": "s24"}, {"n": "target", "t": {"T": 3, "t": "disasm_line"}, "location": "s32"}, {"n": "sym", "t": {"T": 3, "t": "symbol"}, "location": "s40"}, {"n": "cursor", "t": {"T": 3, "t": "disasm_line"}, "location": "s56"}, {"n": "to", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s76"}, {"n": "", "t": {"T": 10}, "location": "s8"}, {"n": "from", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s80"}, {"n": "pcnt_width", "t": {"T": 1, "n": "u8", "s": 1}, "location": "s81"}]
|
data1/train-shard-10.tar
|
077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f_077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f.jsonl
| 16 |
[
"{\"name\": \"disasm_line__browser\", \"code\": \"__int64 __fastcall disasm_line__browser ( __int64 @@a1@@ ) { return @@a1@@ + Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"disasm_line__is_valid_jump\", \"code\": \"_BOOL8 __fastcall disasm_line__is_valid_jump ( __int64 @@a1@@ , __int64 @@a2@@ ) { unsigned __int64 @@v2@@ ; _BOOL8 @@result@@ ; @@result@@ = Number ; if ( @@a1@@ ) { if ( * ( _QWORD * ) ( @@a1@@ + Number ) ) { if ( ( unsigned __int8 ) ins__is_jump ( * ( _QWORD * ) ( @@a1@@ + Number ) ) == Number && disasm_line__has_offset ( @@a1@@ ) ) { @@v2@@ = * ( _QWORD * ) ( @@a1@@ + Number ) ; if ( @@v2@@ < symbol__size ( @@a2@@ ) ) @@result@@ = Number ; } } } return @@result@@ ; }\", \"source\": [{\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"_BOOL8\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "annotate_browser__refresh", "code": "__int64 __fastcall annotate_browser__refresh ( __int64 @@a1@@ ) { unsigned int @@v2@@ ; unsigned int @@v3@@ ; @@v2@@ = ui_browser__list_head_refresh ( @@a1@@ ) ; @@v3@@ = Number * * ( _DWORD * ) ( @@a1@@ + Number ) ; if ( byte_3102 ) annotate_browser__draw_current_jump ( @@a1@@ ) ; ui_browser__set_color ( @@a1@@ , Number L ) ; _ui_browser__vline ( @@a1@@ , @@v3@@ , Number L , ( unsigned __int16 ) ( * ( _WORD * ) ( @@a1@@ + Number ) - Number ) ) ; return @@v2@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "v3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s28"}, {"n": "v2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s32"}]}
|
[{"n": "browser", "t": {"T": 3, "t": "ui_browser"}, "location": "r56"}, {"n": "pcnt_width", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s28"}, {"n": "ret", "t": {"T": 1, "n": "int", "s": 4}, "location": "s32"}]
|
data1/train-shard-10.tar
|
077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f_077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f.jsonl
| 17 |
[
"{\"name\": \"annotate_browser__draw_current_jump\", \"code\": \"unsigned __int64 __fastcall annotate_browser__draw_current_jump ( __int64 @@a1@@ ) { unsigned __int8 @@v2@@ ; unsigned int @@v3@@ ; unsigned int @@v4@@ ; __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; unsigned __int64 @@v10@@ ; @@v10@@ = __readfsqword ( Number ) ; @@v5@@ = * ( _QWORD * ) ( @@a1@@ + Number ) ; @@v6@@ = * ( _QWORD * ) ( * ( _QWORD * ) ( @@a1@@ + Number ) + Number L ) ; if ( ! strstr ( ( const char * ) ( @@v6@@ + Number ) , String ) && disasm_line__is_valid_jump ( @@v5@@ , @@v6@@ ) ) { @@v7@@ = * ( _QWORD * ) ( * ( _QWORD * ) ( @@a1@@ + Number ) + Number L * * ( _QWORD * ) ( @@v5@@ + Number ) ) ; if ( @@v7@@ ) { @@v8@@ = disasm_line__browser ( @@v5@@ ) ; @@v9@@ = disasm_line__browser ( @@v7@@ ) ; if ( annotate_browser__opts ) { @@v3@@ = * ( _DWORD * ) ( @@v8@@ + Number ) ; @@v4@@ = * ( _DWORD * ) ( @@v9@@ + Number ) ; } else { @@v3@@ = * ( _DWORD * ) ( @@v8@@ + Number ) ; @@v4@@ = * ( _DWORD * ) ( @@v9@@ + Number ) ; } @@v2@@ = Number * * ( _DWORD * ) ( @@a1@@ + Number ) ; ui_browser__set_color ( @@a1@@ , Number L ) ; _ui_browser__line_arrow ( @@a1@@ , @@v2@@ + Number + ( unsigned int ) * ( unsigned __int8 * ) ( @@a1@@ + Number ) , @@v3@@ , @@v4@@ ) ; } } return __readfsqword ( Number ) ^ @@v10@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s40\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s56\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s76\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s80\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int8\", \"s\": 1}, \"location\": \"s81\"}]}"
] |
{"name": "disasm__cmp", "code": "_BOOL8 __fastcall disasm__cmp ( __int64 @@a1@@ , __int64 @@a2@@ , int @@a3@@ ) { int @@i@@ ; for ( @@i@@ = Number ; @@i@@ < @@a3@@ ; ++ @@i@@ ) { if ( * ( double * ) ( @@a1@@ + Number * ( @@i@@ + Number L ) + Number ) != * ( double * ) ( @@a2@@ + Number * ( @@i@@ + Number L ) + Number ) ) return * ( double * ) ( @@a2@@ + Number * ( @@i@@ + Number L ) + Number ) > * ( double * ) ( @@a1@@ + Number * ( @@i@@ + Number L ) + Number ) ; } return Number L ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "i", "t": {"T": 1, "n": "int", "s": 4}, "location": "s12"}]}
|
[{"n": "nr_pcnt", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a", "t": {"T": 3, "t": "browser_disasm_line"}, "location": "r56"}, {"n": "b", "t": {"T": 3, "t": "browser_disasm_line"}, "location": "r64"}, {"n": "i", "t": {"T": 1, "n": "int", "s": 4}, "location": "s12"}]
|
data1/train-shard-10.tar
|
077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f_077a73bbcf0edea2dcca80a8235e6fecd72141d5d31fbf5623f58c57e6ca345f.jsonl
| 18 |
[] |
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