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const std = @import("std");
const MatchedArg = @import("MatchedArg.zig");
const ArgValue = MatchedArg.Value;
const ArgHashMap = std.StringHashMap(ArgValue);
pub const ArgMatches = struct {
allocator: std.mem.Allocator,
args: ArgHashMap,
subcommand: ?*SubCommand,
pub fn init(allocator: std.mem.Allocator) ArgMatches {
return ArgMatches{
.allocator = allocator,
.args = ArgHashMap.init(allocator),
.subcommand = null,
};
}
pub fn deinit(self: *ArgMatches) void {
var args_value_iter = self.args.valueIterator();
while (args_value_iter.next()) |value| {
switch (value.*) {
.many => |v| v.deinit(),
else => {},
}
}
self.args.deinit();
if (self.subcommand) |subcommand| {
subcommand.deinit();
self.allocator.destroy(subcommand);
}
}
pub fn putMatchedArg(self: *ArgMatches, arg: MatchedArg) !void {
return self.args.put(arg.name, arg.value);
}
pub fn setSubcommand(self: *ArgMatches, subcommand: SubCommand) !void {
var alloc_subcmd = try self.allocator.create(SubCommand);
alloc_subcmd.* = subcommand;
self.subcommand = alloc_subcmd;
}
pub fn isPresent(self: *const ArgMatches, name_to_lookup: []const u8) bool {
if (self.args.contains(name_to_lookup)) {
return true;
}
if (self.subcommand) |subcmd| {
if (std.mem.eql(u8, subcmd.name, name_to_lookup))
return true;
}
return false;
}
pub fn valueOf(self: *const ArgMatches, arg_name: []const u8) ?[]const u8 {
const arg_value = self.args.get(arg_name);
if (arg_value) |value| {
switch (value) {
.single => |val| {
return val;
},
else => return null,
}
}
if (self.subcommand) |subcmd| {
if (subcmd.matches) |matches| {
return matches.valueOf(arg_name);
}
}
return null;
}
pub fn valuesOf(self: *ArgMatches, name_to_lookup: []const u8) ?[][]const u8 {
var arg_value = self.args.get(name_to_lookup) orelse return null;
switch (arg_value) {
.many => |*values| {
return values.toOwnedSlice();
},
else => return null,
}
}
pub fn subcommandMatches(self: *const ArgMatches, subcmd_name: []const u8) ?ArgMatches {
if (self.subcommand) |subcmd| {
if (std.mem.eql(u8, subcmd.name, subcmd_name)) {
return subcmd.matches;
}
}
return null;
}
};
pub const SubCommand = struct {
name: []const u8,
matches: ?ArgMatches,
pub fn initWithoutArg(name: []const u8) SubCommand {
return SubCommand{
.name = name,
.matches = null,
};
}
pub fn initWithArg(name: []const u8, arg_matches: ArgMatches) SubCommand {
var self = initWithoutArg(name);
self.matches = arg_matches;
return self;
}
pub fn deinit(self: *SubCommand) void {
if (self.matches) |*matches| matches.deinit();
}
}; | src/arg_matches.zig |
const std = @import("std");
usingnamespace @import("vector3.zig");
pub fn QuaternionFn(comptime T: type) type {
if (@typeInfo(T) != .Float) {
@compileError("Quaternion not implemented for " ++ @typeName(T) ++ " must use float type");
}
return struct {
const Self = @This();
const Vec3Type = Vector3Fn(T);
const W = 0;
const X = 1;
const Y = 2;
const Z = 3;
//W, X, Y, Z
data: std.meta.Vector(4, T),
pub const identity = Self{ .data = [_]T{ 1, 0, 0, 0 } };
pub fn axisAngle(axis: Vec3Type, angle_rad: T) Self {
var angle_2 = angle_rad * 0.5;
var sin = Vec3Type.new_value(@sin(angle_2));
var values = axis.normalize().mul(sin).data;
return Self{
.data = [_]T{ @cos(angle_2), values[0], values[1], values[2] },
};
}
pub fn inverse(self: *Self) Self {
var len2 = self.length2();
var inv_len2 = 1 / len2;
var inv_data: std.meta.Vector(4, T) = [_]T{ inv_len2, inv_len2, inv_len2, inv_len2 };
var neg_data: std.meta.Vector(4, T) = [_]T{ -1, -1, -1, 1 };
return (self.data * neg_data) * inv_data;
}
pub fn normalize(self: *Self) Self {
var len = self.length();
return self.data / [_]T{ len, len, len, len };
}
pub fn length(self: Self) T {
return @sqrt(self.length2());
}
pub fn length2(self: Self) T {
var data = self.data * self.data;
return data[W] +
data[X] +
data[Y] +
data[Z];
}
pub fn mul(lhs: Self, rhs: Self) Self {
var l = lhs.data;
var r = rhs.data;
return Self{
.data = [_]T{
(l[W] * r[W]) - (l[X] * r[X]) - (l[Y] * r[Y]) - (l[Z] * r[Z]),
(l[W] * r[X]) + (l[X] * r[W]) + (l[Y] * r[Z]) - (l[Z] * r[Y]),
(l[W] * r[Y]) + (l[Y] * r[X]) + (l[Z] * r[X]) - (l[X] * r[Z]),
(l[W] * r[Z]) + (l[Z] * r[W]) + (l[X] * r[Y]) - (l[Y] * r[X]),
},
};
}
pub fn rotate(self: Self, vec: Vec3Type) Vec3Type {
var u = Vec3Type.new(
self.data[X],
self.data[Y],
self.data[Z],
);
var w = self.data[W];
var uv = u.cross(vec);
var uuv = u.cross(uv);
var r = vec.add(uv.scale(w).add(uuv).scale(2));
return r;
}
};
} | src/linear_math/quaternion.zig |
const std = @import("std");
const input = @embedFile("data/input08");
usingnamespace @import("util.zig");
pub fn main() !void {
var allocator_state = std.heap.ArenaAllocator.init(std.heap.page_allocator);
defer allocator_state.deinit();
const allocator = &allocator_state.allocator;
var insts = try parse(allocator, input);
var part1 = (try execute(allocator, insts)).acc;
print("[Part1] acc = {}", .{part1});
var part2 = try fix(allocator, insts);
print("[Part2] acc = {}", .{part2});
}
const Op = enum { nop, acc, jmp };
const Inst = struct {
op: Op,
arg: i32,
};
fn parse(allocator: *std.mem.Allocator, inputStr: []const u8) ![]Inst {
var insts = std.ArrayList(Inst).init(allocator);
var reader = lines(inputStr);
while (reader.next()) |line| {
const op = inline for (std.meta.fields(Op)) |opField| {
const nameVal = std.mem.readIntSliceNative(u24, opField.name[0..3]);
const inputVal = std.mem.readIntSliceNative(u24, line[0..3]);
if (nameVal == inputVal) {
break @intToEnum(Op, opField.value);
}
} else return error.UnknownInstruction;
const arg = try std.fmt.parseInt(i32, line[4..], 10);
try insts.append(.{ .op = op, .arg = arg });
}
return insts.toOwnedSlice();
}
const ExecutionResult = struct { acc: i32, loop: bool };
fn execute(allocator: *std.mem.Allocator, insts: []const Inst) !ExecutionResult {
const alreadyExecuted = try allocator.alloc(bool, insts.len);
defer allocator.free(alreadyExecuted);
std.mem.set(bool, alreadyExecuted, false);
var ip: isize = 0;
var accumulator: i32 = 0;
while (ip >= 0 and ip < insts.len) {
const i = @intCast(usize, ip);
const inst = insts[i];
if (alreadyExecuted[i]) {
return ExecutionResult { .acc = accumulator, .loop = true };
}
alreadyExecuted[i] = true;
switch (inst.op) {
.nop => ip += 1,
.acc => { accumulator += inst.arg; ip += 1; },
.jmp => ip += inst.arg,
}
}
return ExecutionResult { .acc = accumulator, .loop = false };
}
fn fix(allocator: *std.mem.Allocator, insts: []Inst) !i32 {
for (insts) |*inst| {
switch (inst.op) {
.nop, .jmp => {
const origOp = inst.op;
inst.op = if (inst.op == .nop) .jmp else .nop;
var result = try execute(allocator, insts);
if (!result.loop) {
return result.acc;
}
inst.op = origOp;
},
else => {},
}
}
return error.Unfixable;
}
const expectEqual = std.testing.expectEqual;
const testSrc =
\\nop +0
\\acc +1
\\jmp +4
\\acc +3
\\jmp -3
\\acc -99
\\acc +1
\\jmp -4
\\acc +6
;
test "execute" {
var allocator_state = std.heap.ArenaAllocator.init(std.testing.allocator);
defer allocator_state.deinit();
const allocator = &allocator_state.allocator;
expectEqual(ExecutionResult { .acc = 5, .loop = true }, try execute(allocator, try parse(allocator, testSrc)));
}
test "fix" {
var allocator_state = std.heap.ArenaAllocator.init(std.testing.allocator);
defer allocator_state.deinit();
const allocator = &allocator_state.allocator;
expectEqual(@as(i32, 8), try fix(allocator, try parse(allocator, testSrc)));
} | src/day08.zig |
pub const Map_Tile = enum {
plains, woods, mountain, road, bridge,
sea, // reefs, beach,
river,
// pipe, pipe_seam, pipe_broken,
hq, city, factory, // airport, port,
// miss_silo, com_tower, lab,
const Self = @This();
pub fn defense(self: Self) Defense {
return switch (self) {
.road, .bridge, .sea, .river, => 0,
.plains, => 1,
.woods, => 2,
.city, .factory, => 3,
.mountain, .hq, => 4,
};
}
pub fn move_cost(self: Self, typ: Move_Type) ?Cost {
return switch (typ) {
.infantry => switch (self) {
.plains, .woods, .road,
.bridge, // .beach,
.hq, .city, .factory, // .airport, .port,
// .miss_silo, .com_tower, .lab,
=> @as(?Cost, 1),
.mountain, .river,
=> @as(?Cost, 2),
.sea, // .reefs,
// .pipe, .pipe_seam, .pipe_broken,
=> null,
},
.mech => switch (self) {
.plains, .woods, .mountain, .road, .bridge,
// .beach,
.river,
.hq, .city, .factory, // .airport, .port,
// .miss_silo, .com_tower, .lab,
=> @as(?Cost, 1),
.sea, // .reefs,
// .pipe, .pipe_seam, .pipe_broken,
=> null,
},
.treads => switch (self) {
.plains, .road,
.bridge, // .beach,
.hq, .city, .factory, // .airport, .port,
// .miss_silo, .com_tower, .lab,
=> @as(?Cost, 1),
.woods, => @as(?Cost, 2),
.mountain, .river,
.sea, // .reefs,
// .pipe, .pipe_seam, .pipe_broken,
=> null,
}
};
}
};
pub const Defense = u3;
// Units
pub const Unity_Id = enum {
infantry, mech, // recon,
apc,
// tank, md_tank, neo_tank,
// artillery, rockets,
// anti_air, missiles,
// b_copter, t_copter, fighter, bomber,
// lander, cruiser, sub, b_ship,
const Self = @This();
pub const cnt = @typeInfo(Self).Enum.fields.len;
pub fn move_cost(self: Self) Move_Cost {
return switch (self) {
.infantry => Move_Cost{ .typ = .infantry, .moves = 3 },
.mech => Move_Cost{ .typ = .mech , .moves = 2 },
.apc => Move_Cost{ .typ = .treads , .moves = 6 },
};
}
pub fn may_transport(self: Self, other: Self) bool {
return switch (self) {
.apc => switch (other) {
.infantry, .mech => true,
else => false,
},
else => false,
};
}
pub fn max_fuel(self: Self) Fuel {
return switch (self) {
.infantry => 99,
.mech => 70,
.apc => 70,
};
}
pub fn attack(self: Self, other: Self) ?Damage {
return switch (self) {
.infantry => switch (other) {
.infantry => @as(Damage, 55),
.mech => @as(Damage, 45),
.apc => @as(Damage, 14),
},
.mech => switch (other) {
.infantry => @as(Damage, 65),
.mech => @as(Damage, 55),
.apc => @as(Damage, 75),
},
.apc => null,
};
}
pub fn name_len(self: Self) usize {
const lookup = @typeInfo(Self).Enum.fields;
return switch ( self ) {
.infantry => lookup[@enumToInt(@as(Self, .infantry))].name.len,
.mech => lookup[@enumToInt(@as(Self, .mech ))].name.len,
.apc => lookup[@enumToInt(@as(Self, .apc ))].name.len,
};
}
};
pub const Move_Type = enum {
infantry, mech,
// tires,
treads,
// air,
// ship, lander,
};
pub const Move_Cost = struct {
typ: Move_Type,
moves: Cost,
};
pub const Cost = u4;
pub const Fuel = u7;
pub const Damage = u7; | src/simple_info.zig |
const std = @import("std");
const mem = std.mem;
const math = std.math;
const fmt = std.fmt;
const log = std.log.scoped(.intcode);
const Allocator = mem.Allocator;
const AutoHashMap = std.AutoHashMap;
const ArrayList = std.ArrayList;
const TailQueue = std.TailQueue;
const OpcodeTag = enum(u7) {
add = 1,
mul = 2,
get = 3,
put = 4,
je = 5,
jne = 6,
lt = 7,
eq = 8,
base = 9,
halt = 99,
};
pub const ParamMode = enum(u2) {
/// causes the parameter to be interpreted as a position - if the parameter
/// is 50, its value is the value stored at address 50 in memory
position = 0,
/// in immediate mode, a parameter is interpreted as a value - if the
/// parameter is 50, its value is simply 50.
immediate = 1,
/// The address a relative mode parameter refers to is itself _plus_ the
/// current _relative base_. When the relative base is `0`, relative mode
/// parameters and position mode parameters with the same value refer to
/// the same address.
relative = 2,
};
const Args2 = struct { first: ParamMode, second: ParamMode };
const Args3 = struct { first: ParamMode, second: ParamMode, third: ParamMode };
pub const Instruction = union(OpcodeTag) {
add: Args3,
mul: Args3,
get: ParamMode,
put: ParamMode,
je: Args2,
jne: Args2,
lt: Args3,
eq: Args3,
base: ParamMode,
halt: void,
/// Parse a single instruction
pub fn fromValue(value: i64) Instruction {
// the opcode is the rightmost two digits
const opcode = @intCast(u7, @mod(value, 100));
var rem = @divExact(value - opcode, 100);
// Parameter modes are single digits, _one per parameter_ read right-to-left from the opcode:
// - the first parameter's mode is in the hundreds digit,
// - the second parameter's mode is in the thousands digit,
// - the third parameter's mode is in the ten-thousands digit,
// and so on.
var modes = [_]ParamMode{ .position, .position, .position };
var i: usize = 0;
while (i < 3) : (i += 1) {
const digit = @mod(rem, 10);
rem = @divFloor(rem - digit, 10);
modes[i] = parseMode(digit);
if (rem == 0) {
break;
}
}
const result = blk: {
switch (@intToEnum(OpcodeTag, opcode)) {
.add => {
const val = Instruction{ .add = Args3{ .first = modes[0], .second = modes[1], .third = modes[2] } };
break :blk val;
},
.mul => {
const val = Instruction{ .mul = Args3{ .first = modes[0], .second = modes[1], .third = modes[2] } };
break :blk val;
},
.get => {
const val = Instruction{ .get = modes[0] };
break :blk val;
},
.put => {
const val = Instruction{ .put = modes[0] };
break :blk val;
},
.je => {
const val = Instruction{ .je = Args2{ .first = modes[0], .second = modes[1] } };
break :blk val;
},
.jne => {
const val = Instruction{ .jne = Args2{ .first = modes[0], .second = modes[1] } };
break :blk val;
},
.lt => {
const val = Instruction{ .lt = Args3{ .first = modes[0], .second = modes[1], .third = modes[2] } };
break :blk val;
},
.eq => {
const val = Instruction{ .eq = Args3{ .first = modes[0], .second = modes[1], .third = modes[2] } };
break :blk val;
},
.base => {
const val = Instruction{ .base = modes[0] };
break :blk val;
},
.halt => {
break :blk Instruction{ .halt = {} };
},
}
};
return result;
}
inline fn parseMode(num: i64) ParamMode {
return @intToEnum(ParamMode, @intCast(u2, num));
}
};
pub const IntcodeProgram = struct {
const Self = @This();
allocator: Allocator,
code: []i64,
// context
ip: usize,
base: i64,
// state
ram: AutoHashMap(u64, i64),
pub const Status = enum(u2) {
/// Program needs more numbers to continue (number source "exhausted")
blocked,
/// Program terminated
terminated,
/// EOF
eof,
};
pub fn init(allocator: Allocator, code: []const i64) !Self {
const ram = AutoHashMap(u64, i64).init(allocator);
var code_copy = try allocator.alloc(i64, code.len);
mem.copy(i64, code_copy, code);
return Self{
.allocator = allocator,
.code = code_copy,
.ip = 0,
.base = 0,
.ram = ram,
};
}
pub fn deinit(self: *Self) void {
self.ram.deinit();
self.allocator.free(self.code);
}
// Clone creates an identical copy of the current IntcodeProgram.
pub fn clone(self: Self, allocator: Allocator) !Self {
var copy = try Self.init(allocator, self.code);
copy.ip = self.ip;
copy.base = self.base;
var it = self.ram.iterator();
try copy.ram.ensureTotalCapacity(self.ram.count());
while (it.next()) |entry| {
copy.ram.putAssumeCapacity(entry.key_ptr.*, entry.value_ptr.*);
}
return copy;
}
// Caller owns the result and must call deinit() to free memory.
pub fn run(self: *Self, comptime I: type, input: []const I, comptime O: type, output: *ArrayList(O)) Allocator.Error!Status {
const input_len = input.len;
var input_idx: usize = 0;
const n = self.code.len;
while (self.ip < n) {
// needed to restore self.ip in certain cases
const ip = self.ip;
const instruction = self.readInstruction();
switch (instruction) {
.add => {
const modes = instruction.add;
const a = self.readParam(modes.first);
const b = self.readParam(modes.second);
const out_pos = self.readOutPos(modes.third);
log.debug("[Add] a={d}, b={d}, out_pos={d}", .{ a, b, out_pos });
try self.writeValue(out_pos, a + b);
},
.mul => {
const modes = instruction.mul;
const a = self.readParam(modes.first);
const b = self.readParam(modes.second);
const out_pos = self.readOutPos(modes.third);
log.debug("[Mul] a={d}, b={d}, out_pos={d}", .{ a, b, out_pos });
try self.writeValue(out_pos, a * b);
},
.get => {
if (input_idx >= input_len) {
log.debug("[Get] Need more numbers to continue", .{});
self.ip = ip; // restore old ip
return Status.blocked;
}
const data = @intCast(I, input[input_idx]);
input_idx += 1;
const out_pos = self.readOutPos(instruction.get);
log.debug("[Get] Storing {d} it in position out_pos={d}", .{ data, out_pos });
try self.writeValue(out_pos, data);
},
.put => {
const a = self.readParam(instruction.put);
log.debug("[Put] Appending {d} to output", .{a});
try output.append(@intCast(O, a));
},
.je => {
const modes = instruction.je;
const a = self.readParam(modes.first);
const b = self.readParam(modes.second);
if (a != 0) {
// jump
log.debug("[JUMP-IF-TRUE] a={d}, b={d} => jumping", .{ a, b });
self.ip = @intCast(usize, b);
} else {
log.debug("[JUMP-IF-TRUE] a={d}, b={d} => no jump", .{ a, b });
}
},
.jne => {
const modes = instruction.jne;
const a = self.readParam(modes.first);
const b = self.readParam(modes.second);
if (a == 0) {
log.debug("[JUMP-IF-FALSE] a={d}, b={d} => jump", .{ a, b });
self.ip = @intCast(usize, b);
} else {
log.debug("[JUMP-IF-FALSE] a={d}, b={d} => no jump", .{ a, b });
}
},
.lt => {
const modes = instruction.lt;
const a = self.readParam(modes.first);
const b = self.readParam(modes.second);
const out_pos = self.readOutPos(modes.third);
log.debug("[LT] Checking if {d} < {d} and storing result in out_pos {d}", .{ a, b, out_pos });
const val: i64 = if (a < b) 1 else 0;
try self.writeValue(out_pos, val);
},
.eq => {
const modes = instruction.eq;
const a = self.readParam(modes.first);
const b = self.readParam(modes.second);
const out_pos = self.readOutPos(modes.third);
log.debug("[EQ] Checking if {d} == {d} and storing result in out_pos {d}", .{ a, b, out_pos });
const val: i64 = if (a == b) 1 else 0;
try self.writeValue(out_pos, val);
},
.base => {
const a = self.readParam(instruction.base);
const new_base = self.base + a;
log.debug("[BASE] Adjusting base: {d} -> {d}", .{ self.base, new_base });
self.base = new_base;
},
.halt => {
log.debug("[HALT]", .{});
return Status.terminated;
},
}
log.debug("ip: {d} -> {d}, base: {d}", .{ ip, self.ip, self.base });
}
// program did not terminate with a halt instruction
return Status.eof;
}
inline fn readInstruction(self: *Self) Instruction {
const instruction = Instruction.fromValue(self.code[self.ip]);
self.ip += 1;
return instruction;
}
fn readParam(self: *Self, mode: ParamMode) i64 {
const val = self.code[self.ip];
self.ip += 1;
switch (mode) {
.position => {
return self.readValue(@intCast(u64, val));
},
.immediate => {
return val;
},
.relative => {
return self.readValue(@intCast(u64, self.base + val));
},
}
}
fn readOutPos(self: *Self, mode: ParamMode) u64 {
const val = self.code[self.ip];
self.ip += 1;
switch (mode) {
ParamMode.relative => {
return @intCast(u64, self.base + val);
},
else => {
return @intCast(u64, val);
},
}
}
fn readValue(self: Self, addr: u64) i64 {
const value = blk: {
if (addr < self.code.len) {
const val = self.code[@intCast(usize, addr)];
log.debug("reading addr {d} from code: {d}", .{ addr, val });
break :blk val;
} else if (self.ram.get(addr)) |val| {
log.debug("reading addr {d} from ram: {d}", .{ addr, val });
break :blk val;
} else {
const val = 0;
log.debug("no value for addr {d}, returning default: {d}", .{ addr, val });
break :blk 0;
}
};
return value;
}
fn writeValue(self: *Self, addr: u64, value: i64) !void {
if (addr < self.code.len) {
log.debug("writing {d} to code at addr {d}", .{ value, addr });
self.code[@intCast(usize, addr)] = value;
} else {
log.debug("writing {d} to RAM at addr {d}", .{ value, addr });
try self.ram.put(addr, value);
}
}
};
/// caller owns result and must call `deinit`
pub fn parseInput(allocator: Allocator, file_content: []const u8) ![]i64 {
var list = ArrayList(i64).init(allocator);
var it = mem.tokenize(u8, file_content, ",");
while (it.next()) |val| {
const stripped = mem.trimRight(u8, val, " \n");
const num = try fmt.parseInt(i64, stripped, 10);
try list.append(num);
}
return list.toOwnedSlice();
}
test {
_ = @import("intcode_test.zig");
} | share/zig/intcode.zig |
const std = @import("std");
const rpc = @import("index.zig");
const AutoHashMap = std.AutoHashMap;
const Allocator = std.mem.Allocator;
const socket = std.socket;
const json = std.json;
const net = std.net;
const assert = std.debug.assert;
fn Future(comptime T: type) type {
return struct {
handle: promise,
data: ?T,
};
}
pub const Client = struct {
const ResponseFuture = Future(rpc.Response);
const AwaitMap = std.AutoHashMap(rpc.Oid, ResponseFuture);
allocator: *std.mem.Allocator,
parser: json.Parser,
fd: socket.Socket,
address: net.Address,
await_ids: AwaitMap,
pub fn new(allocator: *std.mem.Allocator) !Client {
return Client {
.fd = try Socket.tcp(Domain.Inet6),
.await_ids = AwaitMap.init(allocator),
.parser = json.Parser.init(allocator, true),
.allocator = allocator,
.address = undefined,
};
}
pub fn close(self: Client) void {
defer self.parser.deinit();
defer self.map.deinit();
defer self.fd.close();
var it = self.map.iter();
while (it.next()) |request| {
cancel request;
}
}
pub fn connect(self: *Client, address: Address) !void {
try self.fd.connect(&address);
errdefer self.fd.close();
self.address = address;
cancel try self.processData();
}
async fn processData(self: *Client) !void {
loop: while (true) {
const data = await self.fd.recv(self.allocator) catch |err| {
switch (err) {
error.Disconnect => {
self.fd.close();
self.fd = try Socket.tcp(Domain.Inet6);
break :loop;
},
else => return err,
}
};
try self.processMessage(data);
}
try self.fd.connect(&address);
}
fn processMessage(self: *Client, data: []const u8) !void {
const root = try self.parser.parse(data).root;
debug.assert(mem.eql(u8, root.Object.get("jsonrpc").?.value.String, "2.0"));
if (root.Object.get("error")) |err| {
fut.data = rpc.Response {
.err = Error.parse(err.String),
.result = null,
.id = null,
};
} else {
const id = Oid.parse(root.Object.get("id").?.value.String);
var fut = self.await_ids.get(id).?;
fut.data = rpc.Response {
.result = root.Object.get("result").?,
.err = null,
.id = id,
};
resume fut.handle;
}
}
pub fn async call(self: *Client, method: []const u8, params: ?rpc.Value) !rpc.Response {
const request = rpc.Request.call(methods, params);
self.fd.send(request.toString() ++ "\r\n");
// const fut = try self.getResponse();
_ = self.await_ids.set(request.id, ResponseFuture {
.handle = @handle(),
.data = null
});
return await fut;
}
pub async fn notify(self: *Client, method: []const u8, params: ?rpc.Value) !void {
const request = rpc.Request.notify(methods, params);
try await self.fd.send(request.toString() ++ "\r\n");
}
}; | src/client.zig |
const std = @import("std");
const Builder = std.build.Builder;
const LibExeObjStep = std.build.LibExeObjStep;
pub const Library = struct {
step: *LibExeObjStep,
pub fn link(self: Library, other: *LibExeObjStep) void {
other.addIncludeDir(include_dir);
other.linkLibrary(self.step);
}
};
fn root() []const u8 {
return std.fs.path.dirname(@src().file) orelse ".";
}
const root_path = root() ++ "/";
pub const include_dir = root_path ++ "mbedtls/include";
const library_include = root_path ++ "mbedtls/library";
pub fn create(b: *Builder, target: std.zig.CrossTarget, mode: std.builtin.Mode) Library {
const ret = b.addStaticLibrary("mbedtls", null);
ret.setTarget(target);
ret.setBuildMode(mode);
ret.addIncludeDir(include_dir);
ret.addIncludeDir(library_include);
// not sure why, but mbedtls has runtime issues when it's not built as
// release-small or with the -Os flag, definitely need to figure out what's
// going on there
ret.addCSourceFiles(srcs, &.{"-Os"});
ret.linkLibC();
if (target.isWindows())
ret.linkSystemLibrary("ws2_32");
return Library{ .step = ret };
}
const srcs = &.{
root_path ++ "mbedtls/library/certs.c",
root_path ++ "mbedtls/library/pkcs11.c",
root_path ++ "mbedtls/library/x509.c",
root_path ++ "mbedtls/library/x509_create.c",
root_path ++ "mbedtls/library/x509_crl.c",
root_path ++ "mbedtls/library/x509_crt.c",
root_path ++ "mbedtls/library/x509_csr.c",
root_path ++ "mbedtls/library/x509write_crt.c",
root_path ++ "mbedtls/library/x509write_csr.c",
root_path ++ "mbedtls/library/debug.c",
root_path ++ "mbedtls/library/net_sockets.c",
root_path ++ "mbedtls/library/ssl_cache.c",
root_path ++ "mbedtls/library/ssl_ciphersuites.c",
root_path ++ "mbedtls/library/ssl_cli.c",
root_path ++ "mbedtls/library/ssl_cookie.c",
root_path ++ "mbedtls/library/ssl_msg.c",
root_path ++ "mbedtls/library/ssl_srv.c",
root_path ++ "mbedtls/library/ssl_ticket.c",
root_path ++ "mbedtls/library/ssl_tls13_keys.c",
root_path ++ "mbedtls/library/ssl_tls.c",
root_path ++ "mbedtls/library/aes.c",
root_path ++ "mbedtls/library/aesni.c",
root_path ++ "mbedtls/library/arc4.c",
root_path ++ "mbedtls/library/aria.c",
root_path ++ "mbedtls/library/asn1parse.c",
root_path ++ "mbedtls/library/asn1write.c",
root_path ++ "mbedtls/library/base64.c",
root_path ++ "mbedtls/library/bignum.c",
root_path ++ "mbedtls/library/blowfish.c",
root_path ++ "mbedtls/library/camellia.c",
root_path ++ "mbedtls/library/ccm.c",
root_path ++ "mbedtls/library/chacha20.c",
root_path ++ "mbedtls/library/chachapoly.c",
root_path ++ "mbedtls/library/cipher.c",
root_path ++ "mbedtls/library/cipher_wrap.c",
root_path ++ "mbedtls/library/cmac.c",
root_path ++ "mbedtls/library/ctr_drbg.c",
root_path ++ "mbedtls/library/des.c",
root_path ++ "mbedtls/library/dhm.c",
root_path ++ "mbedtls/library/ecdh.c",
root_path ++ "mbedtls/library/ecdsa.c",
root_path ++ "mbedtls/library/ecjpake.c",
root_path ++ "mbedtls/library/ecp.c",
root_path ++ "mbedtls/library/ecp_curves.c",
root_path ++ "mbedtls/library/entropy.c",
root_path ++ "mbedtls/library/entropy_poll.c",
root_path ++ "mbedtls/library/error.c",
root_path ++ "mbedtls/library/gcm.c",
root_path ++ "mbedtls/library/havege.c",
root_path ++ "mbedtls/library/hkdf.c",
root_path ++ "mbedtls/library/hmac_drbg.c",
root_path ++ "mbedtls/library/md2.c",
root_path ++ "mbedtls/library/md4.c",
root_path ++ "mbedtls/library/md5.c",
root_path ++ "mbedtls/library/md.c",
root_path ++ "mbedtls/library/memory_buffer_alloc.c",
root_path ++ "mbedtls/library/mps_reader.c",
root_path ++ "mbedtls/library/mps_trace.c",
root_path ++ "mbedtls/library/nist_kw.c",
root_path ++ "mbedtls/library/oid.c",
root_path ++ "mbedtls/library/padlock.c",
root_path ++ "mbedtls/library/pem.c",
root_path ++ "mbedtls/library/pk.c",
root_path ++ "mbedtls/library/pkcs12.c",
root_path ++ "mbedtls/library/pkcs5.c",
root_path ++ "mbedtls/library/pkparse.c",
root_path ++ "mbedtls/library/pk_wrap.c",
root_path ++ "mbedtls/library/pkwrite.c",
root_path ++ "mbedtls/library/platform.c",
root_path ++ "mbedtls/library/platform_util.c",
root_path ++ "mbedtls/library/poly1305.c",
root_path ++ "mbedtls/library/psa_crypto_aead.c",
root_path ++ "mbedtls/library/psa_crypto.c",
root_path ++ "mbedtls/library/psa_crypto_cipher.c",
root_path ++ "mbedtls/library/psa_crypto_client.c",
root_path ++ "mbedtls/library/psa_crypto_driver_wrappers.c",
root_path ++ "mbedtls/library/psa_crypto_ecp.c",
root_path ++ "mbedtls/library/psa_crypto_hash.c",
root_path ++ "mbedtls/library/psa_crypto_mac.c",
root_path ++ "mbedtls/library/psa_crypto_rsa.c",
root_path ++ "mbedtls/library/psa_crypto_se.c",
root_path ++ "mbedtls/library/psa_crypto_slot_management.c",
root_path ++ "mbedtls/library/psa_crypto_storage.c",
root_path ++ "mbedtls/library/psa_its_file.c",
root_path ++ "mbedtls/library/ripemd160.c",
root_path ++ "mbedtls/library/rsa.c",
root_path ++ "mbedtls/library/rsa_internal.c",
root_path ++ "mbedtls/library/sha1.c",
root_path ++ "mbedtls/library/sha256.c",
root_path ++ "mbedtls/library/sha512.c",
root_path ++ "mbedtls/library/threading.c",
root_path ++ "mbedtls/library/timing.c",
root_path ++ "mbedtls/library/version.c",
root_path ++ "mbedtls/library/version_features.c",
root_path ++ "mbedtls/library/xtea.c",
}; | .gyro/zig-mbedtls-mattnite-github.com-a4f5357c/pkg/mbedtls.zig |
const x86_64 = @import("../index.zig");
const bitjuggle = @import("bitjuggle");
const std = @import("std");
/// Invalidate the given address in the TLB using the `invlpg` instruction.
pub fn flush(addr: x86_64.VirtAddr) void {
asm volatile ("invlpg (%[addr])"
:
: [addr] "r" (addr.value),
: "memory"
);
}
/// Invalidate the TLB completely by reloading the CR3 register.
pub fn flushAll() void {
x86_64.registers.control.Cr3.write(x86_64.registers.control.Cr3.read());
}
/// The Invalidate PCID Command to execute.
pub const InvPicCommand = union(enum) {
pub const AddressCommand = struct { virtAddr: x86_64.VirtAddr, pcid: Pcid };
/// The logical processor invalidates mappings—except global translations—for the linear address and PCID specified.
address: AddressCommand,
/// The logical processor invalidates all mappings—except global translations—associated with the PCID.
single: Pcid,
/// The logical processor invalidates all mappings—including global translations—associated with any PCID.
all,
/// The logical processor invalidates all mappings—except global translations—associated with any PCID.
allExceptGlobal,
};
/// The INVPCID descriptor comprises 128 bits and consists of a PCID and a linear address.
/// For INVPCID type 0, the processor uses the full 64 bits of the linear address even outside 64-bit mode; the linear address is not used for other INVPCID types.
pub const InvpcidDescriptor = extern struct {
address: u64,
pcid: u64,
};
/// Structure of a PCID. A PCID has to be <= 4096 for x86_64.
pub const Pcid = packed struct {
value: u12,
/// Create a new PCID
pub fn init(pcid: u12) Pcid {
return .{
.value = pcid,
};
}
};
/// Invalidate the given address in the TLB using the `invpcid` instruction.
///
/// ## Safety
/// This function is unsafe as it requires CPUID.(EAX=07H, ECX=0H):EBX.INVPCID to be 1.
pub fn flushPcid(command: InvPicCommand) void {
var desc = InvpcidDescriptor{
.address = 0,
.pcid = 0,
};
const kind: u64 = blk: {
switch (command) {
.address => |address| {
desc.address = address.virtAddr.value;
desc.pcid = address.pcid.value;
break :blk 0;
},
.single => |pcid| {
desc.pcid = pcid.value;
break :blk 1;
},
.all => break :blk 2,
.allExceptGlobal => break :blk 3,
}
};
asm volatile ("invpcid (%[desc]), %[kind]"
:
: [kind] "r" (kind),
[desc] "r" (@ptrToInt(&desc)),
: "memory"
);
}
comptime {
std.testing.refAllDecls(@This());
} | src/instructions/tlb.zig |
const zt = @import("deps/ZT/src/zt.zig");
const std = @import("std");
const sling = @import("sling.zig");
pub usingnamespace zt.game.Physics;
pub const SweepResult = struct {
hit: bool = false,
/// The normal of the collision, if there was no collision then this is 0,0.
normal: sling.math.Vec2 = .{},
/// How far into the velocity the mover gets before it hits static.
time: f32 = 1.0,
};
pub fn sweepRect(mover: sling.math.Rect, static: sling.math.Rect, velocity: sling.math.Vec2) f32 {
return sweepRectEx(mover, static, velocity).time;
}
/// WARNING: For now, this is not accurate at EXTREMELY high velocities.
/// Given a rectangle that moves, a static rectangle, and the mover's velocity, returns
/// an f32 that represents how far into the velocity that a collision happens. Useful
/// for proper collision that is far more accurate than an intersection. If 1.0 is returned,
/// no collision occured.
///
/// Quite a bit more expensive than simple methods of collision detection, but accurate and
/// avoids popping through thin geometry if used properly.
pub fn sweepRectEx(mover: sling.math.Rect, static: sling.math.Rect, velocity: sling.math.Vec2) SweepResult {
var result: SweepResult = .{};
// Calculate sweep through distances:
var xInvEntry: f32 = undefined;
var yInvEntry: f32 = undefined;
var xInvExit: f32 = undefined;
var yInvExit: f32 = undefined;
if (velocity.x > 0.0) {
xInvEntry = static.position.x - (mover.position.x + mover.size.x);
xInvExit = (static.position.x + static.size.x) - mover.position.x;
} else {
xInvEntry = (static.position.x + static.size.x) - mover.position.x;
xInvExit = static.position.x - (mover.position.x + mover.size.x);
}
if (velocity.y > 0.0) {
yInvEntry = static.position.y - (mover.position.y + mover.size.y);
yInvExit = (static.position.y + static.size.y) - mover.position.y;
} else {
yInvEntry = (static.position.y + static.size.y) - mover.position.y;
yInvExit = static.position.y - (mover.position.y + mover.size.y);
}
var xEntry: f32 = undefined;
var yEntry: f32 = undefined;
var xExit: f32 = undefined;
var yExit: f32 = undefined;
if (velocity.x == 0.0) {
xEntry = -std.math.inf(f32);
xExit = std.math.inf(f32);
} else {
xEntry = xInvEntry / velocity.x;
xExit = xInvExit / velocity.x;
}
if (velocity.y == 0.0) {
yEntry = -std.math.inf(f32);
yExit = std.math.inf(f32);
} else {
yEntry = yInvEntry / velocity.y;
yExit = yInvExit / velocity.y;
}
var entryTime: f32 = std.math.max(xEntry, yEntry);
var exitTime = std.math.min(xExit, yExit);
if (entryTime > exitTime or (xEntry < 0.0 and yEntry < 0.0) or xEntry > 1.0 or yEntry > 1.0) {
result.hit = false;
result.time = 1.0;
} else {
result.hit = true;
result.time = entryTime;
if (xEntry > yEntry) {
if (xInvEntry < 0.0) {
result.normal.x = 1.0;
result.normal.y = 0.0;
} else {
result.normal.x = -1.0;
result.normal.y = 0.0;
}
} else {
if (yInvEntry < 0.0) {
result.normal.x = 0.0;
result.normal.y = 1.0;
} else {
result.normal.x = 0.0;
result.normal.y = -1.0;
}
}
}
return result;
} | src/physics.zig |
const std = @import("std");
const os = std.os;
const warn = std.debug.warn;
const Allocator = std.mem.Allocator;
pub const DirectArena = struct {
next: *DirectArena,
offset: usize,
allocator: Allocator = Allocator{
.reallocFn = DirectArena.realloc,
.shrinkFn = DirectArena.shrink,
},
pub fn init() !*DirectArena {
const slice = os.mmap(
null,
std.mem.page_size,
os.PROT_READ | os.PROT_WRITE,
os.MAP_PRIVATE | os.MAP_ANONYMOUS,
-1,
0,
) catch return error.OutOfMemory;
const arena = @ptrCast(*DirectArena, slice.ptr);
arena.* = DirectArena{
.next = @alignCast(@alignOf(DirectArena), arena),
.offset = std.mem.alignForward(@sizeOf(DirectArena), 16),
};
return arena.next;
}
pub fn deinit(self: *DirectArena) void {
var ptr = self.next;
while (ptr != self) {
var cur = ptr;
ptr = ptr.next;
if (cur.offset > std.mem.page_size) {
os.munmap(@intToPtr([*]align(std.mem.page_size) u8, @ptrToInt(cur))[0..cur.offset]);
} else {
os.munmap(@intToPtr([*]align(std.mem.page_size) u8, @ptrToInt(cur))[0..std.mem.page_size]);
}
}
os.munmap(@intToPtr([*]align(std.mem.page_size) u8, @ptrToInt(self))[0..std.mem.page_size]);
}
fn shrink(allocator: *Allocator, old_mem_unaligned: []u8, old_align: u29, new_size: usize, new_align: u29) []u8 {
return old_mem_unaligned[0..new_size];
}
fn realloc(allocator: *Allocator, old_mem_unaligned: []u8, old_align: u29, new_size: usize, new_align: u29) error{OutOfMemory}![]u8 {
if (new_size == 0)
return (@as([*]u8, undefined))[0..0];
const direct_allocator = @fieldParentPtr(DirectArena, "allocator", allocator);
const arena = direct_allocator.next;
// Simple alloc
{
const offset = std.mem.alignForward(arena.offset, new_align);
if (offset + new_size <= std.mem.page_size) {
const slice = @intToPtr([*]u8, @ptrToInt(arena) + offset)[0..new_size];
arena.offset = offset + new_size;
if (old_mem_unaligned.len > 0)
@memcpy(slice.ptr, old_mem_unaligned.ptr, old_mem_unaligned.len);
return slice;
}
}
const next_offset = std.mem.alignForward(@sizeOf(DirectArena), new_align);
if (next_offset + new_size < std.mem.page_size) {
const next_slice = os.mmap(
null,
std.mem.page_size,
os.PROT_READ | os.PROT_WRITE,
os.MAP_PRIVATE | os.MAP_ANONYMOUS,
-1,
0,
) catch return error.OutOfMemory;
const next = @ptrCast(*DirectArena, next_slice.ptr);
next.offset = next_offset;
next.next = arena;
direct_allocator.next = next;
const slice = @intToPtr([*]u8, @ptrToInt(next) + next.offset)[0..new_size];
next.offset += new_size;
if (old_mem_unaligned.len > 0)
@memcpy(slice.ptr, old_mem_unaligned.ptr, old_mem_unaligned.len);
return slice;
} else {
const next_slice = os.mmap(
null,
(std.mem.page_size + next_offset + new_size - 1) & ~@as(usize, std.mem.page_size - 1),
os.PROT_READ | os.PROT_WRITE,
os.MAP_PRIVATE | os.MAP_ANONYMOUS,
-1,
0,
) catch return error.OutOfMemory;
const next = @ptrCast(*DirectArena, next_slice.ptr);
next.offset = next_slice.len;
if (direct_allocator == arena) {
next.next = arena;
direct_allocator.next = next;
} else {
next.next = arena.next.next;
arena.next = next;
}
const slice = @intToPtr([*]u8, @ptrToInt(next) + next_offset)[0 .. next_slice.len - next_offset];
if (old_mem_unaligned.len > 0) {
@memcpy(slice.ptr, old_mem_unaligned.ptr, old_mem_unaligned.len);
// Note: this will save some memory but propably not worthwhile
// if(old_mem_unaligned.len >= std.mem.page_size) {
// const forget = @intToPtr(*DirectArena, @ptrToInt(old_mem_unaligned.ptr) & ~usize(std.mem.page_size-1));
// if(forget == arena) {
// direct_allocator.next = arena.next;
// }
// else {
// var ptr = arena;
// while(ptr.next != forget) : (ptr = ptr.next) {
// warn("forget: {x}, ptr: {x}\n", @ptrToInt(forget), @ptrToInt(ptr));
// }
// ptr.next = forget.next;
// }
// os.munmap(@intToPtr([*]align(std.mem.page_size) u8, @ptrToInt(forget))[0..old_mem_unaligned.len]);
// }
}
return slice;
}
}
}; | zig/direct_arena.zig |
const std = @import("std");
const mem = std.mem;
const expect = std.testing.expect;
const allocator = std.testing.allocator;
const shrink = @import("./shrink.zig");
const bs = @import("./bitstream.zig");
const hamlet = @embedFile("../fixtures/hamlet.txt");
test "shrink_empty" {
const data: [1]u8 = undefined;
var dst: [1]u8 = undefined;
var used: usize = 99;
// Empty src.
dst[0] = 0x42;
try expect(shrink.hwshrink(
@intToPtr([*]const u8, @ptrToInt(&data[0]) + 8), // pointer to outside allowed memory, expecting no one reads it
0,
&dst,
dst.len,
&used,
));
try expect(used == 0);
try expect(dst[0] == 0x42);
// Empty src, empty dst.
try expect(shrink.hwshrink(
@intToPtr([*]const u8, @ptrToInt(&data[0]) + 8), // pointer to outside allowed memory, expecting no one reads it
0,
@intToPtr([*]u8, @ptrToInt(&dst[0]) + 8), // pointer to outside allowed memory, expecting no one reads it
0,
&used,
));
try expect(used == 0);
// Empty dst.
try expect(!shrink.hwshrink(
&data,
data.len,
@intToPtr([*]u8, @ptrToInt(&dst[0]) + 8), // pointer to outside allowed memory, expecting no one reads it
0,
&used,
));
}
// $ curl -O http://cd.textfiles.com/1stcanadian/utils/pkz110/pkz110.exe
// $ unzip pkz110.exe PKZIP.EXE
// $ echo -n ababcbababaaaaaaa > x
// $ dosbox -c "mount c ." -c "c:" -c "pkzip -es x.zip x" -c exit
// $ xxd -i -s 31 -l $(expr $(find X.ZIP -printf %s) - 100) X.ZIP
const lzw_fig5: []const u8 = "ababcbababaaaaaaa";
const lzw_fig5_shrunk = [_]u8{
0x61, 0xc4, 0x04, 0x1c, 0x23, 0xb0, 0x60, 0x98, 0x83, 0x08, 0xc3, 0x00,
};
test "shrink_basic" {
var dst: [100]u8 = undefined;
var used: usize = 0;
try expect(shrink.hwshrink(lzw_fig5.ptr, lzw_fig5.len, &dst, dst.len, &used));
try expect(used == lzw_fig5_shrunk.len);
try expect(mem.eql(u8, dst[0..lzw_fig5_shrunk.len], lzw_fig5_shrunk[0..lzw_fig5_shrunk.len]));
}
fn roundtrip(src: [*]const u8, src_len: usize) !void {
var compressed: []u8 = undefined;
var uncompressed: []u8 = undefined;
var compressed_cap: usize = 0;
var compressed_size: usize = 0;
var uncompressed_size: usize = 0;
var used: usize = 0;
compressed_cap = src_len * 2 + 100;
compressed = try allocator.alloc(u8, compressed_cap);
uncompressed = try allocator.alloc(u8, src_len);
try expect(
shrink.hwshrink(
src,
src_len,
compressed.ptr,
compressed_cap,
&compressed_size,
),
);
try expect(
shrink.hwunshrink(
compressed.ptr,
compressed_size,
&used,
uncompressed.ptr,
src_len,
&uncompressed_size,
) == shrink.unshrnk_stat_t.HWUNSHRINK_OK,
);
try expect(used == compressed_size);
try expect(uncompressed_size == src_len);
try expect(mem.eql(u8, uncompressed[0..src_len], src[0..src_len]));
allocator.free(compressed);
allocator.free(uncompressed);
}
test "shrink_many_codes" {
var src: [25 * 256 * 2]u8 = undefined;
var dst: [src.len * 2]u8 = undefined;
var i: usize = 0;
var j: usize = 0;
var src_size: usize = 0;
var tmp: usize = 0;
// This will churn through new codes pretty fast, causing code size
// increase and partial clearing multiple times.
src_size = 0;
i = 0;
while (i < 25) : (i += 1) {
j = 0;
while (j < 256) : (j += 1) {
src[src_size] = @intCast(u8, i);
src_size += 1;
src[src_size] = @intCast(u8, j);
src_size += 1;
}
}
try roundtrip(&src, src_size);
// Try shrinking into a too small buffer.
// Hit the buffer full case while signaling increased code size.
i = 0;
while (i < 600) : (i += 1) {
try expect(!shrink.hwshrink(&src, src_size, &dst, i, &tmp));
}
// Hit the buffer full case while signaling partial clearing.
i = 11_000;
while (i < 12_000) : (i += 1) {
try expect(!shrink.hwshrink(&src, src_size, &dst, i, &tmp));
}
}
test "shrink_aaa" {
const src_size: usize = 61505 * 1024;
var src: []u8 = undefined;
// This adds codes to the table which are all prefixes of each other.
// Then each partial clearing will create a self-referential code,
// which means that code is lost. Eventually all codes are lost this
// way, and the bytes are all encoded as literals.
src = try allocator.alloc(u8, src_size);
mem.set(u8, src[0..], 'a');
try roundtrip(src.ptr, src_size);
allocator.free(src);
}
test "shrink_hamlet" {
var compressed: [100 * 1024]u8 = [_]u8{0} ** (100 * 1024);
var uncompressed: [hamlet.len]u8 = [_]u8{0} ** hamlet.len;
var compressed_size: usize = 0;
var used: usize = 0;
var uncompressed_size: usize = 0;
try expect(shrink.hwshrink(hamlet, hamlet.len, &compressed, compressed.len, &compressed_size));
// Update if we make compression better.
try expect(compressed_size == 93_900);
// PKZIP 1.10
// pkzip -es a.zip hamlet.txt
// 93900 bytes
try expect(shrink.hwunshrink(
&compressed,
compressed_size,
&used,
&uncompressed,
hamlet.len,
&uncompressed_size,
) == shrink.unshrnk_stat_t.HWUNSHRINK_OK);
try expect(used == compressed_size);
try expect(uncompressed_size == hamlet.len);
try expect(mem.eql(u8, uncompressed[0..], hamlet));
}
test "unshrink_empty" {
var data: [2]u8 = undefined;
var dst: [1]u8 = undefined;
var src_used: usize = 123;
var dst_used: usize = 456;
// Empty src.
dst[0] = 0x42;
try expect(shrink.hwunshrink(
@intToPtr([*]u8, @ptrToInt(&data[1]) + 8), // pointer to outside allowed memory, expecting no one reads it
0,
&src_used,
&dst,
dst.len,
&dst_used,
) == shrink.unshrnk_stat_t.HWUNSHRINK_OK);
try expect(src_used == 0);
try expect(dst_used == 0);
try expect(dst[0] == 0x42);
// Empty src, empty dst.
try expect(shrink.hwunshrink(
@intToPtr([*]u8, @ptrToInt(&data[1]) + 8), // pointer to outside allowed memory, expecting no one reads it
0,
&src_used,
@intToPtr([*]u8, @ptrToInt(&dst[0]) + 8), // pointer to outside allowed memory, expecting no one reads it
0,
&dst_used,
) == shrink.unshrnk_stat_t.HWUNSHRINK_OK);
try expect(src_used == 0);
try expect(dst_used == 0);
// Empty dst.
try expect(shrink.hwunshrink(
&data,
data.len,
&src_used,
@intToPtr([*]u8, @ptrToInt(&dst[0]) + 8), // pointer to outside allowed memory, expecting no one reads it
0,
&dst_used,
) == shrink.unshrnk_stat_t.HWUNSHRINK_FULL);
}
test "unshrink_basic" {
var comp: [100]u8 = undefined;
var decomp: [100]u8 = undefined;
var comp_size: usize = 0;
var comp_used: usize = 0;
var decomp_used: usize = 0;
var os: bs.ostream_t = undefined;
bs.ostream_init(&os, &comp, comp.len);
_ = bs.ostream_write(&os, 'a', 9);
_ = bs.ostream_write(&os, 'b', 9); // New code: 257 = "ab"
_ = bs.ostream_write(&os, 'c', 9); // New code: 258 = "bc"
_ = bs.ostream_write(&os, 257, 9); // New code: 259 = "ca"
_ = bs.ostream_write(&os, 259, 9);
comp_size = bs.ostream_bytes_written(&os);
try expect(shrink.hwunshrink(&comp, comp_size, &comp_used, &decomp, decomp.len, &decomp_used) == shrink.unshrnk_stat_t.HWUNSHRINK_OK);
try expect(comp_used == comp_size);
try expect(decomp_used == 7);
try expect(decomp[0] == 'a');
try expect(decomp[1] == 'b');
try expect(decomp[2] == 'c');
try expect(decomp[3] == 'a'); // 257
try expect(decomp[4] == 'b');
try expect(decomp[5] == 'c'); // 259
try expect(decomp[6] == 'a');
bs.ostream_init(&os, &comp, comp.len);
_ = bs.ostream_write(&os, 'a', 9);
_ = bs.ostream_write(&os, 'b', 9); // New code: 257 = "ab"
_ = bs.ostream_write(&os, 456, 9); // Invalid code!
comp_size = bs.ostream_bytes_written(&os);
try expect(shrink.hwunshrink(&comp, comp_size, &comp_used, &decomp, decomp.len, &decomp_used) == shrink.unshrnk_stat_t.HWUNSHRINK_ERR);
}
test "unshrink_snag" {
// Hit the "KwKwKw" case, or LZW snag, where the decompressor sees the
// next code before it's been added to the table.
var comp: [100]u8 = undefined;
var decomp: [100]u8 = undefined;
var comp_size: usize = 0;
var comp_used: usize = 0;
var decomp_used: usize = 0;
var os: bs.ostream_t = undefined;
bs.ostream_init(&os, &comp, comp.len);
_ = bs.ostream_write(&os, 'a', 9); // Emit "a"
_ = bs.ostream_write(&os, 'n', 9); // Emit "n"; new code: 257 = "an"
_ = bs.ostream_write(&os, 'b', 9); // Emit "b"; new code: 258 = "nb"
_ = bs.ostream_write(&os, 257, 9); // Emit "an"; new code: 259 = "ba"
_ = bs.ostream_write(&os, 260, 9); // The LZW snag
// Emit and add 260 = "ana"
comp_size = bs.ostream_bytes_written(&os);
try expect(shrink.hwunshrink(&comp, comp_size, &comp_used, &decomp, decomp.len, &decomp_used) == shrink.unshrnk_stat_t.HWUNSHRINK_OK);
try expect(comp_used == comp_size);
try expect(decomp_used == 8);
try expect(decomp[0] == 'a');
try expect(decomp[1] == 'n');
try expect(decomp[2] == 'b');
try expect(decomp[3] == 'a'); // 257
try expect(decomp[4] == 'n');
try expect(decomp[5] == 'a'); // 260
try expect(decomp[6] == 'n');
try expect(decomp[7] == 'a');
// Test hitting the LZW snag where the previous code is invalid.
bs.ostream_init(&os, &comp, comp.len);
_ = bs.ostream_write(&os, 'a', 9); // Emit "a"
_ = bs.ostream_write(&os, 'b', 9); // Emit "b"; new code: 257 = "ab"
_ = bs.ostream_write(&os, 'c', 9); // Emit "c"; new code: 258 = "bc"
_ = bs.ostream_write(&os, 258, 9); // Emit "bc"; new code: 259 = "cb"
_ = bs.ostream_write(&os, 256, 9); // Partial clear, dropping codes:
_ = bs.ostream_write(&os, 2, 9); // 257, 258, 259
_ = bs.ostream_write(&os, 257, 9); // LZW snag; previous code is invalid.
comp_size = bs.ostream_bytes_written(&os);
try expect(shrink.hwunshrink(&comp, comp_size, &comp_used, &decomp, decomp.len, &decomp_used) == shrink.unshrnk_stat_t.HWUNSHRINK_ERR);
}
test "unshrink_early_snag" {
// Hit the LZW snag right at the start. Not sure if this can really
// happen, but handle it anyway.
var comp: [100]u8 = undefined;
var decomp: [100]u8 = undefined;
var comp_size: usize = 0;
var comp_used: usize = 0;
var decomp_used: usize = 0;
var os: bs.ostream_t = undefined;
bs.ostream_init(&os, &comp, comp.len);
_ = bs.ostream_write(&os, 'a', 9); // Emit "a"
_ = bs.ostream_write(&os, 257, 9); // The LZW snag
// Emit and add 257 = "aa"
comp_size = bs.ostream_bytes_written(&os);
try expect(shrink.hwunshrink(&comp, comp_size, &comp_used, &decomp, decomp.len, &decomp_used) == shrink.unshrnk_stat_t.HWUNSHRINK_OK);
try expect(comp_used == comp_size);
try expect(decomp_used == 3);
try expect(decomp[0] == 'a');
try expect(decomp[1] == 'a');
try expect(decomp[2] == 'a'); // 257
}
test "unshrink_tricky_first_code" {
var comp: [100]u8 = undefined;
var decomp: [100]u8 = undefined;
var comp_size: usize = 0;
var comp_used: usize = 0;
var decomp_used: usize = 0;
var os: bs.ostream_t = undefined;
bs.ostream_init(&os, &comp, comp.len);
_ = bs.ostream_write(&os, 257, 9); // An unused code.
comp_size = bs.ostream_bytes_written(&os);
try expect(shrink.hwunshrink(&comp, comp_size, &comp_used, &decomp, decomp.len, &decomp_used) == shrink.unshrnk_stat_t.HWUNSHRINK_ERR);
// Handle control codes also for the first code. (Not sure if PKZIP
// can handle that, but we do.)
bs.ostream_init(&os, &comp, comp.len);
_ = bs.ostream_write(&os, 256, 9); // Control code.
_ = bs.ostream_write(&os, 1, 9); // Code size increase.
_ = bs.ostream_write(&os, 'a', 10); // 'a'.
comp_size = bs.ostream_bytes_written(&os);
try expect(shrink.hwunshrink(&comp, comp_size, &comp_used, &decomp, decomp.len, &decomp_used) == shrink.unshrnk_stat_t.HWUNSHRINK_OK);
try expect(decomp_used == 1);
try expect(decomp[0] == 'a');
bs.ostream_init(&os, &comp, comp.len);
_ = bs.ostream_write(&os, 256, 9); // Control code.
_ = bs.ostream_write(&os, 2, 9); // Partial clear.
_ = bs.ostream_write(&os, 'a', 9); // 'a'.
comp_size = bs.ostream_bytes_written(&os);
try expect(shrink.hwunshrink(&comp, comp_size, &comp_used, &decomp, decomp.len, &decomp_used) == shrink.unshrnk_stat_t.HWUNSHRINK_OK);
try expect(decomp_used == 1);
try expect(decomp[0] == 'a');
}
test "unshrink_invalidated_prefix_codes" {
var comp: [100]u8 = undefined;
var decomp: [100]u8 = undefined;
var comp_size: usize = 0;
var comp_used: usize = 0;
var decomp_used: usize = 0;
var os: bs.ostream_t = undefined;
// Code where the prefix code hasn't been re-used.
bs.ostream_init(&os, &comp, comp.len);
_ = bs.ostream_write(&os, 'a', 9); // Emit "a"
_ = bs.ostream_write(&os, 'b', 9); // Emit "b"; new code: 257 = "ab"
_ = bs.ostream_write(&os, 'c', 9); // Emit "c"; new code: 258 = "bc"
_ = bs.ostream_write(&os, 'd', 9); // Emit "d"; new code: 259 = "cd"
_ = bs.ostream_write(&os, 259, 9); // Emit "cd"; new code: 260 = "dc"
_ = bs.ostream_write(&os, 256, 9); // Partial clear, dropping codes:
_ = bs.ostream_write(&os, 2, 9); // 257, 258, 259, 260
_ = bs.ostream_write(&os, 'x', 9); // Emit "x"; new code: 257 = {259}+"x"
_ = bs.ostream_write(&os, 257, 9); // Error: 257's prefix is invalid.
comp_size = bs.ostream_bytes_written(&os);
try expect(shrink.hwunshrink(&comp, comp_size, &comp_used, &decomp, decomp.len, &decomp_used) == shrink.unshrnk_stat_t.HWUNSHRINK_ERR);
// Code there the prefix code has been re-used.
bs.ostream_init(&os, &comp, comp.len);
_ = bs.ostream_write(&os, 'a', 9); // Emit "a"
_ = bs.ostream_write(&os, 'b', 9); // Emit "b"; new code: 257 = "ab"
_ = bs.ostream_write(&os, 'c', 9); // Emit "c"; new code: 258 = "bc"
_ = bs.ostream_write(&os, 'd', 9); // Emit "d"; new code: 259 = "cd"
_ = bs.ostream_write(&os, 259, 9); // Emit "cd"; new code: 260 = "dc"
_ = bs.ostream_write(&os, 256, 9); // Partial clear, dropping codes:
_ = bs.ostream_write(&os, 2, 9); // 257, 258, 259, 260
_ = bs.ostream_write(&os, 'x', 9); // Emit "x"; new code: 257 = {259}+"x"
_ = bs.ostream_write(&os, 'y', 9); // Emit "y"; new code: 258 = "xy"
_ = bs.ostream_write(&os, 'z', 9); // Emit "z"; new code: 259 = "yz"
_ = bs.ostream_write(&os, '0', 9); // Emit "0"; new code: 260 = "z0"
_ = bs.ostream_write(&os, 257, 9); // Emit "yzx"
comp_size = bs.ostream_bytes_written(&os);
try expect(shrink.hwunshrink(&comp, comp_size, &comp_used, &decomp, decomp.len, &decomp_used) == shrink.unshrnk_stat_t.HWUNSHRINK_OK);
try expect(comp_used == comp_size);
try expect(decomp_used == 13);
try expect(decomp[0] == 'a');
try expect(decomp[1] == 'b');
try expect(decomp[2] == 'c');
try expect(decomp[3] == 'd');
try expect(decomp[4] == 'c');
try expect(decomp[5] == 'd');
try expect(decomp[6] == 'x');
try expect(decomp[7] == 'y');
try expect(decomp[8] == 'z');
try expect(decomp[9] == '0');
try expect(decomp[10] == 'y');
try expect(decomp[11] == 'z');
try expect(decomp[12] == 'x');
// Code where the prefix gets re-used by the next code (i.e. the LZW
// snag). This is the trickiest case.
bs.ostream_init(&os, &comp, comp.len);
_ = bs.ostream_write(&os, 'a', 9); // Emit "a"
_ = bs.ostream_write(&os, 'b', 9); // Emit "b"; new code: 257 = "ab"
_ = bs.ostream_write(&os, 'c', 9); // Emit "c"; new code: 258 = "bc"
_ = bs.ostream_write(&os, 'd', 9); // Emit "d"; new code: 259 = "cd"
_ = bs.ostream_write(&os, 'e', 9); // Emit "e"; new code: 260 = "de"
_ = bs.ostream_write(&os, 'f', 9); // Emit "f"; new code: 261 = "ef"
_ = bs.ostream_write(&os, 261, 9); // Emit "ef"; new code: 262 = "fe"
_ = bs.ostream_write(&os, 256, 9); // Partial clear, dropping codes:
_ = bs.ostream_write(&os, 2, 9); // 257, 258, 259, 260, 261, 262
_ = bs.ostream_write(&os, 'a', 9); // Emit "a"; new code: 257={261}+"a"
_ = bs.ostream_write(&os, 'n', 9); // Emit "n"; new code: 258 = "an"
_ = bs.ostream_write(&os, 'b', 9); // Emit "b"; new code: 259 = "nb"
_ = bs.ostream_write(&os, 258, 9); // Emit "an"; new code: 260 = "ba"
_ = bs.ostream_write(&os, 257, 9); // Emit "anaa". (new old code 261="ana")
// Just to be sure 261 and 257 are represented correctly now:
_ = bs.ostream_write(&os, 261, 9); // Emit "ana"; new code 262="aana"
_ = bs.ostream_write(&os, 257, 9); // Emit "anaa"; new code 263="aanaa"
comp_size = bs.ostream_bytes_written(&os);
try expect(shrink.hwunshrink(&comp, comp_size, &comp_used, &decomp, decomp.len, &decomp_used) == shrink.unshrnk_stat_t.HWUNSHRINK_OK);
try expect(comp_used == comp_size);
try expect(decomp_used == 24);
try expect(decomp[0] == 'a');
try expect(decomp[1] == 'b');
try expect(decomp[2] == 'c');
try expect(decomp[3] == 'd');
try expect(decomp[4] == 'e');
try expect(decomp[5] == 'f');
try expect(decomp[6] == 'e');
try expect(decomp[7] == 'f');
try expect(decomp[8] == 'a');
try expect(decomp[9] == 'n');
try expect(decomp[10] == 'b');
try expect(decomp[11] == 'a');
try expect(decomp[12] == 'n');
try expect(decomp[13] == 'a');
try expect(decomp[14] == 'n');
try expect(decomp[15] == 'a');
try expect(decomp[16] == 'a');
try expect(decomp[17] == 'a');
try expect(decomp[18] == 'n');
try expect(decomp[19] == 'a');
try expect(decomp[20] == 'a');
try expect(decomp[21] == 'n');
try expect(decomp[22] == 'a');
try expect(decomp[23] == 'a');
}
test "unshrink_self_prefix" {
var comp: [100]u8 = undefined;
var decomp: [100]u8 = undefined;
var comp_size: usize = 0;
var comp_used: usize = 0;
var decomp_used: usize = 0;
var os: bs.ostream_t = undefined;
// Create self-prefixed code and try to use it.
bs.ostream_init(&os, &comp, comp.len);
_ = bs.ostream_write(&os, 'a', 9); // Emit "a"
_ = bs.ostream_write(&os, 'b', 9); // Emit "b"; new code: 257 = "ab"
_ = bs.ostream_write(&os, 257, 9); // Emit "ab"; new code: 258 = "ba"
_ = bs.ostream_write(&os, 256, 9); // Partial clear, dropping codes:
_ = bs.ostream_write(&os, 2, 9); // 257, 258
_ = bs.ostream_write(&os, 'a', 9); // Emit "a"; new code: 257 = {257}+"a"
_ = bs.ostream_write(&os, 257, 9); // Error: 257 cannot be used.
comp_size = bs.ostream_bytes_written(&os);
try expect(shrink.hwunshrink(&comp, comp_size, &comp_used, &decomp, decomp.len, &decomp_used) == shrink.unshrnk_stat_t.HWUNSHRINK_ERR);
// Create self-prefixed code and check that it's not recycled by
// partial clearing.
bs.ostream_init(&os, &comp, comp.len);
_ = bs.ostream_write(&os, 'a', 9); // Emit "a"
_ = bs.ostream_write(&os, 'b', 9); // Emit "b"; new code: 257 = "ab"
_ = bs.ostream_write(&os, 257, 9); // Emit "ab"; new code: 258 = "ba"
_ = bs.ostream_write(&os, 256, 9); // Partial clear, dropping codes:
_ = bs.ostream_write(&os, 2, 9); // 257, 258
_ = bs.ostream_write(&os, 'a', 9); // Emit "a"; new code: 257 = {257}+"a"
_ = bs.ostream_write(&os, 'b', 9); // Emit "b"; new code: 258 = "ab"
_ = bs.ostream_write(&os, 256, 9); // Partial clear, dropping codes:
_ = bs.ostream_write(&os, 2, 9); // 258 (Note that 257 isn't re-used)
_ = bs.ostream_write(&os, 'x', 9); // Emit "x"; new code: 258 = "bx"
_ = bs.ostream_write(&os, 258, 9); // Emit "bx".
comp_size = bs.ostream_bytes_written(&os);
try expect(shrink.hwunshrink(&comp, comp_size, &comp_used, &decomp, decomp.len, &decomp_used) == shrink.unshrnk_stat_t.HWUNSHRINK_OK);
try expect(comp_used == comp_size);
try expect(decomp_used == 9);
try expect(decomp[0] == 'a');
try expect(decomp[1] == 'b');
try expect(decomp[2] == 'a');
try expect(decomp[3] == 'b');
try expect(decomp[4] == 'a');
try expect(decomp[5] == 'b');
try expect(decomp[6] == 'x');
try expect(decomp[7] == 'b');
try expect(decomp[8] == 'x');
}
test "unshrink_too_short" {
// Test with too short src and dst.
var comp: [100]u8 = undefined;
var decomp: [100]u8 = undefined;
var comp_size: usize = 0;
var comp_used: usize = 0;
var decomp_used: usize = 0;
var os: bs.ostream_t = undefined;
var i: usize = 0;
var s: shrink.unshrnk_stat_t = undefined;
// Code where the prefix gets re-used by the next code (i.e. the LZW
// snag). Copied from test_unshrink_invalidated_prefix_codes.
bs.ostream_init(&os, &comp, comp.len);
_ = bs.ostream_write(&os, 'a', 9); // Emit "a"
_ = bs.ostream_write(&os, 'b', 9); // Emit "b"; new code: 257 = "ab"
_ = bs.ostream_write(&os, 'c', 9); // Emit "c"; new code: 258 = "bc"
_ = bs.ostream_write(&os, 'd', 9); // Emit "d"; new code: 259 = "cd"
_ = bs.ostream_write(&os, 'e', 9); // Emit "e"; new code: 260 = "de"
_ = bs.ostream_write(&os, 'f', 9); // Emit "f"; new code: 261 = "ef"
_ = bs.ostream_write(&os, 261, 9); // Emit "ef"; new code: 262 = "fe"
_ = bs.ostream_write(&os, 256, 9); // Partial clear, dropping codes:
_ = bs.ostream_write(&os, 2, 9); // 257, 258, 259, 260, 261, 262
_ = bs.ostream_write(&os, 'a', 9); // Emit "a"; new code: 257={261}+"a"
_ = bs.ostream_write(&os, 'n', 9); // Emit "n"; new code: 258 = "an"
_ = bs.ostream_write(&os, 'b', 9); // Emit "b"; new code: 259 = "nb"
_ = bs.ostream_write(&os, 258, 9); // Emit "an"; new code: 260 = "ba"
_ = bs.ostream_write(&os, 257, 9); // Emit "anaa". (new old code 261="ana")
// Just to be sure 261 and 257 are represented correctly now:
_ = bs.ostream_write(&os, 261, 9); // Emit "ana"; new code 262="aana"
_ = bs.ostream_write(&os, 257, 9); // Emit "anaa"; new code 263="aanaa"
comp_size = bs.ostream_bytes_written(&os);
// This is the expected full output.
try expect(shrink.hwunshrink(
&comp,
comp_size,
&comp_used,
&decomp,
decomp.len,
&decomp_used,
) == shrink.unshrnk_stat_t.HWUNSHRINK_OK);
try expect(comp_used == comp_size);
try expect(decomp_used == 24);
try expect(mem.eql(u8, decomp[0..24], "abcdefefanbananaaanaanaa"));
// Test not enough input bytes. It should error or output something shorter.
i = 0;
while (i < comp_size) : (i += 1) {
s = shrink.hwunshrink(&comp, i, &comp_used, &decomp, decomp.len, &decomp_used);
if (s == shrink.unshrnk_stat_t.HWUNSHRINK_OK) {
try expect(comp_used <= i);
try expect(decomp_used < 24);
try expect(
mem.eql(u8, decomp[0..decomp_used], "abcdefefanbananaaanaanaa"[0..decomp_used]),
);
} else {
try expect(s == shrink.unshrnk_stat_t.HWUNSHRINK_ERR);
}
}
// Test not having enough room for the output.
i = 0;
while (i < 24) : (i += 1) {
decomp[i] = 0x42;
s = shrink.hwunshrink(&comp, comp_size, &comp_used, &decomp, i, &decomp_used);
try expect(s == shrink.unshrnk_stat_t.HWUNSHRINK_FULL);
try expect(decomp[i] == 0x42);
}
}
test "unshrink_bad_control_code" {
var comp: [100]u8 = undefined;
var decomp: [100]u8 = undefined;
var comp_size: usize = 0;
var comp_used: usize = 0;
var decomp_used: usize = 0;
var os: bs.ostream_t = undefined;
var i: usize = 0;
var codesize: usize = 0;
// Only 1 and 2 are valid control code values.
bs.ostream_init(&os, &comp, comp.len);
_ = bs.ostream_write(&os, 'a', 9); // Emit "a"
_ = bs.ostream_write(&os, 256, 9);
_ = bs.ostream_write(&os, 3, 9); // Invalid control code.
comp_size = bs.ostream_bytes_written(&os);
try expect(shrink.hwunshrink(&comp, comp_size, &comp_used, &decomp, decomp.len, &decomp_used) == shrink.unshrnk_stat_t.HWUNSHRINK_ERR);
// Try increasing the code size too much.
codesize = 9;
bs.ostream_init(&os, &comp, comp.len);
_ = bs.ostream_write(&os, 'a', codesize); // Emit "a"
i = 0;
while (i < 10) : (i += 1) {
_ = bs.ostream_write(&os, 256, codesize);
_ = bs.ostream_write(&os, 1, codesize); // Increase code size.
codesize += 1;
}
_ = bs.ostream_write(&os, 'b', codesize); // Emit "b"
comp_size = bs.ostream_bytes_written(&os);
try expect(shrink.hwunshrink(&comp, comp_size, &comp_used, &decomp, decomp.len, &decomp_used) == shrink.unshrnk_stat_t.HWUNSHRINK_ERR);
}
test "unshrink_lzw_fig5" {
var dst: [100]u8 = undefined;
var src_used: usize = 0;
var dst_used: usize = 0;
try expect(shrink.hwunshrink(&lzw_fig5_shrunk, lzw_fig5_shrunk.len, &src_used, &dst, dst.len, &dst_used) == shrink.unshrnk_stat_t.HWUNSHRINK_OK);
try expect(src_used == lzw_fig5_shrunk.len);
try expect(dst_used == lzw_fig5.len);
try expect(mem.eql(u8, dst[0..lzw_fig5.len], lzw_fig5[0..]));
} | src/shrink_test.zig |
const std = @import("std");
const t = std.testing;
const base62 = @import("./base62.zig");
const Nil = KSUID{};
pub const Error = error{
InvalidLength,
};
pub const KSUID = struct {
const Self = @This();
pub const epochStamp: i64 = 1400000000;
data: [20]u8 = [_]u8{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
pub fn random(rand: std.rand.Random) KSUID {
// Get a calendar timestamp, in seconds, relative to UTC 1970-01-01.
return randomWithTimestamp(rand, std.time.timestamp());
}
pub fn randomWithTimestamp(rand: std.rand.Random, unixTimestamp: i64) KSUID {
var k = KSUID{};
rand.bytes(k.data[4..]);
const ts = @intCast(u32, unixTimestamp - epochStamp);
std.mem.writeIntBig(u32, k.data[0..4], ts);
return k;
}
pub fn timestamp(self: *const Self) i64 {
return @intCast(i64, self.rawTimestamp()) + epochStamp;
}
pub fn rawTimestamp(self: *const Self) u32 {
return std.mem.readIntBig(u32, self.data[0..4]);
}
pub fn payload(self: *const Self) *const [16]u8 {
return self.data[4..];
}
pub fn parse(data: []const u8) !KSUID {
if (data.len < 27) {
return error.InvalidLength;
}
var k = KSUID{};
_ = try base62.fastDecode(&k.data, data[0..27]);
return k;
}
pub fn format(self: *const Self, dest: *[27]u8) []const u8 {
return base62.fastEncode(dest, &self.data);
}
pub fn fmt(self: *const Self) std.fmt.Formatter(formatKSUID) {
return .{ .data = self };
}
};
pub fn formatKSUID(
ksuid: *const KSUID,
comptime fmt: []const u8,
options: std.fmt.FormatOptions,
writer: anytype,
) !void {
_ = fmt;
_ = options;
var buf: [27]u8 = undefined;
_ = ksuid.format(&buf);
try writer.writeAll(&buf);
}
test "new" {
const a = KSUID{};
try t.expectEqual(Nil, a);
try t.expectEqual(@as(u32, 0), a.rawTimestamp());
try t.expectEqual([_]u8{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, a.payload().*);
}
test "parse" {
const a = try KSUID.parse("1srOrx2ZWZBpBUvZwXKQmoEYga2");
//std.debug.print("payload[{s}]\n", .{std.fmt.fmtSliceHexUpper(a.payload())});
try t.expectEqual(@as(i64, 1621627443), a.timestamp());
var buf: [16]u8 = undefined;
const expected = try std.fmt.hexToBytes(&buf, "E1933E37F275708763ADC7745AF5E7F2");
try t.expectEqualSlices(u8, expected, a.payload());
if (KSUID.parse("***************************")) |_| {
return error.ExpectedError;
} else |err| if (err != error.InvalidCharacter) {
return err;
}
if (KSUID.parse("123")) |_| {
return error.ExpectedError;
} else |err| if (err != error.InvalidLength) {
return err;
}
if (KSUID.parse("fffffffffffffffffffffffffff")) |_| {
return error.ExpectedError;
} else |err| if (err != error.DestTooShort) {
return err;
}
const max = try KSUID.parse("aWgEPTl1tmebfsQzFP4bxwgy80V");
try t.expectEqual(@as(i64, 5694967295), max.timestamp());
try t.expectEqualSlices(u8, &[_]u8{0xff} ** 16, max.payload());
}
test "format" {
var buf: [20]u8 = undefined;
_ = try std.fmt.hexToBytes(&buf, "0669F7EFB5A1CD34B5F99D1154FB6853345C9735");
var fmtbuf: [27]u8 = undefined;
{
const a = KSUID{ .data = buf };
try t.expectEqualSlices(u8, "0ujtsYcgvSTl8PAuAdqWYSMnLOv", a.format(&fmtbuf));
}
// min
{
const a = KSUID{};
try t.expectEqualSlices(u8, "000000000000000000000000000", a.format(&fmtbuf));
}
// max
{
const a = KSUID{ .data = [_]u8{0xff} ** 20 };
try t.expectEqualSlices(u8, "aWgEPTl1tmebfsQzFP4bxwgy80V", a.format(&fmtbuf));
}
}
test "formatter" {
const a = KSUID{};
var fmtbuf: [27]u8 = undefined;
_ = try std.fmt.bufPrint(&fmtbuf, "{s}", .{a.fmt()});
try t.expectEqualSlices(u8, "000000000000000000000000000", &fmtbuf);
}
test "random" {
var prng = std.rand.DefaultPrng.init(0);
const a = KSUID.random(prng.random());
//var fmtbuf: [27]u8 = undefined;
//std.debug.print("random[{s}]\n", .{a.format(&fmtbuf)});
try t.expect(a.timestamp() != 0);
//std.debug.print("payload[{s}]\n", .{std.fmt.fmtSliceHexUpper(a.payload())});
var buf: [16]u8 = undefined;
const expected = try std.fmt.hexToBytes(&buf, "DF230B49615D175307D580C33D6FDA61");
try t.expectEqualSlices(u8, expected, a.payload());
} | src/ksuid.zig |
const std = @import("std");
const data = @import("../../gen2/data.zig");
const assert = std.debug.assert;
const Type = data.Type;
pub const Item = enum(u8) {
None,
PinkBow, // Normal
BlackBelt, // Fighting
SharpBeak, // Flying
PoisonBarb, // Poison
SoftSand, // Ground
HardStone, // Rock
SilverPowder, // Bug
SpellTag, // Ghost
MetalCoat, // Steel
PolkadotBow, // ??? (Normal)
Charcoal, // Fire
MysticWater, // Water
MiracleSeed, // Grass
Magnet, // Electric
TwistedSpoon, // Psychic
NeverMeltIce, // Ice
DragonScale, // Dragon
BlackGlasses, // Dark
MasterBall,
UltraBall,
BrightPowder, // BRIGHTPOWDER
GreatBall,
PokeBall,
TownMap,
MoonStone,
Antidote,
BurnHeal,
IceHeal,
Awakening,
ParylzeHeal,
FullRestore,
MaxPotion,
HyperPotion,
SuperPotion,
Potion,
EscapeRope,
Repel,
MaxElixir,
FireStone,
ThunderStone,
WaterStone,
HPUp,
Protein,
Iron,
Carbos,
LuckyPunch,
Calcium,
RareCandy,
XAccuracy,
LeafStone,
MetalPowder, // METAL_POWDER
Nugget,
PokeDoll,
FullHeal,
Revive,
MaxRevive,
GuardSpec,
SuperRepel,
MaxRepel,
DireHit,
FreshWater,
SodaPop,
Lemonade,
XAttack,
XDefend,
XSpeed,
XSpecial,
PokeFlute,
ExpShare,
SilverLeaf,
PPUp,
Ether,
MaxEther,
Elixir,
MoomooMilk,
QuickClaw, // QUICK_CLAW
GoldLeaf,
KingsRock, // FLINCH
RedApricorn,
TinyMushroom,
BigMushroom,
BlueApricorn,
AmuletCoin, // AMULET_COIN
YellowApricorn,
GreenApricorn,
CleanseTag, // CLEANSE_TAG
WhiteApricorn,
BlackApricorn,
PinkApricorn,
SlowpokeTail,
Stick,
SmokeBall, // ESCAPE
Pearl,
BigPearl,
Everstone,
RageCandyBar,
ThickClub,
FocusBand, // FOCUS_BAND
EnergyPowder,
EnergyRoot,
HealPowder,
RevivalHerb,
LuckyEgg,
Stardust,
StarPiece,
BerryJuice, // BERRY
ScopeLens, // CRITICAL_UP
DragonFang,
Leftovers, // LEFTOVERS
BerserkGene,
SacredAsh,
HeavyBall,
LevelBall,
LureBall,
FastBall,
LightBall,
FriendBall,
MoonBall,
LoveBall,
NormalBox,
GorgeousBox,
SunStone,
UpGrade,
ParkBall,
BrickPiece,
TM01,
TM02,
TM03,
TM04,
TM05,
TM06,
TM07,
TM08,
TM09,
TM10,
TM11,
TM12,
TM13,
TM14,
TM15,
TM16,
TM17,
TM18,
TM19,
TM20,
TM21,
TM22,
TM23,
TM24,
TM25,
TM26,
TM27,
TM28,
TM29,
TM30,
TM31,
TM32,
TM33,
TM34,
TM35,
TM36,
TM37,
TM38,
TM39,
TM40,
TM41,
TM42,
TM43,
TM44,
TM45,
TM46,
TM47,
TM48,
TM49,
TM50,
FlowerMail,
SurfMail,
LightBlueMail,
PortrailMail,
LovelyMail,
EonMail,
MorphMail,
BlueSkyMail,
MusicMail,
MirageMail,
PSNCureBerry, // HEAL_POISON
PRZCureBerry, // HEAL_PARALYZE
BurntBerry, // HEAL_FREEZE
IceBerry, // HEAL_BURN
BitterBerry, // HEAL_CONFUSION
MintBerry, // HEAL_SLEEP
MiracleBerry, // HEAL_STATUS
MysteryBerry, // RESTORE_PP
Berry, // BERRY
GoldBerry, // BERRY
comptime {
assert(@sizeOf(Item) == 1);
}
pub inline fn boost(item: Item) ?Type {
assert(item != .None);
if (item == .PolkadotBow) return .Normal;
return if (@enumToInt(item) <= 18) @intToEnum(Type, @enumToInt(item) - 1) else null;
}
pub inline fn mail(item: Item) bool {
assert(item != .None);
return @enumToInt(item) > 175 and @enumToInt(item) <= 185;
}
pub inline fn berry(item: Item) bool {
assert(item != .None);
return @enumToInt(item) > 185;
}
}; | src/lib/gen2/data/items.zig |
const std = @import("std");
const builtin = @import("builtin");
const Allocator = std.mem.Allocator;
const VM = @import("./vm.zig").VM;
const _compiler = @import("./compiler.zig");
const Compiler = _compiler.Compiler;
const CompileError = _compiler.CompileError;
const ObjString = @import("./obj.zig").ObjString;
fn runFile(allocator: Allocator, file_name: []const u8, args: ?[][:0]u8, testing: bool) !void {
var strings = std.StringHashMap(*ObjString).init(allocator);
var imports = std.StringHashMap(Compiler.ScriptImport).init(allocator);
var vm = try VM.init(allocator, &strings);
var compiler = Compiler.init(allocator, &strings, &imports, false);
defer {
vm.deinit();
compiler.deinit();
strings.deinit();
var it = imports.iterator();
while (it.next()) |kv| {
kv.value_ptr.*.globals.deinit();
}
imports.deinit();
}
var file = std.fs.cwd().openFile(file_name, .{}) catch {
std.debug.print("File not found", .{});
return;
};
defer file.close();
const source = try allocator.alloc(u8, (try file.stat()).size);
defer allocator.free(source);
_ = try file.readAll(source);
if (try compiler.compile(source, file_name, testing)) |function| {
_ = try vm.interpret(function, args);
} else {
return CompileError.Recoverable;
}
}
pub fn main() !void {
var gpa = std.heap.GeneralPurposeAllocator(.{ .safety = true }){};
var allocator: Allocator = if (builtin.mode == .Debug)
gpa.allocator()
else
std.heap.c_allocator;
var args: [][:0]u8 = try std.process.argsAlloc(allocator);
defer std.process.argsFree(allocator, args);
// TODO: use https://github.com/Hejsil/zig-clap
var testing: bool = false;
for (args) |arg, index| {
if (index > 0) {
if (index == 1 and std.mem.eql(u8, arg, "test")) {
testing = true;
} else {
runFile(allocator, arg, args[index..], testing) catch {
// TODO: should probably choses appropriate error code
std.os.exit(1);
};
std.os.exit(0);
}
}
}
}
test "Testing buzz" {
var gpa = std.heap.GeneralPurposeAllocator(.{
.safety = true,
}){};
var allocator: Allocator = if (builtin.mode == .Debug)
gpa.allocator()
else
std.heap.c_allocator;
var test_dir = try std.fs.cwd().openDir("tests", .{ .iterate = true });
var it = test_dir.iterate();
var success = true;
var count: usize = 0;
var fail_count: usize = 0;
while (try it.next()) |file| : (count += 1) {
if (file.kind == .File) {
var file_name: []u8 = try allocator.alloc(u8, 6 + file.name.len);
defer allocator.free(file_name);
var had_error: bool = false;
runFile(allocator, try std.fmt.bufPrint(file_name, "tests/{s}", .{file.name}), null, true) catch {
std.debug.print("\u{001b}[31m[{s}... ✕]\u{001b}[0m\n", .{file.name});
had_error = true;
success = false;
fail_count += 1;
};
if (!had_error) {
std.debug.print("\u{001b}[32m[{s}... ✓]\u{001b}[0m\n", .{file.name});
}
}
}
if (success) {
std.debug.print("\n\u{001b}[32m", .{});
} else {
std.debug.print("\n\u{001b}[31m", .{});
}
std.debug.print("Ran {}, Failed: {}\u{001b}[0m\n", .{
count,
fail_count,
});
std.os.exit(if (success) 0 else 1);
} | src/main.zig |
const Object = @import("Object.zig");
const std = @import("std");
const Symbol = @import("Symbol.zig");
const types = @import("types.zig");
const Wasm = @import("Wasm.zig");
const fs = std.fs;
const leb = std.leb;
const log = std.log.scoped(.zwld);
/// Writes the given `Wasm` object into a binary file as-is.
pub fn emit(wasm: *Wasm, gpa: std.mem.Allocator) !void {
const writer = wasm.file.writer();
const file = wasm.file;
// magic bytes and wasm version
try emitWasmHeader(writer);
// emit sections
if (wasm.types.count() != 0) {
log.debug("Writing 'Types' section ({d})", .{wasm.types.count()});
const offset = try reserveSectionHeader(file);
for (wasm.types.items.items) |type_entry| {
try emitType(type_entry, writer);
}
try emitSectionHeader(file, offset, .type, wasm.types.count());
}
if (wasm.imports.symbolCount() != 0 or wasm.options.import_memory) {
const count = wasm.imports.symbolCount() + @boolToInt(wasm.options.import_memory);
log.debug("Writing 'Imports' section ({d})", .{count});
const offset = try reserveSectionHeader(file);
if (wasm.options.import_memory) {
const mem_import: std.wasm.Import = .{
.module_name = "env",
.name = "memory",
.kind = .{ .memory = wasm.memories.limits },
};
try emitImport(mem_import, writer);
}
for (wasm.imports.symbols()) |sym_with_loc| {
try emitImportSymbol(wasm, sym_with_loc, writer);
}
// TODO: Also emit GOT symbols
try emitSectionHeader(file, offset, .import, count);
}
if (wasm.functions.count() != 0) {
log.debug("Writing 'Functions' section ({d})", .{wasm.functions.count()});
const offset = try reserveSectionHeader(file);
for (wasm.functions.items.items) |func| {
try emitFunction(func, writer);
}
try emitSectionHeader(file, offset, .function, wasm.functions.count());
}
if (wasm.tables.count() != 0) {
log.debug("Writing 'Tables' section ({d})", .{wasm.tables.count()});
const offset = try reserveSectionHeader(file);
for (wasm.tables.items.items) |table| {
try emitTable(table, writer);
}
try emitSectionHeader(file, offset, .table, wasm.tables.count());
}
if (!wasm.options.import_memory) {
log.debug("Writing 'Memory' section", .{});
const offset = try reserveSectionHeader(file);
try emitLimits(wasm.memories.limits, writer);
try emitSectionHeader(file, offset, .memory, 1);
}
if (wasm.globals.count() != 0) {
log.debug("Writing 'Globals' section ({d})", .{wasm.globals.count()});
const offset = try reserveSectionHeader(file);
for (wasm.globals.items.items) |global| {
try emitGlobal(global, writer);
}
try emitSectionHeader(file, offset, .global, wasm.globals.count());
}
if (wasm.exports.count() != 0) {
log.debug("Writing 'Exports' section ({d})", .{wasm.exports.count()});
const offset = try reserveSectionHeader(file);
for (wasm.exports.items.items) |exported| {
try emitExport(exported, writer);
}
try emitSectionHeader(file, offset, .@"export", wasm.exports.count());
}
if (wasm.entry) |entry_index| {
const offset = try reserveSectionHeader(file);
try emitSectionHeader(file, offset, .start, entry_index);
}
if (wasm.elements.functionCount() != 0) {
log.debug("Writing 'Element' section (1)", .{});
const offset = try reserveSectionHeader(file);
try emitElement(wasm, writer);
try emitSectionHeader(file, offset, .element, 1);
}
if (wasm.code_section_index) |index| {
log.debug("Writing 'Code' section ({d})", .{wasm.functions.count()});
const offset = try reserveSectionHeader(file);
var atom = wasm.atoms.get(index).?.getFirst();
while (true) {
try leb.writeULEB128(writer, atom.size);
try writer.writeAll(atom.code.items);
if (atom.next) |next| {
atom = next;
} else break;
}
try emitSectionHeader(file, offset, .code, wasm.functions.count());
}
if (wasm.data_segments.count() != 0) {
const data_count = @intCast(u32, wasm.dataCount());
log.debug("Writing 'Data' section ({d})", .{data_count});
const offset = try reserveSectionHeader(file);
var it = wasm.data_segments.iterator();
while (it.next()) |entry| {
// do not output the 'bss' section
if (std.mem.eql(u8, entry.key_ptr.*, ".bss") and !wasm.options.import_memory) continue;
const atom_index = entry.value_ptr.*;
var atom = wasm.atoms.getPtr(atom_index).?.*.getFirst();
const segment = wasm.segments.items[atom_index];
try leb.writeULEB128(writer, @as(u32, 0)); // flag and memory index (always 0);
try emitInitExpression(.{ .i32_const = @bitCast(i32, segment.offset) }, writer);
try leb.writeULEB128(writer, segment.size);
var current_offset: u32 = 0;
while (true) {
// TODO: Verify if this is faster than allocating segment's size
// Setting all zeroes, memcopy all segments and then writing.
if (current_offset != atom.offset) {
const diff = atom.offset - current_offset;
try writer.writeByteNTimes(0, diff);
current_offset += diff;
}
std.debug.assert(current_offset == atom.offset);
std.debug.assert(atom.code.items.len == atom.size);
try writer.writeAll(atom.code.items);
current_offset += atom.size;
if (atom.next) |next| {
atom = next;
} else {
// Also make sure that if the last atom has extra bytes, we write 0's.
if (current_offset != segment.size) {
try writer.writeByteNTimes(0, segment.size - current_offset);
current_offset += segment.size - current_offset;
}
break;
}
}
std.debug.assert(current_offset == segment.size);
}
try emitSectionHeader(file, offset, .data, data_count);
}
// names section
{
const func_count: u32 = wasm.functions.count() + wasm.imports.functionCount();
const global_count: u32 = wasm.globals.count() + wasm.imports.globalCount();
var funcs = try std.ArrayList(*const Symbol).initCapacity(gpa, func_count);
defer funcs.deinit();
var globals = try std.ArrayList(*const Symbol).initCapacity(gpa, global_count);
defer globals.deinit();
for (wasm.resolved_symbols.keys()) |sym_with_loc| {
const symbol = sym_with_loc.getSymbol(wasm);
switch (symbol.tag) {
.function => funcs.appendAssumeCapacity(symbol),
.global => globals.appendAssumeCapacity(symbol),
else => {}, // do not emit 'names' section for other symbols
}
}
std.sort.sort(*const Symbol, funcs.items, {}, lessThan);
std.sort.sort(*const Symbol, globals.items, {}, lessThan);
const offset = try reserveCustomSectionHeader(file);
try leb.writeULEB128(writer, @intCast(u32, "name".len));
try writer.writeAll("name");
try emitNameSection(0x01, gpa, funcs.items, writer);
try emitNameSection(0x07, gpa, globals.items, writer);
try emitDataNamesSection(wasm, gpa, writer);
try emitCustomHeader(file, offset);
}
}
/// Sorts symbols based on the index of the object they target
fn lessThan(context: void, lhs: *const Symbol, rhs: *const Symbol) bool {
_ = context;
return lhs.index < rhs.index;
}
fn emitSymbol(symbol: *const Symbol, writer: anytype) !void {
try leb.writeULEB128(writer, symbol.index);
try leb.writeULEB128(writer, @intCast(u32, symbol.name.len));
try writer.writeAll(symbol.name);
}
fn emitNameSection(name_type: u8, gpa: std.mem.Allocator, items: anytype, writer: anytype) !void {
var section_list = std.ArrayList(u8).init(gpa);
defer section_list.deinit();
const sec_writer = section_list.writer();
try leb.writeULEB128(sec_writer, @intCast(u32, items.len));
for (items) |sym| try emitSymbol(sym, sec_writer);
try leb.writeULEB128(writer, name_type);
try leb.writeULEB128(writer, @intCast(u32, section_list.items.len));
try writer.writeAll(section_list.items);
}
fn emitDataNamesSection(wasm: *Wasm, gpa: std.mem.Allocator, writer: anytype) !void {
var section_list = std.ArrayList(u8).init(gpa);
defer section_list.deinit();
const sec_writer = section_list.writer();
try leb.writeULEB128(sec_writer, @intCast(u32, wasm.data_segments.count()));
for (wasm.data_segments.keys()) |key, index| {
try leb.writeULEB128(sec_writer, @intCast(u32, index));
try leb.writeULEB128(sec_writer, @intCast(u32, key.len));
try sec_writer.writeAll(key);
}
try leb.writeULEB128(writer, @as(u8, 0x09));
try leb.writeULEB128(writer, @intCast(u32, section_list.items.len));
try writer.writeAll(section_list.items);
}
fn emitWasmHeader(writer: anytype) !void {
try writer.writeAll(&std.wasm.magic);
try writer.writeIntLittle(u32, 1); // version
}
/// Reserves enough space within the file to write our section header.
/// Returns the offset into the file where the header will be written.
fn reserveSectionHeader(file: fs.File) !u64 {
// section id, section byte size, section entry count
const header_size = 1 + 5 + 5;
try file.seekBy(header_size);
return (try file.getPos());
}
fn reserveCustomSectionHeader(file: fs.File) !u64 {
const header_size = 1 + 5;
try file.seekBy(header_size);
return (try file.getPos());
}
/// Emits the actual section header at the given `offset`.
/// Will write the section id, the section byte length, as well as the section entry count.
/// The amount of bytes is calculated using the current position, minus the offset (and reserved header bytes).
fn emitSectionHeader(file: fs.File, offset: u64, section_type: std.wasm.Section, entries: usize) !void {
// section id, section byte size, section entry count
var buf: [1 + 5 + 5]u8 = undefined;
buf[0] = @enumToInt(section_type);
const pos = try file.getPos();
const byte_size = pos + 5 - offset; // +5 due to 'entries' also being part of byte size
leb.writeUnsignedFixed(5, buf[1..6], @intCast(u32, byte_size));
leb.writeUnsignedFixed(5, buf[6..], @intCast(u32, entries));
try file.pwriteAll(&buf, offset - buf.len);
log.debug("Written section '{s}' offset=0x{x:0>8} size={d} count={d}", .{
@tagName(section_type),
offset - buf.len,
byte_size,
entries,
});
}
fn emitCustomHeader(file: fs.File, offset: u64) !void {
var buf: [1 + 5]u8 = undefined;
buf[0] = 0; // 0 = 'custom' section
const pos = try file.getPos();
const byte_size = pos - offset;
leb.writeUnsignedFixed(5, buf[1..6], @intCast(u32, byte_size));
try file.pwriteAll(&buf, offset - buf.len);
}
fn emitType(type_entry: std.wasm.Type, writer: anytype) !void {
log.debug("Writing type {}", .{type_entry});
try leb.writeULEB128(writer, @as(u8, 0x60)); //functype
try leb.writeULEB128(writer, @intCast(u32, type_entry.params.len));
for (type_entry.params) |para_ty| {
try leb.writeULEB128(writer, @enumToInt(para_ty));
}
try leb.writeULEB128(writer, @intCast(u32, type_entry.returns.len));
for (type_entry.returns) |ret_ty| {
try leb.writeULEB128(writer, @enumToInt(ret_ty));
}
}
fn emitImportSymbol(wasm: *const Wasm, sym_loc: Wasm.SymbolWithLoc, writer: anytype) !void {
const symbol = sym_loc.getSymbol(wasm).*;
var import: std.wasm.Import = .{
.module_name = undefined,
.name = symbol.name,
.kind = undefined,
};
switch (symbol.tag) {
.function => {
const value = wasm.imports.imported_functions.values()[symbol.index];
std.debug.assert(value.index == symbol.index);
import.kind = .{ .function = value.type };
import.module_name = wasm.imports.imported_functions.keys()[symbol.index].module_name;
},
.global => {
const value = wasm.imports.imported_globals.values()[symbol.index];
std.debug.assert(value.index == symbol.index);
import.kind = .{ .global = value.global };
import.module_name = wasm.imports.imported_globals.keys()[symbol.index].module_name;
},
.table => {
const value = wasm.imports.imported_tables.values()[symbol.index];
std.debug.assert(value.index == symbol.index);
import.kind = .{ .table = value.table };
import.module_name = wasm.imports.imported_tables.keys()[symbol.index].module_name;
},
else => unreachable,
}
try emitImport(import, writer);
}
fn emitImport(import_entry: std.wasm.Import, writer: anytype) !void {
try leb.writeULEB128(writer, @intCast(u32, import_entry.module_name.len));
try writer.writeAll(import_entry.module_name);
try leb.writeULEB128(writer, @intCast(u32, import_entry.name.len));
try writer.writeAll(import_entry.name);
try leb.writeULEB128(writer, @enumToInt(import_entry.kind));
switch (import_entry.kind) {
.function => |type_index| try leb.writeULEB128(writer, type_index),
.table => |table| try emitTable(table, writer),
.global => |global| {
try leb.writeULEB128(writer, @enumToInt(global.valtype));
try leb.writeULEB128(writer, @boolToInt(global.mutable));
},
.memory => |mem| try emitLimits(mem, writer),
}
}
fn emitFunction(func: std.wasm.Func, writer: anytype) !void {
try leb.writeULEB128(writer, func.type_index);
}
fn emitTable(table: std.wasm.Table, writer: anytype) !void {
try leb.writeULEB128(writer, @enumToInt(table.reftype));
try emitLimits(table.limits, writer);
}
fn emitLimits(limits: std.wasm.Limits, writer: anytype) !void {
try leb.writeULEB128(writer, @boolToInt(limits.max != null));
try leb.writeULEB128(writer, limits.min);
if (limits.max) |max| {
try leb.writeULEB128(writer, max);
}
}
fn emitMemory(mem: types.Memory, writer: anytype) !void {
try emitLimits(mem.limits, writer);
}
fn emitGlobal(global: std.wasm.Global, writer: anytype) !void {
try leb.writeULEB128(writer, @enumToInt(global.global_type.valtype));
try leb.writeULEB128(writer, @boolToInt(global.global_type.mutable));
try emitInitExpression(global.init, writer);
}
fn emitInitExpression(init: std.wasm.InitExpression, writer: anytype) !void {
switch (init) {
.i32_const => |val| {
try leb.writeULEB128(writer, std.wasm.opcode(.i32_const));
try leb.writeILEB128(writer, val);
},
.global_get => |index| {
try leb.writeULEB128(writer, std.wasm.opcode(.global_get));
try leb.writeULEB128(writer, index);
},
else => @panic("TODO: Other init expression emission"),
}
try leb.writeULEB128(writer, std.wasm.opcode(.end));
}
fn emitExport(exported: std.wasm.Export, writer: anytype) !void {
try leb.writeULEB128(writer, @intCast(u32, exported.name.len));
try writer.writeAll(exported.name);
try leb.writeULEB128(writer, @enumToInt(exported.kind));
try leb.writeULEB128(writer, exported.index);
}
fn emitElement(wasm: *const Wasm, writer: anytype) !void {
var flags: u32 = 0;
var index: ?u32 = if (wasm.global_symbols.get("__indirect_function_table")) |sym_loc| blk: {
flags |= 0x2;
break :blk sym_loc.getSymbol(wasm).index;
} else null;
try leb.writeULEB128(writer, flags);
if (index) |idx|
try leb.writeULEB128(writer, idx);
try emitInitExpression(.{ .i32_const = 1 }, writer);
if (flags & 0x3 != 0) {
try leb.writeULEB128(writer, @as(u8, 0));
}
try leb.writeULEB128(writer, wasm.elements.functionCount());
for (wasm.elements.indirect_functions.keys()) |sym_with_loc| {
const symbol = wasm.objects.items[sym_with_loc.file.?].symtable[sym_with_loc.sym_index];
try leb.writeULEB128(writer, symbol.index);
}
} | src/emit_wasm.zig |
const std = @import("std");
const crypto = std.crypto;
const debug = std.debug;
const fmt = std.fmt;
const mem = std.mem;
const Sha512 = std.crypto.hash.sha2.Sha512;
/// Ed25519 (EdDSA) signatures.
pub const Ed25519 = struct {
/// The underlying elliptic curve.
pub const Curve = @import("edwards25519.zig").Edwards25519;
/// Length (in bytes) of a seed required to create a key pair.
pub const seed_length = 32;
/// Length (in bytes) of a compressed secret key.
pub const secret_length = 64;
/// Length (in bytes) of a compressed public key.
pub const public_length = 32;
/// Length (in bytes) of a signature.
pub const signature_length = 64;
/// Length (in bytes) of optional random bytes, for non-deterministic signatures.
pub const noise_length = 32;
/// An Ed25519 key pair.
pub const KeyPair = struct {
/// Public part.
public_key: [public_length]u8,
/// Secret part. What we expose as a secret key is, under the hood, the concatenation of the seed and the public key.
secret_key: [secret_length]u8,
/// Derive a key pair from an optional secret seed.
///
/// As in RFC 8032, an Ed25519 public key is generated by hashing
/// the secret key using the SHA-512 function, and interpreting the
/// bit-swapped, clamped lower-half of the output as the secret scalar.
///
/// For this reason, an EdDSA secret key is commonly called a seed,
/// from which the actual secret is derived.
pub fn create(seed: ?[seed_length]u8) !KeyPair {
const ss = seed orelse ss: {
var random_seed: [seed_length]u8 = undefined;
try crypto.randomBytes(&random_seed);
break :ss random_seed;
};
var az: [Sha512.digest_length]u8 = undefined;
var h = Sha512.init(.{});
h.update(&ss);
h.final(&az);
const p = try Curve.basePoint.clampedMul(az[0..32].*);
var sk: [secret_length]u8 = undefined;
mem.copy(u8, &sk, &ss);
const pk = p.toBytes();
mem.copy(u8, sk[seed_length..], &pk);
return KeyPair{ .public_key = pk, .secret_key = sk };
}
/// Create a KeyPair from a secret key.
pub fn fromSecretKey(secret_key: [secret_length]u8) KeyPair {
return KeyPair{
.secret_key = secret_key,
.public_key = secret_key[seed_length..].*,
};
}
};
/// Sign a message using a key pair, and optional random noise.
/// Having noise creates non-standard, non-deterministic signatures,
/// but has been proven to increase resilience against fault attacks.
pub fn sign(msg: []const u8, key_pair: KeyPair, noise: ?[noise_length]u8) ![signature_length]u8 {
const seed = key_pair.secret_key[0..seed_length];
const public_key = key_pair.secret_key[seed_length..];
if (!mem.eql(u8, public_key, &key_pair.public_key)) {
return error.KeyMismatch;
}
var az: [Sha512.digest_length]u8 = undefined;
var h = Sha512.init(.{});
h.update(seed);
h.final(&az);
h = Sha512.init(.{});
if (noise) |*z| {
h.update(z);
}
h.update(az[32..]);
h.update(msg);
var nonce64: [64]u8 = undefined;
h.final(&nonce64);
const nonce = Curve.scalar.reduce64(nonce64);
const r = try Curve.basePoint.mul(nonce);
var sig: [signature_length]u8 = undefined;
mem.copy(u8, sig[0..32], &r.toBytes());
mem.copy(u8, sig[32..], public_key);
h = Sha512.init(.{});
h.update(&sig);
h.update(msg);
var hram64: [Sha512.digest_length]u8 = undefined;
h.final(&hram64);
const hram = Curve.scalar.reduce64(hram64);
var x = az[0..32];
Curve.scalar.clamp(x);
const s = Curve.scalar.mulAdd(hram, x.*, nonce);
mem.copy(u8, sig[32..], s[0..]);
return sig;
}
/// Verify an Ed25519 signature given a message and a public key.
/// Returns error.InvalidSignature is the signature verification failed.
pub fn verify(sig: [signature_length]u8, msg: []const u8, public_key: [public_length]u8) !void {
const r = sig[0..32];
const s = sig[32..64];
try Curve.scalar.rejectNonCanonical(s.*);
try Curve.rejectNonCanonical(public_key);
const a = try Curve.fromBytes(public_key);
try a.rejectIdentity();
try Curve.rejectNonCanonical(r.*);
const expected_r = try Curve.fromBytes(r.*);
var h = Sha512.init(.{});
h.update(r);
h.update(&public_key);
h.update(msg);
var hram64: [Sha512.digest_length]u8 = undefined;
h.final(&hram64);
const hram = Curve.scalar.reduce64(hram64);
const ah = try a.neg().mulPublic(hram);
const sb_ah = (try Curve.basePoint.mulPublic(s.*)).add(ah);
if (expected_r.sub(sb_ah).clearCofactor().rejectIdentity()) |_| {
return error.InvalidSignature;
} else |_| {}
}
/// A (signature, message, public_key) tuple for batch verification
pub const BatchElement = struct {
sig: [signature_length]u8,
msg: []const u8,
public_key: [public_length]u8,
};
/// Verify several signatures in a single operation, much faster than verifying signatures one-by-one
pub fn verifyBatch(comptime count: usize, signature_batch: [count]BatchElement) !void {
var r_batch: [count][32]u8 = undefined;
var s_batch: [count][32]u8 = undefined;
var a_batch: [count]Curve = undefined;
var expected_r_batch: [count]Curve = undefined;
for (signature_batch) |signature, i| {
const r = signature.sig[0..32];
const s = signature.sig[32..64];
try Curve.scalar.rejectNonCanonical(s.*);
try Curve.rejectNonCanonical(signature.public_key);
const a = try Curve.fromBytes(signature.public_key);
try a.rejectIdentity();
try Curve.rejectNonCanonical(r.*);
const expected_r = try Curve.fromBytes(r.*);
expected_r_batch[i] = expected_r;
r_batch[i] = r.*;
s_batch[i] = s.*;
a_batch[i] = a;
}
var hram_batch: [count]Curve.scalar.CompressedScalar = undefined;
for (signature_batch) |signature, i| {
var h = Sha512.init(.{});
h.update(&r_batch[i]);
h.update(&signature.public_key);
h.update(signature.msg);
var hram64: [Sha512.digest_length]u8 = undefined;
h.final(&hram64);
hram_batch[i] = Curve.scalar.reduce64(hram64);
}
var z_batch: [count]Curve.scalar.CompressedScalar = undefined;
for (z_batch) |*z| {
try std.crypto.randomBytes(z[0..16]);
mem.set(u8, z[16..], 0);
}
var zs_sum = Curve.scalar.zero;
for (z_batch) |z, i| {
const zs = Curve.scalar.mul(z, s_batch[i]);
zs_sum = Curve.scalar.add(zs_sum, zs);
}
zs_sum = Curve.scalar.mul8(zs_sum);
var zhs: [count]Curve.scalar.CompressedScalar = undefined;
for (z_batch) |z, i| {
zhs[i] = Curve.scalar.mul(z, hram_batch[i]);
}
const zr = (try Curve.mulMulti(count, expected_r_batch, z_batch)).clearCofactor();
const zah = (try Curve.mulMulti(count, a_batch, zhs)).clearCofactor();
const zsb = try Curve.basePoint.mulPublic(zs_sum);
if (zr.add(zah).sub(zsb).rejectIdentity()) |_| {
return error.InvalidSignature;
} else |_| {}
}
};
test "ed25519 key pair creation" {
var seed: [32]u8 = undefined;
try fmt.hexToBytes(seed[0..], "8052030376d47112be7f73ed7a019293dd12ad910b654455798b4667d73de166");
const key_pair = try Ed25519.KeyPair.create(seed);
var buf: [256]u8 = undefined;
std.testing.expectEqualStrings(try std.fmt.bufPrint(&buf, "{X}", .{key_pair.secret_key}), "8052030376D47112BE7F73ED7A019293DD12AD910B654455798B4667D73DE1662D6F7455D97B4A3A10D7293909D1A4F2058CB9A370E43FA8154BB280DB839083");
std.testing.expectEqualStrings(try std.fmt.bufPrint(&buf, "{X}", .{key_pair.public_key}), "<KEY>");
}
test "ed25519 signature" {
var seed: [32]u8 = undefined;
try fmt.hexToBytes(seed[0..], "8052030376d47112be7f73ed7a019293dd12ad910b654455798b4667d73de166");
const key_pair = try Ed25519.KeyPair.create(seed);
const sig = try Ed25519.sign("test", key_pair, null);
var buf: [128]u8 = undefined;
std.testing.expectEqualStrings(try std.fmt.bufPrint(&buf, "{X}", .{sig}), "10A442B4A80CC4225B154F43BEF28D2472CA80221951262EB8E0DF9091575E2687CC486E77263C3418C757522D54F84B0359236ABBBD4ACD20DC297FDCA66808");
try Ed25519.verify(sig, "test", key_pair.public_key);
std.testing.expectError(error.InvalidSignature, Ed25519.verify(sig, "TEST", key_pair.public_key));
}
test "ed25519 batch verification" {
var i: usize = 0;
while (i < 100) : (i += 1) {
const key_pair = try Ed25519.KeyPair.create(null);
var msg1: [32]u8 = undefined;
var msg2: [32]u8 = undefined;
try std.crypto.randomBytes(&msg1);
try std.crypto.randomBytes(&msg2);
const sig1 = try Ed25519.sign(&msg1, key_pair, null);
const sig2 = try Ed25519.sign(&msg2, key_pair, null);
var signature_batch = [_]Ed25519.BatchElement{
Ed25519.BatchElement{
.sig = sig1,
.msg = &msg1,
.public_key = key_pair.public_key,
},
Ed25519.BatchElement{
.sig = sig2,
.msg = &msg2,
.public_key = key_pair.public_key,
},
};
try Ed25519.verifyBatch(2, signature_batch);
signature_batch[1].sig = sig1;
std.testing.expectError(error.InvalidSignature, Ed25519.verifyBatch(signature_batch.len, signature_batch));
}
}
test "ed25519 test vectors" {
const Vec = struct {
msg_hex: *const [64:0]u8,
public_key_hex: *const [64:0]u8,
sig_hex: *const [128:0]u8,
expected: ?anyerror,
};
const entries = [_]Vec{
Vec{
.msg_hex = "8c93255d71dcab10e8f379c26200f3c7bd5f09d9bc3068d3ef4edeb4853022b6",
.public_key_hex = "c7176a703d4dd84fba3c0b760d10670f2a2053fa2c39ccc64ec7fd7792ac03fa",
.sig_hex = "c7176a703d4dd84fba3c0b760d10670f2a2053fa2c39ccc64ec7fd7792ac037a0000000000000000000000000000000000000000000000000000000000000000",
.expected = error.WeakPublicKey, // 0
},
Vec{
.msg_hex = "9bd9f44f4dcc75bd531b56b2cd280b0bb38fc1cd6d1230e14861d861de092e79",
.public_key_hex = "c7176a703d4dd84fba3c0b760d10670f2a2053fa2c39ccc64ec7fd7792ac03fa",
.sig_hex = "f7badec5b8abeaf699583992219b7b223f1df3fbbea919844e3f7c554a43dd43a5bb704786be79fc476f91d3f3f89b03984d8068dcf1bb7dfc6637b45450ac04",
.expected = error.WeakPublicKey, // 1
},
Vec{
.msg_hex = "<KEY>",
.public_key_hex = "f7badec5b8abeaf699583992219b7b223f1df3fbbea919844e3f7c554a43dd43",
.sig_hex = "c7176a703d4dd84fba3c0b760d10670f2a2053fa2c39ccc64ec7fd7792ac03fa8c4bd45aecaca5b24fb97bc10ac27ac8751a7dfe1baff8b953ec9f5833ca260e",
.expected = null, // 2 - small order R is acceptable
},
Vec{
.msg_hex = "9bd9f44f4dcc75bd531b56b2cd280b0bb38fc1cd6d1230e14861d861de092e79",
.public_key_hex = "<KEY>",
.sig_hex = "9046a64750444938de19f227bb80485e92b83fdb4b6506c160484c016cc1852f87909e14428a7a1d62e9f22f3d3ad7802db02eb2e688b6c52fcd6648a98bd009",
.expected = null, // 3 - mixed orders
},
Vec{
.msg_hex = "e47d62c63f830dc7a6851a0b1f33ae4bb2f507fb6cffec4011eaccd55b53f56c",
.public_key_hex = "<KEY>",
.sig_hex = "160a1cb0dc9c0258cd0a7d23e94d8fa878bcb1925f2c64246b2dee1796bed5125ec6bc982a269b723e0668e540911a9a6a58921d6925e434ab10aa7940551a09",
.expected = null, // 4 - cofactored verification
},
Vec{
.msg_hex = "e47d62c63f830dc7a6851a0b1f33ae4bb2f507fb6cffec4011eaccd55b53f56c",
.public_key_hex = "<KEY>",
.sig_hex = "21122a84e0b5fca4052f5b1235c80a537878b38f3142356b2c2384ebad4668b7e40bc836dac0f71076f9abe3a53f9c03c1ceeeddb658d0030494ace586687405",
.expected = null, // 5 - cofactored verification
},
Vec{
.msg_hex = "85e241a07d148b41e47d62c63f830dc7a6851a0b1f33ae4bb2f507fb6cffec40",
.public_key_hex = "442aad9f089ad9e14647b1ef9099a1ff4798d78589e66f28eca69c11f582a623",
.sig_hex = "e96f66be976d82e60150baecff9906684aebb1ef181f67a7189ac78ea23b6c0e547f7690a0e2ddcd04d87dbc3490dc19b3b3052f7ff0538cb68afb369ba3a514",
.expected = error.NonCanonical, // 6 - S > L
},
Vec{
.msg_hex = "85e241a07d148b41e47d62c63f830dc7a6851a0b1f33ae4bb2f507fb6cffec40",
.public_key_hex = "442aad9f089ad9e14647b1ef9099a1ff4798d78589e66f28eca69c11f582a623",
.sig_hex = "8ce5b96c8f26d0ab6c47958c9e68b937104cd36e13c33566acd2fe8d38aa19427e71f98a4734e74f2f13f06f97c20d58cc3f54b8bd0d272f42b695dd7e89a8c2",
.expected = error.NonCanonical, // 7 - S >> L
},
Vec{
.msg_hex = "9bedc267423725d473888631ebf45988bad3db83851ee85c85e241a07d148b41",
.public_key_hex = "f7badec5b8abeaf699583992219b7b223f1df3fbbea919844e3f7c554a43dd43",
.sig_hex = "ecffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff03be9678ac102edcd92b0210bb34d7428d12ffc5df5f37e359941266a4e35f0f",
.expected = error.InvalidSignature, // 8 - non-canonical R
},
Vec{
.msg_hex = "9bedc267423725d473888631ebf45988bad3db83851ee85c85e241a07d148b41",
.public_key_hex = "f7badec5b8abeaf699583992219b7b223f1df3fbbea919844e3f7c554a43dd43",
.sig_hex = "ecffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffca8c5b64cd208982aa38d4936621a4775aa233aa0505711d8fdcfdaa943d4908",
.expected = null, // 9 - non-canonical R
},
Vec{
.msg_hex = "<KEY>",
.public_key_hex = "ecffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff",
.sig_hex = "a9d55260f765261eb9b84e106f665e00b867287a761990d7135963ee0a7d59dca5bb704786be79fc476f91d3f3f89b03984d8068dcf1bb7dfc6637b45450ac04",
.expected = error.IdentityElement, // 10 - small-order A
},
Vec{
.msg_hex = "39a591f5321bbe07fd5a23dc2f39d025d74526615746727ceefd6e82ae65c06f",
.public_key_hex = "ecffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff",
.sig_hex = "a9d55260f765261eb9b84e106f665e00b867287a761990d7135963ee0a7d59dca5bb704786be79fc476f91d3f3f89b03984d8068dcf1bb7dfc6637b45450ac04",
.expected = error.IdentityElement, // 11 - small-order A
},
};
for (entries) |entry, i| {
var msg: [entry.msg_hex.len / 2]u8 = undefined;
try fmt.hexToBytes(&msg, entry.msg_hex);
var public_key: [32]u8 = undefined;
try fmt.hexToBytes(&public_key, entry.public_key_hex);
var sig: [64]u8 = undefined;
try fmt.hexToBytes(&sig, entry.sig_hex);
if (entry.expected) |error_type| {
std.testing.expectError(error_type, Ed25519.verify(sig, &msg, public_key));
} else {
try Ed25519.verify(sig, &msg, public_key);
}
}
} | lib/std/crypto/25519/ed25519.zig |
const std = @import("../std.zig");
const math = std.math;
const expect = std.testing.expect;
/// Returns whether x is neither zero, subnormal, infinity, or NaN.
pub fn isNormal(x: anytype) bool {
const T = @TypeOf(x);
const TBits = std.meta.Int(.unsigned, @bitSizeOf(T));
if (@typeInfo(T) != .Float) {
@compileError("isNormal not implemented for " ++ @typeName(T));
}
const increment_exp = 1 << math.floatMantissaBits(T);
const remove_sign = ~@as(TBits, 0) >> 1;
// We add 1 to the exponent, and if it overflows to 0 or becomes 1,
// then it was all zeroes (subnormal) or all ones (special, inf/nan).
// The sign bit is removed because all ones would overflow into it.
// For f80, even though it has an explicit integer part stored,
// the exponent effectively takes priority if mismatching.
const value = @bitCast(TBits, x) +% increment_exp;
return value & remove_sign >= (increment_exp << 1);
}
test "math.isNormal" {
// TODO remove when #11391 is resolved
if (@import("builtin").os.tag == .freebsd) return error.SkipZigTest;
// TODO add `c_longdouble' when math.inf(T) supports it
inline for ([_]type{ f16, f32, f64, f80, f128 }) |T| {
const TBits = std.meta.Int(.unsigned, @bitSizeOf(T));
// normals
try expect(isNormal(@as(T, 1.0)));
try expect(isNormal(math.floatMin(T)));
try expect(isNormal(math.floatMax(T)));
// subnormals
try expect(!isNormal(@as(T, -0.0)));
try expect(!isNormal(@as(T, 0.0)));
try expect(!isNormal(@as(T, math.floatTrueMin(T))));
// largest subnormal
try expect(!isNormal(@bitCast(T, ~(~@as(TBits, 0) << math.floatMantissaDigits(T) - 1))));
// non-finite numbers
try expect(!isNormal(-math.inf(T)));
try expect(!isNormal(math.inf(T)));
try expect(!isNormal(math.nan(T)));
// overflow edge-case (described in implementation, also see #10133)
try expect(!isNormal(@bitCast(T, ~@as(TBits, 0))));
}
} | lib/std/math/isnormal.zig |
const std = @import("../index.zig");
const debug = std.debug;
pub const Adler32 = struct.{
const base = 65521;
const nmax = 5552;
adler: u32,
pub fn init() Adler32 {
return Adler32.{ .adler = 1 };
}
// This fast variant is taken from zlib. It reduces the required modulos and unrolls longer
// buffer inputs and should be much quicker.
pub fn update(self: *Adler32, input: []const u8) void {
var s1 = self.adler & 0xffff;
var s2 = (self.adler >> 16) & 0xffff;
if (input.len == 1) {
s1 +%= input[0];
if (s1 >= base) {
s1 -= base;
}
s2 +%= s1;
if (s2 >= base) {
s2 -= base;
}
} else if (input.len < 16) {
for (input) |b| {
s1 +%= b;
s2 +%= s1;
}
if (s1 >= base) {
s1 -= base;
}
s2 %= base;
} else {
var i: usize = 0;
while (i + nmax <= input.len) : (i += nmax) {
const n = nmax / 16; // note: 16 | nmax
var rounds: usize = 0;
while (rounds < n) : (rounds += 1) {
comptime var j: usize = 0;
inline while (j < 16) : (j += 1) {
s1 +%= input[i + n * j];
s2 +%= s1;
}
}
}
if (i < input.len) {
while (i + 16 <= input.len) : (i += 16) {
comptime var j: usize = 0;
inline while (j < 16) : (j += 1) {
s1 +%= input[i + j];
s2 +%= s1;
}
}
while (i < input.len) : (i += 1) {
s1 +%= input[i];
s2 +%= s1;
}
s1 %= base;
s2 %= base;
}
}
self.adler = s1 | (s2 << 16);
}
pub fn final(self: *Adler32) u32 {
return self.adler;
}
pub fn hash(input: []const u8) u32 {
var c = Adler32.init();
c.update(input);
return c.final();
}
};
test "adler32 sanity" {
debug.assert(Adler32.hash("a") == 0x620062);
debug.assert(Adler32.hash("example") == 0xbc002ed);
}
test "adler32 long" {
const long1 = []u8.{1} ** 1024;
debug.assert(Adler32.hash(long1[0..]) == 0x06780401);
const long2 = []u8.{1} ** 1025;
debug.assert(Adler32.hash(long2[0..]) == 0x0a7a0402);
}
test "adler32 very long" {
const long = []u8.{1} ** 5553;
debug.assert(Adler32.hash(long[0..]) == 0x707f15b2);
} | std/hash/adler.zig |
const std = @import("std");
const crypto = std.crypto;
const debug = std.debug;
const mem = std.mem;
const meta = std.meta;
const NonCanonicalError = crypto.errors.NonCanonicalError;
const NotSquareError = crypto.errors.NotSquareError;
/// Parameters to create a finite field type.
pub const FieldParams = struct {
fiat: type,
field_order: comptime_int,
field_bits: comptime_int,
saturated_bits: comptime_int,
encoded_length: comptime_int,
};
/// A field element, internally stored in Montgomery domain.
pub fn Field(comptime params: FieldParams) type {
const fiat = params.fiat;
const MontgomeryDomainFieldElement = fiat.MontgomeryDomainFieldElement;
const NonMontgomeryDomainFieldElement = fiat.NonMontgomeryDomainFieldElement;
return struct {
const Fe = @This();
limbs: MontgomeryDomainFieldElement,
/// Field size.
pub const field_order = params.field_order;
/// Number of bits to represent the set of all elements.
pub const field_bits = params.field_bits;
/// Number of bits that can be saturated without overflowing.
pub const saturated_bits = params.saturated_bits;
/// Number of bytes required to encode an element.
pub const encoded_length = params.encoded_length;
/// Zero.
pub const zero: Fe = Fe{ .limbs = mem.zeroes(MontgomeryDomainFieldElement) };
/// One.
pub const one = one: {
var fe: Fe = undefined;
fiat.setOne(&fe.limbs);
break :one fe;
};
/// Reject non-canonical encodings of an element.
pub fn rejectNonCanonical(s_: [encoded_length]u8, endian: std.builtin.Endian) NonCanonicalError!void {
var s = if (endian == .Little) s_ else orderSwap(s_);
const field_order_s = comptime fos: {
var fos: [encoded_length]u8 = undefined;
mem.writeIntLittle(std.meta.Int(.unsigned, encoded_length * 8), &fos, field_order);
break :fos fos;
};
if (crypto.utils.timingSafeCompare(u8, &s, &field_order_s, .Little) != .lt) {
return error.NonCanonical;
}
}
/// Swap the endianness of an encoded element.
pub fn orderSwap(s: [encoded_length]u8) [encoded_length]u8 {
var t = s;
for (s) |x, i| t[t.len - 1 - i] = x;
return t;
}
/// Unpack a field element.
pub fn fromBytes(s_: [encoded_length]u8, endian: std.builtin.Endian) NonCanonicalError!Fe {
var s = if (endian == .Little) s_ else orderSwap(s_);
try rejectNonCanonical(s, .Little);
var limbs_z: NonMontgomeryDomainFieldElement = undefined;
fiat.fromBytes(&limbs_z, s);
var limbs: MontgomeryDomainFieldElement = undefined;
fiat.toMontgomery(&limbs, limbs_z);
return Fe{ .limbs = limbs };
}
/// Pack a field element.
pub fn toBytes(fe: Fe, endian: std.builtin.Endian) [encoded_length]u8 {
var limbs_z: NonMontgomeryDomainFieldElement = undefined;
fiat.fromMontgomery(&limbs_z, fe.limbs);
var s: [encoded_length]u8 = undefined;
fiat.toBytes(&s, limbs_z);
return if (endian == .Little) s else orderSwap(s);
}
/// Element as an integer.
pub const IntRepr = meta.Int(.unsigned, params.field_bits);
/// Create a field element from an integer.
pub fn fromInt(comptime x: IntRepr) NonCanonicalError!Fe {
var s: [encoded_length]u8 = undefined;
mem.writeIntLittle(IntRepr, &s, x);
return fromBytes(s, .Little);
}
/// Return the field element as an integer.
pub fn toInt(fe: Fe) IntRepr {
const s = fe.toBytes(.Little);
return mem.readIntLittle(IntRepr, &s);
}
/// Return true if the field element is zero.
pub fn isZero(fe: Fe) bool {
var z: @TypeOf(fe.limbs[0]) = undefined;
fiat.nonzero(&z, fe.limbs);
return z == 0;
}
/// Return true if both field elements are equivalent.
pub fn equivalent(a: Fe, b: Fe) bool {
return a.sub(b).isZero();
}
/// Return true if the element is odd.
pub fn isOdd(fe: Fe) bool {
const s = fe.toBytes(.Little);
return @truncate(u1, s[0]) != 0;
}
/// Conditonally replace a field element with `a` if `c` is positive.
pub fn cMov(fe: *Fe, a: Fe, c: u1) void {
fiat.selectznz(&fe.limbs, c, fe.limbs, a.limbs);
}
/// Add field elements.
pub fn add(a: Fe, b: Fe) Fe {
var fe: Fe = undefined;
fiat.add(&fe.limbs, a.limbs, b.limbs);
return fe;
}
/// Subtract field elements.
pub fn sub(a: Fe, b: Fe) Fe {
var fe: Fe = undefined;
fiat.sub(&fe.limbs, a.limbs, b.limbs);
return fe;
}
/// Double a field element.
pub fn dbl(a: Fe) Fe {
var fe: Fe = undefined;
fiat.add(&fe.limbs, a.limbs, a.limbs);
return fe;
}
/// Multiply field elements.
pub fn mul(a: Fe, b: Fe) Fe {
var fe: Fe = undefined;
fiat.mul(&fe.limbs, a.limbs, b.limbs);
return fe;
}
/// Square a field element.
pub fn sq(a: Fe) Fe {
var fe: Fe = undefined;
fiat.square(&fe.limbs, a.limbs);
return fe;
}
/// Square a field element n times.
fn sqn(a: Fe, comptime n: comptime_int) Fe {
var i: usize = 0;
var fe = a;
while (i < n) : (i += 1) {
fe = fe.sq();
}
return fe;
}
/// Compute a^n.
pub fn pow(a: Fe, comptime T: type, comptime n: T) Fe {
var fe = one;
var x: T = n;
var t = a;
while (true) {
if (@truncate(u1, x) != 0) fe = fe.mul(t);
x >>= 1;
if (x == 0) break;
t = t.sq();
}
return fe;
}
/// Negate a field element.
pub fn neg(a: Fe) Fe {
var fe: Fe = undefined;
fiat.opp(&fe.limbs, a.limbs);
return fe;
}
/// Return the inverse of a field element, or 0 if a=0.
// Field inversion from https://eprint.iacr.org/2021/549.pdf
pub fn invert(a: Fe) Fe {
const iterations = (49 * field_bits + 57) / 17;
const Limbs = @TypeOf(a.limbs);
const Word = @TypeOf(a.limbs[0]);
const XLimbs = [a.limbs.len + 1]Word;
var d: Word = 1;
var f = comptime blk: {
var f: XLimbs = undefined;
fiat.msat(&f);
break :blk f;
};
var g: XLimbs = undefined;
fiat.fromMontgomery(g[0..a.limbs.len], a.limbs);
g[g.len - 1] = 0;
var r = Fe.one.limbs;
var v = Fe.zero.limbs;
var out1: Word = undefined;
var out2: XLimbs = undefined;
var out3: XLimbs = undefined;
var out4: Limbs = undefined;
var out5: Limbs = undefined;
var i: usize = 0;
while (i < iterations - iterations % 2) : (i += 2) {
fiat.divstep(&out1, &out2, &out3, &out4, &out5, d, f, g, v, r);
fiat.divstep(&d, &f, &g, &v, &r, out1, out2, out3, out4, out5);
}
if (iterations % 2 != 0) {
fiat.divstep(&out1, &out2, &out3, &out4, &out5, d, f, g, v, r);
mem.copy(Word, &v, &out4);
mem.copy(Word, &f, &out2);
}
var v_opp: Limbs = undefined;
fiat.opp(&v_opp, v);
fiat.selectznz(&v, @truncate(u1, f[f.len - 1] >> (@bitSizeOf(Word) - 1)), v, v_opp);
const precomp = blk: {
var precomp: Limbs = undefined;
fiat.divstepPrecomp(&precomp);
break :blk precomp;
};
var fe: Fe = undefined;
fiat.mul(&fe.limbs, v, precomp);
return fe;
}
/// Return true if the field element is a square.
pub fn isSquare(x2: Fe) bool {
if (field_order == 115792089210356248762697446949407573530086143415290314195533631308867097853951) {
const t110 = x2.mul(x2.sq()).sq();
const t111 = x2.mul(t110);
const t111111 = t111.mul(x2.mul(t110).sqn(3));
const x15 = t111111.sqn(6).mul(t111111).sqn(3).mul(t111);
const x16 = x15.sq().mul(x2);
const x53 = x16.sqn(16).mul(x16).sqn(15);
const x47 = x15.mul(x53);
const ls = x47.mul(((x53.sqn(17).mul(x2)).sqn(143).mul(x47)).sqn(47)).sq().mul(x2);
return ls.equivalent(Fe.one);
} else if (field_order == 39402006196394479212279040100143613805079739270465446667948293404245721771496870329047266088258938001861606973112319) {
const t111 = x2.mul(x2.mul(x2.sq()).sq());
const t111111 = t111.mul(t111.sqn(3));
const t1111110 = t111111.sq();
const t1111111 = x2.mul(t1111110);
const x12 = t1111110.sqn(5).mul(t111111);
const x31 = x12.sqn(12).mul(x12).sqn(7).mul(t1111111);
const x32 = x31.sq().mul(x2);
const x63 = x32.sqn(31).mul(x31);
const x126 = x63.sqn(63).mul(x63);
const ls = x126.sqn(126).mul(x126).sqn(3).mul(t111).sqn(33).mul(x32).sqn(95).mul(x31);
return ls.equivalent(Fe.one);
} else {
const ls = x2.pow(std.meta.Int(.unsigned, field_bits), (field_order - 1) / 2); // Legendre symbol
return ls.equivalent(Fe.one);
}
}
// x=x2^((field_order+1)/4) w/ field order=3 (mod 4).
fn uncheckedSqrt(x2: Fe) Fe {
comptime debug.assert(field_order % 4 == 3);
if (field_order == 115792089210356248762697446949407573530086143415290314195533631308867097853951) {
const t11 = x2.mul(x2.sq());
const t1111 = t11.mul(t11.sqn(2));
const t11111111 = t1111.mul(t1111.sqn(4));
const x16 = t11111111.sqn(8).mul(t11111111);
return x16.sqn(16).mul(x16).sqn(32).mul(x2).sqn(96).mul(x2).sqn(94);
} else if (field_order == 39402006196394479212279040100143613805079739270465446667948293404245721771496870329047266088258938001861606973112319) {
const t111 = x2.mul(x2.mul(x2.sq()).sq());
const t111111 = t111.mul(t111.sqn(3));
const t1111110 = t111111.sq();
const t1111111 = x2.mul(t1111110);
const x12 = t1111110.sqn(5).mul(t111111);
const x31 = x12.sqn(12).mul(x12).sqn(7).mul(t1111111);
const x32 = x31.sq().mul(x2);
const x63 = x32.sqn(31).mul(x31);
const x126 = x63.sqn(63).mul(x63);
return x126.sqn(126).mul(x126).sqn(3).mul(t111).sqn(33).mul(x32).sqn(64).mul(x2).sqn(30);
} else {
return x2.pow(std.meta.Int(.unsigned, field_bits), (field_order + 1) / 4);
}
}
/// Compute the square root of `x2`, returning `error.NotSquare` if `x2` was not a square.
pub fn sqrt(x2: Fe) NotSquareError!Fe {
const x = x2.uncheckedSqrt();
if (x.sq().equivalent(x2)) {
return x;
}
return error.NotSquare;
}
};
} | lib/std/crypto/pcurves/common.zig |
const std = @import("std");
const ascii = std.ascii;
const mem = std.mem;
const Allocator = mem.Allocator;
const ArrayList = std.ArrayList;
const Context = @import("../server.zig").Server.Context;
// TODO use std.http.Headers
pub const Headers = struct {
list: HeaderList,
pub const Error = error{
InvalidChar,
OutOfMemory,
};
const HeaderList = ArrayList(Header);
const Header = struct {
name: []const u8,
value: []const u8,
fn from(allocator: Allocator, name: []const u8, value: []const u8) Error!Header {
var copy_name = try allocator.alloc(u8, name.len);
var copy_value = try allocator.alloc(u8, value.len);
errdefer allocator.free(copy_name);
errdefer allocator.free(copy_value);
for (name) |c, i| {
copy_name[i] = switch (c) {
'a'...'z', '0'...'9', '!', '#', '$', '%', '&', '\'', '*', '+', '-', '.', '/', '^', '_', '`', '|', '~' => c,
'A'...'Z' => c | 0x20,
else => return Error.InvalidChar,
};
}
var i: usize = 0;
for (mem.trim(u8, value, " \t")) |c| {
if (c == '\r' or c == '\n') {
// obs-fold
} else if (c < ' ' or c > '~') {
return Error.InvalidChar;
} else {
copy_value[i] = c;
i += 1;
}
}
copy_value = allocator.shrink(copy_value, i);
return Header{
.name = copy_name,
.value = copy_value,
};
}
};
pub fn init(allocator: Allocator) Headers {
return Headers{
.list = HeaderList.init(allocator),
};
}
pub fn deinit(headers: Headers) void {
const a = headers.list.allocator;
for (headers.list.items) |h| {
a.free(h.name);
a.free(h.value);
}
headers.list.deinit();
}
pub fn get(headers: *const Headers, allocator: Allocator, name: []const u8) Error!?[]const *Header {
var list = ArrayList(*Header).init(allocator);
errdefer list.deinit();
for (headers.list.items) |*h| {
if (mem.eql(u8, h.name, name)) {
const new = try list.addOne();
new.* = h;
}
}
if (list.items.len == 0) {
return null;
} else {
return list.toOwnedSlice();
}
}
// pub fn set(h: *Headers, name: []const u8, value: []const u8) Error!?[]const u8 {
// // var old = get()
// }
pub fn has(headers: *Headers, name: []const u8) bool {
for (headers.list.items) |*h| {
if (mem.eql(u8, h.name, name)) {
return true;
}
}
return false;
}
pub fn hasTokenIgnoreCase(headers: *const Headers, name: []const u8, token: []const u8) bool {
for (headers.list.items) |*h| {
if (ascii.eqlIgnoreCase(h.name, name) and ascii.eqlIgnoreCase(h.value, token)) {
return true;
}
}
return false;
}
pub fn put(h: *Headers, name: []const u8, value: []const u8) Error!void {
try h.list.append(try Header.from(h.list.allocator, name, value));
}
}; | src/routez/http/headers.zig |
const zmath = @import("zmath");
const color = @import("../color.zig");
const std = @import("std");
const xyY = color.xyY;
const Mat = zmath.Mat;
/// Parameters that define an RGB color space.
pub const RGBColorSpace = struct {
/// Color space identifier.
id: []const u8,
toGamma: fn (f32) f32,
toLinear: fn (f32) f32,
/// White point.
white: xyY,
/// Red point.
red: xyY,
/// Green point.
green: xyY,
/// Blue point.
blue: xyY,
/// RGB to XYZ conversion matrix.
rgb_to_xyz: Mat,
/// XYZ to RGB conversion matrix.
xyz_to_rgb: Mat,
const Self = @This();
/// Construct an RGB color space from primaries and whitepoint.
pub fn init(comptime id: []const u8, comptime gamma: anytype, white: xyY, red: xyY, green: xyY, blue: xyY) Self {
var toGamma: fn (f32) f32 = undefined;
var toLinear: fn (f32) f32 = undefined;
if (@TypeOf(gamma) == comptime_float) {
toGamma = linearToGamma(gamma);
toLinear = gammaToLinear(gamma);
} else if (std.mem.eql(u8, gamma, "sRGB")) {
toGamma = linearToHybridGamma(0.0031308, 12.92, 1.055, 1 / 2.4);
toLinear = hybridGammaToLinear(0.0031308, 12.92, 1.055, 2.4);
} else if (std.mem.eql(u8, gamma, "Rec.601")) {
toGamma = linearToHybridGamma(0.018, 4.5, 1.099, 0.45);
toLinear = hybridGammaToLinear(0.018, 4.5, 1.099, 1 / 0.45);
} else if (std.mem.eql(u8, gamma, "Rec.2020")) {
toGamma = linearToHybridGamma(0.018053968510807, 4.5, 1.09929682680944, 0.45);
toLinear = hybridGammaToLinear(0.018053968510807, 4.5, 1.09929682680944, 1 / 0.45);
} else {
@compileError("Got unsupported value for gamma parameter");
}
var rgb_to_xyz = rgbToXyzMatrix(red, green, blue, white);
// TODO: Uncomment when it no longer crashes the compiler
//var xyz_to_rgb = zmath.inverse(rgb_to_xyz);
var xyz_to_rgb = rgb_to_xyz;
var self = Self{
.id = id,
.toGamma = toGamma,
.toLinear = toLinear,
.white = white,
.red = red,
.green = green,
.blue = blue,
.rgb_to_xyz = rgb_to_xyz,
.xyz_to_rgb = xyz_to_rgb,
};
return self;
}
};
fn linearToGamma(comptime gamma: comptime_float) fn (f32) f32 {
return struct {
fn impl(v: f32) f32 {
return std.math.pow(f32, v, 1 / gamma);
}
}.impl;
}
fn linearToHybridGamma(
comptime breakpoint: comptime_float,
comptime linear_factor: comptime_float,
comptime fac: comptime_float,
comptime exp: comptime_float,
) fn (f32) f32 {
return struct {
fn impl(v: f32) f32 {
if (v <= breakpoint) return v * linear_factor;
return fac * std.math.pow(f32, v, exp) - fac + 1;
}
}.impl;
}
fn gammaToLinear(comptime gamma: comptime_float) fn (f32) f32 {
return struct {
fn impl(v: f32) f32 {
return std.math.pow(f32, v, gamma);
}
}.impl;
}
fn hybridGammaToLinear(
comptime breakpoint: comptime_float,
comptime linear_factor: comptime_float,
comptime fac: comptime_float,
comptime exp: comptime_float,
) fn (f32) f32 {
return struct {
fn impl(v: f32) f32 {
if (v <= breakpoint * linear_factor) return v / linear_factor;
return std.math.pow(f32, (v + fac - 1) / fac, exp);
}
}.impl;
}
/// RGB to XYZ color space transformation matrix.
fn rgbToXyzMatrix(red: xyY, green: xyY, blue: xyY, white: xyY) Mat {
const r = red.toXYZ();
const g = green.toXYZ();
const b = blue.toXYZ();
// build a matrix from the 3 color vectors
var m = Mat{
zmath.f32x4(r.X, g.X, b.X, 0),
zmath.f32x4(r.Y, g.Y, b.Y, 0),
zmath.f32x4(r.Z, g.Z, b.Z, 0),
zmath.f32x4(0, 0, 0, 1),
};
// multiply by the whitepoint
const wXYZ = white.toXYZ();
var w = zmath.f32x4(wXYZ.X, wXYZ.Y, wXYZ.Z, 1);
// TODO: Uncomment when it no longer crashes the compiler
//var s = zmath.mul(zmath.inverse(m), w);
var s = zmath.mul(m, w);
// return colorspace matrix (RGB -> XYZ)
return .{
m[0] * s,
m[1] * s,
m[2] * s,
m[3] * s,
};
}
const si = color.std_illuminant;
// zig fmt: off
pub const sRGB = RGBColorSpace.init("sRGB", "sRGB", si.D65, xyY.init(0.6400, 0.3300, 0.212656), xyY.init(0.3000, 0.6000, 0.715158), xyY.init(0.1500, 0.0600, 0.072186));
pub const ntsc1953 = RGBColorSpace.init("NTSC1953", "Rec.601", si.C, xyY.init(0.6700, 0.3300, 0.299000), xyY.init(0.2100, 0.7100, 0.587000), xyY.init(0.1400, 0.0800, 0.114000));
pub const ntsc = RGBColorSpace.init("NTSC", "Rec.601", si.D65, xyY.init(0.6300, 0.3400, 0.299000), xyY.init(0.3100, 0.5950, 0.587000), xyY.init(0.1550, 0.0700, 0.114000));
pub const ntsc_j = RGBColorSpace.init("NTSC-J", "Rec.601", si.D93, xyY.init(0.6300, 0.3400, 0.299000), xyY.init(0.3100, 0.5950, 0.587000), xyY.init(0.1550, 0.0700, 0.114000));
pub const pal_secam = RGBColorSpace.init("PAL/SECAM", "Rec.601", si.D65, xyY.init(0.6400, 0.3300, 0.299000), xyY.init(0.2900, 0.6000, 0.587000), xyY.init(0.1500, 0.0600, 0.114000));
pub const rec709 = RGBColorSpace.init("Rec.709", "Rec.601", si.D65, xyY.init(0.6400, 0.3300, 0.212600), xyY.init(0.3000, 0.6000, 0.715200), xyY.init(0.1500, 0.0600, 0.072200));
pub const rec2020 = RGBColorSpace.init("Rec.2020", "Rec.2020", si.D65, xyY.init(0.7080, 0.2920, 0.262700), xyY.init(0.1700, 0.7970, 0.678000), xyY.init(0.1310, 0.0460, 0.059300));
pub const adobeRGB = RGBColorSpace.init("AdobeRGB", 2.2, si.D65, xyY.init(0.6400, 0.3300, 0.297361), xyY.init(0.2100, 0.7100, 0.627355), xyY.init(0.1500, 0.0600, 0.075285));
pub const wideGamutRGB = RGBColorSpace.init("WideGamutRGB", 2.2, si.D50, xyY.init(0.7350, 0.2650, 0.258187), xyY.init(0.1150, 0.8260, 0.724938), xyY.init(0.1570, 0.0180, 0.016875));
pub const appleRGB = RGBColorSpace.init("AppleRGB", 1.8, si.D65, xyY.init(0.6250, 0.3400, 0.244634), xyY.init(0.2800, 0.5950, 0.672034), xyY.init(0.1550, 0.0700, 0.083332));
pub const proPhoto = RGBColorSpace.init("ProPhoto", 1.8, si.D50, xyY.init(0.7347, 0.2653, 0.288040), xyY.init(0.1596, 0.8404, 0.711874), xyY.init(0.0366, 0.0001, 0.000086));
pub const cieRGB = RGBColorSpace.init("CIERGB", 2.2, si.E, xyY.init(0.7350, 0.2650, 0.176204), xyY.init(0.2740, 0.7170, 0.812985), xyY.init(0.1670, 0.0090, 0.010811));
pub const p3dci = RGBColorSpace.init("P3DCI", 2.6, si.DCI, xyY.init(0.6800, 0.3200, 0.228975), xyY.init(0.2650, 0.6900, 0.691739), xyY.init(0.1500, 0.0600, 0.079287));
pub const p3d65 = RGBColorSpace.init("P3D65", 2.6, si.D65, xyY.init(0.6800, 0.3200, 0.228973), xyY.init(0.2650, 0.6900, 0.691752), xyY.init(0.1500, 0.0600, 0.079275));
pub const p3d60 = RGBColorSpace.init("P3D60", 2.6, si.D60, xyY.init(0.6800, 0.3200, 0.228973), xyY.init(0.2650, 0.6900, 0.691752), xyY.init(0.1500, 0.0600, 0.079275));
pub const displayP3 = RGBColorSpace.init("DisplayP3", "sRGB", si.D65, xyY.init(0.6800, 0.3200, 0.228973), xyY.init(0.2650, 0.6900, 0.691752), xyY.init(0.1500, 0.0600, 0.079275));
// zig fmt: on
pub const rgbColorSpaces = [_]*const RGBColorSpace{
&sRGB,
&ntsc1953,
&ntsc,
&ntsc_j,
&pal_secam,
&rec709,
&rec2020,
&adobeRGB,
&wideGamutRGB,
&appleRGB,
&proPhoto,
&cieRGB,
&p3dci,
&p3d65,
&p3d60,
&displayP3,
};
pub fn getRGBColorSpaceByName(name: []const u8) ?*const RGBColorSpace {
// Handle aliases first
if (std.mem.eql(u8, name, "BT.709") or std.mem.eql(u8, name, "HDTV")) return &rec709;
if (std.mem.eql(u8, name, "BT.2020") or std.mem.eql(u8, name, "UHDTV")) return &rec2020;
for (rgbColorSpaces) |space| {
if (std.mem.eql(u8, name, space.id)) return space;
}
return null;
}
pub fn getRGBColorSpaceByPoints(white: xyY, rx: f32, ry: f32, gx: f32, gy: f32, bx: f32, by: f32) ?*const RGBColorSpace {
const math = std.math;
const epsilon = 0.00001;
for (rgbColorSpaces) |space| {
if (white.approxEqual(space.white, epsilon) and
math.approxEqAbs(f32, rx, space.red.x, epsilon) and
math.approxEqAbs(f32, ry, space.red.y, epsilon) and
math.approxEqAbs(f32, gx, space.green.x, epsilon) and
math.approxEqAbs(f32, gy, space.green.y, epsilon) and
math.approxEqAbs(f32, bx, space.blue.x, epsilon) and
math.approxEqAbs(f32, by, space.blue.y, epsilon))
{
return space;
}
}
return null;
}
// ********************* TESTS *********************
test "sRGBToLinear" {
const epsilon = 0.000001;
try std.testing.expectEqual(@as(f32, 0), sRGB.toLinear(0));
try std.testing.expectApproxEqAbs(@as(f32, 0.000303526983548838), sRGB.toLinear(1 / 255.0), epsilon);
try std.testing.expectApproxEqAbs(@as(f32, 0.00151763491774419), sRGB.toLinear(5 / 255.0), epsilon);
try std.testing.expectApproxEqAbs(@as(f32, 0.00699541018726539), sRGB.toLinear(20 / 255.0), epsilon);
try std.testing.expectApproxEqAbs(@as(f32, 0.0318960330730115), sRGB.toLinear(50 / 255.0), epsilon);
try std.testing.expectApproxEqAbs(@as(f32, 0.0843762115441488), sRGB.toLinear(82 / 255.0), epsilon);
try std.testing.expectApproxEqAbs(@as(f32, 0.109461702), sRGB.toLinear(93 / 255.0), epsilon);
try std.testing.expectApproxEqAbs(@as(f32, 0.165132194501668), sRGB.toLinear(113 / 255.0), epsilon);
try std.testing.expectApproxEqAbs(@as(f32, 0.296138270798321), sRGB.toLinear(148 / 255.0), epsilon);
try std.testing.expectApproxEqAbs(@as(f32, 0.450785782838223), sRGB.toLinear(179 / 255.0), epsilon);
try std.testing.expectApproxEqAbs(@as(f32, 0.590618840919337), sRGB.toLinear(202 / 255.0), epsilon);
try std.testing.expectApproxEqAbs(@as(f32, 0.879622396887832), sRGB.toLinear(241 / 255.0), epsilon);
try std.testing.expectApproxEqAbs(@as(f32, 1.0), sRGB.toLinear(255 / 255.0), epsilon);
}
test "linearToSRGB" {
const epsilon = 0.000001;
try std.testing.expectEqual(@as(f32, 0), sRGB.toGamma(sRGB.toLinear(0)));
try std.testing.expectApproxEqAbs(@as(f32, 1 / 255.0), sRGB.toGamma(sRGB.toLinear(1 / 255.0)), epsilon);
try std.testing.expectApproxEqAbs(@as(f32, 5 / 255.0), sRGB.toGamma(sRGB.toLinear(5 / 255.0)), epsilon);
try std.testing.expectApproxEqAbs(@as(f32, 20 / 255.0), sRGB.toGamma(sRGB.toLinear(20 / 255.0)), epsilon);
try std.testing.expectApproxEqAbs(@as(f32, 50 / 255.0), sRGB.toGamma(sRGB.toLinear(50 / 255.0)), epsilon);
try std.testing.expectApproxEqAbs(@as(f32, 82 / 255.0), sRGB.toGamma(sRGB.toLinear(82 / 255.0)), epsilon);
try std.testing.expectApproxEqAbs(@as(f32, 93 / 255.0), sRGB.toGamma(sRGB.toLinear(93 / 255.0)), epsilon);
try std.testing.expectApproxEqAbs(@as(f32, 113 / 255.0), sRGB.toGamma(sRGB.toLinear(113 / 255.0)), epsilon);
try std.testing.expectApproxEqAbs(@as(f32, 148 / 255.0), sRGB.toGamma(sRGB.toLinear(148 / 255.0)), epsilon);
try std.testing.expectApproxEqAbs(@as(f32, 179 / 255.0), sRGB.toGamma(sRGB.toLinear(179 / 255.0)), epsilon);
try std.testing.expectApproxEqAbs(@as(f32, 202 / 255.0), sRGB.toGamma(sRGB.toLinear(202 / 255.0)), epsilon);
try std.testing.expectApproxEqAbs(@as(f32, 241 / 255.0), sRGB.toGamma(sRGB.toLinear(241 / 255.0)), epsilon);
try std.testing.expectApproxEqAbs(@as(f32, 1.0), sRGB.toGamma(sRGB.toLinear(255 / 255.0)), epsilon);
}
test "getByName" {
try std.testing.expectEqual(@as(?*const RGBColorSpace, null), getRGBColorSpaceByName("BT709"));
try std.testing.expectEqual(&rec709, getRGBColorSpaceByName("BT.709").?);
try std.testing.expectEqual(&rec709, getRGBColorSpaceByName("HDTV").?);
try std.testing.expectEqual(&rec2020, getRGBColorSpaceByName("BT.2020").?);
try std.testing.expectEqual(&rec2020, getRGBColorSpaceByName("UHDTV").?);
for (rgbColorSpaces) |space| {
try std.testing.expectEqual(space, getRGBColorSpaceByName(space.id).?);
}
}
test "getByPoints" {
for (rgbColorSpaces) |space| {
const fspace = getRGBColorSpaceByPoints(space.white, space.red.x, space.red.y, space.green.x, space.green.y, space.blue.x, space.blue.y);
if (space == &rec709) {
// rec709 has same xy values as sRGB so it should match sRGB which has bigger priority
try std.testing.expectEqualStrings(sRGB.id, fspace.?.id);
} else if (space == &displayP3) {
// displayP3 has same xy values as p3d65 with only difference in gamma so it should match p3d65 which has bigger priority
try std.testing.expectEqualStrings(p3d65.id, fspace.?.id);
} else {
try std.testing.expectEqualStrings(space.id, fspace.?.id);
}
}
} | src/color/colorspace.zig |
const std = @import("std");
const mem = std.mem;
const Allocator = mem.Allocator;
const process = std.process;
const Codegen = @import("Codegen.zig");
const Compilation = @import("Compilation.zig");
const Source = @import("Source.zig");
const Preprocessor = @import("Preprocessor.zig");
const Parser = @import("Parser.zig");
var general_purpose_allocator = std.heap.GeneralPurposeAllocator(.{}){};
pub fn main() u8 {
const gpa = if (std.builtin.link_libc)
std.heap.raw_c_allocator
else
&general_purpose_allocator.allocator;
defer if (!std.builtin.link_libc) {
_ = general_purpose_allocator.deinit();
};
var arena_instance = std.heap.ArenaAllocator.init(gpa);
defer arena_instance.deinit();
const arena = &arena_instance.allocator;
const args = process.argsAlloc(arena) catch {
std.debug.print("out of memory\n", .{});
return 1;
};
var comp = Compilation.init(gpa);
defer comp.deinit();
handleArgs(&comp, args) catch |err| switch (err) {
error.OutOfMemory => {
std.debug.print("out of memory\n", .{});
return 1;
},
error.FatalError => comp.renderErrors(),
};
return @boolToInt(comp.diag.errors != 0);
}
const usage =
\\Usage {s}: [options] file..
\\
\\General options:
\\ -h, --help Print this message.
\\ -v, --version Print aro version.
\\
\\Compile options:
\\ -c Only run preprocess, compile, and assemble steps
\\ -D <macro>=<value> Define <macro> to <value> (defaults to 1)
\\ -E Only run the preprocessor
\\ -fcolor-diagnostics Enable colors in diagnostics
\\ -fno-color-diagnostics Disable colors in diagnostics
\\ -I <dir> Add directory to include search path
\\ -isystem Add directory to SYSTEM include search path
\\ -o <file> Write output to <file>
\\ -std=<standard> Specify language standard
\\ --target=<value> Generate code for the given target
\\ -U <macro> Undefine <macro>
\\ -Wall Enable all warnings
\\ -Werror Treat all warnings as errors
\\ -Werror=<warning> Treat warning as error
\\ -W<warning> Enable the specified warning
\\ -Wno-<warning> Disable the specified warning
\\
\\Depub options:
\\ --verbose-ast Dump produced AST to stdout
\\
\\
;
fn handleArgs(comp: *Compilation, args: [][]const u8) !void {
comp.defineSystemIncludes() catch |err| switch (err) {
error.OutOfMemory => return error.OutOfMemory,
error.SelfExeNotFound => return comp.diag.fatalNoSrc("could not find Aro executable path", .{}),
error.AroIncludeNotFound => return comp.diag.fatalNoSrc("could not find Aro builtin headers", .{}),
};
var source_files = std.ArrayList(Source).init(comp.gpa);
defer source_files.deinit();
var macro_buf = std.ArrayList(u8).init(comp.gpa);
defer macro_buf.deinit();
var i: usize = 1;
while (i < args.len) : (i += 1) {
const arg = args[i];
if (mem.startsWith(u8, arg, "-")) {
if (mem.eql(u8, arg, "-h") or mem.eql(u8, arg, "--help")) {
const std_out = std.io.getStdOut().writer();
std_out.print(usage, .{args[0]}) catch |err| {
return comp.diag.fatalNoSrc("{s} when trying to print usage", .{@errorName(err)});
};
return;
} else if (mem.eql(u8, arg, "-v") or mem.eql(u8, arg, "--version")) {
const std_out = std.io.getStdOut().writer();
std_out.writeAll(@import("lib.zig").version_str ++ "\n") catch |err| {
return comp.diag.fatalNoSrc("{s} when trying to print version", .{@errorName(err)});
};
return;
} else if (mem.eql(u8, arg, "-c")) {
comp.only_compile = true;
} else if (mem.startsWith(u8, arg, "-D")) {
var macro = arg["-D".len..];
if (macro.len == 0) {
i += 1;
if (i >= args.len) return comp.diag.fatalNoSrc("expected argument after -I", .{});
macro = args[i];
}
var value: []const u8 = "1";
if (mem.indexOfScalar(u8, macro, '=')) |some| {
value = macro[some + 1 ..];
macro = macro[0..some];
}
try macro_buf.writer().print("#define {s} {s}\n", .{ macro, value });
} else if (mem.startsWith(u8, arg, "-U")) {
var macro = arg["-U".len..];
if (macro.len == 0) {
i += 1;
if (i >= args.len) return comp.diag.fatalNoSrc("expected argument after -I", .{});
macro = args[i];
}
try macro_buf.writer().print("#undef {s}\n", .{macro});
} else if (mem.eql(u8, arg, "-E")) {
comp.only_preprocess = true;
} else if (mem.eql(u8, arg, "-fcolor-diagnostics")) {
comp.diag.color = true;
} else if (mem.eql(u8, arg, "-fno-color-diagnostics")) {
comp.diag.color = false;
} else if (mem.startsWith(u8, arg, "-I")) {
var path = arg["-I".len..];
if (path.len == 0) {
i += 1;
if (i >= args.len) return comp.diag.fatalNoSrc("expected argument after -I", .{});
path = args[i];
}
try comp.include_dirs.append(path);
} else if (mem.startsWith(u8, arg, "-isystem")) {
var path = arg["-isystem".len..];
if (path.len == 0) {
i += 1;
if (i >= args.len) return comp.diag.fatalNoSrc("expected argument after -isystem", .{});
path = args[i];
}
try comp.system_include_dirs.append(path);
} else if (mem.startsWith(u8, arg, "-o")) {
var file = arg["-o".len..];
if (file.len == 0) {
i += 1;
if (i >= args.len) return comp.diag.fatalNoSrc("expected argument after -o", .{});
file = args[i];
}
comp.output_name = file;
} else if (mem.eql(u8, arg, "-Wall")) {
comp.diag.setAll(.warning);
} else if (mem.eql(u8, arg, "-Werror")) {
comp.diag.setAll(.@"error");
} else if (mem.startsWith(u8, arg, "-Werror=")) {
const option = arg["-Werror=".len..];
try comp.diag.set(option, .@"error");
} else if (mem.startsWith(u8, arg, "-Wno-")) {
const option = arg["-Wno-".len..];
try comp.diag.set(option, .off);
} else if (mem.startsWith(u8, arg, "-W")) {
const option = arg["-W".len..];
try comp.diag.set(option, .warning);
} else if (mem.startsWith(u8, arg, "-std=")) {
const standard = arg["-std=".len..];
comp.langopts.setStandard(standard) catch
return comp.diag.fatalNoSrc("Invalid standard '{s}'", .{standard});
} else if (mem.startsWith(u8, arg, "--target=")) {
const triple = arg["--target=".len..];
const cross = std.zig.CrossTarget.parse(.{ .arch_os_abi = triple }) catch
return comp.diag.fatalNoSrc("Invalid target '{s}'", .{triple});
comp.target = cross.toTarget(); // TODO deprecated
} else if (mem.eql(u8, arg, "--verbose-ast")) {
comp.verbose_ast = true;
} else {
const std_out = std.io.getStdErr().writer();
std_out.print(usage, .{args[0]}) catch {};
return comp.diag.fatalNoSrc("unknown command: {s}", .{arg});
}
} else {
const file = comp.addSource(arg) catch |err| return comp.diag.fatalNoSrc("{s}", .{@errorName(err)});
try source_files.append(file);
}
}
if (source_files.items.len == 0) {
return comp.diag.fatalNoSrc("no input files", .{});
} else if (source_files.items.len != 1 and comp.output_name != null) {
return comp.diag.fatalNoSrc("cannot specify -o when generating multiple output files", .{});
}
const builtin = try comp.generateBuiltinMacros();
const user_macros = blk: {
const duped_path = try comp.gpa.dupe(u8, "<command line>");
errdefer comp.gpa.free(duped_path);
const contents = macro_buf.toOwnedSlice();
errdefer comp.gpa.free(contents);
const source = Source{
.id = @intToEnum(Source.Id, comp.sources.count() + 2),
.path = duped_path,
.buf = contents,
};
try comp.sources.put(duped_path, source);
break :blk source;
};
for (source_files.items) |source| {
processSource(comp, source, builtin, user_macros) catch |e| switch (e) {
error.OutOfMemory => return error.OutOfMemory,
error.FatalError => {},
};
}
}
fn processSource(comp: *Compilation, source: Source, builtin: Source, user_macros: Source) !void {
var pp = Preprocessor.init(comp);
defer pp.deinit();
try pp.preprocess(builtin);
try pp.preprocess(user_macros);
try pp.preprocess(source);
try pp.tokens.append(pp.comp.gpa, .{
.id = .eof,
.loc = .{ .id = source.id, .byte_offset = @intCast(u32, source.buf.len) },
});
if (comp.only_preprocess) {
comp.renderErrors();
const file = if (comp.output_name) |some|
std.fs.cwd().createFile(some, .{}) catch |err|
return comp.diag.fatalNoSrc("{s} when trying to create output file", .{@errorName(err)})
else
std.io.getStdOut();
defer if (comp.output_name != null) file.close();
return pp.prettyPrintTokens(file.writer()) catch |err|
comp.diag.fatalNoSrc("{s} when trying to print tokens", .{@errorName(err)});
}
var tree = try Parser.parse(&pp);
defer tree.deinit();
if (comp.verbose_ast) {
var buf_writer = std.io.bufferedWriter(std.io.getStdOut().writer());
tree.dump(buf_writer.writer()) catch {};
buf_writer.flush() catch {};
}
const prev_errors = comp.diag.errors;
comp.renderErrors();
if (comp.diag.errors != prev_errors) return; // do not compile if there were errors
if (comp.target.getObjectFormat() != .elf or comp.target.cpu.arch != .x86_64) {
return comp.diag.fatalNoSrc(
"unsupported target {s}-{s}-{s}, currently only x86-64 elf is supported",
.{ @tagName(comp.target.cpu.arch), @tagName(comp.target.os.tag), @tagName(comp.target.abi) },
);
}
const obj = try Codegen.generateTree(comp, tree);
defer obj.deinit();
const basename = std.fs.path.basename(source.path);
const out_file_name = comp.output_name orelse try std.fmt.allocPrint(comp.gpa, "{s}{s}", .{
basename[0 .. basename.len - std.fs.path.extension(source.path).len],
comp.target.getObjectFormat().fileExt(comp.target.cpu.arch),
});
defer if (comp.output_name == null) comp.gpa.free(out_file_name);
const out_file = std.fs.cwd().createFile(out_file_name, .{}) catch |err|
return comp.diag.fatalNoSrc("could not create output file '{s}': {s}", .{ out_file_name, @errorName(err) });
defer out_file.close();
obj.finish(out_file) catch |err|
return comp.diag.fatalNoSrc("could output to object file '{s}': {s}", .{ out_file_name, @errorName(err) });
if (comp.only_compile) return;
// TODO invoke linker
}
test {
_ = @import("Codegen.zig");
_ = @import("Compilation.zig");
_ = @import("Diagnostics.zig");
_ = @import("InitList.zig");
_ = @import("Parser.zig");
_ = @import("Preprocessor.zig");
_ = @import("Source.zig");
_ = @import("Tokenizer.zig");
_ = @import("Tree.zig");
_ = @import("Type.zig");
} | src/main.zig |
const zervo = @import("zervo");
const std = @import("std");
const ssl = @import("ssl");
const GraphicsBackend = @import("cairo.zig").CairoBackend;
const RenderContext = zervo.renderer.RenderContext(GraphicsBackend);
const imr = zervo.markups.imr;
const os = std.os;
const net = std.net;
const warn = std.debug.warn;
const Allocator = std.mem.Allocator;
//pub const io_mode = .evented;
const DISABLE_IPV6 = false;
var gpa = std.heap.GeneralPurposeAllocator(.{}) {};
const allocator = &gpa.allocator;
var currentUrl: ?zervo.Url = null;
var addressBar: [:0]u8 = undefined;
var addressBarFocused: bool = false;
var renderCtx: RenderContext = undefined;
var firstLoad: bool = true;
const LoadResult = union(enum) {
Document: imr.Document,
Download: []const u8
};
const LoadErrorDetails = union(enum) {
Input: []const u8
};
fn loadHttp(addr: net.Address, url: zervo.Url) !imr.Document {
var headers = zervo.protocols.http.HeaderMap.init(allocator);
try headers.put("Connection", .{
.value = "close"
});
try headers.put("User-Agent", .{
.value = "Mozilla/5.0 (X11; Linux x86_64; rv:1.0) Gecko/20100101 TestAmabob/1.0"
});
defer headers.deinit();
var response = try zervo.protocols.http.request(allocator, addr, .{
.host = url.host,
.path = url.path,
.headers = headers,
.secure = true
});
defer response.deinit();
const doc = try zervo.markups.html.parse_imr(allocator, response.content);
return doc;
}
fn loadGemini(addr: net.Address, url: zervo.Url, loadErrorDetails: *LoadErrorDetails) !LoadResult {
var errorDetails: zervo.protocols.gemini.GeminiErrorDetails = undefined;
var response = zervo.protocols.gemini.request(allocator, addr, url, &errorDetails) catch |err| switch (err) {
error.KnownError, error.InputRequired => {
errorDetails.deinit();
switch (errorDetails) {
.Input => |input| {
return error.InputRequired;
},
.PermanentFailure => |failure| {
return error.NotFound;
},
else => unreachable
}
},
else => return err
};
defer response.deinit();
if (response.statusCode != 20 and false) {
std.log.err("Request error:\nStatus code: {} {s}", .{response.statusCode, response.meta});
return zervo.protocols.gemini.GeminiError.InvalidStatus;
}
const mime = response.meta;
if (try zervo.markups.from_mime(allocator, url, mime, response.content)) |doc| {
return LoadResult {
.Document = doc
};
} else {
return LoadResult {
.Download = try allocator.dupe(u8, response.content)
};
}
}
fn loadPage(url: zervo.Url) !LoadResult {
std.log.debug("Loading web page at {} host = {s}", .{url, url.host});
var defaultPort: u16 = 80;
if (std.mem.eql(u8, url.scheme, "gemini")) defaultPort = 1965;
if (std.mem.eql(u8, url.scheme, "https")) defaultPort = 443;
const list = try net.getAddressList(allocator, url.host, url.port orelse defaultPort);
defer list.deinit();
if (list.addrs.len == 0) return error.UnknownHostName;
var addr = list.addrs[0];
if (DISABLE_IPV6) {
var i: u32 = 1;
while (addr.any.family == os.AF_INET6) : (i += 1) {
addr = list.addrs[i];
}
}
std.log.debug("Resolved address of {s}: {}", .{url.host, addr});
if (std.mem.eql(u8, url.scheme, "gemini")) {
var details: LoadErrorDetails = undefined;
const doc = try loadGemini(addr, url, &details);
return doc;
} else {
std.log.err("No handler for URL scheme {s}", .{url.scheme});
return error.UnhandledUrlScheme;
}
}
fn loadPageChecked(url: zervo.Url) ?LoadResult {
const doc = loadPage(url) catch |err| {
const name = @errorName(err);
const path = std.mem.concat(allocator, u8, &[_][]const u8 {"res/errors/", name, ".gmi"}) catch unreachable;
defer allocator.free(path);
const file = std.fs.cwd().openFile(path, .{}) catch |e| {
std.log.err("Missing error page for error {s}", .{@errorName(err)});
if (@errorReturnTrace()) |trace| {
std.debug.dumpStackTrace(trace.*);
}
return null;
};
const full = file.readToEndAlloc(allocator, std.math.maxInt(usize)) catch unreachable;
const errorDoc = zervo.markups.gemini.parse(allocator, url, full) catch unreachable;
return LoadResult { .Document = errorDoc };
};
return doc;
}
// Handlers
fn openPage(ctx: *RenderContext, url: zervo.Url) !void {
if (loadPageChecked(url)) |result| {
switch (result) {
.Document => |doc| {
if (currentUrl) |u| {
u.deinit();
}
currentUrl = try url.dupe(allocator);
if (!firstLoad) allocator.free(addressBar);
addressBar = try std.fmt.allocPrintZ(allocator, "{}", .{currentUrl});
if (!firstLoad) ctx.document.deinit();
ctx.document = doc;
ctx.layout();
ctx.offsetY = 0;
ctx.offsetYTarget = 0;
firstLoad = false;
},
.Download => |content| {
defer allocator.free(content);
const lastSlash = std.mem.lastIndexOfScalar(u8, url.path, '/').?;
const name = url.path[lastSlash+1..];
const file = try std.fs.cwd().createFile(name, .{});
try file.writeAll(content);
file.close();
std.log.info("Saved to {s}", .{name});
var xdg = try std.ChildProcess.init(&[_][]const u8 {"xdg-open", name}, allocator);
defer xdg.deinit();
_ = try xdg.spawnAndWait();
}
}
}
}
fn keyPressed(backend: *GraphicsBackend, key: u32, mods: u32) void {
if (addressBarFocused) {
if (key == GraphicsBackend.BackspaceKey) {
if (addressBar.len > 0) {
const len = addressBar.len;
addressBar[len-1] = 0;
addressBar = allocator.shrink(addressBar, len)[0..len-1 :0];
backend.frame_requested = true;
}
} else if (key == GraphicsBackend.EnterKey) {
const url = zervo.Url.parse(addressBar) catch |err| switch (err) {
else => {
std.log.warn("invalid url", .{});
return;
}
};
openPage(&renderCtx, url) catch unreachable;
backend.frame_requested = true;
}
} else {
if (key == GraphicsBackend.UpKey) {
RenderContext.scrollPage(backend, true);
} else if (key == GraphicsBackend.DownKey) {
RenderContext.scrollPage(backend, false);
}
}
}
fn keyTyped(backend: *GraphicsBackend, codepoint: u21) void {
if (addressBarFocused) {
var codepointOut: [4]u8 = undefined;
const codepointLength = std.unicode.utf8Encode(codepoint, &codepointOut) catch unreachable;
const utf8 = codepointOut[0..codepointLength];
const new = std.mem.concat(allocator, u8, &[_][]const u8 {addressBar, utf8}) catch unreachable;
const newZ = allocator.dupeZ(u8, new) catch unreachable;
defer allocator.free(new);
allocator.free(addressBar);
addressBar = newZ;
backend.frame_requested = true;
}
}
fn mouseButton(backend: *GraphicsBackend, button: GraphicsBackend.MouseButton, pressed: bool) void {
const cx = backend.getCursorX();
const cy = backend.getCursorY();
if (cx > 80 and cy > 10 and cx < backend.getWidth() - 10 and cy < 10 + 30) {
addressBarFocused = true;
} else {
addressBarFocused = false;
}
RenderContext.mouseButtonCallback(backend, button, pressed);
}
fn windowResize(backend: *GraphicsBackend, width: f64, height: f64) void {
renderCtx.layout();
}
// Main function
pub fn main() !void {
defer _ = gpa.deinit();
// Initialize OpenSSL.
try ssl.init();
defer ssl.deinit();
// Example URLs:
// gemini://gemini.circumlunar.space/
// gemini://drewdevault.com/
// gemini://skyjake.fi/lagrange/
const url = try zervo.Url.parse("gemini://gemini.circumlunar.space/");
var backend = try GraphicsBackend.init();
renderCtx = RenderContext { .graphics = &backend, .document = undefined, .linkCallback = openPage, .allocator = allocator };
renderCtx.setup();
renderCtx.y = 50;
try openPage(&renderCtx, url);
defer renderCtx.document.deinit();
defer allocator.free(addressBar);
defer currentUrl.?.deinit();
backend.keyTypedCb = keyTyped;
backend.keyPressedCb = keyPressed;
backend.mouseButtonCb = mouseButton;
backend.windowResizeCb = windowResize;
while (true) {
if (backend.frame_requested) {
const g = &backend;
g.clear();
renderCtx.render();
g.moveTo(0, 0);
g.setSourceRGB(0.5, 0.5, 0.5);
g.rectangle(0, 0, g.getWidth(), 50);
g.fill();
g.setSourceRGB(0.1, 0.1, 0.1);
g.rectangle(80, 10, g.getWidth() - 90, 30);
g.fill();
if (currentUrl) |u| {
g.moveTo(90, 14);
g.setFontFace("Nunito");
g.setFontSize(10);
g.setTextWrap(null);
g.setSourceRGB(1, 1, 1);
g.text(addressBar);
g.stroke();
}
}
const g = &backend;
const cx = g.getCursorX();
const cy = g.getCursorY();
if (cx > 80 and cy > 10 and cx < g.getWidth() - 10 and cy < 10 + 30) {
g.setCursor(.Text);
} else {
g.setCursor(.Normal);
}
if (!backend.update()) {
break;
}
}
backend.deinit();
} | src/main.zig |
const std = @import("std");
const mem = std.mem;
const Allocator = std.mem.Allocator;
const ArrayList = std.ArrayList;
const debug = std.debug;
const parse = @import("parse.zig");
const compile = @import("compile.zig");
const Parser = parse.Parser;
const Expr = parse.Expr;
const Assertion = parse.Assertion;
const Compiler = compile.Compiler;
const Program = compile.Program;
const InstructionData = compile.InstructionData;
const Input = @import("input.zig").Input;
const SaveRestore = struct {
// slot position to restore
slot: usize,
// position to store in slot
last_pos: usize,
};
const Thread = struct {
// instruction pointer
ip: usize,
// Current input position
input: Input,
};
const Job = union(enum) {
Thread: Thread,
SaveRestore: SaveRestore,
};
const ExecState = struct {
const BitsetLen = 512;
const BitsetType = u32;
// pending jobs
jobs: ArrayList(Job),
// cache (we can bound this visited bitset since we bound when we use the backtracking engine.
visited: [BitsetLen]BitsetType,
prog: *const Program,
slots: *ArrayList(?usize),
};
// This is bounded and only used for small compiled regexes. It is not quadratic since pre-seen
// nodes are cached across threads.
pub const VmBacktrack = struct {
const Self = @This();
allocator: *Allocator,
pub fn init(allocator: *Allocator) Self {
return Self{ .allocator = allocator };
}
pub fn shouldExec(prog: Program, input: *const Input) bool {
return (prog.insts.len + 1) * (input.bytes.len + 1) < ExecState.BitsetLen * @sizeOf(ExecState.BitsetType);
}
pub fn exec(self: *Self, prog: Program, prog_start: usize, input: *Input, slots: *ArrayList(?usize)) !bool {
// Should never run this without first checking shouldExec and running only if true.
debug.assert(shouldExec(prog, input));
var state = ExecState{
.jobs = ArrayList(Job).init(self.allocator),
.visited = [_]u32{0} ** 512,
.prog = &prog,
.slots = slots,
};
defer state.jobs.deinit();
const t = Job{ .Thread = Thread{ .ip = prog_start, .input = input.clone() } };
try state.jobs.append(t);
while (state.jobs.popOrNull()) |job| {
switch (job) {
Job.Thread => |thread| {
if (try step(&state, &thread)) {
return true;
}
},
Job.SaveRestore => |save| {
if (save.slot < state.slots.items.len) {
state.slots.items[save.slot] = save.last_pos;
}
},
}
}
return false;
}
fn step(state: *ExecState, thread: *const Thread) !bool {
// For linear actions, we can just modify the current thread and avoid pushing new items
// to the stack.
var input = thread.input;
var ip = thread.ip;
while (true) {
const inst = state.prog.insts[ip];
const at = input.current();
if (!shouldVisit(state, ip, input.byte_pos)) {
return false;
}
switch (inst.data) {
InstructionData.Char => |ch| {
if (at == null or at.? != ch) {
return false;
}
input.advance();
},
InstructionData.EmptyMatch => |assertion| {
if (!input.isEmptyMatch(assertion)) {
return false;
}
},
InstructionData.ByteClass => |class| {
if (at == null or !class.contains(at.?)) {
return false;
}
input.advance();
},
InstructionData.AnyCharNotNL => {
if (at == null or at.? == '\n') {
return false;
}
input.advance();
},
InstructionData.Save => |slot| {
// Our capture array may not be long enough, extend and fill with empty
while (state.slots.items.len <= slot) {
// TODO: Can't append null as optional
try state.slots.append(0);
state.slots.items[state.slots.items.len - 1] = null;
}
// We can save an existing match by creating a job which will run on this thread
// failing. This will reset to the old match before any subsequent splits in
// this thread.
if (state.slots.items[slot]) |last_pos| {
const job = Job{
.SaveRestore = SaveRestore{
.slot = slot,
.last_pos = last_pos,
},
};
try state.jobs.append(job);
}
state.slots.items[slot] = input.byte_pos;
},
InstructionData.Match => {
return true;
},
InstructionData.Jump => {
// Jump at end of loop
},
InstructionData.Split => |split| {
const t = Job{ .Thread = Thread{ .ip = split, .input = input.clone() } };
try state.jobs.append(t);
},
}
ip = inst.out;
}
}
// checks if we have visited this specific node and if not, set the bit and return true
fn shouldVisit(state: *ExecState, ip: usize, at: usize) bool {
const BitsetType = ExecState.BitsetType;
const BitsetShiftType = std.math.Log2Int(BitsetType);
const size = @sizeOf(BitsetType);
const n = ip * (state.prog.insts.len + 1) + at;
const bitmask = @intCast(BitsetType, 1) << @intCast(BitsetShiftType, n & (size - 1));
if ((state.visited[n / size] & bitmask) != 0) {
return false;
}
state.visited[n / size] |= bitmask;
return true;
}
}; | src/vm_backtrack.zig |
const std = @import("std");
const assert = std.debug.assert;
pub const Deck = struct {
const MAX_SIZE = 10010;
size: isize,
first: isize,
step: isize,
pub fn init(size: isize) Deck {
var self = Deck{
.size = size,
.first = 0,
.step = 1,
};
return self;
}
pub fn deinit(self: *Deck) void {
_ = self;
}
pub fn get_card(self: *Deck, pos: isize) isize {
var r = pos * self.step;
r = @mod(r, self.size);
var p = self.first + self.size + r;
p = @mod(p, self.size);
return p;
}
pub fn get_pos(self: *Deck, card: isize) isize {
var p: isize = 0;
while (p < self.size) : (p += 1) {
const c = self.get_card(p);
if (c == card) return p;
}
return 0;
}
pub fn deal_into_new_stack(self: *Deck) void {
self.first = @mod(self.first - self.step, self.size);
self.step = -self.step;
}
pub fn cut_N_cards(self: *Deck, n: isize) void {
var r = n * self.step;
r = @mod(r, self.size);
self.first += self.size + r;
self.first = @mod(self.first, self.size);
}
pub fn deal_with_increment_N(self: *Deck, n: isize) void {
const step: i128 = self.step;
const mod: i128 = mod_inverse(n, self.size);
const r: i128 = @mod(step * mod, self.size);
self.step = @intCast(isize, r);
}
pub fn mod_inverse(a: isize, m: isize) isize {
if (m == 1) return 0;
var p: isize = m;
var z: isize = a;
var y: isize = 0;
var x: isize = 1;
while (z > 1) {
// q is quotient
const q: isize = @divTrunc(z, p);
// p is remainder now, process same as Euclid's algorithm
const tz = p;
p = @mod(z, p);
z = tz;
// Update y and x
const tx = y;
y = x - q * y;
x = tx;
}
// Make sure x is positive
if (x < 0) x += m;
return x;
}
pub fn mod_power(b: isize, e: isize, m: isize) isize {
var res: isize = 1;
var bb: isize = @mod(b, m); // Update b if it is more than or equal to m
var ee: isize = e;
while (ee > 0) {
// If e is odd, multiply b with result
var p1: i128 = res;
p1 *= bb;
if (ee & 1 > 0) res = @intCast(isize, @mod(p1, m));
// e must be even now
ee >>= 1; // e = e/2
var p2: i128 = bb;
p2 *= bb;
bb = @intCast(isize, @mod(p2, m));
}
return res;
}
pub fn run_line(self: *Deck, line: []const u8) void {
const ops = [_][]const u8{
"deal into new stack",
"cut",
"deal with increment",
};
for (ops) |op, index| {
if (line.len < op.len) continue;
if (std.mem.eql(u8, line[0..op.len], op)) {
var arg: isize = 0;
if (line.len > op.len) {
arg = std.fmt.parseInt(i32, line[op.len + 1 ..], 10) catch unreachable;
}
// std.debug.warn("WILL RUN [{}] [{}]\n", op, arg);
if (index == 0) {
self.deal_into_new_stack();
}
if (index == 1) {
self.cut_N_cards(arg);
}
if (index == 2) {
self.deal_with_increment_N(arg);
}
// self.show();
}
}
}
pub fn show(self: *Deck) void {
std.debug.warn("DECK size {}, first {}, step {}\n", self.size, self.first, self.step);
}
};
test "new deck is sorted" {
const SIZE = 5;
var s: isize = 1;
while (s < SIZE) : (s += 1) {
var deck = Deck.init(s);
defer deck.deinit();
var j: isize = 0;
while (j < s) : (j += 1) {
assert(deck.get_card(j) == j);
}
}
}
test "new deck dealt into new stack is reversed" {
// std.debug.warn("\n");
const SIZE = 5;
var s: isize = 1;
while (s < SIZE) : (s += 1) {
var deck = Deck.init(s);
defer deck.deinit();
deck.deal_into_new_stack();
var j: isize = 0;
while (j < s) : (j += 1) {
// const c = deck.get_card(s - j - 1);
// std.debug.warn("S {}: C {} is {}, expected {}\n", s, j, c, j);
assert(deck.get_card(s - j - 1) == j);
}
}
}
test "cut N cards, positive" {
// std.debug.warn("\n");
const SIZE = 10;
var deck = Deck.init(SIZE);
defer deck.deinit();
deck.cut_N_cards(3);
// deck.show();
}
test "cut N cards, negative" {
// std.debug.warn("\n");
const SIZE = 10;
var deck = Deck.init(SIZE);
defer deck.deinit();
deck.cut_N_cards(-4);
// deck.show();
}
test "dealt with increment N" {
// std.debug.warn("\n");
const SIZE = 10;
var deck = Deck.init(SIZE);
defer deck.deinit();
deck.deal_with_increment_N(3);
// deck.show();
}
test "shuffle 1" {
// std.debug.warn("\n");
const data =
\\deal with increment 7
\\deal into new stack
\\deal into new stack
;
const expected = "0 3 6 9 2 5 8 1 4 7";
const SIZE = 10;
var deck = Deck.init(SIZE);
defer deck.deinit();
var itd = std.mem.split(u8, data, "\n");
while (itd.next()) |line| {
deck.run_line(line);
}
var ite = std.mem.split(u8, expected, " ");
var p: isize = 0;
while (ite.next()) |s| : (p += 1) {
const card = @intCast(isize, s[0] - '0');
const got = deck.get_card(p);
assert(got == card);
}
}
test "shuffle 2" {
// std.debug.warn("\n");
const data =
\\cut 6
\\deal with increment 7
\\deal into new stack
;
const expected = "3 0 7 4 1 8 5 2 9 6";
const SIZE = 10;
var deck = Deck.init(SIZE);
defer deck.deinit();
var itd = std.mem.split(u8, data, "\n");
while (itd.next()) |line| {
deck.run_line(line);
}
var ite = std.mem.split(u8, expected, " ");
var p: isize = 0;
while (ite.next()) |s| : (p += 1) {
const card = @intCast(isize, s[0] - '0');
const got = deck.get_card(p);
assert(got == card);
}
}
test "shuffle 3" {
// std.debug.warn("\n");
const data =
\\deal with increment 7
\\deal with increment 9
\\cut -2
;
const expected = "6 3 0 7 4 1 8 5 2 9";
const SIZE = 10;
var deck = Deck.init(SIZE);
defer deck.deinit();
var itd = std.mem.split(u8, data, "\n");
while (itd.next()) |line| {
deck.run_line(line);
}
var ite = std.mem.split(u8, expected, " ");
var p: isize = 0;
while (ite.next()) |s| : (p += 1) {
const card = @intCast(isize, s[0] - '0');
const got = deck.get_card(p);
assert(got == card);
}
}
test "shuffle 4" {
// std.debug.warn("\n");
const data =
\\deal into new stack
\\cut -2
\\deal with increment 7
\\cut 8
\\cut -4
\\deal with increment 7
\\cut 3
\\deal with increment 9
\\deal with increment 3
\\cut -1
;
const expected = "9 2 5 8 1 4 7 0 3 6";
const SIZE = 10;
var deck = Deck.init(SIZE);
defer deck.deinit();
var itd = std.mem.split(u8, data, "\n");
while (itd.next()) |line| {
deck.run_line(line);
}
var ite = std.mem.split(u8, expected, " ");
var p: isize = 0;
while (ite.next()) |s| : (p += 1) {
const card = @intCast(isize, s[0] - '0');
const got = deck.get_card(p);
assert(got == card);
}
} | 2019/p22/deck.zig |
const std = @import("std");
const tools = @import("tools");
const with_trace = false;
const assert = std.debug.assert;
fn trace(comptime fmt: []const u8, args: anytype) void {
if (with_trace) std.debug.print(fmt, args);
}
const Map = struct {
tiles: []const u8,
width: usize,
height: usize,
stride: usize,
};
const Vec2 = @Vector(2, i32);
fn pgcd(_a: u32, _b: u32) u32 {
var a = _a;
var b = _b;
while (b != 0) {
var t = b;
b = a % b;
a = t;
}
return a;
}
fn abs(a: i32) u32 {
return @intCast(u32, std.math.absInt(a) catch unreachable);
}
fn normalize(d: Vec2) Vec2 {
const div = pgcd(abs(d[0]), abs(d[1]));
return @divExact(d, @intCast(Vec2, @splat(2, div)));
}
fn includes(list: []Vec2, e: Vec2) bool {
for (list) |it| {
if (@reduce(.And, e == it)) return true;
} else return false;
}
fn angleLessThan(_: void, a: Vec2, b: Vec2) bool {
const angle_a = std.math.atan2(f32, @intToFloat(f32, a[0]), @intToFloat(f32, a[1]));
const angle_b = std.math.atan2(f32, @intToFloat(f32, b[0]), @intToFloat(f32, b[1]));
return angle_a > angle_b;
}
pub fn run(input: []const u8, gpa: std.mem.Allocator) ![2][]const u8 {
var arena = std.heap.ArenaAllocator.init(gpa);
defer arena.deinit();
const allocator = arena.allocator();
// parse map:
const map = blk: {
const line_len = std.mem.indexOfScalar(u8, input, '\n') orelse return error.UnsupportedInput;
break :blk Map{
.tiles = input,
.width = line_len,
.stride = 1 + line_len,
.height = (input.len + 1) / (line_len + 1),
};
};
// liste des astéroïdes:
const asteroids = blk: {
var list = std.ArrayList(Vec2).init(allocator);
for (map.tiles) |t, i| {
if (t != '#') continue;
const x0 = @intCast(i32, i % map.stride);
const y0 = @intCast(i32, i / map.stride);
try list.append(Vec2{ x0, y0 });
}
trace("nb astéroïdes: {}\n", .{list.items.len});
break :blk list.items;
};
// part1
var best_i: usize = undefined;
var best_dirs: []Vec2 = undefined;
var best = ans: {
var best_visibility: usize = 0;
for (asteroids) |a, i| {
var dirs = std.ArrayList(Vec2).init(gpa);
defer dirs.deinit();
for (asteroids) |o, j| {
if (i == j) continue;
const d = normalize(o - a);
if (!includes(dirs.items, d)) {
try dirs.append(d);
}
}
if (dirs.items.len > best_visibility) {
best_visibility = dirs.items.len;
best_i = i;
best_dirs = try allocator.dupe(Vec2, dirs.items);
}
}
break :ans best_visibility;
};
const asteroid200 = ans: {
// sort by angle:
std.sort.sort(Vec2, best_dirs, {}, angleLessThan);
// carte des astéroïdes pas encore détruits:
const alive = try allocator.alloc(u1, map.width * map.height);
defer allocator.free(alive);
{
std.mem.set(u1, alive, 0);
for (asteroids) |a| {
const x = @intCast(usize, a[0]);
const y = @intCast(usize, a[1]);
alive[map.width * y + x] = 1;
}
}
const orig = asteroids[best_i];
const bound = Vec2{ @intCast(i32, map.width), @intCast(i32, map.height) };
var destroy_count: u32 = 0;
while (true) {
for (best_dirs) |d| {
var p = orig + d;
next_dir: while (@reduce(.And, p >= Vec2{ 0, 0 }) and @reduce(.And, p < bound)) : (p += d) {
const x = @intCast(usize, p[0]);
const y = @intCast(usize, p[1]);
if (alive[map.width * y + x] != 0) {
alive[map.width * y + x] = 0;
destroy_count += 1;
if (destroy_count == 200) break :ans x * 100 + y;
break :next_dir;
}
}
}
}
unreachable;
};
return [_][]const u8{
try std.fmt.allocPrint(gpa, "{}", .{best}),
try std.fmt.allocPrint(gpa, "{}", .{asteroid200}),
};
}
pub const main = tools.defaultMain("2019/day10.txt", run); | 2019/day10.zig |
const builtin = @import("builtin");
const std = @import("std");
const fmt = std.fmt;
/// Parses RedisList values.
/// Uses RESP3Parser to delegate parsing of the list contents recursively.
pub const ListParser = struct {
// TODO: prevent users from unmarshaling structs out of strings
pub fn isSupported(comptime T: type) bool {
return switch (@typeInfo(T)) {
.Array => true,
.Struct => |stc| {
for (stc.fields) |f|
if (f.field_type == *anyopaque)
return false;
return true;
},
else => false,
};
}
pub fn isSupportedAlloc(comptime T: type) bool {
return switch (@typeInfo(T)) {
.Pointer => true,
else => isSupported(T),
};
}
pub fn parse(comptime T: type, comptime rootParser: type, msg: anytype) !T {
return parseImpl(T, rootParser, .{}, msg);
}
pub fn parseAlloc(comptime T: type, comptime rootParser: type, allocator: std.mem.Allocator, msg: anytype) !T {
return parseImpl(T, rootParser, .{ .ptr = allocator }, msg);
}
fn decodeArray(comptime T: type, result: []T, rootParser: anytype, allocator: anytype, msg: anytype) !void {
var foundNil = false;
var foundErr = false;
for (result) |*elem| {
if (foundNil or foundErr) {
rootParser.parse(void, msg) catch |err| switch (err) {
error.GotErrorReply => {
foundErr = true;
},
else => return err,
};
} else {
elem.* = (if (@hasField(@TypeOf(allocator), "ptr"))
rootParser.parseAlloc(T, allocator.ptr, msg)
else
rootParser.parse(T, msg)) catch |err| switch (err) {
error.GotNilReply => {
foundNil = true;
continue;
},
error.GotErrorReply => {
foundErr = true;
continue;
},
else => return err,
};
}
}
// Error takes precedence over Nil
if (foundErr) return error.GotErrorReply;
if (foundNil) return error.GotNilReply;
return;
}
pub fn parseImpl(comptime T: type, comptime rootParser: type, allocator: anytype, msg: anytype) !T {
// TODO: write real implementation
var buf: [100]u8 = undefined;
var end: usize = 0;
for (buf) |*elem, i| {
const ch = try msg.readByte();
elem.* = ch;
if (ch == '\r') {
end = i;
break;
}
}
try msg.skipBytes(1, .{});
const size = try fmt.parseInt(usize, buf[0..end], 10);
switch (@typeInfo(T)) {
else => unreachable,
.Pointer => |ptr| {
if (!@hasField(@TypeOf(allocator), "ptr")) {
@compileError("To decode a slice you need to use sendAlloc / pipeAlloc / transAlloc!");
}
var result = try allocator.ptr.alloc(ptr.child, size);
errdefer allocator.ptr.free(result);
try decodeArray(ptr.child, result, rootParser, allocator, msg);
return result;
},
.Array => |arr| {
if (arr.len != size) {
// The user requested an array but the list reply from Redis
// contains a different amount of items.
var foundErr = false;
var i: usize = 0;
while (i < size) : (i += 1) {
// Discard all the items
rootParser.parse(void, msg) catch |err| switch (err) {
error.GotErrorReply => {
foundErr = true;
},
else => return err,
};
}
// GotErrorReply takes precedence over LengthMismatch
if (foundErr) return error.GotErrorReply;
return error.LengthMismatch;
}
var result: T = undefined;
try decodeArray(arr.child, result[0..], rootParser, allocator, msg);
return result;
},
.Struct => |stc| {
var foundNil = false;
var foundErr = false;
if (stc.fields.len != size) {
// The user requested a struct but the list reply from Redis
// contains a different amount of items.
var i: usize = 0;
while (i < size) : (i += 1) {
// Discard all the items
rootParser.parse(void, msg) catch |err| switch (err) {
error.GotErrorReply => {
foundErr = true;
},
else => return err,
};
}
// GotErrorReply takes precedence over LengthMismatch
if (foundErr) return error.GotErrorReply;
return error.LengthMismatch;
}
var result: T = undefined;
inline for (stc.fields) |field| {
if (foundNil or foundErr) {
rootParser.parse(void, msg) catch |err| switch (err) {
error.GotErrorReply => {
foundErr = true;
},
else => return err,
};
} else {
@field(result, field.name) = (if (@hasField(@TypeOf(allocator), "ptr"))
rootParser.parseAlloc(field.field_type, allocator.ptr, msg)
else
rootParser.parse(field.field_type, msg)) catch |err| switch (err) {
else => return err,
error.GotNilReply => blk: {
foundNil = true;
break :blk undefined; // I don't think I can continue here, given the inlining.
},
error.GotErrorReply => blk: {
foundErr = true;
break :blk undefined;
},
};
}
}
if (foundErr) return error.GotErrorReply;
if (foundNil) return error.GotNilReply;
return result;
},
}
}
}; | src/parser/t_list.zig |
export var buf: [10]u8 = undefined;
/// Encodes 64bit uint `src` and writes result bytes into `dest` (must
/// have at least 10 bytes capacity)
pub fn leb128_encode_u(src: u64, dest: []u8) u8 {
if (src < 0x80) {
dest[0] = @intCast(u8, src & 0x7f);
return 1;
}
var n: u8 = 0;
var x: u64 = src;
while (true) {
var byte: u8 = @intCast(u8, x & 0x7f);
x = x >> 7;
if (x != 0) {
byte |= 0x80;
}
dest[n] = byte;
n += 1;
if (x == 0) break;
}
return n;
}
/// Decodes LEB128 bytes in `src` as u64 and writes number of bytes
/// consumed into `num`.
pub fn leb128_decode_u(src: []u8, num: *u8) u64 {
var res: u64 = 0;
var shift: u6 = 0;
var n: u8 = 0;
while (n < 10) {
var byte = src[n];
res |= @intCast(u64, byte & 0x7f) << shift;
shift += 7;
n += 1;
if (byte < 0x80) {
break;
}
}
num.* = n;
return res;
}
/// Like `leb128_encode_u` but for signed integers
pub fn leb128_encode_s(_x: i64, dest: []u8) u8 {
const neg: bool = _x < 0;
if (_x >= -64 and _x < 64) {
dest[0] = @intCast(u8, _x & 0x3f) |
@intCast(u8, @boolToInt(neg)) << 6;
return 1;
}
var n: u8 = 0;
var x: i64 = _x;
var more: bool = true;
while (more) {
var byte: u8 = @intCast(u8, x & 0x7f);
var sign: bool = (byte & 0x40) > 0;
x >>= 7;
if ((x == 0 and !sign) or (x == -1 and sign)) {
more = false;
} else {
byte |= 0x80;
}
dest[n] = byte;
n += 1;
}
return n;
}
/// Like `leb128_decode_u` but for signed integers
pub fn leb128_decode_s(src: []u8, num: *u8) i64 {
var res: i64 = 0;
var shift: u6 = 0;
var n: u8 = 0;
var byte: u8 = 0;
while (true) {
byte = src[n];
res |= @intCast(i64, byte & 0x7f) << shift;
shift += 7;
n += 1;
if ((byte & 0x80) == 0 or n > 9) {
break;
}
}
if (n < 10 and (byte & 0x40) > 0) {
res |= @intCast(i64, -1) << shift;
}
num.* = n;
return res;
}
/// WASM only. JS interop to exchange data via f64 (for lack of i64/u64
/// on JS side). Writes results to exported `buf` array and returns
/// number of bytes used.
export fn leb128_encode_u_js(x: f64) u8 {
return leb128_encode_u(@floatToInt(u64, x), buf[0..]);
}
/// WASM only. JS interop to exchange data via f64 (for lack of i64/u64
/// on JS side). Consumes bytes from the exported `buf` array and returns
/// decoded value. Writes number of bytes consumed into `buf[0]`
export fn leb128_decode_u_js() f64 {
return @intToFloat(f64, leb128_decode_u(buf[0..], &buf[0]));
}
/// See `leb128_encode_u_js`
export fn leb128_encode_s_js(x: f64) u8 {
return leb128_encode_s(@floatToInt(i64, x), buf[0..]);
}
/// See `leb128_decode_u_js`
export fn leb128_decode_s_js() f64 {
return @intToFloat(f64, leb128_decode_s(buf[0..], &buf[0]));
}
const warn = @import("std").debug.warn;
const assert = @import("std").debug.assert;
const mem = @import("std").mem;
test "min safe integer" {
assert(leb128_encode_s(-9007199254740991, buf[0..]) == 8);
assert(mem.eql(u8, buf[0..8], []u8{129, 128, 128, 128, 128, 128, 128, 112}));
}
test "max safe integer" {
assert(leb128_encode_s(9007199254740991, buf[0..]) == 8);
assert(mem.eql(u8, buf[0..8], []u8{255, 255, 255, 255, 255, 255, 255, 15}));
assert(leb128_encode_u(9007199254740991, buf[0..]) == 8);
assert(mem.eql(u8, buf[0..8], []u8{255, 255, 255, 255, 255, 255, 255, 15}));
} | packages/leb128/src/leb128.zig |
const std = @import("std");
// TODO: We can't have packages in tests, so we have to import the fun-with-zig lib manually
const fun = @import("fun");
const common = @import("common.zig");
const formats = @import("formats.zig");
const debug = std.debug;
const fmt = std.fmt;
const generic = fun.generic;
const heap = std.heap;
const io = std.io;
const math = std.math;
const mem = std.mem;
const os = std.os;
const slice = generic.slice;
const lu16 = fun.platform.lu16;
const lu32 = fun.platform.lu32;
/// An in memory filesystem used as an abstraction over the filesystems found in the nintendo ds.
/// The filesystem have the following properties:
/// * Peserves the order files and folders where added to the file system.
/// * This is required, as certain nds games use indexs to fat entries when accessing data,
/// instead of path lookup.
/// * Uses posix paths for accessing files and folders.
/// * `/` is the root folder.
/// * TODO: `..` is the parent folder.
/// * TODO: `.` is the current folder.
/// * It is not `ArenaAllocator` friendly, as it uses `ArrayList` and `HashMap` as containers.
/// * TODO: We can't delete files or folders yet
pub fn Folder(comptime TFile: type) type {
return struct {
const Self = @This();
const IndexMap = std.HashMap([]const u8, usize, mem.hash_slice_u8, mem.eql_slice_u8);
const Nodes = std.ArrayList(Node);
pub const File = TFile;
pub const Node = struct {
// We both store names in `indexs` and here, so that we have access to the names
// when doing ordered iteration.
name: []const u8,
kind: Kind,
pub const Kind = union(enum) {
File: *File,
Folder: *Self,
};
};
// The parent folder. If we are root, then this is `null`
parent: ?*Self,
// Maps names -> indexs in `nodes`. Used for fast lookup.
indexs: IndexMap,
// Stores our nodes. We use an arraylist to preserve the order of created nodes.
nodes: Nodes,
/// Allocate and initialize a new filesystem.
pub fn create(a: *mem.Allocator) !*Self {
const res = try a.create(Self);
res.* = Self.init(a);
return res;
}
/// Deinitialize and free the filesystem.
pub fn destroy(folder: *Self) void {
folder.deinit();
}
pub fn init(a: *mem.Allocator) Self {
return Self{
.parent = null,
.indexs = IndexMap.init(a),
.nodes = Nodes.init(a),
};
}
pub fn deinit(folder: *Self) void {
const parent = folder.parent;
var curr: ?*Self = folder;
while (curr != parent) {
const f = curr.?;
const a = f.allocator();
if (f.nodes.popOrNull()) |node| {
switch (node.kind) {
Node.Kind.File => |file| {
file.deinit();
a.destroy(file);
},
Node.Kind.Folder => |sub_folder| curr = sub_folder,
}
} else {
var it = f.indexs.iterator();
while (it.next()) |entry|
a.free(entry.key);
f.indexs.deinit();
f.nodes.deinit();
curr = f.parent;
f.* = undefined;
a.destroy(f);
}
}
}
// TODO: ensureCapacity for HashMap?
pub fn ensureCapacity(folder: *Self, new_capacity: usize) !void {
try folder.nodes.ensureCapacity(new_capacity);
}
/// Get the allocator the filesystem uses for allocating files and folders.
pub fn allocator(folder: *Self) *mem.Allocator {
return folder.nodes.allocator;
}
/// Get the filesystesm root.
pub fn root(folder: *Self) *Self {
var res = folder;
while (res.parent) |next|
res = next;
return res;
}
/// Given a posix path, return the file at the path location.
/// Return null if no file exists and the path location.
pub fn getFile(folder: *Self, path: []const u8) ?*File {
const node = folder.get(path) orelse return null;
switch (node) {
Node.Kind.File => |res| return res,
Node.Kind.Folder => return null,
}
}
/// Given a posix path, return the folder at the path location.
/// Return null if no file exists and the path location.
pub fn getFolder(folder: *Self, path: []const u8) ?*Self {
const node = folder.get(path) orelse return null;
switch (node) {
Node.Kind.File => return null,
Node.Kind.Folder => |res| return res,
}
}
/// Check if a file or folder exists at the path location.
pub fn exists(folder: *Self, path: []const u8) bool {
return folder.get(path) != null;
}
fn get(folder: *Self, path: []const u8) ?Node.Kind {
var res = Node.Kind{ .Folder = folder.startFolder(path) };
var it = mem.tokenize(path, "/");
while (it.next()) |name| {
switch (res) {
Node.Kind.File => return null,
Node.Kind.Folder => |tmp| {
const entry = tmp.indexs.get(name) orelse return null;
const index = entry.value;
res = tmp.nodes.toSlice()[index].kind;
},
}
}
return res;
}
fn startFolder(folder: *Self, path: []const u8) *Self {
if (path.len == 0 or path[0] != '/')
return folder;
return folder.root();
}
/// Create a file in the current folder.
pub fn createFile(folder: *Self, name: []const u8, file: File) !*File {
const res = try folder.createNode(name);
res.kind = Node.Kind{ .File = try folder.allocator().create(File) };
res.kind.File.* = file;
return res.kind.File;
}
/// Create a folder in the current folder.
pub fn createFolder(folder: *Self, name: []const u8) !*Self {
const res = try folder.createNode(name);
const fold = try Self.create(folder.allocator());
fold.parent = folder;
res.kind = Node.Kind{ .Folder = fold };
return res.kind.Folder;
}
/// Create all none existing folders in `path`.
pub fn createPath(folder: *Self, path: []const u8) !*Self {
var res = folder.startFolder(path);
var it = mem.tokenize(path, "/");
while (it.next()) |name| {
if (res.indexs.get(name)) |entry| {
const node = res.nodes.toSliceConst()[entry.value];
switch (node.kind) {
Node.Kind.File => return error.FileInPath,
Node.Kind.Folder => |sub_folder| res = sub_folder,
}
} else {
res = res.createFolder(name) catch |err| {
// TODO: https://github.com/ziglang/zig/issues/769
switch (err) {
// We just checked that the folder doesn't exist, so this error
// should never happen.
error.NameExists => unreachable,
else => return err,
}
};
}
}
return res;
}
/// Create all none existing folders in `path` and creates a file at the path location.
pub fn createPathAndFile(folder: *Self, path: []const u8, file: File) !*File {
var res_folder = folder;
if (std.os.path.dirnamePosix(path)) |dirname|
res_folder = try folder.createPath(dirname);
return try res_folder.createFile(std.os.path.basenamePosix(path), file);
}
fn createNode(folder: *Self, name: []const u8) !*Node {
try validateName(name);
if (folder.indexs.contains(name))
return error.NameExists;
const a = folder.allocator();
const index = folder.nodes.len;
const owned_name = try mem.dupe(a, u8, name);
errdefer a.free(owned_name);
const res = try folder.nodes.addOne();
errdefer _ = folder.nodes.pop();
_ = try folder.indexs.put(owned_name, index);
res.name = owned_name;
return res;
}
fn validateName(name: []const u8) !void {
if (name.len == 0)
return error.InvalidName;
for (name) |char| {
if (char == '/')
return error.InvalidName;
}
}
};
}
pub const Narc = Folder(struct {
const Self = @This();
allocator: *mem.Allocator,
data: []u8,
pub fn deinit(file: *Self) void {
file.allocator.free(file.data);
file.* = undefined;
}
});
pub const Nitro = Folder(union(enum) {
const Self = @This();
Binary: Binary,
Narc: *Narc,
pub fn deinit(file: *Self) void {
switch (file.*) {
@TagType(Self).Binary => |bin| bin.allocator.free(bin.data),
@TagType(Self).Narc => |narc| narc.destroy(),
}
file.* = undefined;
}
pub const Binary = struct {
allocator: *mem.Allocator,
data: []u8,
};
});
pub const FntMainEntry = packed struct {
offset_to_subtable: lu32,
first_file_id_in_subtable: lu16,
// For the first entry in main-table, the parent id is actually,
// the total number of directories (See FNT Directory Main-Table):
// http://problemkaputt.de/gbatek.htm#dscartridgenitroromandnitroarcfilesystems
parent_id: lu16,
};
pub const FatEntry = extern struct {
start: lu32,
end: lu32,
pub fn init(offset: u32, s: u32) FatEntry {
return FatEntry{
.start = lu32.init(offset),
.end = lu32.init(offset + s),
};
}
pub fn size(entry: FatEntry) usize {
return entry.end.value() - entry.start.value();
}
};
pub fn readNitro(file: std.fs.File, allocator: *mem.Allocator, fnt: []const u8, fat: []const FatEntry) !*Nitro {
return readHelper(Nitro, file, allocator, fnt, fat, 0);
}
pub fn readNarc(file: std.fs.File, allocator: *mem.Allocator, fnt: []const u8, fat: []const FatEntry, img_base: usize) !*Narc {
return readHelper(Narc, file, allocator, fnt, fat, img_base);
}
fn readHelper(comptime F: type, file: std.fs.File, allocator: *mem.Allocator, fnt: []const u8, fat: []const FatEntry, img_base: usize) !*F {
const fnt_main_table = blk: {
const fnt_mains = slice.bytesToSliceTrim(FntMainEntry, fnt);
const first = slice.at(fnt_mains, 0) catch return error.InvalidFnt;
const res = slice.slice(fnt_mains, 0, first.parent_id.value()) catch return error.InvalidFnt;
if (res.len > 4096) return error.InvalidFnt;
break :blk res;
};
const State = struct {
folder: *F,
file_id: u16,
fnt_sub_table: []const u8,
};
var stack = std.ArrayList(State).init(allocator);
defer stack.deinit();
const root = try F.create(allocator);
errdefer root.destroy();
const fnt_first = fnt_main_table[0];
try stack.append(State{
.folder = root,
.file_id = fnt_first.first_file_id_in_subtable.value(),
.fnt_sub_table = slice.slice(fnt, fnt_first.offset_to_subtable.value(), fnt.len) catch return error.InvalidFnt,
});
while (stack.popOrNull()) |state| {
const folder = state.folder;
const file_id = state.file_id;
const fnt_sub_table = state.fnt_sub_table;
var mem_stream = io.SliceInStream.init(fnt_sub_table);
const stream = &mem_stream.stream;
const Kind = enum(u8) {
File = 0x00,
Folder = 0x80,
};
const type_length = try stream.readByte();
if (type_length == 0x80)
return error.InvalidSubTableTypeLength;
if (type_length == 0x00)
continue;
const length = type_length & 0x7F;
const kind = @intToEnum(Kind, type_length & 0x80);
debug.assert(kind == Kind.File or kind == Kind.Folder);
const name = try allocator.alloc(u8, length);
defer allocator.free(name);
try stream.readNoEof(name);
switch (kind) {
Kind.File => {
const fat_entry = slice.at(fat, file_id) catch return error.InvalidFileId;
_ = try folder.createFile(name, switch (F) {
Nitro => try readNitroFile(file, allocator, fat_entry.*, img_base),
Narc => try readNarcFile(file, allocator, fat_entry.*, img_base),
else => comptime unreachable,
});
stack.append(State{
.folder = folder,
.file_id = file_id + 1,
.fnt_sub_table = mem_stream.slice[mem_stream.pos..],
}) catch unreachable;
},
Kind.Folder => {
const id = try stream.readIntLittle(u16);
if (id < 0xF001 or id > 0xFFFF)
return error.InvalidSubDirectoryId;
const fnt_entry = slice.at(fnt_main_table, id & 0x0FFF) catch return error.InvalidSubDirectoryId;
const sub_folder = try folder.createFolder(name);
stack.append(State{
.folder = folder,
.file_id = file_id,
.fnt_sub_table = mem_stream.slice[mem_stream.pos..],
}) catch unreachable;
try stack.append(State{
.folder = sub_folder,
.file_id = fnt_entry.first_file_id_in_subtable.value(),
.fnt_sub_table = slice.slice(fnt, fnt_entry.offset_to_subtable.value(), fnt.len) catch return error.InvalidFnt,
});
},
}
}
return root;
}
pub fn readNitroFile(file: std.fs.File, allocator: *mem.Allocator, fat_entry: FatEntry, img_base: usize) !Nitro.File {
var file_in_stream = file.inStream();
narc_read: {
const names = formats.Chunk.names;
try file.seekTo(fat_entry.start.value() + img_base);
const file_start = try file.getPos();
var buffered_in_stream = io.BufferedInStream(std.fs.File.InStream.Error).init(&file_in_stream.stream);
const stream = &buffered_in_stream.stream;
const header = stream.readStruct(formats.Header) catch break :narc_read;
if (!mem.eql(u8, header.chunk_name, names.narc))
break :narc_read;
if (header.byte_order.value() != 0xFFFE)
break :narc_read;
if (header.chunk_size.value() != 0x0010)
break :narc_read;
if (header.following_chunks.value() != 0x0003)
break :narc_read;
// If we have a valid narc header, then we assume we are reading a narc
// file. All error from here, are therefore bubbled up.
const fat_header = try stream.readStruct(formats.FatChunk);
const fat_size = math.sub(u32, fat_header.header.size.value(), @sizeOf(formats.FatChunk)) catch return error.InvalidChunkSize;
if (!mem.eql(u8, fat_header.header.name, names.fat))
return error.InvalidChunkName;
if (fat_size % @sizeOf(FatEntry) != 0)
return error.InvalidChunkSize;
if (fat_size / @sizeOf(FatEntry) != fat_header.file_count.value())
return error.InvalidChunkSize;
const fat = try allocator.alloc(FatEntry, fat_header.file_count.value());
defer allocator.free(fat);
try stream.readNoEof(@sliceToBytes(fat));
const fnt_header = try stream.readStruct(formats.Chunk);
const fnt_size = math.sub(u32, fnt_header.size.value(), @sizeOf(formats.Chunk)) catch return error.InvalidChunkSize;
if (!mem.eql(u8, fnt_header.name, names.fnt))
return error.InvalidChunkName;
const fnt = try allocator.alloc(u8, fnt_size);
defer allocator.free(fnt);
try stream.readNoEof(fnt);
const fnt_mains = slice.bytesToSliceTrim(FntMainEntry, fnt);
const first_fnt = slice.at(fnt_mains, 0) catch return error.InvalidChunkSize;
const file_data_header = try stream.readStruct(formats.Chunk);
if (!mem.eql(u8, file_data_header.name, names.file_data))
return error.InvalidChunkName;
// Since we are using buffered input, be have to seek back to the narc_img_base,
// when we start reading the file system
const narc_img_base = file_start + @sizeOf(formats.Header) + fat_header.header.size.value() + fnt_header.size.value() + @sizeOf(formats.Chunk);
try file.seekTo(narc_img_base);
// If the first_fnt's offset points into it self, then there doesn't exist an
// fnt sub table and files don't have names. We therefore can't use our normal
// read function, as it relies on the fnt sub table to build the file system.
if (first_fnt.offset_to_subtable.value() < @sizeOf(FntMainEntry)) {
const narc = try Narc.create(allocator);
for (fat) |entry, i| {
var buf: [10]u8 = undefined;
const sub_file_name = try fmt.bufPrint(buf[0..], "{}", i);
const sub_file = try readNarcFile(file, allocator, entry, narc_img_base);
_ = try narc.createFile(sub_file_name, sub_file);
}
return Nitro.File{ .Narc = narc };
} else {
return Nitro.File{ .Narc = try readNarc(file, allocator, fnt, fat, narc_img_base) };
}
}
try file.seekTo(fat_entry.start.value() + img_base);
const data = try allocator.alloc(u8, fat_entry.size());
errdefer allocator.free(data);
try file_in_stream.stream.readNoEof(data);
return Nitro.File{
.Binary = Nitro.File.Binary{
.allocator = allocator,
.data = data,
},
};
}
pub fn readNarcFile(file: std.fs.File, allocator: *mem.Allocator, fat_entry: FatEntry, img_base: usize) !Narc.File {
var file_in_stream = file.inStream();
const stream = &file_in_stream.stream;
try file.seekTo(fat_entry.start.value() + img_base);
const data = try allocator.alloc(u8, fat_entry.size());
errdefer allocator.free(data);
try stream.readNoEof(data);
return Narc.File{
.allocator = allocator,
.data = data,
};
}
pub fn FntAndFiles(comptime FileType: type) type {
return struct {
files: []*FileType,
main_fnt: []FntMainEntry,
sub_fnt: []const u8,
};
}
pub fn getFntAndFiles(comptime F: type, root: *F, allocator: *mem.Allocator) !FntAndFiles(F.File) {
comptime debug.assert(F == Nitro or F == Narc);
var files = std.ArrayList(*F.File).init(allocator);
var main_fnt = std.ArrayList(FntMainEntry).init(allocator);
var sub_fnt = try std.Buffer.initSize(allocator, 0);
const State = struct {
folder: *F,
parent_id: u16,
};
var states = std.ArrayList(State).init(allocator);
var current_state: u16 = 0;
defer states.deinit();
try states.append(State{
.folder = root,
.parent_id = undefined, // We don't know the parent_id of root yet. Filling it out later
});
while (current_state < states.len) : (current_state += 1) {
const state = states.toSliceConst()[current_state];
try main_fnt.append(FntMainEntry{
// We don't know the exect offset yet, but we can save the offset from the sub tables
// base, and then calculate the real offset later.
.offset_to_subtable = lu32.init(@intCast(u32, sub_fnt.len())),
.first_file_id_in_subtable = lu16.init(@intCast(u16, files.len)),
.parent_id = lu16.init(state.parent_id),
});
for (state.folder.nodes.toSliceConst()) |node| {
// The filesystem should uphold the invariant that nodes have names that are not
// zero length.
debug.assert(node.name.len != 0x00);
switch (node.kind) {
F.Node.Kind.Folder => |folder| {
try sub_fnt.appendByte(@intCast(u8, node.name.len + 0x80));
try sub_fnt.append(node.name);
try sub_fnt.append(lu16.init(@intCast(u16, states.len + 0xF000)).bytes);
try states.append(State{
.folder = folder,
.parent_id = current_state + 0xF000,
});
},
F.Node.Kind.File => |f| {
try sub_fnt.appendByte(@intCast(u8, node.name.len));
try sub_fnt.append(node.name);
try files.append(f);
},
}
}
try sub_fnt.appendByte(0x00);
}
// Filling in root parent id
main_fnt.items[0].parent_id = lu16.init(@intCast(u16, main_fnt.len));
// We now know the real offset_to_subtable, and can therefore fill it out.
for (main_fnt.toSlice()) |*entry| {
const main_fnt_len = main_fnt.len * @sizeOf(FntMainEntry);
const offset_from_subtable_base = entry.offset_to_subtable.value();
entry.offset_to_subtable = lu32.init(@intCast(u32, offset_from_subtable_base + main_fnt_len));
}
return FntAndFiles(F.File){
.files = files.toOwnedSlice(),
.main_fnt = main_fnt.toOwnedSlice(),
.sub_fnt = sub_fnt.list.toOwnedSlice(),
};
}
pub fn writeNitroFile(file: std.fs.File, allocator: *mem.Allocator, fs_file: Nitro.File) !void {
const Tag = @TagType(Nitro.File);
switch (fs_file) {
Tag.Binary => |bin| {
try file.write(bin.data);
},
Tag.Narc => |narc| {
const fntAndFiles = try getFntAndFiles(Narc, narc, allocator);
const files = fntAndFiles.files;
const main_fnt = fntAndFiles.main_fnt;
const sub_fnt = fntAndFiles.sub_fnt;
defer {
allocator.free(files);
allocator.free(main_fnt);
allocator.free(sub_fnt);
}
const file_start = try file.getPos();
const fat_start = file_start + @sizeOf(formats.Header);
const fnt_start = fat_start + @sizeOf(formats.FatChunk) + files.len * @sizeOf(FatEntry);
const fnt_end = fnt_start + @sizeOf(formats.Chunk) + sub_fnt.len + main_fnt.len * @sizeOf(FntMainEntry);
const file_image_start = common.@"align"(fnt_end, u32(0x4));
const narc_img_base = file_image_start + @sizeOf(formats.Chunk);
const file_end = blk: {
var res = narc_img_base;
for (files) |f| {
res += f.data.len;
}
break :blk res;
};
var file_out_stream = file.outStream();
var buffered_out_stream = io.BufferedOutStream(std.fs.File.OutStream.Error).init(&file_out_stream.stream);
const stream = &buffered_out_stream.stream;
try stream.write(mem.toBytes(formats.Header.narc(@intCast(u32, file_end - file_start))));
try stream.write(mem.toBytes(formats.FatChunk{
.header = formats.Chunk{
.name = formats.Chunk.names.fat,
.size = lu32.init(@intCast(u32, fnt_start - fat_start)),
},
.file_count = lu16.init(@intCast(u16, files.len)),
.reserved = lu16.init(0x00),
}));
var start: u32 = 0;
for (files) |f| {
const len = @intCast(u32, f.data.len);
const fat_entry = FatEntry.init(start, len);
try stream.write(mem.toBytes(fat_entry));
start += len;
}
try stream.write(mem.toBytes(formats.Chunk{
.name = formats.Chunk.names.fnt,
.size = lu32.init(@intCast(u32, file_image_start - fnt_start)),
}));
try stream.write(@sliceToBytes(main_fnt));
try stream.write(sub_fnt);
try stream.writeByteNTimes(0xFF, file_image_start - fnt_end);
try stream.write(mem.toBytes(formats.Chunk{
.name = formats.Chunk.names.file_data,
.size = lu32.init(@intCast(u32, file_end - file_image_start)),
}));
for (files) |f| {
try stream.write(f.data);
}
try buffered_out_stream.flush();
},
}
} | src/fs.zig |
const std = @import("std");
const ext2 = @import("ext2");
// FIXME: What do we pass in here? Look at elf+dwarf parser for inspiration?
pub fn printSuperBlock(super_block: *const ext2.Ext2_SuperBlock) void {
std.log.info("FS Info:", .{});
std.log.info("\tMagic 0x{X}", .{super_block.s_magic});
std.log.info("\tNumber of block groups {}", .{super_block.block_group_count()});
std.log.info("\tBlock size {}", .{super_block.block_size()});
std.log.info("\tRevsion: {}.{}", .{ super_block.s_rev_level, super_block.s_minor_rev_level });
std.log.info("\ts_blocks_count {}", .{super_block.s_blocks_count});
std.log.info("\ts_first_data_block {}", .{super_block.s_first_data_block});
std.log.info("\ts_blocks_per_group {}", .{super_block.s_blocks_per_group});
std.log.info("\ts_inodes_per_group {}", .{super_block.s_inodes_per_group});
}
pub fn printBlockGroupDescriptor(block_group_descriptor: *const ext2.Ext2_BlockGroupDescriptor) void {
// TODO: Move this into a generic "format" fn and into the Ext2 lib, then info("{}", .{block_group_descriptor})
std.log.info("Block Desc Group:", .{});
std.log.info("\tblock_bitmap: {}", .{block_group_descriptor.bg_block_bitmap});
std.log.info("\tbg_inode_bitmap: {}", .{block_group_descriptor.bg_inode_bitmap});
std.log.info("\tbg_inode_table {}", .{block_group_descriptor.bg_inode_table});
std.log.info("\tbg_free_blocks_count: {}", .{block_group_descriptor.bg_free_blocks_count});
std.log.info("\tbg_free_inodes_count: {}", .{block_group_descriptor.bg_free_inodes_count});
std.log.info("\tbg_used_dirs_count: {}", .{block_group_descriptor.bg_used_dirs_count});
}
pub fn printInodeTableEntry(inode: *const ext2.Ext2_InodeTableEntry) void {
std.log.info("Inode Table Entry:", .{});
std.log.info("\ti_mode: {X:0>4}", .{inode.i_mode});
std.log.info("\ti_size: {}", .{inode.i_size});
std.log.info("\ti_atime: {}", .{inode.i_atime});
std.log.info("\ti_ctime: {}", .{inode.i_ctime});
std.log.info("\ti_mtime: {}", .{inode.i_mtime});
std.log.info("\ti_dtime: {}", .{inode.i_dtime});
std.log.info("\ti_gid: {}", .{inode.i_gid});
std.log.info("\ti_links_count: {}", .{inode.i_links_count});
std.log.info("\ti_blocks: {}", .{inode.i_blocks});
std.log.info("\ti_block[0]: {X}", .{inode.i_block[0]});
std.log.info("\ti_block[1]: {X}", .{inode.i_block[1]});
std.log.info("\ti_block[2]: {X}", .{inode.i_block[2]});
std.log.info("\ti_block[3]: {X}", .{inode.i_block[3]});
std.log.info("\ti_block[4]: {X}", .{inode.i_block[4]});
std.log.info("\ti_block[5]: {X}", .{inode.i_block[5]});
}
pub fn printDirectoryEntry(directory_entry: *const ext2.Ext2_DirectoryEntry) void {
std.log.info("Directory Entry:", .{});
std.log.info("\tinode: {}", .{directory_entry.inode});
std.log.info("\trecord_length: {}", .{directory_entry.record_length});
std.log.info("\tname_length: {}", .{directory_entry.name_length});
std.log.info("\tfile_type: {X}", .{directory_entry.file_type});
}
// FIXME: Fails when s_first_data_block == 0 (file: test1_4kb.img)
// FIXME: Division by zero when calculating block_group_count
pub fn main() anyerror!void {
std.log.info("Inspect an ext2 image (All your files are belong to us.)", .{});
const fname = "data/test3.img";
var f = std.fs.cwd().openFile(fname, std.fs.File.OpenFlags{ .read = true }) catch {
std.log.err("Error opening file: {s}", .{fname});
return;
};
var fs = try ext2.FS.mount(f);
var super_block = try fs.superblock(f);
printSuperBlock(&super_block);
var block_descriptor = try super_block.block_descriptor_at(f, 0);
printBlockGroupDescriptor(&block_descriptor);
// TODO: How to handle sparse superblocks
// FIXME: Change magic number from 2 => Ext2RootInodeIndex
var inode = try super_block.inode_table_at(f, &block_descriptor, 1); // 1 is reserved as root directory
printInodeTableEntry(&inode);
var directory_entry_iterator = try fs.directory_entry_iterator(f, &inode);
while (try directory_entry_iterator.next()) |_| {
//FIXME: Should pass in a struct containg meta + dir entry
//printDirectoryEntry(dir_entry);
switch (try directory_entry_iterator.file_type()) {
ext2.EXT2_FT_DIR => std.log.info("{s}/", .{directory_entry_iterator.name()}),
ext2.EXT2_FT_REG_FILE => std.log.info("{s}", .{directory_entry_iterator.name()}),
else => |v| std.log.info("UNKNOWN {}: {s}", .{ v, directory_entry_iterator.name() }),
}
}
}
test "basic test" {
try std.testing.expectEqual(10, 3 + 7);
} | tools/ext2fs/src/main.zig |
const builtin = @import("builtin");
const std = @import("std.zig");
const assert = std.debug.assert;
const testing = std.testing;
const os = std.os;
const math = std.math;
pub const epoch = @import("time/epoch.zig");
/// Spurious wakeups are possible and no precision of timing is guaranteed.
pub fn sleep(nanoseconds: u64) void {
if (os.windows.is_the_target) {
const ns_per_ms = ns_per_s / ms_per_s;
const big_ms_from_ns = nanoseconds / ns_per_ms;
const ms = math.cast(os.windows.DWORD, big_ms_from_ns) catch math.maxInt(os.windows.DWORD);
os.windows.kernel32.Sleep(ms);
return;
}
const s = nanoseconds / ns_per_s;
const ns = nanoseconds % ns_per_s;
std.os.nanosleep(s, ns);
}
/// Get the posix timestamp, UTC, in seconds
/// TODO audit this function. is it possible to return an error?
pub fn timestamp() u64 {
return @divFloor(milliTimestamp(), ms_per_s);
}
/// Get the posix timestamp, UTC, in milliseconds
/// TODO audit this function. is it possible to return an error?
pub fn milliTimestamp() u64 {
if (os.windows.is_the_target) {
//FileTime has a granularity of 100 nanoseconds
// and uses the NTFS/Windows epoch
var ft: os.windows.FILETIME = undefined;
os.windows.kernel32.GetSystemTimeAsFileTime(&ft);
const hns_per_ms = (ns_per_s / 100) / ms_per_s;
const epoch_adj = epoch.windows * ms_per_s;
const ft64 = (u64(ft.dwHighDateTime) << 32) | ft.dwLowDateTime;
return @divFloor(ft64, hns_per_ms) - -epoch_adj;
}
if (os.wasi.is_the_target and !builtin.link_libc) {
var ns: os.wasi.timestamp_t = undefined;
// TODO: Verify that precision is ignored
const err = os.wasi.clock_time_get(os.wasi.CLOCK_REALTIME, 1, &ns);
assert(err == os.wasi.ESUCCESS);
const ns_per_ms = 1000;
return @divFloor(ns, ns_per_ms);
}
if (os.darwin.is_the_target) {
var tv: os.darwin.timeval = undefined;
var err = os.darwin.gettimeofday(&tv, null);
assert(err == 0);
const sec_ms = tv.tv_sec * ms_per_s;
const usec_ms = @divFloor(tv.tv_usec, us_per_s / ms_per_s);
return @intCast(u64, sec_ms + usec_ms);
}
var ts: os.timespec = undefined;
//From what I can tell there's no reason clock_gettime
// should ever fail for us with CLOCK_REALTIME,
// seccomp aside.
os.clock_gettime(os.CLOCK_REALTIME, &ts) catch unreachable;
const sec_ms = @intCast(u64, ts.tv_sec) * ms_per_s;
const nsec_ms = @divFloor(@intCast(u64, ts.tv_nsec), ns_per_s / ms_per_s);
return sec_ms + nsec_ms;
}
/// Multiples of a base unit (nanoseconds)
pub const nanosecond = 1;
pub const microsecond = 1000 * nanosecond;
pub const millisecond = 1000 * microsecond;
pub const second = 1000 * millisecond;
pub const minute = 60 * second;
pub const hour = 60 * minute;
/// Divisions of a second
pub const ns_per_s = 1000000000;
pub const us_per_s = 1000000;
pub const ms_per_s = 1000;
pub const cs_per_s = 100;
/// Common time divisions
pub const s_per_min = 60;
pub const s_per_hour = s_per_min * 60;
pub const s_per_day = s_per_hour * 24;
pub const s_per_week = s_per_day * 7;
/// A monotonic high-performance timer.
/// Timer.start() must be called to initialize the struct, which captures
/// the counter frequency on windows and darwin, records the resolution,
/// and gives the user an opportunity to check for the existnece of
/// monotonic clocks without forcing them to check for error on each read.
/// .resolution is in nanoseconds on all platforms but .start_time's meaning
/// depends on the OS. On Windows and Darwin it is a hardware counter
/// value that requires calculation to convert to a meaninful unit.
pub const Timer = struct {
///if we used resolution's value when performing the
/// performance counter calc on windows/darwin, it would
/// be less precise
frequency: switch (builtin.os) {
.windows => u64,
.macosx, .ios, .tvos, .watchos => os.darwin.mach_timebase_info_data,
else => void,
},
resolution: u64,
start_time: u64,
const Error = error{TimerUnsupported};
///At some point we may change our minds on RAW, but for now we're
/// sticking with posix standard MONOTONIC. For more information, see:
/// https://github.com/ziglang/zig/pull/933
const monotonic_clock_id = os.CLOCK_MONOTONIC;
/// Initialize the timer structure.
//This gives us an opportunity to grab the counter frequency in windows.
//On Windows: QueryPerformanceCounter will succeed on anything >= XP/2000.
//On Posix: CLOCK_MONOTONIC will only fail if the monotonic counter is not
// supported, or if the timespec pointer is out of bounds, which should be
// impossible here barring cosmic rays or other such occurrences of
// incredibly bad luck.
//On Darwin: This cannot fail, as far as I am able to tell.
pub fn start() Error!Timer {
var self: Timer = undefined;
if (os.windows.is_the_target) {
self.frequency = os.windows.QueryPerformanceFrequency();
self.resolution = @divFloor(ns_per_s, self.frequency);
self.start_time = os.windows.QueryPerformanceCounter();
} else if (os.darwin.is_the_target) {
os.darwin.mach_timebase_info(&self.frequency);
self.resolution = @divFloor(self.frequency.numer, self.frequency.denom);
self.start_time = os.darwin.mach_absolute_time();
} else {
//On Linux, seccomp can do arbitrary things to our ability to call
// syscalls, including return any errno value it wants and
// inconsistently throwing errors. Since we can't account for
// abuses of seccomp in a reasonable way, we'll assume that if
// seccomp is going to block us it will at least do so consistently
var ts: os.timespec = undefined;
os.clock_getres(monotonic_clock_id, &ts) catch return error.TimerUnsupported;
self.resolution = @intCast(u64, ts.tv_sec) * u64(ns_per_s) + @intCast(u64, ts.tv_nsec);
os.clock_gettime(monotonic_clock_id, &ts) catch return error.TimerUnsupported;
self.start_time = @intCast(u64, ts.tv_sec) * u64(ns_per_s) + @intCast(u64, ts.tv_nsec);
}
return self;
}
/// Reads the timer value since start or the last reset in nanoseconds
pub fn read(self: *Timer) u64 {
var clock = clockNative() - self.start_time;
if (os.windows.is_the_target) {
return @divFloor(clock * ns_per_s, self.frequency);
}
if (os.darwin.is_the_target) {
return @divFloor(clock * self.frequency.numer, self.frequency.denom);
}
return clock;
}
/// Resets the timer value to 0/now.
pub fn reset(self: *Timer) void {
self.start_time = clockNative();
}
/// Returns the current value of the timer in nanoseconds, then resets it
pub fn lap(self: *Timer) u64 {
var now = clockNative();
var lap_time = self.read();
self.start_time = now;
return lap_time;
}
fn clockNative() u64 {
if (os.windows.is_the_target) {
return os.windows.QueryPerformanceCounter();
}
if (os.darwin.is_the_target) {
return os.darwin.mach_absolute_time();
}
var ts: os.timespec = undefined;
os.clock_gettime(monotonic_clock_id, &ts) catch unreachable;
return @intCast(u64, ts.tv_sec) * u64(ns_per_s) + @intCast(u64, ts.tv_nsec);
}
};
test "sleep" {
sleep(1);
}
test "timestamp" {
const ns_per_ms = (ns_per_s / ms_per_s);
const margin = 50;
const time_0 = milliTimestamp();
sleep(ns_per_ms);
const time_1 = milliTimestamp();
const interval = time_1 - time_0;
testing.expect(interval > 0 and interval < margin);
}
test "Timer" {
const ns_per_ms = (ns_per_s / ms_per_s);
const margin = ns_per_ms * 150;
var timer = try Timer.start();
sleep(10 * ns_per_ms);
const time_0 = timer.read();
testing.expect(time_0 > 0 and time_0 < margin);
const time_1 = timer.lap();
testing.expect(time_1 >= time_0);
timer.reset();
testing.expect(timer.read() < time_1);
} | lib/std/time.zig |
const std = @import("std");
const util = @import("util");
const input = @embedFile("7.txt");
const Map = util.Map([]const u8, Bag);
const Bag = struct {
contents: []const u8,
num_contained: ?usize = null,
has_shiny_gold: bool = false,
fn update(self: *Bag, bags: *const Map) void {
if (self.num_contained != null) return;
self.num_contained = 0;
if (std.mem.eql(u8, self.contents, "no other bags")) return;
var contents = std.mem.split(self.contents, ", ");
while (contents.next()) |bag_str| {
const num_end = std.mem.indexOf(u8, bag_str, " ").?;
const name_end = std.mem.lastIndexOf(u8, bag_str, " ").?;
const bag_count = util.parseUint(u32, bag_str[0..num_end]) catch unreachable;
const bag_name = bag_str[(num_end + 1)..name_end];
const entry = bags.getEntry(bag_name).?;
entry.value.update(bags);
if (entry.value.has_shiny_gold or std.mem.eql(u8, bag_name, "shiny gold"))
self.has_shiny_gold = true;
self.num_contained.? += bag_count * (1 + entry.value.num_contained.?);
}
}
};
pub fn main(n: util.Utils) !void {
var bags = Map{};
try bags.ensureCapacity(n.arena, 1000);
var possible_containers: usize = 0;
var lines = std.mem.tokenize(input, "\n");
while (lines.next()) |line| {
const name_end = std.mem.indexOf(u8, line, " bags ").?;
const contents_start = name_end + " bags contain ".len;
const contents_end = std.mem.indexOfPos(u8, line, contents_start, ".").?;
bags.putAssumeCapacity(line[0..name_end], .{
.contents = line[contents_start..contents_end],
});
}
for (bags.items()) |*entry| {
entry.value.update(&bags);
possible_containers += @boolToInt(entry.value.has_shiny_gold);
}
try n.out.print("{}\n{}\n", .{
possible_containers,
bags.get("shiny gold").?.num_contained.?,
});
} | 2020/7.zig |
const std = @import("std");
const shared = @import("../shared.zig");
const log = std.log.scoped(.metal_renderer);
const log_objc = std.log.scoped(.metal_renderer_objc);
pub const Renderer = struct {
allocator: *std.mem.Allocator,
lib: *std.DynLib,
params: *shared.Parameters,
objc_init: fn (cb: @TypeOf(objc_log_callback), vst_path: [*:0]u8, ptr: **c_void) callconv(.C) void,
editor_open: fn (ref: *c_void, view: *c_void) callconv(.C) void,
editor_close: fn (ref: *c_void) callconv(.C) void,
update_buffer: fn (ref: *c_void, ptr: [*]f32, len: usize) callconv(.C) void,
objc_ref: *c_void = undefined,
pub fn init(allocator: *std.mem.Allocator, params: *shared.Parameters) !Renderer {
var self: Renderer = undefined;
self.allocator = allocator;
self.params = params;
const vst_path = try resolveVSTPath(allocator);
defer allocator.free(vst_path);
const dynlib_name = "za-renderer.dynlib";
const dynlib_path = try std.fs.path.join(allocator, &[_][]const u8{
vst_path,
dynlib_name,
});
self.lib = try allocator.create(std.DynLib);
self.lib.* = try std.DynLib.open(dynlib_path);
const lookup_names = &[_][]const u8{
"editor_open",
"editor_close",
"objc_init",
"update_buffer",
};
inline for (lookup_names) |name| {
const idx = std.meta.fieldIndex(Renderer, name).?;
const info = std.meta.fields(Renderer)[idx];
@field(self, name) = self.lib.lookup(info.field_type, name ++ "\x00") orelse return error.MissingExport;
}
const c_str = try allocator.allocSentinel(u8, vst_path.len, 0);
std.mem.copy(u8, c_str, vst_path);
self.objc_init(objc_log_callback, c_str, &self.objc_ref);
return self;
}
pub fn editorOpen(self: *Renderer, view_ptr: *c_void) anyerror!void {
self.editor_open(self.objc_ref, view_ptr);
}
pub fn editorClose(self: *Renderer) void {
self.editor_close(self.objc_ref);
}
pub fn update(self: *Renderer, buffer: []f32) void {
self.update_buffer(self.objc_ref, buffer.ptr, buffer.len);
}
fn objc_log_callback(data: [*c]const u8) callconv(.C) void {
log_objc.debug("{s}", .{data});
}
};
export fn __analyzer_macos_dummy_export() void {}
fn resolveVSTPath(allocator: *std.mem.Allocator) ![]const u8 {
const dlfcn = @cImport({
@cInclude("dlfcn.h");
});
var info: dlfcn.Dl_info = undefined;
const success = dlfcn.dladdr(__analyzer_macos_dummy_export, &info);
if (success == 1) {
const name = @ptrCast([*:0]const u8, info.dli_fname);
var name_slice = try allocator.alloc(u8, std.mem.len(name));
@memcpy(name_slice.ptr, name, name_slice.len);
return std.fs.path.dirname(name_slice) orelse return error.DirnameFailed;
} else {
std.log.err("dladdr returned {}", .{success});
return error.dladdrFailed;
}
} | src/macos/renderer.zig |
const std = @import("std");
const zp = @import("zplay");
const dig = zp.deps.dig;
const alg = zp.deps.alg;
const Vec3 = alg.Vec3;
const Vec4 = alg.Vec4;
const Mat4 = alg.Mat4;
const Framebuffer = zp.graphics.common.Framebuffer;
const TextureUnit = zp.graphics.common.Texture.TextureUnit;
const Texture2D = zp.graphics.texture.Texture2D;
const TextureCube = zp.graphics.texture.TextureCube;
const Skybox = zp.graphics.@"3d".Skybox;
const Renderer = zp.graphics.@"3d".Renderer;
const SimpleRenderer = zp.graphics.@"3d".SimpleRenderer;
const Mesh = zp.graphics.@"3d".Mesh;
const Material = zp.graphics.@"3d".Material;
const Camera = zp.graphics.@"3d".Camera;
var skybox: Skybox = undefined;
var cubemap: TextureCube = undefined;
var skybox_material: Material = undefined;
var simple_renderer: SimpleRenderer = undefined;
var fb: Framebuffer = undefined;
var fb_texture: Texture2D = undefined;
var fb_material: Material = undefined;
var quad: Mesh = undefined;
var cube: Mesh = undefined;
var cube_material: Material = undefined;
var color_material: Material = undefined;
var wireframe_mode = false;
var outlined = false;
var rotate_scene_fb = false;
var camera = Camera.fromPositionAndTarget(
Vec3.new(0, 0, 3),
Vec3.zero(),
null,
);
const cube_positions = [_]Vec3{
Vec3.new(0.0, 0.0, 0.0),
Vec3.new(2.0, 5.0, -15.0),
Vec3.new(-1.5, -2.2, -2.5),
Vec3.new(-3.8, -2.0, -12.3),
Vec3.new(2.4, -0.4, -3.5),
Vec3.new(-1.7, 3.0, -7.5),
Vec3.new(1.3, -2.0, -2.5),
Vec3.new(1.5, 2.0, -2.5),
Vec3.new(1.5, 0.2, -1.5),
Vec3.new(-1.3, 1.0, -1.5),
};
fn init(ctx: *zp.Context) anyerror!void {
std.log.info("game init", .{});
// init imgui
try dig.init(ctx.window);
// allocate skybox
skybox = Skybox.init();
// allocate framebuffer
var width: u32 = undefined;
var height: u32 = undefined;
ctx.graphics.getDrawableSize(ctx.window, &width, &height);
fb_texture = try Texture2D.init(
std.testing.allocator,
null,
.rgba,
width,
height,
.{},
);
fb = try Framebuffer.fromTexture(fb_texture.tex, .{});
fb_material = Material.init(.{
.single_texture = fb_texture,
});
// simple renderer
simple_renderer = SimpleRenderer.init();
// generate mesh
quad = try Mesh.genQuad(std.testing.allocator, 2, 2);
cube = try Mesh.genCube(std.testing.allocator, 1, 1, 1);
// load texture
cubemap = try TextureCube.fromFilePath(
std.testing.allocator,
"assets/skybox/right.jpg",
"assets/skybox/left.jpg",
"assets/skybox/top.jpg",
"assets/skybox/bottom.jpg",
"assets/skybox/front.jpg",
"assets/skybox/back.jpg",
);
skybox_material = Material.init(.{
.single_cubemap = cubemap,
});
cube_material = Material.init(.{
.single_texture = try Texture2D.fromFilePath(
std.testing.allocator,
"assets/wall.jpg",
false,
.{},
),
});
color_material = Material.init(.{
.single_texture = try Texture2D.fromPixelData(
std.testing.allocator,
&.{ 0, 255, 0, 255 },
1,
1,
.{},
),
});
// alloc texture unit
var unit = fb_material.allocTextureUnit(0);
unit = cube_material.allocTextureUnit(unit);
unit = skybox_material.allocTextureUnit(unit);
_ = color_material.allocTextureUnit(unit);
}
fn loop(ctx: *zp.Context) void {
const S = struct {
var frame: f32 = 0;
};
S.frame += 1;
// camera movement
const distance = ctx.delta_tick * camera.move_speed;
if (ctx.isKeyPressed(.w)) {
camera.move(.forward, distance);
}
if (ctx.isKeyPressed(.s)) {
camera.move(.backward, distance);
}
if (ctx.isKeyPressed(.a)) {
camera.move(.left, distance);
}
if (ctx.isKeyPressed(.d)) {
camera.move(.right, distance);
}
if (ctx.isKeyPressed(.left)) {
camera.rotate(0, -1);
}
if (ctx.isKeyPressed(.right)) {
camera.rotate(0, 1);
}
if (ctx.isKeyPressed(.up)) {
camera.rotate(1, 0);
}
if (ctx.isKeyPressed(.down)) {
camera.rotate(-1, 0);
}
while (ctx.pollEvent()) |e| {
_ = dig.processEvent(e);
switch (e) {
.window_event => |we| {
switch (we.data) {
.resized => |size| {
ctx.graphics.setViewport(0, 0, size.width, size.height);
},
else => {},
}
},
.keyboard_event => |key| {
if (key.trigger_type == .up) {
switch (key.scan_code) {
.escape => ctx.kill(),
.f1 => ctx.toggleFullscreeen(null),
else => {},
}
}
},
.quit_event => ctx.kill(),
else => {},
}
}
var width: u32 = undefined;
var height: u32 = undefined;
ctx.graphics.getDrawableSize(ctx.window, &width, &height);
// settings
dig.beginFrame();
defer dig.endFrame();
{
dig.setNextWindowPos(
.{ .x = @intToFloat(f32, width) - 10, .y = 50 },
.{
.cond = dig.c.ImGuiCond_Always,
.pivot = .{ .x = 1, .y = 0 },
},
);
if (dig.begin(
"settings",
null,
dig.c.ImGuiWindowFlags_NoMove |
dig.c.ImGuiWindowFlags_NoResize |
dig.c.ImGuiWindowFlags_AlwaysAutoResize,
)) {
_ = dig.checkbox("wireframe", &wireframe_mode);
if (dig.checkbox("outlined", &outlined)) {
ctx.graphics.toggleCapability(.stencil_test, outlined);
}
if (dig.checkbox("rotate scene", &rotate_scene_fb)) {
if (rotate_scene_fb) S.frame = 0;
}
}
dig.end();
}
// render to custom framebuffer
ctx.graphics.useFramebuffer(fb);
{
ctx.graphics.toggleCapability(.depth_test, true);
ctx.graphics.clear(true, true, true, [4]f32{ 0.2, 0.3, 0.3, 1.0 });
const projection = Mat4.perspective(
45,
@intToFloat(f32, width) / @intToFloat(f32, height),
0.1,
100,
);
// draw boxes
ctx.graphics.setPolygonMode(if (wireframe_mode) .line else .fill);
renderBoxes(ctx, projection, S.frame);
// draw skybox
skybox.draw(&ctx.graphics, projection, camera, skybox_material);
}
// draw framebuffer's color texture
ctx.graphics.useFramebuffer(null);
{
ctx.graphics.setPolygonMode(.fill);
ctx.graphics.toggleCapability(.depth_test, false);
ctx.graphics.clear(true, false, false, [4]f32{ 0.3, 0.2, 0.3, 1.0 });
var model = Mat4.identity();
if (rotate_scene_fb) {
model = Mat4.fromRotation(S.frame, Vec3.up());
}
simple_renderer.renderer().begin();
simple_renderer.renderer().renderMesh(
quad,
model,
Mat4.identity(),
null,
fb_material,
null,
) catch unreachable;
simple_renderer.renderer().end();
}
}
fn renderBoxes(ctx: *zp.Context, projection: Mat4, frame: f32) void {
simple_renderer.renderer().begin();
defer simple_renderer.renderer().end();
// update stencil buffers
if (outlined) {
ctx.graphics.setStencilOption(.{
.test_func = .always,
.test_ref = 1,
.action_dppass = .replace,
});
}
for (cube_positions) |pos, i| {
var model = Mat4.fromRotation(
20 * @intToFloat(f32, i) + frame,
Vec3.new(1, 0.3, 0.5),
).translate(pos);
simple_renderer.renderer().renderMesh(
cube,
model,
projection,
camera,
cube_material,
null,
) catch unreachable;
}
// outline cubes
// draw scaled up cubes, using single color
if (outlined) {
ctx.graphics.setStencilOption(.{
.test_func = .not_equal,
.test_ref = 1,
});
for (cube_positions) |pos, i| {
var model = Mat4.fromRotation(
20 * @intToFloat(f32, i) + frame,
Vec3.new(1, 0.3, 0.5),
).translate(pos);
simple_renderer.renderer().renderMesh(
cube,
model.mult(Mat4.fromScale(Vec3.set(1.01))),
projection,
camera,
color_material,
null,
) catch unreachable;
}
}
}
fn quit(ctx: *zp.Context) void {
_ = ctx;
std.log.info("game quit", .{});
}
pub fn main() anyerror!void {
try zp.run(.{
.initFn = init,
.loopFn = loop,
.quitFn = quit,
});
} | examples/cubes.zig |
test "Version" {
var hello = "hello".*;
var version = TestSchema.Version{
.major = 1,
.minor = 2,
.patch = 0,
.pre = &hello,
.build = &([_]u8{}),
};
var in_buffer = [_]u8{0} ** 256;
var stream = std.io.fixedBufferStream(&in_buffer);
var writer = std.io.countingWriter(stream.writer());
var out_stream = std.io.fixedBufferStream(&in_buffer);
var reader = std.io.countingReader(out_stream.reader());
try version.encode(writer.writer());
var other = try TestSchema.Version.decode(std.heap.page_allocator, reader.reader());
std.testing.expectEqual(other.major, 1);
std.testing.expectEqual(other.minor, 2);
std.testing.expectEqual(other.patch, 0);
std.testing.expect(std.mem.eql(u8, version.pre, other.pre));
}
test "JavascriptPackageRequest" {
var req = TestSchema.JavascriptPackageRequest{};
var _h = "Hello".*;
req.name = &_h;
var in_buffer = [_]u8{0} ** 256;
var stream = std.io.fixedBufferStream(&in_buffer);
var writer = std.io.countingWriter(stream.writer());
var out_stream = std.io.fixedBufferStream(&in_buffer);
var reader = std.io.countingReader(out_stream.reader());
try req.encode(writer.writer());
var other = try TestSchema.JavascriptPackageRequest.decode(std.heap.page_allocator, reader.reader());
std.testing.expect(std.mem.eql(u8, req.name.?, other.name.?));
}
test "Manifest" {
var req = std.mem.zeroes(TestSchema.JavascriptPackageManifest);
var names = try std.heap.page_allocator.alloc([]u8, 1);
req.name = names;
var _name = "hi".*;
req.name[0] = &_name;
var in_buffer = [_]u8{0} ** 256;
var stream = std.io.fixedBufferStream(&in_buffer);
var writer = std.io.countingWriter(stream.writer());
var out_stream = std.io.fixedBufferStream(&in_buffer);
var reader = std.io.countingReader(out_stream.reader());
try req.encode(writer.writer());
var other = try TestSchema.JavascriptPackageManifest.decode(std.heap.page_allocator, reader.reader());
std.testing.expect(std.mem.eql(u8, req.name[0], other.name[0]));
} | examples/lockfile_test.zig |
const std = @import("std");
const testing = std.testing;
const debug = std.debug.print;
const KvStore = @import("kvstore.zig").KvStore;
const utils = @import("utils.zig");
pub const BracketPair = struct {
start: usize,
end: usize,
depth: usize, // If nested, how deep
resolved: bool = false,
};
/// Parsers buffer for {{something}}-entries, and provides an array of BracketPair-entries to use for further processing. It doesn't
/// discriminate based on if the contents are valid variable names or functions etc, this must be handled later.
pub fn findAllVariables(comptime BufferSize: usize, comptime MaxNumVariables: usize, buffer: *std.BoundedArray(u8, BufferSize)) !std.BoundedArray(BracketPair, MaxNumVariables) {
var opens: std.BoundedArray(usize, MaxNumVariables) = std.BoundedArray(usize, MaxNumVariables).init(0) catch unreachable;
var pairs: std.BoundedArray(BracketPair, MaxNumVariables) = std.BoundedArray(BracketPair, MaxNumVariables).init(0) catch unreachable;
var skip_next = false;
for (buffer.slice()[0 .. buffer.slice().len - 1]) |char, i| {
if (skip_next) {
skip_next = false;
continue;
}
switch (char) {
'{' => {
if (buffer.slice()[i + 1] == '{') {
try opens.append(i);
skip_next = true;
}
},
'}' => {
if (buffer.slice()[i + 1] == '}') {
skip_next = true;
// pop, if any.
if (opens.slice().len > 0) {
try pairs.append(BracketPair{ .start = opens.pop(), .end = i + 1, .depth = opens.slice().len });
} else {
// TODO: convert to line and col
// TODO: Print surrounding slice?
// Att! Not an error. E.g. for json-payloads...
debug("WARNING: Found close-brackets at idx={d} with none open\n", .{i});
}
}
},
else => {},
}
}
if (opens.slice().len > 0) {
for (opens.slice()) |idx| debug("WARNING: Brackets remaining open: idx={d}\n", .{idx});
// TODO: Print surrounding slice?
}
return pairs;
}
/// Buffer must be large enough to contain the expanded variant.
/// TODO: Test performance with fixed sizes. Possibly redesign the outer to utilize a common scrap buffer
pub fn expandVariables(comptime BufferSize: usize, comptime MaxNumVariables: usize, buffer: *std.BoundedArray(u8, BufferSize), pairs: *std.BoundedArray(BracketPair, MaxNumVariables), variables: *KvStore) error{BufferTooSmall, Overflow}!void {
// Algorithm:
// * prereq: pairs are sorted by depth, desc
// * pick entry from pairs until empty
// * extract key
// * get value for key
// * calculate length-diff as "end_delta"
// * substitute slice in buffer
// * loop through all remaining pairs and any .start or .end that's > prev.end + end_delta with + end_delta
var end_delta: i64 = 0;
for (pairs.slice()) |*pair| {
if (pair.resolved) continue;
var pair_len = pair.end - pair.start + 1;
var key = buffer.slice()[pair.start + 2 .. pair.end - 1];
// check if key is a variable (not function)
if (!(std.mem.indexOf(u8, key, "(") != null and std.mem.indexOf(u8, key, ")") != null)) {
if (variables.get(key)) |value| {
var value_len = value.len;
end_delta = @intCast(i32, value_len) - (@intCast(i32, key.len) + 4); // 4 == {{}}
buffer.replaceRange(pair.start, pair_len, value) catch {
return error.BufferTooSmall;
};
pair.resolved = true;
for (pairs.slice()[0..]) |*pair2| {
if (pair2.resolved) continue;// Since we no longer go exclusively by depth (we run this function multiple times with different sets), we have to check from start and filter out resolved instead
if (pair2.start > @intCast(i64, pair.start + 1)) pair2.start = try utils.addUnsignedSigned(u64, i64, pair2.start, end_delta);
if (pair2.end > @intCast(i64, pair.start + 1)) pair2.end = try utils.addUnsignedSigned(u64, i64, pair2.end, end_delta);
}
} else {
// TODO: Make verbose-dependent?
// debug("WARNING: Could not resolve variable: '{s}'\n", .{key});
// result = error.NoSuchVariableFound;
}
}
}
}
const FunctionEntryFuncPtr = fn (std.mem.Allocator, []const u8, *std.BoundedArray(u8, 1024)) anyerror!void;
const FunctionEntry = struct {
name: []const u8,
function: FunctionEntryFuncPtr,
fn create(name: []const u8, function: FunctionEntryFuncPtr) FunctionEntry {
return .{ .name = name, .function = function };
}
};
fn funcMyfunc(_: std.mem.Allocator, value: []const u8, out_buf: *std.BoundedArray(u8, 1024)) !void {
try out_buf.insertSlice(0, value);
}
fn funcBase64enc(_: std.mem.Allocator, value: []const u8, out_buf: *std.BoundedArray(u8, 1024)) !void {
var buffer: [1024]u8 = undefined;
try out_buf.insertSlice(0, std.base64.standard.Encoder.encode(&buffer, value));
}
test "funcBase64enc" {
var input = "abcde12345:";
var expected = "YWJjZGUxMjM0NTo=";
var output = try std.BoundedArray(u8, 1024).init(0);
try funcBase64enc(std.testing.allocator, input, &output);
try testing.expectEqualStrings(expected, output.constSlice());
}
fn funcEnv(allocator: std.mem.Allocator, value: []const u8, out_buf: *std.BoundedArray(u8, 1024)) !void {
const env_value = try std.process.getEnvVarOwned(allocator, value);
defer allocator.free(env_value);
try out_buf.insertSlice(0, utils.sliceUpTo(u8, env_value, 0, 1024));
if(env_value.len > out_buf.capacity()) {
return error.Overflow;
}
}
test "funcEnv" {
var input = "PATH";
var output = try std.BoundedArray(u8, 1024).init(0);
funcEnv(std.testing.allocator, input, &output) catch |e| switch(e) {
error.Overflow => {},
else => return e
};
try testing.expect(output.slice().len > 0);
}
// fn funcBase64dec() !void {
// }
// fn funcUrlencode() !void {
// }
pub fn getFunction(functions: []const FunctionEntry, name: []const u8) error{NoSuchFunction}!FunctionEntryFuncPtr {
// Att: Inefficient. If data set increases, improve (PERFORMANCE)
for (functions) |*entry| {
if (std.mem.eql(u8, entry.name, name)) {
return entry.function;
}
}
return error.NoSuchFunction;
}
test "getFunction" {
const TestFunctions = struct {
fn funcWoop(_: std.mem.Allocator, value: []const u8, out_buf: *std.BoundedArray(u8, 1024)) !void {
_ = value;
try out_buf.insertSlice(0, "woop");
}
fn funcBlank(_: std.mem.Allocator, value: []const u8, out_buf: *std.BoundedArray(u8, 1024)) !void {
_ = value;
try out_buf.insertSlice(0, "");
}
};
const functions = [_]FunctionEntry{
FunctionEntry.create("woopout", TestFunctions.funcWoop),
FunctionEntry.create("blank", TestFunctions.funcBlank),
};
const functions_slice = functions[0..];
var buf = std.BoundedArray(u8, 1024).init(0) catch unreachable;
try (try getFunction(functions_slice, "woopout"))(std.testing.allocator, "doesntmatter", &buf);
try testing.expectEqualStrings("woop", buf.slice());
try buf.resize(0);
try (try getFunction(functions_slice, "blank"))(std.testing.allocator, "doesntmatter", &buf);
try testing.expectEqualStrings("", buf.slice());
try buf.resize(0);
try testing.expectError(error.NoSuchFunction, getFunction(functions_slice, "nosuchfunction"));
try (try getFunction(global_functions[0..], "myfunc"))(std.testing.allocator, "mydata", &buf);
try testing.expectEqualStrings("mydata", buf.slice());
}
const global_functions = [_]FunctionEntry{
FunctionEntry.create("myfunc", funcMyfunc),
FunctionEntry.create("base64enc", funcBase64enc),
FunctionEntry.create("env", funcEnv),
};
/// Convenience-function looking up functions from the global default-list of functions
pub fn getGlobalFunction(name: []const u8) !FunctionEntryFuncPtr {
return getFunction(global_functions[0..], name);
}
///
pub fn expandFunctions(comptime BufferSize: usize, comptime MaxNumVariables: usize, buffer: *std.BoundedArray(u8, BufferSize), pairs: *std.BoundedArray(BracketPair, MaxNumVariables)) !void {
var arena = std.heap.ArenaAllocator.init(std.heap.page_allocator);
defer arena.deinit();
const allocator = arena.allocator();
var end_delta: i64 = 0;
for (pairs.slice()) |*pair, i| {
if(pair.resolved) continue;
var pair_len = pair.end - pair.start + 1;
var key = buffer.slice()[pair.start + 2 .. pair.end - 1];
// check if key is a function, otherwise ignore
if (std.mem.indexOf(u8, key, "(") != null and std.mem.indexOf(u8, key, ")") != null) {
// Parse function name, extract "parameter", lookup and call proper function
var func_key = key[0..std.mem.indexOf(u8, key, "(").?];
var func_arg = key[std.mem.indexOf(u8, key, "(").? + 1 .. std.mem.indexOf(u8, key, ")").?];
var function = try getGlobalFunction(func_key);
var func_buf = utils.initBoundedArray(u8, 1024);
try function(allocator, func_arg, &func_buf);
buffer.replaceRange(pair.start, pair_len, func_buf.slice()) catch {
// .Overflow
return error.BufferTooSmall;
};
pair.resolved = true;
end_delta = @intCast(i32, func_buf.slice().len) - (@intCast(i32, key.len) + 4); // 4 == {{}}
for (pairs.slice()[i + 1 ..]) |*pair2| {
if (pair2.start > @intCast(i64, pair.start + 1)) pair2.start = try utils.addUnsignedSigned(u64, i64, pair2.start, end_delta);
if (pair2.end > @intCast(i64, pair.start + 1)) pair2.end = try utils.addUnsignedSigned(u64, i64, pair2.end, end_delta);
}
}
}
}
test "bracketparsing - variables and functions" {
const MAX_VARIABLES = 64;
var str = try std.BoundedArray(u8, 1024).fromSlice(
\\begin
\\{{var1}}
\\{{var2}}
\\{{myfunc({{var3}})}}
\\end
);
var variables = KvStore{};
try variables.add("var1", "value1");
try variables.add("var2", "v2");
try variables.add("var3", "woop");
// var functions = [_]Pair{};
var pairs = try findAllVariables(str.buffer.len, MAX_VARIABLES, &str);
try expandVariables(str.buffer.len, MAX_VARIABLES, &str, &pairs, &variables);
try testing.expect(std.mem.indexOf(u8, str.slice(), "{{var1}}") == null);
try testing.expect(std.mem.indexOf(u8, str.slice(), "{{var2}}") == null);
try testing.expect(std.mem.indexOf(u8, str.slice(), "{{var3}}") == null);
try testing.expect(std.mem.indexOf(u8, str.slice(), "{{myfunc") != null);
try testing.expect(std.mem.indexOf(u8, str.slice(), "value1") != null);
try testing.expect(std.mem.indexOf(u8, str.slice(), "v2") != null);
try testing.expect(std.mem.indexOf(u8, str.slice(), "woop") != null);
try expandFunctions(str.buffer.len, MAX_VARIABLES, &str, &pairs);
try testing.expect(std.mem.indexOf(u8, str.slice(), "{{myfunc") == null);
} | src/parser_variables.zig |
const std = @import("std");
const Allocator = std.mem.Allocator;
const nvg = @import("nanovg");
const gui = @import("../gui.zig");
const Point = @import("../geometry.zig").Point;
const Rect = @import("../geometry.zig").Rect;
const RadioButton = @This();
widget: gui.Widget,
allocator: Allocator,
text: []const u8,
hovered: bool = false,
focused: bool = false,
pressed: bool = false,
checked: bool = false,
onClickFn: ?fn (*RadioButton) void = null,
pub fn init(allocator: Allocator, rect: Rect(f32), text: [:0]const u8) !*RadioButton {
var self = try allocator.create(RadioButton);
self.* = RadioButton{
.widget = gui.Widget.init(allocator, rect),
.allocator = allocator,
.text = text,
};
self.widget.focus_policy.mouse = true;
self.widget.focus_policy.keyboard = true;
self.widget.drawFn = draw;
self.widget.onMouseDownFn = onMouseDown;
self.widget.onMouseUpFn = onMouseUp;
self.widget.onKeyDownFn = onKeyDown;
self.widget.onFocusFn = onFocus;
self.widget.onEnterFn = onEnter;
self.widget.onLeaveFn = onLeave;
return self;
}
pub fn deinit(self: *RadioButton) void {
self.widget.deinit();
self.allocator.destroy(self);
}
fn click(self: *RadioButton) void {
if (!self.widget.isEnabled()) return;
if (self.onClickFn) |clickFn| {
clickFn(self);
}
}
pub fn onMouseDown(widget: *gui.Widget, mouse_event: *const gui.MouseEvent) void {
if (!widget.isEnabled()) return;
const self = @fieldParentPtr(RadioButton, "widget", widget);
const mouse_position = Point(f32).make(mouse_event.x, mouse_event.y);
self.hovered = widget.getRect().contains(mouse_position);
if (mouse_event.button == .left) {
if (self.hovered) {
self.pressed = true;
}
}
}
fn onMouseUp(widget: *gui.Widget, mouse_event: *const gui.MouseEvent) void {
if (!widget.isEnabled()) return;
const self = @fieldParentPtr(RadioButton, "widget", widget);
const mouse_position = Point(f32).make(mouse_event.x, mouse_event.y);
self.hovered = widget.getRect().contains(mouse_position);
if (mouse_event.button == .left) {
self.pressed = false;
if (self.hovered) {
self.click();
}
}
}
fn onKeyDown(widget: *gui.Widget, key_event: *gui.KeyEvent) void {
widget.onKeyDown(key_event);
const self = @fieldParentPtr(RadioButton, "widget", widget);
if (key_event.key == .Space) {
self.click();
}
}
fn onFocus(widget: *gui.Widget, focus_event : *gui.FocusEvent) void {
const self = @fieldParentPtr(RadioButton, "widget", widget);
self.focused = focus_event.source == .keyboard;
}
fn onEnter(widget: *gui.Widget) void {
const self = @fieldParentPtr(RadioButton, "widget", widget);
self.hovered = true;
}
fn onLeave(widget: *gui.Widget) void {
const self = @fieldParentPtr(RadioButton, "widget", widget);
self.hovered = false;
}
pub fn draw(widget: *gui.Widget, vg: nvg) void {
const self = @fieldParentPtr(RadioButton, "widget", widget);
const rect = widget.relative_rect;
// const enabled = widget.isEnabled(); // TODO
if (!widget.isFocused()) self.focused = false;
const cx = rect.x + 6;
const cy = rect.y + 0.5 * rect.h;
vg.beginPath();
vg.arc(cx, cy, 5.5, -0.25 * std.math.pi, -1.25 * std.math.pi, .ccw);
vg.strokeColor(gui.theme_colors.shadow);
vg.stroke();
vg.beginPath();
vg.arc(cx, cy, 5.5, 0.75 * std.math.pi, -0.25 * std.math.pi, .ccw);
vg.strokeColor(gui.theme_colors.light);
vg.stroke();
vg.beginPath();
vg.ellipse(cx, cy, 4.5, 4.5);
vg.fillColor(nvg.rgbf(1, 1, 1));
vg.fill();
vg.strokeColor(gui.theme_colors.border);
vg.stroke();
if (self.checked or self.hovered) {
vg.beginPath();
vg.ellipse(cx, cy, 2, 2);
vg.fillColor(if (self.checked) nvg.rgb(0, 0, 0) else gui.theme_colors.shadow);
vg.fill();
}
vg.fontFace("guifont");
vg.fontSize(12);
vg.textAlign(nvg.TextAlign{ .vertical = .middle });
vg.fillColor(nvg.rgb(0, 0, 0));
_ = vg.text(rect.x + 16, cy, self.text);
if (self.focused) {
var bounds: [4]f32 = undefined;
_ = vg.textBounds(rect.x + 16, cy, self.text, &bounds);
vg.beginPath();
vg.rect(@round(bounds[0]) - 1.5, @round(bounds[1]) - 1.5, @round(bounds[2] - bounds[0]) + 3, @round(bounds[3] - bounds[1]) + 3);
vg.strokePaint(vg.imagePattern(0, 0, 2, 2, 0, gui.grid_image, 1));
vg.stroke();
}
} | src/gui/widgets/RadioButton.zig |
const std = @import("std");
const math = std.math;
const bog = @import("../bog.zig");
const Value = bog.Value;
const Vm = bog.Vm;
/// Euler's number (e)
pub const e = math.e;
/// Archimedes' constant (π)
pub const pi = math.pi;
/// Circle constant (τ)
pub const tau = math.tau;
/// log2(e)
pub const log2e = math.log2e;
/// log10(e)
pub const log10e = math.log10e;
/// ln(2)
pub const ln2 = math.ln2;
/// ln(10)
pub const ln10 = math.ln10;
/// 2/sqrt(π)
pub const two_sqrtpi = math.two_sqrtpi;
/// sqrt(2)
pub const sqrt2 = math.sqrt2;
/// 1/sqrt(2)
pub const sqrt1_2 = math.sqrt1_2;
pub fn ln(vm: *Vm, val: Value) !*Value {
return switch (val) {
// TODO fix zig std
// .int => |i| Value{
// .int = std.math.ln(i),
// },
.num => |n| {
const res = try vm.gc.alloc();
res.* = Value{ .num = std.math.ln(n) };
return res;
},
else => vm.typeError(.num, val),
};
}
pub fn sqrt(vm: *Vm, val: Value) !*Value {
return switch (val) {
.int => |i| {
_ = i;
const res = try vm.gc.alloc();
res.* = Value{ .int = std.math.sqrt(@intCast(u64, i)) };
return res;
},
.num => |n| {
const res = try vm.gc.alloc();
res.* = Value{ .num = std.math.sqrt(n) };
return res;
},
else => vm.typeError(.num, val),
};
}
pub fn isNan(val: f64) bool {
return math.isNan(val);
}
pub fn isSignalNan(val: f64) bool {
return math.isSignalNan(val);
}
pub fn fabs(val: f64) f64 {
return math.fabs(val);
}
pub fn ceil(val: f64) f64 {
return math.ceil(val);
}
pub fn floor(val: f64) f64 {
return math.floor(val);
}
pub fn trunc(val: f64) f64 {
return math.trunc(val);
}
pub fn round(val: f64) f64 {
return math.round(val);
}
pub fn isFinite(val: f64) bool {
return math.isFinite(val);
}
pub fn isInf(val: f64) bool {
return math.isInf(val);
}
pub fn isPositiveInf(val: f64) bool {
return math.isPositiveInf(val);
}
pub fn isNegativeInf(val: f64) bool {
return math.isNegativeInf(val);
}
pub fn isNormal(val: f64) bool {
return math.isNormal(val);
}
pub fn signbit(val: f64) bool {
return math.signbit(val);
}
pub fn scalbn(val: f64, n: i32) f64 {
return math.scalbn(val, n);
}
pub fn cbrt(val: f64) f64 {
return math.cbrt(val);
}
pub fn acos(val: f64) f64 {
return math.acos(val);
}
pub fn asin(val: f64) f64 {
return math.asin(val);
}
pub fn atan(val: f64) f64 {
return math.atan(val);
}
pub fn atan2(y: f64, x: f64) f64 {
return math.atan2(f64, y, x);
}
pub fn hypot(x: f64, y: f64) f64 {
return math.hypot(f64, x, y);
}
pub fn exp(val: f64) f64 {
return math.exp(val);
}
pub fn exp2(val: f64) f64 {
return math.exp2(val);
}
pub fn expm1(val: f64) f64 {
return math.expm1(val);
}
pub fn ilogb(val: f64) i32 {
return math.ilogb(val);
}
pub fn log(base: f64, val: f64) f64 {
return math.log(f64, base, val);
}
pub fn log2(val: f64) f64 {
return math.log2(val);
}
pub fn log10(val: f64) f64 {
return math.log10(val);
}
pub fn log1p(val: f64) f64 {
return math.log1p(val);
}
pub fn fma(x: f64, y: f64, z: f64) f64 {
return math.fma(f64, x, y, z);
}
pub fn asinh(val: f64) f64 {
return math.asinh(val);
}
pub fn acosh(val: f64) f64 {
return math.acosh(val);
}
pub fn atanh(val: f64) f64 {
return math.atanh(val);
}
pub fn sinh(val: f64) f64 {
return math.sinh(val);
}
pub fn cosh(val: f64) f64 {
return math.cosh(val);
}
pub fn tanh(val: f64) f64 {
return math.tanh(val);
}
pub fn cos(val: f64) f64 {
return math.cos(val);
}
pub fn sin(val: f64) f64 {
return math.sin(val);
}
pub fn tan(val: f64) f64 {
return math.tan(val);
} | src/std/math.zig |
const std = @import("std");
const assert = std.debug.assert;
const Compilation = @import("Compilation.zig");
const Type = @import("Type.zig");
const Value = @This();
tag: Tag = .unavailable,
data: union {
none: void,
int: u64,
float: f64,
array: []Value,
bytes: []u8,
} = .{ .none = {} },
const Tag = enum {
unavailable,
/// int is used to store integer, boolean and pointer values
int,
float,
array,
bytes,
};
pub fn zero(v: Value) Value {
return switch (v.tag) {
.int => int(0),
.float => float(0),
else => unreachable,
};
}
pub fn one(v: Value) Value {
return switch (v.tag) {
.int => int(1),
.float => float(1),
else => unreachable,
};
}
pub fn int(v: anytype) Value {
if (@TypeOf(v) == comptime_int or @typeInfo(@TypeOf(v)).Int.signedness == .unsigned)
return .{ .tag = .int, .data = .{ .int = v } }
else
return .{ .tag = .int, .data = .{ .int = @bitCast(u64, @as(i64, v)) } };
}
pub fn float(v: anytype) Value {
return .{ .tag = .float, .data = .{ .float = v } };
}
pub fn bytes(v: anytype) Value {
return .{ .tag = .bytes, .data = .{ .bytes = v } };
}
pub fn signExtend(v: Value, old_ty: Type, comp: *Compilation) i64 {
const size = old_ty.sizeof(comp).?;
return switch (size) {
4 => v.getInt(i32),
8 => v.getInt(i64),
else => unreachable,
};
}
/// Converts the stored value from a float to an integer.
/// `.unavailable` value remains unchanged.
pub fn floatToInt(v: *Value, old_ty: Type, new_ty: Type, comp: *Compilation) void {
assert(old_ty.isFloat());
if (v.tag == .unavailable) return;
if (new_ty.isUnsignedInt(comp) and v.data.float < 0) {
v.* = int(0);
return;
}
const size = old_ty.sizeof(comp).?;
v.* = int(switch (size) {
4 => @floatToInt(i32, v.getFloat(f32)),
8 => @floatToInt(i64, v.getFloat(f64)),
else => unreachable,
});
}
/// Converts the stored value from an integer to a float.
/// `.unavailable` value remains unchanged.
pub fn intToFloat(v: *Value, old_ty: Type, new_ty: Type, comp: *Compilation) void {
assert(old_ty.isInt());
if (v.tag == .unavailable) return;
if (!new_ty.isReal() or new_ty.sizeof(comp).? > 8) {
v.tag = .unavailable;
} else if (old_ty.isUnsignedInt(comp)) {
v.* = float(@intToFloat(f64, v.data.int));
} else {
v.* = float(@intToFloat(f64, @bitCast(i64, v.data.int)));
}
}
/// Truncates or extends bits based on type.
/// old_ty is only used for size.
pub fn intCast(v: *Value, old_ty: Type, new_ty: Type, comp: *Compilation) void {
// assert(old_ty.isInt() and new_ty.isInt());
if (v.tag == .unavailable) return;
if (new_ty.is(.bool)) return v.toBool();
if (!old_ty.isUnsignedInt(comp)) {
const size = new_ty.sizeof(comp).?;
switch (size) {
1 => v.* = int(@bitCast(u8, v.getInt(i8))),
2 => v.* = int(@bitCast(u16, v.getInt(i16))),
4 => v.* = int(@bitCast(u32, v.getInt(i32))),
8 => return,
else => unreachable,
}
}
}
/// Truncates data.int to one bit
pub fn toBool(v: *Value) void {
if (v.tag == .unavailable) return;
const res = v.getBool();
v.* = int(@boolToInt(res));
}
pub fn isZero(v: Value) bool {
return switch (v.tag) {
.unavailable => false,
.int => v.data.int == 0,
.float => v.data.float == 0,
.array => unreachable,
.bytes => unreachable,
};
}
pub fn getBool(v: Value) bool {
return switch (v.tag) {
.unavailable => unreachable,
.int => v.data.int != 0,
.float => v.data.float != 0,
.array => unreachable,
.bytes => unreachable,
};
}
pub fn getInt(v: Value, comptime T: type) T {
if (T == u64) return v.data.int;
return if (@typeInfo(T).Int.signedness == .unsigned)
@truncate(T, v.data.int)
else
@truncate(T, @bitCast(i64, v.data.int));
}
pub fn getFloat(v: Value, comptime T: type) T {
if (T == f64) return v.data.float;
return @floatCast(T, v.data.float);
}
const bin_overflow = struct {
inline fn addInt(comptime T: type, out: *Value, a: Value, b: Value) bool {
const a_val = a.getInt(T);
const b_val = b.getInt(T);
var c: T = undefined;
const overflow = @addWithOverflow(T, a_val, b_val, &c);
out.* = int(c);
return overflow;
}
inline fn addFloat(comptime T: type, aa: Value, bb: Value) Value {
const a_val = aa.getFloat(T);
const b_val = bb.getFloat(T);
return float(a_val + b_val);
}
inline fn subInt(comptime T: type, out: *Value, a: Value, b: Value) bool {
const a_val = a.getInt(T);
const b_val = b.getInt(T);
var c: T = undefined;
const overflow = @subWithOverflow(T, a_val, b_val, &c);
out.* = int(c);
return overflow;
}
inline fn subFloat(comptime T: type, aa: Value, bb: Value) Value {
const a_val = aa.getFloat(T);
const b_val = bb.getFloat(T);
return float(a_val - b_val);
}
inline fn mulInt(comptime T: type, out: *Value, a: Value, b: Value) bool {
const a_val = a.getInt(T);
const b_val = b.getInt(T);
var c: T = undefined;
const overflow = @mulWithOverflow(T, a_val, b_val, &c);
out.* = int(c);
return overflow;
}
inline fn mulFloat(comptime T: type, aa: Value, bb: Value) Value {
const a_val = aa.getFloat(T);
const b_val = bb.getFloat(T);
return float(a_val * b_val);
}
const FT = fn (*Value, Value, Value, Type, *Compilation) bool;
fn getOp(intFunc: anytype, floatFunc: anytype) FT {
return struct {
fn op(res: *Value, a: Value, b: Value, ty: Type, comp: *Compilation) bool {
const size = ty.sizeof(comp).?;
if (@TypeOf(floatFunc) != @TypeOf(null) and ty.isFloat()) {
res.* = switch (size) {
4 => floatFunc(f32, a, b),
8 => floatFunc(f64, a, b),
else => unreachable,
};
return false;
}
if (ty.isUnsignedInt(comp)) switch (size) {
1 => unreachable, // promoted to int
2 => unreachable, // promoted to int
4 => return intFunc(u32, res, a, b),
8 => return intFunc(u64, res, a, b),
else => unreachable,
} else switch (size) {
1 => unreachable, // promoted to int
2 => unreachable, // promoted to int
4 => return intFunc(i32, res, a, b),
8 => return intFunc(i64, res, a, b),
else => unreachable,
}
}
}.op;
}
};
pub const add = bin_overflow.getOp(bin_overflow.addInt, bin_overflow.addFloat);
pub const sub = bin_overflow.getOp(bin_overflow.subInt, bin_overflow.subFloat);
pub const mul = bin_overflow.getOp(bin_overflow.mulInt, bin_overflow.mulFloat);
const bin_ops = struct {
inline fn divInt(comptime T: type, aa: Value, bb: Value) Value {
const a_val = aa.getInt(T);
const b_val = bb.getInt(T);
return int(@divTrunc(a_val, b_val));
}
inline fn divFloat(comptime T: type, aa: Value, bb: Value) Value {
const a_val = aa.getFloat(T);
const b_val = bb.getFloat(T);
return float(a_val / b_val);
}
inline fn remInt(comptime T: type, a: Value, b: Value) Value {
const a_val = a.getInt(T);
const b_val = b.getInt(T);
if (@typeInfo(T).Int.signedness == .signed) {
if (a_val == std.math.minInt(T) and b_val == -1) {
return Value{ .tag = .unavailable, .data = .{ .none = {} } };
} else {
if (b_val > 0) return int(@rem(a_val, b_val));
return int(a_val - @divTrunc(a_val, b_val) * b_val);
}
} else {
return int(a_val % b_val);
}
}
inline fn orInt(comptime T: type, a: Value, b: Value) Value {
const a_val = a.getInt(T);
const b_val = b.getInt(T);
return int(a_val | b_val);
}
inline fn xorInt(comptime T: type, a: Value, b: Value) Value {
const a_val = a.getInt(T);
const b_val = b.getInt(T);
return int(a_val ^ b_val);
}
inline fn andInt(comptime T: type, a: Value, b: Value) Value {
const a_val = a.getInt(T);
const b_val = b.getInt(T);
return int(a_val & b_val);
}
inline fn shl(comptime T: type, a: Value, b: Value) Value {
const ShiftT = std.math.Log2Int(T);
const info = @typeInfo(T).Int;
const UT = std.meta.Int(.unsigned, info.bits);
const b_val = b.getInt(T);
if (b_val > std.math.maxInt(ShiftT)) {
return if (info.signedness == .unsigned)
int(@as(UT, std.math.maxInt(UT)))
else
int(@as(T, std.math.minInt(T)));
}
const amt = @truncate(ShiftT, @bitCast(UT, b_val));
const a_val = a.getInt(T);
return int(a_val << amt);
}
inline fn shr(comptime T: type, a: Value, b: Value) Value {
const ShiftT = std.math.Log2Int(T);
const UT = std.meta.Int(.unsigned, @typeInfo(T).Int.bits);
const b_val = b.getInt(T);
if (b_val > std.math.maxInt(ShiftT)) return Value.int(0);
const amt = @truncate(ShiftT, @intCast(UT, b_val));
const a_val = a.getInt(T);
return int(a_val >> amt);
}
const FT = fn (Value, Value, Type, *Compilation) Value;
fn getOp(intFunc: anytype, floatFunc: anytype) FT {
return struct {
fn op(a: Value, b: Value, ty: Type, comp: *Compilation) Value {
const size = ty.sizeof(comp).?;
if (@TypeOf(floatFunc) != @TypeOf(null) and ty.isFloat()) {
switch (size) {
4 => return floatFunc(f32, a, b),
8 => return floatFunc(f64, a, b),
else => unreachable,
}
}
if (ty.isUnsignedInt(comp)) switch (size) {
1 => unreachable, // promoted to int
2 => unreachable, // promoted to int
4 => return intFunc(u32, a, b),
8 => return intFunc(u64, a, b),
else => unreachable,
} else switch (size) {
1 => unreachable, // promoted to int
2 => unreachable, // promoted to int
4 => return intFunc(i32, a, b),
8 => return intFunc(i64, a, b),
else => unreachable,
}
}
}.op;
}
};
/// caller guarantees rhs != 0
pub const div = bin_ops.getOp(bin_ops.divInt, bin_ops.divFloat);
/// caller guarantees rhs != 0
/// caller guarantees lhs != std.math.minInt(T) OR rhs != -1
pub const rem = bin_ops.getOp(bin_ops.remInt, null);
pub const bitOr = bin_ops.getOp(bin_ops.orInt, null);
pub const bitXor = bin_ops.getOp(bin_ops.xorInt, null);
pub const bitAnd = bin_ops.getOp(bin_ops.andInt, null);
pub const shl = bin_ops.getOp(bin_ops.shl, null);
pub const shr = bin_ops.getOp(bin_ops.shr, null);
pub fn bitNot(v: Value, ty: Type, comp: *Compilation) Value {
const size = ty.sizeof(comp).?;
var out: Value = undefined;
if (ty.isUnsignedInt(comp)) switch (size) {
1 => unreachable, // promoted to int
2 => unreachable, // promoted to int
4 => out = int(~v.getInt(u32)),
8 => out = int(~v.getInt(u64)),
else => unreachable,
} else switch (size) {
1 => unreachable, // promoted to int
2 => unreachable, // promoted to int
4 => out = int(~v.getInt(i32)),
8 => out = int(~v.getInt(i64)),
else => unreachable,
}
return out;
}
pub fn compare(a: Value, op: std.math.CompareOperator, b: Value, ty: Type, comp: *Compilation) bool {
assert(a.tag == b.tag);
const S = struct {
inline fn doICompare(comptime T: type, aa: Value, opp: std.math.CompareOperator, bb: Value) bool {
const a_val = aa.getInt(T);
const b_val = bb.getInt(T);
return std.math.compare(a_val, opp, b_val);
}
inline fn doFCompare(comptime T: type, aa: Value, opp: std.math.CompareOperator, bb: Value) bool {
const a_val = aa.getFloat(T);
const b_val = bb.getFloat(T);
return std.math.compare(a_val, opp, b_val);
}
};
const size = ty.sizeof(comp).?;
switch (a.tag) {
.unavailable => return true,
.int => if (ty.isUnsignedInt(comp)) switch (size) {
1 => unreachable, // promoted to int
2 => unreachable, // promoted to int
4 => return S.doICompare(u32, a, op, b),
8 => return S.doICompare(u64, a, op, b),
else => unreachable,
} else switch (size) {
1 => unreachable, // promoted to int
2 => unreachable, // promoted to int
4 => return S.doICompare(i32, a, op, b),
8 => return S.doICompare(i64, a, op, b),
else => unreachable,
},
.float => switch (size) {
4 => return S.doFCompare(f32, a, op, b),
8 => return S.doFCompare(f64, a, op, b),
else => unreachable,
},
else => @panic("TODO"),
}
return false;
}
pub fn hash(v: Value) u64 {
switch (v.tag) {
.unavailable => unreachable,
.int => return std.hash.Wyhash.hash(0, std.mem.asBytes(&v.data.int)),
else => @panic("TODO"),
}
}
pub fn dump(v: Value, ty: Type, comp: *Compilation, w: anytype) !void {
switch (v.tag) {
.unavailable => try w.writeAll("unavailable"),
.int => if (ty.isUnsignedInt(comp))
try w.print("{d}", .{v.data.int})
else {
try w.print("{d}", .{v.signExtend(ty, comp)});
},
// std.fmt does @as instead of @floatCast
.float => try w.print("{d}", .{@floatCast(f64, v.data.float)}),
else => try w.print("({s})", .{@tagName(v.tag)}),
}
} | src/Value.zig |
const builtin = @import("builtin");
const is_test = builtin.is_test;
comptime {
const linkage = if (is_test) builtin.GlobalLinkage.Internal else builtin.GlobalLinkage.Weak;
const strong_linkage = if (is_test) builtin.GlobalLinkage.Internal else builtin.GlobalLinkage.Strong;
@export("__lesf2", @import("compiler_rt/comparesf2.zig").__lesf2, linkage);
@export("__ledf2", @import("compiler_rt/comparedf2.zig").__ledf2, linkage);
@export("__letf2", @import("compiler_rt/comparetf2.zig").__letf2, linkage);
@export("__gesf2", @import("compiler_rt/comparesf2.zig").__gesf2, linkage);
@export("__gedf2", @import("compiler_rt/comparedf2.zig").__gedf2, linkage);
@export("__getf2", @import("compiler_rt/comparetf2.zig").__getf2, linkage);
if (!is_test) {
// only create these aliases when not testing
@export("__cmpsf2", @import("compiler_rt/comparesf2.zig").__lesf2, linkage);
@export("__cmpdf2", @import("compiler_rt/comparedf2.zig").__ledf2, linkage);
@export("__cmptf2", @import("compiler_rt/comparetf2.zig").__letf2, linkage);
@export("__eqsf2", @import("compiler_rt/comparesf2.zig").__eqsf2, linkage);
@export("__eqdf2", @import("compiler_rt/comparedf2.zig").__eqdf2, linkage);
@export("__eqtf2", @import("compiler_rt/comparetf2.zig").__letf2, linkage);
@export("__ltsf2", @import("compiler_rt/comparesf2.zig").__ltsf2, linkage);
@export("__ltdf2", @import("compiler_rt/comparedf2.zig").__ltdf2, linkage);
@export("__lttf2", @import("compiler_rt/comparetf2.zig").__letf2, linkage);
@export("__nesf2", @import("compiler_rt/comparesf2.zig").__nesf2, linkage);
@export("__nedf2", @import("compiler_rt/comparedf2.zig").__nedf2, linkage);
@export("__netf2", @import("compiler_rt/comparetf2.zig").__letf2, linkage);
@export("__gtsf2", @import("compiler_rt/comparesf2.zig").__gtsf2, linkage);
@export("__gtdf2", @import("compiler_rt/comparedf2.zig").__gtdf2, linkage);
@export("__gttf2", @import("compiler_rt/comparetf2.zig").__getf2, linkage);
@export("__gnu_h2f_ieee", @import("compiler_rt/extendXfYf2.zig").__extendhfsf2, linkage);
@export("__gnu_f2h_ieee", @import("compiler_rt/truncXfYf2.zig").__truncsfhf2, linkage);
}
@export("__unordsf2", @import("compiler_rt/comparesf2.zig").__unordsf2, linkage);
@export("__unorddf2", @import("compiler_rt/comparedf2.zig").__unorddf2, linkage);
@export("__unordtf2", @import("compiler_rt/comparetf2.zig").__unordtf2, linkage);
@export("__addsf3", @import("compiler_rt/addXf3.zig").__addsf3, linkage);
@export("__adddf3", @import("compiler_rt/addXf3.zig").__adddf3, linkage);
@export("__addtf3", @import("compiler_rt/addXf3.zig").__addtf3, linkage);
@export("__subsf3", @import("compiler_rt/addXf3.zig").__subsf3, linkage);
@export("__subdf3", @import("compiler_rt/addXf3.zig").__subdf3, linkage);
@export("__subtf3", @import("compiler_rt/addXf3.zig").__subtf3, linkage);
@export("__mulsf3", @import("compiler_rt/mulXf3.zig").__mulsf3, linkage);
@export("__muldf3", @import("compiler_rt/mulXf3.zig").__muldf3, linkage);
@export("__multf3", @import("compiler_rt/mulXf3.zig").__multf3, linkage);
@export("__divsf3", @import("compiler_rt/divsf3.zig").__divsf3, linkage);
@export("__divdf3", @import("compiler_rt/divdf3.zig").__divdf3, linkage);
@export("__floattitf", @import("compiler_rt/floattitf.zig").__floattitf, linkage);
@export("__floattidf", @import("compiler_rt/floattidf.zig").__floattidf, linkage);
@export("__floattisf", @import("compiler_rt/floattisf.zig").__floattisf, linkage);
@export("__floatunditf", @import("compiler_rt/floatunditf.zig").__floatunditf, linkage);
@export("__floatunsitf", @import("compiler_rt/floatunsitf.zig").__floatunsitf, linkage);
@export("__floatuntitf", @import("compiler_rt/floatuntitf.zig").__floatuntitf, linkage);
@export("__floatuntidf", @import("compiler_rt/floatuntidf.zig").__floatuntidf, linkage);
@export("__floatuntisf", @import("compiler_rt/floatuntisf.zig").__floatuntisf, linkage);
@export("__extenddftf2", @import("compiler_rt/extendXfYf2.zig").__extenddftf2, linkage);
@export("__extendsftf2", @import("compiler_rt/extendXfYf2.zig").__extendsftf2, linkage);
@export("__extendhfsf2", @import("compiler_rt/extendXfYf2.zig").__extendhfsf2, linkage);
@export("__truncsfhf2", @import("compiler_rt/truncXfYf2.zig").__truncsfhf2, linkage);
@export("__truncdfhf2", @import("compiler_rt/truncXfYf2.zig").__truncdfhf2, linkage);
@export("__trunctfdf2", @import("compiler_rt/truncXfYf2.zig").__trunctfdf2, linkage);
@export("__trunctfsf2", @import("compiler_rt/truncXfYf2.zig").__trunctfsf2, linkage);
@export("__fixunssfsi", @import("compiler_rt/fixunssfsi.zig").__fixunssfsi, linkage);
@export("__fixunssfdi", @import("compiler_rt/fixunssfdi.zig").__fixunssfdi, linkage);
@export("__fixunssfti", @import("compiler_rt/fixunssfti.zig").__fixunssfti, linkage);
@export("__fixunsdfsi", @import("compiler_rt/fixunsdfsi.zig").__fixunsdfsi, linkage);
@export("__fixunsdfdi", @import("compiler_rt/fixunsdfdi.zig").__fixunsdfdi, linkage);
@export("__fixunsdfti", @import("compiler_rt/fixunsdfti.zig").__fixunsdfti, linkage);
@export("__fixunstfsi", @import("compiler_rt/fixunstfsi.zig").__fixunstfsi, linkage);
@export("__fixunstfdi", @import("compiler_rt/fixunstfdi.zig").__fixunstfdi, linkage);
@export("__fixunstfti", @import("compiler_rt/fixunstfti.zig").__fixunstfti, linkage);
@export("__fixdfdi", @import("compiler_rt/fixdfdi.zig").__fixdfdi, linkage);
@export("__fixdfsi", @import("compiler_rt/fixdfsi.zig").__fixdfsi, linkage);
@export("__fixdfti", @import("compiler_rt/fixdfti.zig").__fixdfti, linkage);
@export("__fixsfdi", @import("compiler_rt/fixsfdi.zig").__fixsfdi, linkage);
@export("__fixsfsi", @import("compiler_rt/fixsfsi.zig").__fixsfsi, linkage);
@export("__fixsfti", @import("compiler_rt/fixsfti.zig").__fixsfti, linkage);
@export("__fixtfdi", @import("compiler_rt/fixtfdi.zig").__fixtfdi, linkage);
@export("__fixtfsi", @import("compiler_rt/fixtfsi.zig").__fixtfsi, linkage);
@export("__fixtfti", @import("compiler_rt/fixtfti.zig").__fixtfti, linkage);
@export("__udivmoddi4", @import("compiler_rt/udivmoddi4.zig").__udivmoddi4, linkage);
@export("__popcountdi2", @import("compiler_rt/popcountdi2.zig").__popcountdi2, linkage);
@export("__divsi3", __divsi3, linkage);
@export("__udivsi3", __udivsi3, linkage);
@export("__udivdi3", __udivdi3, linkage);
@export("__umoddi3", __umoddi3, linkage);
@export("__divmodsi4", __divmodsi4, linkage);
@export("__udivmodsi4", __udivmodsi4, linkage);
@export("__negsf2", @import("compiler_rt/negXf2.zig").__negsf2, linkage);
@export("__negdf2", @import("compiler_rt/negXf2.zig").__negdf2, linkage);
if (is_arm_arch and !is_arm_64) {
@export("__aeabi_uldivmod", __aeabi_uldivmod, linkage);
@export("__aeabi_idiv", __divsi3, linkage);
@export("__aeabi_idivmod", __divmodsi4, linkage);
@export("__aeabi_uidiv", __udivsi3, linkage);
@export("__aeabi_uidivmod", __aeabi_uidivmod, linkage);
@export("__aeabi_memcpy", __aeabi_memcpy, linkage);
@export("__aeabi_memcpy4", __aeabi_memcpy, linkage);
@export("__aeabi_memcpy8", __aeabi_memcpy, linkage);
@export("__aeabi_memmove", __aeabi_memmove, linkage);
@export("__aeabi_memmove4", __aeabi_memmove, linkage);
@export("__aeabi_memmove8", __aeabi_memmove, linkage);
@export("__aeabi_memset", __aeabi_memset, linkage);
@export("__aeabi_memset4", __aeabi_memset, linkage);
@export("__aeabi_memset8", __aeabi_memset, linkage);
@export("__aeabi_memclr", __aeabi_memclr, linkage);
@export("__aeabi_memclr4", __aeabi_memclr, linkage);
@export("__aeabi_memclr8", __aeabi_memclr, linkage);
@export("__aeabi_memcmp", __aeabi_memcmp, linkage);
@export("__aeabi_memcmp4", __aeabi_memcmp, linkage);
@export("__aeabi_memcmp8", __aeabi_memcmp, linkage);
@export("__aeabi_fneg", @import("compiler_rt/negXf2.zig").__negsf2, linkage);
@export("__aeabi_dneg", @import("compiler_rt/negXf2.zig").__negdf2, linkage);
@export("__aeabi_fmul", @import("compiler_rt/mulXf3.zig").__mulsf3, linkage);
@export("__aeabi_dmul", @import("compiler_rt/mulXf3.zig").__muldf3, linkage);
@export("__aeabi_d2h", @import("compiler_rt/truncXfYf2.zig").__truncdfhf2, linkage);
@export("__aeabi_f2ulz", @import("compiler_rt/fixunssfdi.zig").__fixunssfdi, linkage);
@export("__aeabi_d2ulz", @import("compiler_rt/fixunsdfdi.zig").__fixunsdfdi, linkage);
@export("__aeabi_f2lz", @import("compiler_rt/fixsfdi.zig").__fixsfdi, linkage);
@export("__aeabi_d2lz", @import("compiler_rt/fixdfdi.zig").__fixdfdi, linkage);
@export("__aeabi_d2uiz", @import("compiler_rt/fixunsdfsi.zig").__fixunsdfsi, linkage);
@export("__aeabi_h2f", @import("compiler_rt/extendXfYf2.zig").__extendhfsf2, linkage);
@export("__aeabi_f2h", @import("compiler_rt/truncXfYf2.zig").__truncsfhf2, linkage);
@export("__aeabi_fadd", @import("compiler_rt/addXf3.zig").__addsf3, linkage);
@export("__aeabi_dadd", @import("compiler_rt/addXf3.zig").__adddf3, linkage);
@export("__aeabi_fsub", @import("compiler_rt/addXf3.zig").__subsf3, linkage);
@export("__aeabi_dsub", @import("compiler_rt/addXf3.zig").__subdf3, linkage);
@export("__aeabi_f2uiz", @import("compiler_rt/fixunssfsi.zig").__fixunssfsi, linkage);
@export("__aeabi_f2iz", @import("compiler_rt/fixsfsi.zig").__fixsfsi, linkage);
@export("__aeabi_d2iz", @import("compiler_rt/fixdfsi.zig").__fixdfsi, linkage);
@export("__aeabi_fdiv", @import("compiler_rt/divsf3.zig").__divsf3, linkage);
@export("__aeabi_ddiv", @import("compiler_rt/divdf3.zig").__divdf3, linkage);
@export("__aeabi_fcmpeq", @import("compiler_rt/arm/aeabi_fcmp.zig").__aeabi_fcmpeq, linkage);
@export("__aeabi_fcmplt", @import("compiler_rt/arm/aeabi_fcmp.zig").__aeabi_fcmplt, linkage);
@export("__aeabi_fcmple", @import("compiler_rt/arm/aeabi_fcmp.zig").__aeabi_fcmple, linkage);
@export("__aeabi_fcmpge", @import("compiler_rt/arm/aeabi_fcmp.zig").__aeabi_fcmpge, linkage);
@export("__aeabi_fcmpgt", @import("compiler_rt/arm/aeabi_fcmp.zig").__aeabi_fcmpgt, linkage);
@export("__aeabi_fcmpun", @import("compiler_rt/comparesf2.zig").__unordsf2, linkage);
@export("__aeabi_dcmpeq", @import("compiler_rt/arm/aeabi_dcmp.zig").__aeabi_dcmpeq, linkage);
@export("__aeabi_dcmplt", @import("compiler_rt/arm/aeabi_dcmp.zig").__aeabi_dcmplt, linkage);
@export("__aeabi_dcmple", @import("compiler_rt/arm/aeabi_dcmp.zig").__aeabi_dcmple, linkage);
@export("__aeabi_dcmpge", @import("compiler_rt/arm/aeabi_dcmp.zig").__aeabi_dcmpge, linkage);
@export("__aeabi_dcmpgt", @import("compiler_rt/arm/aeabi_dcmp.zig").__aeabi_dcmpgt, linkage);
@export("__aeabi_dcmpun", @import("compiler_rt/comparedf2.zig").__unorddf2, linkage);
}
if (builtin.os == builtin.Os.windows) {
switch (builtin.arch) {
builtin.Arch.i386 => {
if (!builtin.link_libc) {
@export("_chkstk", _chkstk, strong_linkage);
@export("__chkstk_ms", __chkstk_ms, linkage);
}
@export("_aulldiv", @import("compiler_rt/aulldiv.zig")._aulldiv, strong_linkage);
@export("_aullrem", @import("compiler_rt/aullrem.zig")._aullrem, strong_linkage);
},
builtin.Arch.x86_64 => {
if (!builtin.link_libc) {
@export("__chkstk", __chkstk, strong_linkage);
@export("___chkstk_ms", ___chkstk_ms, linkage);
}
// The "ti" functions must use @Vector(2, u64) parameter types to adhere to the ABI
// that LLVM expects compiler-rt to have.
@export("__divti3", @import("compiler_rt/divti3.zig").__divti3_windows_x86_64, linkage);
@export("__modti3", @import("compiler_rt/modti3.zig").__modti3_windows_x86_64, linkage);
@export("__multi3", @import("compiler_rt/multi3.zig").__multi3_windows_x86_64, linkage);
@export("__udivti3", @import("compiler_rt/udivti3.zig").__udivti3_windows_x86_64, linkage);
@export("__udivmodti4", @import("compiler_rt/udivmodti4.zig").__udivmodti4_windows_x86_64, linkage);
@export("__umodti3", @import("compiler_rt/umodti3.zig").__umodti3_windows_x86_64, linkage);
},
else => {},
}
} else {
@export("__divti3", @import("compiler_rt/divti3.zig").__divti3, linkage);
@export("__modti3", @import("compiler_rt/modti3.zig").__modti3, linkage);
@export("__multi3", @import("compiler_rt/multi3.zig").__multi3, linkage);
@export("__udivti3", @import("compiler_rt/udivti3.zig").__udivti3, linkage);
@export("__udivmodti4", @import("compiler_rt/udivmodti4.zig").__udivmodti4, linkage);
@export("__umodti3", @import("compiler_rt/umodti3.zig").__umodti3, linkage);
}
@export("__muloti4", @import("compiler_rt/muloti4.zig").__muloti4, linkage);
@export("__mulodi4", @import("compiler_rt/mulodi4.zig").__mulodi4, linkage);
}
const std = @import("std");
const assert = std.debug.assert;
const testing = std.testing;
const __udivmoddi4 = @import("compiler_rt/udivmoddi4.zig").__udivmoddi4;
// Avoid dragging in the runtime safety mechanisms into this .o file,
// unless we're trying to test this file.
pub fn panic(msg: []const u8, error_return_trace: ?*builtin.StackTrace) noreturn {
@setCold(true);
if (is_test) {
std.debug.panic("{}", msg);
} else {
unreachable;
}
}
extern fn __udivdi3(a: u64, b: u64) u64 {
@setRuntimeSafety(is_test);
return __udivmoddi4(a, b, null);
}
extern fn __umoddi3(a: u64, b: u64) u64 {
@setRuntimeSafety(is_test);
var r: u64 = undefined;
_ = __udivmoddi4(a, b, &r);
return r;
}
const AeabiUlDivModResult = extern struct {
quot: u64,
rem: u64,
};
extern fn __aeabi_uldivmod(numerator: u64, denominator: u64) AeabiUlDivModResult {
@setRuntimeSafety(is_test);
var result: AeabiUlDivModResult = undefined;
result.quot = __udivmoddi4(numerator, denominator, &result.rem);
return result;
}
const is_arm_64 = switch (builtin.arch) {
builtin.Arch.aarch64,
builtin.Arch.aarch64_be,
=> true,
else => false,
};
const is_arm_arch = switch (builtin.arch) {
builtin.Arch.arm,
builtin.Arch.armeb,
builtin.Arch.aarch64,
builtin.Arch.aarch64_be,
builtin.Arch.thumb,
builtin.Arch.thumbeb,
=> true,
else => false,
};
const is_arm_32 = is_arm_arch and !is_arm_64;
const use_thumb_1 = usesThumb1(builtin.arch);
fn usesThumb1(arch: builtin.Arch) bool {
return switch (arch) {
.arm => switch (arch.arm) {
.v6m => true,
else => false,
},
.armeb => switch (arch.armeb) {
.v6m => true,
else => false,
},
.thumb => switch (arch.thumb) {
.v5,
.v5te,
.v4t,
.v6,
.v6m,
.v6k,
=> true,
else => false,
},
.thumbeb => switch (arch.thumbeb) {
.v5,
.v5te,
.v4t,
.v6,
.v6m,
.v6k,
=> true,
else => false,
},
else => false,
};
}
test "usesThumb1" {
testing.expect(usesThumb1(builtin.Arch{ .arm = .v6m }));
testing.expect(!usesThumb1(builtin.Arch{ .arm = .v5 }));
//etc.
testing.expect(usesThumb1(builtin.Arch{ .armeb = .v6m }));
testing.expect(!usesThumb1(builtin.Arch{ .armeb = .v5 }));
//etc.
testing.expect(usesThumb1(builtin.Arch{ .thumb = .v5 }));
testing.expect(usesThumb1(builtin.Arch{ .thumb = .v5te }));
testing.expect(usesThumb1(builtin.Arch{ .thumb = .v4t }));
testing.expect(usesThumb1(builtin.Arch{ .thumb = .v6 }));
testing.expect(usesThumb1(builtin.Arch{ .thumb = .v6k }));
testing.expect(usesThumb1(builtin.Arch{ .thumb = .v6m }));
testing.expect(!usesThumb1(builtin.Arch{ .thumb = .v6t2 }));
//etc.
testing.expect(usesThumb1(builtin.Arch{ .thumbeb = .v5 }));
testing.expect(usesThumb1(builtin.Arch{ .thumbeb = .v5te }));
testing.expect(usesThumb1(builtin.Arch{ .thumbeb = .v4t }));
testing.expect(usesThumb1(builtin.Arch{ .thumbeb = .v6 }));
testing.expect(usesThumb1(builtin.Arch{ .thumbeb = .v6k }));
testing.expect(usesThumb1(builtin.Arch{ .thumbeb = .v6m }));
testing.expect(!usesThumb1(builtin.Arch{ .thumbeb = .v6t2 }));
//etc.
testing.expect(!usesThumb1(builtin.Arch{ .aarch64 = .v8 }));
testing.expect(!usesThumb1(builtin.Arch{ .aarch64_be = .v8 }));
testing.expect(!usesThumb1(builtin.Arch.x86_64));
testing.expect(!usesThumb1(builtin.Arch.riscv32));
//etc.
}
nakedcc fn __aeabi_uidivmod() void {
@setRuntimeSafety(false);
asm volatile (
\\ push { lr }
\\ sub sp, sp, #4
\\ mov r2, sp
\\ bl __udivmodsi4
\\ ldr r1, [sp]
\\ add sp, sp, #4
\\ pop { pc }
:
:
: "r2", "r1"
);
}
nakedcc fn __aeabi_memcpy() noreturn {
@setRuntimeSafety(false);
if (use_thumb_1) {
asm volatile (
\\ push {r7, lr}
\\ bl memcpy
\\ pop {r7, pc}
);
} else {
asm volatile (
\\ b memcpy
);
}
unreachable;
}
nakedcc fn __aeabi_memmove() noreturn {
@setRuntimeSafety(false);
if (use_thumb_1) {
asm volatile (
\\ push {r7, lr}
\\ bl memmove
\\ pop {r7, pc}
);
} else {
asm volatile (
\\ b memmove
);
}
unreachable;
}
nakedcc fn __aeabi_memset() noreturn {
@setRuntimeSafety(false);
if (use_thumb_1) {
asm volatile (
\\ mov r3, r1
\\ mov r1, r2
\\ mov r2, r3
\\ push {r7, lr}
\\ b memset
\\ pop {r7, pc}
);
} else {
asm volatile (
\\ mov r3, r1
\\ mov r1, r2
\\ mov r2, r3
\\ b memset
);
}
unreachable;
}
nakedcc fn __aeabi_memclr() noreturn {
@setRuntimeSafety(false);
if (use_thumb_1) {
asm volatile (
\\ mov r2, r1
\\ movs r1, #0
\\ push {r7, lr}
\\ bl memset
\\ pop {r7, pc}
);
} else {
asm volatile (
\\ mov r2, r1
\\ movs r1, #0
\\ b memset
);
}
unreachable;
}
nakedcc fn __aeabi_memcmp() noreturn {
@setRuntimeSafety(false);
if (use_thumb_1) {
asm volatile (
\\ push {r7, lr}
\\ bl memcmp
\\ pop {r7, pc}
);
} else {
asm volatile (
\\ b memcmp
);
}
unreachable;
}
// _chkstk (_alloca) routine - probe stack between %esp and (%esp-%eax) in 4k increments,
// then decrement %esp by %eax. Preserves all registers except %esp and flags.
// This routine is windows specific
// http://msdn.microsoft.com/en-us/library/ms648426.aspx
nakedcc fn _chkstk() align(4) void {
@setRuntimeSafety(false);
asm volatile (
\\ push %%ecx
\\ push %%eax
\\ cmp $0x1000,%%eax
\\ lea 12(%%esp),%%ecx
\\ jb 1f
\\ 2:
\\ sub $0x1000,%%ecx
\\ test %%ecx,(%%ecx)
\\ sub $0x1000,%%eax
\\ cmp $0x1000,%%eax
\\ ja 2b
\\ 1:
\\ sub %%eax,%%ecx
\\ test %%ecx,(%%ecx)
\\ pop %%eax
\\ pop %%ecx
\\ ret
);
}
nakedcc fn __chkstk() align(4) void {
@setRuntimeSafety(false);
asm volatile (
\\ push %%rcx
\\ push %%rax
\\ cmp $0x1000,%%rax
\\ lea 24(%%rsp),%%rcx
\\ jb 1f
\\2:
\\ sub $0x1000,%%rcx
\\ test %%rcx,(%%rcx)
\\ sub $0x1000,%%rax
\\ cmp $0x1000,%%rax
\\ ja 2b
\\1:
\\ sub %%rax,%%rcx
\\ test %%rcx,(%%rcx)
\\ pop %%rax
\\ pop %%rcx
\\ ret
);
}
// _chkstk routine
// This routine is windows specific
// http://msdn.microsoft.com/en-us/library/ms648426.aspx
nakedcc fn __chkstk_ms() align(4) void {
@setRuntimeSafety(false);
asm volatile (
\\ push %%ecx
\\ push %%eax
\\ cmp $0x1000,%%eax
\\ lea 12(%%esp),%%ecx
\\ jb 1f
\\ 2:
\\ sub $0x1000,%%ecx
\\ test %%ecx,(%%ecx)
\\ sub $0x1000,%%eax
\\ cmp $0x1000,%%eax
\\ ja 2b
\\ 1:
\\ sub %%eax,%%ecx
\\ test %%ecx,(%%ecx)
\\ pop %%eax
\\ pop %%ecx
\\ ret
);
}
nakedcc fn ___chkstk_ms() align(4) void {
@setRuntimeSafety(false);
asm volatile (
\\ push %%rcx
\\ push %%rax
\\ cmp $0x1000,%%rax
\\ lea 24(%%rsp),%%rcx
\\ jb 1f
\\2:
\\ sub $0x1000,%%rcx
\\ test %%rcx,(%%rcx)
\\ sub $0x1000,%%rax
\\ cmp $0x1000,%%rax
\\ ja 2b
\\1:
\\ sub %%rax,%%rcx
\\ test %%rcx,(%%rcx)
\\ pop %%rax
\\ pop %%rcx
\\ ret
);
}
extern fn __divmodsi4(a: i32, b: i32, rem: *i32) i32 {
@setRuntimeSafety(is_test);
const d = __divsi3(a, b);
rem.* = a -% (d * b);
return d;
}
extern fn __udivmodsi4(a: u32, b: u32, rem: *u32) u32 {
@setRuntimeSafety(is_test);
const d = __udivsi3(a, b);
rem.* = @bitCast(u32, @bitCast(i32, a) -% (@bitCast(i32, d) * @bitCast(i32, b)));
return d;
}
extern fn __divsi3(n: i32, d: i32) i32 {
@setRuntimeSafety(is_test);
// Set aside the sign of the quotient.
const sign = @bitCast(u32, (n ^ d) >> 31);
// Take absolute value of a and b via abs(x) = (x^(x >> 31)) - (x >> 31).
const abs_n = (n ^ (n >> 31)) -% (n >> 31);
const abs_d = (d ^ (d >> 31)) -% (d >> 31);
// abs(a) / abs(b)
const res = @bitCast(u32, abs_n) / @bitCast(u32, abs_d);
// Apply sign of quotient to result and return.
return @bitCast(i32, (res ^ sign) -% sign);
}
extern fn __udivsi3(n: u32, d: u32) u32 {
@setRuntimeSafety(is_test);
const n_uword_bits: c_uint = u32.bit_count;
// special cases
if (d == 0) return 0; // ?!
if (n == 0) return 0;
var sr = @bitCast(c_uint, c_int(@clz(d)) - c_int(@clz(n)));
// 0 <= sr <= n_uword_bits - 1 or sr large
if (sr > n_uword_bits - 1) {
// d > r
return 0;
}
if (sr == n_uword_bits - 1) {
// d == 1
return n;
}
sr += 1;
// 1 <= sr <= n_uword_bits - 1
// Not a special case
var q: u32 = n << @intCast(u5, n_uword_bits - sr);
var r: u32 = n >> @intCast(u5, sr);
var carry: u32 = 0;
while (sr > 0) : (sr -= 1) {
// r:q = ((r:q) << 1) | carry
r = (r << 1) | (q >> @intCast(u5, n_uword_bits - 1));
q = (q << 1) | carry;
// carry = 0;
// if (r.all >= d.all)
// {
// r.all -= d.all;
// carry = 1;
// }
const s = @intCast(i32, d -% r -% 1) >> @intCast(u5, n_uword_bits - 1);
carry = @intCast(u32, s & 1);
r -= d & @bitCast(u32, s);
}
q = (q << 1) | carry;
return q;
}
test "test_umoddi3" {
test_one_umoddi3(0, 1, 0);
test_one_umoddi3(2, 1, 0);
test_one_umoddi3(0x8000000000000000, 1, 0x0);
test_one_umoddi3(0x8000000000000000, 2, 0x0);
test_one_umoddi3(0xFFFFFFFFFFFFFFFF, 2, 0x1);
}
fn test_one_umoddi3(a: u64, b: u64, expected_r: u64) void {
const r = __umoddi3(a, b);
testing.expect(r == expected_r);
}
test "test_udivsi3" {
const cases = [][3]u32{
[]u32{
0x00000000,
0x00000001,
0x00000000,
},
[]u32{
0x00000000,
0x00000002,
0x00000000,
},
[]u32{
0x00000000,
0x00000003,
0x00000000,
},
[]u32{
0x00000000,
0x00000010,
0x00000000,
},
[]u32{
0x00000000,
0x078644FA,
0x00000000,
},
[]u32{
0x00000000,
0x0747AE14,
0x00000000,
},
[]u32{
0x00000000,
0x7FFFFFFF,
0x00000000,
},
[]u32{
0x00000000,
0x80000000,
0x00000000,
},
[]u32{
0x00000000,
0xFFFFFFFD,
0x00000000,
},
[]u32{
0x00000000,
0xFFFFFFFE,
0x00000000,
},
[]u32{
0x00000000,
0xFFFFFFFF,
0x00000000,
},
[]u32{
0x00000001,
0x00000001,
0x00000001,
},
[]u32{
0x00000001,
0x00000002,
0x00000000,
},
[]u32{
0x00000001,
0x00000003,
0x00000000,
},
[]u32{
0x00000001,
0x00000010,
0x00000000,
},
[]u32{
0x00000001,
0x078644FA,
0x00000000,
},
[]u32{
0x00000001,
0x0747AE14,
0x00000000,
},
[]u32{
0x00000001,
0x7FFFFFFF,
0x00000000,
},
[]u32{
0x00000001,
0x80000000,
0x00000000,
},
[]u32{
0x00000001,
0xFFFFFFFD,
0x00000000,
},
[]u32{
0x00000001,
0xFFFFFFFE,
0x00000000,
},
[]u32{
0x00000001,
0xFFFFFFFF,
0x00000000,
},
[]u32{
0x00000002,
0x00000001,
0x00000002,
},
[]u32{
0x00000002,
0x00000002,
0x00000001,
},
[]u32{
0x00000002,
0x00000003,
0x00000000,
},
[]u32{
0x00000002,
0x00000010,
0x00000000,
},
[]u32{
0x00000002,
0x078644FA,
0x00000000,
},
[]u32{
0x00000002,
0x0747AE14,
0x00000000,
},
[]u32{
0x00000002,
0x7FFFFFFF,
0x00000000,
},
[]u32{
0x00000002,
0x80000000,
0x00000000,
},
[]u32{
0x00000002,
0xFFFFFFFD,
0x00000000,
},
[]u32{
0x00000002,
0xFFFFFFFE,
0x00000000,
},
[]u32{
0x00000002,
0xFFFFFFFF,
0x00000000,
},
[]u32{
0x00000003,
0x00000001,
0x00000003,
},
[]u32{
0x00000003,
0x00000002,
0x00000001,
},
[]u32{
0x00000003,
0x00000003,
0x00000001,
},
[]u32{
0x00000003,
0x00000010,
0x00000000,
},
[]u32{
0x00000003,
0x078644FA,
0x00000000,
},
[]u32{
0x00000003,
0x0747AE14,
0x00000000,
},
[]u32{
0x00000003,
0x7FFFFFFF,
0x00000000,
},
[]u32{
0x00000003,
0x80000000,
0x00000000,
},
[]u32{
0x00000003,
0xFFFFFFFD,
0x00000000,
},
[]u32{
0x00000003,
0xFFFFFFFE,
0x00000000,
},
[]u32{
0x00000003,
0xFFFFFFFF,
0x00000000,
},
[]u32{
0x00000010,
0x00000001,
0x00000010,
},
[]u32{
0x00000010,
0x00000002,
0x00000008,
},
[]u32{
0x00000010,
0x00000003,
0x00000005,
},
[]u32{
0x00000010,
0x00000010,
0x00000001,
},
[]u32{
0x00000010,
0x078644FA,
0x00000000,
},
[]u32{
0x00000010,
0x0747AE14,
0x00000000,
},
[]u32{
0x00000010,
0x7FFFFFFF,
0x00000000,
},
[]u32{
0x00000010,
0x80000000,
0x00000000,
},
[]u32{
0x00000010,
0xFFFFFFFD,
0x00000000,
},
[]u32{
0x00000010,
0xFFFFFFFE,
0x00000000,
},
[]u32{
0x00000010,
0xFFFFFFFF,
0x00000000,
},
[]u32{
0x078644FA,
0x00000001,
0x078644FA,
},
[]u32{
0x078644FA,
0x00000002,
0x03C3227D,
},
[]u32{
0x078644FA,
0x00000003,
0x028216FE,
},
[]u32{
0x078644FA,
0x00000010,
0x0078644F,
},
[]u32{
0x078644FA,
0x078644FA,
0x00000001,
},
[]u32{
0x078644FA,
0x0747AE14,
0x00000001,
},
[]u32{
0x078644FA,
0x7FFFFFFF,
0x00000000,
},
[]u32{
0x078644FA,
0x80000000,
0x00000000,
},
[]u32{
0x078644FA,
0xFFFFFFFD,
0x00000000,
},
[]u32{
0x078644FA,
0xFFFFFFFE,
0x00000000,
},
[]u32{
0x078644FA,
0xFFFFFFFF,
0x00000000,
},
[]u32{
0x0747AE14,
0x00000001,
0x0747AE14,
},
[]u32{
0x0747AE14,
0x00000002,
0x03A3D70A,
},
[]u32{
0x0747AE14,
0x00000003,
0x026D3A06,
},
[]u32{
0x0747AE14,
0x00000010,
0x00747AE1,
},
[]u32{
0x0747AE14,
0x078644FA,
0x00000000,
},
[]u32{
0x0747AE14,
0x0747AE14,
0x00000001,
},
[]u32{
0x0747AE14,
0x7FFFFFFF,
0x00000000,
},
[]u32{
0x0747AE14,
0x80000000,
0x00000000,
},
[]u32{
0x0747AE14,
0xFFFFFFFD,
0x00000000,
},
[]u32{
0x0747AE14,
0xFFFFFFFE,
0x00000000,
},
[]u32{
0x0747AE14,
0xFFFFFFFF,
0x00000000,
},
[]u32{
0x7FFFFFFF,
0x00000001,
0x7FFFFFFF,
},
[]u32{
0x7FFFFFFF,
0x00000002,
0x3FFFFFFF,
},
[]u32{
0x7FFFFFFF,
0x00000003,
0x2AAAAAAA,
},
[]u32{
0x7FFFFFFF,
0x00000010,
0x07FFFFFF,
},
[]u32{
0x7FFFFFFF,
0x078644FA,
0x00000011,
},
[]u32{
0x7FFFFFFF,
0x0747AE14,
0x00000011,
},
[]u32{
0x7FFFFFFF,
0x7FFFFFFF,
0x00000001,
},
[]u32{
0x7FFFFFFF,
0x80000000,
0x00000000,
},
[]u32{
0x7FFFFFFF,
0xFFFFFFFD,
0x00000000,
},
[]u32{
0x7FFFFFFF,
0xFFFFFFFE,
0x00000000,
},
[]u32{
0x7FFFFFFF,
0xFFFFFFFF,
0x00000000,
},
[]u32{
0x80000000,
0x00000001,
0x80000000,
},
[]u32{
0x80000000,
0x00000002,
0x40000000,
},
[]u32{
0x80000000,
0x00000003,
0x2AAAAAAA,
},
[]u32{
0x80000000,
0x00000010,
0x08000000,
},
[]u32{
0x80000000,
0x078644FA,
0x00000011,
},
[]u32{
0x80000000,
0x0747AE14,
0x00000011,
},
[]u32{
0x80000000,
0x7FFFFFFF,
0x00000001,
},
[]u32{
0x80000000,
0x80000000,
0x00000001,
},
[]u32{
0x80000000,
0xFFFFFFFD,
0x00000000,
},
[]u32{
0x80000000,
0xFFFFFFFE,
0x00000000,
},
[]u32{
0x80000000,
0xFFFFFFFF,
0x00000000,
},
[]u32{
0xFFFFFFFD,
0x00000001,
0xFFFFFFFD,
},
[]u32{
0xFFFFFFFD,
0x00000002,
0x7FFFFFFE,
},
[]u32{
0xFFFFFFFD,
0x00000003,
0x55555554,
},
[]u32{
0xFFFFFFFD,
0x00000010,
0x0FFFFFFF,
},
[]u32{
0xFFFFFFFD,
0x078644FA,
0x00000022,
},
[]u32{
0xFFFFFFFD,
0x0747AE14,
0x00000023,
},
[]u32{
0xFFFFFFFD,
0x7FFFFFFF,
0x00000001,
},
[]u32{
0xFFFFFFFD,
0x80000000,
0x00000001,
},
[]u32{
0xFFFFFFFD,
0xFFFFFFFD,
0x00000001,
},
[]u32{
0xFFFFFFFD,
0xFFFFFFFE,
0x00000000,
},
[]u32{
0xFFFFFFFD,
0xFFFFFFFF,
0x00000000,
},
[]u32{
0xFFFFFFFE,
0x00000001,
0xFFFFFFFE,
},
[]u32{
0xFFFFFFFE,
0x00000002,
0x7FFFFFFF,
},
[]u32{
0xFFFFFFFE,
0x00000003,
0x55555554,
},
[]u32{
0xFFFFFFFE,
0x00000010,
0x0FFFFFFF,
},
[]u32{
0xFFFFFFFE,
0x078644FA,
0x00000022,
},
[]u32{
0xFFFFFFFE,
0x0747AE14,
0x00000023,
},
[]u32{
0xFFFFFFFE,
0x7FFFFFFF,
0x00000002,
},
[]u32{
0xFFFFFFFE,
0x80000000,
0x00000001,
},
[]u32{
0xFFFFFFFE,
0xFFFFFFFD,
0x00000001,
},
[]u32{
0xFFFFFFFE,
0xFFFFFFFE,
0x00000001,
},
[]u32{
0xFFFFFFFE,
0xFFFFFFFF,
0x00000000,
},
[]u32{
0xFFFFFFFF,
0x00000001,
0xFFFFFFFF,
},
[]u32{
0xFFFFFFFF,
0x00000002,
0x7FFFFFFF,
},
[]u32{
0xFFFFFFFF,
0x00000003,
0x55555555,
},
[]u32{
0xFFFFFFFF,
0x00000010,
0x0FFFFFFF,
},
[]u32{
0xFFFFFFFF,
0x078644FA,
0x00000022,
},
[]u32{
0xFFFFFFFF,
0x0747AE14,
0x00000023,
},
[]u32{
0xFFFFFFFF,
0x7FFFFFFF,
0x00000002,
},
[]u32{
0xFFFFFFFF,
0x80000000,
0x00000001,
},
[]u32{
0xFFFFFFFF,
0xFFFFFFFD,
0x00000001,
},
[]u32{
0xFFFFFFFF,
0xFFFFFFFE,
0x00000001,
},
[]u32{
0xFFFFFFFF,
0xFFFFFFFF,
0x00000001,
},
};
for (cases) |case| {
test_one_udivsi3(case[0], case[1], case[2]);
}
}
fn test_one_udivsi3(a: u32, b: u32, expected_q: u32) void {
const q: u32 = __udivsi3(a, b);
testing.expect(q == expected_q);
}
test "test_divsi3" {
const cases = [][3]i32{
[]i32{ 0, 1, 0},
[]i32{ 0, -1, 0},
[]i32{ 2, 1, 2},
[]i32{ 2, -1, -2},
[]i32{-2, 1, -2},
[]i32{-2, -1, 2},
[]i32{@bitCast(i32, u32(0x80000000)), 1, @bitCast(i32, u32(0x80000000))},
[]i32{@bitCast(i32, u32(0x80000000)), -1, @bitCast(i32, u32(0x80000000))},
[]i32{@bitCast(i32, u32(0x80000000)), -2, 0x40000000},
[]i32{@bitCast(i32, u32(0x80000000)), 2, @bitCast(i32, u32(0xC0000000))},
};
for (cases) |case| {
test_one_divsi3(case[0], case[1], case[2]);
}
}
fn test_one_divsi3(a: i32, b: i32, expected_q: i32) void {
const q: i32 = __divsi3(a, b);
testing.expect(q == expected_q);
}
test "test_divmodsi4" {
const cases = [][4]i32{
[]i32{ 0, 1, 0, 0},
[]i32{ 0, -1, 0, 0},
[]i32{ 2, 1, 2, 0},
[]i32{ 2, -1, -2, 0},
[]i32{-2, 1, -2, 0},
[]i32{-2, -1, 2, 0},
[]i32{ 7, 5, 1, 2},
[]i32{-7, 5, -1, -2},
[]i32{19, 5, 3, 4},
[]i32{19, -5, -3, 4},
[]i32{@bitCast(i32, u32(0x80000000)), 8, @bitCast(i32, u32(0xf0000000)), 0},
[]i32{@bitCast(i32, u32(0x80000007)), 8, @bitCast(i32, u32(0xf0000001)), -1},
};
for (cases) |case| {
test_one_divmodsi4(case[0], case[1], case[2], case[3]);
}
}
fn test_one_divmodsi4(a: i32, b: i32, expected_q: i32, expected_r: i32) void {
var r: i32 = undefined;
const q: i32 = __divmodsi4(a, b, &r);
testing.expect(q == expected_q and r == expected_r);
} | std/special/compiler_rt.zig |
const std = @import("std");
pub const code = struct {
// general
pub const BEL = "\x07";
pub const BS = "\x08";
pub const HT = "\x09";
pub const LF = "\x0A";
pub const VT = "\x0B";
pub const FF = "\x0C";
pub const CR = "\x0D";
pub const ESC = "\x1B";
pub const DEL = "\x07";
// foreground color
pub const fg_color = struct {
pub const black = "30";
pub const red = "31";
pub const green = "32";
pub const yellow = "33";
pub const blue = "34";
pub const magenta = "35";
pub const cyan = "36";
pub const white = "37";
};
// background colors
pub const bg_color = struct {
pub const black = "40";
pub const red = "41";
pub const green = "42";
pub const yellow = "43";
pub const blue = "44";
pub const magenta = "45";
pub const cyan = "46";
pub const white = "47";
};
};
pub const cursor = struct {
pub fn home() []u8 {
return code.ESC ++ "[H";
} //moves cursor to home position (0, 0)
// should be same as: code.ESC ++ "[{line};{column}f"
//pub fn goTo(line : i32, column : i32) []u8 { return code.ESC ++ "[{line};{column}H"; }
pub fn up(comptime x: u8) []const u8 {
return std.fmt.comptimePrint(code.ESC ++ "[{}A", .{x});
} //moves cursor up # lines
pub fn down(comptime x: u8) []const u8 {
return std.fmt.comptimePrint(code.ESC ++ "[{}B", .{x});
} //moves cursor down # lines
pub fn right(comptime x: u8) []const u8 {
return std.fmt.comptimePrint(code.ESC ++ "[{}C", .{x});
} //moves cursor right # columns
pub fn left(comptime x: u8) []const u8 {
return std.fmt.comptimePrint(code.ESC ++ "[{}D", .{x});
} //moves cursor left # columns
pub fn nextL(comptime x: u8) []const u8 {
return std.fmt.comptimePrint(code.ESC ++ "[{}E", .{x});
} //moves cursor to beginning of next line, # lines down
pub fn prevL(comptime x: u8) []const u8 {
return std.fmt.comptimePrint(code.ESC ++ "[{}F", .{x});
} //moves cursor to beginning of previous line, # lines up
//pub fn column() comptime []u8 {return code.ESC ++ "[#G"; } //moves cursor to column #
pub fn get() []u8 {
return (code.ESC ++ "[6n");
} //request cursor position (reports as ESC[#;#R)
};
pub const style = struct {
pub const reset = code.ESC ++ "[0m"; // resets style
pub const bold = code.ESC ++ "[1m"; // set bold mode.
pub const dim = code.ESC ++ "[2m"; // set dim/faint mode.
pub const italic = code.ESC ++ "[3m"; // set italic mode.
pub const underline = code.ESC ++ "[4m"; // set underline mode.
pub const blinking = code.ESC ++ "[5m"; // set blinking mode
pub const inverse = code.ESC ++ "[7m"; // set inverse/reverse mode
pub const invisible = code.ESC ++ "[8m"; // set invisible mode
pub const strikethrough = code.ESC ++ "[9m"; // set strikethrough mode.
// foreground color
pub const fg = struct {
pub fn rgb(comptime r: u8, comptime g: u8, comptime b: u8) []u8 {
return code.ESC ++ "[38;2;" ++ std.fmt.formatInt(r, 10, 0, .{}) ++ ";" ++ std.fmt.formatInt(g, 10, 0, .{}) ++ ";" ++ std.fmt.formatInt(b, 10, 0, .{}) ++ "m";
}
// 8 bit colors
pub const black = code.ESC ++ "[" ++ code.fg_color.black ++ "m";
pub const red = code.ESC ++ "[" ++ code.fg_color.red ++ "m";
pub const green = code.ESC ++ "[" ++ code.fg_color.green ++ "m";
pub const yellow = code.ESC ++ "[" ++ code.fg_color.yellow ++ "m";
pub const blue = code.ESC ++ "[" ++ code.fg_color.blue ++ "m";
pub const magenta = code.ESC ++ "[" ++ code.fg_color.magenta ++ "m";
pub const cyan = code.ESC ++ "[" ++ code.fg_color.cyan ++ "m";
pub const white = code.ESC ++ "[" ++ code.fg_color.white ++ "m";
// 256 color code
pub fn col256(comptime col: u8) []const u8 {
return std.fmt.comptimePrint(code.ESC ++ "[38;5;" ++ "{}m", .{col});
}
};
// background color
pub const bg = struct {
// 8 bit colors
pub const black = code.ESC ++ "[" ++ code.bg_color.black ++ "m";
pub const red = code.ESC ++ "[" ++ code.bg_color.red ++ "m";
pub const green = code.ESC ++ "[" ++ code.bg_color.green ++ "m";
pub const yellow = code.ESC ++ "[" ++ code.bg_color.yellow ++ "m";
pub const blue = code.ESC ++ "[" ++ code.bg_color.blue ++ "m";
pub const magenta = code.ESC ++ "[" ++ code.bg_color.magenta ++ "m";
pub const cyan = code.ESC ++ "[" ++ code.bg_color.cyan ++ "m";
pub const white = code.ESC ++ "[" ++ code.bg_color.white ++ "m";
// 256 color code
pub fn col256(comptime col: u8) []const u8 {
return std.fmt.comptimePrint(code.ESC ++ "[48;5;" ++ "{}m", .{col});
}
};
};
// private
// converts u8 to decimal str like 64 -> "064"
fn u8Str(comptime v: u8) []u8 {
const val = [3:0]u8{ '0' + (v / 100) % 10, '0' + (v / 10) % 10, '0' + v % 10 };
return val;
} | src/ansi_esc.zig |
const std = @import("std");
pub const Thread = if (std.builtin.os.tag == .windows)
WindowsThread
else if (std.builtin.link_libc)
PosixThread
else if (std.builtin.os.tag == .linux)
LinuxThread
else
@compileError("Platform not supported");
const WindowsThread = struct {
pub fn spawn(comptime entryFn: fn (usize) void, context: usize) bool {
const Wrapper = struct {
fn entry(raw_arg: std.os.windows.LPVOID) callconv(.C) std.os.windows.DWORD {
entryFn(@ptrToInt(raw_arg));
return 0;
}
};
const handle = std.os.windows.kernel32.CreateThread(
null,
0, // use default stack size
Wrapper.entry,
@intToPtr(std.os.windows.LPVOID, context),
0,
null,
) orelse return false;
// closing the handle detaches the thread
std.os.windows.CloseHandle(handle);
return true;
}
};
const PosixThread = struct {
pub fn spawn(comptime entryFn: fn (usize) void, context: usize) bool {
const Wrapper = struct {
fn entry(ctx: ?*anyopaque) callconv(.C) ?*anyopaque {
entryFn(@ptrToInt(ctx));
return null;
}
};
var handle: std.c.pthread_t = undefined;
const rc = std.c.pthread_create(
&handle,
null,
Wrapper.entry,
@intToPtr(?*anyopaque, context),
);
return rc == 0;
}
};
const LinuxThread = struct {
pub fn spawn(comptime entryFn: fn (usize) void, context: usize) bool {
const stack_size = 4 * 1024 * 1024;
var mmap_size: usize = std.mem.page_size;
const guard_end = mmap_size;
mmap_size = std.mem.alignForward(mmap_size + stack_size, std.mem.page_size);
const stack_end = mmap_size;
mmap_size = std.mem.alignForward(mmap_size, @alignOf(Info));
const info_begin = mmap_size;
mmap_size = std.mem.alignForward(mmap_size + @sizeOf(Info), std.os.linux.tls.tls_image.alloc_align);
const tls_begin = mmap_size;
mmap_size = std.mem.alignForward(mmap_size + std.os.linux.tls.tls_image.alloc_size, std.mem.page_size);
const mmap_bytes = std.os.mmap(
null,
mmap_size,
std.os.PROT_NONE,
std.os.MAP_PRIVATE | std.os.MAP_ANONYMOUS,
-1,
0,
) catch return false;
std.os.mprotect(
mmap_bytes[guard_end..],
std.os.PROT_READ | std.os.PROT_WRITE,
) catch {
std.os.munmap(mmap_bytes);
return false;
};
const info = @ptrCast(*Info, @alignCast(@alignOf(Info), &mmap_bytes[info_begin]));
info.* = .{
.mmap_ptr = @ptrToInt(mmap_bytes.ptr),
.mmap_len = mmap_bytes.len,
.context = context,
.callback = entryFn,
};
var user_desc: switch (std.builtin.arch) {
.i386 => std.os.linux.user_desc,
else => void,
} = undefined;
var tls_ptr = std.os.linux.tls.prepareTLS(mmap_bytes[tls_begin..]);
if (std.builtin.arch == .i386) {
defer tls_ptr = @ptrToInt(&user_desc);
user_desc = .{
.entry_number = std.os.linux.tls.tls_image.gdt_entry_number,
.base_addr = tls_ptr,
.limit = 0xfffff,
.seg_32bit = 1,
.contents = 0,
.read_exec_only = 0,
.limit_in_pages = 1,
.seg_not_present = 0,
.useable = 1,
};
}
const flags: u32 =
std.os.CLONE_SIGHAND | std.os.CLONE_SYSVSEM |
std.os.CLONE_VM | std.os.CLONE_FS | std.os.CLONE_FILES |
std.os.CLONE_THREAD | std.os.CLONE_DETACHED | std.os.CLONE_SETTLS;
var handle: i32 = undefined;
const rc = std.os.linux.clone(
Info.entry,
@ptrToInt(&mmap_bytes[stack_end]),
flags,
@ptrToInt(info),
&handle,
tls_ptr,
&handle,
);
if (std.os.errno(rc) != 0) {
std.os.munmap(mmap_bytes);
return false;
}
return true;
}
const Info = struct {
mmap_ptr: usize,
mmap_len: usize,
context: usize,
callback: fn (usize) void,
fn entry(raw_arg: usize) callconv(.C) u8 {
const self = @intToPtr(*Info, raw_arg);
_ = (self.callback)(self.context);
__unmap_and_exit(self.mmap_ptr, self.mmap_len);
}
};
extern fn __unmap_and_exit(ptr: usize, len: usize) callconv(.C) noreturn;
comptime {
asm (switch (std.builtin.arch) {
.i386 => (
\\.text
\\.global __unmap_and_exit
\\.type __unmap_and_exit, @function
\\__unmap_and_exit:
\\ movl $91, %eax
\\ movl 4(%esp), %ebx
\\ movl 8(%esp), %ecx
\\ int $128
\\ xorl %ebx, %ebx
\\ movl $1, %eax
\\ int $128
),
.x86_64 => (
\\.text
\\.global __unmap_and_exit
\\.type __unmap_and_exit, @function
\\__unmap_and_exit:
\\ movl $11, %eax
\\ syscall
\\ xor %rdi, %rdi
\\ movl $60, %eax
\\ syscall
),
.arm, .armeb, .aarch64, .aarch64_be, .aarch64_32 => (
\\.text
\\.global __unmap_and_exit
\\.type __unmap_and_exit, @function
\\__unmap_and_exit:
\\ mov r7, #91
\\ svc 0
\\ mov r7, #1
\\ svc 0
),
.mips, .mipsel, .mips64, .mips64el => (
\\.set noreorder
\\.global __unmap_and_exit
\\.type __unmap_and_exit, @function
\\__unmap_and_exit:
\\ li $2, 4091
\\ syscall
\\ li $4, 0
\\ li $2, 4001
\\ syscall
),
.powerpc, .powerpc64, .powerpc64le => (
\\.text
\\.global __unmap_and_exit
\\.type __unmap_and_exit, @function
\\__unmap_and_exit:
\\ li 0, 91
\\ sc
\\ li 0, 1
\\ sc
\\ blr
),
else => @compileError("Platform not supported"),
});
}
}; | src/runtime/Thread.zig |
const std = @import("std");
const Allocator = std.mem.Allocator;
const ArrayList = std.ArrayList;
const nvg = @import("nanovg");
const gui = @import("gui.zig");
const event = @import("event.zig");
const Point = @import("geometry.zig").Point;
const Rect = @import("geometry.zig").Rect;
const debug_focus = false;
const Widget = @This();
window: ?*gui.Window = null,
parent: ?*Widget = null,
children: ArrayList(*Widget),
relative_rect: Rect(f32), // Relative to parent
focus_policy: event.FocusPolicy = event.FocusPolicy{},
drawFn: fn (*Widget) void = drawChildren,
onResizeFn: fn (*Widget, *event.ResizeEvent) void = onResize,
onMouseMoveFn: fn (*Widget, *event.MouseEvent) void = onMouseMove,
onMouseDownFn: fn (*Widget, *event.MouseEvent) void = onMouseDown,
onMouseUpFn: fn (*Widget, *event.MouseEvent) void = onMouseUp,
onMouseWheelFn: fn (*Widget, *event.MouseEvent) void = onMouseWheel,
onTouchPanFn: fn (*Widget, *event.TouchEvent) void = onTouchPan,
onTouchZoomFn: fn (*Widget, *event.TouchEvent) void = onTouchZoom,
onKeyDownFn: fn (*Widget, *event.KeyEvent) void = onKeyDown,
onKeyUpFn: fn (*Widget, *event.KeyEvent) void = onKeyUp,
onTextInputFn: fn (*Widget, *event.TextInputEvent) void = onTextInput,
onFocusFn: fn (*Widget, *event.FocusEvent) void = onFocus,
onBlurFn: fn (*Widget, *event.FocusEvent) void = onBlur,
onEnterFn: fn (*Widget) void = onEnter,
onLeaveFn: fn (*Widget) void = onLeave,
onClipboardUpdateFn: fn (*Widget) void = onClipboardUpdate,
const Self = @This();
pub fn init(allocator: *Allocator, rect: Rect(f32)) Self {
return Self{ .children = ArrayList(*Self).init(allocator), .relative_rect = rect };
}
pub fn deinit(self: *Self) void {
self.children.deinit();
}
pub fn addChild(self: *Self, child: *Widget) !void {
std.debug.assert(child.parent == null);
child.parent = self;
try self.children.append(child);
}
pub fn getWindow(self: *Self) ?*gui.Window {
if (self.parent) |parent| {
return parent.getWindow();
}
return self.window;
}
pub fn getApplication(self: *Self) ?*gui.Application {
const window = self.getWindow() orelse return null;
return window.application;
}
pub fn isFocused(self: *Self) bool {
if (self.getWindow()) |window| {
return window.is_active and window.focused_widget == self;
}
return false;
}
pub fn setFocus(self: *Self, focus: bool, source: gui.FocusSource) void {
if (self.getWindow()) |window| {
window.setFocusedWidget(if (focus) self else null, source);
}
}
// local without position
pub fn getRect(self: Self) Rect(f32) {
return .{ .x = 0, .y = 0, .w = self.relative_rect.w, .h = self.relative_rect.h };
}
// position relative to containing window
pub fn getWindowRelativeRect(self: *Self) Rect(f32) {
if (self.parent) |parent| {
const offset = parent.getWindowRelativeRect().getPosition();
return self.relative_rect.translated(offset);
} else {
return self.relative_rect;
}
}
pub fn setPosition(self: *Self, x: f32, y: f32) void {
self.relative_rect.x = x;
self.relative_rect.y = y;
}
// also fires event
pub fn setSize(self: *Self, width: f32, height: f32) void {
if (width != self.relative_rect.w or height != self.relative_rect.h) {
var re = event.ResizeEvent{
.old_width = self.relative_rect.w,
.old_height = self.relative_rect.h,
.new_width = width,
.new_height = height,
};
self.relative_rect.w = width;
self.relative_rect.h = height;
self.handleEvent(&re.event);
}
}
pub fn drawChildren(self: *Self) void {
nvg.save();
defer nvg.restore();
const offset = self.relative_rect.getPosition();
nvg.translate(offset.x, offset.y);
for (self.children.items) |child| {
child.draw();
}
}
pub fn draw(self: *Self) void {
self.drawFn(self);
if (debug_focus) {
if (self.isFocused()) {
nvg.beginPath();
const r = self.relative_rect;
nvg.rect(r.x, r.y, r.w - 1, r.h - 1);
nvg.strokeColor(nvg.rgbf(1, 0, 0));
nvg.stroke();
}
}
}
pub const HitTestResult = struct {
widget: *Widget,
local_position: Point(f32),
};
pub fn hitTest(self: *Self, position: Point(f32)) HitTestResult {
const relative_position = position.subtracted(self.relative_rect.getPosition());
for (self.children.items) |child| {
if (child.relative_rect.contains(relative_position)) {
return child.hitTest(relative_position);
}
}
return HitTestResult{ .widget = self, .local_position = relative_position };
}
fn onResize(self: *Self, resize_event: *event.ResizeEvent) void {
_ = resize_event;
_ = self;
}
fn onMouseMove(self: *Self, mouse_event: *event.MouseEvent) void {
_ = mouse_event;
_ = self;
}
fn onMouseDown(self: *Self, mouse_event: *event.MouseEvent) void {
_ = mouse_event;
_ = self;
}
fn onMouseUp(self: *Self, mouse_event: *event.MouseEvent) void {
_ = mouse_event;
_ = self;
}
fn onMouseWheel(self: *Self, mouse_event: *event.MouseEvent) void {
_ = mouse_event;
_ = self;
}
fn onTouchPan(self: *Self, touch_event: *event.TouchEvent) void {
_ = touch_event;
_ = self;
}
fn onTouchZoom(self: *Self, touch_event: *event.TouchEvent) void {
_ = touch_event;
_ = self;
}
fn onKeyDown(self: *Self, key_event: *event.KeyEvent) void {
if (key_event.key == .Tab) {
if (key_event.modifiers == 0) {
self.focusNextWidget(.keyboard);
key_event.event.accept();
return;
} else if (key_event.isSingleModifierPressed(.shift)) {
self.focusPreviousWidget(.keyboard);
key_event.event.accept();
return;
}
}
key_event.event.ignore();
}
fn onKeyUp(self: *Self, key_event: *event.KeyEvent) void {
_ = self;
key_event.event.ignore();
}
fn onTextInput(self: *Self, text_input_event: *event.TextInputEvent) void {
_ = text_input_event;
_ = self;
}
fn onFocus(self: *Self, focus_event: *event.FocusEvent) void {
_ = focus_event;
_ = self;
}
fn onBlur(self: *Self, focus_event: *event.FocusEvent) void {
_ = focus_event;
_ = self;
}
fn onEnter(self: *Self) void {
_ = self;
}
fn onLeave(self: *Self) void {
_ = self;
}
fn onClipboardUpdate(self: *Self) void {
_ = self;
}
/// bubbles event up until it is accepted
pub fn dispatchEvent(self: *Self, e: *event.Event) void {
var maybe_target: ?*Self = self;
while (maybe_target) |target| : (maybe_target = target.parent) {
target.handleEvent(e);
if (e.is_accepted) break;
}
}
pub fn handleEvent(self: *Self, e: *event.Event) void {
const resize_event = @fieldParentPtr(event.ResizeEvent, "event", e);
const mouse_event = @fieldParentPtr(event.MouseEvent, "event", e);
const touch_event = @fieldParentPtr(event.TouchEvent, "event", e);
const key_event = @fieldParentPtr(event.KeyEvent, "event", e);
const text_input_event = @fieldParentPtr(event.TextInputEvent, "event", e);
const focus_event = @fieldParentPtr(event.FocusEvent, "event", e);
switch (e.type) {
.Resize => self.onResizeFn(self, resize_event),
.MouseMove => self.onMouseMoveFn(self, mouse_event),
.MouseDown => {
if (self.acceptsFocus(.mouse)) {
self.setFocus(true, .mouse);
}
self.onMouseDownFn(self, mouse_event);
},
.MouseUp => self.onMouseUpFn(self, mouse_event),
.MouseWheel => self.onMouseWheelFn(self, mouse_event),
.TouchPan => self.onTouchPanFn(self, touch_event),
.TouchZoom => self.onTouchZoomFn(self, touch_event),
.KeyDown => self.onKeyDownFn(self, key_event),
.KeyUp => self.onKeyUpFn(self, key_event),
.TextInput => self.onTextInputFn(self, text_input_event),
.Focus => self.onFocusFn(self, focus_event),
.Blur => self.onBlurFn(self, focus_event),
.Enter => self.onEnterFn(self),
.Leave => self.onLeaveFn(self),
.ClipboardUpdate => self.onClipboardUpdateFn(self),
}
}
pub fn acceptsFocus(self: Self, source: event.FocusSource) bool {
return self.focus_policy.accepts(source);
}
fn focusNextWidget(self: *Self, source: event.FocusSource) void {
if (!self.acceptsFocus(source)) return;
const window = self.getWindow() orelse return;
var focusable_widgets = std.ArrayList(*gui.Widget).init(self.children.allocator);
defer focusable_widgets.deinit();
window.collectFocusableWidgets(&focusable_widgets, source) catch return;
if (std.mem.indexOfScalar(*gui.Widget, focusable_widgets.items, self)) |i| {
const next_i = (i + 1) % focusable_widgets.items.len;
focusable_widgets.items[next_i].setFocus(true, .keyboard);
}
}
fn focusPreviousWidget(self: *Self, source: event.FocusSource) void {
if (!self.acceptsFocus(source)) return;
const window = self.getWindow() orelse return;
var focusable_widgets = std.ArrayList(*gui.Widget).init(self.children.allocator);
defer focusable_widgets.deinit();
window.collectFocusableWidgets(&focusable_widgets, source) catch return;
if (std.mem.indexOfScalar(*gui.Widget, focusable_widgets.items, self)) |i| {
const n = focusable_widgets.items.len;
const previous_i = (i + n - 1) % n;
focusable_widgets.items[previous_i].setFocus(true, .keyboard);
}
} | src/gui/Widget.zig |
const std = @import("std");
const Allocator = std.mem.Allocator;
const ArrayList = std.ArrayList;
const assert = std.debug.assert;
const print = std.debug.print;
const input = @embedFile("../input/day08.txt");
const Operation = enum(u8) {
Acc,
Jmp,
Nop,
};
const Instruction = struct {
operation: Operation,
argument: i32,
execution_counter: usize = 0,
fn initFromString(string: []const u8) !Instruction {
var tokens = std.mem.tokenize(string, " ");
const op = tokens.next() orelse return error.MissingOperation;
const arg = tokens.next() orelse return error.MissingArgument;
var self = Instruction{
.operation = undefined,
.argument = try std.fmt.parseInt(i32, arg, 10),
};
if (std.mem.eql(u8, op, "acc")) {
self.operation = .Acc;
} else if (std.mem.eql(u8, op, "jmp")) {
self.operation = .Jmp;
} else if (std.mem.eql(u8, op, "nop")) {
self.operation = .Nop;
} else {
return error.UnknownOperation;
}
return self;
}
};
const Program = struct {
instructions: ArrayList(Instruction),
program_counter: usize = 0,
accumulator: i32 = 0,
fn initFromString(allocator: *Allocator, string: []const u8) !Program {
var self = Program{
.instructions = ArrayList(Instruction).init(allocator),
};
var lines = std.mem.split(string, "\n");
while (lines.next()) |line| {
try self.instructions.append(try Instruction.initFromString(line));
}
return self;
}
fn deinit(self: *Program) void {
self.instructions.deinit();
}
fn execute(self: *Program) bool { // true if terminated
while (self.program_counter < self.instructions.items.len) {
var instruction = &self.instructions.items[self.program_counter];
if (instruction.execution_counter >= 1) return false;
instruction.execution_counter += 1;
switch (instruction.operation) {
.Acc => self.accumulator += instruction.argument,
.Jmp => {
const address = @intCast(i32, self.program_counter) + instruction.argument;
self.program_counter = @intCast(usize, address);
continue;
},
.Nop => {},
}
self.program_counter += 1;
}
return true;
}
};
pub fn main() !void {
var gpa = std.heap.GeneralPurposeAllocator(.{}){};
var allocator = &gpa.allocator;
var program = try Program.initFromString(allocator, input);
_ = program.execute();
print("part1: {}\n", .{program.accumulator});
program.deinit();
var i: usize = 0;
while (true) : (i += 1) {
program = try Program.initFromString(allocator, input);
defer program.deinit();
// manipulate an instruction
while (program.instructions.items[i].operation == .Acc) i += 1;
var instruction = &program.instructions.items[i];
instruction.operation = if (instruction.operation == .Jmp) .Nop else .Jmp;
if (program.execute()) {
print("part2: {}\n", .{program.accumulator});
break;
}
}
}
const example =
\\nop +0
\\acc +1
\\jmp +4
\\acc +3
\\jmp -3
\\acc -99
\\acc +1
\\jmp -4
\\acc +6
; | src/day08.zig |
//--------------------------------------------------------------------------------
// Section: Types (3)
//--------------------------------------------------------------------------------
const CLSID_IsolatedAppLauncher_Value = @import("../zig.zig").Guid.initString("bc812430-e75e-4fd1-9641-1f9f1e2d9a1f");
pub const CLSID_IsolatedAppLauncher = &CLSID_IsolatedAppLauncher_Value;
pub const IsolatedAppLauncherTelemetryParameters = extern struct {
EnableForLaunch: BOOL,
CorrelationGUID: Guid,
};
const IID_IIsolatedAppLauncher_Value = @import("../zig.zig").Guid.initString("f686878f-7b42-4cc4-96fb-f4f3b6e3d24d");
pub const IID_IIsolatedAppLauncher = &IID_IIsolatedAppLauncher_Value;
pub const IIsolatedAppLauncher = extern struct {
pub const VTable = extern struct {
base: IUnknown.VTable,
Launch: fn(
self: *const IIsolatedAppLauncher,
appUserModelId: ?[*:0]const u16,
arguments: ?[*:0]const u16,
telemetryParameters: ?*const IsolatedAppLauncherTelemetryParameters,
) callconv(@import("std").os.windows.WINAPI) HRESULT,
};
vtable: *const VTable,
pub fn MethodMixin(comptime T: type) type { return struct {
pub usingnamespace IUnknown.MethodMixin(T);
// NOTE: method is namespaced with interface name to avoid conflicts for now
pub fn IIsolatedAppLauncher_Launch(self: *const T, appUserModelId: ?[*:0]const u16, arguments: ?[*:0]const u16, telemetryParameters: ?*const IsolatedAppLauncherTelemetryParameters) callconv(.Inline) HRESULT {
return @ptrCast(*const IIsolatedAppLauncher.VTable, self.vtable).Launch(@ptrCast(*const IIsolatedAppLauncher, self), appUserModelId, arguments, telemetryParameters);
}
};}
pub usingnamespace MethodMixin(@This());
};
//--------------------------------------------------------------------------------
// Section: Functions (10)
//--------------------------------------------------------------------------------
// TODO: this type is limited to platform 'windows8.0'
pub extern "KERNEL32" fn GetAppContainerNamedObjectPath(
Token: ?HANDLE,
AppContainerSid: ?PSID,
ObjectPathLength: u32,
ObjectPath: ?[*:0]u16,
ReturnLength: ?*u32,
) callconv(@import("std").os.windows.WINAPI) BOOL;
pub extern "api-ms-win-security-isolatedcontainer-l1-1-1" fn IsProcessInWDAGContainer(
Reserved: ?*anyopaque,
isProcessInWDAGContainer: ?*BOOL,
) callconv(@import("std").os.windows.WINAPI) HRESULT;
pub extern "api-ms-win-security-isolatedcontainer-l1-1-0" fn IsProcessInIsolatedContainer(
isProcessInIsolatedContainer: ?*BOOL,
) callconv(@import("std").os.windows.WINAPI) HRESULT;
pub extern "IsolatedWindowsEnvironmentUtils" fn IsProcessInIsolatedWindowsEnvironment(
isProcessInIsolatedWindowsEnvironment: ?*BOOL,
) callconv(@import("std").os.windows.WINAPI) HRESULT;
// TODO: this type is limited to platform 'windows8.0'
pub extern "USERENV" fn CreateAppContainerProfile(
pszAppContainerName: ?[*:0]const u16,
pszDisplayName: ?[*:0]const u16,
pszDescription: ?[*:0]const u16,
pCapabilities: ?[*]SID_AND_ATTRIBUTES,
dwCapabilityCount: u32,
ppSidAppContainerSid: ?*?PSID,
) callconv(@import("std").os.windows.WINAPI) HRESULT;
// TODO: this type is limited to platform 'windows8.0'
pub extern "USERENV" fn DeleteAppContainerProfile(
pszAppContainerName: ?[*:0]const u16,
) callconv(@import("std").os.windows.WINAPI) HRESULT;
// TODO: this type is limited to platform 'windows8.0'
pub extern "USERENV" fn GetAppContainerRegistryLocation(
desiredAccess: u32,
phAppContainerKey: ?*?HKEY,
) callconv(@import("std").os.windows.WINAPI) HRESULT;
// TODO: this type is limited to platform 'windows8.0'
pub extern "USERENV" fn GetAppContainerFolderPath(
pszAppContainerSid: ?[*:0]const u16,
ppszPath: ?*?PWSTR,
) callconv(@import("std").os.windows.WINAPI) HRESULT;
// TODO: this type is limited to platform 'windows10.0.10240'
pub extern "USERENV" fn DeriveRestrictedAppContainerSidFromAppContainerSidAndRestrictedName(
psidAppContainerSid: ?PSID,
pszRestrictedAppContainerName: ?[*:0]const u16,
ppsidRestrictedAppContainerSid: ?*?PSID,
) callconv(@import("std").os.windows.WINAPI) HRESULT;
// TODO: this type is limited to platform 'windows8.0'
pub extern "USERENV" fn DeriveAppContainerSidFromAppContainerName(
pszAppContainerName: ?[*:0]const u16,
ppsidAppContainerSid: ?*?PSID,
) callconv(@import("std").os.windows.WINAPI) HRESULT;
//--------------------------------------------------------------------------------
// Section: Unicode Aliases (0)
//--------------------------------------------------------------------------------
const thismodule = @This();
pub usingnamespace switch (@import("../zig.zig").unicode_mode) {
.ansi => struct {
},
.wide => struct {
},
.unspecified => if (@import("builtin").is_test) struct {
} else struct {
},
};
//--------------------------------------------------------------------------------
// Section: Imports (9)
//--------------------------------------------------------------------------------
const Guid = @import("../zig.zig").Guid;
const BOOL = @import("../foundation.zig").BOOL;
const HANDLE = @import("../foundation.zig").HANDLE;
const HKEY = @import("../system/registry.zig").HKEY;
const HRESULT = @import("../foundation.zig").HRESULT;
const IUnknown = @import("../system/com.zig").IUnknown;
const PSID = @import("../foundation.zig").PSID;
const PWSTR = @import("../foundation.zig").PWSTR;
const SID_AND_ATTRIBUTES = @import("../security.zig").SID_AND_ATTRIBUTES;
test {
@setEvalBranchQuota(
@import("std").meta.declarations(@This()).len * 3
);
// reference all the pub declarations
if (!@import("builtin").is_test) return;
inline for (@import("std").meta.declarations(@This())) |decl| {
if (decl.is_pub) {
_ = decl;
}
}
} | win32/security/isolation.zig |
// --- Globals
// TODO: Need to be zeroed explicitly since c static forces zero.
export var mparams: malloc_params = undefined;
export var _gm_: malloc_state = undefined;
const gm = *_gm_;
// --- Types
pub const malloc_chunk = extern struct {
prev_foot: usize, // size of previous chunk (if free)
head: usize, // size and inuse bits
fd: ?*malloc_chunk, // double links -- used only if free
bk: ?*malloc_chunk,
};
const mchunk = malloc_chunk;
const mchunkptr = ?*malloc_chunk;
const sbinptr = ?*malloc_chunk; // type of bins of chunks
const bindex_t = c_uint;
const binmap_t = c_uint;
const flag_t = c_uint; // type of various bit flag sets
pub const malloc_tree_chunk = extern struct {
// first four fields must be compatible with malloc_chunk
prev_foot: usize,
head: usize,
fd: ?*malloc_tree_chunk,
bk: ?*malloc_tree_chunk,
child: [2]?*malloc_tree_chunk,
parent: ?*malloc_tree_chunk,
index: bindex_t,
};
const tchunk = malloc_tree_chunk;
const tchunkptr = ?*malloc_tree_chunk;
const tbinptr = ?*malloc_tree_chunk; // type of bins of trees
pub const malloc_segment = extern struct {
base: ?*u8, // base address
size: usize, // allocated size
next: ?*malloc_segment, // ptr to next segment
sflags: flag_t, // mmap and extern flag
};
const msegment = malloc_segment;
const msegmentptr = ?*malloc_segment;
// Only used as a dependent
// TODO: Platform dependent.
const CHUNK_OVERHEAD = @sizeOf(usize);
const MALLOC_ALIGNMENT = 2 * @sizeOf(?*c_void); // This is exported incorrectly
const CHUNK_ALIGN_MASK = MALLOC_ALIGNMENT - 1;
// These are left as defines in dlmalloc.c so they can be at compile-time
// May not be necessary.
const NSMALLBINS = 32;
const NTREEBINS = 32;
const SMALLBIN_SHIFT = 3;
const SMALLBIN_WIDTH = 1 << SMALLBIN_SHIFT;
const TREEBIN_SHIFT = 8;
const MIN_LARGE_SIZE = 1 << TREEBIN_SHIFT;
const MAX_SMALL_SIZE = MIN_LARGE_SIZE - 1;
const MAX_SMALL_REQUEST = MAX_SMALL_SIZE - CHUNK_ALIGN_MASK - CHUNK_OVERHEAD;
pub const malloc_state = extern struct {
smallmap: binmap_t,
treemap: binmap_t,
dvsize: usize,
topsize: usize,
least_addr: ?*u8,
dv: mchunkptr,
top: mchunkptr,
trim_check: usize,
release_checks: usize,
magic: usize,
// NOTE: Exporting these require a patched compiler. Incoming pull.
smallbins: [(NSMALLBINS + 1) * 2]mchunkptr,
treebins: [NTREEBINS]tbinptr,
footprint: usize,
max_footprint: usize,
footprint_limit: usize, // zero means no limit
mflags: flag_t,
seg: msegment,
extp: ?*c_void, // unused but available for externsions
exts: usize,
};
extern const mstate = ?*malloc_state;
//#define is_initialized(M) ((M)->top != 0)
export fn is_initialized(m: ?*malloc_state) bool {
return (??m).top != null;
}
pub const malloc_params = extern struct {
magic: usize,
page_size: usize,
granularity: usize,
mmap_threshold: usize,
trim_threshold: usize,
default_mflags: flag_t,
};
// Workaround to export types to a header file.
export fn __type_export_workaround(
a: malloc_chunk,
b: malloc_tree_chunk,
c: malloc_segment,
d: malloc_state,
e: malloc_params,
f: [3]u8,
g: [3][5]u8,
) void {}
// --------------------------------------------------------------
//#define is_aligned(A) (((size_t)((A)) & (CHUNK_ALIGN_MASK)) == 0)
export fn is_aligned(a: ?*c_void) bool {
const q = @ptrToInt(a);
return q & CHUNK_ALIGN_MASK == 0;
}
//#define align_offset(A)\
// ((((size_t)(A) & CHUNK_ALIGN_MASK) == 0)? 0 :\
// ((MALLOC_ALIGNMENT - ((size_t)(A) & CHUNK_ALIGN_MASK)) & CHUNK_ALIGN_MASK))
export fn align_offset(a: usize) usize {
if (a & CHUNK_ALIGN_MASK == 0) {
return 0;
} else {
return (MALLOC_ALIGNMENT - (a & CHUNK_ALIGN_MASK)) & CHUNK_ALIGN_MASK;
}
}
// #define chunk2mem(p) ((void*)((char*)(p) + TWO_SIZE_T_SIZES))
export fn chunk2mem(p: ?*c_void) ?*c_void {
const q = @ptrToInt(p);
return @intToPtr(?*c_void, q + 2 * @sizeOf(usize));
}
//#define mem2chunk(mem) ((mchunkptr)((char*)(mem) - TWO_SIZE_T_SIZES))
export fn mem2chunk(p: ?*c_void) ?*malloc_chunk {
const q = @ptrToInt(p);
return @intToPtr(?*malloc_chunk, q - 2 * @sizeOf(usize));
}
//#define align_as_chunk(A) (mchunkptr)((A) + align_offset(chunk2mem(A)))
export fn align_as_chunk(p: ?*c_void) ?*malloc_chunk {
const q = @ptrToInt(p);
const aoff = @ptrToInt(chunk2mem(p));
return @intToPtr(?*malloc_chunk, q + align_offset(aoff));
}
const MAX_REQUEST = (-MIN_CHUNK_SIZE << 2);
const MIN_REQUEST = (MIN_CHUNK_SIZE - CHUNK_OVERHEAD - 1);
const MIN_CHUNK_SIZE = (@sizeOf(malloc_chunk) + CHUNK_ALIGN_MASK) & ~usize(CHUNK_ALIGN_MASK);
const MMAP_CHUNK_OVERHEAD = 2 * @sizeOf(usize);
const MMAP_FOOT_PAD = 4 * @sizeOf(usize);
//#define pad_request(req) \
// (((req) + CHUNK_OVERHEAD + CHUNK_ALIGN_MASK) & ~CHUNK_ALIGN_MASK)
export fn pad_request(a: usize) usize {
return (a + CHUNK_OVERHEAD + CHUNK_ALIGN_MASK) & ~usize(CHUNK_ALIGN_MASK);
}
//#define request2size(req) \
// (((req) < MIN_REQUEST)? MIN_CHUNK_SIZE : pad_request(req))
export fn request2size(a: usize) usize {
if (a < MIN_REQUEST) {
return MIN_CHUNK_SIZE;
} else {
return pad_request(a);
}
}
// --- Bits
const PINUSE_BIT = usize(1);
const CINUSE_BIT = usize(2);
const FLAG4_BIT = usize(4);
const INUSE_BITS = PINUSE_BIT | CINUSE_BIT;
const FLAG_BITS = PINUSE_BIT | CINUSE_BIT | FLAG4_BIT;
const FENCEPOST_HEAD = INUSE_BITS | @sizeOf(usize);
// #define cinuse(p) ((p)->head & CINUSE_BIT)
export fn cinuse(p: ?*malloc_chunk) bool {
return (??p).head & CINUSE_BIT != 0;
}
// #define pinuse(p) ((p)->head & PINUSE_BIT)
export fn pinuse(p: ?*malloc_chunk) bool {
return (??p).head & PINUSE_BIT != 0;
}
// #define flag4inuse(p) ((p)->head & FLAG4_BIT)
export fn flag4inuse(p: ?*malloc_chunk) bool {
return (??p).head & FLAG4_BIT != 0;
}
// #define is_inuse(p) (((p)->head & INUSE_BITS) != PINUSE_BIT)
export fn is_inuse(p: ?*malloc_chunk) bool {
return (??p).head & INUSE_BITS != PINUSE_BIT;
}
// #define is_mmapped(p) (((p)->head & INUSE_BITS) == 0)
export fn is_mmapped(p: ?*malloc_chunk) bool {
return (??p).head & INUSE_BITS == 0;
}
// #define chunksize(p) ((p)->head & ~(FLAG_BITS))
export fn chunksize(p: ?*malloc_chunk) usize {
return (??p).head & ~(FLAG_BITS);
}
// #define clear_pinuse(p) ((p)->head &= ~PINUSE_BIT)
export fn clear_pinuse(p: ?*malloc_chunk) void {
(??p).head &= ~PINUSE_BIT;
}
// #define set_flag4(p) ((p)->head |= FLAG4_BIT)
export fn set_flag4(p: ?*malloc_chunk) void {
return (??p).head |= FLAG4_BIT;
}
// #define clear_flag4(p) ((p)->head &= ~FLAG4_BIT)
export fn clear_flag4(p: ?*malloc_chunk) void {
return (??p).head &= ~FLAG4_BIT;
}
// ---- Head foot
//#define chunk_plus_offset(p, s) ((mchunkptr)(((char*)(p)) + (s)))
export fn chunk_plus_offset(p: ?*malloc_chunk, s: usize) ?*malloc_chunk {
const q = @ptrToInt(p);
return @intToPtr(?*malloc_chunk, q + s);
}
//#define chunk_minus_offset(p, s) ((mchunkptr)(((char*)(p)) - (s)))
export fn chunk_minus_offset(p: ?*malloc_chunk, s: usize) ?*malloc_chunk {
const q = @ptrToInt(p);
return @intToPtr(?*malloc_chunk, q - s);
}
//#define next_chunk(p) ((mchunkptr)( ((char*)(p)) + ((p)->head & ~FLAG_BITS)))
export fn next_chunk(p: ?*malloc_chunk) ?*malloc_chunk {
const q = @ptrToInt(p);
return @intToPtr(?*malloc_chunk, q + ((??p).head & ~FLAG_BITS));
}
//#define prev_chunk(p) ((mchunkptr)( ((char*)(p)) - ((p)->prev_foot) ))
export fn prev_chunk(p: ?*malloc_chunk) ?*malloc_chunk {
const q = @ptrToInt(p);
return @intToPtr(?*malloc_chunk, q - (??p).prev_foot);
}
//#define next_pinuse(p) ((next_chunk(p)->head) & PINUSE_BIT)
export fn next_pinuse(p: ?*malloc_chunk) bool {
return ((??next_chunk(p)).head & PINUSE_BIT) != 0;
}
//#define get_foot(p, s) (((mchunkptr)((char*)(p) + (s)))->prev_foot)
export fn get_foot(p: ?*malloc_chunk, s: usize) usize {
const q = @ptrToInt(p);
const f = @intToPtr(?*malloc_chunk, q + s);
return (??f).prev_foot;
}
//#define set_foot(p, s) (((mchunkptr)((char*)(p) + (s)))->prev_foot = (s))
export fn set_foot(p: ?*malloc_chunk, s: usize) void {
const q = @ptrToInt(p);
const f = @intToPtr(?*malloc_chunk, q + s);
(??f).prev_foot = s;
}
//#define set_size_and_pinuse_of_free_chunk(p, s)\
// ((p)->head = (s|PINUSE_BIT), set_foot(p, s))
export fn set_size_and_pinuse_of_free_chunk(p: ?*malloc_chunk, s: usize) void {
(??p).head = s | PINUSE_BIT;
set_foot(p, s);
}
//#define set_free_with_pinuse(p, s, n)\
// (clear_pinuse(n), set_size_and_pinuse_of_free_chunk(p, s))
export fn set_free_with_pinuse(p: ?*malloc_chunk, s: usize, n: ?*malloc_chunk) void {
clear_pinuse(n);
set_size_and_pinuse_of_free_chunk(p, s);
}
//#define overhead_for(p)\
// (is_mmapped(p)? MMAP_CHUNK_OVERHEAD : CHUNK_OVERHEAD)
export fn overhead_for(p: ?*malloc_chunk) usize {
if (is_mmapped(p)) {
return MMAP_CHUNK_OVERHEAD;
} else {
return CHUNK_OVERHEAD;
}
}
//#define leftmost_child(t) ((t)->child[0] != 0? (t)->child[0] : (t)->child[1])
export fn leftmost_child(t: ?*malloc_tree_chunk) ?*malloc_tree_chunk {
if ((??t).child[0] != null) {
return (??t).child[0];
} else {
return (??t).child[1];
}
}
// TODO: For now assume MMAP while shared
const USE_MMAP_BIT = usize(1);
const USE_NONCONTIGUOUS_BIT = usize(4);
const EXTERN_BIT = usize(8);
//#define is_mmapped_segment(S) ((S)->sflags & USE_MMAP_BIT)
export fn is_mmapped_segment(s: ?*malloc_segment) bool {
return ((??s).sflags & USE_MMAP_BIT) != 0;
}
//#define is_extern_segment(S) ((S)->sflags & EXTERN_BIT)
export fn is_extern_segment(s: ?*malloc_segment) bool {
return ((??s).sflags & EXTERN_BIT) != 0;
}
//#define segment_holds(S, A)\
// ((char*)(A) >= S->base && (char*)(A) < S->base + S->size)
export fn segment_holds(s: ?*malloc_segment, a: ?*malloc_chunk) bool {
const abase = @ptrToInt(a);
const sbase = @ptrToInt((??s).base);
return abase >= sbase and abase < sbase + (??s).size;
}
//#define should_trim(M,s) (0)
export fn should_trim(m: ?*malloc_state, s: usize) bool {
return false;
} | dlmalloc.zig |
const regs = @import("../types/regs.zig");
const mmio = @import("mmio.zig");
const uart = @import("uart.zig");
const Register = regs.Register;
pub const VCORE_MBOX : u32 = mmio.MMIO_BASE + 0x0000B880;
pub const MBOX_READ = Register { .ReadOnly = VCORE_MBOX + 0x0 };
pub const MBOX_POLL : u32 = VCORE_MBOX + 0x10;
pub const MBOX_SENDER : u32 = VCORE_MBOX + 0x14;
pub const MBOX_STATUS = Register { .ReadOnly = VCORE_MBOX + 0x18 };
pub const MBOX_CONFIG : u32 = VCORE_MBOX + 0x1C;
pub const MBOX_WRITE = Register { .WriteOnly = VCORE_MBOX + 0x20 };
pub const MBOX_RESPONSE : u32 = 0x80000000;
pub const MBOX_FULL : u32 = 0x80000000;
pub const MBOX_EMPTY : u32 = 0x40000000;
pub const MBOX_REQUEST : u32 = 0;
// Channels
pub const MBOX_CH_POWER : u32 = 0;
pub const MBOX_CH_FB : u32 = 1;
pub const MBOX_CH_VUART : u32 = 2;
pub const MBOX_CH_VCHIQ : u32 = 3;
pub const MBOX_CH_LEDS : u32 = 4;
pub const MBOX_CH_BTNS : u32 = 5;
pub const MBOX_CH_TOUCH : u32 = 6;
pub const MBOX_CH_COUNT : u32 = 7;
pub const MBOX_CH_PROP : u32 = 8;
// Tags
pub const MBOX_TAG_GETSERIAL : u32 = 0x10004;
pub const MBOX_TAG_SETPOWER : u32 = 0x28001;
pub const MBOX_TAG_SETCLKRATE : u32 = 0x38002;
pub const MBOX_TAG_LAST : u32 = 0;
// @NOTE: This has to be an array of u32!
/// 16-bit aligned `u32` array for the mailbox calls.
pub var mbox: [36]u32 align(16) = [1]u32{0}**36;
/// Make a call to the mailbox to query information. Note that when running on
/// emulated hardware this may have different results, e.g. a serial number
/// query will always return 0.
pub fn mboxCall(d: u8) ?void {
const val : u32 = 0xf; //FIXME
const r: u32 = @intCast(u32, (@ptrToInt(&mbox) & ~val)) | @intCast(u32, (@intCast(u32, d) & 0xF));
while(mmio.read(MBOX_STATUS).? & MBOX_FULL != 0) {
mmio.wait(1);
}
mmio.write(MBOX_WRITE, r).?;
while (true) {
while (mmio.read(MBOX_STATUS).? & MBOX_EMPTY != 0) {
mmio.wait(1);
}
if (mmio.read(MBOX_READ).? == r)
if (mbox[1] == MBOX_RESPONSE) return else return null;
}
} | kernel/src/arch/aarch64/io/mbox.zig |
const x86_64 = @import("../index.zig");
const bitjuggle = @import("bitjuggle");
const std = @import("std");
const formatWithoutFields = @import("../common.zig").formatWithoutFields;
/// Various control flags modifying the basic operation of the CPU.
pub const Cr0 = packed struct {
/// Enables protected mode.
protected_mode: bool,
/// Enables monitoring of the coprocessor, typical for x87 instructions.
///
/// Controls together with the `task_switched` flag whether a `wait` or `fwait`
/// instruction should cause an `#NE` exception.
monitor_coprocessor: bool,
/// Force all x87 and MMX instructions to cause an `#NE` exception.
emulate_coprocessor: bool,
/// Automatically set to 1 on _hardware_ task switch.
///
/// This flags allows lazily saving x87/MMX/SSE instructions on hardware context switches.
task_switched: bool,
/// Indicates support of 387DX math coprocessor instructions.
///
/// Always set on all recent x86 processors, cannot be cleared.
extension_type: bool,
/// Enables the native (internal) error reporting mechanism for x87 FPU errors.
numeric_error: bool,
z_reserved6_15: u10,
/// Controls whether supervisor-level writes to read-only pages are inhibited.
///
/// When set, it is not possible to write to read-only pages from ring 0.
write_protect: bool,
z_reserved17: bool,
/// Enables automatic usermode alignment checking if `RFlags.alignment_check` is also set.
alignment_mask: bool,
z_reserved19_28: u10,
/// Ignored. Used to control write-back/write-through cache strategy on older CPUs.
not_write_through: bool,
/// Disables some processor caches, specifics are model-dependent.
cache_disable: bool,
/// Enables paging.
///
/// If this bit is set, `protected_mode` must be set.
paging: bool,
z_reserved32_63: u32,
/// Read the current set of CR0 flags.
pub fn read() Cr0 {
return Cr0.fromU64(readRaw());
}
/// Read the current raw CR0 value.
fn readRaw() u64 {
return asm ("mov %%cr0, %[ret]"
: [ret] "=r" (-> u64),
);
}
/// Write CR0 flags.
///
/// Preserves the value of reserved fields.
pub fn write(self: Cr0) void {
writeRaw(self.toU64() | (readRaw() & ALL_RESERVED));
}
/// Write raw CR0 flags.
///
/// Does _not_ preserve any values, including reserved fields.
fn writeRaw(value: u64) void {
asm volatile ("mov %[val], %%cr0"
:
: [val] "r" (value),
: "memory"
);
}
const ALL_RESERVED: u64 = blk: {
var flags = std.mem.zeroes(Cr0);
flags.z_reserved6_15 = std.math.maxInt(u10);
flags.z_reserved17 = true;
flags.z_reserved19_28 = std.math.maxInt(u10);
flags.z_reserved32_63 = std.math.maxInt(u32);
break :blk @bitCast(u64, flags);
};
const ALL_NOT_RESERVED: u64 = ~ALL_RESERVED;
pub fn fromU64(value: u64) Cr0 {
return @bitCast(Cr0, value & ALL_NOT_RESERVED);
}
pub fn toU64(self: Cr0) u64 {
return @bitCast(u64, self) & ALL_NOT_RESERVED;
}
pub fn format(value: Cr0, comptime fmt: []const u8, options: std.fmt.FormatOptions, writer: anytype) !void {
_ = fmt;
return formatWithoutFields(
value,
options,
writer,
&.{ "z_reserved6_15", "z_reserved17", "z_reserved19_28", "z_reserved32_63" },
);
}
test {
try std.testing.expectEqual(@as(usize, 64), @bitSizeOf(Cr0));
try std.testing.expectEqual(@as(usize, 8), @sizeOf(Cr0));
try std.testing.expectEqual(@as(usize, 0b11100000000001010000000000111111), ALL_NOT_RESERVED);
}
comptime {
std.testing.refAllDecls(@This());
}
};
/// Contains the Page Fault Linear Address (PFLA).
///
/// When a page fault occurs, the CPU sets this register to the faulting virtual address.
pub const Cr2 = struct {
/// Read the current page fault linear address from the CR2 register.
pub fn read() x86_64.VirtAddr {
// We can use unchecked as this virtual address is set by the CPU itself
return x86_64.VirtAddr.initUnchecked(asm ("mov %%cr2, %[ret]"
: [ret] "=r" (-> u64),
));
}
comptime {
std.testing.refAllDecls(@This());
}
};
/// Controls cache settings for the highest-level page table.
///
/// Unused if paging is disabled or if `Cr4Flags.pcid` is enabled.
pub const Cr3Flags = packed struct {
z_reserved0: bool,
z_reserved1: bool,
/// Use a writethrough cache policy for the table (otherwise a writeback policy is used).
page_level_writethrough: bool,
/// Disable caching for the table.
page_level_cache_disable: bool,
z_reserved4_63: u60,
const ALL_RESERVED: u64 = blk: {
var flags = std.mem.zeroes(Cr3Flags);
flags.z_reserved0 = true;
flags.z_reserved1 = true;
flags.z_reserved4_63 = std.math.maxInt(u60);
break :blk @bitCast(u64, flags);
};
const ALL_NOT_RESERVED: u64 = ~ALL_RESERVED;
pub fn fromU64(value: u64) Cr3Flags {
return @bitCast(Cr3Flags, value & ALL_NOT_RESERVED);
}
pub fn toU64(self: Cr3Flags) u64 {
return @bitCast(u64, self) & ALL_NOT_RESERVED;
}
pub fn format(value: Cr3Flags, comptime fmt: []const u8, options: std.fmt.FormatOptions, writer: anytype) !void {
_ = fmt;
return formatWithoutFields(
value,
options,
writer,
&.{ "z_reserved0", "z_reserved1", "z_reserved4_63" },
);
}
test {
try std.testing.expectEqual(@as(usize, 64), @bitSizeOf(Cr3Flags));
try std.testing.expectEqual(@as(usize, 8), @sizeOf(Cr3Flags));
}
comptime {
std.testing.refAllDecls(@This());
}
};
/// Contains the physical address of the highest-level page table.
pub const Cr3 = struct {
pub const Contents = struct {
phys_frame: x86_64.structures.paging.PhysFrame,
cr3_flags: Cr3Flags,
pub fn toU64(self: Contents) u64 {
return self.phys_frame.start_address.value | self.cr3_flags.toU64();
}
};
pub const PcidContents = struct {
phys_frame: x86_64.structures.paging.PhysFrame,
pcid: x86_64.instructions.tlb.Pcid,
pub fn toU64(self: PcidContents) u64 {
return self.phys_frame.start_address.value | @as(u64, self.pcid.value);
}
};
/// Read the current P4 table address from the CR3 register.
pub fn read() Contents {
const value = readRaw();
return .{
.phys_frame = x86_64.structures.paging.PhysFrame.containingAddress(
// unchecked is fine as the mask ensures validity
x86_64.PhysAddr.initUnchecked(value & 0x000f_ffff_ffff_f000),
),
.cr3_flags = Cr3Flags.fromU64(value),
};
}
/// Read the raw value from the CR3 register
fn readRaw() u64 {
return asm ("mov %%cr3, %[value]"
: [value] "=r" (-> u64),
);
}
/// Read the current P4 table address from the CR3 register along with PCID.
/// The correct functioning of this requires CR4.PCIDE = 1.
/// See [`Cr4Flags::PCID`]
pub fn readPcid() PcidContents {
const value = readRaw();
return .{
.phys_frame = x86_64.structures.paging.PhysFrame.containingAddress(
// unchecked is fine as the mask ensures validity
x86_64.PhysAddr.initUnchecked(value & 0x000f_ffff_ffff_f000),
),
.pcid = x86_64.instructions.tlb.Pcid.init(@truncate(u12, value & 0xFFF)),
};
}
/// Write a new P4 table address into the CR3 register.
pub fn write(contents: Contents) void {
writeRaw(contents.toU64());
}
/// Write a new P4 table address into the CR3 register.
///
/// ## Safety
/// Changing the level 4 page table is unsafe, because it's possible to violate memory safety by
/// changing the page mapping.
/// [`Cr4Flags::PCID`] must be set before calling this method.
pub fn writePcid(pcidContents: PcidContents) void {
writeRaw(pcidContents.toU64());
}
fn writeRaw(value: u64) void {
asm volatile ("mov %[value], %%cr3"
:
: [value] "r" (value),
: "memory"
);
}
comptime {
std.testing.refAllDecls(@This());
}
};
/// Contains various control flags that enable architectural extensions, and indicate support for specific processor capabilities.
pub const Cr4 = packed struct {
/// Enables hardware-supported performance enhancements for software running in
/// virtual-8086 mode.
virtual_8086_mode_extensions: bool,
/// Enables support for protected-mode virtual interrupts.
protected_mode_virtual_interrupts: bool,
/// When set, only privilege-level 0 can execute the RDTSC or RDTSCP instructions.
timestamp_disable: bool,
/// Enables I/O breakpoint capability and enforces treatment of DR4 and DR5 x86_64 registers
/// as reserved.
debugging_extensions: bool,
/// Enables the use of 4MB physical frames; ignored in long mode.
page_size_extension: bool,
/// Enables physical address extensions and 2MB physical frames. Required in long mode.
physical_address_extension: bool,
/// Enables the machine-check exception mechanism.
machine_check_exception: bool,
/// Enables the global page feature, allowing some page translations to be marked as global (see `PageTableFlags.global`).
page_global: bool,
/// Allows software running at any privilege level to use the RDPMC instruction.
performance_monitor_counter: bool,
/// Enables the use of legacy SSE instructions; allows using FXSAVE/FXRSTOR for saving
/// processor state of 128-bit media instructions.
osfxsr: bool,
/// Enables the SIMD floating-point exception (#XF) for handling unmasked 256-bit and
/// 128-bit media floating-point errors.
osxmmexcpt_enable: bool,
/// Prevents the execution of the SGDT, SIDT, SLDT, SMSW, and STR instructions by
/// user-mode software.
user_mode_instruction_prevention: bool,
/// Enables 5-level paging on supported CPUs (Intel Only).
l5_paging: bool,
/// Enables VMX instructions (Intel Only).
virtual_machine_extensions: bool,
/// Enables SMX instructions (Intel Only).
safer_mode_extensions: bool,
/// Enables software running in 64-bit mode at any privilege level to read and write
/// the FS.base and GS.base hidden segment register state.
fsgsbase: bool,
z_reserved16: bool,
/// Enables process-context identifiers (PCIDs).
pcid: bool,
/// Enables extended processor state management instructions, including XGETBV and XSAVE.
osxsave: bool,
//// Enables the Key Locker feature (Intel Only).
///
/// This enables creation and use of opaque AES key handles; see the
/// [Intel Key Locker Specification](https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html)
/// for more information.
key_locker: bool,
/// Prevents the execution of instructions that reside in pages accessible by user-mode
/// software when the processor is in supervisor-mode.
supervisor_mode_execution_prevention: bool,
/// Enables restrictions for supervisor-mode software when reading data from user-mode
/// pages.
supervisor_mode_access_prevention: bool,
/// Enables protection keys for user-mode pages.
///
/// Also enables access to the PKRU register (via the `RDPKRU`/`WRPKRU` instructions) to set user-mode protection key access
/// controls.
protection_key_user: bool,
/// Enables Control-flow Enforcement Technology (CET)
///
/// This enables the shadow stack feature, ensuring return addresses read via `RET` and `IRET` have not been corrupted.
control_flow_enforcement: bool,
/// Enables protection keys for supervisor-mode pages (Intel Only).
///
/// Also enables the `IA32_PKRS` MSR to set supervisor-mode protection key access controls.
protection_key_supervisor: bool,
z_reserved25_31: u7,
z_reserved32_63: u32,
/// Read the current set of CR0 flags.
pub fn read() Cr4 {
return Cr4.fromU64(readRaw());
}
/// Read the current raw CR4 value.
fn readRaw() u64 {
return asm ("mov %%cr4, %[ret]"
: [ret] "=r" (-> u64),
);
}
/// Write CR4 flags.
///
/// Preserves the value of reserved fields.
pub fn write(self: Cr4) void {
writeRaw(self.toU64() | (readRaw() & ALL_RESERVED));
}
/// Write raw CR4 flags.
///
/// Does _not_ preserve any values, including reserved fields.
fn writeRaw(value: u64) void {
asm volatile ("mov %[val], %%cr4"
:
: [val] "r" (value),
: "memory"
);
}
const ALL_RESERVED: u64 = blk: {
var flags = std.mem.zeroes(Cr4);
flags.z_reserved16 = true;
flags.z_reserved25_31 = std.math.maxInt(u7);
flags.z_reserved32_63 = std.math.maxInt(u32);
break :blk @bitCast(u64, flags);
};
const ALL_NOT_RESERVED: u64 = ~ALL_RESERVED;
pub fn fromU64(value: u64) Cr4 {
return @bitCast(Cr4, value & ALL_NOT_RESERVED);
}
pub fn toU64(self: Cr4) u64 {
return @bitCast(u64, self) & ALL_NOT_RESERVED;
}
pub fn format(value: Cr4, comptime fmt: []const u8, options: std.fmt.FormatOptions, writer: anytype) !void {
_ = fmt;
return formatWithoutFields(
value,
options,
writer,
&.{ "z_reserved16", "z_reserved25_31", "z_reserved32_63" },
);
}
test {
try std.testing.expectEqual(@as(usize, 64), @bitSizeOf(Cr4));
try std.testing.expectEqual(@as(usize, 8), @sizeOf(Cr4));
}
comptime {
std.testing.refAllDecls(@This());
}
};
comptime {
std.testing.refAllDecls(@This());
} | src/registers/control.zig |
const std = @import("std");
const zalgebra = @import("zalgebra");
const physics = @import("didot-physics");
const Vec3 = zalgebra.Vec3;
const Quat = zalgebra.Quat;
const Allocator = std.mem.Allocator;
const rad = zalgebra.to_radians;
const graphics = @import("didot-graphics");
const objects = @import("didot-objects");
const Scene = objects.Scene;
const Input = graphics.Input;
const Transform = objects.Transform;
const Camera = objects.Camera;
const Query = objects.Query;
const ShaderProgram = graphics.ShaderProgram;
const GameObject = objects.GameObject;
const TextureAsset = graphics.TextureAsset;
const Material = graphics.Material;
const Skybox = objects.Skybox;
const PointLight = objects.PointLight;
pub const log = @import("didot-app").log;
const Systems = @import("didot-app").Systems;
const Application = @import("didot-app").Application;
var world: physics.World = undefined;
var scene: *Scene = undefined;
//pub const io_mode = .evented;
const App = blk: {
comptime var systems = Systems {};
systems.addSystem(update);
systems.addSystem(testSystem);
systems.addSystem(playerSystem);
systems.addSystem(cameraSystem);
systems.addSystem(physics.rigidbodySystem);
break :blk Application(systems);
};
const CameraController = struct { input: *Input, player: *GameObject };
fn cameraSystem(controller: *CameraController, transform: *Transform) !void {
const input = controller.input;
transform.position = controller.player.getComponent(Transform).?.position;
if (input.isMouseButtonDown(.Left)) {
input.setMouseInputMode(.Grabbed);
} else if (input.isMouseButtonDown(.Right) or input.isKeyDown(Input.KEY_ESCAPE)) {
input.setMouseInputMode(.Normal);
}
if (input.getMouseInputMode() == .Grabbed) {
const delta = 1.0; // TODO: put delta in Application struct
var euler = transform.rotation.extractRotation();
euler.x += (input.mouseDelta.x / 3.0) * delta;
euler.y -= (input.mouseDelta.y / 3.0) * delta;
if (euler.y > 89) euler.y = 89;
if (euler.y < -89) euler.y = -89;
transform.rotation = Quat.fromEulerAngle(euler);
}
}
const PlayerController = struct { input: *Input };
fn playerSystem(controller: *PlayerController, rb: *physics.Rigidbody) !void {
const input = controller.input;
const delta = 1.0; // TODO: put delta in Application struct
const speed: f32 = 40 / delta;
const camera = scene.findChild("Camera").?.getComponent(Transform).?;
var forward = camera.getForward();
const right = camera.getRight();
forward.y = 0;
if (input.isKeyDown(Input.KEY_W)) {
rb.addForce(forward.scale(speed));
}
if (input.isKeyDown(Input.KEY_S)) {
rb.addForce(forward.scale(-speed));
}
if (input.isKeyDown(Input.KEY_A)) {
rb.addForce(right.scale(-speed));
}
if (input.isKeyDown(Input.KEY_D)) {
rb.addForce(right.scale(speed));
}
if (input.isKeyDown(Input.KEY_SPACE)) {
rb.addForce(Vec3.new(0, speed, 0));
}
}
fn loadSkybox(allocator: *Allocator, camera: *Camera) !void {
const asset = &scene.assetManager;
try asset.put("textures/skybox", try TextureAsset.initCubemap(allocator, .{
.front = asset.get("textures/skybox/front.png").?,
.back = asset.get("textures/skybox/back.png").?,
.left = asset.get("textures/skybox/left.png").?,
.right = asset.get("textures/skybox/right.png").?,
.top = asset.get("textures/skybox/top.png").?,
.bottom = asset.get("textures/skybox/bottom.png").?,
}));
var skyboxShader = try ShaderProgram.createFromFile(allocator, "assets/shaders/skybox-vert.glsl", "assets/shaders/skybox-frag.glsl");
camera.skybox = Skybox {
.mesh = asset.get("Mesh/Cube").?,
.cubemap = asset.get("textures/skybox").?,
.shader = skyboxShader
};
}
fn testSystem(query: Query(.{})) !void {
var iter = query.iterator();
while (iter.next()) |go| {
_ = go;
}
}
fn update() !void {
world.update();
}
fn init(allocator: *Allocator, app: *App) !void {
world = physics.World.create();
world.setGravity(Vec3.new(0, -9.8, 0));
var shader = try ShaderProgram.createFromFile(allocator, "assets/shaders/vert.glsl", "assets/shaders/frag.glsl");
scene = app.scene;
const asset = &scene.assetManager;
try asset.autoLoad(allocator);
//try asset.comptimeAutoLoad(allocator);
var concreteMaterial = Material { .texture = asset.get("textures/grass.bmp") };
var player = try GameObject.createObject(allocator, null);
player.getComponent(Transform).?.* = .{
.position = Vec3.new(1.5, 3.5, -0.5),
.scale = Vec3.new(2, 2, 2)
};
player.name = "Player";
try player.addComponent(PlayerController { .input = &app.window.input });
try player.addComponent(physics.Rigidbody {
.world = &world,
.collider = .{
.Sphere = .{ .radius = 1.0 }
}
});
try scene.add(player);
var camera = try GameObject.createObject(allocator, null);
try camera.addComponent(Camera { .shader = shader });
camera.getComponent(Transform).?.* = .{
.position = Vec3.new(1.5, 3.5, -0.5),
.rotation = Quat.fromEulerAngle(Vec3.new(-120, -15, 0))
};
camera.name = "Camera";
try camera.addComponent(CameraController {
.input = &app.window.input,
.player = scene.findChild("Player").?
});
try scene.add(camera);
try loadSkybox(allocator, camera.getComponent(Camera).?);
var cube = try GameObject.createObject(allocator, asset.get("Mesh/Cube"));
cube.getComponent(Transform).?.* = .{
.position = Vec3.new(5, -0.75, -10),
.scale = Vec3.new(250, 0.1, 250)
};
cube.material = concreteMaterial;
try cube.addComponent(physics.Rigidbody {
.world=&world,
.kinematic=.Kinematic,
.collider = .{
.Box = .{}
},
.material = .{
.friction = 10
}
});
try scene.add(cube);
var i: usize = 0;
var rand = std.rand.DefaultPrng.init(145115126);
var random = rand.random;
while (i < 50) : (i += 1) {
var domino = try GameObject.createObject(allocator, asset.get("Mesh/Cube"));
domino.getComponent(Transform).?.* = .{
.position = Vec3.new(-1.2, 0.75, -3 - (1.3 * @intToFloat(f32, i))),
.scale = Vec3.new(1, 2, 0.1)
};
domino.material.ambient = Vec3.new(random.float(f32) * 0.1, random.float(f32) * 0.1, random.float(f32) * 0.1);
domino.material.diffuse = Vec3.new(random.float(f32), random.float(f32), random.float(f32));
try domino.addComponent(physics.Rigidbody { .world = &world,
.collider = .{ .Box = .{} }});
try scene.add(domino);
}
var light = try GameObject.createObject(allocator, asset.get("Mesh/Cube"));
light.getComponent(Transform).?.position = Vec3.new(1, 5, -5);
light.material.ambient = Vec3.one();
try light.addComponent(PointLight {});
try scene.add(light);
}
var gp: std.heap.GeneralPurposeAllocator(.{}) = .{};
pub fn main() !void {
defer _ = gp.deinit();
const gpa_allocator = &gp.allocator;
const allocator = gpa_allocator;
var app = App {
.title = "Test Room",
.initFn = init
};
try app.run(allocator, try Scene.create(allocator, null));
} | examples/test-portal/example-scene.zig |
usingnamespace @import("psptypes.zig");
pub const SceMp3InitArg = extern struct {
mp3StreamStart: SceUInt32,
unk1: SceUInt32,
mp3StreamEnd: SceUInt32,
unk2: SceUInt32,
mp3Buf: ?*SceVoid,
mp3BufSize: SceInt32,
pcmBuf: ?*SceVoid,
pcmBufSize: SceInt32,
};
// sceMp3ReserveMp3Handle
//
// @param args - Pointer to SceMp3InitArg structure
//
// @return sceMp3 handle on success, < 0 on error.
pub extern fn sceMp3ReserveMp3Handle(args: *SceMp3InitArg) SceInt32;
pub fn mp3ReserveMp3Handle(args: *SceMp3InitArg) !SceInt32 {
var res = sceMp3ReserveMp3Handle(args);
if (res < 0) {
return error.Unexpected;
}
return res;
}
// sceMp3ReleaseMp3Handle
//
// @param handle - sceMp3 handle
//
// @return 0 if success, < 0 on error.
pub extern fn sceMp3ReleaseMp3Handle(handle: SceInt32) SceInt32;
pub fn mp3ReleaseMp3Handle(handle: SceInt32) !void {
var res = sceMp3ReleaseMp3Handle(handle);
if (res < 0) {
return error.Unexpected;
}
}
// sceMp3InitResource
//
// @return 0 if success, < 0 on error.
pub extern fn sceMp3InitResource() SceInt32;
pub fn mp3InitResource() !void {
var res = sceMp3InitResource();
if (res < 0) {
return error.Unexpected;
}
}
// sceMp3TermResource
//
// @return 0 if success, < 0 on error.
pub extern fn sceMp3TermResource() SceInt32;
pub fn mp3TermResource() !void {
var res = sceMp3TermResource();
if (res < 0) {
return error.Unexpected;
}
}
// sceMp3Init
//
// @param handle - sceMp3 handle
//
// @return 0 if success, < 0 on error.
pub extern fn sceMp3Init(handle: SceInt32) SceInt32;
pub fn mp3Init(handle: SceInt32) !void {
var res = sceMp3Init(handle);
if (res < 0) {
return error.Unexpected;
}
}
// sceMp3Decode
//
// @param handle - sceMp3 handle
// @param dst - Pointer to destination pcm samples buffer
//
// @return number of bytes in decoded pcm buffer, < 0 on error.
pub extern fn sceMp3Decode(handle: SceInt32, dst: *[]SceShort16) SceInt32;
pub fn mp3Decode(handle: SceInt32, dst: *[]SceShort16) !i32 {
var res = sceMp3Decode(handle, dst);
if (res < 0) {
return error.Unexpected;
}
return res;
}
// sceMp3GetInfoToAddStreamData
//
// @param handle - sceMp3 handle
// @param dst - Pointer to stream data buffer
// @param towrite - Space remaining in stream data buffer
// @param srcpos - Position in source stream to start reading from
//
// @return 0 if success, < 0 on error.
pub extern fn sceMp3GetInfoToAddStreamData(handle: SceInt32, dst: *[]SceUChar8, towrite: *SceInt32, srcpos: *SceInt32) SceInt32;
pub fn mp3GetInfoToAddStreamData(handle: SceInt32, dst: *[]SceUChar8, towrite: *SceInt32, srcpos: *SceInt32) !void {
var res = sceMp3GetInfoToAddStreamData(handle, dst, towrite, srcpos);
if (res < 0) {
return error.Unexpected;
}
}
// sceMp3NotifyAddStreamData
//
// @param handle - sceMp3 handle
// @param size - number of bytes added to the stream data buffer
//
// @return 0 if success, < 0 on error.
pub extern fn sceMp3NotifyAddStreamData(handle: SceInt32, size: SceInt32) SceInt32;
pub fn mp3NotifyAddStreamData(handle: SceInt32, size: SceInt32) !void {
var res = sceMp3NotifyAddStreamData(handle, size);
if (res < 0) {
return error.Unexpected;
}
}
// sceMp3CheckStreamDataNeeded
//
// @param handle - sceMp3 handle
//
// @return 1 if more stream data is needed, < 0 on error.
pub extern fn sceMp3CheckStreamDataNeeded(handle: SceInt32) SceInt32;
// sceMp3SetLoopNum
//
// @param handle - sceMp3 handle
// @param loop - Number of loops
//
// @return 0 if success, < 0 on error.
pub extern fn sceMp3SetLoopNum(handle: SceInt32, loop: SceInt32) SceInt32;
pub fn mp3SetLoopNum(handle: SceInt32, loop: SceInt32) !void {
var res = sceMp3SetLoopNum(handle, loop);
if (res < 0) {
return error.Unexpected;
}
}
// sceMp3GetLoopNum
//
// @param handle - sceMp3 handle
//
// @return Number of loops
pub extern fn sceMp3GetLoopNum(handle: SceInt32) SceInt32;
// sceMp3GetSumDecodedSample
//
// @param handle - sceMp3 handle
//
// @return Number of decoded samples
pub extern fn sceMp3GetSumDecodedSample(handle: SceInt32) SceInt32;
// sceMp3GetMaxOutputSample
//
// @param handle - sceMp3 handle
//
// @return Number of max samples to output
pub extern fn sceMp3GetMaxOutputSample(handle: SceInt32) SceInt32;
// sceMp3GetSamplingRate
//
// @param handle - sceMp3 handle
//
// @return Sampling rate of the mp3
pub extern fn sceMp3GetSamplingRate(handle: SceInt32) SceInt32;
// sceMp3GetBitRate
//
// @param handle - sceMp3 handle
//
// @return Bitrate of the mp3
pub extern fn sceMp3GetBitRate(handle: SceInt32) SceInt32;
// sceMp3GetMp3ChannelNum
//
// @param handle - sceMp3 handle
//
// @return Number of channels of the mp3
pub extern fn sceMp3GetMp3ChannelNum(handle: SceInt32) SceInt32;
// sceMp3ResetPlayPosition
//
// @param handle - sceMp3 handle
//
// @return < 0 on error
pub extern fn sceMp3ResetPlayPosition(handle: SceInt32) SceInt32;
pub fn mp3ResetPlayPosition(handle: SceInt32) !void {
var res = sceMp3ResetPlayPosition(handle);
if (res < 0) {
return error.Unexpected;
}
} | src/psp/sdk/pspmp3.zig |
const std = @import("std");
const Allocator = std.mem.Allocator;
const utils = @import("utils.zig");
const ConsoleStyle = utils.ConsoleStyle;
name: []const u8,
is_private: bool,
is_fork: bool,
is_archived: bool,
is_template: bool,
description: []const u8,
repository: []const u8,
language: []const u8,
size: u32,
stars: u32,
watches: u32,
forks: u32,
license: []const u8,
created: []const u8,
modified: []const u8,
branch: []const u8,
const Info = @This();
pub fn free(self: *Info, allocator: Allocator) void {
allocator.free(self.name);
allocator.free(self.description);
allocator.free(self.repository);
allocator.free(self.language);
allocator.free(self.license);
allocator.free(self.created);
allocator.free(self.modified);
allocator.free(self.branch);
}
pub fn print(info: *Info, file: std.fs.File) !void {
const rand_engine = std.rand.DefaultPrng.init(@intCast(u64, std.time.milliTimestamp())).random();
const choice = rand_engine.enumValue(utils.Color);
const writer = file.writer();
const color = ConsoleStyle.init(file);
{
const id = std.mem.indexOf(u8, info.name, "/").?;
try color.setColor(choice);
try writer.print(" {s}", .{info.name[0..id]});
try color.reset();
try writer.writeByte('/');
try color.setColor(choice);
try writer.print("{s} ", .{info.name[id + 1 ..]});
if (info.is_fork) try writer.writeAll("🔗 ");
if (info.is_private) try writer.writeAll("🔒 ");
if (info.is_template) try writer.writeAll("🗒; ");
if (info.is_archived) try writer.writeAll("📦 ");
try writer.writeByte('\n');
try color.reset();
try writer.writeAll(" ");
try writer.writeByteNTimes('~', info.name.len);
try writer.writeByte('\n');
}
{
var x: usize = 0;
while (x < info.description.len) {
const end = blk: {
const amount = 60;
if (x + amount >= info.description.len) {
break :blk info.description.len - x;
} else {
break :blk amount;
}
};
const str = std.mem.trimLeft(u8, info.description[x .. x + end], " ");
try writer.print("{s}\n", .{str});
x += end;
}
try writer.writeByte('\n');
}
const fields = .{
"repository",
"license",
"branch",
"created",
"modified",
"language",
"size",
"stars",
"watches",
"forks",
};
inline for (fields) |f| {
const info_fields = std.meta.fields(Info);
const field_id: usize = std.meta.fieldIndex(Info, f).?;
const field = info_fields[field_id];
const data = @field(info, field.name);
if (field.field_type == []const u8) {
if (!std.mem.eql(u8, data, "")) {
try writer.writeByte('-');
try color.setColor(choice);
try writer.print(" {s}", .{field.name});
try color.reset();
try writer.print(": {s}\n", .{data});
}
} else {
if (data != 0) {
try writer.writeByte('-');
try color.setColor(choice);
try writer.print(" {s}", .{field.name});
try color.reset();
try writer.print(": {}\n", .{data});
}
}
}
try writer.writeByte('\n');
} | src/Info.zig |
pub fn Register(comptime R: type) type {
return RegisterRW(R, R);
}
pub fn RegisterRW(comptime Read: type, comptime Write: type) type {
return struct {
raw_ptr: *volatile u32,
const Self = @This();
pub fn init(address: usize) Self {
return Self{ .raw_ptr = @intToPtr(*volatile u32, address) };
}
pub fn initRange(address: usize, comptime dim_increment: usize, comptime num_registers: usize) [num_registers]Self {
var registers: [num_registers]Self = undefined;
var i: usize = 0;
while (i < num_registers) : (i += 1) {
registers[i] = Self.init(address + (i * dim_increment));
}
return registers;
}
pub fn read(self: Self) Read {
return @bitCast(Read, self.raw_ptr.*);
}
pub fn write(self: Self, value: Write) void {
var temp = value;
self.raw_ptr.* = @ptrCast(*u32, @alignCast(4, &temp)).*;
}
pub fn modify(self: Self, new_value: anytype) void {
if (Read != Write) {
@compileError("Can't modify because read and write types for this register aren't the same.");
}
var old_value = self.read();
const info = @typeInfo(@TypeOf(new_value));
inline for (info.Struct.fields) |field| {
@field(old_value, field.name) = @field(new_value, field.name);
}
self.write(old_value);
}
pub fn read_raw(self: Self) u32 {
return self.raw_ptr.*;
}
pub fn write_raw(self: Self, value: u32) void {
self.raw_ptr.* = value;
}
pub fn default_read_value(self: Self) Read {
_ = self;
return Read{};
}
pub fn default_write_value(self: Self) Write {
_ = self;
return Write{};
}
};
}
pub const device_name = "RP2040";
pub const device_revision = "0.1";
pub const device_description = "unknown";
pub const cpu = struct {
pub const name = "CM0PLUS";
pub const revision = "r0p1";
pub const endian = "little";
pub const mpu_present = true;
pub const fpu_present = true;
pub const vendor_systick_config = false;
pub const nvic_prio_bits = 2;
};
/// QSPI flash execute-in-place block
pub const XIP_CTRL = struct {
const base_address = 0x14000000;
/// STREAM_FIFO
const STREAM_FIFO_val = packed struct {
STREAM_FIFO_0: u8 = 0,
STREAM_FIFO_1: u8 = 0,
STREAM_FIFO_2: u8 = 0,
STREAM_FIFO_3: u8 = 0,
};
/// FIFO stream data\n
pub const STREAM_FIFO = Register(STREAM_FIFO_val).init(base_address + 0x1c);
/// STREAM_CTR
const STREAM_CTR_val = packed struct {
/// STREAM_CTR [0:21]
/// Write a nonzero value to start a streaming read. This will then\n
STREAM_CTR: u22 = 0,
/// unused [22:31]
_unused22: u2 = 0,
_unused24: u8 = 0,
};
/// FIFO stream control
pub const STREAM_CTR = Register(STREAM_CTR_val).init(base_address + 0x18);
/// STREAM_ADDR
const STREAM_ADDR_val = packed struct {
/// unused [0:1]
_unused0: u2 = 0,
/// STREAM_ADDR [2:31]
/// The address of the next word to be streamed from flash to the streaming FIFO.\n
STREAM_ADDR: u30 = 0,
};
/// FIFO stream address
pub const STREAM_ADDR = Register(STREAM_ADDR_val).init(base_address + 0x14);
/// CTR_ACC
const CTR_ACC_val = packed struct {
CTR_ACC_0: u8 = 0,
CTR_ACC_1: u8 = 0,
CTR_ACC_2: u8 = 0,
CTR_ACC_3: u8 = 0,
};
/// Cache Access counter\n
pub const CTR_ACC = Register(CTR_ACC_val).init(base_address + 0x10);
/// CTR_HIT
const CTR_HIT_val = packed struct {
CTR_HIT_0: u8 = 0,
CTR_HIT_1: u8 = 0,
CTR_HIT_2: u8 = 0,
CTR_HIT_3: u8 = 0,
};
/// Cache Hit counter\n
pub const CTR_HIT = Register(CTR_HIT_val).init(base_address + 0xc);
/// STAT
const STAT_val = packed struct {
/// FLUSH_READY [0:0]
/// Reads as 0 while a cache flush is in progress, and 1 otherwise.\n
FLUSH_READY: u1 = 0,
/// FIFO_EMPTY [1:1]
/// When 1, indicates the XIP streaming FIFO is completely empty.
FIFO_EMPTY: u1 = 1,
/// FIFO_FULL [2:2]
/// When 1, indicates the XIP streaming FIFO is completely full.\n
FIFO_FULL: u1 = 0,
/// unused [3:31]
_unused3: u5 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Cache Status
pub const STAT = Register(STAT_val).init(base_address + 0x8);
/// FLUSH
const FLUSH_val = packed struct {
/// FLUSH [0:0]
/// Write 1 to flush the cache. This clears the tag memory, but\n
FLUSH: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Cache Flush control
pub const FLUSH = Register(FLUSH_val).init(base_address + 0x4);
/// CTRL
const CTRL_val = packed struct {
/// EN [0:0]
/// When 1, enable the cache. When the cache is disabled, all XIP accesses\n
EN: u1 = 1,
/// ERR_BADWRITE [1:1]
/// When 1, writes to any alias other than 0x0 (caching, allocating)\n
ERR_BADWRITE: u1 = 1,
/// unused [2:2]
_unused2: u1 = 0,
/// POWER_DOWN [3:3]
/// When 1, the cache memories are powered down. They retain state,\n
POWER_DOWN: u1 = 0,
/// unused [4:31]
_unused4: u4 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Cache control
pub const CTRL = Register(CTRL_val).init(base_address + 0x0);
};
/// DW_apb_ssi has the following features:\n
pub const XIP_SSI = struct {
const base_address = 0x18000000;
/// TXD_DRIVE_EDGE
const TXD_DRIVE_EDGE_val = packed struct {
/// TDE [0:7]
/// TXD drive edge
TDE: u8 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// TX drive edge
pub const TXD_DRIVE_EDGE = Register(TXD_DRIVE_EDGE_val).init(base_address + 0xf8);
/// SPI_CTRLR0
const SPI_CTRLR0_val = packed struct {
/// TRANS_TYPE [0:1]
/// Address and instruction transfer format
TRANS_TYPE: u2 = 0,
/// ADDR_L [2:5]
/// Address length (0b-60b in 4b increments)
ADDR_L: u4 = 0,
/// unused [6:7]
_unused6: u2 = 0,
/// INST_L [8:9]
/// Instruction length (0/4/8/16b)
INST_L: u2 = 0,
/// unused [10:10]
_unused10: u1 = 0,
/// WAIT_CYCLES [11:15]
/// Wait cycles between control frame transmit and data reception (in SCLK cycles)
WAIT_CYCLES: u5 = 0,
/// SPI_DDR_EN [16:16]
/// SPI DDR transfer enable
SPI_DDR_EN: u1 = 0,
/// INST_DDR_EN [17:17]
/// Instruction DDR transfer enable
INST_DDR_EN: u1 = 0,
/// SPI_RXDS_EN [18:18]
/// Read data strobe enable
SPI_RXDS_EN: u1 = 0,
/// unused [19:23]
_unused19: u5 = 0,
/// XIP_CMD [24:31]
/// SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit)
XIP_CMD: u8 = 3,
};
/// SPI control
pub const SPI_CTRLR0 = Register(SPI_CTRLR0_val).init(base_address + 0xf4);
/// RX_SAMPLE_DLY
const RX_SAMPLE_DLY_val = packed struct {
/// RSD [0:7]
/// RXD sample delay (in SCLK cycles)
RSD: u8 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// RX sample delay
pub const RX_SAMPLE_DLY = Register(RX_SAMPLE_DLY_val).init(base_address + 0xf0);
/// DR0
const DR0_val = packed struct {
/// DR [0:31]
/// First data register of 36
DR: u32 = 0,
};
/// Data Register 0 (of 36)
pub const DR0 = Register(DR0_val).init(base_address + 0x60);
/// SSI_VERSION_ID
const SSI_VERSION_ID_val = packed struct {
/// SSI_COMP_VERSION [0:31]
/// SNPS component version (format X.YY)
SSI_COMP_VERSION: u32 = 875573546,
};
/// Version ID
pub const SSI_VERSION_ID = Register(SSI_VERSION_ID_val).init(base_address + 0x5c);
/// IDR
const IDR_val = packed struct {
/// IDCODE [0:31]
/// Peripheral dentification code
IDCODE: u32 = 1364414537,
};
/// Identification register
pub const IDR = Register(IDR_val).init(base_address + 0x58);
/// DMARDLR
const DMARDLR_val = packed struct {
/// DMARDL [0:7]
/// Receive data watermark level (DMARDLR+1)
DMARDL: u8 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// DMA RX data level
pub const DMARDLR = Register(DMARDLR_val).init(base_address + 0x54);
/// DMATDLR
const DMATDLR_val = packed struct {
/// DMATDL [0:7]
/// Transmit data watermark level
DMATDL: u8 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// DMA TX data level
pub const DMATDLR = Register(DMATDLR_val).init(base_address + 0x50);
/// DMACR
const DMACR_val = packed struct {
/// RDMAE [0:0]
/// Receive DMA enable
RDMAE: u1 = 0,
/// TDMAE [1:1]
/// Transmit DMA enable
TDMAE: u1 = 0,
/// unused [2:31]
_unused2: u6 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// DMA control
pub const DMACR = Register(DMACR_val).init(base_address + 0x4c);
/// ICR
const ICR_val = packed struct {
/// ICR [0:0]
/// Clear-on-read all active interrupts
ICR: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt clear
pub const ICR = Register(ICR_val).init(base_address + 0x48);
/// MSTICR
const MSTICR_val = packed struct {
/// MSTICR [0:0]
/// Clear-on-read multi-master contention interrupt
MSTICR: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Multi-master interrupt clear
pub const MSTICR = Register(MSTICR_val).init(base_address + 0x44);
/// RXUICR
const RXUICR_val = packed struct {
/// RXUICR [0:0]
/// Clear-on-read receive FIFO underflow interrupt
RXUICR: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// RX FIFO underflow interrupt clear
pub const RXUICR = Register(RXUICR_val).init(base_address + 0x40);
/// RXOICR
const RXOICR_val = packed struct {
/// RXOICR [0:0]
/// Clear-on-read receive FIFO overflow interrupt
RXOICR: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// RX FIFO overflow interrupt clear
pub const RXOICR = Register(RXOICR_val).init(base_address + 0x3c);
/// TXOICR
const TXOICR_val = packed struct {
/// TXOICR [0:0]
/// Clear-on-read transmit FIFO overflow interrupt
TXOICR: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// TX FIFO overflow interrupt clear
pub const TXOICR = Register(TXOICR_val).init(base_address + 0x38);
/// RISR
const RISR_val = packed struct {
/// TXEIR [0:0]
/// Transmit FIFO empty raw interrupt status
TXEIR: u1 = 0,
/// TXOIR [1:1]
/// Transmit FIFO overflow raw interrupt status
TXOIR: u1 = 0,
/// RXUIR [2:2]
/// Receive FIFO underflow raw interrupt status
RXUIR: u1 = 0,
/// RXOIR [3:3]
/// Receive FIFO overflow raw interrupt status
RXOIR: u1 = 0,
/// RXFIR [4:4]
/// Receive FIFO full raw interrupt status
RXFIR: u1 = 0,
/// MSTIR [5:5]
/// Multi-master contention raw interrupt status
MSTIR: u1 = 0,
/// unused [6:31]
_unused6: u2 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Raw interrupt status
pub const RISR = Register(RISR_val).init(base_address + 0x34);
/// ISR
const ISR_val = packed struct {
/// TXEIS [0:0]
/// Transmit FIFO empty interrupt status
TXEIS: u1 = 0,
/// TXOIS [1:1]
/// Transmit FIFO overflow interrupt status
TXOIS: u1 = 0,
/// RXUIS [2:2]
/// Receive FIFO underflow interrupt status
RXUIS: u1 = 0,
/// RXOIS [3:3]
/// Receive FIFO overflow interrupt status
RXOIS: u1 = 0,
/// RXFIS [4:4]
/// Receive FIFO full interrupt status
RXFIS: u1 = 0,
/// MSTIS [5:5]
/// Multi-master contention interrupt status
MSTIS: u1 = 0,
/// unused [6:31]
_unused6: u2 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt status
pub const ISR = Register(ISR_val).init(base_address + 0x30);
/// IMR
const IMR_val = packed struct {
/// TXEIM [0:0]
/// Transmit FIFO empty interrupt mask
TXEIM: u1 = 0,
/// TXOIM [1:1]
/// Transmit FIFO overflow interrupt mask
TXOIM: u1 = 0,
/// RXUIM [2:2]
/// Receive FIFO underflow interrupt mask
RXUIM: u1 = 0,
/// RXOIM [3:3]
/// Receive FIFO overflow interrupt mask
RXOIM: u1 = 0,
/// RXFIM [4:4]
/// Receive FIFO full interrupt mask
RXFIM: u1 = 0,
/// MSTIM [5:5]
/// Multi-master contention interrupt mask
MSTIM: u1 = 0,
/// unused [6:31]
_unused6: u2 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt mask
pub const IMR = Register(IMR_val).init(base_address + 0x2c);
/// SR
const SR_val = packed struct {
/// BUSY [0:0]
/// SSI busy flag
BUSY: u1 = 0,
/// TFNF [1:1]
/// Transmit FIFO not full
TFNF: u1 = 0,
/// TFE [2:2]
/// Transmit FIFO empty
TFE: u1 = 0,
/// RFNE [3:3]
/// Receive FIFO not empty
RFNE: u1 = 0,
/// RFF [4:4]
/// Receive FIFO full
RFF: u1 = 0,
/// TXE [5:5]
/// Transmission error
TXE: u1 = 0,
/// DCOL [6:6]
/// Data collision error
DCOL: u1 = 0,
/// unused [7:31]
_unused7: u1 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Status register
pub const SR = Register(SR_val).init(base_address + 0x28);
/// RXFLR
const RXFLR_val = packed struct {
/// RXTFL [0:7]
/// Receive FIFO level
RXTFL: u8 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// RX FIFO level
pub const RXFLR = Register(RXFLR_val).init(base_address + 0x24);
/// TXFLR
const TXFLR_val = packed struct {
/// TFTFL [0:7]
/// Transmit FIFO level
TFTFL: u8 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// TX FIFO level
pub const TXFLR = Register(TXFLR_val).init(base_address + 0x20);
/// RXFTLR
const RXFTLR_val = packed struct {
/// RFT [0:7]
/// Receive FIFO threshold
RFT: u8 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// RX FIFO threshold level
pub const RXFTLR = Register(RXFTLR_val).init(base_address + 0x1c);
/// TXFTLR
const TXFTLR_val = packed struct {
/// TFT [0:7]
/// Transmit FIFO threshold
TFT: u8 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// TX FIFO threshold level
pub const TXFTLR = Register(TXFTLR_val).init(base_address + 0x18);
/// BAUDR
const BAUDR_val = packed struct {
/// SCKDV [0:15]
/// SSI clock divider
SCKDV: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Baud rate
pub const BAUDR = Register(BAUDR_val).init(base_address + 0x14);
/// SER
const SER_val = packed struct {
/// SER [0:0]
/// For each bit:\n
SER: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Slave enable
pub const SER = Register(SER_val).init(base_address + 0x10);
/// MWCR
const MWCR_val = packed struct {
/// MWMOD [0:0]
/// Microwire transfer mode
MWMOD: u1 = 0,
/// MDD [1:1]
/// Microwire control
MDD: u1 = 0,
/// MHS [2:2]
/// Microwire handshaking
MHS: u1 = 0,
/// unused [3:31]
_unused3: u5 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Microwire Control
pub const MWCR = Register(MWCR_val).init(base_address + 0xc);
/// SSIENR
const SSIENR_val = packed struct {
/// SSI_EN [0:0]
/// SSI enable
SSI_EN: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// SSI Enable
pub const SSIENR = Register(SSIENR_val).init(base_address + 0x8);
/// CTRLR1
const CTRLR1_val = packed struct {
/// NDF [0:15]
/// Number of data frames
NDF: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Master Control register 1
pub const CTRLR1 = Register(CTRLR1_val).init(base_address + 0x4);
/// CTRLR0
const CTRLR0_val = packed struct {
/// DFS [0:3]
/// Data frame size
DFS: u4 = 0,
/// FRF [4:5]
/// Frame format
FRF: u2 = 0,
/// SCPH [6:6]
/// Serial clock phase
SCPH: u1 = 0,
/// SCPOL [7:7]
/// Serial clock polarity
SCPOL: u1 = 0,
/// TMOD [8:9]
/// Transfer mode
TMOD: u2 = 0,
/// SLV_OE [10:10]
/// Slave output enable
SLV_OE: u1 = 0,
/// SRL [11:11]
/// Shift register loop (test mode)
SRL: u1 = 0,
/// CFS [12:15]
/// Control frame size\n
CFS: u4 = 0,
/// DFS_32 [16:20]
/// Data frame size in 32b transfer mode\n
DFS_32: u5 = 0,
/// SPI_FRF [21:22]
/// SPI frame format
SPI_FRF: u2 = 0,
/// unused [23:23]
_unused23: u1 = 0,
/// SSTE [24:24]
/// Slave select toggle enable
SSTE: u1 = 0,
/// unused [25:31]
_unused25: u7 = 0,
};
/// Control register 0
pub const CTRLR0 = Register(CTRLR0_val).init(base_address + 0x0);
};
/// No description
pub const SYSINFO = struct {
const base_address = 0x40000000;
/// GITREF_RP2040
const GITREF_RP2040_val = packed struct {
GITREF_RP2040_0: u8 = 0,
GITREF_RP2040_1: u8 = 0,
GITREF_RP2040_2: u8 = 0,
GITREF_RP2040_3: u8 = 0,
};
/// Git hash of the chip source. Used to identify chip version.
pub const GITREF_RP2040 = Register(GITREF_RP2040_val).init(base_address + 0x40);
/// PLATFORM
const PLATFORM_val = packed struct {
/// FPGA [0:0]
/// No description
FPGA: u1 = 0,
/// ASIC [1:1]
/// No description
ASIC: u1 = 0,
/// unused [2:31]
_unused2: u6 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Platform register. Allows software to know what environment it is running in.
pub const PLATFORM = Register(PLATFORM_val).init(base_address + 0x4);
/// CHIP_ID
const CHIP_ID_val = packed struct {
/// MANUFACTURER [0:11]
/// No description
MANUFACTURER: u12 = 0,
/// PART [12:27]
/// No description
PART: u16 = 0,
/// REVISION [28:31]
/// No description
REVISION: u4 = 0,
};
/// JEDEC JEP-106 compliant chip identifier.
pub const CHIP_ID = Register(CHIP_ID_val).init(base_address + 0x0);
};
/// Register block for various chip control signals
pub const SYSCFG = struct {
const base_address = 0x40004000;
/// MEMPOWERDOWN
const MEMPOWERDOWN_val = packed struct {
/// SRAM0 [0:0]
/// No description
SRAM0: u1 = 0,
/// SRAM1 [1:1]
/// No description
SRAM1: u1 = 0,
/// SRAM2 [2:2]
/// No description
SRAM2: u1 = 0,
/// SRAM3 [3:3]
/// No description
SRAM3: u1 = 0,
/// SRAM4 [4:4]
/// No description
SRAM4: u1 = 0,
/// SRAM5 [5:5]
/// No description
SRAM5: u1 = 0,
/// USB [6:6]
/// No description
USB: u1 = 0,
/// ROM [7:7]
/// No description
ROM: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Control power downs to memories. Set high to power down memories.\n
pub const MEMPOWERDOWN = Register(MEMPOWERDOWN_val).init(base_address + 0x18);
/// DBGFORCE
const DBGFORCE_val = packed struct {
/// PROC0_SWDO [0:0]
/// Observe the value of processor 0 SWDIO output.
PROC0_SWDO: u1 = 0,
/// PROC0_SWDI [1:1]
/// Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set
PROC0_SWDI: u1 = 1,
/// PROC0_SWCLK [2:2]
/// Directly drive processor 0 SWCLK, if PROC0_ATTACH is set
PROC0_SWCLK: u1 = 1,
/// PROC0_ATTACH [3:3]
/// Attach processor 0 debug port to syscfg controls, and disconnect it from external SWD pads.
PROC0_ATTACH: u1 = 0,
/// PROC1_SWDO [4:4]
/// Observe the value of processor 1 SWDIO output.
PROC1_SWDO: u1 = 0,
/// PROC1_SWDI [5:5]
/// Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set
PROC1_SWDI: u1 = 1,
/// PROC1_SWCLK [6:6]
/// Directly drive processor 1 SWCLK, if PROC1_ATTACH is set
PROC1_SWCLK: u1 = 1,
/// PROC1_ATTACH [7:7]
/// Attach processor 1 debug port to syscfg controls, and disconnect it from external SWD pads.
PROC1_ATTACH: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Directly control the SWD debug port of either processor
pub const DBGFORCE = Register(DBGFORCE_val).init(base_address + 0x14);
/// PROC_IN_SYNC_BYPASS_HI
const PROC_IN_SYNC_BYPASS_HI_val = packed struct {
/// PROC_IN_SYNC_BYPASS_HI [0:5]
/// No description
PROC_IN_SYNC_BYPASS_HI: u6 = 0,
/// unused [6:31]
_unused6: u2 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// For each bit, if 1, bypass the input synchronizer between that GPIO\n
pub const PROC_IN_SYNC_BYPASS_HI = Register(PROC_IN_SYNC_BYPASS_HI_val).init(base_address + 0x10);
/// PROC_IN_SYNC_BYPASS
const PROC_IN_SYNC_BYPASS_val = packed struct {
/// PROC_IN_SYNC_BYPASS [0:29]
/// No description
PROC_IN_SYNC_BYPASS: u30 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// For each bit, if 1, bypass the input synchronizer between that GPIO\n
pub const PROC_IN_SYNC_BYPASS = Register(PROC_IN_SYNC_BYPASS_val).init(base_address + 0xc);
/// PROC_CONFIG
const PROC_CONFIG_val = packed struct {
/// PROC0_HALTED [0:0]
/// Indication that proc0 has halted
PROC0_HALTED: u1 = 0,
/// PROC1_HALTED [1:1]
/// Indication that proc1 has halted
PROC1_HALTED: u1 = 0,
/// unused [2:23]
_unused2: u6 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
/// PROC0_DAP_INSTID [24:27]
/// Configure proc0 DAP instance ID.\n
PROC0_DAP_INSTID: u4 = 0,
/// PROC1_DAP_INSTID [28:31]
/// Configure proc1 DAP instance ID.\n
PROC1_DAP_INSTID: u4 = 1,
};
/// Configuration for processors
pub const PROC_CONFIG = Register(PROC_CONFIG_val).init(base_address + 0x8);
/// PROC1_NMI_MASK
const PROC1_NMI_MASK_val = packed struct {
PROC1_NMI_MASK_0: u8 = 0,
PROC1_NMI_MASK_1: u8 = 0,
PROC1_NMI_MASK_2: u8 = 0,
PROC1_NMI_MASK_3: u8 = 0,
};
/// Processor core 1 NMI source mask\n
pub const PROC1_NMI_MASK = Register(PROC1_NMI_MASK_val).init(base_address + 0x4);
/// PROC0_NMI_MASK
const PROC0_NMI_MASK_val = packed struct {
PROC0_NMI_MASK_0: u8 = 0,
PROC0_NMI_MASK_1: u8 = 0,
PROC0_NMI_MASK_2: u8 = 0,
PROC0_NMI_MASK_3: u8 = 0,
};
/// Processor core 0 NMI source mask\n
pub const PROC0_NMI_MASK = Register(PROC0_NMI_MASK_val).init(base_address + 0x0);
};
/// No description
pub const CLOCKS = struct {
const base_address = 0x40008000;
/// INTS
const INTS_val = packed struct {
/// CLK_SYS_RESUS [0:0]
/// No description
CLK_SYS_RESUS: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt status after masking & forcing
pub const INTS = Register(INTS_val).init(base_address + 0xc4);
/// INTF
const INTF_val = packed struct {
/// CLK_SYS_RESUS [0:0]
/// No description
CLK_SYS_RESUS: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt Force
pub const INTF = Register(INTF_val).init(base_address + 0xc0);
/// INTE
const INTE_val = packed struct {
/// CLK_SYS_RESUS [0:0]
/// No description
CLK_SYS_RESUS: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt Enable
pub const INTE = Register(INTE_val).init(base_address + 0xbc);
/// INTR
const INTR_val = packed struct {
/// CLK_SYS_RESUS [0:0]
/// No description
CLK_SYS_RESUS: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Raw Interrupts
pub const INTR = Register(INTR_val).init(base_address + 0xb8);
/// ENABLED1
const ENABLED1_val = packed struct {
/// clk_sys_sram4 [0:0]
/// No description
clk_sys_sram4: u1 = 0,
/// clk_sys_sram5 [1:1]
/// No description
clk_sys_sram5: u1 = 0,
/// clk_sys_syscfg [2:2]
/// No description
clk_sys_syscfg: u1 = 0,
/// clk_sys_sysinfo [3:3]
/// No description
clk_sys_sysinfo: u1 = 0,
/// clk_sys_tbman [4:4]
/// No description
clk_sys_tbman: u1 = 0,
/// clk_sys_timer [5:5]
/// No description
clk_sys_timer: u1 = 0,
/// clk_peri_uart0 [6:6]
/// No description
clk_peri_uart0: u1 = 0,
/// clk_sys_uart0 [7:7]
/// No description
clk_sys_uart0: u1 = 0,
/// clk_peri_uart1 [8:8]
/// No description
clk_peri_uart1: u1 = 0,
/// clk_sys_uart1 [9:9]
/// No description
clk_sys_uart1: u1 = 0,
/// clk_sys_usbctrl [10:10]
/// No description
clk_sys_usbctrl: u1 = 0,
/// clk_usb_usbctrl [11:11]
/// No description
clk_usb_usbctrl: u1 = 0,
/// clk_sys_watchdog [12:12]
/// No description
clk_sys_watchdog: u1 = 0,
/// clk_sys_xip [13:13]
/// No description
clk_sys_xip: u1 = 0,
/// clk_sys_xosc [14:14]
/// No description
clk_sys_xosc: u1 = 0,
/// unused [15:31]
_unused15: u1 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// indicates the state of the clock enable
pub const ENABLED1 = Register(ENABLED1_val).init(base_address + 0xb4);
/// ENABLED0
const ENABLED0_val = packed struct {
/// clk_sys_clocks [0:0]
/// No description
clk_sys_clocks: u1 = 0,
/// clk_adc_adc [1:1]
/// No description
clk_adc_adc: u1 = 0,
/// clk_sys_adc [2:2]
/// No description
clk_sys_adc: u1 = 0,
/// clk_sys_busctrl [3:3]
/// No description
clk_sys_busctrl: u1 = 0,
/// clk_sys_busfabric [4:4]
/// No description
clk_sys_busfabric: u1 = 0,
/// clk_sys_dma [5:5]
/// No description
clk_sys_dma: u1 = 0,
/// clk_sys_i2c0 [6:6]
/// No description
clk_sys_i2c0: u1 = 0,
/// clk_sys_i2c1 [7:7]
/// No description
clk_sys_i2c1: u1 = 0,
/// clk_sys_io [8:8]
/// No description
clk_sys_io: u1 = 0,
/// clk_sys_jtag [9:9]
/// No description
clk_sys_jtag: u1 = 0,
/// clk_sys_vreg_and_chip_reset [10:10]
/// No description
clk_sys_vreg_and_chip_reset: u1 = 0,
/// clk_sys_pads [11:11]
/// No description
clk_sys_pads: u1 = 0,
/// clk_sys_pio0 [12:12]
/// No description
clk_sys_pio0: u1 = 0,
/// clk_sys_pio1 [13:13]
/// No description
clk_sys_pio1: u1 = 0,
/// clk_sys_pll_sys [14:14]
/// No description
clk_sys_pll_sys: u1 = 0,
/// clk_sys_pll_usb [15:15]
/// No description
clk_sys_pll_usb: u1 = 0,
/// clk_sys_psm [16:16]
/// No description
clk_sys_psm: u1 = 0,
/// clk_sys_pwm [17:17]
/// No description
clk_sys_pwm: u1 = 0,
/// clk_sys_resets [18:18]
/// No description
clk_sys_resets: u1 = 0,
/// clk_sys_rom [19:19]
/// No description
clk_sys_rom: u1 = 0,
/// clk_sys_rosc [20:20]
/// No description
clk_sys_rosc: u1 = 0,
/// clk_rtc_rtc [21:21]
/// No description
clk_rtc_rtc: u1 = 0,
/// clk_sys_rtc [22:22]
/// No description
clk_sys_rtc: u1 = 0,
/// clk_sys_sio [23:23]
/// No description
clk_sys_sio: u1 = 0,
/// clk_peri_spi0 [24:24]
/// No description
clk_peri_spi0: u1 = 0,
/// clk_sys_spi0 [25:25]
/// No description
clk_sys_spi0: u1 = 0,
/// clk_peri_spi1 [26:26]
/// No description
clk_peri_spi1: u1 = 0,
/// clk_sys_spi1 [27:27]
/// No description
clk_sys_spi1: u1 = 0,
/// clk_sys_sram0 [28:28]
/// No description
clk_sys_sram0: u1 = 0,
/// clk_sys_sram1 [29:29]
/// No description
clk_sys_sram1: u1 = 0,
/// clk_sys_sram2 [30:30]
/// No description
clk_sys_sram2: u1 = 0,
/// clk_sys_sram3 [31:31]
/// No description
clk_sys_sram3: u1 = 0,
};
/// indicates the state of the clock enable
pub const ENABLED0 = Register(ENABLED0_val).init(base_address + 0xb0);
/// SLEEP_EN1
const SLEEP_EN1_val = packed struct {
/// clk_sys_sram4 [0:0]
/// No description
clk_sys_sram4: u1 = 1,
/// clk_sys_sram5 [1:1]
/// No description
clk_sys_sram5: u1 = 1,
/// clk_sys_syscfg [2:2]
/// No description
clk_sys_syscfg: u1 = 1,
/// clk_sys_sysinfo [3:3]
/// No description
clk_sys_sysinfo: u1 = 1,
/// clk_sys_tbman [4:4]
/// No description
clk_sys_tbman: u1 = 1,
/// clk_sys_timer [5:5]
/// No description
clk_sys_timer: u1 = 1,
/// clk_peri_uart0 [6:6]
/// No description
clk_peri_uart0: u1 = 1,
/// clk_sys_uart0 [7:7]
/// No description
clk_sys_uart0: u1 = 1,
/// clk_peri_uart1 [8:8]
/// No description
clk_peri_uart1: u1 = 1,
/// clk_sys_uart1 [9:9]
/// No description
clk_sys_uart1: u1 = 1,
/// clk_sys_usbctrl [10:10]
/// No description
clk_sys_usbctrl: u1 = 1,
/// clk_usb_usbctrl [11:11]
/// No description
clk_usb_usbctrl: u1 = 1,
/// clk_sys_watchdog [12:12]
/// No description
clk_sys_watchdog: u1 = 1,
/// clk_sys_xip [13:13]
/// No description
clk_sys_xip: u1 = 1,
/// clk_sys_xosc [14:14]
/// No description
clk_sys_xosc: u1 = 1,
/// unused [15:31]
_unused15: u1 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// enable clock in sleep mode
pub const SLEEP_EN1 = Register(SLEEP_EN1_val).init(base_address + 0xac);
/// SLEEP_EN0
const SLEEP_EN0_val = packed struct {
/// clk_sys_clocks [0:0]
/// No description
clk_sys_clocks: u1 = 1,
/// clk_adc_adc [1:1]
/// No description
clk_adc_adc: u1 = 1,
/// clk_sys_adc [2:2]
/// No description
clk_sys_adc: u1 = 1,
/// clk_sys_busctrl [3:3]
/// No description
clk_sys_busctrl: u1 = 1,
/// clk_sys_busfabric [4:4]
/// No description
clk_sys_busfabric: u1 = 1,
/// clk_sys_dma [5:5]
/// No description
clk_sys_dma: u1 = 1,
/// clk_sys_i2c0 [6:6]
/// No description
clk_sys_i2c0: u1 = 1,
/// clk_sys_i2c1 [7:7]
/// No description
clk_sys_i2c1: u1 = 1,
/// clk_sys_io [8:8]
/// No description
clk_sys_io: u1 = 1,
/// clk_sys_jtag [9:9]
/// No description
clk_sys_jtag: u1 = 1,
/// clk_sys_vreg_and_chip_reset [10:10]
/// No description
clk_sys_vreg_and_chip_reset: u1 = 1,
/// clk_sys_pads [11:11]
/// No description
clk_sys_pads: u1 = 1,
/// clk_sys_pio0 [12:12]
/// No description
clk_sys_pio0: u1 = 1,
/// clk_sys_pio1 [13:13]
/// No description
clk_sys_pio1: u1 = 1,
/// clk_sys_pll_sys [14:14]
/// No description
clk_sys_pll_sys: u1 = 1,
/// clk_sys_pll_usb [15:15]
/// No description
clk_sys_pll_usb: u1 = 1,
/// clk_sys_psm [16:16]
/// No description
clk_sys_psm: u1 = 1,
/// clk_sys_pwm [17:17]
/// No description
clk_sys_pwm: u1 = 1,
/// clk_sys_resets [18:18]
/// No description
clk_sys_resets: u1 = 1,
/// clk_sys_rom [19:19]
/// No description
clk_sys_rom: u1 = 1,
/// clk_sys_rosc [20:20]
/// No description
clk_sys_rosc: u1 = 1,
/// clk_rtc_rtc [21:21]
/// No description
clk_rtc_rtc: u1 = 1,
/// clk_sys_rtc [22:22]
/// No description
clk_sys_rtc: u1 = 1,
/// clk_sys_sio [23:23]
/// No description
clk_sys_sio: u1 = 1,
/// clk_peri_spi0 [24:24]
/// No description
clk_peri_spi0: u1 = 1,
/// clk_sys_spi0 [25:25]
/// No description
clk_sys_spi0: u1 = 1,
/// clk_peri_spi1 [26:26]
/// No description
clk_peri_spi1: u1 = 1,
/// clk_sys_spi1 [27:27]
/// No description
clk_sys_spi1: u1 = 1,
/// clk_sys_sram0 [28:28]
/// No description
clk_sys_sram0: u1 = 1,
/// clk_sys_sram1 [29:29]
/// No description
clk_sys_sram1: u1 = 1,
/// clk_sys_sram2 [30:30]
/// No description
clk_sys_sram2: u1 = 1,
/// clk_sys_sram3 [31:31]
/// No description
clk_sys_sram3: u1 = 1,
};
/// enable clock in sleep mode
pub const SLEEP_EN0 = Register(SLEEP_EN0_val).init(base_address + 0xa8);
/// WAKE_EN1
const WAKE_EN1_val = packed struct {
/// clk_sys_sram4 [0:0]
/// No description
clk_sys_sram4: u1 = 1,
/// clk_sys_sram5 [1:1]
/// No description
clk_sys_sram5: u1 = 1,
/// clk_sys_syscfg [2:2]
/// No description
clk_sys_syscfg: u1 = 1,
/// clk_sys_sysinfo [3:3]
/// No description
clk_sys_sysinfo: u1 = 1,
/// clk_sys_tbman [4:4]
/// No description
clk_sys_tbman: u1 = 1,
/// clk_sys_timer [5:5]
/// No description
clk_sys_timer: u1 = 1,
/// clk_peri_uart0 [6:6]
/// No description
clk_peri_uart0: u1 = 1,
/// clk_sys_uart0 [7:7]
/// No description
clk_sys_uart0: u1 = 1,
/// clk_peri_uart1 [8:8]
/// No description
clk_peri_uart1: u1 = 1,
/// clk_sys_uart1 [9:9]
/// No description
clk_sys_uart1: u1 = 1,
/// clk_sys_usbctrl [10:10]
/// No description
clk_sys_usbctrl: u1 = 1,
/// clk_usb_usbctrl [11:11]
/// No description
clk_usb_usbctrl: u1 = 1,
/// clk_sys_watchdog [12:12]
/// No description
clk_sys_watchdog: u1 = 1,
/// clk_sys_xip [13:13]
/// No description
clk_sys_xip: u1 = 1,
/// clk_sys_xosc [14:14]
/// No description
clk_sys_xosc: u1 = 1,
/// unused [15:31]
_unused15: u1 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// enable clock in wake mode
pub const WAKE_EN1 = Register(WAKE_EN1_val).init(base_address + 0xa4);
/// WAKE_EN0
const WAKE_EN0_val = packed struct {
/// clk_sys_clocks [0:0]
/// No description
clk_sys_clocks: u1 = 1,
/// clk_adc_adc [1:1]
/// No description
clk_adc_adc: u1 = 1,
/// clk_sys_adc [2:2]
/// No description
clk_sys_adc: u1 = 1,
/// clk_sys_busctrl [3:3]
/// No description
clk_sys_busctrl: u1 = 1,
/// clk_sys_busfabric [4:4]
/// No description
clk_sys_busfabric: u1 = 1,
/// clk_sys_dma [5:5]
/// No description
clk_sys_dma: u1 = 1,
/// clk_sys_i2c0 [6:6]
/// No description
clk_sys_i2c0: u1 = 1,
/// clk_sys_i2c1 [7:7]
/// No description
clk_sys_i2c1: u1 = 1,
/// clk_sys_io [8:8]
/// No description
clk_sys_io: u1 = 1,
/// clk_sys_jtag [9:9]
/// No description
clk_sys_jtag: u1 = 1,
/// clk_sys_vreg_and_chip_reset [10:10]
/// No description
clk_sys_vreg_and_chip_reset: u1 = 1,
/// clk_sys_pads [11:11]
/// No description
clk_sys_pads: u1 = 1,
/// clk_sys_pio0 [12:12]
/// No description
clk_sys_pio0: u1 = 1,
/// clk_sys_pio1 [13:13]
/// No description
clk_sys_pio1: u1 = 1,
/// clk_sys_pll_sys [14:14]
/// No description
clk_sys_pll_sys: u1 = 1,
/// clk_sys_pll_usb [15:15]
/// No description
clk_sys_pll_usb: u1 = 1,
/// clk_sys_psm [16:16]
/// No description
clk_sys_psm: u1 = 1,
/// clk_sys_pwm [17:17]
/// No description
clk_sys_pwm: u1 = 1,
/// clk_sys_resets [18:18]
/// No description
clk_sys_resets: u1 = 1,
/// clk_sys_rom [19:19]
/// No description
clk_sys_rom: u1 = 1,
/// clk_sys_rosc [20:20]
/// No description
clk_sys_rosc: u1 = 1,
/// clk_rtc_rtc [21:21]
/// No description
clk_rtc_rtc: u1 = 1,
/// clk_sys_rtc [22:22]
/// No description
clk_sys_rtc: u1 = 1,
/// clk_sys_sio [23:23]
/// No description
clk_sys_sio: u1 = 1,
/// clk_peri_spi0 [24:24]
/// No description
clk_peri_spi0: u1 = 1,
/// clk_sys_spi0 [25:25]
/// No description
clk_sys_spi0: u1 = 1,
/// clk_peri_spi1 [26:26]
/// No description
clk_peri_spi1: u1 = 1,
/// clk_sys_spi1 [27:27]
/// No description
clk_sys_spi1: u1 = 1,
/// clk_sys_sram0 [28:28]
/// No description
clk_sys_sram0: u1 = 1,
/// clk_sys_sram1 [29:29]
/// No description
clk_sys_sram1: u1 = 1,
/// clk_sys_sram2 [30:30]
/// No description
clk_sys_sram2: u1 = 1,
/// clk_sys_sram3 [31:31]
/// No description
clk_sys_sram3: u1 = 1,
};
/// enable clock in wake mode
pub const WAKE_EN0 = Register(WAKE_EN0_val).init(base_address + 0xa0);
/// FC0_RESULT
const FC0_RESULT_val = packed struct {
/// FRAC [0:4]
/// No description
FRAC: u5 = 0,
/// KHZ [5:29]
/// No description
KHZ: u25 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// Result of frequency measurement, only valid when status_done=1
pub const FC0_RESULT = Register(FC0_RESULT_val).init(base_address + 0x9c);
/// FC0_STATUS
const FC0_STATUS_val = packed struct {
/// PASS [0:0]
/// Test passed
PASS: u1 = 0,
/// unused [1:3]
_unused1: u3 = 0,
/// DONE [4:4]
/// Test complete
DONE: u1 = 0,
/// unused [5:7]
_unused5: u3 = 0,
/// RUNNING [8:8]
/// Test running
RUNNING: u1 = 0,
/// unused [9:11]
_unused9: u3 = 0,
/// WAITING [12:12]
/// Waiting for test clock to start
WAITING: u1 = 0,
/// unused [13:15]
_unused13: u3 = 0,
/// FAIL [16:16]
/// Test failed
FAIL: u1 = 0,
/// unused [17:19]
_unused17: u3 = 0,
/// SLOW [20:20]
/// Test clock slower than expected, only valid when status_done=1
SLOW: u1 = 0,
/// unused [21:23]
_unused21: u3 = 0,
/// FAST [24:24]
/// Test clock faster than expected, only valid when status_done=1
FAST: u1 = 0,
/// unused [25:27]
_unused25: u3 = 0,
/// DIED [28:28]
/// Test clock stopped during test
DIED: u1 = 0,
/// unused [29:31]
_unused29: u3 = 0,
};
/// Frequency counter status
pub const FC0_STATUS = Register(FC0_STATUS_val).init(base_address + 0x98);
/// FC0_SRC
const FC0_SRC_val = packed struct {
/// FC0_SRC [0:7]
/// No description
FC0_SRC: u8 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Clock sent to frequency counter, set to 0 when not required\n
pub const FC0_SRC = Register(FC0_SRC_val).init(base_address + 0x94);
/// FC0_INTERVAL
const FC0_INTERVAL_val = packed struct {
/// FC0_INTERVAL [0:3]
/// No description
FC0_INTERVAL: u4 = 8,
/// unused [4:31]
_unused4: u4 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval\n
pub const FC0_INTERVAL = Register(FC0_INTERVAL_val).init(base_address + 0x90);
/// FC0_DELAY
const FC0_DELAY_val = packed struct {
/// FC0_DELAY [0:2]
/// No description
FC0_DELAY: u3 = 1,
/// unused [3:31]
_unused3: u5 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Delays the start of frequency counting to allow the mux to settle\n
pub const FC0_DELAY = Register(FC0_DELAY_val).init(base_address + 0x8c);
/// FC0_MAX_KHZ
const FC0_MAX_KHZ_val = packed struct {
/// FC0_MAX_KHZ [0:24]
/// No description
FC0_MAX_KHZ: u25 = 33554431,
/// unused [25:31]
_unused25: u7 = 0,
};
/// Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags
pub const FC0_MAX_KHZ = Register(FC0_MAX_KHZ_val).init(base_address + 0x88);
/// FC0_MIN_KHZ
const FC0_MIN_KHZ_val = packed struct {
/// FC0_MIN_KHZ [0:24]
/// No description
FC0_MIN_KHZ: u25 = 0,
/// unused [25:31]
_unused25: u7 = 0,
};
/// Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags
pub const FC0_MIN_KHZ = Register(FC0_MIN_KHZ_val).init(base_address + 0x84);
/// FC0_REF_KHZ
const FC0_REF_KHZ_val = packed struct {
/// FC0_REF_KHZ [0:19]
/// No description
FC0_REF_KHZ: u20 = 0,
/// unused [20:31]
_unused20: u4 = 0,
_unused24: u8 = 0,
};
/// Reference clock frequency in kHz
pub const FC0_REF_KHZ = Register(FC0_REF_KHZ_val).init(base_address + 0x80);
/// CLK_SYS_RESUS_STATUS
const CLK_SYS_RESUS_STATUS_val = packed struct {
/// RESUSSED [0:0]
/// Clock has been resuscitated, correct the error then send ctrl_clear=1
RESUSSED: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// No description
pub const CLK_SYS_RESUS_STATUS = Register(CLK_SYS_RESUS_STATUS_val).init(base_address + 0x7c);
/// CLK_SYS_RESUS_CTRL
const CLK_SYS_RESUS_CTRL_val = packed struct {
/// TIMEOUT [0:7]
/// This is expressed as a number of clk_ref cycles\n
TIMEOUT: u8 = 255,
/// ENABLE [8:8]
/// Enable resus
ENABLE: u1 = 0,
/// unused [9:11]
_unused9: u3 = 0,
/// FRCE [12:12]
/// Force a resus, for test purposes only
FRCE: u1 = 0,
/// unused [13:15]
_unused13: u3 = 0,
/// CLEAR [16:16]
/// For clearing the resus after the fault that triggered it has been corrected
CLEAR: u1 = 0,
/// unused [17:31]
_unused17: u7 = 0,
_unused24: u8 = 0,
};
/// No description
pub const CLK_SYS_RESUS_CTRL = Register(CLK_SYS_RESUS_CTRL_val).init(base_address + 0x78);
/// CLK_RTC_SELECTED
const CLK_RTC_SELECTED_val = packed struct {
CLK_RTC_SELECTED_0: u8 = 1,
CLK_RTC_SELECTED_1: u8 = 0,
CLK_RTC_SELECTED_2: u8 = 0,
CLK_RTC_SELECTED_3: u8 = 0,
};
/// Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
pub const CLK_RTC_SELECTED = Register(CLK_RTC_SELECTED_val).init(base_address + 0x74);
/// CLK_RTC_DIV
const CLK_RTC_DIV_val = packed struct {
/// FRAC [0:7]
/// Fractional component of the divisor
FRAC: u8 = 0,
/// INT [8:31]
/// Integer component of the divisor, 0 -> divide by 2^16
INT: u24 = 1,
};
/// Clock divisor, can be changed on-the-fly
pub const CLK_RTC_DIV = Register(CLK_RTC_DIV_val).init(base_address + 0x70);
/// CLK_RTC_CTRL
const CLK_RTC_CTRL_val = packed struct {
/// unused [0:4]
_unused0: u5 = 0,
/// AUXSRC [5:7]
/// Selects the auxiliary clock source, will glitch when switching
AUXSRC: u3 = 0,
/// unused [8:9]
_unused8: u2 = 0,
/// KILL [10:10]
/// Asynchronously kills the clock generator
KILL: u1 = 0,
/// ENABLE [11:11]
/// Starts and stops the clock generator cleanly
ENABLE: u1 = 0,
/// unused [12:15]
_unused12: u4 = 0,
/// PHASE [16:17]
/// This delays the enable signal by up to 3 cycles of the input clock\n
PHASE: u2 = 0,
/// unused [18:19]
_unused18: u2 = 0,
/// NUDGE [20:20]
/// An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n
NUDGE: u1 = 0,
/// unused [21:31]
_unused21: u3 = 0,
_unused24: u8 = 0,
};
/// Clock control, can be changed on-the-fly (except for auxsrc)
pub const CLK_RTC_CTRL = Register(CLK_RTC_CTRL_val).init(base_address + 0x6c);
/// CLK_ADC_SELECTED
const CLK_ADC_SELECTED_val = packed struct {
CLK_ADC_SELECTED_0: u8 = 1,
CLK_ADC_SELECTED_1: u8 = 0,
CLK_ADC_SELECTED_2: u8 = 0,
CLK_ADC_SELECTED_3: u8 = 0,
};
/// Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
pub const CLK_ADC_SELECTED = Register(CLK_ADC_SELECTED_val).init(base_address + 0x68);
/// CLK_ADC_DIV
const CLK_ADC_DIV_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// INT [8:9]
/// Integer component of the divisor, 0 -> divide by 2^16
INT: u2 = 1,
/// unused [10:31]
_unused10: u6 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Clock divisor, can be changed on-the-fly
pub const CLK_ADC_DIV = Register(CLK_ADC_DIV_val).init(base_address + 0x64);
/// CLK_ADC_CTRL
const CLK_ADC_CTRL_val = packed struct {
/// unused [0:4]
_unused0: u5 = 0,
/// AUXSRC [5:7]
/// Selects the auxiliary clock source, will glitch when switching
AUXSRC: u3 = 0,
/// unused [8:9]
_unused8: u2 = 0,
/// KILL [10:10]
/// Asynchronously kills the clock generator
KILL: u1 = 0,
/// ENABLE [11:11]
/// Starts and stops the clock generator cleanly
ENABLE: u1 = 0,
/// unused [12:15]
_unused12: u4 = 0,
/// PHASE [16:17]
/// This delays the enable signal by up to 3 cycles of the input clock\n
PHASE: u2 = 0,
/// unused [18:19]
_unused18: u2 = 0,
/// NUDGE [20:20]
/// An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n
NUDGE: u1 = 0,
/// unused [21:31]
_unused21: u3 = 0,
_unused24: u8 = 0,
};
/// Clock control, can be changed on-the-fly (except for auxsrc)
pub const CLK_ADC_CTRL = Register(CLK_ADC_CTRL_val).init(base_address + 0x60);
/// CLK_USB_SELECTED
const CLK_USB_SELECTED_val = packed struct {
CLK_USB_SELECTED_0: u8 = 1,
CLK_USB_SELECTED_1: u8 = 0,
CLK_USB_SELECTED_2: u8 = 0,
CLK_USB_SELECTED_3: u8 = 0,
};
/// Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
pub const CLK_USB_SELECTED = Register(CLK_USB_SELECTED_val).init(base_address + 0x5c);
/// CLK_USB_DIV
const CLK_USB_DIV_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// INT [8:9]
/// Integer component of the divisor, 0 -> divide by 2^16
INT: u2 = 1,
/// unused [10:31]
_unused10: u6 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Clock divisor, can be changed on-the-fly
pub const CLK_USB_DIV = Register(CLK_USB_DIV_val).init(base_address + 0x58);
/// CLK_USB_CTRL
const CLK_USB_CTRL_val = packed struct {
/// unused [0:4]
_unused0: u5 = 0,
/// AUXSRC [5:7]
/// Selects the auxiliary clock source, will glitch when switching
AUXSRC: u3 = 0,
/// unused [8:9]
_unused8: u2 = 0,
/// KILL [10:10]
/// Asynchronously kills the clock generator
KILL: u1 = 0,
/// ENABLE [11:11]
/// Starts and stops the clock generator cleanly
ENABLE: u1 = 0,
/// unused [12:15]
_unused12: u4 = 0,
/// PHASE [16:17]
/// This delays the enable signal by up to 3 cycles of the input clock\n
PHASE: u2 = 0,
/// unused [18:19]
_unused18: u2 = 0,
/// NUDGE [20:20]
/// An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n
NUDGE: u1 = 0,
/// unused [21:31]
_unused21: u3 = 0,
_unused24: u8 = 0,
};
/// Clock control, can be changed on-the-fly (except for auxsrc)
pub const CLK_USB_CTRL = Register(CLK_USB_CTRL_val).init(base_address + 0x54);
/// CLK_PERI_SELECTED
const CLK_PERI_SELECTED_val = packed struct {
CLK_PERI_SELECTED_0: u8 = 1,
CLK_PERI_SELECTED_1: u8 = 0,
CLK_PERI_SELECTED_2: u8 = 0,
CLK_PERI_SELECTED_3: u8 = 0,
};
/// Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
pub const CLK_PERI_SELECTED = Register(CLK_PERI_SELECTED_val).init(base_address + 0x50);
/// CLK_PERI_CTRL
const CLK_PERI_CTRL_val = packed struct {
/// unused [0:4]
_unused0: u5 = 0,
/// AUXSRC [5:7]
/// Selects the auxiliary clock source, will glitch when switching
AUXSRC: u3 = 0,
/// unused [8:9]
_unused8: u2 = 0,
/// KILL [10:10]
/// Asynchronously kills the clock generator
KILL: u1 = 0,
/// ENABLE [11:11]
/// Starts and stops the clock generator cleanly
ENABLE: u1 = 0,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Clock control, can be changed on-the-fly (except for auxsrc)
pub const CLK_PERI_CTRL = Register(CLK_PERI_CTRL_val).init(base_address + 0x48);
/// CLK_SYS_SELECTED
const CLK_SYS_SELECTED_val = packed struct {
CLK_SYS_SELECTED_0: u8 = 1,
CLK_SYS_SELECTED_1: u8 = 0,
CLK_SYS_SELECTED_2: u8 = 0,
CLK_SYS_SELECTED_3: u8 = 0,
};
/// Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
pub const CLK_SYS_SELECTED = Register(CLK_SYS_SELECTED_val).init(base_address + 0x44);
/// CLK_SYS_DIV
const CLK_SYS_DIV_val = packed struct {
/// FRAC [0:7]
/// Fractional component of the divisor
FRAC: u8 = 0,
/// INT [8:31]
/// Integer component of the divisor, 0 -> divide by 2^16
INT: u24 = 1,
};
/// Clock divisor, can be changed on-the-fly
pub const CLK_SYS_DIV = Register(CLK_SYS_DIV_val).init(base_address + 0x40);
/// CLK_SYS_CTRL
const CLK_SYS_CTRL_val = packed struct {
/// SRC [0:0]
/// Selects the clock source glitchlessly, can be changed on-the-fly
SRC: u1 = 0,
/// unused [1:4]
_unused1: u4 = 0,
/// AUXSRC [5:7]
/// Selects the auxiliary clock source, will glitch when switching
AUXSRC: u3 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Clock control, can be changed on-the-fly (except for auxsrc)
pub const CLK_SYS_CTRL = Register(CLK_SYS_CTRL_val).init(base_address + 0x3c);
/// CLK_REF_SELECTED
const CLK_REF_SELECTED_val = packed struct {
CLK_REF_SELECTED_0: u8 = 1,
CLK_REF_SELECTED_1: u8 = 0,
CLK_REF_SELECTED_2: u8 = 0,
CLK_REF_SELECTED_3: u8 = 0,
};
/// Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
pub const CLK_REF_SELECTED = Register(CLK_REF_SELECTED_val).init(base_address + 0x38);
/// CLK_REF_DIV
const CLK_REF_DIV_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// INT [8:9]
/// Integer component of the divisor, 0 -> divide by 2^16
INT: u2 = 1,
/// unused [10:31]
_unused10: u6 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Clock divisor, can be changed on-the-fly
pub const CLK_REF_DIV = Register(CLK_REF_DIV_val).init(base_address + 0x34);
/// CLK_REF_CTRL
const CLK_REF_CTRL_val = packed struct {
/// SRC [0:1]
/// Selects the clock source glitchlessly, can be changed on-the-fly
SRC: u2 = 0,
/// unused [2:4]
_unused2: u3 = 0,
/// AUXSRC [5:6]
/// Selects the auxiliary clock source, will glitch when switching
AUXSRC: u2 = 0,
/// unused [7:31]
_unused7: u1 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Clock control, can be changed on-the-fly (except for auxsrc)
pub const CLK_REF_CTRL = Register(CLK_REF_CTRL_val).init(base_address + 0x30);
/// CLK_GPOUT3_SELECTED
const CLK_GPOUT3_SELECTED_val = packed struct {
CLK_GPOUT3_SELECTED_0: u8 = 1,
CLK_GPOUT3_SELECTED_1: u8 = 0,
CLK_GPOUT3_SELECTED_2: u8 = 0,
CLK_GPOUT3_SELECTED_3: u8 = 0,
};
/// Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
pub const CLK_GPOUT3_SELECTED = Register(CLK_GPOUT3_SELECTED_val).init(base_address + 0x2c);
/// CLK_GPOUT3_DIV
const CLK_GPOUT3_DIV_val = packed struct {
/// FRAC [0:7]
/// Fractional component of the divisor
FRAC: u8 = 0,
/// INT [8:31]
/// Integer component of the divisor, 0 -> divide by 2^16
INT: u24 = 1,
};
/// Clock divisor, can be changed on-the-fly
pub const CLK_GPOUT3_DIV = Register(CLK_GPOUT3_DIV_val).init(base_address + 0x28);
/// CLK_GPOUT3_CTRL
const CLK_GPOUT3_CTRL_val = packed struct {
/// unused [0:4]
_unused0: u5 = 0,
/// AUXSRC [5:8]
/// Selects the auxiliary clock source, will glitch when switching
AUXSRC: u4 = 0,
/// unused [9:9]
_unused9: u1 = 0,
/// KILL [10:10]
/// Asynchronously kills the clock generator
KILL: u1 = 0,
/// ENABLE [11:11]
/// Starts and stops the clock generator cleanly
ENABLE: u1 = 0,
/// DC50 [12:12]
/// Enables duty cycle correction for odd divisors
DC50: u1 = 0,
/// unused [13:15]
_unused13: u3 = 0,
/// PHASE [16:17]
/// This delays the enable signal by up to 3 cycles of the input clock\n
PHASE: u2 = 0,
/// unused [18:19]
_unused18: u2 = 0,
/// NUDGE [20:20]
/// An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n
NUDGE: u1 = 0,
/// unused [21:31]
_unused21: u3 = 0,
_unused24: u8 = 0,
};
/// Clock control, can be changed on-the-fly (except for auxsrc)
pub const CLK_GPOUT3_CTRL = Register(CLK_GPOUT3_CTRL_val).init(base_address + 0x24);
/// CLK_GPOUT2_SELECTED
const CLK_GPOUT2_SELECTED_val = packed struct {
CLK_GPOUT2_SELECTED_0: u8 = 1,
CLK_GPOUT2_SELECTED_1: u8 = 0,
CLK_GPOUT2_SELECTED_2: u8 = 0,
CLK_GPOUT2_SELECTED_3: u8 = 0,
};
/// Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
pub const CLK_GPOUT2_SELECTED = Register(CLK_GPOUT2_SELECTED_val).init(base_address + 0x20);
/// CLK_GPOUT2_DIV
const CLK_GPOUT2_DIV_val = packed struct {
/// FRAC [0:7]
/// Fractional component of the divisor
FRAC: u8 = 0,
/// INT [8:31]
/// Integer component of the divisor, 0 -> divide by 2^16
INT: u24 = 1,
};
/// Clock divisor, can be changed on-the-fly
pub const CLK_GPOUT2_DIV = Register(CLK_GPOUT2_DIV_val).init(base_address + 0x1c);
/// CLK_GPOUT2_CTRL
const CLK_GPOUT2_CTRL_val = packed struct {
/// unused [0:4]
_unused0: u5 = 0,
/// AUXSRC [5:8]
/// Selects the auxiliary clock source, will glitch when switching
AUXSRC: u4 = 0,
/// unused [9:9]
_unused9: u1 = 0,
/// KILL [10:10]
/// Asynchronously kills the clock generator
KILL: u1 = 0,
/// ENABLE [11:11]
/// Starts and stops the clock generator cleanly
ENABLE: u1 = 0,
/// DC50 [12:12]
/// Enables duty cycle correction for odd divisors
DC50: u1 = 0,
/// unused [13:15]
_unused13: u3 = 0,
/// PHASE [16:17]
/// This delays the enable signal by up to 3 cycles of the input clock\n
PHASE: u2 = 0,
/// unused [18:19]
_unused18: u2 = 0,
/// NUDGE [20:20]
/// An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n
NUDGE: u1 = 0,
/// unused [21:31]
_unused21: u3 = 0,
_unused24: u8 = 0,
};
/// Clock control, can be changed on-the-fly (except for auxsrc)
pub const CLK_GPOUT2_CTRL = Register(CLK_GPOUT2_CTRL_val).init(base_address + 0x18);
/// CLK_GPOUT1_SELECTED
const CLK_GPOUT1_SELECTED_val = packed struct {
CLK_GPOUT1_SELECTED_0: u8 = 1,
CLK_GPOUT1_SELECTED_1: u8 = 0,
CLK_GPOUT1_SELECTED_2: u8 = 0,
CLK_GPOUT1_SELECTED_3: u8 = 0,
};
/// Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
pub const CLK_GPOUT1_SELECTED = Register(CLK_GPOUT1_SELECTED_val).init(base_address + 0x14);
/// CLK_GPOUT1_DIV
const CLK_GPOUT1_DIV_val = packed struct {
/// FRAC [0:7]
/// Fractional component of the divisor
FRAC: u8 = 0,
/// INT [8:31]
/// Integer component of the divisor, 0 -> divide by 2^16
INT: u24 = 1,
};
/// Clock divisor, can be changed on-the-fly
pub const CLK_GPOUT1_DIV = Register(CLK_GPOUT1_DIV_val).init(base_address + 0x10);
/// CLK_GPOUT1_CTRL
const CLK_GPOUT1_CTRL_val = packed struct {
/// unused [0:4]
_unused0: u5 = 0,
/// AUXSRC [5:8]
/// Selects the auxiliary clock source, will glitch when switching
AUXSRC: u4 = 0,
/// unused [9:9]
_unused9: u1 = 0,
/// KILL [10:10]
/// Asynchronously kills the clock generator
KILL: u1 = 0,
/// ENABLE [11:11]
/// Starts and stops the clock generator cleanly
ENABLE: u1 = 0,
/// DC50 [12:12]
/// Enables duty cycle correction for odd divisors
DC50: u1 = 0,
/// unused [13:15]
_unused13: u3 = 0,
/// PHASE [16:17]
/// This delays the enable signal by up to 3 cycles of the input clock\n
PHASE: u2 = 0,
/// unused [18:19]
_unused18: u2 = 0,
/// NUDGE [20:20]
/// An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n
NUDGE: u1 = 0,
/// unused [21:31]
_unused21: u3 = 0,
_unused24: u8 = 0,
};
/// Clock control, can be changed on-the-fly (except for auxsrc)
pub const CLK_GPOUT1_CTRL = Register(CLK_GPOUT1_CTRL_val).init(base_address + 0xc);
/// CLK_GPOUT0_SELECTED
const CLK_GPOUT0_SELECTED_val = packed struct {
CLK_GPOUT0_SELECTED_0: u8 = 1,
CLK_GPOUT0_SELECTED_1: u8 = 0,
CLK_GPOUT0_SELECTED_2: u8 = 0,
CLK_GPOUT0_SELECTED_3: u8 = 0,
};
/// Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
pub const CLK_GPOUT0_SELECTED = Register(CLK_GPOUT0_SELECTED_val).init(base_address + 0x8);
/// CLK_GPOUT0_DIV
const CLK_GPOUT0_DIV_val = packed struct {
/// FRAC [0:7]
/// Fractional component of the divisor
FRAC: u8 = 0,
/// INT [8:31]
/// Integer component of the divisor, 0 -> divide by 2^16
INT: u24 = 1,
};
/// Clock divisor, can be changed on-the-fly
pub const CLK_GPOUT0_DIV = Register(CLK_GPOUT0_DIV_val).init(base_address + 0x4);
/// CLK_GPOUT0_CTRL
const CLK_GPOUT0_CTRL_val = packed struct {
/// unused [0:4]
_unused0: u5 = 0,
/// AUXSRC [5:8]
/// Selects the auxiliary clock source, will glitch when switching
AUXSRC: u4 = 0,
/// unused [9:9]
_unused9: u1 = 0,
/// KILL [10:10]
/// Asynchronously kills the clock generator
KILL: u1 = 0,
/// ENABLE [11:11]
/// Starts and stops the clock generator cleanly
ENABLE: u1 = 0,
/// DC50 [12:12]
/// Enables duty cycle correction for odd divisors
DC50: u1 = 0,
/// unused [13:15]
_unused13: u3 = 0,
/// PHASE [16:17]
/// This delays the enable signal by up to 3 cycles of the input clock\n
PHASE: u2 = 0,
/// unused [18:19]
_unused18: u2 = 0,
/// NUDGE [20:20]
/// An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n
NUDGE: u1 = 0,
/// unused [21:31]
_unused21: u3 = 0,
_unused24: u8 = 0,
};
/// Clock control, can be changed on-the-fly (except for auxsrc)
pub const CLK_GPOUT0_CTRL = Register(CLK_GPOUT0_CTRL_val).init(base_address + 0x0);
};
/// No description
pub const RESETS = struct {
const base_address = 0x4000c000;
/// RESET_DONE
const RESET_DONE_val = packed struct {
/// adc [0:0]
/// No description
adc: u1 = 0,
/// busctrl [1:1]
/// No description
busctrl: u1 = 0,
/// dma [2:2]
/// No description
dma: u1 = 0,
/// i2c0 [3:3]
/// No description
i2c0: u1 = 0,
/// i2c1 [4:4]
/// No description
i2c1: u1 = 0,
/// io_bank0 [5:5]
/// No description
io_bank0: u1 = 0,
/// io_qspi [6:6]
/// No description
io_qspi: u1 = 0,
/// jtag [7:7]
/// No description
jtag: u1 = 0,
/// pads_bank0 [8:8]
/// No description
pads_bank0: u1 = 0,
/// pads_qspi [9:9]
/// No description
pads_qspi: u1 = 0,
/// pio0 [10:10]
/// No description
pio0: u1 = 0,
/// pio1 [11:11]
/// No description
pio1: u1 = 0,
/// pll_sys [12:12]
/// No description
pll_sys: u1 = 0,
/// pll_usb [13:13]
/// No description
pll_usb: u1 = 0,
/// pwm [14:14]
/// No description
pwm: u1 = 0,
/// rtc [15:15]
/// No description
rtc: u1 = 0,
/// spi0 [16:16]
/// No description
spi0: u1 = 0,
/// spi1 [17:17]
/// No description
spi1: u1 = 0,
/// syscfg [18:18]
/// No description
syscfg: u1 = 0,
/// sysinfo [19:19]
/// No description
sysinfo: u1 = 0,
/// tbman [20:20]
/// No description
tbman: u1 = 0,
/// timer [21:21]
/// No description
timer: u1 = 0,
/// uart0 [22:22]
/// No description
uart0: u1 = 0,
/// uart1 [23:23]
/// No description
uart1: u1 = 0,
/// usbctrl [24:24]
/// No description
usbctrl: u1 = 0,
/// unused [25:31]
_unused25: u7 = 0,
};
/// Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral's registers are ready to be accessed.
pub const RESET_DONE = Register(RESET_DONE_val).init(base_address + 0x8);
/// WDSEL
const WDSEL_val = packed struct {
/// adc [0:0]
/// No description
adc: u1 = 0,
/// busctrl [1:1]
/// No description
busctrl: u1 = 0,
/// dma [2:2]
/// No description
dma: u1 = 0,
/// i2c0 [3:3]
/// No description
i2c0: u1 = 0,
/// i2c1 [4:4]
/// No description
i2c1: u1 = 0,
/// io_bank0 [5:5]
/// No description
io_bank0: u1 = 0,
/// io_qspi [6:6]
/// No description
io_qspi: u1 = 0,
/// jtag [7:7]
/// No description
jtag: u1 = 0,
/// pads_bank0 [8:8]
/// No description
pads_bank0: u1 = 0,
/// pads_qspi [9:9]
/// No description
pads_qspi: u1 = 0,
/// pio0 [10:10]
/// No description
pio0: u1 = 0,
/// pio1 [11:11]
/// No description
pio1: u1 = 0,
/// pll_sys [12:12]
/// No description
pll_sys: u1 = 0,
/// pll_usb [13:13]
/// No description
pll_usb: u1 = 0,
/// pwm [14:14]
/// No description
pwm: u1 = 0,
/// rtc [15:15]
/// No description
rtc: u1 = 0,
/// spi0 [16:16]
/// No description
spi0: u1 = 0,
/// spi1 [17:17]
/// No description
spi1: u1 = 0,
/// syscfg [18:18]
/// No description
syscfg: u1 = 0,
/// sysinfo [19:19]
/// No description
sysinfo: u1 = 0,
/// tbman [20:20]
/// No description
tbman: u1 = 0,
/// timer [21:21]
/// No description
timer: u1 = 0,
/// uart0 [22:22]
/// No description
uart0: u1 = 0,
/// uart1 [23:23]
/// No description
uart1: u1 = 0,
/// usbctrl [24:24]
/// No description
usbctrl: u1 = 0,
/// unused [25:31]
_unused25: u7 = 0,
};
/// Watchdog select. If a bit is set then the watchdog will reset this peripheral when the watchdog fires.
pub const WDSEL = Register(WDSEL_val).init(base_address + 0x4);
/// RESET
const RESET_val = packed struct {
/// adc [0:0]
/// No description
adc: u1 = 1,
/// busctrl [1:1]
/// No description
busctrl: u1 = 1,
/// dma [2:2]
/// No description
dma: u1 = 1,
/// i2c0 [3:3]
/// No description
i2c0: u1 = 1,
/// i2c1 [4:4]
/// No description
i2c1: u1 = 1,
/// io_bank0 [5:5]
/// No description
io_bank0: u1 = 1,
/// io_qspi [6:6]
/// No description
io_qspi: u1 = 1,
/// jtag [7:7]
/// No description
jtag: u1 = 1,
/// pads_bank0 [8:8]
/// No description
pads_bank0: u1 = 1,
/// pads_qspi [9:9]
/// No description
pads_qspi: u1 = 1,
/// pio0 [10:10]
/// No description
pio0: u1 = 1,
/// pio1 [11:11]
/// No description
pio1: u1 = 1,
/// pll_sys [12:12]
/// No description
pll_sys: u1 = 1,
/// pll_usb [13:13]
/// No description
pll_usb: u1 = 1,
/// pwm [14:14]
/// No description
pwm: u1 = 1,
/// rtc [15:15]
/// No description
rtc: u1 = 1,
/// spi0 [16:16]
/// No description
spi0: u1 = 1,
/// spi1 [17:17]
/// No description
spi1: u1 = 1,
/// syscfg [18:18]
/// No description
syscfg: u1 = 1,
/// sysinfo [19:19]
/// No description
sysinfo: u1 = 1,
/// tbman [20:20]
/// No description
tbman: u1 = 1,
/// timer [21:21]
/// No description
timer: u1 = 1,
/// uart0 [22:22]
/// No description
uart0: u1 = 1,
/// uart1 [23:23]
/// No description
uart1: u1 = 1,
/// usbctrl [24:24]
/// No description
usbctrl: u1 = 1,
/// unused [25:31]
_unused25: u7 = 0,
};
/// Reset control. If a bit is set it means the peripheral is in reset. 0 means the peripheral's reset is deasserted.
pub const RESET = Register(RESET_val).init(base_address + 0x0);
};
/// No description
pub const PSM = struct {
const base_address = 0x40010000;
/// DONE
const DONE_val = packed struct {
/// rosc [0:0]
/// No description
rosc: u1 = 0,
/// xosc [1:1]
/// No description
xosc: u1 = 0,
/// clocks [2:2]
/// No description
clocks: u1 = 0,
/// resets [3:3]
/// No description
resets: u1 = 0,
/// busfabric [4:4]
/// No description
busfabric: u1 = 0,
/// rom [5:5]
/// No description
rom: u1 = 0,
/// sram0 [6:6]
/// No description
sram0: u1 = 0,
/// sram1 [7:7]
/// No description
sram1: u1 = 0,
/// sram2 [8:8]
/// No description
sram2: u1 = 0,
/// sram3 [9:9]
/// No description
sram3: u1 = 0,
/// sram4 [10:10]
/// No description
sram4: u1 = 0,
/// sram5 [11:11]
/// No description
sram5: u1 = 0,
/// xip [12:12]
/// No description
xip: u1 = 0,
/// vreg_and_chip_reset [13:13]
/// No description
vreg_and_chip_reset: u1 = 0,
/// sio [14:14]
/// No description
sio: u1 = 0,
/// proc0 [15:15]
/// No description
proc0: u1 = 0,
/// proc1 [16:16]
/// No description
proc1: u1 = 0,
/// unused [17:31]
_unused17: u7 = 0,
_unused24: u8 = 0,
};
/// Indicates the peripheral's registers are ready to access.
pub const DONE = Register(DONE_val).init(base_address + 0xc);
/// WDSEL
const WDSEL_val = packed struct {
/// rosc [0:0]
/// No description
rosc: u1 = 0,
/// xosc [1:1]
/// No description
xosc: u1 = 0,
/// clocks [2:2]
/// No description
clocks: u1 = 0,
/// resets [3:3]
/// No description
resets: u1 = 0,
/// busfabric [4:4]
/// No description
busfabric: u1 = 0,
/// rom [5:5]
/// No description
rom: u1 = 0,
/// sram0 [6:6]
/// No description
sram0: u1 = 0,
/// sram1 [7:7]
/// No description
sram1: u1 = 0,
/// sram2 [8:8]
/// No description
sram2: u1 = 0,
/// sram3 [9:9]
/// No description
sram3: u1 = 0,
/// sram4 [10:10]
/// No description
sram4: u1 = 0,
/// sram5 [11:11]
/// No description
sram5: u1 = 0,
/// xip [12:12]
/// No description
xip: u1 = 0,
/// vreg_and_chip_reset [13:13]
/// No description
vreg_and_chip_reset: u1 = 0,
/// sio [14:14]
/// No description
sio: u1 = 0,
/// proc0 [15:15]
/// No description
proc0: u1 = 0,
/// proc1 [16:16]
/// No description
proc1: u1 = 0,
/// unused [17:31]
_unused17: u7 = 0,
_unused24: u8 = 0,
};
/// Set to 1 if this peripheral should be reset when the watchdog fires.
pub const WDSEL = Register(WDSEL_val).init(base_address + 0x8);
/// FRCE_OFF
const FRCE_OFF_val = packed struct {
/// rosc [0:0]
/// No description
rosc: u1 = 0,
/// xosc [1:1]
/// No description
xosc: u1 = 0,
/// clocks [2:2]
/// No description
clocks: u1 = 0,
/// resets [3:3]
/// No description
resets: u1 = 0,
/// busfabric [4:4]
/// No description
busfabric: u1 = 0,
/// rom [5:5]
/// No description
rom: u1 = 0,
/// sram0 [6:6]
/// No description
sram0: u1 = 0,
/// sram1 [7:7]
/// No description
sram1: u1 = 0,
/// sram2 [8:8]
/// No description
sram2: u1 = 0,
/// sram3 [9:9]
/// No description
sram3: u1 = 0,
/// sram4 [10:10]
/// No description
sram4: u1 = 0,
/// sram5 [11:11]
/// No description
sram5: u1 = 0,
/// xip [12:12]
/// No description
xip: u1 = 0,
/// vreg_and_chip_reset [13:13]
/// No description
vreg_and_chip_reset: u1 = 0,
/// sio [14:14]
/// No description
sio: u1 = 0,
/// proc0 [15:15]
/// No description
proc0: u1 = 0,
/// proc1 [16:16]
/// No description
proc1: u1 = 0,
/// unused [17:31]
_unused17: u7 = 0,
_unused24: u8 = 0,
};
/// Force into reset (i.e. power it off)
pub const FRCE_OFF = Register(FRCE_OFF_val).init(base_address + 0x4);
/// FRCE_ON
const FRCE_ON_val = packed struct {
/// rosc [0:0]
/// No description
rosc: u1 = 0,
/// xosc [1:1]
/// No description
xosc: u1 = 0,
/// clocks [2:2]
/// No description
clocks: u1 = 0,
/// resets [3:3]
/// No description
resets: u1 = 0,
/// busfabric [4:4]
/// No description
busfabric: u1 = 0,
/// rom [5:5]
/// No description
rom: u1 = 0,
/// sram0 [6:6]
/// No description
sram0: u1 = 0,
/// sram1 [7:7]
/// No description
sram1: u1 = 0,
/// sram2 [8:8]
/// No description
sram2: u1 = 0,
/// sram3 [9:9]
/// No description
sram3: u1 = 0,
/// sram4 [10:10]
/// No description
sram4: u1 = 0,
/// sram5 [11:11]
/// No description
sram5: u1 = 0,
/// xip [12:12]
/// No description
xip: u1 = 0,
/// vreg_and_chip_reset [13:13]
/// No description
vreg_and_chip_reset: u1 = 0,
/// sio [14:14]
/// No description
sio: u1 = 0,
/// proc0 [15:15]
/// No description
proc0: u1 = 0,
/// proc1 [16:16]
/// No description
proc1: u1 = 0,
/// unused [17:31]
_unused17: u7 = 0,
_unused24: u8 = 0,
};
/// Force block out of reset (i.e. power it on)
pub const FRCE_ON = Register(FRCE_ON_val).init(base_address + 0x0);
};
/// No description
pub const IO_BANK0 = struct {
const base_address = 0x40014000;
/// DORMANT_WAKE_INTS3
const DORMANT_WAKE_INTS3_val = packed struct {
/// GPIO24_LEVEL_LOW [0:0]
/// No description
GPIO24_LEVEL_LOW: u1 = 0,
/// GPIO24_LEVEL_HIGH [1:1]
/// No description
GPIO24_LEVEL_HIGH: u1 = 0,
/// GPIO24_EDGE_LOW [2:2]
/// No description
GPIO24_EDGE_LOW: u1 = 0,
/// GPIO24_EDGE_HIGH [3:3]
/// No description
GPIO24_EDGE_HIGH: u1 = 0,
/// GPIO25_LEVEL_LOW [4:4]
/// No description
GPIO25_LEVEL_LOW: u1 = 0,
/// GPIO25_LEVEL_HIGH [5:5]
/// No description
GPIO25_LEVEL_HIGH: u1 = 0,
/// GPIO25_EDGE_LOW [6:6]
/// No description
GPIO25_EDGE_LOW: u1 = 0,
/// GPIO25_EDGE_HIGH [7:7]
/// No description
GPIO25_EDGE_HIGH: u1 = 0,
/// GPIO26_LEVEL_LOW [8:8]
/// No description
GPIO26_LEVEL_LOW: u1 = 0,
/// GPIO26_LEVEL_HIGH [9:9]
/// No description
GPIO26_LEVEL_HIGH: u1 = 0,
/// GPIO26_EDGE_LOW [10:10]
/// No description
GPIO26_EDGE_LOW: u1 = 0,
/// GPIO26_EDGE_HIGH [11:11]
/// No description
GPIO26_EDGE_HIGH: u1 = 0,
/// GPIO27_LEVEL_LOW [12:12]
/// No description
GPIO27_LEVEL_LOW: u1 = 0,
/// GPIO27_LEVEL_HIGH [13:13]
/// No description
GPIO27_LEVEL_HIGH: u1 = 0,
/// GPIO27_EDGE_LOW [14:14]
/// No description
GPIO27_EDGE_LOW: u1 = 0,
/// GPIO27_EDGE_HIGH [15:15]
/// No description
GPIO27_EDGE_HIGH: u1 = 0,
/// GPIO28_LEVEL_LOW [16:16]
/// No description
GPIO28_LEVEL_LOW: u1 = 0,
/// GPIO28_LEVEL_HIGH [17:17]
/// No description
GPIO28_LEVEL_HIGH: u1 = 0,
/// GPIO28_EDGE_LOW [18:18]
/// No description
GPIO28_EDGE_LOW: u1 = 0,
/// GPIO28_EDGE_HIGH [19:19]
/// No description
GPIO28_EDGE_HIGH: u1 = 0,
/// GPIO29_LEVEL_LOW [20:20]
/// No description
GPIO29_LEVEL_LOW: u1 = 0,
/// GPIO29_LEVEL_HIGH [21:21]
/// No description
GPIO29_LEVEL_HIGH: u1 = 0,
/// GPIO29_EDGE_LOW [22:22]
/// No description
GPIO29_EDGE_LOW: u1 = 0,
/// GPIO29_EDGE_HIGH [23:23]
/// No description
GPIO29_EDGE_HIGH: u1 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Interrupt status after masking & forcing for dormant_wake
pub const DORMANT_WAKE_INTS3 = Register(DORMANT_WAKE_INTS3_val).init(base_address + 0x18c);
/// DORMANT_WAKE_INTS2
const DORMANT_WAKE_INTS2_val = packed struct {
/// GPIO16_LEVEL_LOW [0:0]
/// No description
GPIO16_LEVEL_LOW: u1 = 0,
/// GPIO16_LEVEL_HIGH [1:1]
/// No description
GPIO16_LEVEL_HIGH: u1 = 0,
/// GPIO16_EDGE_LOW [2:2]
/// No description
GPIO16_EDGE_LOW: u1 = 0,
/// GPIO16_EDGE_HIGH [3:3]
/// No description
GPIO16_EDGE_HIGH: u1 = 0,
/// GPIO17_LEVEL_LOW [4:4]
/// No description
GPIO17_LEVEL_LOW: u1 = 0,
/// GPIO17_LEVEL_HIGH [5:5]
/// No description
GPIO17_LEVEL_HIGH: u1 = 0,
/// GPIO17_EDGE_LOW [6:6]
/// No description
GPIO17_EDGE_LOW: u1 = 0,
/// GPIO17_EDGE_HIGH [7:7]
/// No description
GPIO17_EDGE_HIGH: u1 = 0,
/// GPIO18_LEVEL_LOW [8:8]
/// No description
GPIO18_LEVEL_LOW: u1 = 0,
/// GPIO18_LEVEL_HIGH [9:9]
/// No description
GPIO18_LEVEL_HIGH: u1 = 0,
/// GPIO18_EDGE_LOW [10:10]
/// No description
GPIO18_EDGE_LOW: u1 = 0,
/// GPIO18_EDGE_HIGH [11:11]
/// No description
GPIO18_EDGE_HIGH: u1 = 0,
/// GPIO19_LEVEL_LOW [12:12]
/// No description
GPIO19_LEVEL_LOW: u1 = 0,
/// GPIO19_LEVEL_HIGH [13:13]
/// No description
GPIO19_LEVEL_HIGH: u1 = 0,
/// GPIO19_EDGE_LOW [14:14]
/// No description
GPIO19_EDGE_LOW: u1 = 0,
/// GPIO19_EDGE_HIGH [15:15]
/// No description
GPIO19_EDGE_HIGH: u1 = 0,
/// GPIO20_LEVEL_LOW [16:16]
/// No description
GPIO20_LEVEL_LOW: u1 = 0,
/// GPIO20_LEVEL_HIGH [17:17]
/// No description
GPIO20_LEVEL_HIGH: u1 = 0,
/// GPIO20_EDGE_LOW [18:18]
/// No description
GPIO20_EDGE_LOW: u1 = 0,
/// GPIO20_EDGE_HIGH [19:19]
/// No description
GPIO20_EDGE_HIGH: u1 = 0,
/// GPIO21_LEVEL_LOW [20:20]
/// No description
GPIO21_LEVEL_LOW: u1 = 0,
/// GPIO21_LEVEL_HIGH [21:21]
/// No description
GPIO21_LEVEL_HIGH: u1 = 0,
/// GPIO21_EDGE_LOW [22:22]
/// No description
GPIO21_EDGE_LOW: u1 = 0,
/// GPIO21_EDGE_HIGH [23:23]
/// No description
GPIO21_EDGE_HIGH: u1 = 0,
/// GPIO22_LEVEL_LOW [24:24]
/// No description
GPIO22_LEVEL_LOW: u1 = 0,
/// GPIO22_LEVEL_HIGH [25:25]
/// No description
GPIO22_LEVEL_HIGH: u1 = 0,
/// GPIO22_EDGE_LOW [26:26]
/// No description
GPIO22_EDGE_LOW: u1 = 0,
/// GPIO22_EDGE_HIGH [27:27]
/// No description
GPIO22_EDGE_HIGH: u1 = 0,
/// GPIO23_LEVEL_LOW [28:28]
/// No description
GPIO23_LEVEL_LOW: u1 = 0,
/// GPIO23_LEVEL_HIGH [29:29]
/// No description
GPIO23_LEVEL_HIGH: u1 = 0,
/// GPIO23_EDGE_LOW [30:30]
/// No description
GPIO23_EDGE_LOW: u1 = 0,
/// GPIO23_EDGE_HIGH [31:31]
/// No description
GPIO23_EDGE_HIGH: u1 = 0,
};
/// Interrupt status after masking & forcing for dormant_wake
pub const DORMANT_WAKE_INTS2 = Register(DORMANT_WAKE_INTS2_val).init(base_address + 0x188);
/// DORMANT_WAKE_INTS1
const DORMANT_WAKE_INTS1_val = packed struct {
/// GPIO8_LEVEL_LOW [0:0]
/// No description
GPIO8_LEVEL_LOW: u1 = 0,
/// GPIO8_LEVEL_HIGH [1:1]
/// No description
GPIO8_LEVEL_HIGH: u1 = 0,
/// GPIO8_EDGE_LOW [2:2]
/// No description
GPIO8_EDGE_LOW: u1 = 0,
/// GPIO8_EDGE_HIGH [3:3]
/// No description
GPIO8_EDGE_HIGH: u1 = 0,
/// GPIO9_LEVEL_LOW [4:4]
/// No description
GPIO9_LEVEL_LOW: u1 = 0,
/// GPIO9_LEVEL_HIGH [5:5]
/// No description
GPIO9_LEVEL_HIGH: u1 = 0,
/// GPIO9_EDGE_LOW [6:6]
/// No description
GPIO9_EDGE_LOW: u1 = 0,
/// GPIO9_EDGE_HIGH [7:7]
/// No description
GPIO9_EDGE_HIGH: u1 = 0,
/// GPIO10_LEVEL_LOW [8:8]
/// No description
GPIO10_LEVEL_LOW: u1 = 0,
/// GPIO10_LEVEL_HIGH [9:9]
/// No description
GPIO10_LEVEL_HIGH: u1 = 0,
/// GPIO10_EDGE_LOW [10:10]
/// No description
GPIO10_EDGE_LOW: u1 = 0,
/// GPIO10_EDGE_HIGH [11:11]
/// No description
GPIO10_EDGE_HIGH: u1 = 0,
/// GPIO11_LEVEL_LOW [12:12]
/// No description
GPIO11_LEVEL_LOW: u1 = 0,
/// GPIO11_LEVEL_HIGH [13:13]
/// No description
GPIO11_LEVEL_HIGH: u1 = 0,
/// GPIO11_EDGE_LOW [14:14]
/// No description
GPIO11_EDGE_LOW: u1 = 0,
/// GPIO11_EDGE_HIGH [15:15]
/// No description
GPIO11_EDGE_HIGH: u1 = 0,
/// GPIO12_LEVEL_LOW [16:16]
/// No description
GPIO12_LEVEL_LOW: u1 = 0,
/// GPIO12_LEVEL_HIGH [17:17]
/// No description
GPIO12_LEVEL_HIGH: u1 = 0,
/// GPIO12_EDGE_LOW [18:18]
/// No description
GPIO12_EDGE_LOW: u1 = 0,
/// GPIO12_EDGE_HIGH [19:19]
/// No description
GPIO12_EDGE_HIGH: u1 = 0,
/// GPIO13_LEVEL_LOW [20:20]
/// No description
GPIO13_LEVEL_LOW: u1 = 0,
/// GPIO13_LEVEL_HIGH [21:21]
/// No description
GPIO13_LEVEL_HIGH: u1 = 0,
/// GPIO13_EDGE_LOW [22:22]
/// No description
GPIO13_EDGE_LOW: u1 = 0,
/// GPIO13_EDGE_HIGH [23:23]
/// No description
GPIO13_EDGE_HIGH: u1 = 0,
/// GPIO14_LEVEL_LOW [24:24]
/// No description
GPIO14_LEVEL_LOW: u1 = 0,
/// GPIO14_LEVEL_HIGH [25:25]
/// No description
GPIO14_LEVEL_HIGH: u1 = 0,
/// GPIO14_EDGE_LOW [26:26]
/// No description
GPIO14_EDGE_LOW: u1 = 0,
/// GPIO14_EDGE_HIGH [27:27]
/// No description
GPIO14_EDGE_HIGH: u1 = 0,
/// GPIO15_LEVEL_LOW [28:28]
/// No description
GPIO15_LEVEL_LOW: u1 = 0,
/// GPIO15_LEVEL_HIGH [29:29]
/// No description
GPIO15_LEVEL_HIGH: u1 = 0,
/// GPIO15_EDGE_LOW [30:30]
/// No description
GPIO15_EDGE_LOW: u1 = 0,
/// GPIO15_EDGE_HIGH [31:31]
/// No description
GPIO15_EDGE_HIGH: u1 = 0,
};
/// Interrupt status after masking & forcing for dormant_wake
pub const DORMANT_WAKE_INTS1 = Register(DORMANT_WAKE_INTS1_val).init(base_address + 0x184);
/// DORMANT_WAKE_INTS0
const DORMANT_WAKE_INTS0_val = packed struct {
/// GPIO0_LEVEL_LOW [0:0]
/// No description
GPIO0_LEVEL_LOW: u1 = 0,
/// GPIO0_LEVEL_HIGH [1:1]
/// No description
GPIO0_LEVEL_HIGH: u1 = 0,
/// GPIO0_EDGE_LOW [2:2]
/// No description
GPIO0_EDGE_LOW: u1 = 0,
/// GPIO0_EDGE_HIGH [3:3]
/// No description
GPIO0_EDGE_HIGH: u1 = 0,
/// GPIO1_LEVEL_LOW [4:4]
/// No description
GPIO1_LEVEL_LOW: u1 = 0,
/// GPIO1_LEVEL_HIGH [5:5]
/// No description
GPIO1_LEVEL_HIGH: u1 = 0,
/// GPIO1_EDGE_LOW [6:6]
/// No description
GPIO1_EDGE_LOW: u1 = 0,
/// GPIO1_EDGE_HIGH [7:7]
/// No description
GPIO1_EDGE_HIGH: u1 = 0,
/// GPIO2_LEVEL_LOW [8:8]
/// No description
GPIO2_LEVEL_LOW: u1 = 0,
/// GPIO2_LEVEL_HIGH [9:9]
/// No description
GPIO2_LEVEL_HIGH: u1 = 0,
/// GPIO2_EDGE_LOW [10:10]
/// No description
GPIO2_EDGE_LOW: u1 = 0,
/// GPIO2_EDGE_HIGH [11:11]
/// No description
GPIO2_EDGE_HIGH: u1 = 0,
/// GPIO3_LEVEL_LOW [12:12]
/// No description
GPIO3_LEVEL_LOW: u1 = 0,
/// GPIO3_LEVEL_HIGH [13:13]
/// No description
GPIO3_LEVEL_HIGH: u1 = 0,
/// GPIO3_EDGE_LOW [14:14]
/// No description
GPIO3_EDGE_LOW: u1 = 0,
/// GPIO3_EDGE_HIGH [15:15]
/// No description
GPIO3_EDGE_HIGH: u1 = 0,
/// GPIO4_LEVEL_LOW [16:16]
/// No description
GPIO4_LEVEL_LOW: u1 = 0,
/// GPIO4_LEVEL_HIGH [17:17]
/// No description
GPIO4_LEVEL_HIGH: u1 = 0,
/// GPIO4_EDGE_LOW [18:18]
/// No description
GPIO4_EDGE_LOW: u1 = 0,
/// GPIO4_EDGE_HIGH [19:19]
/// No description
GPIO4_EDGE_HIGH: u1 = 0,
/// GPIO5_LEVEL_LOW [20:20]
/// No description
GPIO5_LEVEL_LOW: u1 = 0,
/// GPIO5_LEVEL_HIGH [21:21]
/// No description
GPIO5_LEVEL_HIGH: u1 = 0,
/// GPIO5_EDGE_LOW [22:22]
/// No description
GPIO5_EDGE_LOW: u1 = 0,
/// GPIO5_EDGE_HIGH [23:23]
/// No description
GPIO5_EDGE_HIGH: u1 = 0,
/// GPIO6_LEVEL_LOW [24:24]
/// No description
GPIO6_LEVEL_LOW: u1 = 0,
/// GPIO6_LEVEL_HIGH [25:25]
/// No description
GPIO6_LEVEL_HIGH: u1 = 0,
/// GPIO6_EDGE_LOW [26:26]
/// No description
GPIO6_EDGE_LOW: u1 = 0,
/// GPIO6_EDGE_HIGH [27:27]
/// No description
GPIO6_EDGE_HIGH: u1 = 0,
/// GPIO7_LEVEL_LOW [28:28]
/// No description
GPIO7_LEVEL_LOW: u1 = 0,
/// GPIO7_LEVEL_HIGH [29:29]
/// No description
GPIO7_LEVEL_HIGH: u1 = 0,
/// GPIO7_EDGE_LOW [30:30]
/// No description
GPIO7_EDGE_LOW: u1 = 0,
/// GPIO7_EDGE_HIGH [31:31]
/// No description
GPIO7_EDGE_HIGH: u1 = 0,
};
/// Interrupt status after masking & forcing for dormant_wake
pub const DORMANT_WAKE_INTS0 = Register(DORMANT_WAKE_INTS0_val).init(base_address + 0x180);
/// DORMANT_WAKE_INTF3
const DORMANT_WAKE_INTF3_val = packed struct {
/// GPIO24_LEVEL_LOW [0:0]
/// No description
GPIO24_LEVEL_LOW: u1 = 0,
/// GPIO24_LEVEL_HIGH [1:1]
/// No description
GPIO24_LEVEL_HIGH: u1 = 0,
/// GPIO24_EDGE_LOW [2:2]
/// No description
GPIO24_EDGE_LOW: u1 = 0,
/// GPIO24_EDGE_HIGH [3:3]
/// No description
GPIO24_EDGE_HIGH: u1 = 0,
/// GPIO25_LEVEL_LOW [4:4]
/// No description
GPIO25_LEVEL_LOW: u1 = 0,
/// GPIO25_LEVEL_HIGH [5:5]
/// No description
GPIO25_LEVEL_HIGH: u1 = 0,
/// GPIO25_EDGE_LOW [6:6]
/// No description
GPIO25_EDGE_LOW: u1 = 0,
/// GPIO25_EDGE_HIGH [7:7]
/// No description
GPIO25_EDGE_HIGH: u1 = 0,
/// GPIO26_LEVEL_LOW [8:8]
/// No description
GPIO26_LEVEL_LOW: u1 = 0,
/// GPIO26_LEVEL_HIGH [9:9]
/// No description
GPIO26_LEVEL_HIGH: u1 = 0,
/// GPIO26_EDGE_LOW [10:10]
/// No description
GPIO26_EDGE_LOW: u1 = 0,
/// GPIO26_EDGE_HIGH [11:11]
/// No description
GPIO26_EDGE_HIGH: u1 = 0,
/// GPIO27_LEVEL_LOW [12:12]
/// No description
GPIO27_LEVEL_LOW: u1 = 0,
/// GPIO27_LEVEL_HIGH [13:13]
/// No description
GPIO27_LEVEL_HIGH: u1 = 0,
/// GPIO27_EDGE_LOW [14:14]
/// No description
GPIO27_EDGE_LOW: u1 = 0,
/// GPIO27_EDGE_HIGH [15:15]
/// No description
GPIO27_EDGE_HIGH: u1 = 0,
/// GPIO28_LEVEL_LOW [16:16]
/// No description
GPIO28_LEVEL_LOW: u1 = 0,
/// GPIO28_LEVEL_HIGH [17:17]
/// No description
GPIO28_LEVEL_HIGH: u1 = 0,
/// GPIO28_EDGE_LOW [18:18]
/// No description
GPIO28_EDGE_LOW: u1 = 0,
/// GPIO28_EDGE_HIGH [19:19]
/// No description
GPIO28_EDGE_HIGH: u1 = 0,
/// GPIO29_LEVEL_LOW [20:20]
/// No description
GPIO29_LEVEL_LOW: u1 = 0,
/// GPIO29_LEVEL_HIGH [21:21]
/// No description
GPIO29_LEVEL_HIGH: u1 = 0,
/// GPIO29_EDGE_LOW [22:22]
/// No description
GPIO29_EDGE_LOW: u1 = 0,
/// GPIO29_EDGE_HIGH [23:23]
/// No description
GPIO29_EDGE_HIGH: u1 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Interrupt Force for dormant_wake
pub const DORMANT_WAKE_INTF3 = Register(DORMANT_WAKE_INTF3_val).init(base_address + 0x17c);
/// DORMANT_WAKE_INTF2
const DORMANT_WAKE_INTF2_val = packed struct {
/// GPIO16_LEVEL_LOW [0:0]
/// No description
GPIO16_LEVEL_LOW: u1 = 0,
/// GPIO16_LEVEL_HIGH [1:1]
/// No description
GPIO16_LEVEL_HIGH: u1 = 0,
/// GPIO16_EDGE_LOW [2:2]
/// No description
GPIO16_EDGE_LOW: u1 = 0,
/// GPIO16_EDGE_HIGH [3:3]
/// No description
GPIO16_EDGE_HIGH: u1 = 0,
/// GPIO17_LEVEL_LOW [4:4]
/// No description
GPIO17_LEVEL_LOW: u1 = 0,
/// GPIO17_LEVEL_HIGH [5:5]
/// No description
GPIO17_LEVEL_HIGH: u1 = 0,
/// GPIO17_EDGE_LOW [6:6]
/// No description
GPIO17_EDGE_LOW: u1 = 0,
/// GPIO17_EDGE_HIGH [7:7]
/// No description
GPIO17_EDGE_HIGH: u1 = 0,
/// GPIO18_LEVEL_LOW [8:8]
/// No description
GPIO18_LEVEL_LOW: u1 = 0,
/// GPIO18_LEVEL_HIGH [9:9]
/// No description
GPIO18_LEVEL_HIGH: u1 = 0,
/// GPIO18_EDGE_LOW [10:10]
/// No description
GPIO18_EDGE_LOW: u1 = 0,
/// GPIO18_EDGE_HIGH [11:11]
/// No description
GPIO18_EDGE_HIGH: u1 = 0,
/// GPIO19_LEVEL_LOW [12:12]
/// No description
GPIO19_LEVEL_LOW: u1 = 0,
/// GPIO19_LEVEL_HIGH [13:13]
/// No description
GPIO19_LEVEL_HIGH: u1 = 0,
/// GPIO19_EDGE_LOW [14:14]
/// No description
GPIO19_EDGE_LOW: u1 = 0,
/// GPIO19_EDGE_HIGH [15:15]
/// No description
GPIO19_EDGE_HIGH: u1 = 0,
/// GPIO20_LEVEL_LOW [16:16]
/// No description
GPIO20_LEVEL_LOW: u1 = 0,
/// GPIO20_LEVEL_HIGH [17:17]
/// No description
GPIO20_LEVEL_HIGH: u1 = 0,
/// GPIO20_EDGE_LOW [18:18]
/// No description
GPIO20_EDGE_LOW: u1 = 0,
/// GPIO20_EDGE_HIGH [19:19]
/// No description
GPIO20_EDGE_HIGH: u1 = 0,
/// GPIO21_LEVEL_LOW [20:20]
/// No description
GPIO21_LEVEL_LOW: u1 = 0,
/// GPIO21_LEVEL_HIGH [21:21]
/// No description
GPIO21_LEVEL_HIGH: u1 = 0,
/// GPIO21_EDGE_LOW [22:22]
/// No description
GPIO21_EDGE_LOW: u1 = 0,
/// GPIO21_EDGE_HIGH [23:23]
/// No description
GPIO21_EDGE_HIGH: u1 = 0,
/// GPIO22_LEVEL_LOW [24:24]
/// No description
GPIO22_LEVEL_LOW: u1 = 0,
/// GPIO22_LEVEL_HIGH [25:25]
/// No description
GPIO22_LEVEL_HIGH: u1 = 0,
/// GPIO22_EDGE_LOW [26:26]
/// No description
GPIO22_EDGE_LOW: u1 = 0,
/// GPIO22_EDGE_HIGH [27:27]
/// No description
GPIO22_EDGE_HIGH: u1 = 0,
/// GPIO23_LEVEL_LOW [28:28]
/// No description
GPIO23_LEVEL_LOW: u1 = 0,
/// GPIO23_LEVEL_HIGH [29:29]
/// No description
GPIO23_LEVEL_HIGH: u1 = 0,
/// GPIO23_EDGE_LOW [30:30]
/// No description
GPIO23_EDGE_LOW: u1 = 0,
/// GPIO23_EDGE_HIGH [31:31]
/// No description
GPIO23_EDGE_HIGH: u1 = 0,
};
/// Interrupt Force for dormant_wake
pub const DORMANT_WAKE_INTF2 = Register(DORMANT_WAKE_INTF2_val).init(base_address + 0x178);
/// DORMANT_WAKE_INTF1
const DORMANT_WAKE_INTF1_val = packed struct {
/// GPIO8_LEVEL_LOW [0:0]
/// No description
GPIO8_LEVEL_LOW: u1 = 0,
/// GPIO8_LEVEL_HIGH [1:1]
/// No description
GPIO8_LEVEL_HIGH: u1 = 0,
/// GPIO8_EDGE_LOW [2:2]
/// No description
GPIO8_EDGE_LOW: u1 = 0,
/// GPIO8_EDGE_HIGH [3:3]
/// No description
GPIO8_EDGE_HIGH: u1 = 0,
/// GPIO9_LEVEL_LOW [4:4]
/// No description
GPIO9_LEVEL_LOW: u1 = 0,
/// GPIO9_LEVEL_HIGH [5:5]
/// No description
GPIO9_LEVEL_HIGH: u1 = 0,
/// GPIO9_EDGE_LOW [6:6]
/// No description
GPIO9_EDGE_LOW: u1 = 0,
/// GPIO9_EDGE_HIGH [7:7]
/// No description
GPIO9_EDGE_HIGH: u1 = 0,
/// GPIO10_LEVEL_LOW [8:8]
/// No description
GPIO10_LEVEL_LOW: u1 = 0,
/// GPIO10_LEVEL_HIGH [9:9]
/// No description
GPIO10_LEVEL_HIGH: u1 = 0,
/// GPIO10_EDGE_LOW [10:10]
/// No description
GPIO10_EDGE_LOW: u1 = 0,
/// GPIO10_EDGE_HIGH [11:11]
/// No description
GPIO10_EDGE_HIGH: u1 = 0,
/// GPIO11_LEVEL_LOW [12:12]
/// No description
GPIO11_LEVEL_LOW: u1 = 0,
/// GPIO11_LEVEL_HIGH [13:13]
/// No description
GPIO11_LEVEL_HIGH: u1 = 0,
/// GPIO11_EDGE_LOW [14:14]
/// No description
GPIO11_EDGE_LOW: u1 = 0,
/// GPIO11_EDGE_HIGH [15:15]
/// No description
GPIO11_EDGE_HIGH: u1 = 0,
/// GPIO12_LEVEL_LOW [16:16]
/// No description
GPIO12_LEVEL_LOW: u1 = 0,
/// GPIO12_LEVEL_HIGH [17:17]
/// No description
GPIO12_LEVEL_HIGH: u1 = 0,
/// GPIO12_EDGE_LOW [18:18]
/// No description
GPIO12_EDGE_LOW: u1 = 0,
/// GPIO12_EDGE_HIGH [19:19]
/// No description
GPIO12_EDGE_HIGH: u1 = 0,
/// GPIO13_LEVEL_LOW [20:20]
/// No description
GPIO13_LEVEL_LOW: u1 = 0,
/// GPIO13_LEVEL_HIGH [21:21]
/// No description
GPIO13_LEVEL_HIGH: u1 = 0,
/// GPIO13_EDGE_LOW [22:22]
/// No description
GPIO13_EDGE_LOW: u1 = 0,
/// GPIO13_EDGE_HIGH [23:23]
/// No description
GPIO13_EDGE_HIGH: u1 = 0,
/// GPIO14_LEVEL_LOW [24:24]
/// No description
GPIO14_LEVEL_LOW: u1 = 0,
/// GPIO14_LEVEL_HIGH [25:25]
/// No description
GPIO14_LEVEL_HIGH: u1 = 0,
/// GPIO14_EDGE_LOW [26:26]
/// No description
GPIO14_EDGE_LOW: u1 = 0,
/// GPIO14_EDGE_HIGH [27:27]
/// No description
GPIO14_EDGE_HIGH: u1 = 0,
/// GPIO15_LEVEL_LOW [28:28]
/// No description
GPIO15_LEVEL_LOW: u1 = 0,
/// GPIO15_LEVEL_HIGH [29:29]
/// No description
GPIO15_LEVEL_HIGH: u1 = 0,
/// GPIO15_EDGE_LOW [30:30]
/// No description
GPIO15_EDGE_LOW: u1 = 0,
/// GPIO15_EDGE_HIGH [31:31]
/// No description
GPIO15_EDGE_HIGH: u1 = 0,
};
/// Interrupt Force for dormant_wake
pub const DORMANT_WAKE_INTF1 = Register(DORMANT_WAKE_INTF1_val).init(base_address + 0x174);
/// DORMANT_WAKE_INTF0
const DORMANT_WAKE_INTF0_val = packed struct {
/// GPIO0_LEVEL_LOW [0:0]
/// No description
GPIO0_LEVEL_LOW: u1 = 0,
/// GPIO0_LEVEL_HIGH [1:1]
/// No description
GPIO0_LEVEL_HIGH: u1 = 0,
/// GPIO0_EDGE_LOW [2:2]
/// No description
GPIO0_EDGE_LOW: u1 = 0,
/// GPIO0_EDGE_HIGH [3:3]
/// No description
GPIO0_EDGE_HIGH: u1 = 0,
/// GPIO1_LEVEL_LOW [4:4]
/// No description
GPIO1_LEVEL_LOW: u1 = 0,
/// GPIO1_LEVEL_HIGH [5:5]
/// No description
GPIO1_LEVEL_HIGH: u1 = 0,
/// GPIO1_EDGE_LOW [6:6]
/// No description
GPIO1_EDGE_LOW: u1 = 0,
/// GPIO1_EDGE_HIGH [7:7]
/// No description
GPIO1_EDGE_HIGH: u1 = 0,
/// GPIO2_LEVEL_LOW [8:8]
/// No description
GPIO2_LEVEL_LOW: u1 = 0,
/// GPIO2_LEVEL_HIGH [9:9]
/// No description
GPIO2_LEVEL_HIGH: u1 = 0,
/// GPIO2_EDGE_LOW [10:10]
/// No description
GPIO2_EDGE_LOW: u1 = 0,
/// GPIO2_EDGE_HIGH [11:11]
/// No description
GPIO2_EDGE_HIGH: u1 = 0,
/// GPIO3_LEVEL_LOW [12:12]
/// No description
GPIO3_LEVEL_LOW: u1 = 0,
/// GPIO3_LEVEL_HIGH [13:13]
/// No description
GPIO3_LEVEL_HIGH: u1 = 0,
/// GPIO3_EDGE_LOW [14:14]
/// No description
GPIO3_EDGE_LOW: u1 = 0,
/// GPIO3_EDGE_HIGH [15:15]
/// No description
GPIO3_EDGE_HIGH: u1 = 0,
/// GPIO4_LEVEL_LOW [16:16]
/// No description
GPIO4_LEVEL_LOW: u1 = 0,
/// GPIO4_LEVEL_HIGH [17:17]
/// No description
GPIO4_LEVEL_HIGH: u1 = 0,
/// GPIO4_EDGE_LOW [18:18]
/// No description
GPIO4_EDGE_LOW: u1 = 0,
/// GPIO4_EDGE_HIGH [19:19]
/// No description
GPIO4_EDGE_HIGH: u1 = 0,
/// GPIO5_LEVEL_LOW [20:20]
/// No description
GPIO5_LEVEL_LOW: u1 = 0,
/// GPIO5_LEVEL_HIGH [21:21]
/// No description
GPIO5_LEVEL_HIGH: u1 = 0,
/// GPIO5_EDGE_LOW [22:22]
/// No description
GPIO5_EDGE_LOW: u1 = 0,
/// GPIO5_EDGE_HIGH [23:23]
/// No description
GPIO5_EDGE_HIGH: u1 = 0,
/// GPIO6_LEVEL_LOW [24:24]
/// No description
GPIO6_LEVEL_LOW: u1 = 0,
/// GPIO6_LEVEL_HIGH [25:25]
/// No description
GPIO6_LEVEL_HIGH: u1 = 0,
/// GPIO6_EDGE_LOW [26:26]
/// No description
GPIO6_EDGE_LOW: u1 = 0,
/// GPIO6_EDGE_HIGH [27:27]
/// No description
GPIO6_EDGE_HIGH: u1 = 0,
/// GPIO7_LEVEL_LOW [28:28]
/// No description
GPIO7_LEVEL_LOW: u1 = 0,
/// GPIO7_LEVEL_HIGH [29:29]
/// No description
GPIO7_LEVEL_HIGH: u1 = 0,
/// GPIO7_EDGE_LOW [30:30]
/// No description
GPIO7_EDGE_LOW: u1 = 0,
/// GPIO7_EDGE_HIGH [31:31]
/// No description
GPIO7_EDGE_HIGH: u1 = 0,
};
/// Interrupt Force for dormant_wake
pub const DORMANT_WAKE_INTF0 = Register(DORMANT_WAKE_INTF0_val).init(base_address + 0x170);
/// DORMANT_WAKE_INTE3
const DORMANT_WAKE_INTE3_val = packed struct {
/// GPIO24_LEVEL_LOW [0:0]
/// No description
GPIO24_LEVEL_LOW: u1 = 0,
/// GPIO24_LEVEL_HIGH [1:1]
/// No description
GPIO24_LEVEL_HIGH: u1 = 0,
/// GPIO24_EDGE_LOW [2:2]
/// No description
GPIO24_EDGE_LOW: u1 = 0,
/// GPIO24_EDGE_HIGH [3:3]
/// No description
GPIO24_EDGE_HIGH: u1 = 0,
/// GPIO25_LEVEL_LOW [4:4]
/// No description
GPIO25_LEVEL_LOW: u1 = 0,
/// GPIO25_LEVEL_HIGH [5:5]
/// No description
GPIO25_LEVEL_HIGH: u1 = 0,
/// GPIO25_EDGE_LOW [6:6]
/// No description
GPIO25_EDGE_LOW: u1 = 0,
/// GPIO25_EDGE_HIGH [7:7]
/// No description
GPIO25_EDGE_HIGH: u1 = 0,
/// GPIO26_LEVEL_LOW [8:8]
/// No description
GPIO26_LEVEL_LOW: u1 = 0,
/// GPIO26_LEVEL_HIGH [9:9]
/// No description
GPIO26_LEVEL_HIGH: u1 = 0,
/// GPIO26_EDGE_LOW [10:10]
/// No description
GPIO26_EDGE_LOW: u1 = 0,
/// GPIO26_EDGE_HIGH [11:11]
/// No description
GPIO26_EDGE_HIGH: u1 = 0,
/// GPIO27_LEVEL_LOW [12:12]
/// No description
GPIO27_LEVEL_LOW: u1 = 0,
/// GPIO27_LEVEL_HIGH [13:13]
/// No description
GPIO27_LEVEL_HIGH: u1 = 0,
/// GPIO27_EDGE_LOW [14:14]
/// No description
GPIO27_EDGE_LOW: u1 = 0,
/// GPIO27_EDGE_HIGH [15:15]
/// No description
GPIO27_EDGE_HIGH: u1 = 0,
/// GPIO28_LEVEL_LOW [16:16]
/// No description
GPIO28_LEVEL_LOW: u1 = 0,
/// GPIO28_LEVEL_HIGH [17:17]
/// No description
GPIO28_LEVEL_HIGH: u1 = 0,
/// GPIO28_EDGE_LOW [18:18]
/// No description
GPIO28_EDGE_LOW: u1 = 0,
/// GPIO28_EDGE_HIGH [19:19]
/// No description
GPIO28_EDGE_HIGH: u1 = 0,
/// GPIO29_LEVEL_LOW [20:20]
/// No description
GPIO29_LEVEL_LOW: u1 = 0,
/// GPIO29_LEVEL_HIGH [21:21]
/// No description
GPIO29_LEVEL_HIGH: u1 = 0,
/// GPIO29_EDGE_LOW [22:22]
/// No description
GPIO29_EDGE_LOW: u1 = 0,
/// GPIO29_EDGE_HIGH [23:23]
/// No description
GPIO29_EDGE_HIGH: u1 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Interrupt Enable for dormant_wake
pub const DORMANT_WAKE_INTE3 = Register(DORMANT_WAKE_INTE3_val).init(base_address + 0x16c);
/// DORMANT_WAKE_INTE2
const DORMANT_WAKE_INTE2_val = packed struct {
/// GPIO16_LEVEL_LOW [0:0]
/// No description
GPIO16_LEVEL_LOW: u1 = 0,
/// GPIO16_LEVEL_HIGH [1:1]
/// No description
GPIO16_LEVEL_HIGH: u1 = 0,
/// GPIO16_EDGE_LOW [2:2]
/// No description
GPIO16_EDGE_LOW: u1 = 0,
/// GPIO16_EDGE_HIGH [3:3]
/// No description
GPIO16_EDGE_HIGH: u1 = 0,
/// GPIO17_LEVEL_LOW [4:4]
/// No description
GPIO17_LEVEL_LOW: u1 = 0,
/// GPIO17_LEVEL_HIGH [5:5]
/// No description
GPIO17_LEVEL_HIGH: u1 = 0,
/// GPIO17_EDGE_LOW [6:6]
/// No description
GPIO17_EDGE_LOW: u1 = 0,
/// GPIO17_EDGE_HIGH [7:7]
/// No description
GPIO17_EDGE_HIGH: u1 = 0,
/// GPIO18_LEVEL_LOW [8:8]
/// No description
GPIO18_LEVEL_LOW: u1 = 0,
/// GPIO18_LEVEL_HIGH [9:9]
/// No description
GPIO18_LEVEL_HIGH: u1 = 0,
/// GPIO18_EDGE_LOW [10:10]
/// No description
GPIO18_EDGE_LOW: u1 = 0,
/// GPIO18_EDGE_HIGH [11:11]
/// No description
GPIO18_EDGE_HIGH: u1 = 0,
/// GPIO19_LEVEL_LOW [12:12]
/// No description
GPIO19_LEVEL_LOW: u1 = 0,
/// GPIO19_LEVEL_HIGH [13:13]
/// No description
GPIO19_LEVEL_HIGH: u1 = 0,
/// GPIO19_EDGE_LOW [14:14]
/// No description
GPIO19_EDGE_LOW: u1 = 0,
/// GPIO19_EDGE_HIGH [15:15]
/// No description
GPIO19_EDGE_HIGH: u1 = 0,
/// GPIO20_LEVEL_LOW [16:16]
/// No description
GPIO20_LEVEL_LOW: u1 = 0,
/// GPIO20_LEVEL_HIGH [17:17]
/// No description
GPIO20_LEVEL_HIGH: u1 = 0,
/// GPIO20_EDGE_LOW [18:18]
/// No description
GPIO20_EDGE_LOW: u1 = 0,
/// GPIO20_EDGE_HIGH [19:19]
/// No description
GPIO20_EDGE_HIGH: u1 = 0,
/// GPIO21_LEVEL_LOW [20:20]
/// No description
GPIO21_LEVEL_LOW: u1 = 0,
/// GPIO21_LEVEL_HIGH [21:21]
/// No description
GPIO21_LEVEL_HIGH: u1 = 0,
/// GPIO21_EDGE_LOW [22:22]
/// No description
GPIO21_EDGE_LOW: u1 = 0,
/// GPIO21_EDGE_HIGH [23:23]
/// No description
GPIO21_EDGE_HIGH: u1 = 0,
/// GPIO22_LEVEL_LOW [24:24]
/// No description
GPIO22_LEVEL_LOW: u1 = 0,
/// GPIO22_LEVEL_HIGH [25:25]
/// No description
GPIO22_LEVEL_HIGH: u1 = 0,
/// GPIO22_EDGE_LOW [26:26]
/// No description
GPIO22_EDGE_LOW: u1 = 0,
/// GPIO22_EDGE_HIGH [27:27]
/// No description
GPIO22_EDGE_HIGH: u1 = 0,
/// GPIO23_LEVEL_LOW [28:28]
/// No description
GPIO23_LEVEL_LOW: u1 = 0,
/// GPIO23_LEVEL_HIGH [29:29]
/// No description
GPIO23_LEVEL_HIGH: u1 = 0,
/// GPIO23_EDGE_LOW [30:30]
/// No description
GPIO23_EDGE_LOW: u1 = 0,
/// GPIO23_EDGE_HIGH [31:31]
/// No description
GPIO23_EDGE_HIGH: u1 = 0,
};
/// Interrupt Enable for dormant_wake
pub const DORMANT_WAKE_INTE2 = Register(DORMANT_WAKE_INTE2_val).init(base_address + 0x168);
/// DORMANT_WAKE_INTE1
const DORMANT_WAKE_INTE1_val = packed struct {
/// GPIO8_LEVEL_LOW [0:0]
/// No description
GPIO8_LEVEL_LOW: u1 = 0,
/// GPIO8_LEVEL_HIGH [1:1]
/// No description
GPIO8_LEVEL_HIGH: u1 = 0,
/// GPIO8_EDGE_LOW [2:2]
/// No description
GPIO8_EDGE_LOW: u1 = 0,
/// GPIO8_EDGE_HIGH [3:3]
/// No description
GPIO8_EDGE_HIGH: u1 = 0,
/// GPIO9_LEVEL_LOW [4:4]
/// No description
GPIO9_LEVEL_LOW: u1 = 0,
/// GPIO9_LEVEL_HIGH [5:5]
/// No description
GPIO9_LEVEL_HIGH: u1 = 0,
/// GPIO9_EDGE_LOW [6:6]
/// No description
GPIO9_EDGE_LOW: u1 = 0,
/// GPIO9_EDGE_HIGH [7:7]
/// No description
GPIO9_EDGE_HIGH: u1 = 0,
/// GPIO10_LEVEL_LOW [8:8]
/// No description
GPIO10_LEVEL_LOW: u1 = 0,
/// GPIO10_LEVEL_HIGH [9:9]
/// No description
GPIO10_LEVEL_HIGH: u1 = 0,
/// GPIO10_EDGE_LOW [10:10]
/// No description
GPIO10_EDGE_LOW: u1 = 0,
/// GPIO10_EDGE_HIGH [11:11]
/// No description
GPIO10_EDGE_HIGH: u1 = 0,
/// GPIO11_LEVEL_LOW [12:12]
/// No description
GPIO11_LEVEL_LOW: u1 = 0,
/// GPIO11_LEVEL_HIGH [13:13]
/// No description
GPIO11_LEVEL_HIGH: u1 = 0,
/// GPIO11_EDGE_LOW [14:14]
/// No description
GPIO11_EDGE_LOW: u1 = 0,
/// GPIO11_EDGE_HIGH [15:15]
/// No description
GPIO11_EDGE_HIGH: u1 = 0,
/// GPIO12_LEVEL_LOW [16:16]
/// No description
GPIO12_LEVEL_LOW: u1 = 0,
/// GPIO12_LEVEL_HIGH [17:17]
/// No description
GPIO12_LEVEL_HIGH: u1 = 0,
/// GPIO12_EDGE_LOW [18:18]
/// No description
GPIO12_EDGE_LOW: u1 = 0,
/// GPIO12_EDGE_HIGH [19:19]
/// No description
GPIO12_EDGE_HIGH: u1 = 0,
/// GPIO13_LEVEL_LOW [20:20]
/// No description
GPIO13_LEVEL_LOW: u1 = 0,
/// GPIO13_LEVEL_HIGH [21:21]
/// No description
GPIO13_LEVEL_HIGH: u1 = 0,
/// GPIO13_EDGE_LOW [22:22]
/// No description
GPIO13_EDGE_LOW: u1 = 0,
/// GPIO13_EDGE_HIGH [23:23]
/// No description
GPIO13_EDGE_HIGH: u1 = 0,
/// GPIO14_LEVEL_LOW [24:24]
/// No description
GPIO14_LEVEL_LOW: u1 = 0,
/// GPIO14_LEVEL_HIGH [25:25]
/// No description
GPIO14_LEVEL_HIGH: u1 = 0,
/// GPIO14_EDGE_LOW [26:26]
/// No description
GPIO14_EDGE_LOW: u1 = 0,
/// GPIO14_EDGE_HIGH [27:27]
/// No description
GPIO14_EDGE_HIGH: u1 = 0,
/// GPIO15_LEVEL_LOW [28:28]
/// No description
GPIO15_LEVEL_LOW: u1 = 0,
/// GPIO15_LEVEL_HIGH [29:29]
/// No description
GPIO15_LEVEL_HIGH: u1 = 0,
/// GPIO15_EDGE_LOW [30:30]
/// No description
GPIO15_EDGE_LOW: u1 = 0,
/// GPIO15_EDGE_HIGH [31:31]
/// No description
GPIO15_EDGE_HIGH: u1 = 0,
};
/// Interrupt Enable for dormant_wake
pub const DORMANT_WAKE_INTE1 = Register(DORMANT_WAKE_INTE1_val).init(base_address + 0x164);
/// DORMANT_WAKE_INTE0
const DORMANT_WAKE_INTE0_val = packed struct {
/// GPIO0_LEVEL_LOW [0:0]
/// No description
GPIO0_LEVEL_LOW: u1 = 0,
/// GPIO0_LEVEL_HIGH [1:1]
/// No description
GPIO0_LEVEL_HIGH: u1 = 0,
/// GPIO0_EDGE_LOW [2:2]
/// No description
GPIO0_EDGE_LOW: u1 = 0,
/// GPIO0_EDGE_HIGH [3:3]
/// No description
GPIO0_EDGE_HIGH: u1 = 0,
/// GPIO1_LEVEL_LOW [4:4]
/// No description
GPIO1_LEVEL_LOW: u1 = 0,
/// GPIO1_LEVEL_HIGH [5:5]
/// No description
GPIO1_LEVEL_HIGH: u1 = 0,
/// GPIO1_EDGE_LOW [6:6]
/// No description
GPIO1_EDGE_LOW: u1 = 0,
/// GPIO1_EDGE_HIGH [7:7]
/// No description
GPIO1_EDGE_HIGH: u1 = 0,
/// GPIO2_LEVEL_LOW [8:8]
/// No description
GPIO2_LEVEL_LOW: u1 = 0,
/// GPIO2_LEVEL_HIGH [9:9]
/// No description
GPIO2_LEVEL_HIGH: u1 = 0,
/// GPIO2_EDGE_LOW [10:10]
/// No description
GPIO2_EDGE_LOW: u1 = 0,
/// GPIO2_EDGE_HIGH [11:11]
/// No description
GPIO2_EDGE_HIGH: u1 = 0,
/// GPIO3_LEVEL_LOW [12:12]
/// No description
GPIO3_LEVEL_LOW: u1 = 0,
/// GPIO3_LEVEL_HIGH [13:13]
/// No description
GPIO3_LEVEL_HIGH: u1 = 0,
/// GPIO3_EDGE_LOW [14:14]
/// No description
GPIO3_EDGE_LOW: u1 = 0,
/// GPIO3_EDGE_HIGH [15:15]
/// No description
GPIO3_EDGE_HIGH: u1 = 0,
/// GPIO4_LEVEL_LOW [16:16]
/// No description
GPIO4_LEVEL_LOW: u1 = 0,
/// GPIO4_LEVEL_HIGH [17:17]
/// No description
GPIO4_LEVEL_HIGH: u1 = 0,
/// GPIO4_EDGE_LOW [18:18]
/// No description
GPIO4_EDGE_LOW: u1 = 0,
/// GPIO4_EDGE_HIGH [19:19]
/// No description
GPIO4_EDGE_HIGH: u1 = 0,
/// GPIO5_LEVEL_LOW [20:20]
/// No description
GPIO5_LEVEL_LOW: u1 = 0,
/// GPIO5_LEVEL_HIGH [21:21]
/// No description
GPIO5_LEVEL_HIGH: u1 = 0,
/// GPIO5_EDGE_LOW [22:22]
/// No description
GPIO5_EDGE_LOW: u1 = 0,
/// GPIO5_EDGE_HIGH [23:23]
/// No description
GPIO5_EDGE_HIGH: u1 = 0,
/// GPIO6_LEVEL_LOW [24:24]
/// No description
GPIO6_LEVEL_LOW: u1 = 0,
/// GPIO6_LEVEL_HIGH [25:25]
/// No description
GPIO6_LEVEL_HIGH: u1 = 0,
/// GPIO6_EDGE_LOW [26:26]
/// No description
GPIO6_EDGE_LOW: u1 = 0,
/// GPIO6_EDGE_HIGH [27:27]
/// No description
GPIO6_EDGE_HIGH: u1 = 0,
/// GPIO7_LEVEL_LOW [28:28]
/// No description
GPIO7_LEVEL_LOW: u1 = 0,
/// GPIO7_LEVEL_HIGH [29:29]
/// No description
GPIO7_LEVEL_HIGH: u1 = 0,
/// GPIO7_EDGE_LOW [30:30]
/// No description
GPIO7_EDGE_LOW: u1 = 0,
/// GPIO7_EDGE_HIGH [31:31]
/// No description
GPIO7_EDGE_HIGH: u1 = 0,
};
/// Interrupt Enable for dormant_wake
pub const DORMANT_WAKE_INTE0 = Register(DORMANT_WAKE_INTE0_val).init(base_address + 0x160);
/// PROC1_INTS3
const PROC1_INTS3_val = packed struct {
/// GPIO24_LEVEL_LOW [0:0]
/// No description
GPIO24_LEVEL_LOW: u1 = 0,
/// GPIO24_LEVEL_HIGH [1:1]
/// No description
GPIO24_LEVEL_HIGH: u1 = 0,
/// GPIO24_EDGE_LOW [2:2]
/// No description
GPIO24_EDGE_LOW: u1 = 0,
/// GPIO24_EDGE_HIGH [3:3]
/// No description
GPIO24_EDGE_HIGH: u1 = 0,
/// GPIO25_LEVEL_LOW [4:4]
/// No description
GPIO25_LEVEL_LOW: u1 = 0,
/// GPIO25_LEVEL_HIGH [5:5]
/// No description
GPIO25_LEVEL_HIGH: u1 = 0,
/// GPIO25_EDGE_LOW [6:6]
/// No description
GPIO25_EDGE_LOW: u1 = 0,
/// GPIO25_EDGE_HIGH [7:7]
/// No description
GPIO25_EDGE_HIGH: u1 = 0,
/// GPIO26_LEVEL_LOW [8:8]
/// No description
GPIO26_LEVEL_LOW: u1 = 0,
/// GPIO26_LEVEL_HIGH [9:9]
/// No description
GPIO26_LEVEL_HIGH: u1 = 0,
/// GPIO26_EDGE_LOW [10:10]
/// No description
GPIO26_EDGE_LOW: u1 = 0,
/// GPIO26_EDGE_HIGH [11:11]
/// No description
GPIO26_EDGE_HIGH: u1 = 0,
/// GPIO27_LEVEL_LOW [12:12]
/// No description
GPIO27_LEVEL_LOW: u1 = 0,
/// GPIO27_LEVEL_HIGH [13:13]
/// No description
GPIO27_LEVEL_HIGH: u1 = 0,
/// GPIO27_EDGE_LOW [14:14]
/// No description
GPIO27_EDGE_LOW: u1 = 0,
/// GPIO27_EDGE_HIGH [15:15]
/// No description
GPIO27_EDGE_HIGH: u1 = 0,
/// GPIO28_LEVEL_LOW [16:16]
/// No description
GPIO28_LEVEL_LOW: u1 = 0,
/// GPIO28_LEVEL_HIGH [17:17]
/// No description
GPIO28_LEVEL_HIGH: u1 = 0,
/// GPIO28_EDGE_LOW [18:18]
/// No description
GPIO28_EDGE_LOW: u1 = 0,
/// GPIO28_EDGE_HIGH [19:19]
/// No description
GPIO28_EDGE_HIGH: u1 = 0,
/// GPIO29_LEVEL_LOW [20:20]
/// No description
GPIO29_LEVEL_LOW: u1 = 0,
/// GPIO29_LEVEL_HIGH [21:21]
/// No description
GPIO29_LEVEL_HIGH: u1 = 0,
/// GPIO29_EDGE_LOW [22:22]
/// No description
GPIO29_EDGE_LOW: u1 = 0,
/// GPIO29_EDGE_HIGH [23:23]
/// No description
GPIO29_EDGE_HIGH: u1 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Interrupt status after masking & forcing for proc1
pub const PROC1_INTS3 = Register(PROC1_INTS3_val).init(base_address + 0x15c);
/// PROC1_INTS2
const PROC1_INTS2_val = packed struct {
/// GPIO16_LEVEL_LOW [0:0]
/// No description
GPIO16_LEVEL_LOW: u1 = 0,
/// GPIO16_LEVEL_HIGH [1:1]
/// No description
GPIO16_LEVEL_HIGH: u1 = 0,
/// GPIO16_EDGE_LOW [2:2]
/// No description
GPIO16_EDGE_LOW: u1 = 0,
/// GPIO16_EDGE_HIGH [3:3]
/// No description
GPIO16_EDGE_HIGH: u1 = 0,
/// GPIO17_LEVEL_LOW [4:4]
/// No description
GPIO17_LEVEL_LOW: u1 = 0,
/// GPIO17_LEVEL_HIGH [5:5]
/// No description
GPIO17_LEVEL_HIGH: u1 = 0,
/// GPIO17_EDGE_LOW [6:6]
/// No description
GPIO17_EDGE_LOW: u1 = 0,
/// GPIO17_EDGE_HIGH [7:7]
/// No description
GPIO17_EDGE_HIGH: u1 = 0,
/// GPIO18_LEVEL_LOW [8:8]
/// No description
GPIO18_LEVEL_LOW: u1 = 0,
/// GPIO18_LEVEL_HIGH [9:9]
/// No description
GPIO18_LEVEL_HIGH: u1 = 0,
/// GPIO18_EDGE_LOW [10:10]
/// No description
GPIO18_EDGE_LOW: u1 = 0,
/// GPIO18_EDGE_HIGH [11:11]
/// No description
GPIO18_EDGE_HIGH: u1 = 0,
/// GPIO19_LEVEL_LOW [12:12]
/// No description
GPIO19_LEVEL_LOW: u1 = 0,
/// GPIO19_LEVEL_HIGH [13:13]
/// No description
GPIO19_LEVEL_HIGH: u1 = 0,
/// GPIO19_EDGE_LOW [14:14]
/// No description
GPIO19_EDGE_LOW: u1 = 0,
/// GPIO19_EDGE_HIGH [15:15]
/// No description
GPIO19_EDGE_HIGH: u1 = 0,
/// GPIO20_LEVEL_LOW [16:16]
/// No description
GPIO20_LEVEL_LOW: u1 = 0,
/// GPIO20_LEVEL_HIGH [17:17]
/// No description
GPIO20_LEVEL_HIGH: u1 = 0,
/// GPIO20_EDGE_LOW [18:18]
/// No description
GPIO20_EDGE_LOW: u1 = 0,
/// GPIO20_EDGE_HIGH [19:19]
/// No description
GPIO20_EDGE_HIGH: u1 = 0,
/// GPIO21_LEVEL_LOW [20:20]
/// No description
GPIO21_LEVEL_LOW: u1 = 0,
/// GPIO21_LEVEL_HIGH [21:21]
/// No description
GPIO21_LEVEL_HIGH: u1 = 0,
/// GPIO21_EDGE_LOW [22:22]
/// No description
GPIO21_EDGE_LOW: u1 = 0,
/// GPIO21_EDGE_HIGH [23:23]
/// No description
GPIO21_EDGE_HIGH: u1 = 0,
/// GPIO22_LEVEL_LOW [24:24]
/// No description
GPIO22_LEVEL_LOW: u1 = 0,
/// GPIO22_LEVEL_HIGH [25:25]
/// No description
GPIO22_LEVEL_HIGH: u1 = 0,
/// GPIO22_EDGE_LOW [26:26]
/// No description
GPIO22_EDGE_LOW: u1 = 0,
/// GPIO22_EDGE_HIGH [27:27]
/// No description
GPIO22_EDGE_HIGH: u1 = 0,
/// GPIO23_LEVEL_LOW [28:28]
/// No description
GPIO23_LEVEL_LOW: u1 = 0,
/// GPIO23_LEVEL_HIGH [29:29]
/// No description
GPIO23_LEVEL_HIGH: u1 = 0,
/// GPIO23_EDGE_LOW [30:30]
/// No description
GPIO23_EDGE_LOW: u1 = 0,
/// GPIO23_EDGE_HIGH [31:31]
/// No description
GPIO23_EDGE_HIGH: u1 = 0,
};
/// Interrupt status after masking & forcing for proc1
pub const PROC1_INTS2 = Register(PROC1_INTS2_val).init(base_address + 0x158);
/// PROC1_INTS1
const PROC1_INTS1_val = packed struct {
/// GPIO8_LEVEL_LOW [0:0]
/// No description
GPIO8_LEVEL_LOW: u1 = 0,
/// GPIO8_LEVEL_HIGH [1:1]
/// No description
GPIO8_LEVEL_HIGH: u1 = 0,
/// GPIO8_EDGE_LOW [2:2]
/// No description
GPIO8_EDGE_LOW: u1 = 0,
/// GPIO8_EDGE_HIGH [3:3]
/// No description
GPIO8_EDGE_HIGH: u1 = 0,
/// GPIO9_LEVEL_LOW [4:4]
/// No description
GPIO9_LEVEL_LOW: u1 = 0,
/// GPIO9_LEVEL_HIGH [5:5]
/// No description
GPIO9_LEVEL_HIGH: u1 = 0,
/// GPIO9_EDGE_LOW [6:6]
/// No description
GPIO9_EDGE_LOW: u1 = 0,
/// GPIO9_EDGE_HIGH [7:7]
/// No description
GPIO9_EDGE_HIGH: u1 = 0,
/// GPIO10_LEVEL_LOW [8:8]
/// No description
GPIO10_LEVEL_LOW: u1 = 0,
/// GPIO10_LEVEL_HIGH [9:9]
/// No description
GPIO10_LEVEL_HIGH: u1 = 0,
/// GPIO10_EDGE_LOW [10:10]
/// No description
GPIO10_EDGE_LOW: u1 = 0,
/// GPIO10_EDGE_HIGH [11:11]
/// No description
GPIO10_EDGE_HIGH: u1 = 0,
/// GPIO11_LEVEL_LOW [12:12]
/// No description
GPIO11_LEVEL_LOW: u1 = 0,
/// GPIO11_LEVEL_HIGH [13:13]
/// No description
GPIO11_LEVEL_HIGH: u1 = 0,
/// GPIO11_EDGE_LOW [14:14]
/// No description
GPIO11_EDGE_LOW: u1 = 0,
/// GPIO11_EDGE_HIGH [15:15]
/// No description
GPIO11_EDGE_HIGH: u1 = 0,
/// GPIO12_LEVEL_LOW [16:16]
/// No description
GPIO12_LEVEL_LOW: u1 = 0,
/// GPIO12_LEVEL_HIGH [17:17]
/// No description
GPIO12_LEVEL_HIGH: u1 = 0,
/// GPIO12_EDGE_LOW [18:18]
/// No description
GPIO12_EDGE_LOW: u1 = 0,
/// GPIO12_EDGE_HIGH [19:19]
/// No description
GPIO12_EDGE_HIGH: u1 = 0,
/// GPIO13_LEVEL_LOW [20:20]
/// No description
GPIO13_LEVEL_LOW: u1 = 0,
/// GPIO13_LEVEL_HIGH [21:21]
/// No description
GPIO13_LEVEL_HIGH: u1 = 0,
/// GPIO13_EDGE_LOW [22:22]
/// No description
GPIO13_EDGE_LOW: u1 = 0,
/// GPIO13_EDGE_HIGH [23:23]
/// No description
GPIO13_EDGE_HIGH: u1 = 0,
/// GPIO14_LEVEL_LOW [24:24]
/// No description
GPIO14_LEVEL_LOW: u1 = 0,
/// GPIO14_LEVEL_HIGH [25:25]
/// No description
GPIO14_LEVEL_HIGH: u1 = 0,
/// GPIO14_EDGE_LOW [26:26]
/// No description
GPIO14_EDGE_LOW: u1 = 0,
/// GPIO14_EDGE_HIGH [27:27]
/// No description
GPIO14_EDGE_HIGH: u1 = 0,
/// GPIO15_LEVEL_LOW [28:28]
/// No description
GPIO15_LEVEL_LOW: u1 = 0,
/// GPIO15_LEVEL_HIGH [29:29]
/// No description
GPIO15_LEVEL_HIGH: u1 = 0,
/// GPIO15_EDGE_LOW [30:30]
/// No description
GPIO15_EDGE_LOW: u1 = 0,
/// GPIO15_EDGE_HIGH [31:31]
/// No description
GPIO15_EDGE_HIGH: u1 = 0,
};
/// Interrupt status after masking & forcing for proc1
pub const PROC1_INTS1 = Register(PROC1_INTS1_val).init(base_address + 0x154);
/// PROC1_INTS0
const PROC1_INTS0_val = packed struct {
/// GPIO0_LEVEL_LOW [0:0]
/// No description
GPIO0_LEVEL_LOW: u1 = 0,
/// GPIO0_LEVEL_HIGH [1:1]
/// No description
GPIO0_LEVEL_HIGH: u1 = 0,
/// GPIO0_EDGE_LOW [2:2]
/// No description
GPIO0_EDGE_LOW: u1 = 0,
/// GPIO0_EDGE_HIGH [3:3]
/// No description
GPIO0_EDGE_HIGH: u1 = 0,
/// GPIO1_LEVEL_LOW [4:4]
/// No description
GPIO1_LEVEL_LOW: u1 = 0,
/// GPIO1_LEVEL_HIGH [5:5]
/// No description
GPIO1_LEVEL_HIGH: u1 = 0,
/// GPIO1_EDGE_LOW [6:6]
/// No description
GPIO1_EDGE_LOW: u1 = 0,
/// GPIO1_EDGE_HIGH [7:7]
/// No description
GPIO1_EDGE_HIGH: u1 = 0,
/// GPIO2_LEVEL_LOW [8:8]
/// No description
GPIO2_LEVEL_LOW: u1 = 0,
/// GPIO2_LEVEL_HIGH [9:9]
/// No description
GPIO2_LEVEL_HIGH: u1 = 0,
/// GPIO2_EDGE_LOW [10:10]
/// No description
GPIO2_EDGE_LOW: u1 = 0,
/// GPIO2_EDGE_HIGH [11:11]
/// No description
GPIO2_EDGE_HIGH: u1 = 0,
/// GPIO3_LEVEL_LOW [12:12]
/// No description
GPIO3_LEVEL_LOW: u1 = 0,
/// GPIO3_LEVEL_HIGH [13:13]
/// No description
GPIO3_LEVEL_HIGH: u1 = 0,
/// GPIO3_EDGE_LOW [14:14]
/// No description
GPIO3_EDGE_LOW: u1 = 0,
/// GPIO3_EDGE_HIGH [15:15]
/// No description
GPIO3_EDGE_HIGH: u1 = 0,
/// GPIO4_LEVEL_LOW [16:16]
/// No description
GPIO4_LEVEL_LOW: u1 = 0,
/// GPIO4_LEVEL_HIGH [17:17]
/// No description
GPIO4_LEVEL_HIGH: u1 = 0,
/// GPIO4_EDGE_LOW [18:18]
/// No description
GPIO4_EDGE_LOW: u1 = 0,
/// GPIO4_EDGE_HIGH [19:19]
/// No description
GPIO4_EDGE_HIGH: u1 = 0,
/// GPIO5_LEVEL_LOW [20:20]
/// No description
GPIO5_LEVEL_LOW: u1 = 0,
/// GPIO5_LEVEL_HIGH [21:21]
/// No description
GPIO5_LEVEL_HIGH: u1 = 0,
/// GPIO5_EDGE_LOW [22:22]
/// No description
GPIO5_EDGE_LOW: u1 = 0,
/// GPIO5_EDGE_HIGH [23:23]
/// No description
GPIO5_EDGE_HIGH: u1 = 0,
/// GPIO6_LEVEL_LOW [24:24]
/// No description
GPIO6_LEVEL_LOW: u1 = 0,
/// GPIO6_LEVEL_HIGH [25:25]
/// No description
GPIO6_LEVEL_HIGH: u1 = 0,
/// GPIO6_EDGE_LOW [26:26]
/// No description
GPIO6_EDGE_LOW: u1 = 0,
/// GPIO6_EDGE_HIGH [27:27]
/// No description
GPIO6_EDGE_HIGH: u1 = 0,
/// GPIO7_LEVEL_LOW [28:28]
/// No description
GPIO7_LEVEL_LOW: u1 = 0,
/// GPIO7_LEVEL_HIGH [29:29]
/// No description
GPIO7_LEVEL_HIGH: u1 = 0,
/// GPIO7_EDGE_LOW [30:30]
/// No description
GPIO7_EDGE_LOW: u1 = 0,
/// GPIO7_EDGE_HIGH [31:31]
/// No description
GPIO7_EDGE_HIGH: u1 = 0,
};
/// Interrupt status after masking & forcing for proc1
pub const PROC1_INTS0 = Register(PROC1_INTS0_val).init(base_address + 0x150);
/// PROC1_INTF3
const PROC1_INTF3_val = packed struct {
/// GPIO24_LEVEL_LOW [0:0]
/// No description
GPIO24_LEVEL_LOW: u1 = 0,
/// GPIO24_LEVEL_HIGH [1:1]
/// No description
GPIO24_LEVEL_HIGH: u1 = 0,
/// GPIO24_EDGE_LOW [2:2]
/// No description
GPIO24_EDGE_LOW: u1 = 0,
/// GPIO24_EDGE_HIGH [3:3]
/// No description
GPIO24_EDGE_HIGH: u1 = 0,
/// GPIO25_LEVEL_LOW [4:4]
/// No description
GPIO25_LEVEL_LOW: u1 = 0,
/// GPIO25_LEVEL_HIGH [5:5]
/// No description
GPIO25_LEVEL_HIGH: u1 = 0,
/// GPIO25_EDGE_LOW [6:6]
/// No description
GPIO25_EDGE_LOW: u1 = 0,
/// GPIO25_EDGE_HIGH [7:7]
/// No description
GPIO25_EDGE_HIGH: u1 = 0,
/// GPIO26_LEVEL_LOW [8:8]
/// No description
GPIO26_LEVEL_LOW: u1 = 0,
/// GPIO26_LEVEL_HIGH [9:9]
/// No description
GPIO26_LEVEL_HIGH: u1 = 0,
/// GPIO26_EDGE_LOW [10:10]
/// No description
GPIO26_EDGE_LOW: u1 = 0,
/// GPIO26_EDGE_HIGH [11:11]
/// No description
GPIO26_EDGE_HIGH: u1 = 0,
/// GPIO27_LEVEL_LOW [12:12]
/// No description
GPIO27_LEVEL_LOW: u1 = 0,
/// GPIO27_LEVEL_HIGH [13:13]
/// No description
GPIO27_LEVEL_HIGH: u1 = 0,
/// GPIO27_EDGE_LOW [14:14]
/// No description
GPIO27_EDGE_LOW: u1 = 0,
/// GPIO27_EDGE_HIGH [15:15]
/// No description
GPIO27_EDGE_HIGH: u1 = 0,
/// GPIO28_LEVEL_LOW [16:16]
/// No description
GPIO28_LEVEL_LOW: u1 = 0,
/// GPIO28_LEVEL_HIGH [17:17]
/// No description
GPIO28_LEVEL_HIGH: u1 = 0,
/// GPIO28_EDGE_LOW [18:18]
/// No description
GPIO28_EDGE_LOW: u1 = 0,
/// GPIO28_EDGE_HIGH [19:19]
/// No description
GPIO28_EDGE_HIGH: u1 = 0,
/// GPIO29_LEVEL_LOW [20:20]
/// No description
GPIO29_LEVEL_LOW: u1 = 0,
/// GPIO29_LEVEL_HIGH [21:21]
/// No description
GPIO29_LEVEL_HIGH: u1 = 0,
/// GPIO29_EDGE_LOW [22:22]
/// No description
GPIO29_EDGE_LOW: u1 = 0,
/// GPIO29_EDGE_HIGH [23:23]
/// No description
GPIO29_EDGE_HIGH: u1 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Interrupt Force for proc1
pub const PROC1_INTF3 = Register(PROC1_INTF3_val).init(base_address + 0x14c);
/// PROC1_INTF2
const PROC1_INTF2_val = packed struct {
/// GPIO16_LEVEL_LOW [0:0]
/// No description
GPIO16_LEVEL_LOW: u1 = 0,
/// GPIO16_LEVEL_HIGH [1:1]
/// No description
GPIO16_LEVEL_HIGH: u1 = 0,
/// GPIO16_EDGE_LOW [2:2]
/// No description
GPIO16_EDGE_LOW: u1 = 0,
/// GPIO16_EDGE_HIGH [3:3]
/// No description
GPIO16_EDGE_HIGH: u1 = 0,
/// GPIO17_LEVEL_LOW [4:4]
/// No description
GPIO17_LEVEL_LOW: u1 = 0,
/// GPIO17_LEVEL_HIGH [5:5]
/// No description
GPIO17_LEVEL_HIGH: u1 = 0,
/// GPIO17_EDGE_LOW [6:6]
/// No description
GPIO17_EDGE_LOW: u1 = 0,
/// GPIO17_EDGE_HIGH [7:7]
/// No description
GPIO17_EDGE_HIGH: u1 = 0,
/// GPIO18_LEVEL_LOW [8:8]
/// No description
GPIO18_LEVEL_LOW: u1 = 0,
/// GPIO18_LEVEL_HIGH [9:9]
/// No description
GPIO18_LEVEL_HIGH: u1 = 0,
/// GPIO18_EDGE_LOW [10:10]
/// No description
GPIO18_EDGE_LOW: u1 = 0,
/// GPIO18_EDGE_HIGH [11:11]
/// No description
GPIO18_EDGE_HIGH: u1 = 0,
/// GPIO19_LEVEL_LOW [12:12]
/// No description
GPIO19_LEVEL_LOW: u1 = 0,
/// GPIO19_LEVEL_HIGH [13:13]
/// No description
GPIO19_LEVEL_HIGH: u1 = 0,
/// GPIO19_EDGE_LOW [14:14]
/// No description
GPIO19_EDGE_LOW: u1 = 0,
/// GPIO19_EDGE_HIGH [15:15]
/// No description
GPIO19_EDGE_HIGH: u1 = 0,
/// GPIO20_LEVEL_LOW [16:16]
/// No description
GPIO20_LEVEL_LOW: u1 = 0,
/// GPIO20_LEVEL_HIGH [17:17]
/// No description
GPIO20_LEVEL_HIGH: u1 = 0,
/// GPIO20_EDGE_LOW [18:18]
/// No description
GPIO20_EDGE_LOW: u1 = 0,
/// GPIO20_EDGE_HIGH [19:19]
/// No description
GPIO20_EDGE_HIGH: u1 = 0,
/// GPIO21_LEVEL_LOW [20:20]
/// No description
GPIO21_LEVEL_LOW: u1 = 0,
/// GPIO21_LEVEL_HIGH [21:21]
/// No description
GPIO21_LEVEL_HIGH: u1 = 0,
/// GPIO21_EDGE_LOW [22:22]
/// No description
GPIO21_EDGE_LOW: u1 = 0,
/// GPIO21_EDGE_HIGH [23:23]
/// No description
GPIO21_EDGE_HIGH: u1 = 0,
/// GPIO22_LEVEL_LOW [24:24]
/// No description
GPIO22_LEVEL_LOW: u1 = 0,
/// GPIO22_LEVEL_HIGH [25:25]
/// No description
GPIO22_LEVEL_HIGH: u1 = 0,
/// GPIO22_EDGE_LOW [26:26]
/// No description
GPIO22_EDGE_LOW: u1 = 0,
/// GPIO22_EDGE_HIGH [27:27]
/// No description
GPIO22_EDGE_HIGH: u1 = 0,
/// GPIO23_LEVEL_LOW [28:28]
/// No description
GPIO23_LEVEL_LOW: u1 = 0,
/// GPIO23_LEVEL_HIGH [29:29]
/// No description
GPIO23_LEVEL_HIGH: u1 = 0,
/// GPIO23_EDGE_LOW [30:30]
/// No description
GPIO23_EDGE_LOW: u1 = 0,
/// GPIO23_EDGE_HIGH [31:31]
/// No description
GPIO23_EDGE_HIGH: u1 = 0,
};
/// Interrupt Force for proc1
pub const PROC1_INTF2 = Register(PROC1_INTF2_val).init(base_address + 0x148);
/// PROC1_INTF1
const PROC1_INTF1_val = packed struct {
/// GPIO8_LEVEL_LOW [0:0]
/// No description
GPIO8_LEVEL_LOW: u1 = 0,
/// GPIO8_LEVEL_HIGH [1:1]
/// No description
GPIO8_LEVEL_HIGH: u1 = 0,
/// GPIO8_EDGE_LOW [2:2]
/// No description
GPIO8_EDGE_LOW: u1 = 0,
/// GPIO8_EDGE_HIGH [3:3]
/// No description
GPIO8_EDGE_HIGH: u1 = 0,
/// GPIO9_LEVEL_LOW [4:4]
/// No description
GPIO9_LEVEL_LOW: u1 = 0,
/// GPIO9_LEVEL_HIGH [5:5]
/// No description
GPIO9_LEVEL_HIGH: u1 = 0,
/// GPIO9_EDGE_LOW [6:6]
/// No description
GPIO9_EDGE_LOW: u1 = 0,
/// GPIO9_EDGE_HIGH [7:7]
/// No description
GPIO9_EDGE_HIGH: u1 = 0,
/// GPIO10_LEVEL_LOW [8:8]
/// No description
GPIO10_LEVEL_LOW: u1 = 0,
/// GPIO10_LEVEL_HIGH [9:9]
/// No description
GPIO10_LEVEL_HIGH: u1 = 0,
/// GPIO10_EDGE_LOW [10:10]
/// No description
GPIO10_EDGE_LOW: u1 = 0,
/// GPIO10_EDGE_HIGH [11:11]
/// No description
GPIO10_EDGE_HIGH: u1 = 0,
/// GPIO11_LEVEL_LOW [12:12]
/// No description
GPIO11_LEVEL_LOW: u1 = 0,
/// GPIO11_LEVEL_HIGH [13:13]
/// No description
GPIO11_LEVEL_HIGH: u1 = 0,
/// GPIO11_EDGE_LOW [14:14]
/// No description
GPIO11_EDGE_LOW: u1 = 0,
/// GPIO11_EDGE_HIGH [15:15]
/// No description
GPIO11_EDGE_HIGH: u1 = 0,
/// GPIO12_LEVEL_LOW [16:16]
/// No description
GPIO12_LEVEL_LOW: u1 = 0,
/// GPIO12_LEVEL_HIGH [17:17]
/// No description
GPIO12_LEVEL_HIGH: u1 = 0,
/// GPIO12_EDGE_LOW [18:18]
/// No description
GPIO12_EDGE_LOW: u1 = 0,
/// GPIO12_EDGE_HIGH [19:19]
/// No description
GPIO12_EDGE_HIGH: u1 = 0,
/// GPIO13_LEVEL_LOW [20:20]
/// No description
GPIO13_LEVEL_LOW: u1 = 0,
/// GPIO13_LEVEL_HIGH [21:21]
/// No description
GPIO13_LEVEL_HIGH: u1 = 0,
/// GPIO13_EDGE_LOW [22:22]
/// No description
GPIO13_EDGE_LOW: u1 = 0,
/// GPIO13_EDGE_HIGH [23:23]
/// No description
GPIO13_EDGE_HIGH: u1 = 0,
/// GPIO14_LEVEL_LOW [24:24]
/// No description
GPIO14_LEVEL_LOW: u1 = 0,
/// GPIO14_LEVEL_HIGH [25:25]
/// No description
GPIO14_LEVEL_HIGH: u1 = 0,
/// GPIO14_EDGE_LOW [26:26]
/// No description
GPIO14_EDGE_LOW: u1 = 0,
/// GPIO14_EDGE_HIGH [27:27]
/// No description
GPIO14_EDGE_HIGH: u1 = 0,
/// GPIO15_LEVEL_LOW [28:28]
/// No description
GPIO15_LEVEL_LOW: u1 = 0,
/// GPIO15_LEVEL_HIGH [29:29]
/// No description
GPIO15_LEVEL_HIGH: u1 = 0,
/// GPIO15_EDGE_LOW [30:30]
/// No description
GPIO15_EDGE_LOW: u1 = 0,
/// GPIO15_EDGE_HIGH [31:31]
/// No description
GPIO15_EDGE_HIGH: u1 = 0,
};
/// Interrupt Force for proc1
pub const PROC1_INTF1 = Register(PROC1_INTF1_val).init(base_address + 0x144);
/// PROC1_INTF0
const PROC1_INTF0_val = packed struct {
/// GPIO0_LEVEL_LOW [0:0]
/// No description
GPIO0_LEVEL_LOW: u1 = 0,
/// GPIO0_LEVEL_HIGH [1:1]
/// No description
GPIO0_LEVEL_HIGH: u1 = 0,
/// GPIO0_EDGE_LOW [2:2]
/// No description
GPIO0_EDGE_LOW: u1 = 0,
/// GPIO0_EDGE_HIGH [3:3]
/// No description
GPIO0_EDGE_HIGH: u1 = 0,
/// GPIO1_LEVEL_LOW [4:4]
/// No description
GPIO1_LEVEL_LOW: u1 = 0,
/// GPIO1_LEVEL_HIGH [5:5]
/// No description
GPIO1_LEVEL_HIGH: u1 = 0,
/// GPIO1_EDGE_LOW [6:6]
/// No description
GPIO1_EDGE_LOW: u1 = 0,
/// GPIO1_EDGE_HIGH [7:7]
/// No description
GPIO1_EDGE_HIGH: u1 = 0,
/// GPIO2_LEVEL_LOW [8:8]
/// No description
GPIO2_LEVEL_LOW: u1 = 0,
/// GPIO2_LEVEL_HIGH [9:9]
/// No description
GPIO2_LEVEL_HIGH: u1 = 0,
/// GPIO2_EDGE_LOW [10:10]
/// No description
GPIO2_EDGE_LOW: u1 = 0,
/// GPIO2_EDGE_HIGH [11:11]
/// No description
GPIO2_EDGE_HIGH: u1 = 0,
/// GPIO3_LEVEL_LOW [12:12]
/// No description
GPIO3_LEVEL_LOW: u1 = 0,
/// GPIO3_LEVEL_HIGH [13:13]
/// No description
GPIO3_LEVEL_HIGH: u1 = 0,
/// GPIO3_EDGE_LOW [14:14]
/// No description
GPIO3_EDGE_LOW: u1 = 0,
/// GPIO3_EDGE_HIGH [15:15]
/// No description
GPIO3_EDGE_HIGH: u1 = 0,
/// GPIO4_LEVEL_LOW [16:16]
/// No description
GPIO4_LEVEL_LOW: u1 = 0,
/// GPIO4_LEVEL_HIGH [17:17]
/// No description
GPIO4_LEVEL_HIGH: u1 = 0,
/// GPIO4_EDGE_LOW [18:18]
/// No description
GPIO4_EDGE_LOW: u1 = 0,
/// GPIO4_EDGE_HIGH [19:19]
/// No description
GPIO4_EDGE_HIGH: u1 = 0,
/// GPIO5_LEVEL_LOW [20:20]
/// No description
GPIO5_LEVEL_LOW: u1 = 0,
/// GPIO5_LEVEL_HIGH [21:21]
/// No description
GPIO5_LEVEL_HIGH: u1 = 0,
/// GPIO5_EDGE_LOW [22:22]
/// No description
GPIO5_EDGE_LOW: u1 = 0,
/// GPIO5_EDGE_HIGH [23:23]
/// No description
GPIO5_EDGE_HIGH: u1 = 0,
/// GPIO6_LEVEL_LOW [24:24]
/// No description
GPIO6_LEVEL_LOW: u1 = 0,
/// GPIO6_LEVEL_HIGH [25:25]
/// No description
GPIO6_LEVEL_HIGH: u1 = 0,
/// GPIO6_EDGE_LOW [26:26]
/// No description
GPIO6_EDGE_LOW: u1 = 0,
/// GPIO6_EDGE_HIGH [27:27]
/// No description
GPIO6_EDGE_HIGH: u1 = 0,
/// GPIO7_LEVEL_LOW [28:28]
/// No description
GPIO7_LEVEL_LOW: u1 = 0,
/// GPIO7_LEVEL_HIGH [29:29]
/// No description
GPIO7_LEVEL_HIGH: u1 = 0,
/// GPIO7_EDGE_LOW [30:30]
/// No description
GPIO7_EDGE_LOW: u1 = 0,
/// GPIO7_EDGE_HIGH [31:31]
/// No description
GPIO7_EDGE_HIGH: u1 = 0,
};
/// Interrupt Force for proc1
pub const PROC1_INTF0 = Register(PROC1_INTF0_val).init(base_address + 0x140);
/// PROC1_INTE3
const PROC1_INTE3_val = packed struct {
/// GPIO24_LEVEL_LOW [0:0]
/// No description
GPIO24_LEVEL_LOW: u1 = 0,
/// GPIO24_LEVEL_HIGH [1:1]
/// No description
GPIO24_LEVEL_HIGH: u1 = 0,
/// GPIO24_EDGE_LOW [2:2]
/// No description
GPIO24_EDGE_LOW: u1 = 0,
/// GPIO24_EDGE_HIGH [3:3]
/// No description
GPIO24_EDGE_HIGH: u1 = 0,
/// GPIO25_LEVEL_LOW [4:4]
/// No description
GPIO25_LEVEL_LOW: u1 = 0,
/// GPIO25_LEVEL_HIGH [5:5]
/// No description
GPIO25_LEVEL_HIGH: u1 = 0,
/// GPIO25_EDGE_LOW [6:6]
/// No description
GPIO25_EDGE_LOW: u1 = 0,
/// GPIO25_EDGE_HIGH [7:7]
/// No description
GPIO25_EDGE_HIGH: u1 = 0,
/// GPIO26_LEVEL_LOW [8:8]
/// No description
GPIO26_LEVEL_LOW: u1 = 0,
/// GPIO26_LEVEL_HIGH [9:9]
/// No description
GPIO26_LEVEL_HIGH: u1 = 0,
/// GPIO26_EDGE_LOW [10:10]
/// No description
GPIO26_EDGE_LOW: u1 = 0,
/// GPIO26_EDGE_HIGH [11:11]
/// No description
GPIO26_EDGE_HIGH: u1 = 0,
/// GPIO27_LEVEL_LOW [12:12]
/// No description
GPIO27_LEVEL_LOW: u1 = 0,
/// GPIO27_LEVEL_HIGH [13:13]
/// No description
GPIO27_LEVEL_HIGH: u1 = 0,
/// GPIO27_EDGE_LOW [14:14]
/// No description
GPIO27_EDGE_LOW: u1 = 0,
/// GPIO27_EDGE_HIGH [15:15]
/// No description
GPIO27_EDGE_HIGH: u1 = 0,
/// GPIO28_LEVEL_LOW [16:16]
/// No description
GPIO28_LEVEL_LOW: u1 = 0,
/// GPIO28_LEVEL_HIGH [17:17]
/// No description
GPIO28_LEVEL_HIGH: u1 = 0,
/// GPIO28_EDGE_LOW [18:18]
/// No description
GPIO28_EDGE_LOW: u1 = 0,
/// GPIO28_EDGE_HIGH [19:19]
/// No description
GPIO28_EDGE_HIGH: u1 = 0,
/// GPIO29_LEVEL_LOW [20:20]
/// No description
GPIO29_LEVEL_LOW: u1 = 0,
/// GPIO29_LEVEL_HIGH [21:21]
/// No description
GPIO29_LEVEL_HIGH: u1 = 0,
/// GPIO29_EDGE_LOW [22:22]
/// No description
GPIO29_EDGE_LOW: u1 = 0,
/// GPIO29_EDGE_HIGH [23:23]
/// No description
GPIO29_EDGE_HIGH: u1 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Interrupt Enable for proc1
pub const PROC1_INTE3 = Register(PROC1_INTE3_val).init(base_address + 0x13c);
/// PROC1_INTE2
const PROC1_INTE2_val = packed struct {
/// GPIO16_LEVEL_LOW [0:0]
/// No description
GPIO16_LEVEL_LOW: u1 = 0,
/// GPIO16_LEVEL_HIGH [1:1]
/// No description
GPIO16_LEVEL_HIGH: u1 = 0,
/// GPIO16_EDGE_LOW [2:2]
/// No description
GPIO16_EDGE_LOW: u1 = 0,
/// GPIO16_EDGE_HIGH [3:3]
/// No description
GPIO16_EDGE_HIGH: u1 = 0,
/// GPIO17_LEVEL_LOW [4:4]
/// No description
GPIO17_LEVEL_LOW: u1 = 0,
/// GPIO17_LEVEL_HIGH [5:5]
/// No description
GPIO17_LEVEL_HIGH: u1 = 0,
/// GPIO17_EDGE_LOW [6:6]
/// No description
GPIO17_EDGE_LOW: u1 = 0,
/// GPIO17_EDGE_HIGH [7:7]
/// No description
GPIO17_EDGE_HIGH: u1 = 0,
/// GPIO18_LEVEL_LOW [8:8]
/// No description
GPIO18_LEVEL_LOW: u1 = 0,
/// GPIO18_LEVEL_HIGH [9:9]
/// No description
GPIO18_LEVEL_HIGH: u1 = 0,
/// GPIO18_EDGE_LOW [10:10]
/// No description
GPIO18_EDGE_LOW: u1 = 0,
/// GPIO18_EDGE_HIGH [11:11]
/// No description
GPIO18_EDGE_HIGH: u1 = 0,
/// GPIO19_LEVEL_LOW [12:12]
/// No description
GPIO19_LEVEL_LOW: u1 = 0,
/// GPIO19_LEVEL_HIGH [13:13]
/// No description
GPIO19_LEVEL_HIGH: u1 = 0,
/// GPIO19_EDGE_LOW [14:14]
/// No description
GPIO19_EDGE_LOW: u1 = 0,
/// GPIO19_EDGE_HIGH [15:15]
/// No description
GPIO19_EDGE_HIGH: u1 = 0,
/// GPIO20_LEVEL_LOW [16:16]
/// No description
GPIO20_LEVEL_LOW: u1 = 0,
/// GPIO20_LEVEL_HIGH [17:17]
/// No description
GPIO20_LEVEL_HIGH: u1 = 0,
/// GPIO20_EDGE_LOW [18:18]
/// No description
GPIO20_EDGE_LOW: u1 = 0,
/// GPIO20_EDGE_HIGH [19:19]
/// No description
GPIO20_EDGE_HIGH: u1 = 0,
/// GPIO21_LEVEL_LOW [20:20]
/// No description
GPIO21_LEVEL_LOW: u1 = 0,
/// GPIO21_LEVEL_HIGH [21:21]
/// No description
GPIO21_LEVEL_HIGH: u1 = 0,
/// GPIO21_EDGE_LOW [22:22]
/// No description
GPIO21_EDGE_LOW: u1 = 0,
/// GPIO21_EDGE_HIGH [23:23]
/// No description
GPIO21_EDGE_HIGH: u1 = 0,
/// GPIO22_LEVEL_LOW [24:24]
/// No description
GPIO22_LEVEL_LOW: u1 = 0,
/// GPIO22_LEVEL_HIGH [25:25]
/// No description
GPIO22_LEVEL_HIGH: u1 = 0,
/// GPIO22_EDGE_LOW [26:26]
/// No description
GPIO22_EDGE_LOW: u1 = 0,
/// GPIO22_EDGE_HIGH [27:27]
/// No description
GPIO22_EDGE_HIGH: u1 = 0,
/// GPIO23_LEVEL_LOW [28:28]
/// No description
GPIO23_LEVEL_LOW: u1 = 0,
/// GPIO23_LEVEL_HIGH [29:29]
/// No description
GPIO23_LEVEL_HIGH: u1 = 0,
/// GPIO23_EDGE_LOW [30:30]
/// No description
GPIO23_EDGE_LOW: u1 = 0,
/// GPIO23_EDGE_HIGH [31:31]
/// No description
GPIO23_EDGE_HIGH: u1 = 0,
};
/// Interrupt Enable for proc1
pub const PROC1_INTE2 = Register(PROC1_INTE2_val).init(base_address + 0x138);
/// PROC1_INTE1
const PROC1_INTE1_val = packed struct {
/// GPIO8_LEVEL_LOW [0:0]
/// No description
GPIO8_LEVEL_LOW: u1 = 0,
/// GPIO8_LEVEL_HIGH [1:1]
/// No description
GPIO8_LEVEL_HIGH: u1 = 0,
/// GPIO8_EDGE_LOW [2:2]
/// No description
GPIO8_EDGE_LOW: u1 = 0,
/// GPIO8_EDGE_HIGH [3:3]
/// No description
GPIO8_EDGE_HIGH: u1 = 0,
/// GPIO9_LEVEL_LOW [4:4]
/// No description
GPIO9_LEVEL_LOW: u1 = 0,
/// GPIO9_LEVEL_HIGH [5:5]
/// No description
GPIO9_LEVEL_HIGH: u1 = 0,
/// GPIO9_EDGE_LOW [6:6]
/// No description
GPIO9_EDGE_LOW: u1 = 0,
/// GPIO9_EDGE_HIGH [7:7]
/// No description
GPIO9_EDGE_HIGH: u1 = 0,
/// GPIO10_LEVEL_LOW [8:8]
/// No description
GPIO10_LEVEL_LOW: u1 = 0,
/// GPIO10_LEVEL_HIGH [9:9]
/// No description
GPIO10_LEVEL_HIGH: u1 = 0,
/// GPIO10_EDGE_LOW [10:10]
/// No description
GPIO10_EDGE_LOW: u1 = 0,
/// GPIO10_EDGE_HIGH [11:11]
/// No description
GPIO10_EDGE_HIGH: u1 = 0,
/// GPIO11_LEVEL_LOW [12:12]
/// No description
GPIO11_LEVEL_LOW: u1 = 0,
/// GPIO11_LEVEL_HIGH [13:13]
/// No description
GPIO11_LEVEL_HIGH: u1 = 0,
/// GPIO11_EDGE_LOW [14:14]
/// No description
GPIO11_EDGE_LOW: u1 = 0,
/// GPIO11_EDGE_HIGH [15:15]
/// No description
GPIO11_EDGE_HIGH: u1 = 0,
/// GPIO12_LEVEL_LOW [16:16]
/// No description
GPIO12_LEVEL_LOW: u1 = 0,
/// GPIO12_LEVEL_HIGH [17:17]
/// No description
GPIO12_LEVEL_HIGH: u1 = 0,
/// GPIO12_EDGE_LOW [18:18]
/// No description
GPIO12_EDGE_LOW: u1 = 0,
/// GPIO12_EDGE_HIGH [19:19]
/// No description
GPIO12_EDGE_HIGH: u1 = 0,
/// GPIO13_LEVEL_LOW [20:20]
/// No description
GPIO13_LEVEL_LOW: u1 = 0,
/// GPIO13_LEVEL_HIGH [21:21]
/// No description
GPIO13_LEVEL_HIGH: u1 = 0,
/// GPIO13_EDGE_LOW [22:22]
/// No description
GPIO13_EDGE_LOW: u1 = 0,
/// GPIO13_EDGE_HIGH [23:23]
/// No description
GPIO13_EDGE_HIGH: u1 = 0,
/// GPIO14_LEVEL_LOW [24:24]
/// No description
GPIO14_LEVEL_LOW: u1 = 0,
/// GPIO14_LEVEL_HIGH [25:25]
/// No description
GPIO14_LEVEL_HIGH: u1 = 0,
/// GPIO14_EDGE_LOW [26:26]
/// No description
GPIO14_EDGE_LOW: u1 = 0,
/// GPIO14_EDGE_HIGH [27:27]
/// No description
GPIO14_EDGE_HIGH: u1 = 0,
/// GPIO15_LEVEL_LOW [28:28]
/// No description
GPIO15_LEVEL_LOW: u1 = 0,
/// GPIO15_LEVEL_HIGH [29:29]
/// No description
GPIO15_LEVEL_HIGH: u1 = 0,
/// GPIO15_EDGE_LOW [30:30]
/// No description
GPIO15_EDGE_LOW: u1 = 0,
/// GPIO15_EDGE_HIGH [31:31]
/// No description
GPIO15_EDGE_HIGH: u1 = 0,
};
/// Interrupt Enable for proc1
pub const PROC1_INTE1 = Register(PROC1_INTE1_val).init(base_address + 0x134);
/// PROC1_INTE0
const PROC1_INTE0_val = packed struct {
/// GPIO0_LEVEL_LOW [0:0]
/// No description
GPIO0_LEVEL_LOW: u1 = 0,
/// GPIO0_LEVEL_HIGH [1:1]
/// No description
GPIO0_LEVEL_HIGH: u1 = 0,
/// GPIO0_EDGE_LOW [2:2]
/// No description
GPIO0_EDGE_LOW: u1 = 0,
/// GPIO0_EDGE_HIGH [3:3]
/// No description
GPIO0_EDGE_HIGH: u1 = 0,
/// GPIO1_LEVEL_LOW [4:4]
/// No description
GPIO1_LEVEL_LOW: u1 = 0,
/// GPIO1_LEVEL_HIGH [5:5]
/// No description
GPIO1_LEVEL_HIGH: u1 = 0,
/// GPIO1_EDGE_LOW [6:6]
/// No description
GPIO1_EDGE_LOW: u1 = 0,
/// GPIO1_EDGE_HIGH [7:7]
/// No description
GPIO1_EDGE_HIGH: u1 = 0,
/// GPIO2_LEVEL_LOW [8:8]
/// No description
GPIO2_LEVEL_LOW: u1 = 0,
/// GPIO2_LEVEL_HIGH [9:9]
/// No description
GPIO2_LEVEL_HIGH: u1 = 0,
/// GPIO2_EDGE_LOW [10:10]
/// No description
GPIO2_EDGE_LOW: u1 = 0,
/// GPIO2_EDGE_HIGH [11:11]
/// No description
GPIO2_EDGE_HIGH: u1 = 0,
/// GPIO3_LEVEL_LOW [12:12]
/// No description
GPIO3_LEVEL_LOW: u1 = 0,
/// GPIO3_LEVEL_HIGH [13:13]
/// No description
GPIO3_LEVEL_HIGH: u1 = 0,
/// GPIO3_EDGE_LOW [14:14]
/// No description
GPIO3_EDGE_LOW: u1 = 0,
/// GPIO3_EDGE_HIGH [15:15]
/// No description
GPIO3_EDGE_HIGH: u1 = 0,
/// GPIO4_LEVEL_LOW [16:16]
/// No description
GPIO4_LEVEL_LOW: u1 = 0,
/// GPIO4_LEVEL_HIGH [17:17]
/// No description
GPIO4_LEVEL_HIGH: u1 = 0,
/// GPIO4_EDGE_LOW [18:18]
/// No description
GPIO4_EDGE_LOW: u1 = 0,
/// GPIO4_EDGE_HIGH [19:19]
/// No description
GPIO4_EDGE_HIGH: u1 = 0,
/// GPIO5_LEVEL_LOW [20:20]
/// No description
GPIO5_LEVEL_LOW: u1 = 0,
/// GPIO5_LEVEL_HIGH [21:21]
/// No description
GPIO5_LEVEL_HIGH: u1 = 0,
/// GPIO5_EDGE_LOW [22:22]
/// No description
GPIO5_EDGE_LOW: u1 = 0,
/// GPIO5_EDGE_HIGH [23:23]
/// No description
GPIO5_EDGE_HIGH: u1 = 0,
/// GPIO6_LEVEL_LOW [24:24]
/// No description
GPIO6_LEVEL_LOW: u1 = 0,
/// GPIO6_LEVEL_HIGH [25:25]
/// No description
GPIO6_LEVEL_HIGH: u1 = 0,
/// GPIO6_EDGE_LOW [26:26]
/// No description
GPIO6_EDGE_LOW: u1 = 0,
/// GPIO6_EDGE_HIGH [27:27]
/// No description
GPIO6_EDGE_HIGH: u1 = 0,
/// GPIO7_LEVEL_LOW [28:28]
/// No description
GPIO7_LEVEL_LOW: u1 = 0,
/// GPIO7_LEVEL_HIGH [29:29]
/// No description
GPIO7_LEVEL_HIGH: u1 = 0,
/// GPIO7_EDGE_LOW [30:30]
/// No description
GPIO7_EDGE_LOW: u1 = 0,
/// GPIO7_EDGE_HIGH [31:31]
/// No description
GPIO7_EDGE_HIGH: u1 = 0,
};
/// Interrupt Enable for proc1
pub const PROC1_INTE0 = Register(PROC1_INTE0_val).init(base_address + 0x130);
/// PROC0_INTS3
const PROC0_INTS3_val = packed struct {
/// GPIO24_LEVEL_LOW [0:0]
/// No description
GPIO24_LEVEL_LOW: u1 = 0,
/// GPIO24_LEVEL_HIGH [1:1]
/// No description
GPIO24_LEVEL_HIGH: u1 = 0,
/// GPIO24_EDGE_LOW [2:2]
/// No description
GPIO24_EDGE_LOW: u1 = 0,
/// GPIO24_EDGE_HIGH [3:3]
/// No description
GPIO24_EDGE_HIGH: u1 = 0,
/// GPIO25_LEVEL_LOW [4:4]
/// No description
GPIO25_LEVEL_LOW: u1 = 0,
/// GPIO25_LEVEL_HIGH [5:5]
/// No description
GPIO25_LEVEL_HIGH: u1 = 0,
/// GPIO25_EDGE_LOW [6:6]
/// No description
GPIO25_EDGE_LOW: u1 = 0,
/// GPIO25_EDGE_HIGH [7:7]
/// No description
GPIO25_EDGE_HIGH: u1 = 0,
/// GPIO26_LEVEL_LOW [8:8]
/// No description
GPIO26_LEVEL_LOW: u1 = 0,
/// GPIO26_LEVEL_HIGH [9:9]
/// No description
GPIO26_LEVEL_HIGH: u1 = 0,
/// GPIO26_EDGE_LOW [10:10]
/// No description
GPIO26_EDGE_LOW: u1 = 0,
/// GPIO26_EDGE_HIGH [11:11]
/// No description
GPIO26_EDGE_HIGH: u1 = 0,
/// GPIO27_LEVEL_LOW [12:12]
/// No description
GPIO27_LEVEL_LOW: u1 = 0,
/// GPIO27_LEVEL_HIGH [13:13]
/// No description
GPIO27_LEVEL_HIGH: u1 = 0,
/// GPIO27_EDGE_LOW [14:14]
/// No description
GPIO27_EDGE_LOW: u1 = 0,
/// GPIO27_EDGE_HIGH [15:15]
/// No description
GPIO27_EDGE_HIGH: u1 = 0,
/// GPIO28_LEVEL_LOW [16:16]
/// No description
GPIO28_LEVEL_LOW: u1 = 0,
/// GPIO28_LEVEL_HIGH [17:17]
/// No description
GPIO28_LEVEL_HIGH: u1 = 0,
/// GPIO28_EDGE_LOW [18:18]
/// No description
GPIO28_EDGE_LOW: u1 = 0,
/// GPIO28_EDGE_HIGH [19:19]
/// No description
GPIO28_EDGE_HIGH: u1 = 0,
/// GPIO29_LEVEL_LOW [20:20]
/// No description
GPIO29_LEVEL_LOW: u1 = 0,
/// GPIO29_LEVEL_HIGH [21:21]
/// No description
GPIO29_LEVEL_HIGH: u1 = 0,
/// GPIO29_EDGE_LOW [22:22]
/// No description
GPIO29_EDGE_LOW: u1 = 0,
/// GPIO29_EDGE_HIGH [23:23]
/// No description
GPIO29_EDGE_HIGH: u1 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Interrupt status after masking & forcing for proc0
pub const PROC0_INTS3 = Register(PROC0_INTS3_val).init(base_address + 0x12c);
/// PROC0_INTS2
const PROC0_INTS2_val = packed struct {
/// GPIO16_LEVEL_LOW [0:0]
/// No description
GPIO16_LEVEL_LOW: u1 = 0,
/// GPIO16_LEVEL_HIGH [1:1]
/// No description
GPIO16_LEVEL_HIGH: u1 = 0,
/// GPIO16_EDGE_LOW [2:2]
/// No description
GPIO16_EDGE_LOW: u1 = 0,
/// GPIO16_EDGE_HIGH [3:3]
/// No description
GPIO16_EDGE_HIGH: u1 = 0,
/// GPIO17_LEVEL_LOW [4:4]
/// No description
GPIO17_LEVEL_LOW: u1 = 0,
/// GPIO17_LEVEL_HIGH [5:5]
/// No description
GPIO17_LEVEL_HIGH: u1 = 0,
/// GPIO17_EDGE_LOW [6:6]
/// No description
GPIO17_EDGE_LOW: u1 = 0,
/// GPIO17_EDGE_HIGH [7:7]
/// No description
GPIO17_EDGE_HIGH: u1 = 0,
/// GPIO18_LEVEL_LOW [8:8]
/// No description
GPIO18_LEVEL_LOW: u1 = 0,
/// GPIO18_LEVEL_HIGH [9:9]
/// No description
GPIO18_LEVEL_HIGH: u1 = 0,
/// GPIO18_EDGE_LOW [10:10]
/// No description
GPIO18_EDGE_LOW: u1 = 0,
/// GPIO18_EDGE_HIGH [11:11]
/// No description
GPIO18_EDGE_HIGH: u1 = 0,
/// GPIO19_LEVEL_LOW [12:12]
/// No description
GPIO19_LEVEL_LOW: u1 = 0,
/// GPIO19_LEVEL_HIGH [13:13]
/// No description
GPIO19_LEVEL_HIGH: u1 = 0,
/// GPIO19_EDGE_LOW [14:14]
/// No description
GPIO19_EDGE_LOW: u1 = 0,
/// GPIO19_EDGE_HIGH [15:15]
/// No description
GPIO19_EDGE_HIGH: u1 = 0,
/// GPIO20_LEVEL_LOW [16:16]
/// No description
GPIO20_LEVEL_LOW: u1 = 0,
/// GPIO20_LEVEL_HIGH [17:17]
/// No description
GPIO20_LEVEL_HIGH: u1 = 0,
/// GPIO20_EDGE_LOW [18:18]
/// No description
GPIO20_EDGE_LOW: u1 = 0,
/// GPIO20_EDGE_HIGH [19:19]
/// No description
GPIO20_EDGE_HIGH: u1 = 0,
/// GPIO21_LEVEL_LOW [20:20]
/// No description
GPIO21_LEVEL_LOW: u1 = 0,
/// GPIO21_LEVEL_HIGH [21:21]
/// No description
GPIO21_LEVEL_HIGH: u1 = 0,
/// GPIO21_EDGE_LOW [22:22]
/// No description
GPIO21_EDGE_LOW: u1 = 0,
/// GPIO21_EDGE_HIGH [23:23]
/// No description
GPIO21_EDGE_HIGH: u1 = 0,
/// GPIO22_LEVEL_LOW [24:24]
/// No description
GPIO22_LEVEL_LOW: u1 = 0,
/// GPIO22_LEVEL_HIGH [25:25]
/// No description
GPIO22_LEVEL_HIGH: u1 = 0,
/// GPIO22_EDGE_LOW [26:26]
/// No description
GPIO22_EDGE_LOW: u1 = 0,
/// GPIO22_EDGE_HIGH [27:27]
/// No description
GPIO22_EDGE_HIGH: u1 = 0,
/// GPIO23_LEVEL_LOW [28:28]
/// No description
GPIO23_LEVEL_LOW: u1 = 0,
/// GPIO23_LEVEL_HIGH [29:29]
/// No description
GPIO23_LEVEL_HIGH: u1 = 0,
/// GPIO23_EDGE_LOW [30:30]
/// No description
GPIO23_EDGE_LOW: u1 = 0,
/// GPIO23_EDGE_HIGH [31:31]
/// No description
GPIO23_EDGE_HIGH: u1 = 0,
};
/// Interrupt status after masking & forcing for proc0
pub const PROC0_INTS2 = Register(PROC0_INTS2_val).init(base_address + 0x128);
/// PROC0_INTS1
const PROC0_INTS1_val = packed struct {
/// GPIO8_LEVEL_LOW [0:0]
/// No description
GPIO8_LEVEL_LOW: u1 = 0,
/// GPIO8_LEVEL_HIGH [1:1]
/// No description
GPIO8_LEVEL_HIGH: u1 = 0,
/// GPIO8_EDGE_LOW [2:2]
/// No description
GPIO8_EDGE_LOW: u1 = 0,
/// GPIO8_EDGE_HIGH [3:3]
/// No description
GPIO8_EDGE_HIGH: u1 = 0,
/// GPIO9_LEVEL_LOW [4:4]
/// No description
GPIO9_LEVEL_LOW: u1 = 0,
/// GPIO9_LEVEL_HIGH [5:5]
/// No description
GPIO9_LEVEL_HIGH: u1 = 0,
/// GPIO9_EDGE_LOW [6:6]
/// No description
GPIO9_EDGE_LOW: u1 = 0,
/// GPIO9_EDGE_HIGH [7:7]
/// No description
GPIO9_EDGE_HIGH: u1 = 0,
/// GPIO10_LEVEL_LOW [8:8]
/// No description
GPIO10_LEVEL_LOW: u1 = 0,
/// GPIO10_LEVEL_HIGH [9:9]
/// No description
GPIO10_LEVEL_HIGH: u1 = 0,
/// GPIO10_EDGE_LOW [10:10]
/// No description
GPIO10_EDGE_LOW: u1 = 0,
/// GPIO10_EDGE_HIGH [11:11]
/// No description
GPIO10_EDGE_HIGH: u1 = 0,
/// GPIO11_LEVEL_LOW [12:12]
/// No description
GPIO11_LEVEL_LOW: u1 = 0,
/// GPIO11_LEVEL_HIGH [13:13]
/// No description
GPIO11_LEVEL_HIGH: u1 = 0,
/// GPIO11_EDGE_LOW [14:14]
/// No description
GPIO11_EDGE_LOW: u1 = 0,
/// GPIO11_EDGE_HIGH [15:15]
/// No description
GPIO11_EDGE_HIGH: u1 = 0,
/// GPIO12_LEVEL_LOW [16:16]
/// No description
GPIO12_LEVEL_LOW: u1 = 0,
/// GPIO12_LEVEL_HIGH [17:17]
/// No description
GPIO12_LEVEL_HIGH: u1 = 0,
/// GPIO12_EDGE_LOW [18:18]
/// No description
GPIO12_EDGE_LOW: u1 = 0,
/// GPIO12_EDGE_HIGH [19:19]
/// No description
GPIO12_EDGE_HIGH: u1 = 0,
/// GPIO13_LEVEL_LOW [20:20]
/// No description
GPIO13_LEVEL_LOW: u1 = 0,
/// GPIO13_LEVEL_HIGH [21:21]
/// No description
GPIO13_LEVEL_HIGH: u1 = 0,
/// GPIO13_EDGE_LOW [22:22]
/// No description
GPIO13_EDGE_LOW: u1 = 0,
/// GPIO13_EDGE_HIGH [23:23]
/// No description
GPIO13_EDGE_HIGH: u1 = 0,
/// GPIO14_LEVEL_LOW [24:24]
/// No description
GPIO14_LEVEL_LOW: u1 = 0,
/// GPIO14_LEVEL_HIGH [25:25]
/// No description
GPIO14_LEVEL_HIGH: u1 = 0,
/// GPIO14_EDGE_LOW [26:26]
/// No description
GPIO14_EDGE_LOW: u1 = 0,
/// GPIO14_EDGE_HIGH [27:27]
/// No description
GPIO14_EDGE_HIGH: u1 = 0,
/// GPIO15_LEVEL_LOW [28:28]
/// No description
GPIO15_LEVEL_LOW: u1 = 0,
/// GPIO15_LEVEL_HIGH [29:29]
/// No description
GPIO15_LEVEL_HIGH: u1 = 0,
/// GPIO15_EDGE_LOW [30:30]
/// No description
GPIO15_EDGE_LOW: u1 = 0,
/// GPIO15_EDGE_HIGH [31:31]
/// No description
GPIO15_EDGE_HIGH: u1 = 0,
};
/// Interrupt status after masking & forcing for proc0
pub const PROC0_INTS1 = Register(PROC0_INTS1_val).init(base_address + 0x124);
/// PROC0_INTS0
const PROC0_INTS0_val = packed struct {
/// GPIO0_LEVEL_LOW [0:0]
/// No description
GPIO0_LEVEL_LOW: u1 = 0,
/// GPIO0_LEVEL_HIGH [1:1]
/// No description
GPIO0_LEVEL_HIGH: u1 = 0,
/// GPIO0_EDGE_LOW [2:2]
/// No description
GPIO0_EDGE_LOW: u1 = 0,
/// GPIO0_EDGE_HIGH [3:3]
/// No description
GPIO0_EDGE_HIGH: u1 = 0,
/// GPIO1_LEVEL_LOW [4:4]
/// No description
GPIO1_LEVEL_LOW: u1 = 0,
/// GPIO1_LEVEL_HIGH [5:5]
/// No description
GPIO1_LEVEL_HIGH: u1 = 0,
/// GPIO1_EDGE_LOW [6:6]
/// No description
GPIO1_EDGE_LOW: u1 = 0,
/// GPIO1_EDGE_HIGH [7:7]
/// No description
GPIO1_EDGE_HIGH: u1 = 0,
/// GPIO2_LEVEL_LOW [8:8]
/// No description
GPIO2_LEVEL_LOW: u1 = 0,
/// GPIO2_LEVEL_HIGH [9:9]
/// No description
GPIO2_LEVEL_HIGH: u1 = 0,
/// GPIO2_EDGE_LOW [10:10]
/// No description
GPIO2_EDGE_LOW: u1 = 0,
/// GPIO2_EDGE_HIGH [11:11]
/// No description
GPIO2_EDGE_HIGH: u1 = 0,
/// GPIO3_LEVEL_LOW [12:12]
/// No description
GPIO3_LEVEL_LOW: u1 = 0,
/// GPIO3_LEVEL_HIGH [13:13]
/// No description
GPIO3_LEVEL_HIGH: u1 = 0,
/// GPIO3_EDGE_LOW [14:14]
/// No description
GPIO3_EDGE_LOW: u1 = 0,
/// GPIO3_EDGE_HIGH [15:15]
/// No description
GPIO3_EDGE_HIGH: u1 = 0,
/// GPIO4_LEVEL_LOW [16:16]
/// No description
GPIO4_LEVEL_LOW: u1 = 0,
/// GPIO4_LEVEL_HIGH [17:17]
/// No description
GPIO4_LEVEL_HIGH: u1 = 0,
/// GPIO4_EDGE_LOW [18:18]
/// No description
GPIO4_EDGE_LOW: u1 = 0,
/// GPIO4_EDGE_HIGH [19:19]
/// No description
GPIO4_EDGE_HIGH: u1 = 0,
/// GPIO5_LEVEL_LOW [20:20]
/// No description
GPIO5_LEVEL_LOW: u1 = 0,
/// GPIO5_LEVEL_HIGH [21:21]
/// No description
GPIO5_LEVEL_HIGH: u1 = 0,
/// GPIO5_EDGE_LOW [22:22]
/// No description
GPIO5_EDGE_LOW: u1 = 0,
/// GPIO5_EDGE_HIGH [23:23]
/// No description
GPIO5_EDGE_HIGH: u1 = 0,
/// GPIO6_LEVEL_LOW [24:24]
/// No description
GPIO6_LEVEL_LOW: u1 = 0,
/// GPIO6_LEVEL_HIGH [25:25]
/// No description
GPIO6_LEVEL_HIGH: u1 = 0,
/// GPIO6_EDGE_LOW [26:26]
/// No description
GPIO6_EDGE_LOW: u1 = 0,
/// GPIO6_EDGE_HIGH [27:27]
/// No description
GPIO6_EDGE_HIGH: u1 = 0,
/// GPIO7_LEVEL_LOW [28:28]
/// No description
GPIO7_LEVEL_LOW: u1 = 0,
/// GPIO7_LEVEL_HIGH [29:29]
/// No description
GPIO7_LEVEL_HIGH: u1 = 0,
/// GPIO7_EDGE_LOW [30:30]
/// No description
GPIO7_EDGE_LOW: u1 = 0,
/// GPIO7_EDGE_HIGH [31:31]
/// No description
GPIO7_EDGE_HIGH: u1 = 0,
};
/// Interrupt status after masking & forcing for proc0
pub const PROC0_INTS0 = Register(PROC0_INTS0_val).init(base_address + 0x120);
/// PROC0_INTF3
const PROC0_INTF3_val = packed struct {
/// GPIO24_LEVEL_LOW [0:0]
/// No description
GPIO24_LEVEL_LOW: u1 = 0,
/// GPIO24_LEVEL_HIGH [1:1]
/// No description
GPIO24_LEVEL_HIGH: u1 = 0,
/// GPIO24_EDGE_LOW [2:2]
/// No description
GPIO24_EDGE_LOW: u1 = 0,
/// GPIO24_EDGE_HIGH [3:3]
/// No description
GPIO24_EDGE_HIGH: u1 = 0,
/// GPIO25_LEVEL_LOW [4:4]
/// No description
GPIO25_LEVEL_LOW: u1 = 0,
/// GPIO25_LEVEL_HIGH [5:5]
/// No description
GPIO25_LEVEL_HIGH: u1 = 0,
/// GPIO25_EDGE_LOW [6:6]
/// No description
GPIO25_EDGE_LOW: u1 = 0,
/// GPIO25_EDGE_HIGH [7:7]
/// No description
GPIO25_EDGE_HIGH: u1 = 0,
/// GPIO26_LEVEL_LOW [8:8]
/// No description
GPIO26_LEVEL_LOW: u1 = 0,
/// GPIO26_LEVEL_HIGH [9:9]
/// No description
GPIO26_LEVEL_HIGH: u1 = 0,
/// GPIO26_EDGE_LOW [10:10]
/// No description
GPIO26_EDGE_LOW: u1 = 0,
/// GPIO26_EDGE_HIGH [11:11]
/// No description
GPIO26_EDGE_HIGH: u1 = 0,
/// GPIO27_LEVEL_LOW [12:12]
/// No description
GPIO27_LEVEL_LOW: u1 = 0,
/// GPIO27_LEVEL_HIGH [13:13]
/// No description
GPIO27_LEVEL_HIGH: u1 = 0,
/// GPIO27_EDGE_LOW [14:14]
/// No description
GPIO27_EDGE_LOW: u1 = 0,
/// GPIO27_EDGE_HIGH [15:15]
/// No description
GPIO27_EDGE_HIGH: u1 = 0,
/// GPIO28_LEVEL_LOW [16:16]
/// No description
GPIO28_LEVEL_LOW: u1 = 0,
/// GPIO28_LEVEL_HIGH [17:17]
/// No description
GPIO28_LEVEL_HIGH: u1 = 0,
/// GPIO28_EDGE_LOW [18:18]
/// No description
GPIO28_EDGE_LOW: u1 = 0,
/// GPIO28_EDGE_HIGH [19:19]
/// No description
GPIO28_EDGE_HIGH: u1 = 0,
/// GPIO29_LEVEL_LOW [20:20]
/// No description
GPIO29_LEVEL_LOW: u1 = 0,
/// GPIO29_LEVEL_HIGH [21:21]
/// No description
GPIO29_LEVEL_HIGH: u1 = 0,
/// GPIO29_EDGE_LOW [22:22]
/// No description
GPIO29_EDGE_LOW: u1 = 0,
/// GPIO29_EDGE_HIGH [23:23]
/// No description
GPIO29_EDGE_HIGH: u1 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Interrupt Force for proc0
pub const PROC0_INTF3 = Register(PROC0_INTF3_val).init(base_address + 0x11c);
/// PROC0_INTF2
const PROC0_INTF2_val = packed struct {
/// GPIO16_LEVEL_LOW [0:0]
/// No description
GPIO16_LEVEL_LOW: u1 = 0,
/// GPIO16_LEVEL_HIGH [1:1]
/// No description
GPIO16_LEVEL_HIGH: u1 = 0,
/// GPIO16_EDGE_LOW [2:2]
/// No description
GPIO16_EDGE_LOW: u1 = 0,
/// GPIO16_EDGE_HIGH [3:3]
/// No description
GPIO16_EDGE_HIGH: u1 = 0,
/// GPIO17_LEVEL_LOW [4:4]
/// No description
GPIO17_LEVEL_LOW: u1 = 0,
/// GPIO17_LEVEL_HIGH [5:5]
/// No description
GPIO17_LEVEL_HIGH: u1 = 0,
/// GPIO17_EDGE_LOW [6:6]
/// No description
GPIO17_EDGE_LOW: u1 = 0,
/// GPIO17_EDGE_HIGH [7:7]
/// No description
GPIO17_EDGE_HIGH: u1 = 0,
/// GPIO18_LEVEL_LOW [8:8]
/// No description
GPIO18_LEVEL_LOW: u1 = 0,
/// GPIO18_LEVEL_HIGH [9:9]
/// No description
GPIO18_LEVEL_HIGH: u1 = 0,
/// GPIO18_EDGE_LOW [10:10]
/// No description
GPIO18_EDGE_LOW: u1 = 0,
/// GPIO18_EDGE_HIGH [11:11]
/// No description
GPIO18_EDGE_HIGH: u1 = 0,
/// GPIO19_LEVEL_LOW [12:12]
/// No description
GPIO19_LEVEL_LOW: u1 = 0,
/// GPIO19_LEVEL_HIGH [13:13]
/// No description
GPIO19_LEVEL_HIGH: u1 = 0,
/// GPIO19_EDGE_LOW [14:14]
/// No description
GPIO19_EDGE_LOW: u1 = 0,
/// GPIO19_EDGE_HIGH [15:15]
/// No description
GPIO19_EDGE_HIGH: u1 = 0,
/// GPIO20_LEVEL_LOW [16:16]
/// No description
GPIO20_LEVEL_LOW: u1 = 0,
/// GPIO20_LEVEL_HIGH [17:17]
/// No description
GPIO20_LEVEL_HIGH: u1 = 0,
/// GPIO20_EDGE_LOW [18:18]
/// No description
GPIO20_EDGE_LOW: u1 = 0,
/// GPIO20_EDGE_HIGH [19:19]
/// No description
GPIO20_EDGE_HIGH: u1 = 0,
/// GPIO21_LEVEL_LOW [20:20]
/// No description
GPIO21_LEVEL_LOW: u1 = 0,
/// GPIO21_LEVEL_HIGH [21:21]
/// No description
GPIO21_LEVEL_HIGH: u1 = 0,
/// GPIO21_EDGE_LOW [22:22]
/// No description
GPIO21_EDGE_LOW: u1 = 0,
/// GPIO21_EDGE_HIGH [23:23]
/// No description
GPIO21_EDGE_HIGH: u1 = 0,
/// GPIO22_LEVEL_LOW [24:24]
/// No description
GPIO22_LEVEL_LOW: u1 = 0,
/// GPIO22_LEVEL_HIGH [25:25]
/// No description
GPIO22_LEVEL_HIGH: u1 = 0,
/// GPIO22_EDGE_LOW [26:26]
/// No description
GPIO22_EDGE_LOW: u1 = 0,
/// GPIO22_EDGE_HIGH [27:27]
/// No description
GPIO22_EDGE_HIGH: u1 = 0,
/// GPIO23_LEVEL_LOW [28:28]
/// No description
GPIO23_LEVEL_LOW: u1 = 0,
/// GPIO23_LEVEL_HIGH [29:29]
/// No description
GPIO23_LEVEL_HIGH: u1 = 0,
/// GPIO23_EDGE_LOW [30:30]
/// No description
GPIO23_EDGE_LOW: u1 = 0,
/// GPIO23_EDGE_HIGH [31:31]
/// No description
GPIO23_EDGE_HIGH: u1 = 0,
};
/// Interrupt Force for proc0
pub const PROC0_INTF2 = Register(PROC0_INTF2_val).init(base_address + 0x118);
/// PROC0_INTF1
const PROC0_INTF1_val = packed struct {
/// GPIO8_LEVEL_LOW [0:0]
/// No description
GPIO8_LEVEL_LOW: u1 = 0,
/// GPIO8_LEVEL_HIGH [1:1]
/// No description
GPIO8_LEVEL_HIGH: u1 = 0,
/// GPIO8_EDGE_LOW [2:2]
/// No description
GPIO8_EDGE_LOW: u1 = 0,
/// GPIO8_EDGE_HIGH [3:3]
/// No description
GPIO8_EDGE_HIGH: u1 = 0,
/// GPIO9_LEVEL_LOW [4:4]
/// No description
GPIO9_LEVEL_LOW: u1 = 0,
/// GPIO9_LEVEL_HIGH [5:5]
/// No description
GPIO9_LEVEL_HIGH: u1 = 0,
/// GPIO9_EDGE_LOW [6:6]
/// No description
GPIO9_EDGE_LOW: u1 = 0,
/// GPIO9_EDGE_HIGH [7:7]
/// No description
GPIO9_EDGE_HIGH: u1 = 0,
/// GPIO10_LEVEL_LOW [8:8]
/// No description
GPIO10_LEVEL_LOW: u1 = 0,
/// GPIO10_LEVEL_HIGH [9:9]
/// No description
GPIO10_LEVEL_HIGH: u1 = 0,
/// GPIO10_EDGE_LOW [10:10]
/// No description
GPIO10_EDGE_LOW: u1 = 0,
/// GPIO10_EDGE_HIGH [11:11]
/// No description
GPIO10_EDGE_HIGH: u1 = 0,
/// GPIO11_LEVEL_LOW [12:12]
/// No description
GPIO11_LEVEL_LOW: u1 = 0,
/// GPIO11_LEVEL_HIGH [13:13]
/// No description
GPIO11_LEVEL_HIGH: u1 = 0,
/// GPIO11_EDGE_LOW [14:14]
/// No description
GPIO11_EDGE_LOW: u1 = 0,
/// GPIO11_EDGE_HIGH [15:15]
/// No description
GPIO11_EDGE_HIGH: u1 = 0,
/// GPIO12_LEVEL_LOW [16:16]
/// No description
GPIO12_LEVEL_LOW: u1 = 0,
/// GPIO12_LEVEL_HIGH [17:17]
/// No description
GPIO12_LEVEL_HIGH: u1 = 0,
/// GPIO12_EDGE_LOW [18:18]
/// No description
GPIO12_EDGE_LOW: u1 = 0,
/// GPIO12_EDGE_HIGH [19:19]
/// No description
GPIO12_EDGE_HIGH: u1 = 0,
/// GPIO13_LEVEL_LOW [20:20]
/// No description
GPIO13_LEVEL_LOW: u1 = 0,
/// GPIO13_LEVEL_HIGH [21:21]
/// No description
GPIO13_LEVEL_HIGH: u1 = 0,
/// GPIO13_EDGE_LOW [22:22]
/// No description
GPIO13_EDGE_LOW: u1 = 0,
/// GPIO13_EDGE_HIGH [23:23]
/// No description
GPIO13_EDGE_HIGH: u1 = 0,
/// GPIO14_LEVEL_LOW [24:24]
/// No description
GPIO14_LEVEL_LOW: u1 = 0,
/// GPIO14_LEVEL_HIGH [25:25]
/// No description
GPIO14_LEVEL_HIGH: u1 = 0,
/// GPIO14_EDGE_LOW [26:26]
/// No description
GPIO14_EDGE_LOW: u1 = 0,
/// GPIO14_EDGE_HIGH [27:27]
/// No description
GPIO14_EDGE_HIGH: u1 = 0,
/// GPIO15_LEVEL_LOW [28:28]
/// No description
GPIO15_LEVEL_LOW: u1 = 0,
/// GPIO15_LEVEL_HIGH [29:29]
/// No description
GPIO15_LEVEL_HIGH: u1 = 0,
/// GPIO15_EDGE_LOW [30:30]
/// No description
GPIO15_EDGE_LOW: u1 = 0,
/// GPIO15_EDGE_HIGH [31:31]
/// No description
GPIO15_EDGE_HIGH: u1 = 0,
};
/// Interrupt Force for proc0
pub const PROC0_INTF1 = Register(PROC0_INTF1_val).init(base_address + 0x114);
/// PROC0_INTF0
const PROC0_INTF0_val = packed struct {
/// GPIO0_LEVEL_LOW [0:0]
/// No description
GPIO0_LEVEL_LOW: u1 = 0,
/// GPIO0_LEVEL_HIGH [1:1]
/// No description
GPIO0_LEVEL_HIGH: u1 = 0,
/// GPIO0_EDGE_LOW [2:2]
/// No description
GPIO0_EDGE_LOW: u1 = 0,
/// GPIO0_EDGE_HIGH [3:3]
/// No description
GPIO0_EDGE_HIGH: u1 = 0,
/// GPIO1_LEVEL_LOW [4:4]
/// No description
GPIO1_LEVEL_LOW: u1 = 0,
/// GPIO1_LEVEL_HIGH [5:5]
/// No description
GPIO1_LEVEL_HIGH: u1 = 0,
/// GPIO1_EDGE_LOW [6:6]
/// No description
GPIO1_EDGE_LOW: u1 = 0,
/// GPIO1_EDGE_HIGH [7:7]
/// No description
GPIO1_EDGE_HIGH: u1 = 0,
/// GPIO2_LEVEL_LOW [8:8]
/// No description
GPIO2_LEVEL_LOW: u1 = 0,
/// GPIO2_LEVEL_HIGH [9:9]
/// No description
GPIO2_LEVEL_HIGH: u1 = 0,
/// GPIO2_EDGE_LOW [10:10]
/// No description
GPIO2_EDGE_LOW: u1 = 0,
/// GPIO2_EDGE_HIGH [11:11]
/// No description
GPIO2_EDGE_HIGH: u1 = 0,
/// GPIO3_LEVEL_LOW [12:12]
/// No description
GPIO3_LEVEL_LOW: u1 = 0,
/// GPIO3_LEVEL_HIGH [13:13]
/// No description
GPIO3_LEVEL_HIGH: u1 = 0,
/// GPIO3_EDGE_LOW [14:14]
/// No description
GPIO3_EDGE_LOW: u1 = 0,
/// GPIO3_EDGE_HIGH [15:15]
/// No description
GPIO3_EDGE_HIGH: u1 = 0,
/// GPIO4_LEVEL_LOW [16:16]
/// No description
GPIO4_LEVEL_LOW: u1 = 0,
/// GPIO4_LEVEL_HIGH [17:17]
/// No description
GPIO4_LEVEL_HIGH: u1 = 0,
/// GPIO4_EDGE_LOW [18:18]
/// No description
GPIO4_EDGE_LOW: u1 = 0,
/// GPIO4_EDGE_HIGH [19:19]
/// No description
GPIO4_EDGE_HIGH: u1 = 0,
/// GPIO5_LEVEL_LOW [20:20]
/// No description
GPIO5_LEVEL_LOW: u1 = 0,
/// GPIO5_LEVEL_HIGH [21:21]
/// No description
GPIO5_LEVEL_HIGH: u1 = 0,
/// GPIO5_EDGE_LOW [22:22]
/// No description
GPIO5_EDGE_LOW: u1 = 0,
/// GPIO5_EDGE_HIGH [23:23]
/// No description
GPIO5_EDGE_HIGH: u1 = 0,
/// GPIO6_LEVEL_LOW [24:24]
/// No description
GPIO6_LEVEL_LOW: u1 = 0,
/// GPIO6_LEVEL_HIGH [25:25]
/// No description
GPIO6_LEVEL_HIGH: u1 = 0,
/// GPIO6_EDGE_LOW [26:26]
/// No description
GPIO6_EDGE_LOW: u1 = 0,
/// GPIO6_EDGE_HIGH [27:27]
/// No description
GPIO6_EDGE_HIGH: u1 = 0,
/// GPIO7_LEVEL_LOW [28:28]
/// No description
GPIO7_LEVEL_LOW: u1 = 0,
/// GPIO7_LEVEL_HIGH [29:29]
/// No description
GPIO7_LEVEL_HIGH: u1 = 0,
/// GPIO7_EDGE_LOW [30:30]
/// No description
GPIO7_EDGE_LOW: u1 = 0,
/// GPIO7_EDGE_HIGH [31:31]
/// No description
GPIO7_EDGE_HIGH: u1 = 0,
};
/// Interrupt Force for proc0
pub const PROC0_INTF0 = Register(PROC0_INTF0_val).init(base_address + 0x110);
/// PROC0_INTE3
const PROC0_INTE3_val = packed struct {
/// GPIO24_LEVEL_LOW [0:0]
/// No description
GPIO24_LEVEL_LOW: u1 = 0,
/// GPIO24_LEVEL_HIGH [1:1]
/// No description
GPIO24_LEVEL_HIGH: u1 = 0,
/// GPIO24_EDGE_LOW [2:2]
/// No description
GPIO24_EDGE_LOW: u1 = 0,
/// GPIO24_EDGE_HIGH [3:3]
/// No description
GPIO24_EDGE_HIGH: u1 = 0,
/// GPIO25_LEVEL_LOW [4:4]
/// No description
GPIO25_LEVEL_LOW: u1 = 0,
/// GPIO25_LEVEL_HIGH [5:5]
/// No description
GPIO25_LEVEL_HIGH: u1 = 0,
/// GPIO25_EDGE_LOW [6:6]
/// No description
GPIO25_EDGE_LOW: u1 = 0,
/// GPIO25_EDGE_HIGH [7:7]
/// No description
GPIO25_EDGE_HIGH: u1 = 0,
/// GPIO26_LEVEL_LOW [8:8]
/// No description
GPIO26_LEVEL_LOW: u1 = 0,
/// GPIO26_LEVEL_HIGH [9:9]
/// No description
GPIO26_LEVEL_HIGH: u1 = 0,
/// GPIO26_EDGE_LOW [10:10]
/// No description
GPIO26_EDGE_LOW: u1 = 0,
/// GPIO26_EDGE_HIGH [11:11]
/// No description
GPIO26_EDGE_HIGH: u1 = 0,
/// GPIO27_LEVEL_LOW [12:12]
/// No description
GPIO27_LEVEL_LOW: u1 = 0,
/// GPIO27_LEVEL_HIGH [13:13]
/// No description
GPIO27_LEVEL_HIGH: u1 = 0,
/// GPIO27_EDGE_LOW [14:14]
/// No description
GPIO27_EDGE_LOW: u1 = 0,
/// GPIO27_EDGE_HIGH [15:15]
/// No description
GPIO27_EDGE_HIGH: u1 = 0,
/// GPIO28_LEVEL_LOW [16:16]
/// No description
GPIO28_LEVEL_LOW: u1 = 0,
/// GPIO28_LEVEL_HIGH [17:17]
/// No description
GPIO28_LEVEL_HIGH: u1 = 0,
/// GPIO28_EDGE_LOW [18:18]
/// No description
GPIO28_EDGE_LOW: u1 = 0,
/// GPIO28_EDGE_HIGH [19:19]
/// No description
GPIO28_EDGE_HIGH: u1 = 0,
/// GPIO29_LEVEL_LOW [20:20]
/// No description
GPIO29_LEVEL_LOW: u1 = 0,
/// GPIO29_LEVEL_HIGH [21:21]
/// No description
GPIO29_LEVEL_HIGH: u1 = 0,
/// GPIO29_EDGE_LOW [22:22]
/// No description
GPIO29_EDGE_LOW: u1 = 0,
/// GPIO29_EDGE_HIGH [23:23]
/// No description
GPIO29_EDGE_HIGH: u1 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Interrupt Enable for proc0
pub const PROC0_INTE3 = Register(PROC0_INTE3_val).init(base_address + 0x10c);
/// PROC0_INTE2
const PROC0_INTE2_val = packed struct {
/// GPIO16_LEVEL_LOW [0:0]
/// No description
GPIO16_LEVEL_LOW: u1 = 0,
/// GPIO16_LEVEL_HIGH [1:1]
/// No description
GPIO16_LEVEL_HIGH: u1 = 0,
/// GPIO16_EDGE_LOW [2:2]
/// No description
GPIO16_EDGE_LOW: u1 = 0,
/// GPIO16_EDGE_HIGH [3:3]
/// No description
GPIO16_EDGE_HIGH: u1 = 0,
/// GPIO17_LEVEL_LOW [4:4]
/// No description
GPIO17_LEVEL_LOW: u1 = 0,
/// GPIO17_LEVEL_HIGH [5:5]
/// No description
GPIO17_LEVEL_HIGH: u1 = 0,
/// GPIO17_EDGE_LOW [6:6]
/// No description
GPIO17_EDGE_LOW: u1 = 0,
/// GPIO17_EDGE_HIGH [7:7]
/// No description
GPIO17_EDGE_HIGH: u1 = 0,
/// GPIO18_LEVEL_LOW [8:8]
/// No description
GPIO18_LEVEL_LOW: u1 = 0,
/// GPIO18_LEVEL_HIGH [9:9]
/// No description
GPIO18_LEVEL_HIGH: u1 = 0,
/// GPIO18_EDGE_LOW [10:10]
/// No description
GPIO18_EDGE_LOW: u1 = 0,
/// GPIO18_EDGE_HIGH [11:11]
/// No description
GPIO18_EDGE_HIGH: u1 = 0,
/// GPIO19_LEVEL_LOW [12:12]
/// No description
GPIO19_LEVEL_LOW: u1 = 0,
/// GPIO19_LEVEL_HIGH [13:13]
/// No description
GPIO19_LEVEL_HIGH: u1 = 0,
/// GPIO19_EDGE_LOW [14:14]
/// No description
GPIO19_EDGE_LOW: u1 = 0,
/// GPIO19_EDGE_HIGH [15:15]
/// No description
GPIO19_EDGE_HIGH: u1 = 0,
/// GPIO20_LEVEL_LOW [16:16]
/// No description
GPIO20_LEVEL_LOW: u1 = 0,
/// GPIO20_LEVEL_HIGH [17:17]
/// No description
GPIO20_LEVEL_HIGH: u1 = 0,
/// GPIO20_EDGE_LOW [18:18]
/// No description
GPIO20_EDGE_LOW: u1 = 0,
/// GPIO20_EDGE_HIGH [19:19]
/// No description
GPIO20_EDGE_HIGH: u1 = 0,
/// GPIO21_LEVEL_LOW [20:20]
/// No description
GPIO21_LEVEL_LOW: u1 = 0,
/// GPIO21_LEVEL_HIGH [21:21]
/// No description
GPIO21_LEVEL_HIGH: u1 = 0,
/// GPIO21_EDGE_LOW [22:22]
/// No description
GPIO21_EDGE_LOW: u1 = 0,
/// GPIO21_EDGE_HIGH [23:23]
/// No description
GPIO21_EDGE_HIGH: u1 = 0,
/// GPIO22_LEVEL_LOW [24:24]
/// No description
GPIO22_LEVEL_LOW: u1 = 0,
/// GPIO22_LEVEL_HIGH [25:25]
/// No description
GPIO22_LEVEL_HIGH: u1 = 0,
/// GPIO22_EDGE_LOW [26:26]
/// No description
GPIO22_EDGE_LOW: u1 = 0,
/// GPIO22_EDGE_HIGH [27:27]
/// No description
GPIO22_EDGE_HIGH: u1 = 0,
/// GPIO23_LEVEL_LOW [28:28]
/// No description
GPIO23_LEVEL_LOW: u1 = 0,
/// GPIO23_LEVEL_HIGH [29:29]
/// No description
GPIO23_LEVEL_HIGH: u1 = 0,
/// GPIO23_EDGE_LOW [30:30]
/// No description
GPIO23_EDGE_LOW: u1 = 0,
/// GPIO23_EDGE_HIGH [31:31]
/// No description
GPIO23_EDGE_HIGH: u1 = 0,
};
/// Interrupt Enable for proc0
pub const PROC0_INTE2 = Register(PROC0_INTE2_val).init(base_address + 0x108);
/// PROC0_INTE1
const PROC0_INTE1_val = packed struct {
/// GPIO8_LEVEL_LOW [0:0]
/// No description
GPIO8_LEVEL_LOW: u1 = 0,
/// GPIO8_LEVEL_HIGH [1:1]
/// No description
GPIO8_LEVEL_HIGH: u1 = 0,
/// GPIO8_EDGE_LOW [2:2]
/// No description
GPIO8_EDGE_LOW: u1 = 0,
/// GPIO8_EDGE_HIGH [3:3]
/// No description
GPIO8_EDGE_HIGH: u1 = 0,
/// GPIO9_LEVEL_LOW [4:4]
/// No description
GPIO9_LEVEL_LOW: u1 = 0,
/// GPIO9_LEVEL_HIGH [5:5]
/// No description
GPIO9_LEVEL_HIGH: u1 = 0,
/// GPIO9_EDGE_LOW [6:6]
/// No description
GPIO9_EDGE_LOW: u1 = 0,
/// GPIO9_EDGE_HIGH [7:7]
/// No description
GPIO9_EDGE_HIGH: u1 = 0,
/// GPIO10_LEVEL_LOW [8:8]
/// No description
GPIO10_LEVEL_LOW: u1 = 0,
/// GPIO10_LEVEL_HIGH [9:9]
/// No description
GPIO10_LEVEL_HIGH: u1 = 0,
/// GPIO10_EDGE_LOW [10:10]
/// No description
GPIO10_EDGE_LOW: u1 = 0,
/// GPIO10_EDGE_HIGH [11:11]
/// No description
GPIO10_EDGE_HIGH: u1 = 0,
/// GPIO11_LEVEL_LOW [12:12]
/// No description
GPIO11_LEVEL_LOW: u1 = 0,
/// GPIO11_LEVEL_HIGH [13:13]
/// No description
GPIO11_LEVEL_HIGH: u1 = 0,
/// GPIO11_EDGE_LOW [14:14]
/// No description
GPIO11_EDGE_LOW: u1 = 0,
/// GPIO11_EDGE_HIGH [15:15]
/// No description
GPIO11_EDGE_HIGH: u1 = 0,
/// GPIO12_LEVEL_LOW [16:16]
/// No description
GPIO12_LEVEL_LOW: u1 = 0,
/// GPIO12_LEVEL_HIGH [17:17]
/// No description
GPIO12_LEVEL_HIGH: u1 = 0,
/// GPIO12_EDGE_LOW [18:18]
/// No description
GPIO12_EDGE_LOW: u1 = 0,
/// GPIO12_EDGE_HIGH [19:19]
/// No description
GPIO12_EDGE_HIGH: u1 = 0,
/// GPIO13_LEVEL_LOW [20:20]
/// No description
GPIO13_LEVEL_LOW: u1 = 0,
/// GPIO13_LEVEL_HIGH [21:21]
/// No description
GPIO13_LEVEL_HIGH: u1 = 0,
/// GPIO13_EDGE_LOW [22:22]
/// No description
GPIO13_EDGE_LOW: u1 = 0,
/// GPIO13_EDGE_HIGH [23:23]
/// No description
GPIO13_EDGE_HIGH: u1 = 0,
/// GPIO14_LEVEL_LOW [24:24]
/// No description
GPIO14_LEVEL_LOW: u1 = 0,
/// GPIO14_LEVEL_HIGH [25:25]
/// No description
GPIO14_LEVEL_HIGH: u1 = 0,
/// GPIO14_EDGE_LOW [26:26]
/// No description
GPIO14_EDGE_LOW: u1 = 0,
/// GPIO14_EDGE_HIGH [27:27]
/// No description
GPIO14_EDGE_HIGH: u1 = 0,
/// GPIO15_LEVEL_LOW [28:28]
/// No description
GPIO15_LEVEL_LOW: u1 = 0,
/// GPIO15_LEVEL_HIGH [29:29]
/// No description
GPIO15_LEVEL_HIGH: u1 = 0,
/// GPIO15_EDGE_LOW [30:30]
/// No description
GPIO15_EDGE_LOW: u1 = 0,
/// GPIO15_EDGE_HIGH [31:31]
/// No description
GPIO15_EDGE_HIGH: u1 = 0,
};
/// Interrupt Enable for proc0
pub const PROC0_INTE1 = Register(PROC0_INTE1_val).init(base_address + 0x104);
/// PROC0_INTE0
const PROC0_INTE0_val = packed struct {
/// GPIO0_LEVEL_LOW [0:0]
/// No description
GPIO0_LEVEL_LOW: u1 = 0,
/// GPIO0_LEVEL_HIGH [1:1]
/// No description
GPIO0_LEVEL_HIGH: u1 = 0,
/// GPIO0_EDGE_LOW [2:2]
/// No description
GPIO0_EDGE_LOW: u1 = 0,
/// GPIO0_EDGE_HIGH [3:3]
/// No description
GPIO0_EDGE_HIGH: u1 = 0,
/// GPIO1_LEVEL_LOW [4:4]
/// No description
GPIO1_LEVEL_LOW: u1 = 0,
/// GPIO1_LEVEL_HIGH [5:5]
/// No description
GPIO1_LEVEL_HIGH: u1 = 0,
/// GPIO1_EDGE_LOW [6:6]
/// No description
GPIO1_EDGE_LOW: u1 = 0,
/// GPIO1_EDGE_HIGH [7:7]
/// No description
GPIO1_EDGE_HIGH: u1 = 0,
/// GPIO2_LEVEL_LOW [8:8]
/// No description
GPIO2_LEVEL_LOW: u1 = 0,
/// GPIO2_LEVEL_HIGH [9:9]
/// No description
GPIO2_LEVEL_HIGH: u1 = 0,
/// GPIO2_EDGE_LOW [10:10]
/// No description
GPIO2_EDGE_LOW: u1 = 0,
/// GPIO2_EDGE_HIGH [11:11]
/// No description
GPIO2_EDGE_HIGH: u1 = 0,
/// GPIO3_LEVEL_LOW [12:12]
/// No description
GPIO3_LEVEL_LOW: u1 = 0,
/// GPIO3_LEVEL_HIGH [13:13]
/// No description
GPIO3_LEVEL_HIGH: u1 = 0,
/// GPIO3_EDGE_LOW [14:14]
/// No description
GPIO3_EDGE_LOW: u1 = 0,
/// GPIO3_EDGE_HIGH [15:15]
/// No description
GPIO3_EDGE_HIGH: u1 = 0,
/// GPIO4_LEVEL_LOW [16:16]
/// No description
GPIO4_LEVEL_LOW: u1 = 0,
/// GPIO4_LEVEL_HIGH [17:17]
/// No description
GPIO4_LEVEL_HIGH: u1 = 0,
/// GPIO4_EDGE_LOW [18:18]
/// No description
GPIO4_EDGE_LOW: u1 = 0,
/// GPIO4_EDGE_HIGH [19:19]
/// No description
GPIO4_EDGE_HIGH: u1 = 0,
/// GPIO5_LEVEL_LOW [20:20]
/// No description
GPIO5_LEVEL_LOW: u1 = 0,
/// GPIO5_LEVEL_HIGH [21:21]
/// No description
GPIO5_LEVEL_HIGH: u1 = 0,
/// GPIO5_EDGE_LOW [22:22]
/// No description
GPIO5_EDGE_LOW: u1 = 0,
/// GPIO5_EDGE_HIGH [23:23]
/// No description
GPIO5_EDGE_HIGH: u1 = 0,
/// GPIO6_LEVEL_LOW [24:24]
/// No description
GPIO6_LEVEL_LOW: u1 = 0,
/// GPIO6_LEVEL_HIGH [25:25]
/// No description
GPIO6_LEVEL_HIGH: u1 = 0,
/// GPIO6_EDGE_LOW [26:26]
/// No description
GPIO6_EDGE_LOW: u1 = 0,
/// GPIO6_EDGE_HIGH [27:27]
/// No description
GPIO6_EDGE_HIGH: u1 = 0,
/// GPIO7_LEVEL_LOW [28:28]
/// No description
GPIO7_LEVEL_LOW: u1 = 0,
/// GPIO7_LEVEL_HIGH [29:29]
/// No description
GPIO7_LEVEL_HIGH: u1 = 0,
/// GPIO7_EDGE_LOW [30:30]
/// No description
GPIO7_EDGE_LOW: u1 = 0,
/// GPIO7_EDGE_HIGH [31:31]
/// No description
GPIO7_EDGE_HIGH: u1 = 0,
};
/// Interrupt Enable for proc0
pub const PROC0_INTE0 = Register(PROC0_INTE0_val).init(base_address + 0x100);
/// INTR3
const INTR3_val = packed struct {
/// GPIO24_LEVEL_LOW [0:0]
/// No description
GPIO24_LEVEL_LOW: u1 = 0,
/// GPIO24_LEVEL_HIGH [1:1]
/// No description
GPIO24_LEVEL_HIGH: u1 = 0,
/// GPIO24_EDGE_LOW [2:2]
/// No description
GPIO24_EDGE_LOW: u1 = 0,
/// GPIO24_EDGE_HIGH [3:3]
/// No description
GPIO24_EDGE_HIGH: u1 = 0,
/// GPIO25_LEVEL_LOW [4:4]
/// No description
GPIO25_LEVEL_LOW: u1 = 0,
/// GPIO25_LEVEL_HIGH [5:5]
/// No description
GPIO25_LEVEL_HIGH: u1 = 0,
/// GPIO25_EDGE_LOW [6:6]
/// No description
GPIO25_EDGE_LOW: u1 = 0,
/// GPIO25_EDGE_HIGH [7:7]
/// No description
GPIO25_EDGE_HIGH: u1 = 0,
/// GPIO26_LEVEL_LOW [8:8]
/// No description
GPIO26_LEVEL_LOW: u1 = 0,
/// GPIO26_LEVEL_HIGH [9:9]
/// No description
GPIO26_LEVEL_HIGH: u1 = 0,
/// GPIO26_EDGE_LOW [10:10]
/// No description
GPIO26_EDGE_LOW: u1 = 0,
/// GPIO26_EDGE_HIGH [11:11]
/// No description
GPIO26_EDGE_HIGH: u1 = 0,
/// GPIO27_LEVEL_LOW [12:12]
/// No description
GPIO27_LEVEL_LOW: u1 = 0,
/// GPIO27_LEVEL_HIGH [13:13]
/// No description
GPIO27_LEVEL_HIGH: u1 = 0,
/// GPIO27_EDGE_LOW [14:14]
/// No description
GPIO27_EDGE_LOW: u1 = 0,
/// GPIO27_EDGE_HIGH [15:15]
/// No description
GPIO27_EDGE_HIGH: u1 = 0,
/// GPIO28_LEVEL_LOW [16:16]
/// No description
GPIO28_LEVEL_LOW: u1 = 0,
/// GPIO28_LEVEL_HIGH [17:17]
/// No description
GPIO28_LEVEL_HIGH: u1 = 0,
/// GPIO28_EDGE_LOW [18:18]
/// No description
GPIO28_EDGE_LOW: u1 = 0,
/// GPIO28_EDGE_HIGH [19:19]
/// No description
GPIO28_EDGE_HIGH: u1 = 0,
/// GPIO29_LEVEL_LOW [20:20]
/// No description
GPIO29_LEVEL_LOW: u1 = 0,
/// GPIO29_LEVEL_HIGH [21:21]
/// No description
GPIO29_LEVEL_HIGH: u1 = 0,
/// GPIO29_EDGE_LOW [22:22]
/// No description
GPIO29_EDGE_LOW: u1 = 0,
/// GPIO29_EDGE_HIGH [23:23]
/// No description
GPIO29_EDGE_HIGH: u1 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Raw Interrupts
pub const INTR3 = Register(INTR3_val).init(base_address + 0xfc);
/// INTR2
const INTR2_val = packed struct {
/// GPIO16_LEVEL_LOW [0:0]
/// No description
GPIO16_LEVEL_LOW: u1 = 0,
/// GPIO16_LEVEL_HIGH [1:1]
/// No description
GPIO16_LEVEL_HIGH: u1 = 0,
/// GPIO16_EDGE_LOW [2:2]
/// No description
GPIO16_EDGE_LOW: u1 = 0,
/// GPIO16_EDGE_HIGH [3:3]
/// No description
GPIO16_EDGE_HIGH: u1 = 0,
/// GPIO17_LEVEL_LOW [4:4]
/// No description
GPIO17_LEVEL_LOW: u1 = 0,
/// GPIO17_LEVEL_HIGH [5:5]
/// No description
GPIO17_LEVEL_HIGH: u1 = 0,
/// GPIO17_EDGE_LOW [6:6]
/// No description
GPIO17_EDGE_LOW: u1 = 0,
/// GPIO17_EDGE_HIGH [7:7]
/// No description
GPIO17_EDGE_HIGH: u1 = 0,
/// GPIO18_LEVEL_LOW [8:8]
/// No description
GPIO18_LEVEL_LOW: u1 = 0,
/// GPIO18_LEVEL_HIGH [9:9]
/// No description
GPIO18_LEVEL_HIGH: u1 = 0,
/// GPIO18_EDGE_LOW [10:10]
/// No description
GPIO18_EDGE_LOW: u1 = 0,
/// GPIO18_EDGE_HIGH [11:11]
/// No description
GPIO18_EDGE_HIGH: u1 = 0,
/// GPIO19_LEVEL_LOW [12:12]
/// No description
GPIO19_LEVEL_LOW: u1 = 0,
/// GPIO19_LEVEL_HIGH [13:13]
/// No description
GPIO19_LEVEL_HIGH: u1 = 0,
/// GPIO19_EDGE_LOW [14:14]
/// No description
GPIO19_EDGE_LOW: u1 = 0,
/// GPIO19_EDGE_HIGH [15:15]
/// No description
GPIO19_EDGE_HIGH: u1 = 0,
/// GPIO20_LEVEL_LOW [16:16]
/// No description
GPIO20_LEVEL_LOW: u1 = 0,
/// GPIO20_LEVEL_HIGH [17:17]
/// No description
GPIO20_LEVEL_HIGH: u1 = 0,
/// GPIO20_EDGE_LOW [18:18]
/// No description
GPIO20_EDGE_LOW: u1 = 0,
/// GPIO20_EDGE_HIGH [19:19]
/// No description
GPIO20_EDGE_HIGH: u1 = 0,
/// GPIO21_LEVEL_LOW [20:20]
/// No description
GPIO21_LEVEL_LOW: u1 = 0,
/// GPIO21_LEVEL_HIGH [21:21]
/// No description
GPIO21_LEVEL_HIGH: u1 = 0,
/// GPIO21_EDGE_LOW [22:22]
/// No description
GPIO21_EDGE_LOW: u1 = 0,
/// GPIO21_EDGE_HIGH [23:23]
/// No description
GPIO21_EDGE_HIGH: u1 = 0,
/// GPIO22_LEVEL_LOW [24:24]
/// No description
GPIO22_LEVEL_LOW: u1 = 0,
/// GPIO22_LEVEL_HIGH [25:25]
/// No description
GPIO22_LEVEL_HIGH: u1 = 0,
/// GPIO22_EDGE_LOW [26:26]
/// No description
GPIO22_EDGE_LOW: u1 = 0,
/// GPIO22_EDGE_HIGH [27:27]
/// No description
GPIO22_EDGE_HIGH: u1 = 0,
/// GPIO23_LEVEL_LOW [28:28]
/// No description
GPIO23_LEVEL_LOW: u1 = 0,
/// GPIO23_LEVEL_HIGH [29:29]
/// No description
GPIO23_LEVEL_HIGH: u1 = 0,
/// GPIO23_EDGE_LOW [30:30]
/// No description
GPIO23_EDGE_LOW: u1 = 0,
/// GPIO23_EDGE_HIGH [31:31]
/// No description
GPIO23_EDGE_HIGH: u1 = 0,
};
/// Raw Interrupts
pub const INTR2 = Register(INTR2_val).init(base_address + 0xf8);
/// INTR1
const INTR1_val = packed struct {
/// GPIO8_LEVEL_LOW [0:0]
/// No description
GPIO8_LEVEL_LOW: u1 = 0,
/// GPIO8_LEVEL_HIGH [1:1]
/// No description
GPIO8_LEVEL_HIGH: u1 = 0,
/// GPIO8_EDGE_LOW [2:2]
/// No description
GPIO8_EDGE_LOW: u1 = 0,
/// GPIO8_EDGE_HIGH [3:3]
/// No description
GPIO8_EDGE_HIGH: u1 = 0,
/// GPIO9_LEVEL_LOW [4:4]
/// No description
GPIO9_LEVEL_LOW: u1 = 0,
/// GPIO9_LEVEL_HIGH [5:5]
/// No description
GPIO9_LEVEL_HIGH: u1 = 0,
/// GPIO9_EDGE_LOW [6:6]
/// No description
GPIO9_EDGE_LOW: u1 = 0,
/// GPIO9_EDGE_HIGH [7:7]
/// No description
GPIO9_EDGE_HIGH: u1 = 0,
/// GPIO10_LEVEL_LOW [8:8]
/// No description
GPIO10_LEVEL_LOW: u1 = 0,
/// GPIO10_LEVEL_HIGH [9:9]
/// No description
GPIO10_LEVEL_HIGH: u1 = 0,
/// GPIO10_EDGE_LOW [10:10]
/// No description
GPIO10_EDGE_LOW: u1 = 0,
/// GPIO10_EDGE_HIGH [11:11]
/// No description
GPIO10_EDGE_HIGH: u1 = 0,
/// GPIO11_LEVEL_LOW [12:12]
/// No description
GPIO11_LEVEL_LOW: u1 = 0,
/// GPIO11_LEVEL_HIGH [13:13]
/// No description
GPIO11_LEVEL_HIGH: u1 = 0,
/// GPIO11_EDGE_LOW [14:14]
/// No description
GPIO11_EDGE_LOW: u1 = 0,
/// GPIO11_EDGE_HIGH [15:15]
/// No description
GPIO11_EDGE_HIGH: u1 = 0,
/// GPIO12_LEVEL_LOW [16:16]
/// No description
GPIO12_LEVEL_LOW: u1 = 0,
/// GPIO12_LEVEL_HIGH [17:17]
/// No description
GPIO12_LEVEL_HIGH: u1 = 0,
/// GPIO12_EDGE_LOW [18:18]
/// No description
GPIO12_EDGE_LOW: u1 = 0,
/// GPIO12_EDGE_HIGH [19:19]
/// No description
GPIO12_EDGE_HIGH: u1 = 0,
/// GPIO13_LEVEL_LOW [20:20]
/// No description
GPIO13_LEVEL_LOW: u1 = 0,
/// GPIO13_LEVEL_HIGH [21:21]
/// No description
GPIO13_LEVEL_HIGH: u1 = 0,
/// GPIO13_EDGE_LOW [22:22]
/// No description
GPIO13_EDGE_LOW: u1 = 0,
/// GPIO13_EDGE_HIGH [23:23]
/// No description
GPIO13_EDGE_HIGH: u1 = 0,
/// GPIO14_LEVEL_LOW [24:24]
/// No description
GPIO14_LEVEL_LOW: u1 = 0,
/// GPIO14_LEVEL_HIGH [25:25]
/// No description
GPIO14_LEVEL_HIGH: u1 = 0,
/// GPIO14_EDGE_LOW [26:26]
/// No description
GPIO14_EDGE_LOW: u1 = 0,
/// GPIO14_EDGE_HIGH [27:27]
/// No description
GPIO14_EDGE_HIGH: u1 = 0,
/// GPIO15_LEVEL_LOW [28:28]
/// No description
GPIO15_LEVEL_LOW: u1 = 0,
/// GPIO15_LEVEL_HIGH [29:29]
/// No description
GPIO15_LEVEL_HIGH: u1 = 0,
/// GPIO15_EDGE_LOW [30:30]
/// No description
GPIO15_EDGE_LOW: u1 = 0,
/// GPIO15_EDGE_HIGH [31:31]
/// No description
GPIO15_EDGE_HIGH: u1 = 0,
};
/// Raw Interrupts
pub const INTR1 = Register(INTR1_val).init(base_address + 0xf4);
/// INTR0
const INTR0_val = packed struct {
/// GPIO0_LEVEL_LOW [0:0]
/// No description
GPIO0_LEVEL_LOW: u1 = 0,
/// GPIO0_LEVEL_HIGH [1:1]
/// No description
GPIO0_LEVEL_HIGH: u1 = 0,
/// GPIO0_EDGE_LOW [2:2]
/// No description
GPIO0_EDGE_LOW: u1 = 0,
/// GPIO0_EDGE_HIGH [3:3]
/// No description
GPIO0_EDGE_HIGH: u1 = 0,
/// GPIO1_LEVEL_LOW [4:4]
/// No description
GPIO1_LEVEL_LOW: u1 = 0,
/// GPIO1_LEVEL_HIGH [5:5]
/// No description
GPIO1_LEVEL_HIGH: u1 = 0,
/// GPIO1_EDGE_LOW [6:6]
/// No description
GPIO1_EDGE_LOW: u1 = 0,
/// GPIO1_EDGE_HIGH [7:7]
/// No description
GPIO1_EDGE_HIGH: u1 = 0,
/// GPIO2_LEVEL_LOW [8:8]
/// No description
GPIO2_LEVEL_LOW: u1 = 0,
/// GPIO2_LEVEL_HIGH [9:9]
/// No description
GPIO2_LEVEL_HIGH: u1 = 0,
/// GPIO2_EDGE_LOW [10:10]
/// No description
GPIO2_EDGE_LOW: u1 = 0,
/// GPIO2_EDGE_HIGH [11:11]
/// No description
GPIO2_EDGE_HIGH: u1 = 0,
/// GPIO3_LEVEL_LOW [12:12]
/// No description
GPIO3_LEVEL_LOW: u1 = 0,
/// GPIO3_LEVEL_HIGH [13:13]
/// No description
GPIO3_LEVEL_HIGH: u1 = 0,
/// GPIO3_EDGE_LOW [14:14]
/// No description
GPIO3_EDGE_LOW: u1 = 0,
/// GPIO3_EDGE_HIGH [15:15]
/// No description
GPIO3_EDGE_HIGH: u1 = 0,
/// GPIO4_LEVEL_LOW [16:16]
/// No description
GPIO4_LEVEL_LOW: u1 = 0,
/// GPIO4_LEVEL_HIGH [17:17]
/// No description
GPIO4_LEVEL_HIGH: u1 = 0,
/// GPIO4_EDGE_LOW [18:18]
/// No description
GPIO4_EDGE_LOW: u1 = 0,
/// GPIO4_EDGE_HIGH [19:19]
/// No description
GPIO4_EDGE_HIGH: u1 = 0,
/// GPIO5_LEVEL_LOW [20:20]
/// No description
GPIO5_LEVEL_LOW: u1 = 0,
/// GPIO5_LEVEL_HIGH [21:21]
/// No description
GPIO5_LEVEL_HIGH: u1 = 0,
/// GPIO5_EDGE_LOW [22:22]
/// No description
GPIO5_EDGE_LOW: u1 = 0,
/// GPIO5_EDGE_HIGH [23:23]
/// No description
GPIO5_EDGE_HIGH: u1 = 0,
/// GPIO6_LEVEL_LOW [24:24]
/// No description
GPIO6_LEVEL_LOW: u1 = 0,
/// GPIO6_LEVEL_HIGH [25:25]
/// No description
GPIO6_LEVEL_HIGH: u1 = 0,
/// GPIO6_EDGE_LOW [26:26]
/// No description
GPIO6_EDGE_LOW: u1 = 0,
/// GPIO6_EDGE_HIGH [27:27]
/// No description
GPIO6_EDGE_HIGH: u1 = 0,
/// GPIO7_LEVEL_LOW [28:28]
/// No description
GPIO7_LEVEL_LOW: u1 = 0,
/// GPIO7_LEVEL_HIGH [29:29]
/// No description
GPIO7_LEVEL_HIGH: u1 = 0,
/// GPIO7_EDGE_LOW [30:30]
/// No description
GPIO7_EDGE_LOW: u1 = 0,
/// GPIO7_EDGE_HIGH [31:31]
/// No description
GPIO7_EDGE_HIGH: u1 = 0,
};
/// Raw Interrupts
pub const INTR0 = Register(INTR0_val).init(base_address + 0xf0);
/// GPIO29_CTRL
const GPIO29_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO29_CTRL = Register(GPIO29_CTRL_val).init(base_address + 0xec);
/// GPIO29_STATUS
const GPIO29_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO29_STATUS = Register(GPIO29_STATUS_val).init(base_address + 0xe8);
/// GPIO28_CTRL
const GPIO28_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO28_CTRL = Register(GPIO28_CTRL_val).init(base_address + 0xe4);
/// GPIO28_STATUS
const GPIO28_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO28_STATUS = Register(GPIO28_STATUS_val).init(base_address + 0xe0);
/// GPIO27_CTRL
const GPIO27_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO27_CTRL = Register(GPIO27_CTRL_val).init(base_address + 0xdc);
/// GPIO27_STATUS
const GPIO27_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO27_STATUS = Register(GPIO27_STATUS_val).init(base_address + 0xd8);
/// GPIO26_CTRL
const GPIO26_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO26_CTRL = Register(GPIO26_CTRL_val).init(base_address + 0xd4);
/// GPIO26_STATUS
const GPIO26_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO26_STATUS = Register(GPIO26_STATUS_val).init(base_address + 0xd0);
/// GPIO25_CTRL
const GPIO25_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO25_CTRL = Register(GPIO25_CTRL_val).init(base_address + 0xcc);
/// GPIO25_STATUS
const GPIO25_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO25_STATUS = Register(GPIO25_STATUS_val).init(base_address + 0xc8);
/// GPIO24_CTRL
const GPIO24_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO24_CTRL = Register(GPIO24_CTRL_val).init(base_address + 0xc4);
/// GPIO24_STATUS
const GPIO24_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO24_STATUS = Register(GPIO24_STATUS_val).init(base_address + 0xc0);
/// GPIO23_CTRL
const GPIO23_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO23_CTRL = Register(GPIO23_CTRL_val).init(base_address + 0xbc);
/// GPIO23_STATUS
const GPIO23_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO23_STATUS = Register(GPIO23_STATUS_val).init(base_address + 0xb8);
/// GPIO22_CTRL
const GPIO22_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO22_CTRL = Register(GPIO22_CTRL_val).init(base_address + 0xb4);
/// GPIO22_STATUS
const GPIO22_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO22_STATUS = Register(GPIO22_STATUS_val).init(base_address + 0xb0);
/// GPIO21_CTRL
const GPIO21_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO21_CTRL = Register(GPIO21_CTRL_val).init(base_address + 0xac);
/// GPIO21_STATUS
const GPIO21_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO21_STATUS = Register(GPIO21_STATUS_val).init(base_address + 0xa8);
/// GPIO20_CTRL
const GPIO20_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO20_CTRL = Register(GPIO20_CTRL_val).init(base_address + 0xa4);
/// GPIO20_STATUS
const GPIO20_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO20_STATUS = Register(GPIO20_STATUS_val).init(base_address + 0xa0);
/// GPIO19_CTRL
const GPIO19_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO19_CTRL = Register(GPIO19_CTRL_val).init(base_address + 0x9c);
/// GPIO19_STATUS
const GPIO19_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO19_STATUS = Register(GPIO19_STATUS_val).init(base_address + 0x98);
/// GPIO18_CTRL
const GPIO18_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO18_CTRL = Register(GPIO18_CTRL_val).init(base_address + 0x94);
/// GPIO18_STATUS
const GPIO18_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO18_STATUS = Register(GPIO18_STATUS_val).init(base_address + 0x90);
/// GPIO17_CTRL
const GPIO17_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO17_CTRL = Register(GPIO17_CTRL_val).init(base_address + 0x8c);
/// GPIO17_STATUS
const GPIO17_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO17_STATUS = Register(GPIO17_STATUS_val).init(base_address + 0x88);
/// GPIO16_CTRL
const GPIO16_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO16_CTRL = Register(GPIO16_CTRL_val).init(base_address + 0x84);
/// GPIO16_STATUS
const GPIO16_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO16_STATUS = Register(GPIO16_STATUS_val).init(base_address + 0x80);
/// GPIO15_CTRL
const GPIO15_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO15_CTRL = Register(GPIO15_CTRL_val).init(base_address + 0x7c);
/// GPIO15_STATUS
const GPIO15_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO15_STATUS = Register(GPIO15_STATUS_val).init(base_address + 0x78);
/// GPIO14_CTRL
const GPIO14_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO14_CTRL = Register(GPIO14_CTRL_val).init(base_address + 0x74);
/// GPIO14_STATUS
const GPIO14_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO14_STATUS = Register(GPIO14_STATUS_val).init(base_address + 0x70);
/// GPIO13_CTRL
const GPIO13_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO13_CTRL = Register(GPIO13_CTRL_val).init(base_address + 0x6c);
/// GPIO13_STATUS
const GPIO13_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO13_STATUS = Register(GPIO13_STATUS_val).init(base_address + 0x68);
/// GPIO12_CTRL
const GPIO12_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO12_CTRL = Register(GPIO12_CTRL_val).init(base_address + 0x64);
/// GPIO12_STATUS
const GPIO12_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO12_STATUS = Register(GPIO12_STATUS_val).init(base_address + 0x60);
/// GPIO11_CTRL
const GPIO11_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO11_CTRL = Register(GPIO11_CTRL_val).init(base_address + 0x5c);
/// GPIO11_STATUS
const GPIO11_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO11_STATUS = Register(GPIO11_STATUS_val).init(base_address + 0x58);
/// GPIO10_CTRL
const GPIO10_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO10_CTRL = Register(GPIO10_CTRL_val).init(base_address + 0x54);
/// GPIO10_STATUS
const GPIO10_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO10_STATUS = Register(GPIO10_STATUS_val).init(base_address + 0x50);
/// GPIO9_CTRL
const GPIO9_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO9_CTRL = Register(GPIO9_CTRL_val).init(base_address + 0x4c);
/// GPIO9_STATUS
const GPIO9_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO9_STATUS = Register(GPIO9_STATUS_val).init(base_address + 0x48);
/// GPIO8_CTRL
const GPIO8_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO8_CTRL = Register(GPIO8_CTRL_val).init(base_address + 0x44);
/// GPIO8_STATUS
const GPIO8_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO8_STATUS = Register(GPIO8_STATUS_val).init(base_address + 0x40);
/// GPIO7_CTRL
const GPIO7_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO7_CTRL = Register(GPIO7_CTRL_val).init(base_address + 0x3c);
/// GPIO7_STATUS
const GPIO7_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO7_STATUS = Register(GPIO7_STATUS_val).init(base_address + 0x38);
/// GPIO6_CTRL
const GPIO6_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO6_CTRL = Register(GPIO6_CTRL_val).init(base_address + 0x34);
/// GPIO6_STATUS
const GPIO6_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO6_STATUS = Register(GPIO6_STATUS_val).init(base_address + 0x30);
/// GPIO5_CTRL
const GPIO5_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO5_CTRL = Register(GPIO5_CTRL_val).init(base_address + 0x2c);
/// GPIO5_STATUS
const GPIO5_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO5_STATUS = Register(GPIO5_STATUS_val).init(base_address + 0x28);
/// GPIO4_CTRL
const GPIO4_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO4_CTRL = Register(GPIO4_CTRL_val).init(base_address + 0x24);
/// GPIO4_STATUS
const GPIO4_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO4_STATUS = Register(GPIO4_STATUS_val).init(base_address + 0x20);
/// GPIO3_CTRL
const GPIO3_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO3_CTRL = Register(GPIO3_CTRL_val).init(base_address + 0x1c);
/// GPIO3_STATUS
const GPIO3_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO3_STATUS = Register(GPIO3_STATUS_val).init(base_address + 0x18);
/// GPIO2_CTRL
const GPIO2_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO2_CTRL = Register(GPIO2_CTRL_val).init(base_address + 0x14);
/// GPIO2_STATUS
const GPIO2_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO2_STATUS = Register(GPIO2_STATUS_val).init(base_address + 0x10);
/// GPIO1_CTRL
const GPIO1_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO1_CTRL = Register(GPIO1_CTRL_val).init(base_address + 0xc);
/// GPIO1_STATUS
const GPIO1_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO1_STATUS = Register(GPIO1_STATUS_val).init(base_address + 0x8);
/// GPIO0_CTRL
const GPIO0_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO0_CTRL = Register(GPIO0_CTRL_val).init(base_address + 0x4);
/// GPIO0_STATUS
const GPIO0_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO0_STATUS = Register(GPIO0_STATUS_val).init(base_address + 0x0);
};
/// No description
pub const IO_QSPI = struct {
const base_address = 0x40018000;
/// DORMANT_WAKE_INTS
const DORMANT_WAKE_INTS_val = packed struct {
/// GPIO_QSPI_SCLK_LEVEL_LOW [0:0]
/// No description
GPIO_QSPI_SCLK_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SCLK_LEVEL_HIGH [1:1]
/// No description
GPIO_QSPI_SCLK_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SCLK_EDGE_LOW [2:2]
/// No description
GPIO_QSPI_SCLK_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SCLK_EDGE_HIGH [3:3]
/// No description
GPIO_QSPI_SCLK_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SS_LEVEL_LOW [4:4]
/// No description
GPIO_QSPI_SS_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SS_LEVEL_HIGH [5:5]
/// No description
GPIO_QSPI_SS_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SS_EDGE_LOW [6:6]
/// No description
GPIO_QSPI_SS_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SS_EDGE_HIGH [7:7]
/// No description
GPIO_QSPI_SS_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD0_LEVEL_LOW [8:8]
/// No description
GPIO_QSPI_SD0_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD0_LEVEL_HIGH [9:9]
/// No description
GPIO_QSPI_SD0_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD0_EDGE_LOW [10:10]
/// No description
GPIO_QSPI_SD0_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD0_EDGE_HIGH [11:11]
/// No description
GPIO_QSPI_SD0_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD1_LEVEL_LOW [12:12]
/// No description
GPIO_QSPI_SD1_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD1_LEVEL_HIGH [13:13]
/// No description
GPIO_QSPI_SD1_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD1_EDGE_LOW [14:14]
/// No description
GPIO_QSPI_SD1_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD1_EDGE_HIGH [15:15]
/// No description
GPIO_QSPI_SD1_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD2_LEVEL_LOW [16:16]
/// No description
GPIO_QSPI_SD2_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD2_LEVEL_HIGH [17:17]
/// No description
GPIO_QSPI_SD2_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD2_EDGE_LOW [18:18]
/// No description
GPIO_QSPI_SD2_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD2_EDGE_HIGH [19:19]
/// No description
GPIO_QSPI_SD2_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD3_LEVEL_LOW [20:20]
/// No description
GPIO_QSPI_SD3_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD3_LEVEL_HIGH [21:21]
/// No description
GPIO_QSPI_SD3_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD3_EDGE_LOW [22:22]
/// No description
GPIO_QSPI_SD3_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD3_EDGE_HIGH [23:23]
/// No description
GPIO_QSPI_SD3_EDGE_HIGH: u1 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Interrupt status after masking & forcing for dormant_wake
pub const DORMANT_WAKE_INTS = Register(DORMANT_WAKE_INTS_val).init(base_address + 0x54);
/// DORMANT_WAKE_INTF
const DORMANT_WAKE_INTF_val = packed struct {
/// GPIO_QSPI_SCLK_LEVEL_LOW [0:0]
/// No description
GPIO_QSPI_SCLK_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SCLK_LEVEL_HIGH [1:1]
/// No description
GPIO_QSPI_SCLK_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SCLK_EDGE_LOW [2:2]
/// No description
GPIO_QSPI_SCLK_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SCLK_EDGE_HIGH [3:3]
/// No description
GPIO_QSPI_SCLK_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SS_LEVEL_LOW [4:4]
/// No description
GPIO_QSPI_SS_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SS_LEVEL_HIGH [5:5]
/// No description
GPIO_QSPI_SS_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SS_EDGE_LOW [6:6]
/// No description
GPIO_QSPI_SS_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SS_EDGE_HIGH [7:7]
/// No description
GPIO_QSPI_SS_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD0_LEVEL_LOW [8:8]
/// No description
GPIO_QSPI_SD0_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD0_LEVEL_HIGH [9:9]
/// No description
GPIO_QSPI_SD0_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD0_EDGE_LOW [10:10]
/// No description
GPIO_QSPI_SD0_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD0_EDGE_HIGH [11:11]
/// No description
GPIO_QSPI_SD0_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD1_LEVEL_LOW [12:12]
/// No description
GPIO_QSPI_SD1_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD1_LEVEL_HIGH [13:13]
/// No description
GPIO_QSPI_SD1_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD1_EDGE_LOW [14:14]
/// No description
GPIO_QSPI_SD1_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD1_EDGE_HIGH [15:15]
/// No description
GPIO_QSPI_SD1_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD2_LEVEL_LOW [16:16]
/// No description
GPIO_QSPI_SD2_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD2_LEVEL_HIGH [17:17]
/// No description
GPIO_QSPI_SD2_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD2_EDGE_LOW [18:18]
/// No description
GPIO_QSPI_SD2_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD2_EDGE_HIGH [19:19]
/// No description
GPIO_QSPI_SD2_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD3_LEVEL_LOW [20:20]
/// No description
GPIO_QSPI_SD3_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD3_LEVEL_HIGH [21:21]
/// No description
GPIO_QSPI_SD3_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD3_EDGE_LOW [22:22]
/// No description
GPIO_QSPI_SD3_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD3_EDGE_HIGH [23:23]
/// No description
GPIO_QSPI_SD3_EDGE_HIGH: u1 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Interrupt Force for dormant_wake
pub const DORMANT_WAKE_INTF = Register(DORMANT_WAKE_INTF_val).init(base_address + 0x50);
/// DORMANT_WAKE_INTE
const DORMANT_WAKE_INTE_val = packed struct {
/// GPIO_QSPI_SCLK_LEVEL_LOW [0:0]
/// No description
GPIO_QSPI_SCLK_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SCLK_LEVEL_HIGH [1:1]
/// No description
GPIO_QSPI_SCLK_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SCLK_EDGE_LOW [2:2]
/// No description
GPIO_QSPI_SCLK_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SCLK_EDGE_HIGH [3:3]
/// No description
GPIO_QSPI_SCLK_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SS_LEVEL_LOW [4:4]
/// No description
GPIO_QSPI_SS_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SS_LEVEL_HIGH [5:5]
/// No description
GPIO_QSPI_SS_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SS_EDGE_LOW [6:6]
/// No description
GPIO_QSPI_SS_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SS_EDGE_HIGH [7:7]
/// No description
GPIO_QSPI_SS_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD0_LEVEL_LOW [8:8]
/// No description
GPIO_QSPI_SD0_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD0_LEVEL_HIGH [9:9]
/// No description
GPIO_QSPI_SD0_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD0_EDGE_LOW [10:10]
/// No description
GPIO_QSPI_SD0_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD0_EDGE_HIGH [11:11]
/// No description
GPIO_QSPI_SD0_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD1_LEVEL_LOW [12:12]
/// No description
GPIO_QSPI_SD1_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD1_LEVEL_HIGH [13:13]
/// No description
GPIO_QSPI_SD1_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD1_EDGE_LOW [14:14]
/// No description
GPIO_QSPI_SD1_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD1_EDGE_HIGH [15:15]
/// No description
GPIO_QSPI_SD1_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD2_LEVEL_LOW [16:16]
/// No description
GPIO_QSPI_SD2_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD2_LEVEL_HIGH [17:17]
/// No description
GPIO_QSPI_SD2_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD2_EDGE_LOW [18:18]
/// No description
GPIO_QSPI_SD2_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD2_EDGE_HIGH [19:19]
/// No description
GPIO_QSPI_SD2_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD3_LEVEL_LOW [20:20]
/// No description
GPIO_QSPI_SD3_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD3_LEVEL_HIGH [21:21]
/// No description
GPIO_QSPI_SD3_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD3_EDGE_LOW [22:22]
/// No description
GPIO_QSPI_SD3_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD3_EDGE_HIGH [23:23]
/// No description
GPIO_QSPI_SD3_EDGE_HIGH: u1 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Interrupt Enable for dormant_wake
pub const DORMANT_WAKE_INTE = Register(DORMANT_WAKE_INTE_val).init(base_address + 0x4c);
/// PROC1_INTS
const PROC1_INTS_val = packed struct {
/// GPIO_QSPI_SCLK_LEVEL_LOW [0:0]
/// No description
GPIO_QSPI_SCLK_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SCLK_LEVEL_HIGH [1:1]
/// No description
GPIO_QSPI_SCLK_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SCLK_EDGE_LOW [2:2]
/// No description
GPIO_QSPI_SCLK_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SCLK_EDGE_HIGH [3:3]
/// No description
GPIO_QSPI_SCLK_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SS_LEVEL_LOW [4:4]
/// No description
GPIO_QSPI_SS_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SS_LEVEL_HIGH [5:5]
/// No description
GPIO_QSPI_SS_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SS_EDGE_LOW [6:6]
/// No description
GPIO_QSPI_SS_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SS_EDGE_HIGH [7:7]
/// No description
GPIO_QSPI_SS_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD0_LEVEL_LOW [8:8]
/// No description
GPIO_QSPI_SD0_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD0_LEVEL_HIGH [9:9]
/// No description
GPIO_QSPI_SD0_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD0_EDGE_LOW [10:10]
/// No description
GPIO_QSPI_SD0_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD0_EDGE_HIGH [11:11]
/// No description
GPIO_QSPI_SD0_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD1_LEVEL_LOW [12:12]
/// No description
GPIO_QSPI_SD1_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD1_LEVEL_HIGH [13:13]
/// No description
GPIO_QSPI_SD1_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD1_EDGE_LOW [14:14]
/// No description
GPIO_QSPI_SD1_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD1_EDGE_HIGH [15:15]
/// No description
GPIO_QSPI_SD1_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD2_LEVEL_LOW [16:16]
/// No description
GPIO_QSPI_SD2_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD2_LEVEL_HIGH [17:17]
/// No description
GPIO_QSPI_SD2_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD2_EDGE_LOW [18:18]
/// No description
GPIO_QSPI_SD2_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD2_EDGE_HIGH [19:19]
/// No description
GPIO_QSPI_SD2_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD3_LEVEL_LOW [20:20]
/// No description
GPIO_QSPI_SD3_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD3_LEVEL_HIGH [21:21]
/// No description
GPIO_QSPI_SD3_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD3_EDGE_LOW [22:22]
/// No description
GPIO_QSPI_SD3_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD3_EDGE_HIGH [23:23]
/// No description
GPIO_QSPI_SD3_EDGE_HIGH: u1 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Interrupt status after masking & forcing for proc1
pub const PROC1_INTS = Register(PROC1_INTS_val).init(base_address + 0x48);
/// PROC1_INTF
const PROC1_INTF_val = packed struct {
/// GPIO_QSPI_SCLK_LEVEL_LOW [0:0]
/// No description
GPIO_QSPI_SCLK_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SCLK_LEVEL_HIGH [1:1]
/// No description
GPIO_QSPI_SCLK_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SCLK_EDGE_LOW [2:2]
/// No description
GPIO_QSPI_SCLK_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SCLK_EDGE_HIGH [3:3]
/// No description
GPIO_QSPI_SCLK_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SS_LEVEL_LOW [4:4]
/// No description
GPIO_QSPI_SS_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SS_LEVEL_HIGH [5:5]
/// No description
GPIO_QSPI_SS_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SS_EDGE_LOW [6:6]
/// No description
GPIO_QSPI_SS_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SS_EDGE_HIGH [7:7]
/// No description
GPIO_QSPI_SS_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD0_LEVEL_LOW [8:8]
/// No description
GPIO_QSPI_SD0_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD0_LEVEL_HIGH [9:9]
/// No description
GPIO_QSPI_SD0_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD0_EDGE_LOW [10:10]
/// No description
GPIO_QSPI_SD0_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD0_EDGE_HIGH [11:11]
/// No description
GPIO_QSPI_SD0_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD1_LEVEL_LOW [12:12]
/// No description
GPIO_QSPI_SD1_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD1_LEVEL_HIGH [13:13]
/// No description
GPIO_QSPI_SD1_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD1_EDGE_LOW [14:14]
/// No description
GPIO_QSPI_SD1_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD1_EDGE_HIGH [15:15]
/// No description
GPIO_QSPI_SD1_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD2_LEVEL_LOW [16:16]
/// No description
GPIO_QSPI_SD2_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD2_LEVEL_HIGH [17:17]
/// No description
GPIO_QSPI_SD2_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD2_EDGE_LOW [18:18]
/// No description
GPIO_QSPI_SD2_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD2_EDGE_HIGH [19:19]
/// No description
GPIO_QSPI_SD2_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD3_LEVEL_LOW [20:20]
/// No description
GPIO_QSPI_SD3_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD3_LEVEL_HIGH [21:21]
/// No description
GPIO_QSPI_SD3_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD3_EDGE_LOW [22:22]
/// No description
GPIO_QSPI_SD3_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD3_EDGE_HIGH [23:23]
/// No description
GPIO_QSPI_SD3_EDGE_HIGH: u1 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Interrupt Force for proc1
pub const PROC1_INTF = Register(PROC1_INTF_val).init(base_address + 0x44);
/// PROC1_INTE
const PROC1_INTE_val = packed struct {
/// GPIO_QSPI_SCLK_LEVEL_LOW [0:0]
/// No description
GPIO_QSPI_SCLK_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SCLK_LEVEL_HIGH [1:1]
/// No description
GPIO_QSPI_SCLK_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SCLK_EDGE_LOW [2:2]
/// No description
GPIO_QSPI_SCLK_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SCLK_EDGE_HIGH [3:3]
/// No description
GPIO_QSPI_SCLK_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SS_LEVEL_LOW [4:4]
/// No description
GPIO_QSPI_SS_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SS_LEVEL_HIGH [5:5]
/// No description
GPIO_QSPI_SS_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SS_EDGE_LOW [6:6]
/// No description
GPIO_QSPI_SS_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SS_EDGE_HIGH [7:7]
/// No description
GPIO_QSPI_SS_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD0_LEVEL_LOW [8:8]
/// No description
GPIO_QSPI_SD0_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD0_LEVEL_HIGH [9:9]
/// No description
GPIO_QSPI_SD0_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD0_EDGE_LOW [10:10]
/// No description
GPIO_QSPI_SD0_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD0_EDGE_HIGH [11:11]
/// No description
GPIO_QSPI_SD0_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD1_LEVEL_LOW [12:12]
/// No description
GPIO_QSPI_SD1_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD1_LEVEL_HIGH [13:13]
/// No description
GPIO_QSPI_SD1_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD1_EDGE_LOW [14:14]
/// No description
GPIO_QSPI_SD1_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD1_EDGE_HIGH [15:15]
/// No description
GPIO_QSPI_SD1_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD2_LEVEL_LOW [16:16]
/// No description
GPIO_QSPI_SD2_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD2_LEVEL_HIGH [17:17]
/// No description
GPIO_QSPI_SD2_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD2_EDGE_LOW [18:18]
/// No description
GPIO_QSPI_SD2_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD2_EDGE_HIGH [19:19]
/// No description
GPIO_QSPI_SD2_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD3_LEVEL_LOW [20:20]
/// No description
GPIO_QSPI_SD3_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD3_LEVEL_HIGH [21:21]
/// No description
GPIO_QSPI_SD3_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD3_EDGE_LOW [22:22]
/// No description
GPIO_QSPI_SD3_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD3_EDGE_HIGH [23:23]
/// No description
GPIO_QSPI_SD3_EDGE_HIGH: u1 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Interrupt Enable for proc1
pub const PROC1_INTE = Register(PROC1_INTE_val).init(base_address + 0x40);
/// PROC0_INTS
const PROC0_INTS_val = packed struct {
/// GPIO_QSPI_SCLK_LEVEL_LOW [0:0]
/// No description
GPIO_QSPI_SCLK_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SCLK_LEVEL_HIGH [1:1]
/// No description
GPIO_QSPI_SCLK_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SCLK_EDGE_LOW [2:2]
/// No description
GPIO_QSPI_SCLK_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SCLK_EDGE_HIGH [3:3]
/// No description
GPIO_QSPI_SCLK_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SS_LEVEL_LOW [4:4]
/// No description
GPIO_QSPI_SS_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SS_LEVEL_HIGH [5:5]
/// No description
GPIO_QSPI_SS_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SS_EDGE_LOW [6:6]
/// No description
GPIO_QSPI_SS_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SS_EDGE_HIGH [7:7]
/// No description
GPIO_QSPI_SS_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD0_LEVEL_LOW [8:8]
/// No description
GPIO_QSPI_SD0_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD0_LEVEL_HIGH [9:9]
/// No description
GPIO_QSPI_SD0_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD0_EDGE_LOW [10:10]
/// No description
GPIO_QSPI_SD0_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD0_EDGE_HIGH [11:11]
/// No description
GPIO_QSPI_SD0_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD1_LEVEL_LOW [12:12]
/// No description
GPIO_QSPI_SD1_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD1_LEVEL_HIGH [13:13]
/// No description
GPIO_QSPI_SD1_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD1_EDGE_LOW [14:14]
/// No description
GPIO_QSPI_SD1_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD1_EDGE_HIGH [15:15]
/// No description
GPIO_QSPI_SD1_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD2_LEVEL_LOW [16:16]
/// No description
GPIO_QSPI_SD2_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD2_LEVEL_HIGH [17:17]
/// No description
GPIO_QSPI_SD2_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD2_EDGE_LOW [18:18]
/// No description
GPIO_QSPI_SD2_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD2_EDGE_HIGH [19:19]
/// No description
GPIO_QSPI_SD2_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD3_LEVEL_LOW [20:20]
/// No description
GPIO_QSPI_SD3_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD3_LEVEL_HIGH [21:21]
/// No description
GPIO_QSPI_SD3_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD3_EDGE_LOW [22:22]
/// No description
GPIO_QSPI_SD3_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD3_EDGE_HIGH [23:23]
/// No description
GPIO_QSPI_SD3_EDGE_HIGH: u1 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Interrupt status after masking & forcing for proc0
pub const PROC0_INTS = Register(PROC0_INTS_val).init(base_address + 0x3c);
/// PROC0_INTF
const PROC0_INTF_val = packed struct {
/// GPIO_QSPI_SCLK_LEVEL_LOW [0:0]
/// No description
GPIO_QSPI_SCLK_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SCLK_LEVEL_HIGH [1:1]
/// No description
GPIO_QSPI_SCLK_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SCLK_EDGE_LOW [2:2]
/// No description
GPIO_QSPI_SCLK_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SCLK_EDGE_HIGH [3:3]
/// No description
GPIO_QSPI_SCLK_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SS_LEVEL_LOW [4:4]
/// No description
GPIO_QSPI_SS_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SS_LEVEL_HIGH [5:5]
/// No description
GPIO_QSPI_SS_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SS_EDGE_LOW [6:6]
/// No description
GPIO_QSPI_SS_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SS_EDGE_HIGH [7:7]
/// No description
GPIO_QSPI_SS_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD0_LEVEL_LOW [8:8]
/// No description
GPIO_QSPI_SD0_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD0_LEVEL_HIGH [9:9]
/// No description
GPIO_QSPI_SD0_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD0_EDGE_LOW [10:10]
/// No description
GPIO_QSPI_SD0_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD0_EDGE_HIGH [11:11]
/// No description
GPIO_QSPI_SD0_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD1_LEVEL_LOW [12:12]
/// No description
GPIO_QSPI_SD1_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD1_LEVEL_HIGH [13:13]
/// No description
GPIO_QSPI_SD1_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD1_EDGE_LOW [14:14]
/// No description
GPIO_QSPI_SD1_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD1_EDGE_HIGH [15:15]
/// No description
GPIO_QSPI_SD1_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD2_LEVEL_LOW [16:16]
/// No description
GPIO_QSPI_SD2_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD2_LEVEL_HIGH [17:17]
/// No description
GPIO_QSPI_SD2_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD2_EDGE_LOW [18:18]
/// No description
GPIO_QSPI_SD2_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD2_EDGE_HIGH [19:19]
/// No description
GPIO_QSPI_SD2_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD3_LEVEL_LOW [20:20]
/// No description
GPIO_QSPI_SD3_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD3_LEVEL_HIGH [21:21]
/// No description
GPIO_QSPI_SD3_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD3_EDGE_LOW [22:22]
/// No description
GPIO_QSPI_SD3_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD3_EDGE_HIGH [23:23]
/// No description
GPIO_QSPI_SD3_EDGE_HIGH: u1 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Interrupt Force for proc0
pub const PROC0_INTF = Register(PROC0_INTF_val).init(base_address + 0x38);
/// PROC0_INTE
const PROC0_INTE_val = packed struct {
/// GPIO_QSPI_SCLK_LEVEL_LOW [0:0]
/// No description
GPIO_QSPI_SCLK_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SCLK_LEVEL_HIGH [1:1]
/// No description
GPIO_QSPI_SCLK_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SCLK_EDGE_LOW [2:2]
/// No description
GPIO_QSPI_SCLK_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SCLK_EDGE_HIGH [3:3]
/// No description
GPIO_QSPI_SCLK_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SS_LEVEL_LOW [4:4]
/// No description
GPIO_QSPI_SS_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SS_LEVEL_HIGH [5:5]
/// No description
GPIO_QSPI_SS_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SS_EDGE_LOW [6:6]
/// No description
GPIO_QSPI_SS_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SS_EDGE_HIGH [7:7]
/// No description
GPIO_QSPI_SS_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD0_LEVEL_LOW [8:8]
/// No description
GPIO_QSPI_SD0_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD0_LEVEL_HIGH [9:9]
/// No description
GPIO_QSPI_SD0_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD0_EDGE_LOW [10:10]
/// No description
GPIO_QSPI_SD0_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD0_EDGE_HIGH [11:11]
/// No description
GPIO_QSPI_SD0_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD1_LEVEL_LOW [12:12]
/// No description
GPIO_QSPI_SD1_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD1_LEVEL_HIGH [13:13]
/// No description
GPIO_QSPI_SD1_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD1_EDGE_LOW [14:14]
/// No description
GPIO_QSPI_SD1_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD1_EDGE_HIGH [15:15]
/// No description
GPIO_QSPI_SD1_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD2_LEVEL_LOW [16:16]
/// No description
GPIO_QSPI_SD2_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD2_LEVEL_HIGH [17:17]
/// No description
GPIO_QSPI_SD2_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD2_EDGE_LOW [18:18]
/// No description
GPIO_QSPI_SD2_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD2_EDGE_HIGH [19:19]
/// No description
GPIO_QSPI_SD2_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD3_LEVEL_LOW [20:20]
/// No description
GPIO_QSPI_SD3_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD3_LEVEL_HIGH [21:21]
/// No description
GPIO_QSPI_SD3_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD3_EDGE_LOW [22:22]
/// No description
GPIO_QSPI_SD3_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD3_EDGE_HIGH [23:23]
/// No description
GPIO_QSPI_SD3_EDGE_HIGH: u1 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Interrupt Enable for proc0
pub const PROC0_INTE = Register(PROC0_INTE_val).init(base_address + 0x34);
/// INTR
const INTR_val = packed struct {
/// GPIO_QSPI_SCLK_LEVEL_LOW [0:0]
/// No description
GPIO_QSPI_SCLK_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SCLK_LEVEL_HIGH [1:1]
/// No description
GPIO_QSPI_SCLK_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SCLK_EDGE_LOW [2:2]
/// No description
GPIO_QSPI_SCLK_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SCLK_EDGE_HIGH [3:3]
/// No description
GPIO_QSPI_SCLK_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SS_LEVEL_LOW [4:4]
/// No description
GPIO_QSPI_SS_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SS_LEVEL_HIGH [5:5]
/// No description
GPIO_QSPI_SS_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SS_EDGE_LOW [6:6]
/// No description
GPIO_QSPI_SS_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SS_EDGE_HIGH [7:7]
/// No description
GPIO_QSPI_SS_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD0_LEVEL_LOW [8:8]
/// No description
GPIO_QSPI_SD0_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD0_LEVEL_HIGH [9:9]
/// No description
GPIO_QSPI_SD0_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD0_EDGE_LOW [10:10]
/// No description
GPIO_QSPI_SD0_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD0_EDGE_HIGH [11:11]
/// No description
GPIO_QSPI_SD0_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD1_LEVEL_LOW [12:12]
/// No description
GPIO_QSPI_SD1_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD1_LEVEL_HIGH [13:13]
/// No description
GPIO_QSPI_SD1_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD1_EDGE_LOW [14:14]
/// No description
GPIO_QSPI_SD1_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD1_EDGE_HIGH [15:15]
/// No description
GPIO_QSPI_SD1_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD2_LEVEL_LOW [16:16]
/// No description
GPIO_QSPI_SD2_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD2_LEVEL_HIGH [17:17]
/// No description
GPIO_QSPI_SD2_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD2_EDGE_LOW [18:18]
/// No description
GPIO_QSPI_SD2_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD2_EDGE_HIGH [19:19]
/// No description
GPIO_QSPI_SD2_EDGE_HIGH: u1 = 0,
/// GPIO_QSPI_SD3_LEVEL_LOW [20:20]
/// No description
GPIO_QSPI_SD3_LEVEL_LOW: u1 = 0,
/// GPIO_QSPI_SD3_LEVEL_HIGH [21:21]
/// No description
GPIO_QSPI_SD3_LEVEL_HIGH: u1 = 0,
/// GPIO_QSPI_SD3_EDGE_LOW [22:22]
/// No description
GPIO_QSPI_SD3_EDGE_LOW: u1 = 0,
/// GPIO_QSPI_SD3_EDGE_HIGH [23:23]
/// No description
GPIO_QSPI_SD3_EDGE_HIGH: u1 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Raw Interrupts
pub const INTR = Register(INTR_val).init(base_address + 0x30);
/// GPIO_QSPI_SD3_CTRL
const GPIO_QSPI_SD3_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO_QSPI_SD3_CTRL = Register(GPIO_QSPI_SD3_CTRL_val).init(base_address + 0x2c);
/// GPIO_QSPI_SD3_STATUS
const GPIO_QSPI_SD3_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO_QSPI_SD3_STATUS = Register(GPIO_QSPI_SD3_STATUS_val).init(base_address + 0x28);
/// GPIO_QSPI_SD2_CTRL
const GPIO_QSPI_SD2_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO_QSPI_SD2_CTRL = Register(GPIO_QSPI_SD2_CTRL_val).init(base_address + 0x24);
/// GPIO_QSPI_SD2_STATUS
const GPIO_QSPI_SD2_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO_QSPI_SD2_STATUS = Register(GPIO_QSPI_SD2_STATUS_val).init(base_address + 0x20);
/// GPIO_QSPI_SD1_CTRL
const GPIO_QSPI_SD1_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO_QSPI_SD1_CTRL = Register(GPIO_QSPI_SD1_CTRL_val).init(base_address + 0x1c);
/// GPIO_QSPI_SD1_STATUS
const GPIO_QSPI_SD1_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO_QSPI_SD1_STATUS = Register(GPIO_QSPI_SD1_STATUS_val).init(base_address + 0x18);
/// GPIO_QSPI_SD0_CTRL
const GPIO_QSPI_SD0_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO_QSPI_SD0_CTRL = Register(GPIO_QSPI_SD0_CTRL_val).init(base_address + 0x14);
/// GPIO_QSPI_SD0_STATUS
const GPIO_QSPI_SD0_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO_QSPI_SD0_STATUS = Register(GPIO_QSPI_SD0_STATUS_val).init(base_address + 0x10);
/// GPIO_QSPI_SS_CTRL
const GPIO_QSPI_SS_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO_QSPI_SS_CTRL = Register(GPIO_QSPI_SS_CTRL_val).init(base_address + 0xc);
/// GPIO_QSPI_SS_STATUS
const GPIO_QSPI_SS_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO_QSPI_SS_STATUS = Register(GPIO_QSPI_SS_STATUS_val).init(base_address + 0x8);
/// GPIO_QSPI_SCLK_CTRL
const GPIO_QSPI_SCLK_CTRL_val = packed struct {
/// FUNCSEL [0:4]
/// 0-31 -> selects pin function according to the gpio table\n
FUNCSEL: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// OUTOVER [8:9]
/// No description
OUTOVER: u2 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEOVER [12:13]
/// No description
OEOVER: u2 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// INOVER [16:17]
/// No description
INOVER: u2 = 0,
/// unused [18:27]
_unused18: u6 = 0,
_unused24: u4 = 0,
/// IRQOVER [28:29]
/// No description
IRQOVER: u2 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO control including function select and overrides.
pub const GPIO_QSPI_SCLK_CTRL = Register(GPIO_QSPI_SCLK_CTRL_val).init(base_address + 0x4);
/// GPIO_QSPI_SCLK_STATUS
const GPIO_QSPI_SCLK_STATUS_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// OUTFROMPERI [8:8]
/// output signal from selected peripheral, before register override is applied
OUTFROMPERI: u1 = 0,
/// OUTTOPAD [9:9]
/// output signal to pad after register override is applied
OUTTOPAD: u1 = 0,
/// unused [10:11]
_unused10: u2 = 0,
/// OEFROMPERI [12:12]
/// output enable from selected peripheral, before register override is applied
OEFROMPERI: u1 = 0,
/// OETOPAD [13:13]
/// output enable to pad after register override is applied
OETOPAD: u1 = 0,
/// unused [14:16]
_unused14: u2 = 0,
_unused16: u1 = 0,
/// INFROMPAD [17:17]
/// input signal from pad, before override is applied
INFROMPAD: u1 = 0,
/// unused [18:18]
_unused18: u1 = 0,
/// INTOPERI [19:19]
/// input signal to peripheral, after override is applied
INTOPERI: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// IRQFROMPAD [24:24]
/// interrupt from pad before override is applied
IRQFROMPAD: u1 = 0,
/// unused [25:25]
_unused25: u1 = 0,
/// IRQTOPROC [26:26]
/// interrupt to processors, after override is applied
IRQTOPROC: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// GPIO status
pub const GPIO_QSPI_SCLK_STATUS = Register(GPIO_QSPI_SCLK_STATUS_val).init(base_address + 0x0);
};
/// No description
pub const PADS_BANK0 = struct {
const base_address = 0x4001c000;
/// SWD
const SWD_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 0,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 1,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const SWD = Register(SWD_val).init(base_address + 0x80);
/// SWCLK
const SWCLK_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 0,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 1,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 1,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const SWCLK = Register(SWCLK_val).init(base_address + 0x7c);
/// GPIO29
const GPIO29_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 1,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 0,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO29 = Register(GPIO29_val).init(base_address + 0x78);
/// GPIO28
const GPIO28_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 1,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 0,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO28 = Register(GPIO28_val).init(base_address + 0x74);
/// GPIO27
const GPIO27_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 1,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 0,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO27 = Register(GPIO27_val).init(base_address + 0x70);
/// GPIO26
const GPIO26_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 1,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 0,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO26 = Register(GPIO26_val).init(base_address + 0x6c);
/// GPIO25
const GPIO25_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 1,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 0,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO25 = Register(GPIO25_val).init(base_address + 0x68);
/// GPIO24
const GPIO24_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 1,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 0,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO24 = Register(GPIO24_val).init(base_address + 0x64);
/// GPIO23
const GPIO23_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 1,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 0,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO23 = Register(GPIO23_val).init(base_address + 0x60);
/// GPIO22
const GPIO22_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 1,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 0,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO22 = Register(GPIO22_val).init(base_address + 0x5c);
/// GPIO21
const GPIO21_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 1,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 0,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO21 = Register(GPIO21_val).init(base_address + 0x58);
/// GPIO20
const GPIO20_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 1,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 0,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO20 = Register(GPIO20_val).init(base_address + 0x54);
/// GPIO19
const GPIO19_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 1,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 0,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO19 = Register(GPIO19_val).init(base_address + 0x50);
/// GPIO18
const GPIO18_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 1,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 0,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO18 = Register(GPIO18_val).init(base_address + 0x4c);
/// GPIO17
const GPIO17_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 1,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 0,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO17 = Register(GPIO17_val).init(base_address + 0x48);
/// GPIO16
const GPIO16_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 1,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 0,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO16 = Register(GPIO16_val).init(base_address + 0x44);
/// GPIO15
const GPIO15_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 1,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 0,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO15 = Register(GPIO15_val).init(base_address + 0x40);
/// GPIO14
const GPIO14_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 1,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 0,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO14 = Register(GPIO14_val).init(base_address + 0x3c);
/// GPIO13
const GPIO13_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 1,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 0,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO13 = Register(GPIO13_val).init(base_address + 0x38);
/// GPIO12
const GPIO12_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 1,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 0,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO12 = Register(GPIO12_val).init(base_address + 0x34);
/// GPIO11
const GPIO11_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 1,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 0,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO11 = Register(GPIO11_val).init(base_address + 0x30);
/// GPIO10
const GPIO10_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 1,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 0,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO10 = Register(GPIO10_val).init(base_address + 0x2c);
/// GPIO9
const GPIO9_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 1,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 0,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO9 = Register(GPIO9_val).init(base_address + 0x28);
/// GPIO8
const GPIO8_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 1,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 0,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO8 = Register(GPIO8_val).init(base_address + 0x24);
/// GPIO7
const GPIO7_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 1,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 0,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO7 = Register(GPIO7_val).init(base_address + 0x20);
/// GPIO6
const GPIO6_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 1,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 0,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO6 = Register(GPIO6_val).init(base_address + 0x1c);
/// GPIO5
const GPIO5_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 1,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 0,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO5 = Register(GPIO5_val).init(base_address + 0x18);
/// GPIO4
const GPIO4_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 1,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 0,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO4 = Register(GPIO4_val).init(base_address + 0x14);
/// GPIO3
const GPIO3_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 1,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 0,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO3 = Register(GPIO3_val).init(base_address + 0x10);
/// GPIO2
const GPIO2_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 1,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 0,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO2 = Register(GPIO2_val).init(base_address + 0xc);
/// GPIO1
const GPIO1_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 1,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 0,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO1 = Register(GPIO1_val).init(base_address + 0x8);
/// GPIO0
const GPIO0_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 1,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 0,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO0 = Register(GPIO0_val).init(base_address + 0x4);
/// VOLTAGE_SELECT
const VOLTAGE_SELECT_val = packed struct {
/// VOLTAGE_SELECT [0:0]
/// No description
VOLTAGE_SELECT: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Voltage select. Per bank control
pub const VOLTAGE_SELECT = Register(VOLTAGE_SELECT_val).init(base_address + 0x0);
};
/// No description
pub const PADS_QSPI = struct {
const base_address = 0x40020000;
/// GPIO_QSPI_SS
const GPIO_QSPI_SS_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 0,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 1,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO_QSPI_SS = Register(GPIO_QSPI_SS_val).init(base_address + 0x18);
/// GPIO_QSPI_SD3
const GPIO_QSPI_SD3_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 0,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 0,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO_QSPI_SD3 = Register(GPIO_QSPI_SD3_val).init(base_address + 0x14);
/// GPIO_QSPI_SD2
const GPIO_QSPI_SD2_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 0,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 0,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO_QSPI_SD2 = Register(GPIO_QSPI_SD2_val).init(base_address + 0x10);
/// GPIO_QSPI_SD1
const GPIO_QSPI_SD1_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 0,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 0,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO_QSPI_SD1 = Register(GPIO_QSPI_SD1_val).init(base_address + 0xc);
/// GPIO_QSPI_SD0
const GPIO_QSPI_SD0_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 0,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 0,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO_QSPI_SD0 = Register(GPIO_QSPI_SD0_val).init(base_address + 0x8);
/// GPIO_QSPI_SCLK
const GPIO_QSPI_SCLK_val = packed struct {
/// SLEWFAST [0:0]
/// Slew rate control. 1 = Fast, 0 = Slow
SLEWFAST: u1 = 0,
/// SCHMITT [1:1]
/// Enable schmitt trigger
SCHMITT: u1 = 1,
/// PDE [2:2]
/// Pull down enable
PDE: u1 = 1,
/// PUE [3:3]
/// Pull up enable
PUE: u1 = 0,
/// DRIVE [4:5]
/// Drive strength.
DRIVE: u2 = 1,
/// IE [6:6]
/// Input enable
IE: u1 = 1,
/// OD [7:7]
/// Output disable. Has priority over output enable from peripherals
OD: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Pad control register
pub const GPIO_QSPI_SCLK = Register(GPIO_QSPI_SCLK_val).init(base_address + 0x4);
/// VOLTAGE_SELECT
const VOLTAGE_SELECT_val = packed struct {
/// VOLTAGE_SELECT [0:0]
/// No description
VOLTAGE_SELECT: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Voltage select. Per bank control
pub const VOLTAGE_SELECT = Register(VOLTAGE_SELECT_val).init(base_address + 0x0);
};
/// Controls the crystal oscillator
pub const XOSC = struct {
const base_address = 0x40024000;
/// COUNT
const COUNT_val = packed struct {
/// COUNT [0:7]
/// No description
COUNT: u8 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// A down counter running at the xosc frequency which counts to zero and stops.\n
pub const COUNT = Register(COUNT_val).init(base_address + 0x1c);
/// STARTUP
const STARTUP_val = packed struct {
/// DELAY [0:13]
/// in multiples of 256*xtal_period
DELAY: u14 = 0,
/// unused [14:19]
_unused14: u2 = 0,
_unused16: u4 = 0,
/// X4 [20:20]
/// Multiplies the startup_delay by 4. This is of little value to the user given that the delay can be programmed directly
X4: u1 = 0,
/// unused [21:31]
_unused21: u3 = 0,
_unused24: u8 = 0,
};
/// Controls the startup delay
pub const STARTUP = Register(STARTUP_val).init(base_address + 0xc);
/// DORMANT
const DORMANT_val = packed struct {
DORMANT_0: u8 = 0,
DORMANT_1: u8 = 0,
DORMANT_2: u8 = 0,
DORMANT_3: u8 = 0,
};
/// Crystal Oscillator pause control\n
pub const DORMANT = Register(DORMANT_val).init(base_address + 0x8);
/// STATUS
const STATUS_val = packed struct {
/// FREQ_RANGE [0:1]
/// The current frequency range setting, always reads 0
FREQ_RANGE: u2 = 0,
/// unused [2:11]
_unused2: u6 = 0,
_unused8: u4 = 0,
/// ENABLED [12:12]
/// Oscillator is enabled but not necessarily running and stable, resets to 0
ENABLED: u1 = 0,
/// unused [13:23]
_unused13: u3 = 0,
_unused16: u8 = 0,
/// BADWRITE [24:24]
/// An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT
BADWRITE: u1 = 0,
/// unused [25:30]
_unused25: u6 = 0,
/// STABLE [31:31]
/// Oscillator is running and stable
STABLE: u1 = 0,
};
/// Crystal Oscillator Status
pub const STATUS = Register(STATUS_val).init(base_address + 0x4);
/// CTRL
const CTRL_val = packed struct {
/// FREQ_RANGE [0:11]
/// Frequency range. This resets to 0xAA0 and cannot be changed.
FREQ_RANGE: u12 = 0,
/// ENABLE [12:23]
/// On power-up this field is initialised to DISABLE and the chip runs from the ROSC.\n
ENABLE: u12 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Crystal Oscillator Control
pub const CTRL = Register(CTRL_val).init(base_address + 0x0);
};
/// No description
pub const PLL_SYS = struct {
const base_address = 0x40028000;
/// PRIM
const PRIM_val = packed struct {
/// unused [0:11]
_unused0: u8 = 0,
_unused8: u4 = 0,
/// POSTDIV2 [12:14]
/// divide by 1-7
POSTDIV2: u3 = 7,
/// unused [15:15]
_unused15: u1 = 0,
/// POSTDIV1 [16:18]
/// divide by 1-7
POSTDIV1: u3 = 7,
/// unused [19:31]
_unused19: u5 = 0,
_unused24: u8 = 0,
};
/// Controls the PLL post dividers for the primary output\n
pub const PRIM = Register(PRIM_val).init(base_address + 0xc);
/// FBDIV_INT
const FBDIV_INT_val = packed struct {
/// FBDIV_INT [0:11]
/// see ctrl reg description for constraints
FBDIV_INT: u12 = 0,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Feedback divisor\n
pub const FBDIV_INT = Register(FBDIV_INT_val).init(base_address + 0x8);
/// PWR
const PWR_val = packed struct {
/// PD [0:0]
/// PLL powerdown\n
PD: u1 = 1,
/// unused [1:1]
_unused1: u1 = 0,
/// DSMPD [2:2]
/// PLL DSM powerdown\n
DSMPD: u1 = 1,
/// POSTDIVPD [3:3]
/// PLL post divider powerdown\n
POSTDIVPD: u1 = 1,
/// unused [4:4]
_unused4: u1 = 0,
/// VCOPD [5:5]
/// PLL VCO powerdown\n
VCOPD: u1 = 1,
/// unused [6:31]
_unused6: u2 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Controls the PLL power modes.
pub const PWR = Register(PWR_val).init(base_address + 0x4);
/// CS
const CS_val = packed struct {
/// REFDIV [0:5]
/// Divides the PLL input reference clock.\n
REFDIV: u6 = 1,
/// unused [6:7]
_unused6: u2 = 0,
/// BYPASS [8:8]
/// Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so.
BYPASS: u1 = 0,
/// unused [9:30]
_unused9: u7 = 0,
_unused16: u8 = 0,
_unused24: u7 = 0,
/// LOCK [31:31]
/// PLL is locked
LOCK: u1 = 0,
};
/// Control and Status\n
pub const CS = Register(CS_val).init(base_address + 0x0);
};
/// No description
pub const PLL_USB = struct {
const base_address = 0x4002c000;
/// PRIM
const PRIM_val = packed struct {
/// unused [0:11]
_unused0: u8 = 0,
_unused8: u4 = 0,
/// POSTDIV2 [12:14]
/// divide by 1-7
POSTDIV2: u3 = 7,
/// unused [15:15]
_unused15: u1 = 0,
/// POSTDIV1 [16:18]
/// divide by 1-7
POSTDIV1: u3 = 7,
/// unused [19:31]
_unused19: u5 = 0,
_unused24: u8 = 0,
};
/// Controls the PLL post dividers for the primary output\n
pub const PRIM = Register(PRIM_val).init(base_address + 0xc);
/// FBDIV_INT
const FBDIV_INT_val = packed struct {
/// FBDIV_INT [0:11]
/// see ctrl reg description for constraints
FBDIV_INT: u12 = 0,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Feedback divisor\n
pub const FBDIV_INT = Register(FBDIV_INT_val).init(base_address + 0x8);
/// PWR
const PWR_val = packed struct {
/// PD [0:0]
/// PLL powerdown\n
PD: u1 = 1,
/// unused [1:1]
_unused1: u1 = 0,
/// DSMPD [2:2]
/// PLL DSM powerdown\n
DSMPD: u1 = 1,
/// POSTDIVPD [3:3]
/// PLL post divider powerdown\n
POSTDIVPD: u1 = 1,
/// unused [4:4]
_unused4: u1 = 0,
/// VCOPD [5:5]
/// PLL VCO powerdown\n
VCOPD: u1 = 1,
/// unused [6:31]
_unused6: u2 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Controls the PLL power modes.
pub const PWR = Register(PWR_val).init(base_address + 0x4);
/// CS
const CS_val = packed struct {
/// REFDIV [0:5]
/// Divides the PLL input reference clock.\n
REFDIV: u6 = 1,
/// unused [6:7]
_unused6: u2 = 0,
/// BYPASS [8:8]
/// Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so.
BYPASS: u1 = 0,
/// unused [9:30]
_unused9: u7 = 0,
_unused16: u8 = 0,
_unused24: u7 = 0,
/// LOCK [31:31]
/// PLL is locked
LOCK: u1 = 0,
};
/// Control and Status\n
pub const CS = Register(CS_val).init(base_address + 0x0);
};
/// Register block for busfabric control signals and performance counters
pub const BUSCTRL = struct {
const base_address = 0x40030000;
/// PERFSEL3
const PERFSEL3_val = packed struct {
/// PERFSEL3 [0:4]
/// Select an event for PERFCTR3. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.
PERFSEL3: u5 = 31,
/// unused [5:31]
_unused5: u3 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Bus fabric performance event select for PERFCTR3
pub const PERFSEL3 = Register(PERFSEL3_val).init(base_address + 0x24);
/// PERFCTR3
const PERFCTR3_val = packed struct {
/// PERFCTR3 [0:23]
/// Busfabric saturating performance counter 3\n
PERFCTR3: u24 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Bus fabric performance counter 3
pub const PERFCTR3 = Register(PERFCTR3_val).init(base_address + 0x20);
/// PERFSEL2
const PERFSEL2_val = packed struct {
/// PERFSEL2 [0:4]
/// Select an event for PERFCTR2. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.
PERFSEL2: u5 = 31,
/// unused [5:31]
_unused5: u3 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Bus fabric performance event select for PERFCTR2
pub const PERFSEL2 = Register(PERFSEL2_val).init(base_address + 0x1c);
/// PERFCTR2
const PERFCTR2_val = packed struct {
/// PERFCTR2 [0:23]
/// Busfabric saturating performance counter 2\n
PERFCTR2: u24 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Bus fabric performance counter 2
pub const PERFCTR2 = Register(PERFCTR2_val).init(base_address + 0x18);
/// PERFSEL1
const PERFSEL1_val = packed struct {
/// PERFSEL1 [0:4]
/// Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.
PERFSEL1: u5 = 31,
/// unused [5:31]
_unused5: u3 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Bus fabric performance event select for PERFCTR1
pub const PERFSEL1 = Register(PERFSEL1_val).init(base_address + 0x14);
/// PERFCTR1
const PERFCTR1_val = packed struct {
/// PERFCTR1 [0:23]
/// Busfabric saturating performance counter 1\n
PERFCTR1: u24 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Bus fabric performance counter 1
pub const PERFCTR1 = Register(PERFCTR1_val).init(base_address + 0x10);
/// PERFSEL0
const PERFSEL0_val = packed struct {
/// PERFSEL0 [0:4]
/// Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.
PERFSEL0: u5 = 31,
/// unused [5:31]
_unused5: u3 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Bus fabric performance event select for PERFCTR0
pub const PERFSEL0 = Register(PERFSEL0_val).init(base_address + 0xc);
/// PERFCTR0
const PERFCTR0_val = packed struct {
/// PERFCTR0 [0:23]
/// Busfabric saturating performance counter 0\n
PERFCTR0: u24 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Bus fabric performance counter 0
pub const PERFCTR0 = Register(PERFCTR0_val).init(base_address + 0x8);
/// BUS_PRIORITY_ACK
const BUS_PRIORITY_ACK_val = packed struct {
/// BUS_PRIORITY_ACK [0:0]
/// Goes to 1 once all arbiters have registered the new global priority levels.\n
BUS_PRIORITY_ACK: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Bus priority acknowledge
pub const BUS_PRIORITY_ACK = Register(BUS_PRIORITY_ACK_val).init(base_address + 0x4);
/// BUS_PRIORITY
const BUS_PRIORITY_val = packed struct {
/// PROC0 [0:0]
/// 0 - low priority, 1 - high priority
PROC0: u1 = 0,
/// unused [1:3]
_unused1: u3 = 0,
/// PROC1 [4:4]
/// 0 - low priority, 1 - high priority
PROC1: u1 = 0,
/// unused [5:7]
_unused5: u3 = 0,
/// DMA_R [8:8]
/// 0 - low priority, 1 - high priority
DMA_R: u1 = 0,
/// unused [9:11]
_unused9: u3 = 0,
/// DMA_W [12:12]
/// 0 - low priority, 1 - high priority
DMA_W: u1 = 0,
/// unused [13:31]
_unused13: u3 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Set the priority of each master for bus arbitration.
pub const BUS_PRIORITY = Register(BUS_PRIORITY_val).init(base_address + 0x0);
};
/// No description
pub const UART0 = struct {
const base_address = 0x40034000;
/// UARTPCELLID3
const UARTPCELLID3_val = packed struct {
/// UARTPCELLID3 [0:7]
/// These bits read back as 0xB1
UARTPCELLID3: u8 = 177,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// UARTPCellID3 Register
pub const UARTPCELLID3 = Register(UARTPCELLID3_val).init(base_address + 0xffc);
/// UARTPCELLID2
const UARTPCELLID2_val = packed struct {
/// UARTPCELLID2 [0:7]
/// These bits read back as 0x05
UARTPCELLID2: u8 = 5,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// UARTPCellID2 Register
pub const UARTPCELLID2 = Register(UARTPCELLID2_val).init(base_address + 0xff8);
/// UARTPCELLID1
const UARTPCELLID1_val = packed struct {
/// UARTPCELLID1 [0:7]
/// These bits read back as 0xF0
UARTPCELLID1: u8 = 240,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// UARTPCellID1 Register
pub const UARTPCELLID1 = Register(UARTPCELLID1_val).init(base_address + 0xff4);
/// UARTPCELLID0
const UARTPCELLID0_val = packed struct {
/// UARTPCELLID0 [0:7]
/// These bits read back as 0x0D
UARTPCELLID0: u8 = 13,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// UARTPCellID0 Register
pub const UARTPCELLID0 = Register(UARTPCELLID0_val).init(base_address + 0xff0);
/// UARTPERIPHID3
const UARTPERIPHID3_val = packed struct {
/// CONFIGURATION [0:7]
/// These bits read back as 0x00
CONFIGURATION: u8 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// UARTPeriphID3 Register
pub const UARTPERIPHID3 = Register(UARTPERIPHID3_val).init(base_address + 0xfec);
/// UARTPERIPHID2
const UARTPERIPHID2_val = packed struct {
/// DESIGNER1 [0:3]
/// These bits read back as 0x4
DESIGNER1: u4 = 4,
/// REVISION [4:7]
/// This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3
REVISION: u4 = 3,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// UARTPeriphID2 Register
pub const UARTPERIPHID2 = Register(UARTPERIPHID2_val).init(base_address + 0xfe8);
/// UARTPERIPHID1
const UARTPERIPHID1_val = packed struct {
/// PARTNUMBER1 [0:3]
/// These bits read back as 0x0
PARTNUMBER1: u4 = 0,
/// DESIGNER0 [4:7]
/// These bits read back as 0x1
DESIGNER0: u4 = 1,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// UARTPeriphID1 Register
pub const UARTPERIPHID1 = Register(UARTPERIPHID1_val).init(base_address + 0xfe4);
/// UARTPERIPHID0
const UARTPERIPHID0_val = packed struct {
/// PARTNUMBER0 [0:7]
/// These bits read back as 0x11
PARTNUMBER0: u8 = 17,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// UARTPeriphID0 Register
pub const UARTPERIPHID0 = Register(UARTPERIPHID0_val).init(base_address + 0xfe0);
/// UARTDMACR
const UARTDMACR_val = packed struct {
/// RXDMAE [0:0]
/// Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled.
RXDMAE: u1 = 0,
/// TXDMAE [1:1]
/// Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.
TXDMAE: u1 = 0,
/// DMAONERR [2:2]
/// DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted.
DMAONERR: u1 = 0,
/// unused [3:31]
_unused3: u5 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// DMA Control Register, UARTDMACR
pub const UARTDMACR = Register(UARTDMACR_val).init(base_address + 0x48);
/// UARTICR
const UARTICR_val = packed struct {
/// RIMIC [0:0]
/// nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt.
RIMIC: u1 = 0,
/// CTSMIC [1:1]
/// nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt.
CTSMIC: u1 = 0,
/// DCDMIC [2:2]
/// nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt.
DCDMIC: u1 = 0,
/// DSRMIC [3:3]
/// nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt.
DSRMIC: u1 = 0,
/// RXIC [4:4]
/// Receive interrupt clear. Clears the UARTRXINTR interrupt.
RXIC: u1 = 0,
/// TXIC [5:5]
/// Transmit interrupt clear. Clears the UARTTXINTR interrupt.
TXIC: u1 = 0,
/// RTIC [6:6]
/// Receive timeout interrupt clear. Clears the UARTRTINTR interrupt.
RTIC: u1 = 0,
/// FEIC [7:7]
/// Framing error interrupt clear. Clears the UARTFEINTR interrupt.
FEIC: u1 = 0,
/// PEIC [8:8]
/// Parity error interrupt clear. Clears the UARTPEINTR interrupt.
PEIC: u1 = 0,
/// BEIC [9:9]
/// Break error interrupt clear. Clears the UARTBEINTR interrupt.
BEIC: u1 = 0,
/// OEIC [10:10]
/// Overrun error interrupt clear. Clears the UARTOEINTR interrupt.
OEIC: u1 = 0,
/// unused [11:31]
_unused11: u5 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt Clear Register, UARTICR
pub const UARTICR = Register(UARTICR_val).init(base_address + 0x44);
/// UARTMIS
const UARTMIS_val = packed struct {
/// RIMMIS [0:0]
/// nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt.
RIMMIS: u1 = 0,
/// CTSMMIS [1:1]
/// nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt.
CTSMMIS: u1 = 0,
/// DCDMMIS [2:2]
/// nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt.
DCDMMIS: u1 = 0,
/// DSRMMIS [3:3]
/// nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt.
DSRMMIS: u1 = 0,
/// RXMIS [4:4]
/// Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt.
RXMIS: u1 = 0,
/// TXMIS [5:5]
/// Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt.
TXMIS: u1 = 0,
/// RTMIS [6:6]
/// Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt.
RTMIS: u1 = 0,
/// FEMIS [7:7]
/// Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt.
FEMIS: u1 = 0,
/// PEMIS [8:8]
/// Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt.
PEMIS: u1 = 0,
/// BEMIS [9:9]
/// Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt.
BEMIS: u1 = 0,
/// OEMIS [10:10]
/// Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt.
OEMIS: u1 = 0,
/// unused [11:31]
_unused11: u5 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Masked Interrupt Status Register, UARTMIS
pub const UARTMIS = Register(UARTMIS_val).init(base_address + 0x40);
/// UARTRIS
const UARTRIS_val = packed struct {
/// RIRMIS [0:0]
/// nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt.
RIRMIS: u1 = 0,
/// CTSRMIS [1:1]
/// nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt.
CTSRMIS: u1 = 0,
/// DCDRMIS [2:2]
/// nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt.
DCDRMIS: u1 = 0,
/// DSRRMIS [3:3]
/// nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt.
DSRRMIS: u1 = 0,
/// RXRIS [4:4]
/// Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt.
RXRIS: u1 = 0,
/// TXRIS [5:5]
/// Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt.
TXRIS: u1 = 0,
/// RTRIS [6:6]
/// Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a
RTRIS: u1 = 0,
/// FERIS [7:7]
/// Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt.
FERIS: u1 = 0,
/// PERIS [8:8]
/// Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt.
PERIS: u1 = 0,
/// BERIS [9:9]
/// Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt.
BERIS: u1 = 0,
/// OERIS [10:10]
/// Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt.
OERIS: u1 = 0,
/// unused [11:31]
_unused11: u5 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Raw Interrupt Status Register, UARTRIS
pub const UARTRIS = Register(UARTRIS_val).init(base_address + 0x3c);
/// UARTIMSC
const UARTIMSC_val = packed struct {
/// RIMIM [0:0]
/// nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask.
RIMIM: u1 = 0,
/// CTSMIM [1:1]
/// nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask.
CTSMIM: u1 = 0,
/// DCDMIM [2:2]
/// nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask.
DCDMIM: u1 = 0,
/// DSRMIM [3:3]
/// nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask.
DSRMIM: u1 = 0,
/// RXIM [4:4]
/// Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask.
RXIM: u1 = 0,
/// TXIM [5:5]
/// Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask.
TXIM: u1 = 0,
/// RTIM [6:6]
/// Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask.
RTIM: u1 = 0,
/// FEIM [7:7]
/// Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask.
FEIM: u1 = 0,
/// PEIM [8:8]
/// Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask.
PEIM: u1 = 0,
/// BEIM [9:9]
/// Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask.
BEIM: u1 = 0,
/// OEIM [10:10]
/// Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask.
OEIM: u1 = 0,
/// unused [11:31]
_unused11: u5 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt Mask Set/Clear Register, UARTIMSC
pub const UARTIMSC = Register(UARTIMSC_val).init(base_address + 0x38);
/// UARTIFLS
const UARTIFLS_val = packed struct {
/// TXIFLSEL [0:2]
/// Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved.
TXIFLSEL: u3 = 2,
/// RXIFLSEL [3:5]
/// Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved.
RXIFLSEL: u3 = 2,
/// unused [6:31]
_unused6: u2 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt FIFO Level Select Register, UARTIFLS
pub const UARTIFLS = Register(UARTIFLS_val).init(base_address + 0x34);
/// UARTCR
const UARTCR_val = packed struct {
/// UARTEN [0:0]
/// UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit.
UARTEN: u1 = 0,
/// SIREN [1:1]
/// SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART.
SIREN: u1 = 0,
/// SIRLP [2:2]
/// SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances.
SIRLP: u1 = 0,
/// unused [3:6]
_unused3: u4 = 0,
/// LBE [7:7]
/// Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback.
LBE: u1 = 0,
/// TXE [8:8]
/// Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping.
TXE: u1 = 1,
/// RXE [9:9]
/// Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping.
RXE: u1 = 1,
/// DTR [10:10]
/// Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW.
DTR: u1 = 0,
/// RTS [11:11]
/// Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW.
RTS: u1 = 0,
/// OUT1 [12:12]
/// This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD).
OUT1: u1 = 0,
/// OUT2 [13:13]
/// This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI).
OUT2: u1 = 0,
/// RTSEN [14:14]
/// RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received.
RTSEN: u1 = 0,
/// CTSEN [15:15]
/// CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted.
CTSEN: u1 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Control Register, UARTCR
pub const UARTCR = Register(UARTCR_val).init(base_address + 0x30);
/// UARTLCR_H
const UARTLCR_H_val = packed struct {
/// BRK [0:0]
/// Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0.
BRK: u1 = 0,
/// PEN [1:1]
/// Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled.
PEN: u1 = 0,
/// EPS [2:2]
/// Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation.
EPS: u1 = 0,
/// STP2 [3:3]
/// Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received.
STP2: u1 = 0,
/// FEN [4:4]
/// Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode).
FEN: u1 = 0,
/// WLEN [5:6]
/// Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits.
WLEN: u2 = 0,
/// SPS [7:7]
/// Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation.
SPS: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Line Control Register, UARTLCR_H
pub const UARTLCR_H = Register(UARTLCR_H_val).init(base_address + 0x2c);
/// UARTFBRD
const UARTFBRD_val = packed struct {
/// BAUD_DIVFRAC [0:5]
/// The fractional baud rate divisor. These bits are cleared to 0 on reset.
BAUD_DIVFRAC: u6 = 0,
/// unused [6:31]
_unused6: u2 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Fractional Baud Rate Register, UARTFBRD
pub const UARTFBRD = Register(UARTFBRD_val).init(base_address + 0x28);
/// UARTIBRD
const UARTIBRD_val = packed struct {
/// BAUD_DIVINT [0:15]
/// The integer baud rate divisor. These bits are cleared to 0 on reset.
BAUD_DIVINT: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Integer Baud Rate Register, UARTIBRD
pub const UARTIBRD = Register(UARTIBRD_val).init(base_address + 0x24);
/// UARTILPR
const UARTILPR_val = packed struct {
/// ILPDVSR [0:7]
/// 8-bit low-power divisor value. These bits are cleared to 0 at reset.
ILPDVSR: u8 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// IrDA Low-Power Counter Register, UARTILPR
pub const UARTILPR = Register(UARTILPR_val).init(base_address + 0x20);
/// UARTFR
const UARTFR_val = packed struct {
/// CTS [0:0]
/// Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW.
CTS: u1 = 0,
/// DSR [1:1]
/// Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW.
DSR: u1 = 0,
/// DCD [2:2]
/// Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW.
DCD: u1 = 0,
/// BUSY [3:3]
/// UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not.
BUSY: u1 = 0,
/// RXFE [4:4]
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
RXFE: u1 = 1,
/// TXFF [5:5]
/// Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
TXFF: u1 = 0,
/// RXFF [6:6]
/// Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full.
RXFF: u1 = 0,
/// TXFE [7:7]
/// Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register.
TXFE: u1 = 1,
/// RI [8:8]
/// Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW.
RI: u1 = 0,
/// unused [9:31]
_unused9: u7 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Flag Register, UARTFR
pub const UARTFR = Register(UARTFR_val).init(base_address + 0x18);
/// UARTRSR
const UARTRSR_val = packed struct {
/// FE [0:0]
/// Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.
FE: u1 = 0,
/// PE [1:1]
/// Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.
PE: u1 = 0,
/// BE [2:2]
/// Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received.
BE: u1 = 0,
/// OE [3:3]
/// Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO.
OE: u1 = 0,
/// unused [4:31]
_unused4: u4 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Receive Status Register/Error Clear Register, UARTRSR/UARTECR
pub const UARTRSR = Register(UARTRSR_val).init(base_address + 0x4);
/// UARTDR
const UARTDR_val = packed struct {
/// DATA [0:7]
/// Receive (read) data character. Transmit (write) data character.
DATA: u8 = 0,
/// FE [8:8]
/// Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO.
FE: u1 = 0,
/// PE [9:9]
/// Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO.
PE: u1 = 0,
/// BE [10:10]
/// Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received.
BE: u1 = 0,
/// OE [11:11]
/// Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it.
OE: u1 = 0,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Data Register, UARTDR
pub const UARTDR = Register(UARTDR_val).init(base_address + 0x0);
};
/// No description
pub const UART1 = struct {
const base_address = 0x40038000;
/// UARTPCELLID3
const UARTPCELLID3_val = packed struct {
/// UARTPCELLID3 [0:7]
/// These bits read back as 0xB1
UARTPCELLID3: u8 = 177,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// UARTPCellID3 Register
pub const UARTPCELLID3 = Register(UARTPCELLID3_val).init(base_address + 0xffc);
/// UARTPCELLID2
const UARTPCELLID2_val = packed struct {
/// UARTPCELLID2 [0:7]
/// These bits read back as 0x05
UARTPCELLID2: u8 = 5,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// UARTPCellID2 Register
pub const UARTPCELLID2 = Register(UARTPCELLID2_val).init(base_address + 0xff8);
/// UARTPCELLID1
const UARTPCELLID1_val = packed struct {
/// UARTPCELLID1 [0:7]
/// These bits read back as 0xF0
UARTPCELLID1: u8 = 240,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// UARTPCellID1 Register
pub const UARTPCELLID1 = Register(UARTPCELLID1_val).init(base_address + 0xff4);
/// UARTPCELLID0
const UARTPCELLID0_val = packed struct {
/// UARTPCELLID0 [0:7]
/// These bits read back as 0x0D
UARTPCELLID0: u8 = 13,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// UARTPCellID0 Register
pub const UARTPCELLID0 = Register(UARTPCELLID0_val).init(base_address + 0xff0);
/// UARTPERIPHID3
const UARTPERIPHID3_val = packed struct {
/// CONFIGURATION [0:7]
/// These bits read back as 0x00
CONFIGURATION: u8 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// UARTPeriphID3 Register
pub const UARTPERIPHID3 = Register(UARTPERIPHID3_val).init(base_address + 0xfec);
/// UARTPERIPHID2
const UARTPERIPHID2_val = packed struct {
/// DESIGNER1 [0:3]
/// These bits read back as 0x4
DESIGNER1: u4 = 4,
/// REVISION [4:7]
/// This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3
REVISION: u4 = 3,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// UARTPeriphID2 Register
pub const UARTPERIPHID2 = Register(UARTPERIPHID2_val).init(base_address + 0xfe8);
/// UARTPERIPHID1
const UARTPERIPHID1_val = packed struct {
/// PARTNUMBER1 [0:3]
/// These bits read back as 0x0
PARTNUMBER1: u4 = 0,
/// DESIGNER0 [4:7]
/// These bits read back as 0x1
DESIGNER0: u4 = 1,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// UARTPeriphID1 Register
pub const UARTPERIPHID1 = Register(UARTPERIPHID1_val).init(base_address + 0xfe4);
/// UARTPERIPHID0
const UARTPERIPHID0_val = packed struct {
/// PARTNUMBER0 [0:7]
/// These bits read back as 0x11
PARTNUMBER0: u8 = 17,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// UARTPeriphID0 Register
pub const UARTPERIPHID0 = Register(UARTPERIPHID0_val).init(base_address + 0xfe0);
/// UARTDMACR
const UARTDMACR_val = packed struct {
/// RXDMAE [0:0]
/// Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled.
RXDMAE: u1 = 0,
/// TXDMAE [1:1]
/// Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.
TXDMAE: u1 = 0,
/// DMAONERR [2:2]
/// DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted.
DMAONERR: u1 = 0,
/// unused [3:31]
_unused3: u5 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// DMA Control Register, UARTDMACR
pub const UARTDMACR = Register(UARTDMACR_val).init(base_address + 0x48);
/// UARTICR
const UARTICR_val = packed struct {
/// RIMIC [0:0]
/// nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt.
RIMIC: u1 = 0,
/// CTSMIC [1:1]
/// nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt.
CTSMIC: u1 = 0,
/// DCDMIC [2:2]
/// nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt.
DCDMIC: u1 = 0,
/// DSRMIC [3:3]
/// nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt.
DSRMIC: u1 = 0,
/// RXIC [4:4]
/// Receive interrupt clear. Clears the UARTRXINTR interrupt.
RXIC: u1 = 0,
/// TXIC [5:5]
/// Transmit interrupt clear. Clears the UARTTXINTR interrupt.
TXIC: u1 = 0,
/// RTIC [6:6]
/// Receive timeout interrupt clear. Clears the UARTRTINTR interrupt.
RTIC: u1 = 0,
/// FEIC [7:7]
/// Framing error interrupt clear. Clears the UARTFEINTR interrupt.
FEIC: u1 = 0,
/// PEIC [8:8]
/// Parity error interrupt clear. Clears the UARTPEINTR interrupt.
PEIC: u1 = 0,
/// BEIC [9:9]
/// Break error interrupt clear. Clears the UARTBEINTR interrupt.
BEIC: u1 = 0,
/// OEIC [10:10]
/// Overrun error interrupt clear. Clears the UARTOEINTR interrupt.
OEIC: u1 = 0,
/// unused [11:31]
_unused11: u5 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt Clear Register, UARTICR
pub const UARTICR = Register(UARTICR_val).init(base_address + 0x44);
/// UARTMIS
const UARTMIS_val = packed struct {
/// RIMMIS [0:0]
/// nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt.
RIMMIS: u1 = 0,
/// CTSMMIS [1:1]
/// nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt.
CTSMMIS: u1 = 0,
/// DCDMMIS [2:2]
/// nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt.
DCDMMIS: u1 = 0,
/// DSRMMIS [3:3]
/// nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt.
DSRMMIS: u1 = 0,
/// RXMIS [4:4]
/// Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt.
RXMIS: u1 = 0,
/// TXMIS [5:5]
/// Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt.
TXMIS: u1 = 0,
/// RTMIS [6:6]
/// Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt.
RTMIS: u1 = 0,
/// FEMIS [7:7]
/// Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt.
FEMIS: u1 = 0,
/// PEMIS [8:8]
/// Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt.
PEMIS: u1 = 0,
/// BEMIS [9:9]
/// Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt.
BEMIS: u1 = 0,
/// OEMIS [10:10]
/// Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt.
OEMIS: u1 = 0,
/// unused [11:31]
_unused11: u5 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Masked Interrupt Status Register, UARTMIS
pub const UARTMIS = Register(UARTMIS_val).init(base_address + 0x40);
/// UARTRIS
const UARTRIS_val = packed struct {
/// RIRMIS [0:0]
/// nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt.
RIRMIS: u1 = 0,
/// CTSRMIS [1:1]
/// nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt.
CTSRMIS: u1 = 0,
/// DCDRMIS [2:2]
/// nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt.
DCDRMIS: u1 = 0,
/// DSRRMIS [3:3]
/// nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt.
DSRRMIS: u1 = 0,
/// RXRIS [4:4]
/// Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt.
RXRIS: u1 = 0,
/// TXRIS [5:5]
/// Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt.
TXRIS: u1 = 0,
/// RTRIS [6:6]
/// Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a
RTRIS: u1 = 0,
/// FERIS [7:7]
/// Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt.
FERIS: u1 = 0,
/// PERIS [8:8]
/// Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt.
PERIS: u1 = 0,
/// BERIS [9:9]
/// Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt.
BERIS: u1 = 0,
/// OERIS [10:10]
/// Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt.
OERIS: u1 = 0,
/// unused [11:31]
_unused11: u5 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Raw Interrupt Status Register, UARTRIS
pub const UARTRIS = Register(UARTRIS_val).init(base_address + 0x3c);
/// UARTIMSC
const UARTIMSC_val = packed struct {
/// RIMIM [0:0]
/// nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask.
RIMIM: u1 = 0,
/// CTSMIM [1:1]
/// nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask.
CTSMIM: u1 = 0,
/// DCDMIM [2:2]
/// nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask.
DCDMIM: u1 = 0,
/// DSRMIM [3:3]
/// nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask.
DSRMIM: u1 = 0,
/// RXIM [4:4]
/// Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask.
RXIM: u1 = 0,
/// TXIM [5:5]
/// Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask.
TXIM: u1 = 0,
/// RTIM [6:6]
/// Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask.
RTIM: u1 = 0,
/// FEIM [7:7]
/// Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask.
FEIM: u1 = 0,
/// PEIM [8:8]
/// Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask.
PEIM: u1 = 0,
/// BEIM [9:9]
/// Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask.
BEIM: u1 = 0,
/// OEIM [10:10]
/// Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask.
OEIM: u1 = 0,
/// unused [11:31]
_unused11: u5 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt Mask Set/Clear Register, UARTIMSC
pub const UARTIMSC = Register(UARTIMSC_val).init(base_address + 0x38);
/// UARTIFLS
const UARTIFLS_val = packed struct {
/// TXIFLSEL [0:2]
/// Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved.
TXIFLSEL: u3 = 2,
/// RXIFLSEL [3:5]
/// Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved.
RXIFLSEL: u3 = 2,
/// unused [6:31]
_unused6: u2 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt FIFO Level Select Register, UARTIFLS
pub const UARTIFLS = Register(UARTIFLS_val).init(base_address + 0x34);
/// UARTCR
const UARTCR_val = packed struct {
/// UARTEN [0:0]
/// UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit.
UARTEN: u1 = 0,
/// SIREN [1:1]
/// SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART.
SIREN: u1 = 0,
/// SIRLP [2:2]
/// SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances.
SIRLP: u1 = 0,
/// unused [3:6]
_unused3: u4 = 0,
/// LBE [7:7]
/// Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback.
LBE: u1 = 0,
/// TXE [8:8]
/// Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping.
TXE: u1 = 1,
/// RXE [9:9]
/// Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping.
RXE: u1 = 1,
/// DTR [10:10]
/// Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW.
DTR: u1 = 0,
/// RTS [11:11]
/// Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW.
RTS: u1 = 0,
/// OUT1 [12:12]
/// This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD).
OUT1: u1 = 0,
/// OUT2 [13:13]
/// This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI).
OUT2: u1 = 0,
/// RTSEN [14:14]
/// RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received.
RTSEN: u1 = 0,
/// CTSEN [15:15]
/// CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted.
CTSEN: u1 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Control Register, UARTCR
pub const UARTCR = Register(UARTCR_val).init(base_address + 0x30);
/// UARTLCR_H
const UARTLCR_H_val = packed struct {
/// BRK [0:0]
/// Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0.
BRK: u1 = 0,
/// PEN [1:1]
/// Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled.
PEN: u1 = 0,
/// EPS [2:2]
/// Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation.
EPS: u1 = 0,
/// STP2 [3:3]
/// Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received.
STP2: u1 = 0,
/// FEN [4:4]
/// Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode).
FEN: u1 = 0,
/// WLEN [5:6]
/// Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits.
WLEN: u2 = 0,
/// SPS [7:7]
/// Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation.
SPS: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Line Control Register, UARTLCR_H
pub const UARTLCR_H = Register(UARTLCR_H_val).init(base_address + 0x2c);
/// UARTFBRD
const UARTFBRD_val = packed struct {
/// BAUD_DIVFRAC [0:5]
/// The fractional baud rate divisor. These bits are cleared to 0 on reset.
BAUD_DIVFRAC: u6 = 0,
/// unused [6:31]
_unused6: u2 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Fractional Baud Rate Register, UARTFBRD
pub const UARTFBRD = Register(UARTFBRD_val).init(base_address + 0x28);
/// UARTIBRD
const UARTIBRD_val = packed struct {
/// BAUD_DIVINT [0:15]
/// The integer baud rate divisor. These bits are cleared to 0 on reset.
BAUD_DIVINT: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Integer Baud Rate Register, UARTIBRD
pub const UARTIBRD = Register(UARTIBRD_val).init(base_address + 0x24);
/// UARTILPR
const UARTILPR_val = packed struct {
/// ILPDVSR [0:7]
/// 8-bit low-power divisor value. These bits are cleared to 0 at reset.
ILPDVSR: u8 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// IrDA Low-Power Counter Register, UARTILPR
pub const UARTILPR = Register(UARTILPR_val).init(base_address + 0x20);
/// UARTFR
const UARTFR_val = packed struct {
/// CTS [0:0]
/// Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW.
CTS: u1 = 0,
/// DSR [1:1]
/// Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW.
DSR: u1 = 0,
/// DCD [2:2]
/// Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW.
DCD: u1 = 0,
/// BUSY [3:3]
/// UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not.
BUSY: u1 = 0,
/// RXFE [4:4]
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
RXFE: u1 = 1,
/// TXFF [5:5]
/// Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
TXFF: u1 = 0,
/// RXFF [6:6]
/// Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full.
RXFF: u1 = 0,
/// TXFE [7:7]
/// Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register.
TXFE: u1 = 1,
/// RI [8:8]
/// Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW.
RI: u1 = 0,
/// unused [9:31]
_unused9: u7 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Flag Register, UARTFR
pub const UARTFR = Register(UARTFR_val).init(base_address + 0x18);
/// UARTRSR
const UARTRSR_val = packed struct {
/// FE [0:0]
/// Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.
FE: u1 = 0,
/// PE [1:1]
/// Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.
PE: u1 = 0,
/// BE [2:2]
/// Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received.
BE: u1 = 0,
/// OE [3:3]
/// Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO.
OE: u1 = 0,
/// unused [4:31]
_unused4: u4 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Receive Status Register/Error Clear Register, UARTRSR/UARTECR
pub const UARTRSR = Register(UARTRSR_val).init(base_address + 0x4);
/// UARTDR
const UARTDR_val = packed struct {
/// DATA [0:7]
/// Receive (read) data character. Transmit (write) data character.
DATA: u8 = 0,
/// FE [8:8]
/// Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO.
FE: u1 = 0,
/// PE [9:9]
/// Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO.
PE: u1 = 0,
/// BE [10:10]
/// Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received.
BE: u1 = 0,
/// OE [11:11]
/// Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it.
OE: u1 = 0,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Data Register, UARTDR
pub const UARTDR = Register(UARTDR_val).init(base_address + 0x0);
};
/// No description
pub const SPI0 = struct {
const base_address = 0x4003c000;
/// SSPPCELLID3
const SSPPCELLID3_val = packed struct {
/// SSPPCELLID3 [0:7]
/// These bits read back as 0xB1
SSPPCELLID3: u8 = 177,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// PrimeCell identification registers, SSPPCellID0-3 on page 3-16
pub const SSPPCELLID3 = Register(SSPPCELLID3_val).init(base_address + 0xffc);
/// SSPPCELLID2
const SSPPCELLID2_val = packed struct {
/// SSPPCELLID2 [0:7]
/// These bits read back as 0x05
SSPPCELLID2: u8 = 5,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// PrimeCell identification registers, SSPPCellID0-3 on page 3-16
pub const SSPPCELLID2 = Register(SSPPCELLID2_val).init(base_address + 0xff8);
/// SSPPCELLID1
const SSPPCELLID1_val = packed struct {
/// SSPPCELLID1 [0:7]
/// These bits read back as 0xF0
SSPPCELLID1: u8 = 240,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// PrimeCell identification registers, SSPPCellID0-3 on page 3-16
pub const SSPPCELLID1 = Register(SSPPCELLID1_val).init(base_address + 0xff4);
/// SSPPCELLID0
const SSPPCELLID0_val = packed struct {
/// SSPPCELLID0 [0:7]
/// These bits read back as 0x0D
SSPPCELLID0: u8 = 13,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// PrimeCell identification registers, SSPPCellID0-3 on page 3-16
pub const SSPPCELLID0 = Register(SSPPCELLID0_val).init(base_address + 0xff0);
/// SSPPERIPHID3
const SSPPERIPHID3_val = packed struct {
/// CONFIGURATION [0:7]
/// These bits read back as 0x00
CONFIGURATION: u8 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Peripheral identification registers, SSPPeriphID0-3 on page 3-13
pub const SSPPERIPHID3 = Register(SSPPERIPHID3_val).init(base_address + 0xfec);
/// SSPPERIPHID2
const SSPPERIPHID2_val = packed struct {
/// DESIGNER1 [0:3]
/// These bits read back as 0x4
DESIGNER1: u4 = 4,
/// REVISION [4:7]
/// These bits return the peripheral revision
REVISION: u4 = 3,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Peripheral identification registers, SSPPeriphID0-3 on page 3-13
pub const SSPPERIPHID2 = Register(SSPPERIPHID2_val).init(base_address + 0xfe8);
/// SSPPERIPHID1
const SSPPERIPHID1_val = packed struct {
/// PARTNUMBER1 [0:3]
/// These bits read back as 0x0
PARTNUMBER1: u4 = 0,
/// DESIGNER0 [4:7]
/// These bits read back as 0x1
DESIGNER0: u4 = 1,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Peripheral identification registers, SSPPeriphID0-3 on page 3-13
pub const SSPPERIPHID1 = Register(SSPPERIPHID1_val).init(base_address + 0xfe4);
/// SSPPERIPHID0
const SSPPERIPHID0_val = packed struct {
/// PARTNUMBER0 [0:7]
/// These bits read back as 0x22
PARTNUMBER0: u8 = 34,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Peripheral identification registers, SSPPeriphID0-3 on page 3-13
pub const SSPPERIPHID0 = Register(SSPPERIPHID0_val).init(base_address + 0xfe0);
/// SSPDMACR
const SSPDMACR_val = packed struct {
/// RXDMAE [0:0]
/// Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled.
RXDMAE: u1 = 0,
/// TXDMAE [1:1]
/// Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.
TXDMAE: u1 = 0,
/// unused [2:31]
_unused2: u6 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// DMA control register, SSPDMACR on page 3-12
pub const SSPDMACR = Register(SSPDMACR_val).init(base_address + 0x24);
/// SSPICR
const SSPICR_val = packed struct {
/// RORIC [0:0]
/// Clears the SSPRORINTR interrupt
RORIC: u1 = 0,
/// RTIC [1:1]
/// Clears the SSPRTINTR interrupt
RTIC: u1 = 0,
/// unused [2:31]
_unused2: u6 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt clear register, SSPICR on page 3-11
pub const SSPICR = Register(SSPICR_val).init(base_address + 0x20);
/// SSPMIS
const SSPMIS_val = packed struct {
/// RORMIS [0:0]
/// Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt
RORMIS: u1 = 0,
/// RTMIS [1:1]
/// Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
RTMIS: u1 = 0,
/// RXMIS [2:2]
/// Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt
RXMIS: u1 = 0,
/// TXMIS [3:3]
/// Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
TXMIS: u1 = 0,
/// unused [4:31]
_unused4: u4 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Masked interrupt status register, SSPMIS on page 3-11
pub const SSPMIS = Register(SSPMIS_val).init(base_address + 0x1c);
/// SSPRIS
const SSPRIS_val = packed struct {
/// RORRIS [0:0]
/// Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt
RORRIS: u1 = 0,
/// RTRIS [1:1]
/// Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt
RTRIS: u1 = 0,
/// RXRIS [2:2]
/// Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt
RXRIS: u1 = 0,
/// TXRIS [3:3]
/// Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt
TXRIS: u1 = 1,
/// unused [4:31]
_unused4: u4 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Raw interrupt status register, SSPRIS on page 3-10
pub const SSPRIS = Register(SSPRIS_val).init(base_address + 0x18);
/// SSPIMSC
const SSPIMSC_val = packed struct {
/// RORIM [0:0]
/// Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked.
RORIM: u1 = 0,
/// RTIM [1:1]
/// Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked.
RTIM: u1 = 0,
/// RXIM [2:2]
/// Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked.
RXIM: u1 = 0,
/// TXIM [3:3]
/// Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked.
TXIM: u1 = 0,
/// unused [4:31]
_unused4: u4 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt mask set or clear register, SSPIMSC on page 3-9
pub const SSPIMSC = Register(SSPIMSC_val).init(base_address + 0x14);
/// SSPCPSR
const SSPCPSR_val = packed struct {
/// CPSDVSR [0:7]
/// Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads.
CPSDVSR: u8 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Clock prescale register, SSPCPSR on page 3-8
pub const SSPCPSR = Register(SSPCPSR_val).init(base_address + 0x10);
/// SSPSR
const SSPSR_val = packed struct {
/// TFE [0:0]
/// Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty.
TFE: u1 = 1,
/// TNF [1:1]
/// Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full.
TNF: u1 = 1,
/// RNE [2:2]
/// Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty.
RNE: u1 = 0,
/// RFF [3:3]
/// Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full.
RFF: u1 = 0,
/// BSY [4:4]
/// PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty.
BSY: u1 = 0,
/// unused [5:31]
_unused5: u3 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Status register, SSPSR on page 3-7
pub const SSPSR = Register(SSPSR_val).init(base_address + 0xc);
/// SSPDR
const SSPDR_val = packed struct {
/// DATA [0:15]
/// Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies.
DATA: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Data register, SSPDR on page 3-6
pub const SSPDR = Register(SSPDR_val).init(base_address + 0x8);
/// SSPCR1
const SSPCR1_val = packed struct {
/// LBM [0:0]
/// Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally.
LBM: u1 = 0,
/// SSE [1:1]
/// Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled.
SSE: u1 = 0,
/// MS [2:2]
/// Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave.
MS: u1 = 0,
/// SOD [3:3]
/// Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode.
SOD: u1 = 0,
/// unused [4:31]
_unused4: u4 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Control register 1, SSPCR1 on page 3-5
pub const SSPCR1 = Register(SSPCR1_val).init(base_address + 0x4);
/// SSPCR0
const SSPCR0_val = packed struct {
/// DSS [0:3]
/// Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data.
DSS: u4 = 0,
/// FRF [4:5]
/// Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame format. 10 National Microwire frame format. 11 Reserved, undefined operation.
FRF: u2 = 0,
/// SPO [6:6]
/// SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10.
SPO: u1 = 0,
/// SPH [7:7]
/// SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10.
SPH: u1 = 0,
/// SCR [8:15]
/// Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255.
SCR: u8 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Control register 0, SSPCR0 on page 3-4
pub const SSPCR0 = Register(SSPCR0_val).init(base_address + 0x0);
};
/// No description
pub const SPI1 = struct {
const base_address = 0x40040000;
/// SSPPCELLID3
const SSPPCELLID3_val = packed struct {
/// SSPPCELLID3 [0:7]
/// These bits read back as 0xB1
SSPPCELLID3: u8 = 177,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// PrimeCell identification registers, SSPPCellID0-3 on page 3-16
pub const SSPPCELLID3 = Register(SSPPCELLID3_val).init(base_address + 0xffc);
/// SSPPCELLID2
const SSPPCELLID2_val = packed struct {
/// SSPPCELLID2 [0:7]
/// These bits read back as 0x05
SSPPCELLID2: u8 = 5,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// PrimeCell identification registers, SSPPCellID0-3 on page 3-16
pub const SSPPCELLID2 = Register(SSPPCELLID2_val).init(base_address + 0xff8);
/// SSPPCELLID1
const SSPPCELLID1_val = packed struct {
/// SSPPCELLID1 [0:7]
/// These bits read back as 0xF0
SSPPCELLID1: u8 = 240,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// PrimeCell identification registers, SSPPCellID0-3 on page 3-16
pub const SSPPCELLID1 = Register(SSPPCELLID1_val).init(base_address + 0xff4);
/// SSPPCELLID0
const SSPPCELLID0_val = packed struct {
/// SSPPCELLID0 [0:7]
/// These bits read back as 0x0D
SSPPCELLID0: u8 = 13,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// PrimeCell identification registers, SSPPCellID0-3 on page 3-16
pub const SSPPCELLID0 = Register(SSPPCELLID0_val).init(base_address + 0xff0);
/// SSPPERIPHID3
const SSPPERIPHID3_val = packed struct {
/// CONFIGURATION [0:7]
/// These bits read back as 0x00
CONFIGURATION: u8 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Peripheral identification registers, SSPPeriphID0-3 on page 3-13
pub const SSPPERIPHID3 = Register(SSPPERIPHID3_val).init(base_address + 0xfec);
/// SSPPERIPHID2
const SSPPERIPHID2_val = packed struct {
/// DESIGNER1 [0:3]
/// These bits read back as 0x4
DESIGNER1: u4 = 4,
/// REVISION [4:7]
/// These bits return the peripheral revision
REVISION: u4 = 3,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Peripheral identification registers, SSPPeriphID0-3 on page 3-13
pub const SSPPERIPHID2 = Register(SSPPERIPHID2_val).init(base_address + 0xfe8);
/// SSPPERIPHID1
const SSPPERIPHID1_val = packed struct {
/// PARTNUMBER1 [0:3]
/// These bits read back as 0x0
PARTNUMBER1: u4 = 0,
/// DESIGNER0 [4:7]
/// These bits read back as 0x1
DESIGNER0: u4 = 1,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Peripheral identification registers, SSPPeriphID0-3 on page 3-13
pub const SSPPERIPHID1 = Register(SSPPERIPHID1_val).init(base_address + 0xfe4);
/// SSPPERIPHID0
const SSPPERIPHID0_val = packed struct {
/// PARTNUMBER0 [0:7]
/// These bits read back as 0x22
PARTNUMBER0: u8 = 34,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Peripheral identification registers, SSPPeriphID0-3 on page 3-13
pub const SSPPERIPHID0 = Register(SSPPERIPHID0_val).init(base_address + 0xfe0);
/// SSPDMACR
const SSPDMACR_val = packed struct {
/// RXDMAE [0:0]
/// Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled.
RXDMAE: u1 = 0,
/// TXDMAE [1:1]
/// Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.
TXDMAE: u1 = 0,
/// unused [2:31]
_unused2: u6 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// DMA control register, SSPDMACR on page 3-12
pub const SSPDMACR = Register(SSPDMACR_val).init(base_address + 0x24);
/// SSPICR
const SSPICR_val = packed struct {
/// RORIC [0:0]
/// Clears the SSPRORINTR interrupt
RORIC: u1 = 0,
/// RTIC [1:1]
/// Clears the SSPRTINTR interrupt
RTIC: u1 = 0,
/// unused [2:31]
_unused2: u6 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt clear register, SSPICR on page 3-11
pub const SSPICR = Register(SSPICR_val).init(base_address + 0x20);
/// SSPMIS
const SSPMIS_val = packed struct {
/// RORMIS [0:0]
/// Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt
RORMIS: u1 = 0,
/// RTMIS [1:1]
/// Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
RTMIS: u1 = 0,
/// RXMIS [2:2]
/// Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt
RXMIS: u1 = 0,
/// TXMIS [3:3]
/// Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
TXMIS: u1 = 0,
/// unused [4:31]
_unused4: u4 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Masked interrupt status register, SSPMIS on page 3-11
pub const SSPMIS = Register(SSPMIS_val).init(base_address + 0x1c);
/// SSPRIS
const SSPRIS_val = packed struct {
/// RORRIS [0:0]
/// Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt
RORRIS: u1 = 0,
/// RTRIS [1:1]
/// Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt
RTRIS: u1 = 0,
/// RXRIS [2:2]
/// Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt
RXRIS: u1 = 0,
/// TXRIS [3:3]
/// Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt
TXRIS: u1 = 1,
/// unused [4:31]
_unused4: u4 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Raw interrupt status register, SSPRIS on page 3-10
pub const SSPRIS = Register(SSPRIS_val).init(base_address + 0x18);
/// SSPIMSC
const SSPIMSC_val = packed struct {
/// RORIM [0:0]
/// Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked.
RORIM: u1 = 0,
/// RTIM [1:1]
/// Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked.
RTIM: u1 = 0,
/// RXIM [2:2]
/// Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked.
RXIM: u1 = 0,
/// TXIM [3:3]
/// Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked.
TXIM: u1 = 0,
/// unused [4:31]
_unused4: u4 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt mask set or clear register, SSPIMSC on page 3-9
pub const SSPIMSC = Register(SSPIMSC_val).init(base_address + 0x14);
/// SSPCPSR
const SSPCPSR_val = packed struct {
/// CPSDVSR [0:7]
/// Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads.
CPSDVSR: u8 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Clock prescale register, SSPCPSR on page 3-8
pub const SSPCPSR = Register(SSPCPSR_val).init(base_address + 0x10);
/// SSPSR
const SSPSR_val = packed struct {
/// TFE [0:0]
/// Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty.
TFE: u1 = 1,
/// TNF [1:1]
/// Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full.
TNF: u1 = 1,
/// RNE [2:2]
/// Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty.
RNE: u1 = 0,
/// RFF [3:3]
/// Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full.
RFF: u1 = 0,
/// BSY [4:4]
/// PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty.
BSY: u1 = 0,
/// unused [5:31]
_unused5: u3 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Status register, SSPSR on page 3-7
pub const SSPSR = Register(SSPSR_val).init(base_address + 0xc);
/// SSPDR
const SSPDR_val = packed struct {
/// DATA [0:15]
/// Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies.
DATA: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Data register, SSPDR on page 3-6
pub const SSPDR = Register(SSPDR_val).init(base_address + 0x8);
/// SSPCR1
const SSPCR1_val = packed struct {
/// LBM [0:0]
/// Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally.
LBM: u1 = 0,
/// SSE [1:1]
/// Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled.
SSE: u1 = 0,
/// MS [2:2]
/// Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave.
MS: u1 = 0,
/// SOD [3:3]
/// Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode.
SOD: u1 = 0,
/// unused [4:31]
_unused4: u4 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Control register 1, SSPCR1 on page 3-5
pub const SSPCR1 = Register(SSPCR1_val).init(base_address + 0x4);
/// SSPCR0
const SSPCR0_val = packed struct {
/// DSS [0:3]
/// Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data.
DSS: u4 = 0,
/// FRF [4:5]
/// Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame format. 10 National Microwire frame format. 11 Reserved, undefined operation.
FRF: u2 = 0,
/// SPO [6:6]
/// SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10.
SPO: u1 = 0,
/// SPH [7:7]
/// SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10.
SPH: u1 = 0,
/// SCR [8:15]
/// Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255.
SCR: u8 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Control register 0, SSPCR0 on page 3-4
pub const SSPCR0 = Register(SSPCR0_val).init(base_address + 0x0);
};
/// DW_apb_i2c address block
pub const I2C0 = struct {
const base_address = 0x40044000;
/// IC_COMP_TYPE
const IC_COMP_TYPE_val = packed struct {
/// IC_COMP_TYPE [0:31]
/// Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number.
IC_COMP_TYPE: u32 = 1146552640,
};
/// I2C Component Type Register
pub const IC_COMP_TYPE = Register(IC_COMP_TYPE_val).init(base_address + 0xfc);
/// IC_COMP_VERSION
const IC_COMP_VERSION_val = packed struct {
/// IC_COMP_VERSION [0:31]
/// No description
IC_COMP_VERSION: u32 = 842019114,
};
/// I2C Component Version Register
pub const IC_COMP_VERSION = Register(IC_COMP_VERSION_val).init(base_address + 0xf8);
/// IC_COMP_PARAM_1
const IC_COMP_PARAM_1_val = packed struct {
/// APB_DATA_WIDTH [0:1]
/// APB data bus width is 32 bits
APB_DATA_WIDTH: u2 = 0,
/// MAX_SPEED_MODE [2:3]
/// MAX SPEED MODE = FAST MODE
MAX_SPEED_MODE: u2 = 0,
/// HC_COUNT_VALUES [4:4]
/// Programmable count values for each mode.
HC_COUNT_VALUES: u1 = 0,
/// INTR_IO [5:5]
/// COMBINED Interrupt outputs
INTR_IO: u1 = 0,
/// HAS_DMA [6:6]
/// DMA handshaking signals are enabled
HAS_DMA: u1 = 0,
/// ADD_ENCODED_PARAMS [7:7]
/// Encoded parameters not visible
ADD_ENCODED_PARAMS: u1 = 0,
/// RX_BUFFER_DEPTH [8:15]
/// RX Buffer Depth = 16
RX_BUFFER_DEPTH: u8 = 0,
/// TX_BUFFER_DEPTH [16:23]
/// TX Buffer Depth = 16
TX_BUFFER_DEPTH: u8 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Component Parameter Register 1\n\n
pub const IC_COMP_PARAM_1 = Register(IC_COMP_PARAM_1_val).init(base_address + 0xf4);
/// IC_CLR_RESTART_DET
const IC_CLR_RESTART_DET_val = packed struct {
/// CLR_RESTART_DET [0:0]
/// Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register.\n\n
CLR_RESTART_DET: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Clear RESTART_DET Interrupt Register
pub const IC_CLR_RESTART_DET = Register(IC_CLR_RESTART_DET_val).init(base_address + 0xa8);
/// IC_FS_SPKLEN
const IC_FS_SPKLEN_val = packed struct {
/// IC_FS_SPKLEN [0:7]
/// This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'.
IC_FS_SPKLEN: u8 = 7,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C SS, FS or FM+ spike suppression limit\n\n
pub const IC_FS_SPKLEN = Register(IC_FS_SPKLEN_val).init(base_address + 0xa0);
/// IC_ENABLE_STATUS
const IC_ENABLE_STATUS_val = packed struct {
/// IC_EN [0:0]
/// ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1).\n\n
IC_EN: u1 = 0,
/// SLV_DISABLED_WHILE_BUSY [1:1]
/// Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while:\n\n
SLV_DISABLED_WHILE_BUSY: u1 = 0,
/// SLV_RX_DATA_LOST [2:2]
/// Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK.\n\n
SLV_RX_DATA_LOST: u1 = 0,
/// unused [3:31]
_unused3: u5 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C Enable Status Register\n\n
pub const IC_ENABLE_STATUS = Register(IC_ENABLE_STATUS_val).init(base_address + 0x9c);
/// IC_ACK_GENERAL_CALL
const IC_ACK_GENERAL_CALL_val = packed struct {
/// ACK_GEN_CALL [0:0]
/// ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe).
ACK_GEN_CALL: u1 = 1,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C ACK General Call Register\n\n
pub const IC_ACK_GENERAL_CALL = Register(IC_ACK_GENERAL_CALL_val).init(base_address + 0x98);
/// IC_SDA_SETUP
const IC_SDA_SETUP_val = packed struct {
/// SDA_SETUP [0:7]
/// SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2.
SDA_SETUP: u8 = 100,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C SDA Setup Register\n\n
pub const IC_SDA_SETUP = Register(IC_SDA_SETUP_val).init(base_address + 0x94);
/// IC_DMA_RDLR
const IC_DMA_RDLR_val = packed struct {
/// DMARDL [0:3]
/// Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO.\n\n
DMARDL: u4 = 0,
/// unused [4:31]
_unused4: u4 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C Receive Data Level Register
pub const IC_DMA_RDLR = Register(IC_DMA_RDLR_val).init(base_address + 0x90);
/// IC_DMA_TDLR
const IC_DMA_TDLR_val = packed struct {
/// DMATDL [0:3]
/// Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1.\n\n
DMATDL: u4 = 0,
/// unused [4:31]
_unused4: u4 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// DMA Transmit Data Level Register
pub const IC_DMA_TDLR = Register(IC_DMA_TDLR_val).init(base_address + 0x8c);
/// IC_DMA_CR
const IC_DMA_CR_val = packed struct {
/// RDMAE [0:0]
/// Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0
RDMAE: u1 = 0,
/// TDMAE [1:1]
/// Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0
TDMAE: u1 = 0,
/// unused [2:31]
_unused2: u6 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// DMA Control Register\n\n
pub const IC_DMA_CR = Register(IC_DMA_CR_val).init(base_address + 0x88);
/// IC_SLV_DATA_NACK_ONLY
const IC_SLV_DATA_NACK_ONLY_val = packed struct {
/// NACK [0:0]
/// Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer.\n\n
NACK: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Generate Slave Data NACK Register\n\n
pub const IC_SLV_DATA_NACK_ONLY = Register(IC_SLV_DATA_NACK_ONLY_val).init(base_address + 0x84);
/// IC_TX_ABRT_SOURCE
const IC_TX_ABRT_SOURCE_val = packed struct {
/// ABRT_7B_ADDR_NOACK [0:0]
/// This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave.\n\n
ABRT_7B_ADDR_NOACK: u1 = 0,
/// ABRT_10ADDR1_NOACK [1:1]
/// This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave.\n\n
ABRT_10ADDR1_NOACK: u1 = 0,
/// ABRT_10ADDR2_NOACK [2:2]
/// This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave.\n\n
ABRT_10ADDR2_NOACK: u1 = 0,
/// ABRT_TXDATA_NOACK [3:3]
/// This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s).\n\n
ABRT_TXDATA_NOACK: u1 = 0,
/// ABRT_GCALL_NOACK [4:4]
/// This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call.\n\n
ABRT_GCALL_NOACK: u1 = 0,
/// ABRT_GCALL_READ [5:5]
/// This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1).\n\n
ABRT_GCALL_READ: u1 = 0,
/// ABRT_HS_ACKDET [6:6]
/// This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior).\n\n
ABRT_HS_ACKDET: u1 = 0,
/// ABRT_SBYTE_ACKDET [7:7]
/// This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior).\n\n
ABRT_SBYTE_ACKDET: u1 = 0,
/// ABRT_HS_NORSTRT [8:8]
/// This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode.\n\n
ABRT_HS_NORSTRT: u1 = 0,
/// ABRT_SBYTE_NORSTRT [9:9]
/// To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte.\n\n
ABRT_SBYTE_NORSTRT: u1 = 0,
/// ABRT_10B_RD_NORSTRT [10:10]
/// This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode.\n\n
ABRT_10B_RD_NORSTRT: u1 = 0,
/// ABRT_MASTER_DIS [11:11]
/// This field indicates that the User tries to initiate a Master operation with the Master mode disabled.\n\n
ABRT_MASTER_DIS: u1 = 0,
/// ARB_LOST [12:12]
/// This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration.\n\n
ARB_LOST: u1 = 0,
/// ABRT_SLVFLUSH_TXFIFO [13:13]
/// This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO.\n\n
ABRT_SLVFLUSH_TXFIFO: u1 = 0,
/// ABRT_SLV_ARBLOST [14:14]
/// This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus.\n\n
ABRT_SLV_ARBLOST: u1 = 0,
/// ABRT_SLVRD_INTX [15:15]
/// 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register.\n\n
ABRT_SLVRD_INTX: u1 = 0,
/// ABRT_USER_ABRT [16:16]
/// This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1])\n\n
ABRT_USER_ABRT: u1 = 0,
/// unused [17:22]
_unused17: u6 = 0,
/// TX_FLUSH_CNT [23:31]
/// This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled.\n\n
TX_FLUSH_CNT: u9 = 0,
};
/// I2C Transmit Abort Source Register\n\n
pub const IC_TX_ABRT_SOURCE = Register(IC_TX_ABRT_SOURCE_val).init(base_address + 0x80);
/// IC_SDA_HOLD
const IC_SDA_HOLD_val = packed struct {
/// IC_SDA_TX_HOLD [0:15]
/// Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter.\n\n
IC_SDA_TX_HOLD: u16 = 1,
/// IC_SDA_RX_HOLD [16:23]
/// Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver.\n\n
IC_SDA_RX_HOLD: u8 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// I2C SDA Hold Time Length Register\n\n
pub const IC_SDA_HOLD = Register(IC_SDA_HOLD_val).init(base_address + 0x7c);
/// IC_RXFLR
const IC_RXFLR_val = packed struct {
/// RXFLR [0:4]
/// Receive FIFO Level. Contains the number of valid data entries in the receive FIFO.\n\n
RXFLR: u5 = 0,
/// unused [5:31]
_unused5: u3 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO.
pub const IC_RXFLR = Register(IC_RXFLR_val).init(base_address + 0x78);
/// IC_TXFLR
const IC_TXFLR_val = packed struct {
/// TXFLR [0:4]
/// Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO.\n\n
TXFLR: u5 = 0,
/// unused [5:31]
_unused5: u3 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO.
pub const IC_TXFLR = Register(IC_TXFLR_val).init(base_address + 0x74);
/// IC_STATUS
const IC_STATUS_val = packed struct {
/// ACTIVITY [0:0]
/// I2C Activity Status. Reset value: 0x0
ACTIVITY: u1 = 0,
/// TFNF [1:1]
/// Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1
TFNF: u1 = 1,
/// TFE [2:2]
/// Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1
TFE: u1 = 1,
/// RFNE [3:3]
/// Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0
RFNE: u1 = 0,
/// RFF [4:4]
/// Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0
RFF: u1 = 0,
/// MST_ACTIVITY [5:5]
/// Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits.\n\n
MST_ACTIVITY: u1 = 0,
/// SLV_ACTIVITY [6:6]
/// Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0
SLV_ACTIVITY: u1 = 0,
/// unused [7:31]
_unused7: u1 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C Status Register\n\n
pub const IC_STATUS = Register(IC_STATUS_val).init(base_address + 0x70);
/// IC_ENABLE
const IC_ENABLE_val = packed struct {
/// ENABLE [0:0]
/// Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'.\n\n
ENABLE: u1 = 0,
/// ABORT [1:1]
/// When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation.\n\n
ABORT: u1 = 0,
/// TX_CMD_BLOCK [2:2]
/// In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT
TX_CMD_BLOCK: u1 = 0,
/// unused [3:31]
_unused3: u5 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C Enable Register
pub const IC_ENABLE = Register(IC_ENABLE_val).init(base_address + 0x6c);
/// IC_CLR_GEN_CALL
const IC_CLR_GEN_CALL_val = packed struct {
/// CLR_GEN_CALL [0:0]
/// Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register.\n\n
CLR_GEN_CALL: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Clear GEN_CALL Interrupt Register
pub const IC_CLR_GEN_CALL = Register(IC_CLR_GEN_CALL_val).init(base_address + 0x68);
/// IC_CLR_START_DET
const IC_CLR_START_DET_val = packed struct {
/// CLR_START_DET [0:0]
/// Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register.\n\n
CLR_START_DET: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Clear START_DET Interrupt Register
pub const IC_CLR_START_DET = Register(IC_CLR_START_DET_val).init(base_address + 0x64);
/// IC_CLR_STOP_DET
const IC_CLR_STOP_DET_val = packed struct {
/// CLR_STOP_DET [0:0]
/// Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register.\n\n
CLR_STOP_DET: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Clear STOP_DET Interrupt Register
pub const IC_CLR_STOP_DET = Register(IC_CLR_STOP_DET_val).init(base_address + 0x60);
/// IC_CLR_ACTIVITY
const IC_CLR_ACTIVITY_val = packed struct {
/// CLR_ACTIVITY [0:0]
/// Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register.\n\n
CLR_ACTIVITY: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Clear ACTIVITY Interrupt Register
pub const IC_CLR_ACTIVITY = Register(IC_CLR_ACTIVITY_val).init(base_address + 0x5c);
/// IC_CLR_RX_DONE
const IC_CLR_RX_DONE_val = packed struct {
/// CLR_RX_DONE [0:0]
/// Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register.\n\n
CLR_RX_DONE: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Clear RX_DONE Interrupt Register
pub const IC_CLR_RX_DONE = Register(IC_CLR_RX_DONE_val).init(base_address + 0x58);
/// IC_CLR_TX_ABRT
const IC_CLR_TX_ABRT_val = packed struct {
/// CLR_TX_ABRT [0:0]
/// Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.\n\n
CLR_TX_ABRT: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Clear TX_ABRT Interrupt Register
pub const IC_CLR_TX_ABRT = Register(IC_CLR_TX_ABRT_val).init(base_address + 0x54);
/// IC_CLR_RD_REQ
const IC_CLR_RD_REQ_val = packed struct {
/// CLR_RD_REQ [0:0]
/// Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register.\n\n
CLR_RD_REQ: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Clear RD_REQ Interrupt Register
pub const IC_CLR_RD_REQ = Register(IC_CLR_RD_REQ_val).init(base_address + 0x50);
/// IC_CLR_TX_OVER
const IC_CLR_TX_OVER_val = packed struct {
/// CLR_TX_OVER [0:0]
/// Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register.\n\n
CLR_TX_OVER: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Clear TX_OVER Interrupt Register
pub const IC_CLR_TX_OVER = Register(IC_CLR_TX_OVER_val).init(base_address + 0x4c);
/// IC_CLR_RX_OVER
const IC_CLR_RX_OVER_val = packed struct {
/// CLR_RX_OVER [0:0]
/// Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register.\n\n
CLR_RX_OVER: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Clear RX_OVER Interrupt Register
pub const IC_CLR_RX_OVER = Register(IC_CLR_RX_OVER_val).init(base_address + 0x48);
/// IC_CLR_RX_UNDER
const IC_CLR_RX_UNDER_val = packed struct {
/// CLR_RX_UNDER [0:0]
/// Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register.\n\n
CLR_RX_UNDER: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Clear RX_UNDER Interrupt Register
pub const IC_CLR_RX_UNDER = Register(IC_CLR_RX_UNDER_val).init(base_address + 0x44);
/// IC_CLR_INTR
const IC_CLR_INTR_val = packed struct {
/// CLR_INTR [0:0]
/// Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.\n\n
CLR_INTR: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Clear Combined and Individual Interrupt Register
pub const IC_CLR_INTR = Register(IC_CLR_INTR_val).init(base_address + 0x40);
/// IC_TX_TL
const IC_TX_TL_val = packed struct {
/// TX_TL [0:7]
/// Transmit FIFO Threshold Level.\n\n
TX_TL: u8 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C Transmit FIFO Threshold Register
pub const IC_TX_TL = Register(IC_TX_TL_val).init(base_address + 0x3c);
/// IC_RX_TL
const IC_RX_TL_val = packed struct {
/// RX_TL [0:7]
/// Receive FIFO Threshold Level.\n\n
RX_TL: u8 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C Receive FIFO Threshold Register
pub const IC_RX_TL = Register(IC_RX_TL_val).init(base_address + 0x38);
/// IC_RAW_INTR_STAT
const IC_RAW_INTR_STAT_val = packed struct {
/// RX_UNDER [0:0]
/// Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n
RX_UNDER: u1 = 0,
/// RX_OVER [1:1]
/// Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n
RX_OVER: u1 = 0,
/// RX_FULL [2:2]
/// Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues.\n\n
RX_FULL: u1 = 0,
/// TX_OVER [3:3]
/// Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n
TX_OVER: u1 = 0,
/// TX_EMPTY [4:4]
/// The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0.\n\n
TX_EMPTY: u1 = 0,
/// RD_REQ [5:5]
/// This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register.\n\n
RD_REQ: u1 = 0,
/// TX_ABRT [6:6]
/// This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places.\n\n
TX_ABRT: u1 = 0,
/// RX_DONE [7:7]
/// When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done.\n\n
RX_DONE: u1 = 0,
/// ACTIVITY [8:8]
/// This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus.\n\n
ACTIVITY: u1 = 0,
/// STOP_DET [9:9]
/// Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.\n\n
STOP_DET: u1 = 0,
/// START_DET [10:10]
/// Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.\n\n
START_DET: u1 = 0,
/// GEN_CALL [11:11]
/// Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer.\n\n
GEN_CALL: u1 = 0,
/// RESTART_DET [12:12]
/// Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1.\n\n
RESTART_DET: u1 = 0,
/// unused [13:31]
_unused13: u3 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C Raw Interrupt Status Register\n\n
pub const IC_RAW_INTR_STAT = Register(IC_RAW_INTR_STAT_val).init(base_address + 0x34);
/// IC_INTR_MASK
const IC_INTR_MASK_val = packed struct {
/// M_RX_UNDER [0:0]
/// This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register.\n\n
M_RX_UNDER: u1 = 1,
/// M_RX_OVER [1:1]
/// This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register.\n\n
M_RX_OVER: u1 = 1,
/// M_RX_FULL [2:2]
/// This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register.\n\n
M_RX_FULL: u1 = 1,
/// M_TX_OVER [3:3]
/// This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register.\n\n
M_TX_OVER: u1 = 1,
/// M_TX_EMPTY [4:4]
/// This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register.\n\n
M_TX_EMPTY: u1 = 1,
/// M_RD_REQ [5:5]
/// This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.\n\n
M_RD_REQ: u1 = 1,
/// M_TX_ABRT [6:6]
/// This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register.\n\n
M_TX_ABRT: u1 = 1,
/// M_RX_DONE [7:7]
/// This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register.\n\n
M_RX_DONE: u1 = 1,
/// M_ACTIVITY [8:8]
/// This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register.\n\n
M_ACTIVITY: u1 = 0,
/// M_STOP_DET [9:9]
/// This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register.\n\n
M_STOP_DET: u1 = 0,
/// M_START_DET [10:10]
/// This bit masks the R_START_DET interrupt in IC_INTR_STAT register.\n\n
M_START_DET: u1 = 0,
/// M_GEN_CALL [11:11]
/// This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register.\n\n
M_GEN_CALL: u1 = 1,
/// M_RESTART_DET [12:12]
/// This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register.\n\n
M_RESTART_DET: u1 = 0,
/// unused [13:31]
_unused13: u3 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C Interrupt Mask Register.\n\n
pub const IC_INTR_MASK = Register(IC_INTR_MASK_val).init(base_address + 0x30);
/// IC_INTR_STAT
const IC_INTR_STAT_val = packed struct {
/// R_RX_UNDER [0:0]
/// See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit.\n\n
R_RX_UNDER: u1 = 0,
/// R_RX_OVER [1:1]
/// See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit.\n\n
R_RX_OVER: u1 = 0,
/// R_RX_FULL [2:2]
/// See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit.\n\n
R_RX_FULL: u1 = 0,
/// R_TX_OVER [3:3]
/// See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit.\n\n
R_TX_OVER: u1 = 0,
/// R_TX_EMPTY [4:4]
/// See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit.\n\n
R_TX_EMPTY: u1 = 0,
/// R_RD_REQ [5:5]
/// See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit.\n\n
R_RD_REQ: u1 = 0,
/// R_TX_ABRT [6:6]
/// See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit.\n\n
R_TX_ABRT: u1 = 0,
/// R_RX_DONE [7:7]
/// See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit.\n\n
R_RX_DONE: u1 = 0,
/// R_ACTIVITY [8:8]
/// See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit.\n\n
R_ACTIVITY: u1 = 0,
/// R_STOP_DET [9:9]
/// See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit.\n\n
R_STOP_DET: u1 = 0,
/// R_START_DET [10:10]
/// See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit.\n\n
R_START_DET: u1 = 0,
/// R_GEN_CALL [11:11]
/// See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit.\n\n
R_GEN_CALL: u1 = 0,
/// R_RESTART_DET [12:12]
/// See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit.\n\n
R_RESTART_DET: u1 = 0,
/// unused [13:31]
_unused13: u3 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C Interrupt Status Register\n\n
pub const IC_INTR_STAT = Register(IC_INTR_STAT_val).init(base_address + 0x2c);
/// IC_FS_SCL_LCNT
const IC_FS_SCL_LCNT_val = packed struct {
/// IC_FS_SCL_LCNT [0:15]
/// This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n
IC_FS_SCL_LCNT: u16 = 13,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register
pub const IC_FS_SCL_LCNT = Register(IC_FS_SCL_LCNT_val).init(base_address + 0x20);
/// IC_FS_SCL_HCNT
const IC_FS_SCL_HCNT_val = packed struct {
/// IC_FS_SCL_HCNT [0:15]
/// This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n
IC_FS_SCL_HCNT: u16 = 6,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register
pub const IC_FS_SCL_HCNT = Register(IC_FS_SCL_HCNT_val).init(base_address + 0x1c);
/// IC_SS_SCL_LCNT
const IC_SS_SCL_LCNT_val = packed struct {
/// IC_SS_SCL_LCNT [0:15]
/// This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'\n\n
IC_SS_SCL_LCNT: u16 = 47,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Standard Speed I2C Clock SCL Low Count Register
pub const IC_SS_SCL_LCNT = Register(IC_SS_SCL_LCNT_val).init(base_address + 0x18);
/// IC_SS_SCL_HCNT
const IC_SS_SCL_HCNT_val = packed struct {
/// IC_SS_SCL_HCNT [0:15]
/// This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n
IC_SS_SCL_HCNT: u16 = 40,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Standard Speed I2C Clock SCL High Count Register
pub const IC_SS_SCL_HCNT = Register(IC_SS_SCL_HCNT_val).init(base_address + 0x14);
/// IC_DATA_CMD
const IC_DATA_CMD_val = packed struct {
/// DAT [0:7]
/// This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface.\n\n
DAT: u8 = 0,
/// CMD [8:8]
/// This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master.\n\n
CMD: u1 = 0,
/// STOP [9:9]
/// This bit controls whether a STOP is issued after the byte is sent or received.\n\n
STOP: u1 = 0,
/// RESTART [10:10]
/// This bit controls whether a RESTART is issued before the byte is sent or received.\n\n
RESTART: u1 = 0,
/// FIRST_DATA_BYTE [11:11]
/// Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode.\n\n
FIRST_DATA_BYTE: u1 = 0,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO.\n\n
pub const IC_DATA_CMD = Register(IC_DATA_CMD_val).init(base_address + 0x10);
/// IC_SAR
const IC_SAR_val = packed struct {
/// IC_SAR [0:9]
/// The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used.\n\n
IC_SAR: u10 = 85,
/// unused [10:31]
_unused10: u6 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C Slave Address Register
pub const IC_SAR = Register(IC_SAR_val).init(base_address + 0x8);
/// IC_TAR
const IC_TAR_val = packed struct {
/// IC_TAR [0:9]
/// This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits.\n\n
IC_TAR: u10 = 85,
/// GC_OR_START [10:10]
/// If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0
GC_OR_START: u1 = 0,
/// SPECIAL [11:11]
/// This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0
SPECIAL: u1 = 0,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C Target Address Register\n\n
pub const IC_TAR = Register(IC_TAR_val).init(base_address + 0x4);
/// IC_CON
const IC_CON_val = packed struct {
/// MASTER_MODE [0:0]
/// This bit controls whether the DW_apb_i2c master is enabled.\n\n
MASTER_MODE: u1 = 1,
/// SPEED [1:2]
/// These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode.\n\n
SPEED: u2 = 2,
/// IC_10BITADDR_SLAVE [3:3]
/// When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register.
IC_10BITADDR_SLAVE: u1 = 0,
/// IC_10BITADDR_MASTER [4:4]
/// Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing
IC_10BITADDR_MASTER: u1 = 0,
/// IC_RESTART_EN [5:5]
/// Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.\n\n
IC_RESTART_EN: u1 = 1,
/// IC_SLAVE_DISABLE [6:6]
/// This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled.\n\n
IC_SLAVE_DISABLE: u1 = 1,
/// STOP_DET_IFADDRESSED [7:7]
/// In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0\n\n
STOP_DET_IFADDRESSED: u1 = 0,
/// TX_EMPTY_CTRL [8:8]
/// This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register.\n\n
TX_EMPTY_CTRL: u1 = 0,
/// RX_FIFO_FULL_HLD_CTRL [9:9]
/// This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter.\n\n
RX_FIFO_FULL_HLD_CTRL: u1 = 0,
/// STOP_DET_IF_MASTER_ACTIVE [10:10]
/// Master issues the STOP_DET interrupt irrespective of whether master is active or not
STOP_DET_IF_MASTER_ACTIVE: u1 = 0,
/// unused [11:31]
_unused11: u5 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n
pub const IC_CON = Register(IC_CON_val).init(base_address + 0x0);
};
/// DW_apb_i2c address block
pub const I2C1 = struct {
const base_address = 0x40048000;
/// IC_COMP_TYPE
const IC_COMP_TYPE_val = packed struct {
/// IC_COMP_TYPE [0:31]
/// Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number.
IC_COMP_TYPE: u32 = 1146552640,
};
/// I2C Component Type Register
pub const IC_COMP_TYPE = Register(IC_COMP_TYPE_val).init(base_address + 0xfc);
/// IC_COMP_VERSION
const IC_COMP_VERSION_val = packed struct {
/// IC_COMP_VERSION [0:31]
/// No description
IC_COMP_VERSION: u32 = 842019114,
};
/// I2C Component Version Register
pub const IC_COMP_VERSION = Register(IC_COMP_VERSION_val).init(base_address + 0xf8);
/// IC_COMP_PARAM_1
const IC_COMP_PARAM_1_val = packed struct {
/// APB_DATA_WIDTH [0:1]
/// APB data bus width is 32 bits
APB_DATA_WIDTH: u2 = 0,
/// MAX_SPEED_MODE [2:3]
/// MAX SPEED MODE = FAST MODE
MAX_SPEED_MODE: u2 = 0,
/// HC_COUNT_VALUES [4:4]
/// Programmable count values for each mode.
HC_COUNT_VALUES: u1 = 0,
/// INTR_IO [5:5]
/// COMBINED Interrupt outputs
INTR_IO: u1 = 0,
/// HAS_DMA [6:6]
/// DMA handshaking signals are enabled
HAS_DMA: u1 = 0,
/// ADD_ENCODED_PARAMS [7:7]
/// Encoded parameters not visible
ADD_ENCODED_PARAMS: u1 = 0,
/// RX_BUFFER_DEPTH [8:15]
/// RX Buffer Depth = 16
RX_BUFFER_DEPTH: u8 = 0,
/// TX_BUFFER_DEPTH [16:23]
/// TX Buffer Depth = 16
TX_BUFFER_DEPTH: u8 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Component Parameter Register 1\n\n
pub const IC_COMP_PARAM_1 = Register(IC_COMP_PARAM_1_val).init(base_address + 0xf4);
/// IC_CLR_RESTART_DET
const IC_CLR_RESTART_DET_val = packed struct {
/// CLR_RESTART_DET [0:0]
/// Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register.\n\n
CLR_RESTART_DET: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Clear RESTART_DET Interrupt Register
pub const IC_CLR_RESTART_DET = Register(IC_CLR_RESTART_DET_val).init(base_address + 0xa8);
/// IC_FS_SPKLEN
const IC_FS_SPKLEN_val = packed struct {
/// IC_FS_SPKLEN [0:7]
/// This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'.
IC_FS_SPKLEN: u8 = 7,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C SS, FS or FM+ spike suppression limit\n\n
pub const IC_FS_SPKLEN = Register(IC_FS_SPKLEN_val).init(base_address + 0xa0);
/// IC_ENABLE_STATUS
const IC_ENABLE_STATUS_val = packed struct {
/// IC_EN [0:0]
/// ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1).\n\n
IC_EN: u1 = 0,
/// SLV_DISABLED_WHILE_BUSY [1:1]
/// Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while:\n\n
SLV_DISABLED_WHILE_BUSY: u1 = 0,
/// SLV_RX_DATA_LOST [2:2]
/// Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK.\n\n
SLV_RX_DATA_LOST: u1 = 0,
/// unused [3:31]
_unused3: u5 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C Enable Status Register\n\n
pub const IC_ENABLE_STATUS = Register(IC_ENABLE_STATUS_val).init(base_address + 0x9c);
/// IC_ACK_GENERAL_CALL
const IC_ACK_GENERAL_CALL_val = packed struct {
/// ACK_GEN_CALL [0:0]
/// ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe).
ACK_GEN_CALL: u1 = 1,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C ACK General Call Register\n\n
pub const IC_ACK_GENERAL_CALL = Register(IC_ACK_GENERAL_CALL_val).init(base_address + 0x98);
/// IC_SDA_SETUP
const IC_SDA_SETUP_val = packed struct {
/// SDA_SETUP [0:7]
/// SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2.
SDA_SETUP: u8 = 100,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C SDA Setup Register\n\n
pub const IC_SDA_SETUP = Register(IC_SDA_SETUP_val).init(base_address + 0x94);
/// IC_DMA_RDLR
const IC_DMA_RDLR_val = packed struct {
/// DMARDL [0:3]
/// Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO.\n\n
DMARDL: u4 = 0,
/// unused [4:31]
_unused4: u4 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C Receive Data Level Register
pub const IC_DMA_RDLR = Register(IC_DMA_RDLR_val).init(base_address + 0x90);
/// IC_DMA_TDLR
const IC_DMA_TDLR_val = packed struct {
/// DMATDL [0:3]
/// Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1.\n\n
DMATDL: u4 = 0,
/// unused [4:31]
_unused4: u4 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// DMA Transmit Data Level Register
pub const IC_DMA_TDLR = Register(IC_DMA_TDLR_val).init(base_address + 0x8c);
/// IC_DMA_CR
const IC_DMA_CR_val = packed struct {
/// RDMAE [0:0]
/// Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0
RDMAE: u1 = 0,
/// TDMAE [1:1]
/// Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0
TDMAE: u1 = 0,
/// unused [2:31]
_unused2: u6 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// DMA Control Register\n\n
pub const IC_DMA_CR = Register(IC_DMA_CR_val).init(base_address + 0x88);
/// IC_SLV_DATA_NACK_ONLY
const IC_SLV_DATA_NACK_ONLY_val = packed struct {
/// NACK [0:0]
/// Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer.\n\n
NACK: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Generate Slave Data NACK Register\n\n
pub const IC_SLV_DATA_NACK_ONLY = Register(IC_SLV_DATA_NACK_ONLY_val).init(base_address + 0x84);
/// IC_TX_ABRT_SOURCE
const IC_TX_ABRT_SOURCE_val = packed struct {
/// ABRT_7B_ADDR_NOACK [0:0]
/// This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave.\n\n
ABRT_7B_ADDR_NOACK: u1 = 0,
/// ABRT_10ADDR1_NOACK [1:1]
/// This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave.\n\n
ABRT_10ADDR1_NOACK: u1 = 0,
/// ABRT_10ADDR2_NOACK [2:2]
/// This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave.\n\n
ABRT_10ADDR2_NOACK: u1 = 0,
/// ABRT_TXDATA_NOACK [3:3]
/// This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s).\n\n
ABRT_TXDATA_NOACK: u1 = 0,
/// ABRT_GCALL_NOACK [4:4]
/// This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call.\n\n
ABRT_GCALL_NOACK: u1 = 0,
/// ABRT_GCALL_READ [5:5]
/// This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1).\n\n
ABRT_GCALL_READ: u1 = 0,
/// ABRT_HS_ACKDET [6:6]
/// This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior).\n\n
ABRT_HS_ACKDET: u1 = 0,
/// ABRT_SBYTE_ACKDET [7:7]
/// This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior).\n\n
ABRT_SBYTE_ACKDET: u1 = 0,
/// ABRT_HS_NORSTRT [8:8]
/// This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode.\n\n
ABRT_HS_NORSTRT: u1 = 0,
/// ABRT_SBYTE_NORSTRT [9:9]
/// To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte.\n\n
ABRT_SBYTE_NORSTRT: u1 = 0,
/// ABRT_10B_RD_NORSTRT [10:10]
/// This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode.\n\n
ABRT_10B_RD_NORSTRT: u1 = 0,
/// ABRT_MASTER_DIS [11:11]
/// This field indicates that the User tries to initiate a Master operation with the Master mode disabled.\n\n
ABRT_MASTER_DIS: u1 = 0,
/// ARB_LOST [12:12]
/// This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration.\n\n
ARB_LOST: u1 = 0,
/// ABRT_SLVFLUSH_TXFIFO [13:13]
/// This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO.\n\n
ABRT_SLVFLUSH_TXFIFO: u1 = 0,
/// ABRT_SLV_ARBLOST [14:14]
/// This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus.\n\n
ABRT_SLV_ARBLOST: u1 = 0,
/// ABRT_SLVRD_INTX [15:15]
/// 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register.\n\n
ABRT_SLVRD_INTX: u1 = 0,
/// ABRT_USER_ABRT [16:16]
/// This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1])\n\n
ABRT_USER_ABRT: u1 = 0,
/// unused [17:22]
_unused17: u6 = 0,
/// TX_FLUSH_CNT [23:31]
/// This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled.\n\n
TX_FLUSH_CNT: u9 = 0,
};
/// I2C Transmit Abort Source Register\n\n
pub const IC_TX_ABRT_SOURCE = Register(IC_TX_ABRT_SOURCE_val).init(base_address + 0x80);
/// IC_SDA_HOLD
const IC_SDA_HOLD_val = packed struct {
/// IC_SDA_TX_HOLD [0:15]
/// Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter.\n\n
IC_SDA_TX_HOLD: u16 = 1,
/// IC_SDA_RX_HOLD [16:23]
/// Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver.\n\n
IC_SDA_RX_HOLD: u8 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// I2C SDA Hold Time Length Register\n\n
pub const IC_SDA_HOLD = Register(IC_SDA_HOLD_val).init(base_address + 0x7c);
/// IC_RXFLR
const IC_RXFLR_val = packed struct {
/// RXFLR [0:4]
/// Receive FIFO Level. Contains the number of valid data entries in the receive FIFO.\n\n
RXFLR: u5 = 0,
/// unused [5:31]
_unused5: u3 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO.
pub const IC_RXFLR = Register(IC_RXFLR_val).init(base_address + 0x78);
/// IC_TXFLR
const IC_TXFLR_val = packed struct {
/// TXFLR [0:4]
/// Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO.\n\n
TXFLR: u5 = 0,
/// unused [5:31]
_unused5: u3 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO.
pub const IC_TXFLR = Register(IC_TXFLR_val).init(base_address + 0x74);
/// IC_STATUS
const IC_STATUS_val = packed struct {
/// ACTIVITY [0:0]
/// I2C Activity Status. Reset value: 0x0
ACTIVITY: u1 = 0,
/// TFNF [1:1]
/// Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1
TFNF: u1 = 1,
/// TFE [2:2]
/// Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1
TFE: u1 = 1,
/// RFNE [3:3]
/// Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0
RFNE: u1 = 0,
/// RFF [4:4]
/// Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0
RFF: u1 = 0,
/// MST_ACTIVITY [5:5]
/// Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits.\n\n
MST_ACTIVITY: u1 = 0,
/// SLV_ACTIVITY [6:6]
/// Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0
SLV_ACTIVITY: u1 = 0,
/// unused [7:31]
_unused7: u1 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C Status Register\n\n
pub const IC_STATUS = Register(IC_STATUS_val).init(base_address + 0x70);
/// IC_ENABLE
const IC_ENABLE_val = packed struct {
/// ENABLE [0:0]
/// Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'.\n\n
ENABLE: u1 = 0,
/// ABORT [1:1]
/// When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation.\n\n
ABORT: u1 = 0,
/// TX_CMD_BLOCK [2:2]
/// In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT
TX_CMD_BLOCK: u1 = 0,
/// unused [3:31]
_unused3: u5 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C Enable Register
pub const IC_ENABLE = Register(IC_ENABLE_val).init(base_address + 0x6c);
/// IC_CLR_GEN_CALL
const IC_CLR_GEN_CALL_val = packed struct {
/// CLR_GEN_CALL [0:0]
/// Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register.\n\n
CLR_GEN_CALL: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Clear GEN_CALL Interrupt Register
pub const IC_CLR_GEN_CALL = Register(IC_CLR_GEN_CALL_val).init(base_address + 0x68);
/// IC_CLR_START_DET
const IC_CLR_START_DET_val = packed struct {
/// CLR_START_DET [0:0]
/// Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register.\n\n
CLR_START_DET: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Clear START_DET Interrupt Register
pub const IC_CLR_START_DET = Register(IC_CLR_START_DET_val).init(base_address + 0x64);
/// IC_CLR_STOP_DET
const IC_CLR_STOP_DET_val = packed struct {
/// CLR_STOP_DET [0:0]
/// Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register.\n\n
CLR_STOP_DET: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Clear STOP_DET Interrupt Register
pub const IC_CLR_STOP_DET = Register(IC_CLR_STOP_DET_val).init(base_address + 0x60);
/// IC_CLR_ACTIVITY
const IC_CLR_ACTIVITY_val = packed struct {
/// CLR_ACTIVITY [0:0]
/// Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register.\n\n
CLR_ACTIVITY: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Clear ACTIVITY Interrupt Register
pub const IC_CLR_ACTIVITY = Register(IC_CLR_ACTIVITY_val).init(base_address + 0x5c);
/// IC_CLR_RX_DONE
const IC_CLR_RX_DONE_val = packed struct {
/// CLR_RX_DONE [0:0]
/// Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register.\n\n
CLR_RX_DONE: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Clear RX_DONE Interrupt Register
pub const IC_CLR_RX_DONE = Register(IC_CLR_RX_DONE_val).init(base_address + 0x58);
/// IC_CLR_TX_ABRT
const IC_CLR_TX_ABRT_val = packed struct {
/// CLR_TX_ABRT [0:0]
/// Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.\n\n
CLR_TX_ABRT: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Clear TX_ABRT Interrupt Register
pub const IC_CLR_TX_ABRT = Register(IC_CLR_TX_ABRT_val).init(base_address + 0x54);
/// IC_CLR_RD_REQ
const IC_CLR_RD_REQ_val = packed struct {
/// CLR_RD_REQ [0:0]
/// Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register.\n\n
CLR_RD_REQ: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Clear RD_REQ Interrupt Register
pub const IC_CLR_RD_REQ = Register(IC_CLR_RD_REQ_val).init(base_address + 0x50);
/// IC_CLR_TX_OVER
const IC_CLR_TX_OVER_val = packed struct {
/// CLR_TX_OVER [0:0]
/// Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register.\n\n
CLR_TX_OVER: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Clear TX_OVER Interrupt Register
pub const IC_CLR_TX_OVER = Register(IC_CLR_TX_OVER_val).init(base_address + 0x4c);
/// IC_CLR_RX_OVER
const IC_CLR_RX_OVER_val = packed struct {
/// CLR_RX_OVER [0:0]
/// Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register.\n\n
CLR_RX_OVER: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Clear RX_OVER Interrupt Register
pub const IC_CLR_RX_OVER = Register(IC_CLR_RX_OVER_val).init(base_address + 0x48);
/// IC_CLR_RX_UNDER
const IC_CLR_RX_UNDER_val = packed struct {
/// CLR_RX_UNDER [0:0]
/// Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register.\n\n
CLR_RX_UNDER: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Clear RX_UNDER Interrupt Register
pub const IC_CLR_RX_UNDER = Register(IC_CLR_RX_UNDER_val).init(base_address + 0x44);
/// IC_CLR_INTR
const IC_CLR_INTR_val = packed struct {
/// CLR_INTR [0:0]
/// Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.\n\n
CLR_INTR: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Clear Combined and Individual Interrupt Register
pub const IC_CLR_INTR = Register(IC_CLR_INTR_val).init(base_address + 0x40);
/// IC_TX_TL
const IC_TX_TL_val = packed struct {
/// TX_TL [0:7]
/// Transmit FIFO Threshold Level.\n\n
TX_TL: u8 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C Transmit FIFO Threshold Register
pub const IC_TX_TL = Register(IC_TX_TL_val).init(base_address + 0x3c);
/// IC_RX_TL
const IC_RX_TL_val = packed struct {
/// RX_TL [0:7]
/// Receive FIFO Threshold Level.\n\n
RX_TL: u8 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C Receive FIFO Threshold Register
pub const IC_RX_TL = Register(IC_RX_TL_val).init(base_address + 0x38);
/// IC_RAW_INTR_STAT
const IC_RAW_INTR_STAT_val = packed struct {
/// RX_UNDER [0:0]
/// Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n
RX_UNDER: u1 = 0,
/// RX_OVER [1:1]
/// Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n
RX_OVER: u1 = 0,
/// RX_FULL [2:2]
/// Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues.\n\n
RX_FULL: u1 = 0,
/// TX_OVER [3:3]
/// Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n
TX_OVER: u1 = 0,
/// TX_EMPTY [4:4]
/// The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0.\n\n
TX_EMPTY: u1 = 0,
/// RD_REQ [5:5]
/// This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register.\n\n
RD_REQ: u1 = 0,
/// TX_ABRT [6:6]
/// This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places.\n\n
TX_ABRT: u1 = 0,
/// RX_DONE [7:7]
/// When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done.\n\n
RX_DONE: u1 = 0,
/// ACTIVITY [8:8]
/// This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus.\n\n
ACTIVITY: u1 = 0,
/// STOP_DET [9:9]
/// Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.\n\n
STOP_DET: u1 = 0,
/// START_DET [10:10]
/// Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.\n\n
START_DET: u1 = 0,
/// GEN_CALL [11:11]
/// Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer.\n\n
GEN_CALL: u1 = 0,
/// RESTART_DET [12:12]
/// Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1.\n\n
RESTART_DET: u1 = 0,
/// unused [13:31]
_unused13: u3 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C Raw Interrupt Status Register\n\n
pub const IC_RAW_INTR_STAT = Register(IC_RAW_INTR_STAT_val).init(base_address + 0x34);
/// IC_INTR_MASK
const IC_INTR_MASK_val = packed struct {
/// M_RX_UNDER [0:0]
/// This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register.\n\n
M_RX_UNDER: u1 = 1,
/// M_RX_OVER [1:1]
/// This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register.\n\n
M_RX_OVER: u1 = 1,
/// M_RX_FULL [2:2]
/// This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register.\n\n
M_RX_FULL: u1 = 1,
/// M_TX_OVER [3:3]
/// This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register.\n\n
M_TX_OVER: u1 = 1,
/// M_TX_EMPTY [4:4]
/// This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register.\n\n
M_TX_EMPTY: u1 = 1,
/// M_RD_REQ [5:5]
/// This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.\n\n
M_RD_REQ: u1 = 1,
/// M_TX_ABRT [6:6]
/// This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register.\n\n
M_TX_ABRT: u1 = 1,
/// M_RX_DONE [7:7]
/// This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register.\n\n
M_RX_DONE: u1 = 1,
/// M_ACTIVITY [8:8]
/// This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register.\n\n
M_ACTIVITY: u1 = 0,
/// M_STOP_DET [9:9]
/// This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register.\n\n
M_STOP_DET: u1 = 0,
/// M_START_DET [10:10]
/// This bit masks the R_START_DET interrupt in IC_INTR_STAT register.\n\n
M_START_DET: u1 = 0,
/// M_GEN_CALL [11:11]
/// This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register.\n\n
M_GEN_CALL: u1 = 1,
/// M_RESTART_DET [12:12]
/// This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register.\n\n
M_RESTART_DET: u1 = 0,
/// unused [13:31]
_unused13: u3 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C Interrupt Mask Register.\n\n
pub const IC_INTR_MASK = Register(IC_INTR_MASK_val).init(base_address + 0x30);
/// IC_INTR_STAT
const IC_INTR_STAT_val = packed struct {
/// R_RX_UNDER [0:0]
/// See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit.\n\n
R_RX_UNDER: u1 = 0,
/// R_RX_OVER [1:1]
/// See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit.\n\n
R_RX_OVER: u1 = 0,
/// R_RX_FULL [2:2]
/// See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit.\n\n
R_RX_FULL: u1 = 0,
/// R_TX_OVER [3:3]
/// See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit.\n\n
R_TX_OVER: u1 = 0,
/// R_TX_EMPTY [4:4]
/// See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit.\n\n
R_TX_EMPTY: u1 = 0,
/// R_RD_REQ [5:5]
/// See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit.\n\n
R_RD_REQ: u1 = 0,
/// R_TX_ABRT [6:6]
/// See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit.\n\n
R_TX_ABRT: u1 = 0,
/// R_RX_DONE [7:7]
/// See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit.\n\n
R_RX_DONE: u1 = 0,
/// R_ACTIVITY [8:8]
/// See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit.\n\n
R_ACTIVITY: u1 = 0,
/// R_STOP_DET [9:9]
/// See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit.\n\n
R_STOP_DET: u1 = 0,
/// R_START_DET [10:10]
/// See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit.\n\n
R_START_DET: u1 = 0,
/// R_GEN_CALL [11:11]
/// See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit.\n\n
R_GEN_CALL: u1 = 0,
/// R_RESTART_DET [12:12]
/// See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit.\n\n
R_RESTART_DET: u1 = 0,
/// unused [13:31]
_unused13: u3 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C Interrupt Status Register\n\n
pub const IC_INTR_STAT = Register(IC_INTR_STAT_val).init(base_address + 0x2c);
/// IC_FS_SCL_LCNT
const IC_FS_SCL_LCNT_val = packed struct {
/// IC_FS_SCL_LCNT [0:15]
/// This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n
IC_FS_SCL_LCNT: u16 = 13,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register
pub const IC_FS_SCL_LCNT = Register(IC_FS_SCL_LCNT_val).init(base_address + 0x20);
/// IC_FS_SCL_HCNT
const IC_FS_SCL_HCNT_val = packed struct {
/// IC_FS_SCL_HCNT [0:15]
/// This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n
IC_FS_SCL_HCNT: u16 = 6,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register
pub const IC_FS_SCL_HCNT = Register(IC_FS_SCL_HCNT_val).init(base_address + 0x1c);
/// IC_SS_SCL_LCNT
const IC_SS_SCL_LCNT_val = packed struct {
/// IC_SS_SCL_LCNT [0:15]
/// This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'\n\n
IC_SS_SCL_LCNT: u16 = 47,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Standard Speed I2C Clock SCL Low Count Register
pub const IC_SS_SCL_LCNT = Register(IC_SS_SCL_LCNT_val).init(base_address + 0x18);
/// IC_SS_SCL_HCNT
const IC_SS_SCL_HCNT_val = packed struct {
/// IC_SS_SCL_HCNT [0:15]
/// This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n
IC_SS_SCL_HCNT: u16 = 40,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Standard Speed I2C Clock SCL High Count Register
pub const IC_SS_SCL_HCNT = Register(IC_SS_SCL_HCNT_val).init(base_address + 0x14);
/// IC_DATA_CMD
const IC_DATA_CMD_val = packed struct {
/// DAT [0:7]
/// This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface.\n\n
DAT: u8 = 0,
/// CMD [8:8]
/// This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master.\n\n
CMD: u1 = 0,
/// STOP [9:9]
/// This bit controls whether a STOP is issued after the byte is sent or received.\n\n
STOP: u1 = 0,
/// RESTART [10:10]
/// This bit controls whether a RESTART is issued before the byte is sent or received.\n\n
RESTART: u1 = 0,
/// FIRST_DATA_BYTE [11:11]
/// Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode.\n\n
FIRST_DATA_BYTE: u1 = 0,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO.\n\n
pub const IC_DATA_CMD = Register(IC_DATA_CMD_val).init(base_address + 0x10);
/// IC_SAR
const IC_SAR_val = packed struct {
/// IC_SAR [0:9]
/// The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used.\n\n
IC_SAR: u10 = 85,
/// unused [10:31]
_unused10: u6 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C Slave Address Register
pub const IC_SAR = Register(IC_SAR_val).init(base_address + 0x8);
/// IC_TAR
const IC_TAR_val = packed struct {
/// IC_TAR [0:9]
/// This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits.\n\n
IC_TAR: u10 = 85,
/// GC_OR_START [10:10]
/// If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0
GC_OR_START: u1 = 0,
/// SPECIAL [11:11]
/// This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0
SPECIAL: u1 = 0,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C Target Address Register\n\n
pub const IC_TAR = Register(IC_TAR_val).init(base_address + 0x4);
/// IC_CON
const IC_CON_val = packed struct {
/// MASTER_MODE [0:0]
/// This bit controls whether the DW_apb_i2c master is enabled.\n\n
MASTER_MODE: u1 = 1,
/// SPEED [1:2]
/// These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode.\n\n
SPEED: u2 = 2,
/// IC_10BITADDR_SLAVE [3:3]
/// When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register.
IC_10BITADDR_SLAVE: u1 = 0,
/// IC_10BITADDR_MASTER [4:4]
/// Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing
IC_10BITADDR_MASTER: u1 = 0,
/// IC_RESTART_EN [5:5]
/// Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.\n\n
IC_RESTART_EN: u1 = 1,
/// IC_SLAVE_DISABLE [6:6]
/// This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled.\n\n
IC_SLAVE_DISABLE: u1 = 1,
/// STOP_DET_IFADDRESSED [7:7]
/// In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0\n\n
STOP_DET_IFADDRESSED: u1 = 0,
/// TX_EMPTY_CTRL [8:8]
/// This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register.\n\n
TX_EMPTY_CTRL: u1 = 0,
/// RX_FIFO_FULL_HLD_CTRL [9:9]
/// This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter.\n\n
RX_FIFO_FULL_HLD_CTRL: u1 = 0,
/// STOP_DET_IF_MASTER_ACTIVE [10:10]
/// Master issues the STOP_DET interrupt irrespective of whether master is active or not
STOP_DET_IF_MASTER_ACTIVE: u1 = 0,
/// unused [11:31]
_unused11: u5 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n
pub const IC_CON = Register(IC_CON_val).init(base_address + 0x0);
};
/// Control and data interface to SAR ADC
pub const ADC = struct {
const base_address = 0x4004c000;
/// INTS
const INTS_val = packed struct {
/// FIFO [0:0]
/// Triggered when the sample FIFO reaches a certain level.\n
FIFO: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt status after masking & forcing
pub const INTS = Register(INTS_val).init(base_address + 0x20);
/// INTF
const INTF_val = packed struct {
/// FIFO [0:0]
/// Triggered when the sample FIFO reaches a certain level.\n
FIFO: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt Force
pub const INTF = Register(INTF_val).init(base_address + 0x1c);
/// INTE
const INTE_val = packed struct {
/// FIFO [0:0]
/// Triggered when the sample FIFO reaches a certain level.\n
FIFO: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt Enable
pub const INTE = Register(INTE_val).init(base_address + 0x18);
/// INTR
const INTR_val = packed struct {
/// FIFO [0:0]
/// Triggered when the sample FIFO reaches a certain level.\n
FIFO: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Raw Interrupts
pub const INTR = Register(INTR_val).init(base_address + 0x14);
/// DIV
const DIV_val = packed struct {
/// FRAC [0:7]
/// Fractional part of clock divisor. First-order delta-sigma.
FRAC: u8 = 0,
/// INT [8:23]
/// Integer part of clock divisor.
INT: u16 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Clock divider. If non-zero, CS_START_MANY will start conversions\n
pub const DIV = Register(DIV_val).init(base_address + 0x10);
/// FIFO
const FIFO_val = packed struct {
/// VAL [0:11]
/// No description
VAL: u12 = 0,
/// unused [12:14]
_unused12: u3 = 0,
/// ERR [15:15]
/// 1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted.
ERR: u1 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Conversion result FIFO
pub const FIFO = Register(FIFO_val).init(base_address + 0xc);
/// FCS
const FCS_val = packed struct {
/// EN [0:0]
/// If 1: write result to the FIFO after each conversion.
EN: u1 = 0,
/// SHIFT [1:1]
/// If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers.
SHIFT: u1 = 0,
/// ERR [2:2]
/// If 1: conversion error bit appears in the FIFO alongside the result
ERR: u1 = 0,
/// DREQ_EN [3:3]
/// If 1: assert DMA requests when FIFO contains data
DREQ_EN: u1 = 0,
/// unused [4:7]
_unused4: u4 = 0,
/// EMPTY [8:8]
/// No description
EMPTY: u1 = 0,
/// FULL [9:9]
/// No description
FULL: u1 = 0,
/// UNDER [10:10]
/// 1 if the FIFO has been underflowed. Write 1 to clear.
UNDER: u1 = 0,
/// OVER [11:11]
/// 1 if the FIFO has been overflowed. Write 1 to clear.
OVER: u1 = 0,
/// unused [12:15]
_unused12: u4 = 0,
/// LEVEL [16:19]
/// The number of conversion results currently waiting in the FIFO
LEVEL: u4 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// THRESH [24:27]
/// DREQ/IRQ asserted when level >= threshold
THRESH: u4 = 0,
/// unused [28:31]
_unused28: u4 = 0,
};
/// FIFO control and status
pub const FCS = Register(FCS_val).init(base_address + 0x8);
/// RESULT
const RESULT_val = packed struct {
/// RESULT [0:11]
/// No description
RESULT: u12 = 0,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Result of most recent ADC conversion
pub const RESULT = Register(RESULT_val).init(base_address + 0x4);
/// CS
const CS_val = packed struct {
/// EN [0:0]
/// Power on ADC and enable its clock.\n
EN: u1 = 0,
/// TS_EN [1:1]
/// Power on temperature sensor. 1 - enabled. 0 - disabled.
TS_EN: u1 = 0,
/// START_ONCE [2:2]
/// Start a single conversion. Self-clearing. Ignored if start_many is asserted.
START_ONCE: u1 = 0,
/// START_MANY [3:3]
/// Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes.
START_MANY: u1 = 0,
/// unused [4:7]
_unused4: u4 = 0,
/// READY [8:8]
/// 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed.\n
READY: u1 = 0,
/// ERR [9:9]
/// The most recent ADC conversion encountered an error; result is undefined or noisy.
ERR: u1 = 0,
/// ERR_STICKY [10:10]
/// Some past ADC conversion encountered an error. Write 1 to clear.
ERR_STICKY: u1 = 0,
/// unused [11:11]
_unused11: u1 = 0,
/// AINSEL [12:14]
/// Select analog mux input. Updated automatically in round-robin mode.
AINSEL: u3 = 0,
/// unused [15:15]
_unused15: u1 = 0,
/// RROBIN [16:20]
/// Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable.\n
RROBIN: u5 = 0,
/// unused [21:31]
_unused21: u3 = 0,
_unused24: u8 = 0,
};
/// ADC Control and Status
pub const CS = Register(CS_val).init(base_address + 0x0);
};
/// Simple PWM
pub const PWM = struct {
const base_address = 0x40050000;
/// INTS
const INTS_val = packed struct {
/// CH0 [0:0]
/// No description
CH0: u1 = 0,
/// CH1 [1:1]
/// No description
CH1: u1 = 0,
/// CH2 [2:2]
/// No description
CH2: u1 = 0,
/// CH3 [3:3]
/// No description
CH3: u1 = 0,
/// CH4 [4:4]
/// No description
CH4: u1 = 0,
/// CH5 [5:5]
/// No description
CH5: u1 = 0,
/// CH6 [6:6]
/// No description
CH6: u1 = 0,
/// CH7 [7:7]
/// No description
CH7: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt status after masking & forcing
pub const INTS = Register(INTS_val).init(base_address + 0xb0);
/// INTF
const INTF_val = packed struct {
/// CH0 [0:0]
/// No description
CH0: u1 = 0,
/// CH1 [1:1]
/// No description
CH1: u1 = 0,
/// CH2 [2:2]
/// No description
CH2: u1 = 0,
/// CH3 [3:3]
/// No description
CH3: u1 = 0,
/// CH4 [4:4]
/// No description
CH4: u1 = 0,
/// CH5 [5:5]
/// No description
CH5: u1 = 0,
/// CH6 [6:6]
/// No description
CH6: u1 = 0,
/// CH7 [7:7]
/// No description
CH7: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt Force
pub const INTF = Register(INTF_val).init(base_address + 0xac);
/// INTE
const INTE_val = packed struct {
/// CH0 [0:0]
/// No description
CH0: u1 = 0,
/// CH1 [1:1]
/// No description
CH1: u1 = 0,
/// CH2 [2:2]
/// No description
CH2: u1 = 0,
/// CH3 [3:3]
/// No description
CH3: u1 = 0,
/// CH4 [4:4]
/// No description
CH4: u1 = 0,
/// CH5 [5:5]
/// No description
CH5: u1 = 0,
/// CH6 [6:6]
/// No description
CH6: u1 = 0,
/// CH7 [7:7]
/// No description
CH7: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt Enable
pub const INTE = Register(INTE_val).init(base_address + 0xa8);
/// INTR
const INTR_val = packed struct {
/// CH0 [0:0]
/// No description
CH0: u1 = 0,
/// CH1 [1:1]
/// No description
CH1: u1 = 0,
/// CH2 [2:2]
/// No description
CH2: u1 = 0,
/// CH3 [3:3]
/// No description
CH3: u1 = 0,
/// CH4 [4:4]
/// No description
CH4: u1 = 0,
/// CH5 [5:5]
/// No description
CH5: u1 = 0,
/// CH6 [6:6]
/// No description
CH6: u1 = 0,
/// CH7 [7:7]
/// No description
CH7: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Raw Interrupts
pub const INTR = Register(INTR_val).init(base_address + 0xa4);
/// EN
const EN_val = packed struct {
/// CH0 [0:0]
/// No description
CH0: u1 = 0,
/// CH1 [1:1]
/// No description
CH1: u1 = 0,
/// CH2 [2:2]
/// No description
CH2: u1 = 0,
/// CH3 [3:3]
/// No description
CH3: u1 = 0,
/// CH4 [4:4]
/// No description
CH4: u1 = 0,
/// CH5 [5:5]
/// No description
CH5: u1 = 0,
/// CH6 [6:6]
/// No description
CH6: u1 = 0,
/// CH7 [7:7]
/// No description
CH7: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// This register aliases the CSR_EN bits for all channels.\n
pub const EN = Register(EN_val).init(base_address + 0xa0);
/// CH7_TOP
const CH7_TOP_val = packed struct {
/// CH7_TOP [0:15]
/// No description
CH7_TOP: u16 = 65535,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Counter wrap value
pub const CH7_TOP = Register(CH7_TOP_val).init(base_address + 0x9c);
/// CH7_CC
const CH7_CC_val = packed struct {
/// A [0:15]
/// No description
A: u16 = 0,
/// B [16:31]
/// No description
B: u16 = 0,
};
/// Counter compare values
pub const CH7_CC = Register(CH7_CC_val).init(base_address + 0x98);
/// CH7_CTR
const CH7_CTR_val = packed struct {
/// CH7_CTR [0:15]
/// No description
CH7_CTR: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Direct access to the PWM counter
pub const CH7_CTR = Register(CH7_CTR_val).init(base_address + 0x94);
/// CH7_DIV
const CH7_DIV_val = packed struct {
/// FRAC [0:3]
/// No description
FRAC: u4 = 0,
/// INT [4:11]
/// No description
INT: u8 = 1,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// INT and FRAC form a fixed-point fractional number.\n
pub const CH7_DIV = Register(CH7_DIV_val).init(base_address + 0x90);
/// CH7_CSR
const CH7_CSR_val = packed struct {
/// EN [0:0]
/// Enable the PWM channel.
EN: u1 = 0,
/// PH_CORRECT [1:1]
/// 1: Enable phase-correct modulation. 0: Trailing-edge
PH_CORRECT: u1 = 0,
/// A_INV [2:2]
/// Invert output A
A_INV: u1 = 0,
/// B_INV [3:3]
/// Invert output B
B_INV: u1 = 0,
/// DIVMODE [4:5]
/// No description
DIVMODE: u2 = 0,
/// PH_RET [6:6]
/// Retard the phase of the counter by 1 count, while it is running.\n
PH_RET: u1 = 0,
/// PH_ADV [7:7]
/// Advance the phase of the counter by 1 count, while it is running.\n
PH_ADV: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Control and status register
pub const CH7_CSR = Register(CH7_CSR_val).init(base_address + 0x8c);
/// CH6_TOP
const CH6_TOP_val = packed struct {
/// CH6_TOP [0:15]
/// No description
CH6_TOP: u16 = 65535,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Counter wrap value
pub const CH6_TOP = Register(CH6_TOP_val).init(base_address + 0x88);
/// CH6_CC
const CH6_CC_val = packed struct {
/// A [0:15]
/// No description
A: u16 = 0,
/// B [16:31]
/// No description
B: u16 = 0,
};
/// Counter compare values
pub const CH6_CC = Register(CH6_CC_val).init(base_address + 0x84);
/// CH6_CTR
const CH6_CTR_val = packed struct {
/// CH6_CTR [0:15]
/// No description
CH6_CTR: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Direct access to the PWM counter
pub const CH6_CTR = Register(CH6_CTR_val).init(base_address + 0x80);
/// CH6_DIV
const CH6_DIV_val = packed struct {
/// FRAC [0:3]
/// No description
FRAC: u4 = 0,
/// INT [4:11]
/// No description
INT: u8 = 1,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// INT and FRAC form a fixed-point fractional number.\n
pub const CH6_DIV = Register(CH6_DIV_val).init(base_address + 0x7c);
/// CH6_CSR
const CH6_CSR_val = packed struct {
/// EN [0:0]
/// Enable the PWM channel.
EN: u1 = 0,
/// PH_CORRECT [1:1]
/// 1: Enable phase-correct modulation. 0: Trailing-edge
PH_CORRECT: u1 = 0,
/// A_INV [2:2]
/// Invert output A
A_INV: u1 = 0,
/// B_INV [3:3]
/// Invert output B
B_INV: u1 = 0,
/// DIVMODE [4:5]
/// No description
DIVMODE: u2 = 0,
/// PH_RET [6:6]
/// Retard the phase of the counter by 1 count, while it is running.\n
PH_RET: u1 = 0,
/// PH_ADV [7:7]
/// Advance the phase of the counter by 1 count, while it is running.\n
PH_ADV: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Control and status register
pub const CH6_CSR = Register(CH6_CSR_val).init(base_address + 0x78);
/// CH5_TOP
const CH5_TOP_val = packed struct {
/// CH5_TOP [0:15]
/// No description
CH5_TOP: u16 = 65535,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Counter wrap value
pub const CH5_TOP = Register(CH5_TOP_val).init(base_address + 0x74);
/// CH5_CC
const CH5_CC_val = packed struct {
/// A [0:15]
/// No description
A: u16 = 0,
/// B [16:31]
/// No description
B: u16 = 0,
};
/// Counter compare values
pub const CH5_CC = Register(CH5_CC_val).init(base_address + 0x70);
/// CH5_CTR
const CH5_CTR_val = packed struct {
/// CH5_CTR [0:15]
/// No description
CH5_CTR: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Direct access to the PWM counter
pub const CH5_CTR = Register(CH5_CTR_val).init(base_address + 0x6c);
/// CH5_DIV
const CH5_DIV_val = packed struct {
/// FRAC [0:3]
/// No description
FRAC: u4 = 0,
/// INT [4:11]
/// No description
INT: u8 = 1,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// INT and FRAC form a fixed-point fractional number.\n
pub const CH5_DIV = Register(CH5_DIV_val).init(base_address + 0x68);
/// CH5_CSR
const CH5_CSR_val = packed struct {
/// EN [0:0]
/// Enable the PWM channel.
EN: u1 = 0,
/// PH_CORRECT [1:1]
/// 1: Enable phase-correct modulation. 0: Trailing-edge
PH_CORRECT: u1 = 0,
/// A_INV [2:2]
/// Invert output A
A_INV: u1 = 0,
/// B_INV [3:3]
/// Invert output B
B_INV: u1 = 0,
/// DIVMODE [4:5]
/// No description
DIVMODE: u2 = 0,
/// PH_RET [6:6]
/// Retard the phase of the counter by 1 count, while it is running.\n
PH_RET: u1 = 0,
/// PH_ADV [7:7]
/// Advance the phase of the counter by 1 count, while it is running.\n
PH_ADV: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Control and status register
pub const CH5_CSR = Register(CH5_CSR_val).init(base_address + 0x64);
/// CH4_TOP
const CH4_TOP_val = packed struct {
/// CH4_TOP [0:15]
/// No description
CH4_TOP: u16 = 65535,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Counter wrap value
pub const CH4_TOP = Register(CH4_TOP_val).init(base_address + 0x60);
/// CH4_CC
const CH4_CC_val = packed struct {
/// A [0:15]
/// No description
A: u16 = 0,
/// B [16:31]
/// No description
B: u16 = 0,
};
/// Counter compare values
pub const CH4_CC = Register(CH4_CC_val).init(base_address + 0x5c);
/// CH4_CTR
const CH4_CTR_val = packed struct {
/// CH4_CTR [0:15]
/// No description
CH4_CTR: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Direct access to the PWM counter
pub const CH4_CTR = Register(CH4_CTR_val).init(base_address + 0x58);
/// CH4_DIV
const CH4_DIV_val = packed struct {
/// FRAC [0:3]
/// No description
FRAC: u4 = 0,
/// INT [4:11]
/// No description
INT: u8 = 1,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// INT and FRAC form a fixed-point fractional number.\n
pub const CH4_DIV = Register(CH4_DIV_val).init(base_address + 0x54);
/// CH4_CSR
const CH4_CSR_val = packed struct {
/// EN [0:0]
/// Enable the PWM channel.
EN: u1 = 0,
/// PH_CORRECT [1:1]
/// 1: Enable phase-correct modulation. 0: Trailing-edge
PH_CORRECT: u1 = 0,
/// A_INV [2:2]
/// Invert output A
A_INV: u1 = 0,
/// B_INV [3:3]
/// Invert output B
B_INV: u1 = 0,
/// DIVMODE [4:5]
/// No description
DIVMODE: u2 = 0,
/// PH_RET [6:6]
/// Retard the phase of the counter by 1 count, while it is running.\n
PH_RET: u1 = 0,
/// PH_ADV [7:7]
/// Advance the phase of the counter by 1 count, while it is running.\n
PH_ADV: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Control and status register
pub const CH4_CSR = Register(CH4_CSR_val).init(base_address + 0x50);
/// CH3_TOP
const CH3_TOP_val = packed struct {
/// CH3_TOP [0:15]
/// No description
CH3_TOP: u16 = 65535,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Counter wrap value
pub const CH3_TOP = Register(CH3_TOP_val).init(base_address + 0x4c);
/// CH3_CC
const CH3_CC_val = packed struct {
/// A [0:15]
/// No description
A: u16 = 0,
/// B [16:31]
/// No description
B: u16 = 0,
};
/// Counter compare values
pub const CH3_CC = Register(CH3_CC_val).init(base_address + 0x48);
/// CH3_CTR
const CH3_CTR_val = packed struct {
/// CH3_CTR [0:15]
/// No description
CH3_CTR: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Direct access to the PWM counter
pub const CH3_CTR = Register(CH3_CTR_val).init(base_address + 0x44);
/// CH3_DIV
const CH3_DIV_val = packed struct {
/// FRAC [0:3]
/// No description
FRAC: u4 = 0,
/// INT [4:11]
/// No description
INT: u8 = 1,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// INT and FRAC form a fixed-point fractional number.\n
pub const CH3_DIV = Register(CH3_DIV_val).init(base_address + 0x40);
/// CH3_CSR
const CH3_CSR_val = packed struct {
/// EN [0:0]
/// Enable the PWM channel.
EN: u1 = 0,
/// PH_CORRECT [1:1]
/// 1: Enable phase-correct modulation. 0: Trailing-edge
PH_CORRECT: u1 = 0,
/// A_INV [2:2]
/// Invert output A
A_INV: u1 = 0,
/// B_INV [3:3]
/// Invert output B
B_INV: u1 = 0,
/// DIVMODE [4:5]
/// No description
DIVMODE: u2 = 0,
/// PH_RET [6:6]
/// Retard the phase of the counter by 1 count, while it is running.\n
PH_RET: u1 = 0,
/// PH_ADV [7:7]
/// Advance the phase of the counter by 1 count, while it is running.\n
PH_ADV: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Control and status register
pub const CH3_CSR = Register(CH3_CSR_val).init(base_address + 0x3c);
/// CH2_TOP
const CH2_TOP_val = packed struct {
/// CH2_TOP [0:15]
/// No description
CH2_TOP: u16 = 65535,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Counter wrap value
pub const CH2_TOP = Register(CH2_TOP_val).init(base_address + 0x38);
/// CH2_CC
const CH2_CC_val = packed struct {
/// A [0:15]
/// No description
A: u16 = 0,
/// B [16:31]
/// No description
B: u16 = 0,
};
/// Counter compare values
pub const CH2_CC = Register(CH2_CC_val).init(base_address + 0x34);
/// CH2_CTR
const CH2_CTR_val = packed struct {
/// CH2_CTR [0:15]
/// No description
CH2_CTR: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Direct access to the PWM counter
pub const CH2_CTR = Register(CH2_CTR_val).init(base_address + 0x30);
/// CH2_DIV
const CH2_DIV_val = packed struct {
/// FRAC [0:3]
/// No description
FRAC: u4 = 0,
/// INT [4:11]
/// No description
INT: u8 = 1,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// INT and FRAC form a fixed-point fractional number.\n
pub const CH2_DIV = Register(CH2_DIV_val).init(base_address + 0x2c);
/// CH2_CSR
const CH2_CSR_val = packed struct {
/// EN [0:0]
/// Enable the PWM channel.
EN: u1 = 0,
/// PH_CORRECT [1:1]
/// 1: Enable phase-correct modulation. 0: Trailing-edge
PH_CORRECT: u1 = 0,
/// A_INV [2:2]
/// Invert output A
A_INV: u1 = 0,
/// B_INV [3:3]
/// Invert output B
B_INV: u1 = 0,
/// DIVMODE [4:5]
/// No description
DIVMODE: u2 = 0,
/// PH_RET [6:6]
/// Retard the phase of the counter by 1 count, while it is running.\n
PH_RET: u1 = 0,
/// PH_ADV [7:7]
/// Advance the phase of the counter by 1 count, while it is running.\n
PH_ADV: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Control and status register
pub const CH2_CSR = Register(CH2_CSR_val).init(base_address + 0x28);
/// CH1_TOP
const CH1_TOP_val = packed struct {
/// CH1_TOP [0:15]
/// No description
CH1_TOP: u16 = 65535,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Counter wrap value
pub const CH1_TOP = Register(CH1_TOP_val).init(base_address + 0x24);
/// CH1_CC
const CH1_CC_val = packed struct {
/// A [0:15]
/// No description
A: u16 = 0,
/// B [16:31]
/// No description
B: u16 = 0,
};
/// Counter compare values
pub const CH1_CC = Register(CH1_CC_val).init(base_address + 0x20);
/// CH1_CTR
const CH1_CTR_val = packed struct {
/// CH1_CTR [0:15]
/// No description
CH1_CTR: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Direct access to the PWM counter
pub const CH1_CTR = Register(CH1_CTR_val).init(base_address + 0x1c);
/// CH1_DIV
const CH1_DIV_val = packed struct {
/// FRAC [0:3]
/// No description
FRAC: u4 = 0,
/// INT [4:11]
/// No description
INT: u8 = 1,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// INT and FRAC form a fixed-point fractional number.\n
pub const CH1_DIV = Register(CH1_DIV_val).init(base_address + 0x18);
/// CH1_CSR
const CH1_CSR_val = packed struct {
/// EN [0:0]
/// Enable the PWM channel.
EN: u1 = 0,
/// PH_CORRECT [1:1]
/// 1: Enable phase-correct modulation. 0: Trailing-edge
PH_CORRECT: u1 = 0,
/// A_INV [2:2]
/// Invert output A
A_INV: u1 = 0,
/// B_INV [3:3]
/// Invert output B
B_INV: u1 = 0,
/// DIVMODE [4:5]
/// No description
DIVMODE: u2 = 0,
/// PH_RET [6:6]
/// Retard the phase of the counter by 1 count, while it is running.\n
PH_RET: u1 = 0,
/// PH_ADV [7:7]
/// Advance the phase of the counter by 1 count, while it is running.\n
PH_ADV: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Control and status register
pub const CH1_CSR = Register(CH1_CSR_val).init(base_address + 0x14);
/// CH0_TOP
const CH0_TOP_val = packed struct {
/// CH0_TOP [0:15]
/// No description
CH0_TOP: u16 = 65535,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Counter wrap value
pub const CH0_TOP = Register(CH0_TOP_val).init(base_address + 0x10);
/// CH0_CC
const CH0_CC_val = packed struct {
/// A [0:15]
/// No description
A: u16 = 0,
/// B [16:31]
/// No description
B: u16 = 0,
};
/// Counter compare values
pub const CH0_CC = Register(CH0_CC_val).init(base_address + 0xc);
/// CH0_CTR
const CH0_CTR_val = packed struct {
/// CH0_CTR [0:15]
/// No description
CH0_CTR: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Direct access to the PWM counter
pub const CH0_CTR = Register(CH0_CTR_val).init(base_address + 0x8);
/// CH0_DIV
const CH0_DIV_val = packed struct {
/// FRAC [0:3]
/// No description
FRAC: u4 = 0,
/// INT [4:11]
/// No description
INT: u8 = 1,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// INT and FRAC form a fixed-point fractional number.\n
pub const CH0_DIV = Register(CH0_DIV_val).init(base_address + 0x4);
/// CH0_CSR
const CH0_CSR_val = packed struct {
/// EN [0:0]
/// Enable the PWM channel.
EN: u1 = 0,
/// PH_CORRECT [1:1]
/// 1: Enable phase-correct modulation. 0: Trailing-edge
PH_CORRECT: u1 = 0,
/// A_INV [2:2]
/// Invert output A
A_INV: u1 = 0,
/// B_INV [3:3]
/// Invert output B
B_INV: u1 = 0,
/// DIVMODE [4:5]
/// No description
DIVMODE: u2 = 0,
/// PH_RET [6:6]
/// Retard the phase of the counter by 1 count, while it is running.\n
PH_RET: u1 = 0,
/// PH_ADV [7:7]
/// Advance the phase of the counter by 1 count, while it is running.\n
PH_ADV: u1 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Control and status register
pub const CH0_CSR = Register(CH0_CSR_val).init(base_address + 0x0);
};
/// Controls time and alarms\n
pub const TIMER = struct {
const base_address = 0x40054000;
/// INTS
const INTS_val = packed struct {
/// ALARM_0 [0:0]
/// No description
ALARM_0: u1 = 0,
/// ALARM_1 [1:1]
/// No description
ALARM_1: u1 = 0,
/// ALARM_2 [2:2]
/// No description
ALARM_2: u1 = 0,
/// ALARM_3 [3:3]
/// No description
ALARM_3: u1 = 0,
/// unused [4:31]
_unused4: u4 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt status after masking & forcing
pub const INTS = Register(INTS_val).init(base_address + 0x40);
/// INTF
const INTF_val = packed struct {
/// ALARM_0 [0:0]
/// No description
ALARM_0: u1 = 0,
/// ALARM_1 [1:1]
/// No description
ALARM_1: u1 = 0,
/// ALARM_2 [2:2]
/// No description
ALARM_2: u1 = 0,
/// ALARM_3 [3:3]
/// No description
ALARM_3: u1 = 0,
/// unused [4:31]
_unused4: u4 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt Force
pub const INTF = Register(INTF_val).init(base_address + 0x3c);
/// INTE
const INTE_val = packed struct {
/// ALARM_0 [0:0]
/// No description
ALARM_0: u1 = 0,
/// ALARM_1 [1:1]
/// No description
ALARM_1: u1 = 0,
/// ALARM_2 [2:2]
/// No description
ALARM_2: u1 = 0,
/// ALARM_3 [3:3]
/// No description
ALARM_3: u1 = 0,
/// unused [4:31]
_unused4: u4 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt Enable
pub const INTE = Register(INTE_val).init(base_address + 0x38);
/// INTR
const INTR_val = packed struct {
/// ALARM_0 [0:0]
/// No description
ALARM_0: u1 = 0,
/// ALARM_1 [1:1]
/// No description
ALARM_1: u1 = 0,
/// ALARM_2 [2:2]
/// No description
ALARM_2: u1 = 0,
/// ALARM_3 [3:3]
/// No description
ALARM_3: u1 = 0,
/// unused [4:31]
_unused4: u4 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Raw Interrupts
pub const INTR = Register(INTR_val).init(base_address + 0x34);
/// PAUSE
const PAUSE_val = packed struct {
/// PAUSE [0:0]
/// No description
PAUSE: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Set high to pause the timer
pub const PAUSE = Register(PAUSE_val).init(base_address + 0x30);
/// DBGPAUSE
const DBGPAUSE_val = packed struct {
/// unused [0:0]
_unused0: u1 = 1,
/// DBG0 [1:1]
/// Pause when processor 0 is in debug mode
DBG0: u1 = 1,
/// DBG1 [2:2]
/// Pause when processor 1 is in debug mode
DBG1: u1 = 1,
/// unused [3:31]
_unused3: u5 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Set bits high to enable pause when the corresponding debug ports are active
pub const DBGPAUSE = Register(DBGPAUSE_val).init(base_address + 0x2c);
/// TIMERAWL
const TIMERAWL_val = packed struct {
TIMERAWL_0: u8 = 0,
TIMERAWL_1: u8 = 0,
TIMERAWL_2: u8 = 0,
TIMERAWL_3: u8 = 0,
};
/// Raw read from bits 31:0 of time (no side effects)
pub const TIMERAWL = Register(TIMERAWL_val).init(base_address + 0x28);
/// TIMERAWH
const TIMERAWH_val = packed struct {
TIMERAWH_0: u8 = 0,
TIMERAWH_1: u8 = 0,
TIMERAWH_2: u8 = 0,
TIMERAWH_3: u8 = 0,
};
/// Raw read from bits 63:32 of time (no side effects)
pub const TIMERAWH = Register(TIMERAWH_val).init(base_address + 0x24);
/// ARMED
const ARMED_val = packed struct {
/// ARMED [0:3]
/// No description
ARMED: u4 = 0,
/// unused [4:31]
_unused4: u4 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Indicates the armed/disarmed status of each alarm.\n
pub const ARMED = Register(ARMED_val).init(base_address + 0x20);
/// ALARM3
const ALARM3_val = packed struct {
ALARM3_0: u8 = 0,
ALARM3_1: u8 = 0,
ALARM3_2: u8 = 0,
ALARM3_3: u8 = 0,
};
/// Arm alarm 3, and configure the time it will fire.\n
pub const ALARM3 = Register(ALARM3_val).init(base_address + 0x1c);
/// ALARM2
const ALARM2_val = packed struct {
ALARM2_0: u8 = 0,
ALARM2_1: u8 = 0,
ALARM2_2: u8 = 0,
ALARM2_3: u8 = 0,
};
/// Arm alarm 2, and configure the time it will fire.\n
pub const ALARM2 = Register(ALARM2_val).init(base_address + 0x18);
/// ALARM1
const ALARM1_val = packed struct {
ALARM1_0: u8 = 0,
ALARM1_1: u8 = 0,
ALARM1_2: u8 = 0,
ALARM1_3: u8 = 0,
};
/// Arm alarm 1, and configure the time it will fire.\n
pub const ALARM1 = Register(ALARM1_val).init(base_address + 0x14);
/// ALARM0
const ALARM0_val = packed struct {
ALARM0_0: u8 = 0,
ALARM0_1: u8 = 0,
ALARM0_2: u8 = 0,
ALARM0_3: u8 = 0,
};
/// Arm alarm 0, and configure the time it will fire.\n
pub const ALARM0 = Register(ALARM0_val).init(base_address + 0x10);
/// TIMELR
const TIMELR_val = packed struct {
TIMELR_0: u8 = 0,
TIMELR_1: u8 = 0,
TIMELR_2: u8 = 0,
TIMELR_3: u8 = 0,
};
/// Read from bits 31:0 of time
pub const TIMELR = Register(TIMELR_val).init(base_address + 0xc);
/// TIMEHR
const TIMEHR_val = packed struct {
TIMEHR_0: u8 = 0,
TIMEHR_1: u8 = 0,
TIMEHR_2: u8 = 0,
TIMEHR_3: u8 = 0,
};
/// Read from bits 63:32 of time\n
pub const TIMEHR = Register(TIMEHR_val).init(base_address + 0x8);
/// TIMELW
const TIMELW_val = packed struct {
TIMELW_0: u8 = 0,
TIMELW_1: u8 = 0,
TIMELW_2: u8 = 0,
TIMELW_3: u8 = 0,
};
/// Write to bits 31:0 of time\n
pub const TIMELW = Register(TIMELW_val).init(base_address + 0x4);
/// TIMEHW
const TIMEHW_val = packed struct {
TIMEHW_0: u8 = 0,
TIMEHW_1: u8 = 0,
TIMEHW_2: u8 = 0,
TIMEHW_3: u8 = 0,
};
/// Write to bits 63:32 of time\n
pub const TIMEHW = Register(TIMEHW_val).init(base_address + 0x0);
};
/// No description
pub const WATCHDOG = struct {
const base_address = 0x40058000;
/// TICK
const TICK_val = packed struct {
/// CYCLES [0:8]
/// Total number of clk_tick cycles before the next tick.
CYCLES: u9 = 0,
/// ENABLE [9:9]
/// start / stop tick generation
ENABLE: u1 = 1,
/// RUNNING [10:10]
/// Is the tick generator running?
RUNNING: u1 = 0,
/// COUNT [11:19]
/// Count down timer: the remaining number clk_tick cycles before the next tick is generated.
COUNT: u9 = 0,
/// unused [20:31]
_unused20: u4 = 0,
_unused24: u8 = 0,
};
/// Controls the tick generator
pub const TICK = Register(TICK_val).init(base_address + 0x2c);
/// SCRATCH7
const SCRATCH7_val = packed struct {
SCRATCH7_0: u8 = 0,
SCRATCH7_1: u8 = 0,
SCRATCH7_2: u8 = 0,
SCRATCH7_3: u8 = 0,
};
/// Scratch register. Information persists through soft reset of the chip.
pub const SCRATCH7 = Register(SCRATCH7_val).init(base_address + 0x28);
/// SCRATCH6
const SCRATCH6_val = packed struct {
SCRATCH6_0: u8 = 0,
SCRATCH6_1: u8 = 0,
SCRATCH6_2: u8 = 0,
SCRATCH6_3: u8 = 0,
};
/// Scratch register. Information persists through soft reset of the chip.
pub const SCRATCH6 = Register(SCRATCH6_val).init(base_address + 0x24);
/// SCRATCH5
const SCRATCH5_val = packed struct {
SCRATCH5_0: u8 = 0,
SCRATCH5_1: u8 = 0,
SCRATCH5_2: u8 = 0,
SCRATCH5_3: u8 = 0,
};
/// Scratch register. Information persists through soft reset of the chip.
pub const SCRATCH5 = Register(SCRATCH5_val).init(base_address + 0x20);
/// SCRATCH4
const SCRATCH4_val = packed struct {
SCRATCH4_0: u8 = 0,
SCRATCH4_1: u8 = 0,
SCRATCH4_2: u8 = 0,
SCRATCH4_3: u8 = 0,
};
/// Scratch register. Information persists through soft reset of the chip.
pub const SCRATCH4 = Register(SCRATCH4_val).init(base_address + 0x1c);
/// SCRATCH3
const SCRATCH3_val = packed struct {
SCRATCH3_0: u8 = 0,
SCRATCH3_1: u8 = 0,
SCRATCH3_2: u8 = 0,
SCRATCH3_3: u8 = 0,
};
/// Scratch register. Information persists through soft reset of the chip.
pub const SCRATCH3 = Register(SCRATCH3_val).init(base_address + 0x18);
/// SCRATCH2
const SCRATCH2_val = packed struct {
SCRATCH2_0: u8 = 0,
SCRATCH2_1: u8 = 0,
SCRATCH2_2: u8 = 0,
SCRATCH2_3: u8 = 0,
};
/// Scratch register. Information persists through soft reset of the chip.
pub const SCRATCH2 = Register(SCRATCH2_val).init(base_address + 0x14);
/// SCRATCH1
const SCRATCH1_val = packed struct {
SCRATCH1_0: u8 = 0,
SCRATCH1_1: u8 = 0,
SCRATCH1_2: u8 = 0,
SCRATCH1_3: u8 = 0,
};
/// Scratch register. Information persists through soft reset of the chip.
pub const SCRATCH1 = Register(SCRATCH1_val).init(base_address + 0x10);
/// SCRATCH0
const SCRATCH0_val = packed struct {
SCRATCH0_0: u8 = 0,
SCRATCH0_1: u8 = 0,
SCRATCH0_2: u8 = 0,
SCRATCH0_3: u8 = 0,
};
/// Scratch register. Information persists through soft reset of the chip.
pub const SCRATCH0 = Register(SCRATCH0_val).init(base_address + 0xc);
/// REASON
const REASON_val = packed struct {
/// TIMER [0:0]
/// No description
TIMER: u1 = 0,
/// FORCE [1:1]
/// No description
FORCE: u1 = 0,
/// unused [2:31]
_unused2: u6 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Logs the reason for the last reset. Both bits are zero for the case of a hardware reset.
pub const REASON = Register(REASON_val).init(base_address + 0x8);
/// LOAD
const LOAD_val = packed struct {
/// LOAD [0:23]
/// No description
LOAD: u24 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Load the watchdog timer. The maximum setting is 0xffffff which corresponds to 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1).
pub const LOAD = Register(LOAD_val).init(base_address + 0x4);
/// CTRL
const CTRL_val = packed struct {
/// TIME [0:23]
/// Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset will be triggered
TIME: u24 = 0,
/// PAUSE_JTAG [24:24]
/// Pause the watchdog timer when JTAG is accessing the bus fabric
PAUSE_JTAG: u1 = 1,
/// PAUSE_DBG0 [25:25]
/// Pause the watchdog timer when processor 0 is in debug mode
PAUSE_DBG0: u1 = 1,
/// PAUSE_DBG1 [26:26]
/// Pause the watchdog timer when processor 1 is in debug mode
PAUSE_DBG1: u1 = 1,
/// unused [27:29]
_unused27: u3 = 0,
/// ENABLE [30:30]
/// When not enabled the watchdog timer is paused
ENABLE: u1 = 0,
/// TRIGGER [31:31]
/// Trigger a watchdog reset
TRIGGER: u1 = 0,
};
/// Watchdog control\n
pub const CTRL = Register(CTRL_val).init(base_address + 0x0);
};
/// Register block to control RTC
pub const RTC = struct {
const base_address = 0x4005c000;
/// INTS
const INTS_val = packed struct {
/// RTC [0:0]
/// No description
RTC: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt status after masking & forcing
pub const INTS = Register(INTS_val).init(base_address + 0x2c);
/// INTF
const INTF_val = packed struct {
/// RTC [0:0]
/// No description
RTC: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt Force
pub const INTF = Register(INTF_val).init(base_address + 0x28);
/// INTE
const INTE_val = packed struct {
/// RTC [0:0]
/// No description
RTC: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt Enable
pub const INTE = Register(INTE_val).init(base_address + 0x24);
/// INTR
const INTR_val = packed struct {
/// RTC [0:0]
/// No description
RTC: u1 = 0,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Raw Interrupts
pub const INTR = Register(INTR_val).init(base_address + 0x20);
/// RTC_0
const RTC_0_val = packed struct {
/// SEC [0:5]
/// Seconds
SEC: u6 = 0,
/// unused [6:7]
_unused6: u2 = 0,
/// MIN [8:13]
/// Minutes
MIN: u6 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// HOUR [16:20]
/// Hours
HOUR: u5 = 0,
/// unused [21:23]
_unused21: u3 = 0,
/// DOTW [24:26]
/// Day of the week
DOTW: u3 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// RTC register 0\n
pub const RTC_0 = Register(RTC_0_val).init(base_address + 0x1c);
/// RTC_1
const RTC_1_val = packed struct {
/// DAY [0:4]
/// Day of the month (1..31)
DAY: u5 = 0,
/// unused [5:7]
_unused5: u3 = 0,
/// MONTH [8:11]
/// Month (1..12)
MONTH: u4 = 0,
/// YEAR [12:23]
/// Year
YEAR: u12 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// RTC register 1.
pub const RTC_1 = Register(RTC_1_val).init(base_address + 0x18);
/// IRQ_SETUP_1
const IRQ_SETUP_1_val = packed struct {
/// SEC [0:5]
/// Seconds
SEC: u6 = 0,
/// unused [6:7]
_unused6: u2 = 0,
/// MIN [8:13]
/// Minutes
MIN: u6 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// HOUR [16:20]
/// Hours
HOUR: u5 = 0,
/// unused [21:23]
_unused21: u3 = 0,
/// DOTW [24:26]
/// Day of the week
DOTW: u3 = 0,
/// unused [27:27]
_unused27: u1 = 0,
/// SEC_ENA [28:28]
/// Enable second matching
SEC_ENA: u1 = 0,
/// MIN_ENA [29:29]
/// Enable minute matching
MIN_ENA: u1 = 0,
/// HOUR_ENA [30:30]
/// Enable hour matching
HOUR_ENA: u1 = 0,
/// DOTW_ENA [31:31]
/// Enable day of the week matching
DOTW_ENA: u1 = 0,
};
/// Interrupt setup register 1
pub const IRQ_SETUP_1 = Register(IRQ_SETUP_1_val).init(base_address + 0x14);
/// IRQ_SETUP_0
const IRQ_SETUP_0_val = packed struct {
/// DAY [0:4]
/// Day of the month (1..31)
DAY: u5 = 0,
/// unused [5:7]
_unused5: u3 = 0,
/// MONTH [8:11]
/// Month (1..12)
MONTH: u4 = 0,
/// YEAR [12:23]
/// Year
YEAR: u12 = 0,
/// DAY_ENA [24:24]
/// Enable day matching
DAY_ENA: u1 = 0,
/// MONTH_ENA [25:25]
/// Enable month matching
MONTH_ENA: u1 = 0,
/// YEAR_ENA [26:26]
/// Enable year matching
YEAR_ENA: u1 = 0,
/// unused [27:27]
_unused27: u1 = 0,
/// MATCH_ENA [28:28]
/// Global match enable. Don't change any other value while this one is enabled
MATCH_ENA: u1 = 0,
/// MATCH_ACTIVE [29:29]
/// No description
MATCH_ACTIVE: u1 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// Interrupt setup register 0
pub const IRQ_SETUP_0 = Register(IRQ_SETUP_0_val).init(base_address + 0x10);
/// CTRL
const CTRL_val = packed struct {
/// RTC_ENABLE [0:0]
/// Enable RTC
RTC_ENABLE: u1 = 0,
/// RTC_ACTIVE [1:1]
/// RTC enabled (running)
RTC_ACTIVE: u1 = 0,
/// unused [2:3]
_unused2: u2 = 0,
/// LOAD [4:4]
/// Load RTC
LOAD: u1 = 0,
/// unused [5:7]
_unused5: u3 = 0,
/// FORCE_NOTLEAPYEAR [8:8]
/// If set, leapyear is forced off.\n
FORCE_NOTLEAPYEAR: u1 = 0,
/// unused [9:31]
_unused9: u7 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// RTC Control and status
pub const CTRL = Register(CTRL_val).init(base_address + 0xc);
/// SETUP_1
const SETUP_1_val = packed struct {
/// SEC [0:5]
/// Seconds
SEC: u6 = 0,
/// unused [6:7]
_unused6: u2 = 0,
/// MIN [8:13]
/// Minutes
MIN: u6 = 0,
/// unused [14:15]
_unused14: u2 = 0,
/// HOUR [16:20]
/// Hours
HOUR: u5 = 0,
/// unused [21:23]
_unused21: u3 = 0,
/// DOTW [24:26]
/// Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7
DOTW: u3 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// RTC setup register 1
pub const SETUP_1 = Register(SETUP_1_val).init(base_address + 0x8);
/// SETUP_0
const SETUP_0_val = packed struct {
/// DAY [0:4]
/// Day of the month (1..31)
DAY: u5 = 0,
/// unused [5:7]
_unused5: u3 = 0,
/// MONTH [8:11]
/// Month (1..12)
MONTH: u4 = 0,
/// YEAR [12:23]
/// Year
YEAR: u12 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// RTC setup register 0
pub const SETUP_0 = Register(SETUP_0_val).init(base_address + 0x4);
/// CLKDIV_M1
const CLKDIV_M1_val = packed struct {
/// CLKDIV_M1 [0:15]
/// No description
CLKDIV_M1: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Divider minus 1 for the 1 second counter. Safe to change the value when RTC is not enabled.
pub const CLKDIV_M1 = Register(CLKDIV_M1_val).init(base_address + 0x0);
};
/// No description
pub const ROSC = struct {
const base_address = 0x40060000;
/// COUNT
const COUNT_val = packed struct {
/// COUNT [0:7]
/// No description
COUNT: u8 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// A down counter running at the ROSC frequency which counts to zero and stops.\n
pub const COUNT = Register(COUNT_val).init(base_address + 0x20);
/// RANDOMBIT
const RANDOMBIT_val = packed struct {
/// RANDOMBIT [0:0]
/// No description
RANDOMBIT: u1 = 1,
/// unused [1:31]
_unused1: u7 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency
pub const RANDOMBIT = Register(RANDOMBIT_val).init(base_address + 0x1c);
/// STATUS
const STATUS_val = packed struct {
/// unused [0:11]
_unused0: u8 = 0,
_unused8: u4 = 0,
/// ENABLED [12:12]
/// Oscillator is enabled but not necessarily running and stable\n
ENABLED: u1 = 0,
/// unused [13:15]
_unused13: u3 = 0,
/// DIV_RUNNING [16:16]
/// post-divider is running\n
DIV_RUNNING: u1 = 0,
/// unused [17:23]
_unused17: u7 = 0,
/// BADWRITE [24:24]
/// An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT
BADWRITE: u1 = 0,
/// unused [25:30]
_unused25: u6 = 0,
/// STABLE [31:31]
/// Oscillator is running and stable
STABLE: u1 = 0,
};
/// Ring Oscillator Status
pub const STATUS = Register(STATUS_val).init(base_address + 0x18);
/// PHASE
const PHASE_val = packed struct {
/// SHIFT [0:1]
/// phase shift the phase-shifted output by SHIFT input clocks\n
SHIFT: u2 = 0,
/// FLIP [2:2]
/// invert the phase-shifted output\n
FLIP: u1 = 0,
/// ENABLE [3:3]
/// enable the phase-shifted output\n
ENABLE: u1 = 1,
/// PASSWD [4:11]
/// set to 0xaa\n
PASSWD: u8 = 0,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Controls the phase shifted output
pub const PHASE = Register(PHASE_val).init(base_address + 0x14);
/// DIV
const DIV_val = packed struct {
/// DIV [0:11]
/// set to 0xaa0 + div where\n
DIV: u12 = 0,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Controls the output divider
pub const DIV = Register(DIV_val).init(base_address + 0x10);
/// DORMANT
const DORMANT_val = packed struct {
DORMANT_0: u8 = 0,
DORMANT_1: u8 = 0,
DORMANT_2: u8 = 0,
DORMANT_3: u8 = 0,
};
/// Ring Oscillator pause control\n
pub const DORMANT = Register(DORMANT_val).init(base_address + 0xc);
/// FREQB
const FREQB_val = packed struct {
/// DS4 [0:2]
/// Stage 4 drive strength
DS4: u3 = 0,
/// unused [3:3]
_unused3: u1 = 0,
/// DS5 [4:6]
/// Stage 5 drive strength
DS5: u3 = 0,
/// unused [7:7]
_unused7: u1 = 0,
/// DS6 [8:10]
/// Stage 6 drive strength
DS6: u3 = 0,
/// unused [11:11]
_unused11: u1 = 0,
/// DS7 [12:14]
/// Stage 7 drive strength
DS7: u3 = 0,
/// unused [15:15]
_unused15: u1 = 0,
/// PASSWD [16:31]
/// Set to 0x9696 to apply the settings\n
PASSWD: u16 = 0,
};
/// For a detailed description see freqa register
pub const FREQB = Register(FREQB_val).init(base_address + 0x8);
/// FREQA
const FREQA_val = packed struct {
/// DS0 [0:2]
/// Stage 0 drive strength
DS0: u3 = 0,
/// unused [3:3]
_unused3: u1 = 0,
/// DS1 [4:6]
/// Stage 1 drive strength
DS1: u3 = 0,
/// unused [7:7]
_unused7: u1 = 0,
/// DS2 [8:10]
/// Stage 2 drive strength
DS2: u3 = 0,
/// unused [11:11]
_unused11: u1 = 0,
/// DS3 [12:14]
/// Stage 3 drive strength
DS3: u3 = 0,
/// unused [15:15]
_unused15: u1 = 0,
/// PASSWD [16:31]
/// Set to 0x9696 to apply the settings\n
PASSWD: u16 = 0,
};
/// The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage\n
pub const FREQA = Register(FREQA_val).init(base_address + 0x4);
/// CTRL
const CTRL_val = packed struct {
/// FREQ_RANGE [0:11]
/// Controls the number of delay stages in the ROSC ring\n
FREQ_RANGE: u12 = 2720,
/// ENABLE [12:23]
/// On power-up this field is initialised to ENABLE\n
ENABLE: u12 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Ring Oscillator control
pub const CTRL = Register(CTRL_val).init(base_address + 0x0);
};
/// control and status for on-chip voltage regulator and chip level reset subsystem
pub const VREG_AND_CHIP_RESET = struct {
const base_address = 0x40064000;
/// CHIP_RESET
const CHIP_RESET_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// HAD_POR [8:8]
/// Last reset was from the power-on reset or brown-out detection blocks
HAD_POR: u1 = 0,
/// unused [9:15]
_unused9: u7 = 0,
/// HAD_RUN [16:16]
/// Last reset was from the RUN pin
HAD_RUN: u1 = 0,
/// unused [17:19]
_unused17: u3 = 0,
/// HAD_PSM_RESTART [20:20]
/// Last reset was from the debug port
HAD_PSM_RESTART: u1 = 0,
/// unused [21:23]
_unused21: u3 = 0,
/// PSM_RESTART_FLAG [24:24]
/// This is set by psm_restart from the debugger.\n
PSM_RESTART_FLAG: u1 = 0,
/// unused [25:31]
_unused25: u7 = 0,
};
/// Chip reset control and status
pub const CHIP_RESET = Register(CHIP_RESET_val).init(base_address + 0x8);
/// BOD
const BOD_val = packed struct {
/// EN [0:0]
/// enable\n
EN: u1 = 1,
/// unused [1:3]
_unused1: u3 = 0,
/// VSEL [4:7]
/// threshold select\n
VSEL: u4 = 9,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// brown-out detection control
pub const BOD = Register(BOD_val).init(base_address + 0x4);
/// VREG
const VREG_val = packed struct {
/// EN [0:0]
/// enable\n
EN: u1 = 1,
/// HIZ [1:1]
/// high impedance mode select\n
HIZ: u1 = 0,
/// unused [2:3]
_unused2: u2 = 0,
/// VSEL [4:7]
/// output voltage select\n
VSEL: u4 = 11,
/// unused [8:11]
_unused8: u4 = 0,
/// ROK [12:12]
/// regulation status\n
ROK: u1 = 0,
/// unused [13:31]
_unused13: u3 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Voltage regulator control and status
pub const VREG = Register(VREG_val).init(base_address + 0x0);
};
/// Testbench manager. Allows the programmer to know what platform their software is running on.
pub const TBMAN = struct {
const base_address = 0x4006c000;
/// PLATFORM
const PLATFORM_val = packed struct {
/// ASIC [0:0]
/// Indicates the platform is an ASIC
ASIC: u1 = 1,
/// FPGA [1:1]
/// Indicates the platform is an FPGA
FPGA: u1 = 0,
/// unused [2:31]
_unused2: u6 = 1,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Indicates the type of platform in use
pub const PLATFORM = Register(PLATFORM_val).init(base_address + 0x0);
};
/// DMA with separate read and write masters
pub const DMA = struct {
const base_address = 0x50000000;
/// CH11_DBG_TCR
const CH11_DBG_TCR_val = packed struct {
CH11_DBG_TCR_0: u8 = 0,
CH11_DBG_TCR_1: u8 = 0,
CH11_DBG_TCR_2: u8 = 0,
CH11_DBG_TCR_3: u8 = 0,
};
/// Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
pub const CH11_DBG_TCR = Register(CH11_DBG_TCR_val).init(base_address + 0xac4);
/// CH11_DBG_CTDREQ
const CH11_DBG_CTDREQ_val = packed struct {
/// CH11_DBG_CTDREQ [0:5]
/// No description
CH11_DBG_CTDREQ: u6 = 0,
/// unused [6:31]
_unused6: u2 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
pub const CH11_DBG_CTDREQ = Register(CH11_DBG_CTDREQ_val).init(base_address + 0xac0);
/// CH10_DBG_TCR
const CH10_DBG_TCR_val = packed struct {
CH10_DBG_TCR_0: u8 = 0,
CH10_DBG_TCR_1: u8 = 0,
CH10_DBG_TCR_2: u8 = 0,
CH10_DBG_TCR_3: u8 = 0,
};
/// Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
pub const CH10_DBG_TCR = Register(CH10_DBG_TCR_val).init(base_address + 0xa84);
/// CH10_DBG_CTDREQ
const CH10_DBG_CTDREQ_val = packed struct {
/// CH10_DBG_CTDREQ [0:5]
/// No description
CH10_DBG_CTDREQ: u6 = 0,
/// unused [6:31]
_unused6: u2 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
pub const CH10_DBG_CTDREQ = Register(CH10_DBG_CTDREQ_val).init(base_address + 0xa80);
/// CH9_DBG_TCR
const CH9_DBG_TCR_val = packed struct {
CH9_DBG_TCR_0: u8 = 0,
CH9_DBG_TCR_1: u8 = 0,
CH9_DBG_TCR_2: u8 = 0,
CH9_DBG_TCR_3: u8 = 0,
};
/// Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
pub const CH9_DBG_TCR = Register(CH9_DBG_TCR_val).init(base_address + 0xa44);
/// CH9_DBG_CTDREQ
const CH9_DBG_CTDREQ_val = packed struct {
/// CH9_DBG_CTDREQ [0:5]
/// No description
CH9_DBG_CTDREQ: u6 = 0,
/// unused [6:31]
_unused6: u2 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
pub const CH9_DBG_CTDREQ = Register(CH9_DBG_CTDREQ_val).init(base_address + 0xa40);
/// CH8_DBG_TCR
const CH8_DBG_TCR_val = packed struct {
CH8_DBG_TCR_0: u8 = 0,
CH8_DBG_TCR_1: u8 = 0,
CH8_DBG_TCR_2: u8 = 0,
CH8_DBG_TCR_3: u8 = 0,
};
/// Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
pub const CH8_DBG_TCR = Register(CH8_DBG_TCR_val).init(base_address + 0xa04);
/// CH8_DBG_CTDREQ
const CH8_DBG_CTDREQ_val = packed struct {
/// CH8_DBG_CTDREQ [0:5]
/// No description
CH8_DBG_CTDREQ: u6 = 0,
/// unused [6:31]
_unused6: u2 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
pub const CH8_DBG_CTDREQ = Register(CH8_DBG_CTDREQ_val).init(base_address + 0xa00);
/// CH7_DBG_TCR
const CH7_DBG_TCR_val = packed struct {
CH7_DBG_TCR_0: u8 = 0,
CH7_DBG_TCR_1: u8 = 0,
CH7_DBG_TCR_2: u8 = 0,
CH7_DBG_TCR_3: u8 = 0,
};
/// Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
pub const CH7_DBG_TCR = Register(CH7_DBG_TCR_val).init(base_address + 0x9c4);
/// CH7_DBG_CTDREQ
const CH7_DBG_CTDREQ_val = packed struct {
/// CH7_DBG_CTDREQ [0:5]
/// No description
CH7_DBG_CTDREQ: u6 = 0,
/// unused [6:31]
_unused6: u2 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
pub const CH7_DBG_CTDREQ = Register(CH7_DBG_CTDREQ_val).init(base_address + 0x9c0);
/// CH6_DBG_TCR
const CH6_DBG_TCR_val = packed struct {
CH6_DBG_TCR_0: u8 = 0,
CH6_DBG_TCR_1: u8 = 0,
CH6_DBG_TCR_2: u8 = 0,
CH6_DBG_TCR_3: u8 = 0,
};
/// Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
pub const CH6_DBG_TCR = Register(CH6_DBG_TCR_val).init(base_address + 0x984);
/// CH6_DBG_CTDREQ
const CH6_DBG_CTDREQ_val = packed struct {
/// CH6_DBG_CTDREQ [0:5]
/// No description
CH6_DBG_CTDREQ: u6 = 0,
/// unused [6:31]
_unused6: u2 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
pub const CH6_DBG_CTDREQ = Register(CH6_DBG_CTDREQ_val).init(base_address + 0x980);
/// CH5_DBG_TCR
const CH5_DBG_TCR_val = packed struct {
CH5_DBG_TCR_0: u8 = 0,
CH5_DBG_TCR_1: u8 = 0,
CH5_DBG_TCR_2: u8 = 0,
CH5_DBG_TCR_3: u8 = 0,
};
/// Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
pub const CH5_DBG_TCR = Register(CH5_DBG_TCR_val).init(base_address + 0x944);
/// CH5_DBG_CTDREQ
const CH5_DBG_CTDREQ_val = packed struct {
/// CH5_DBG_CTDREQ [0:5]
/// No description
CH5_DBG_CTDREQ: u6 = 0,
/// unused [6:31]
_unused6: u2 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
pub const CH5_DBG_CTDREQ = Register(CH5_DBG_CTDREQ_val).init(base_address + 0x940);
/// CH4_DBG_TCR
const CH4_DBG_TCR_val = packed struct {
CH4_DBG_TCR_0: u8 = 0,
CH4_DBG_TCR_1: u8 = 0,
CH4_DBG_TCR_2: u8 = 0,
CH4_DBG_TCR_3: u8 = 0,
};
/// Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
pub const CH4_DBG_TCR = Register(CH4_DBG_TCR_val).init(base_address + 0x904);
/// CH4_DBG_CTDREQ
const CH4_DBG_CTDREQ_val = packed struct {
/// CH4_DBG_CTDREQ [0:5]
/// No description
CH4_DBG_CTDREQ: u6 = 0,
/// unused [6:31]
_unused6: u2 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
pub const CH4_DBG_CTDREQ = Register(CH4_DBG_CTDREQ_val).init(base_address + 0x900);
/// CH3_DBG_TCR
const CH3_DBG_TCR_val = packed struct {
CH3_DBG_TCR_0: u8 = 0,
CH3_DBG_TCR_1: u8 = 0,
CH3_DBG_TCR_2: u8 = 0,
CH3_DBG_TCR_3: u8 = 0,
};
/// Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
pub const CH3_DBG_TCR = Register(CH3_DBG_TCR_val).init(base_address + 0x8c4);
/// CH3_DBG_CTDREQ
const CH3_DBG_CTDREQ_val = packed struct {
/// CH3_DBG_CTDREQ [0:5]
/// No description
CH3_DBG_CTDREQ: u6 = 0,
/// unused [6:31]
_unused6: u2 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
pub const CH3_DBG_CTDREQ = Register(CH3_DBG_CTDREQ_val).init(base_address + 0x8c0);
/// CH2_DBG_TCR
const CH2_DBG_TCR_val = packed struct {
CH2_DBG_TCR_0: u8 = 0,
CH2_DBG_TCR_1: u8 = 0,
CH2_DBG_TCR_2: u8 = 0,
CH2_DBG_TCR_3: u8 = 0,
};
/// Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
pub const CH2_DBG_TCR = Register(CH2_DBG_TCR_val).init(base_address + 0x884);
/// CH2_DBG_CTDREQ
const CH2_DBG_CTDREQ_val = packed struct {
/// CH2_DBG_CTDREQ [0:5]
/// No description
CH2_DBG_CTDREQ: u6 = 0,
/// unused [6:31]
_unused6: u2 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
pub const CH2_DBG_CTDREQ = Register(CH2_DBG_CTDREQ_val).init(base_address + 0x880);
/// CH1_DBG_TCR
const CH1_DBG_TCR_val = packed struct {
CH1_DBG_TCR_0: u8 = 0,
CH1_DBG_TCR_1: u8 = 0,
CH1_DBG_TCR_2: u8 = 0,
CH1_DBG_TCR_3: u8 = 0,
};
/// Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
pub const CH1_DBG_TCR = Register(CH1_DBG_TCR_val).init(base_address + 0x844);
/// CH1_DBG_CTDREQ
const CH1_DBG_CTDREQ_val = packed struct {
/// CH1_DBG_CTDREQ [0:5]
/// No description
CH1_DBG_CTDREQ: u6 = 0,
/// unused [6:31]
_unused6: u2 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
pub const CH1_DBG_CTDREQ = Register(CH1_DBG_CTDREQ_val).init(base_address + 0x840);
/// CH0_DBG_TCR
const CH0_DBG_TCR_val = packed struct {
CH0_DBG_TCR_0: u8 = 0,
CH0_DBG_TCR_1: u8 = 0,
CH0_DBG_TCR_2: u8 = 0,
CH0_DBG_TCR_3: u8 = 0,
};
/// Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
pub const CH0_DBG_TCR = Register(CH0_DBG_TCR_val).init(base_address + 0x804);
/// CH0_DBG_CTDREQ
const CH0_DBG_CTDREQ_val = packed struct {
/// CH0_DBG_CTDREQ [0:5]
/// No description
CH0_DBG_CTDREQ: u6 = 0,
/// unused [6:31]
_unused6: u2 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
pub const CH0_DBG_CTDREQ = Register(CH0_DBG_CTDREQ_val).init(base_address + 0x800);
/// N_CHANNELS
const N_CHANNELS_val = packed struct {
/// N_CHANNELS [0:4]
/// No description
N_CHANNELS: u5 = 0,
/// unused [5:31]
_unused5: u3 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area.
pub const N_CHANNELS = Register(N_CHANNELS_val).init(base_address + 0x448);
/// CHAN_ABORT
const CHAN_ABORT_val = packed struct {
/// CHAN_ABORT [0:15]
/// Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs.\n\n
CHAN_ABORT: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Abort an in-progress transfer sequence on one or more channels
pub const CHAN_ABORT = Register(CHAN_ABORT_val).init(base_address + 0x444);
/// FIFO_LEVELS
const FIFO_LEVELS_val = packed struct {
/// TDF_LVL [0:7]
/// Current Transfer-Data-FIFO fill level
TDF_LVL: u8 = 0,
/// WAF_LVL [8:15]
/// Current Write-Address-FIFO fill level
WAF_LVL: u8 = 0,
/// RAF_LVL [16:23]
/// Current Read-Address-FIFO fill level
RAF_LVL: u8 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Debug RAF, WAF, TDF levels
pub const FIFO_LEVELS = Register(FIFO_LEVELS_val).init(base_address + 0x440);
/// SNIFF_DATA
const SNIFF_DATA_val = packed struct {
SNIFF_DATA_0: u8 = 0,
SNIFF_DATA_1: u8 = 0,
SNIFF_DATA_2: u8 = 0,
SNIFF_DATA_3: u8 = 0,
};
/// Data accumulator for sniff hardware\n
pub const SNIFF_DATA = Register(SNIFF_DATA_val).init(base_address + 0x438);
/// SNIFF_CTRL
const SNIFF_CTRL_val = packed struct {
/// EN [0:0]
/// Enable sniffer
EN: u1 = 0,
/// DMACH [1:4]
/// DMA channel for Sniffer to observe
DMACH: u4 = 0,
/// CALC [5:8]
/// No description
CALC: u4 = 0,
/// BSWAP [9:9]
/// Locally perform a byte reverse on the sniffed data, before feeding into checksum.\n\n
BSWAP: u1 = 0,
/// OUT_REV [10:10]
/// If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.
OUT_REV: u1 = 0,
/// OUT_INV [11:11]
/// If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.
OUT_INV: u1 = 0,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Sniffer Control
pub const SNIFF_CTRL = Register(SNIFF_CTRL_val).init(base_address + 0x434);
/// MULTI_CHAN_TRIGGER
const MULTI_CHAN_TRIGGER_val = packed struct {
/// MULTI_CHAN_TRIGGER [0:15]
/// Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy.
MULTI_CHAN_TRIGGER: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Trigger one or more channels simultaneously
pub const MULTI_CHAN_TRIGGER = Register(MULTI_CHAN_TRIGGER_val).init(base_address + 0x430);
/// TIMER3
const TIMER3_val = packed struct {
/// Y [0:15]
/// Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.
Y: u16 = 0,
/// X [16:31]
/// Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.
X: u16 = 0,
};
/// Pacing (X/Y) Fractional Timer\n
pub const TIMER3 = Register(TIMER3_val).init(base_address + 0x42c);
/// TIMER2
const TIMER2_val = packed struct {
/// Y [0:15]
/// Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.
Y: u16 = 0,
/// X [16:31]
/// Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.
X: u16 = 0,
};
/// Pacing (X/Y) Fractional Timer\n
pub const TIMER2 = Register(TIMER2_val).init(base_address + 0x428);
/// TIMER1
const TIMER1_val = packed struct {
/// Y [0:15]
/// Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.
Y: u16 = 0,
/// X [16:31]
/// Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.
X: u16 = 0,
};
/// Pacing (X/Y) Fractional Timer\n
pub const TIMER1 = Register(TIMER1_val).init(base_address + 0x424);
/// TIMER0
const TIMER0_val = packed struct {
/// Y [0:15]
/// Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.
Y: u16 = 0,
/// X [16:31]
/// Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.
X: u16 = 0,
};
/// Pacing (X/Y) Fractional Timer\n
pub const TIMER0 = Register(TIMER0_val).init(base_address + 0x420);
/// INTS1
const INTS1_val = packed struct {
/// INTS1 [0:15]
/// Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted.\n
INTS1: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt Status (masked) for IRQ 1
pub const INTS1 = Register(INTS1_val).init(base_address + 0x41c);
/// INTF1
const INTF1_val = packed struct {
/// INTF1 [0:15]
/// Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared.
INTF1: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Force Interrupts for IRQ 1
pub const INTF1 = Register(INTF1_val).init(base_address + 0x418);
/// INTE1
const INTE1_val = packed struct {
/// INTE1 [0:15]
/// Set bit n to pass interrupts from channel n to DMA IRQ 1.
INTE1: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt Enables for IRQ 1
pub const INTE1 = Register(INTE1_val).init(base_address + 0x414);
/// INTS0
const INTS0_val = packed struct {
/// INTS0 [0:15]
/// Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted.\n
INTS0: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt Status for IRQ 0
pub const INTS0 = Register(INTS0_val).init(base_address + 0x40c);
/// INTF0
const INTF0_val = packed struct {
/// INTF0 [0:15]
/// Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared.
INTF0: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Force Interrupts
pub const INTF0 = Register(INTF0_val).init(base_address + 0x408);
/// INTE0
const INTE0_val = packed struct {
/// INTE0 [0:15]
/// Set bit n to pass interrupts from channel n to DMA IRQ 0.
INTE0: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt Enables for IRQ 0
pub const INTE0 = Register(INTE0_val).init(base_address + 0x404);
/// INTR
const INTR_val = packed struct {
/// INTR [0:15]
/// Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1.\n\n
INTR: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt Status (raw)
pub const INTR = Register(INTR_val).init(base_address + 0x400);
/// CH11_AL3_READ_ADDR_TRIG
const CH11_AL3_READ_ADDR_TRIG_val = packed struct {
CH11_AL3_READ_ADDR_TRIG_0: u8 = 0,
CH11_AL3_READ_ADDR_TRIG_1: u8 = 0,
CH11_AL3_READ_ADDR_TRIG_2: u8 = 0,
CH11_AL3_READ_ADDR_TRIG_3: u8 = 0,
};
/// Alias for channel 11 READ_ADDR register\n
pub const CH11_AL3_READ_ADDR_TRIG = Register(CH11_AL3_READ_ADDR_TRIG_val).init(base_address + 0x2fc);
/// CH11_AL3_TRANS_COUNT
const CH11_AL3_TRANS_COUNT_val = packed struct {
CH11_AL3_TRANS_COUNT_0: u8 = 0,
CH11_AL3_TRANS_COUNT_1: u8 = 0,
CH11_AL3_TRANS_COUNT_2: u8 = 0,
CH11_AL3_TRANS_COUNT_3: u8 = 0,
};
/// Alias for channel 11 TRANS_COUNT register
pub const CH11_AL3_TRANS_COUNT = Register(CH11_AL3_TRANS_COUNT_val).init(base_address + 0x2f8);
/// CH11_AL3_WRITE_ADDR
const CH11_AL3_WRITE_ADDR_val = packed struct {
CH11_AL3_WRITE_ADDR_0: u8 = 0,
CH11_AL3_WRITE_ADDR_1: u8 = 0,
CH11_AL3_WRITE_ADDR_2: u8 = 0,
CH11_AL3_WRITE_ADDR_3: u8 = 0,
};
/// Alias for channel 11 WRITE_ADDR register
pub const CH11_AL3_WRITE_ADDR = Register(CH11_AL3_WRITE_ADDR_val).init(base_address + 0x2f4);
/// CH11_AL3_CTRL
const CH11_AL3_CTRL_val = packed struct {
CH11_AL3_CTRL_0: u8 = 0,
CH11_AL3_CTRL_1: u8 = 0,
CH11_AL3_CTRL_2: u8 = 0,
CH11_AL3_CTRL_3: u8 = 0,
};
/// Alias for channel 11 CTRL register
pub const CH11_AL3_CTRL = Register(CH11_AL3_CTRL_val).init(base_address + 0x2f0);
/// CH11_AL2_WRITE_ADDR_TRIG
const CH11_AL2_WRITE_ADDR_TRIG_val = packed struct {
CH11_AL2_WRITE_ADDR_TRIG_0: u8 = 0,
CH11_AL2_WRITE_ADDR_TRIG_1: u8 = 0,
CH11_AL2_WRITE_ADDR_TRIG_2: u8 = 0,
CH11_AL2_WRITE_ADDR_TRIG_3: u8 = 0,
};
/// Alias for channel 11 WRITE_ADDR register\n
pub const CH11_AL2_WRITE_ADDR_TRIG = Register(CH11_AL2_WRITE_ADDR_TRIG_val).init(base_address + 0x2ec);
/// CH11_AL2_READ_ADDR
const CH11_AL2_READ_ADDR_val = packed struct {
CH11_AL2_READ_ADDR_0: u8 = 0,
CH11_AL2_READ_ADDR_1: u8 = 0,
CH11_AL2_READ_ADDR_2: u8 = 0,
CH11_AL2_READ_ADDR_3: u8 = 0,
};
/// Alias for channel 11 READ_ADDR register
pub const CH11_AL2_READ_ADDR = Register(CH11_AL2_READ_ADDR_val).init(base_address + 0x2e8);
/// CH11_AL2_TRANS_COUNT
const CH11_AL2_TRANS_COUNT_val = packed struct {
CH11_AL2_TRANS_COUNT_0: u8 = 0,
CH11_AL2_TRANS_COUNT_1: u8 = 0,
CH11_AL2_TRANS_COUNT_2: u8 = 0,
CH11_AL2_TRANS_COUNT_3: u8 = 0,
};
/// Alias for channel 11 TRANS_COUNT register
pub const CH11_AL2_TRANS_COUNT = Register(CH11_AL2_TRANS_COUNT_val).init(base_address + 0x2e4);
/// CH11_AL2_CTRL
const CH11_AL2_CTRL_val = packed struct {
CH11_AL2_CTRL_0: u8 = 0,
CH11_AL2_CTRL_1: u8 = 0,
CH11_AL2_CTRL_2: u8 = 0,
CH11_AL2_CTRL_3: u8 = 0,
};
/// Alias for channel 11 CTRL register
pub const CH11_AL2_CTRL = Register(CH11_AL2_CTRL_val).init(base_address + 0x2e0);
/// CH11_AL1_TRANS_COUNT_TRIG
const CH11_AL1_TRANS_COUNT_TRIG_val = packed struct {
CH11_AL1_TRANS_COUNT_TRIG_0: u8 = 0,
CH11_AL1_TRANS_COUNT_TRIG_1: u8 = 0,
CH11_AL1_TRANS_COUNT_TRIG_2: u8 = 0,
CH11_AL1_TRANS_COUNT_TRIG_3: u8 = 0,
};
/// Alias for channel 11 TRANS_COUNT register\n
pub const CH11_AL1_TRANS_COUNT_TRIG = Register(CH11_AL1_TRANS_COUNT_TRIG_val).init(base_address + 0x2dc);
/// CH11_AL1_WRITE_ADDR
const CH11_AL1_WRITE_ADDR_val = packed struct {
CH11_AL1_WRITE_ADDR_0: u8 = 0,
CH11_AL1_WRITE_ADDR_1: u8 = 0,
CH11_AL1_WRITE_ADDR_2: u8 = 0,
CH11_AL1_WRITE_ADDR_3: u8 = 0,
};
/// Alias for channel 11 WRITE_ADDR register
pub const CH11_AL1_WRITE_ADDR = Register(CH11_AL1_WRITE_ADDR_val).init(base_address + 0x2d8);
/// CH11_AL1_READ_ADDR
const CH11_AL1_READ_ADDR_val = packed struct {
CH11_AL1_READ_ADDR_0: u8 = 0,
CH11_AL1_READ_ADDR_1: u8 = 0,
CH11_AL1_READ_ADDR_2: u8 = 0,
CH11_AL1_READ_ADDR_3: u8 = 0,
};
/// Alias for channel 11 READ_ADDR register
pub const CH11_AL1_READ_ADDR = Register(CH11_AL1_READ_ADDR_val).init(base_address + 0x2d4);
/// CH11_AL1_CTRL
const CH11_AL1_CTRL_val = packed struct {
CH11_AL1_CTRL_0: u8 = 0,
CH11_AL1_CTRL_1: u8 = 0,
CH11_AL1_CTRL_2: u8 = 0,
CH11_AL1_CTRL_3: u8 = 0,
};
/// Alias for channel 11 CTRL register
pub const CH11_AL1_CTRL = Register(CH11_AL1_CTRL_val).init(base_address + 0x2d0);
/// CH11_CTRL_TRIG
const CH11_CTRL_TRIG_val = packed struct {
/// EN [0:0]
/// DMA Channel Enable.\n
EN: u1 = 0,
/// HIGH_PRIORITY [1:1]
/// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
HIGH_PRIORITY: u1 = 0,
/// DATA_SIZE [2:3]
/// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
DATA_SIZE: u2 = 0,
/// INCR_READ [4:4]
/// If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
INCR_READ: u1 = 0,
/// INCR_WRITE [5:5]
/// If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
INCR_WRITE: u1 = 0,
/// RING_SIZE [6:9]
/// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
RING_SIZE: u4 = 0,
/// RING_SEL [10:10]
/// Select whether RING_SIZE applies to read or write addresses.\n
RING_SEL: u1 = 0,
/// CHAIN_TO [11:14]
/// When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n
CHAIN_TO: u4 = 11,
/// TREQ_SEL [15:20]
/// Select a Transfer Request signal.\n
TREQ_SEL: u6 = 0,
/// IRQ_QUIET [21:21]
/// In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
IRQ_QUIET: u1 = 0,
/// BSWAP [22:22]
/// Apply byte-swap transformation to DMA data.\n
BSWAP: u1 = 0,
/// SNIFF_EN [23:23]
/// If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
SNIFF_EN: u1 = 0,
/// BUSY [24:24]
/// This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
BUSY: u1 = 0,
/// unused [25:28]
_unused25: u4 = 0,
/// WRITE_ERROR [29:29]
/// If 1, the channel received a write bus error. Write one to clear.\n
WRITE_ERROR: u1 = 0,
/// READ_ERROR [30:30]
/// If 1, the channel received a read bus error. Write one to clear.\n
READ_ERROR: u1 = 0,
/// AHB_ERROR [31:31]
/// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
AHB_ERROR: u1 = 0,
};
/// DMA Channel 11 Control and Status
pub const CH11_CTRL_TRIG = Register(CH11_CTRL_TRIG_val).init(base_address + 0x2cc);
/// CH11_TRANS_COUNT
const CH11_TRANS_COUNT_val = packed struct {
CH11_TRANS_COUNT_0: u8 = 0,
CH11_TRANS_COUNT_1: u8 = 0,
CH11_TRANS_COUNT_2: u8 = 0,
CH11_TRANS_COUNT_3: u8 = 0,
};
/// DMA Channel 11 Transfer Count\n
pub const CH11_TRANS_COUNT = Register(CH11_TRANS_COUNT_val).init(base_address + 0x2c8);
/// CH11_WRITE_ADDR
const CH11_WRITE_ADDR_val = packed struct {
CH11_WRITE_ADDR_0: u8 = 0,
CH11_WRITE_ADDR_1: u8 = 0,
CH11_WRITE_ADDR_2: u8 = 0,
CH11_WRITE_ADDR_3: u8 = 0,
};
/// DMA Channel 11 Write Address pointer\n
pub const CH11_WRITE_ADDR = Register(CH11_WRITE_ADDR_val).init(base_address + 0x2c4);
/// CH11_READ_ADDR
const CH11_READ_ADDR_val = packed struct {
CH11_READ_ADDR_0: u8 = 0,
CH11_READ_ADDR_1: u8 = 0,
CH11_READ_ADDR_2: u8 = 0,
CH11_READ_ADDR_3: u8 = 0,
};
/// DMA Channel 11 Read Address pointer\n
pub const CH11_READ_ADDR = Register(CH11_READ_ADDR_val).init(base_address + 0x2c0);
/// CH10_AL3_READ_ADDR_TRIG
const CH10_AL3_READ_ADDR_TRIG_val = packed struct {
CH10_AL3_READ_ADDR_TRIG_0: u8 = 0,
CH10_AL3_READ_ADDR_TRIG_1: u8 = 0,
CH10_AL3_READ_ADDR_TRIG_2: u8 = 0,
CH10_AL3_READ_ADDR_TRIG_3: u8 = 0,
};
/// Alias for channel 10 READ_ADDR register\n
pub const CH10_AL3_READ_ADDR_TRIG = Register(CH10_AL3_READ_ADDR_TRIG_val).init(base_address + 0x2bc);
/// CH10_AL3_TRANS_COUNT
const CH10_AL3_TRANS_COUNT_val = packed struct {
CH10_AL3_TRANS_COUNT_0: u8 = 0,
CH10_AL3_TRANS_COUNT_1: u8 = 0,
CH10_AL3_TRANS_COUNT_2: u8 = 0,
CH10_AL3_TRANS_COUNT_3: u8 = 0,
};
/// Alias for channel 10 TRANS_COUNT register
pub const CH10_AL3_TRANS_COUNT = Register(CH10_AL3_TRANS_COUNT_val).init(base_address + 0x2b8);
/// CH10_AL3_WRITE_ADDR
const CH10_AL3_WRITE_ADDR_val = packed struct {
CH10_AL3_WRITE_ADDR_0: u8 = 0,
CH10_AL3_WRITE_ADDR_1: u8 = 0,
CH10_AL3_WRITE_ADDR_2: u8 = 0,
CH10_AL3_WRITE_ADDR_3: u8 = 0,
};
/// Alias for channel 10 WRITE_ADDR register
pub const CH10_AL3_WRITE_ADDR = Register(CH10_AL3_WRITE_ADDR_val).init(base_address + 0x2b4);
/// CH10_AL3_CTRL
const CH10_AL3_CTRL_val = packed struct {
CH10_AL3_CTRL_0: u8 = 0,
CH10_AL3_CTRL_1: u8 = 0,
CH10_AL3_CTRL_2: u8 = 0,
CH10_AL3_CTRL_3: u8 = 0,
};
/// Alias for channel 10 CTRL register
pub const CH10_AL3_CTRL = Register(CH10_AL3_CTRL_val).init(base_address + 0x2b0);
/// CH10_AL2_WRITE_ADDR_TRIG
const CH10_AL2_WRITE_ADDR_TRIG_val = packed struct {
CH10_AL2_WRITE_ADDR_TRIG_0: u8 = 0,
CH10_AL2_WRITE_ADDR_TRIG_1: u8 = 0,
CH10_AL2_WRITE_ADDR_TRIG_2: u8 = 0,
CH10_AL2_WRITE_ADDR_TRIG_3: u8 = 0,
};
/// Alias for channel 10 WRITE_ADDR register\n
pub const CH10_AL2_WRITE_ADDR_TRIG = Register(CH10_AL2_WRITE_ADDR_TRIG_val).init(base_address + 0x2ac);
/// CH10_AL2_READ_ADDR
const CH10_AL2_READ_ADDR_val = packed struct {
CH10_AL2_READ_ADDR_0: u8 = 0,
CH10_AL2_READ_ADDR_1: u8 = 0,
CH10_AL2_READ_ADDR_2: u8 = 0,
CH10_AL2_READ_ADDR_3: u8 = 0,
};
/// Alias for channel 10 READ_ADDR register
pub const CH10_AL2_READ_ADDR = Register(CH10_AL2_READ_ADDR_val).init(base_address + 0x2a8);
/// CH10_AL2_TRANS_COUNT
const CH10_AL2_TRANS_COUNT_val = packed struct {
CH10_AL2_TRANS_COUNT_0: u8 = 0,
CH10_AL2_TRANS_COUNT_1: u8 = 0,
CH10_AL2_TRANS_COUNT_2: u8 = 0,
CH10_AL2_TRANS_COUNT_3: u8 = 0,
};
/// Alias for channel 10 TRANS_COUNT register
pub const CH10_AL2_TRANS_COUNT = Register(CH10_AL2_TRANS_COUNT_val).init(base_address + 0x2a4);
/// CH10_AL2_CTRL
const CH10_AL2_CTRL_val = packed struct {
CH10_AL2_CTRL_0: u8 = 0,
CH10_AL2_CTRL_1: u8 = 0,
CH10_AL2_CTRL_2: u8 = 0,
CH10_AL2_CTRL_3: u8 = 0,
};
/// Alias for channel 10 CTRL register
pub const CH10_AL2_CTRL = Register(CH10_AL2_CTRL_val).init(base_address + 0x2a0);
/// CH10_AL1_TRANS_COUNT_TRIG
const CH10_AL1_TRANS_COUNT_TRIG_val = packed struct {
CH10_AL1_TRANS_COUNT_TRIG_0: u8 = 0,
CH10_AL1_TRANS_COUNT_TRIG_1: u8 = 0,
CH10_AL1_TRANS_COUNT_TRIG_2: u8 = 0,
CH10_AL1_TRANS_COUNT_TRIG_3: u8 = 0,
};
/// Alias for channel 10 TRANS_COUNT register\n
pub const CH10_AL1_TRANS_COUNT_TRIG = Register(CH10_AL1_TRANS_COUNT_TRIG_val).init(base_address + 0x29c);
/// CH10_AL1_WRITE_ADDR
const CH10_AL1_WRITE_ADDR_val = packed struct {
CH10_AL1_WRITE_ADDR_0: u8 = 0,
CH10_AL1_WRITE_ADDR_1: u8 = 0,
CH10_AL1_WRITE_ADDR_2: u8 = 0,
CH10_AL1_WRITE_ADDR_3: u8 = 0,
};
/// Alias for channel 10 WRITE_ADDR register
pub const CH10_AL1_WRITE_ADDR = Register(CH10_AL1_WRITE_ADDR_val).init(base_address + 0x298);
/// CH10_AL1_READ_ADDR
const CH10_AL1_READ_ADDR_val = packed struct {
CH10_AL1_READ_ADDR_0: u8 = 0,
CH10_AL1_READ_ADDR_1: u8 = 0,
CH10_AL1_READ_ADDR_2: u8 = 0,
CH10_AL1_READ_ADDR_3: u8 = 0,
};
/// Alias for channel 10 READ_ADDR register
pub const CH10_AL1_READ_ADDR = Register(CH10_AL1_READ_ADDR_val).init(base_address + 0x294);
/// CH10_AL1_CTRL
const CH10_AL1_CTRL_val = packed struct {
CH10_AL1_CTRL_0: u8 = 0,
CH10_AL1_CTRL_1: u8 = 0,
CH10_AL1_CTRL_2: u8 = 0,
CH10_AL1_CTRL_3: u8 = 0,
};
/// Alias for channel 10 CTRL register
pub const CH10_AL1_CTRL = Register(CH10_AL1_CTRL_val).init(base_address + 0x290);
/// CH10_CTRL_TRIG
const CH10_CTRL_TRIG_val = packed struct {
/// EN [0:0]
/// DMA Channel Enable.\n
EN: u1 = 0,
/// HIGH_PRIORITY [1:1]
/// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
HIGH_PRIORITY: u1 = 0,
/// DATA_SIZE [2:3]
/// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
DATA_SIZE: u2 = 0,
/// INCR_READ [4:4]
/// If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
INCR_READ: u1 = 0,
/// INCR_WRITE [5:5]
/// If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
INCR_WRITE: u1 = 0,
/// RING_SIZE [6:9]
/// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
RING_SIZE: u4 = 0,
/// RING_SEL [10:10]
/// Select whether RING_SIZE applies to read or write addresses.\n
RING_SEL: u1 = 0,
/// CHAIN_TO [11:14]
/// When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n
CHAIN_TO: u4 = 10,
/// TREQ_SEL [15:20]
/// Select a Transfer Request signal.\n
TREQ_SEL: u6 = 0,
/// IRQ_QUIET [21:21]
/// In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
IRQ_QUIET: u1 = 0,
/// BSWAP [22:22]
/// Apply byte-swap transformation to DMA data.\n
BSWAP: u1 = 0,
/// SNIFF_EN [23:23]
/// If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
SNIFF_EN: u1 = 0,
/// BUSY [24:24]
/// This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
BUSY: u1 = 0,
/// unused [25:28]
_unused25: u4 = 0,
/// WRITE_ERROR [29:29]
/// If 1, the channel received a write bus error. Write one to clear.\n
WRITE_ERROR: u1 = 0,
/// READ_ERROR [30:30]
/// If 1, the channel received a read bus error. Write one to clear.\n
READ_ERROR: u1 = 0,
/// AHB_ERROR [31:31]
/// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
AHB_ERROR: u1 = 0,
};
/// DMA Channel 10 Control and Status
pub const CH10_CTRL_TRIG = Register(CH10_CTRL_TRIG_val).init(base_address + 0x28c);
/// CH10_TRANS_COUNT
const CH10_TRANS_COUNT_val = packed struct {
CH10_TRANS_COUNT_0: u8 = 0,
CH10_TRANS_COUNT_1: u8 = 0,
CH10_TRANS_COUNT_2: u8 = 0,
CH10_TRANS_COUNT_3: u8 = 0,
};
/// DMA Channel 10 Transfer Count\n
pub const CH10_TRANS_COUNT = Register(CH10_TRANS_COUNT_val).init(base_address + 0x288);
/// CH10_WRITE_ADDR
const CH10_WRITE_ADDR_val = packed struct {
CH10_WRITE_ADDR_0: u8 = 0,
CH10_WRITE_ADDR_1: u8 = 0,
CH10_WRITE_ADDR_2: u8 = 0,
CH10_WRITE_ADDR_3: u8 = 0,
};
/// DMA Channel 10 Write Address pointer\n
pub const CH10_WRITE_ADDR = Register(CH10_WRITE_ADDR_val).init(base_address + 0x284);
/// CH10_READ_ADDR
const CH10_READ_ADDR_val = packed struct {
CH10_READ_ADDR_0: u8 = 0,
CH10_READ_ADDR_1: u8 = 0,
CH10_READ_ADDR_2: u8 = 0,
CH10_READ_ADDR_3: u8 = 0,
};
/// DMA Channel 10 Read Address pointer\n
pub const CH10_READ_ADDR = Register(CH10_READ_ADDR_val).init(base_address + 0x280);
/// CH9_AL3_READ_ADDR_TRIG
const CH9_AL3_READ_ADDR_TRIG_val = packed struct {
CH9_AL3_READ_ADDR_TRIG_0: u8 = 0,
CH9_AL3_READ_ADDR_TRIG_1: u8 = 0,
CH9_AL3_READ_ADDR_TRIG_2: u8 = 0,
CH9_AL3_READ_ADDR_TRIG_3: u8 = 0,
};
/// Alias for channel 9 READ_ADDR register\n
pub const CH9_AL3_READ_ADDR_TRIG = Register(CH9_AL3_READ_ADDR_TRIG_val).init(base_address + 0x27c);
/// CH9_AL3_TRANS_COUNT
const CH9_AL3_TRANS_COUNT_val = packed struct {
CH9_AL3_TRANS_COUNT_0: u8 = 0,
CH9_AL3_TRANS_COUNT_1: u8 = 0,
CH9_AL3_TRANS_COUNT_2: u8 = 0,
CH9_AL3_TRANS_COUNT_3: u8 = 0,
};
/// Alias for channel 9 TRANS_COUNT register
pub const CH9_AL3_TRANS_COUNT = Register(CH9_AL3_TRANS_COUNT_val).init(base_address + 0x278);
/// CH9_AL3_WRITE_ADDR
const CH9_AL3_WRITE_ADDR_val = packed struct {
CH9_AL3_WRITE_ADDR_0: u8 = 0,
CH9_AL3_WRITE_ADDR_1: u8 = 0,
CH9_AL3_WRITE_ADDR_2: u8 = 0,
CH9_AL3_WRITE_ADDR_3: u8 = 0,
};
/// Alias for channel 9 WRITE_ADDR register
pub const CH9_AL3_WRITE_ADDR = Register(CH9_AL3_WRITE_ADDR_val).init(base_address + 0x274);
/// CH9_AL3_CTRL
const CH9_AL3_CTRL_val = packed struct {
CH9_AL3_CTRL_0: u8 = 0,
CH9_AL3_CTRL_1: u8 = 0,
CH9_AL3_CTRL_2: u8 = 0,
CH9_AL3_CTRL_3: u8 = 0,
};
/// Alias for channel 9 CTRL register
pub const CH9_AL3_CTRL = Register(CH9_AL3_CTRL_val).init(base_address + 0x270);
/// CH9_AL2_WRITE_ADDR_TRIG
const CH9_AL2_WRITE_ADDR_TRIG_val = packed struct {
CH9_AL2_WRITE_ADDR_TRIG_0: u8 = 0,
CH9_AL2_WRITE_ADDR_TRIG_1: u8 = 0,
CH9_AL2_WRITE_ADDR_TRIG_2: u8 = 0,
CH9_AL2_WRITE_ADDR_TRIG_3: u8 = 0,
};
/// Alias for channel 9 WRITE_ADDR register\n
pub const CH9_AL2_WRITE_ADDR_TRIG = Register(CH9_AL2_WRITE_ADDR_TRIG_val).init(base_address + 0x26c);
/// CH9_AL2_READ_ADDR
const CH9_AL2_READ_ADDR_val = packed struct {
CH9_AL2_READ_ADDR_0: u8 = 0,
CH9_AL2_READ_ADDR_1: u8 = 0,
CH9_AL2_READ_ADDR_2: u8 = 0,
CH9_AL2_READ_ADDR_3: u8 = 0,
};
/// Alias for channel 9 READ_ADDR register
pub const CH9_AL2_READ_ADDR = Register(CH9_AL2_READ_ADDR_val).init(base_address + 0x268);
/// CH9_AL2_TRANS_COUNT
const CH9_AL2_TRANS_COUNT_val = packed struct {
CH9_AL2_TRANS_COUNT_0: u8 = 0,
CH9_AL2_TRANS_COUNT_1: u8 = 0,
CH9_AL2_TRANS_COUNT_2: u8 = 0,
CH9_AL2_TRANS_COUNT_3: u8 = 0,
};
/// Alias for channel 9 TRANS_COUNT register
pub const CH9_AL2_TRANS_COUNT = Register(CH9_AL2_TRANS_COUNT_val).init(base_address + 0x264);
/// CH9_AL2_CTRL
const CH9_AL2_CTRL_val = packed struct {
CH9_AL2_CTRL_0: u8 = 0,
CH9_AL2_CTRL_1: u8 = 0,
CH9_AL2_CTRL_2: u8 = 0,
CH9_AL2_CTRL_3: u8 = 0,
};
/// Alias for channel 9 CTRL register
pub const CH9_AL2_CTRL = Register(CH9_AL2_CTRL_val).init(base_address + 0x260);
/// CH9_AL1_TRANS_COUNT_TRIG
const CH9_AL1_TRANS_COUNT_TRIG_val = packed struct {
CH9_AL1_TRANS_COUNT_TRIG_0: u8 = 0,
CH9_AL1_TRANS_COUNT_TRIG_1: u8 = 0,
CH9_AL1_TRANS_COUNT_TRIG_2: u8 = 0,
CH9_AL1_TRANS_COUNT_TRIG_3: u8 = 0,
};
/// Alias for channel 9 TRANS_COUNT register\n
pub const CH9_AL1_TRANS_COUNT_TRIG = Register(CH9_AL1_TRANS_COUNT_TRIG_val).init(base_address + 0x25c);
/// CH9_AL1_WRITE_ADDR
const CH9_AL1_WRITE_ADDR_val = packed struct {
CH9_AL1_WRITE_ADDR_0: u8 = 0,
CH9_AL1_WRITE_ADDR_1: u8 = 0,
CH9_AL1_WRITE_ADDR_2: u8 = 0,
CH9_AL1_WRITE_ADDR_3: u8 = 0,
};
/// Alias for channel 9 WRITE_ADDR register
pub const CH9_AL1_WRITE_ADDR = Register(CH9_AL1_WRITE_ADDR_val).init(base_address + 0x258);
/// CH9_AL1_READ_ADDR
const CH9_AL1_READ_ADDR_val = packed struct {
CH9_AL1_READ_ADDR_0: u8 = 0,
CH9_AL1_READ_ADDR_1: u8 = 0,
CH9_AL1_READ_ADDR_2: u8 = 0,
CH9_AL1_READ_ADDR_3: u8 = 0,
};
/// Alias for channel 9 READ_ADDR register
pub const CH9_AL1_READ_ADDR = Register(CH9_AL1_READ_ADDR_val).init(base_address + 0x254);
/// CH9_AL1_CTRL
const CH9_AL1_CTRL_val = packed struct {
CH9_AL1_CTRL_0: u8 = 0,
CH9_AL1_CTRL_1: u8 = 0,
CH9_AL1_CTRL_2: u8 = 0,
CH9_AL1_CTRL_3: u8 = 0,
};
/// Alias for channel 9 CTRL register
pub const CH9_AL1_CTRL = Register(CH9_AL1_CTRL_val).init(base_address + 0x250);
/// CH9_CTRL_TRIG
const CH9_CTRL_TRIG_val = packed struct {
/// EN [0:0]
/// DMA Channel Enable.\n
EN: u1 = 0,
/// HIGH_PRIORITY [1:1]
/// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
HIGH_PRIORITY: u1 = 0,
/// DATA_SIZE [2:3]
/// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
DATA_SIZE: u2 = 0,
/// INCR_READ [4:4]
/// If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
INCR_READ: u1 = 0,
/// INCR_WRITE [5:5]
/// If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
INCR_WRITE: u1 = 0,
/// RING_SIZE [6:9]
/// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
RING_SIZE: u4 = 0,
/// RING_SEL [10:10]
/// Select whether RING_SIZE applies to read or write addresses.\n
RING_SEL: u1 = 0,
/// CHAIN_TO [11:14]
/// When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n
CHAIN_TO: u4 = 9,
/// TREQ_SEL [15:20]
/// Select a Transfer Request signal.\n
TREQ_SEL: u6 = 0,
/// IRQ_QUIET [21:21]
/// In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
IRQ_QUIET: u1 = 0,
/// BSWAP [22:22]
/// Apply byte-swap transformation to DMA data.\n
BSWAP: u1 = 0,
/// SNIFF_EN [23:23]
/// If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
SNIFF_EN: u1 = 0,
/// BUSY [24:24]
/// This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
BUSY: u1 = 0,
/// unused [25:28]
_unused25: u4 = 0,
/// WRITE_ERROR [29:29]
/// If 1, the channel received a write bus error. Write one to clear.\n
WRITE_ERROR: u1 = 0,
/// READ_ERROR [30:30]
/// If 1, the channel received a read bus error. Write one to clear.\n
READ_ERROR: u1 = 0,
/// AHB_ERROR [31:31]
/// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
AHB_ERROR: u1 = 0,
};
/// DMA Channel 9 Control and Status
pub const CH9_CTRL_TRIG = Register(CH9_CTRL_TRIG_val).init(base_address + 0x24c);
/// CH9_TRANS_COUNT
const CH9_TRANS_COUNT_val = packed struct {
CH9_TRANS_COUNT_0: u8 = 0,
CH9_TRANS_COUNT_1: u8 = 0,
CH9_TRANS_COUNT_2: u8 = 0,
CH9_TRANS_COUNT_3: u8 = 0,
};
/// DMA Channel 9 Transfer Count\n
pub const CH9_TRANS_COUNT = Register(CH9_TRANS_COUNT_val).init(base_address + 0x248);
/// CH9_WRITE_ADDR
const CH9_WRITE_ADDR_val = packed struct {
CH9_WRITE_ADDR_0: u8 = 0,
CH9_WRITE_ADDR_1: u8 = 0,
CH9_WRITE_ADDR_2: u8 = 0,
CH9_WRITE_ADDR_3: u8 = 0,
};
/// DMA Channel 9 Write Address pointer\n
pub const CH9_WRITE_ADDR = Register(CH9_WRITE_ADDR_val).init(base_address + 0x244);
/// CH9_READ_ADDR
const CH9_READ_ADDR_val = packed struct {
CH9_READ_ADDR_0: u8 = 0,
CH9_READ_ADDR_1: u8 = 0,
CH9_READ_ADDR_2: u8 = 0,
CH9_READ_ADDR_3: u8 = 0,
};
/// DMA Channel 9 Read Address pointer\n
pub const CH9_READ_ADDR = Register(CH9_READ_ADDR_val).init(base_address + 0x240);
/// CH8_AL3_READ_ADDR_TRIG
const CH8_AL3_READ_ADDR_TRIG_val = packed struct {
CH8_AL3_READ_ADDR_TRIG_0: u8 = 0,
CH8_AL3_READ_ADDR_TRIG_1: u8 = 0,
CH8_AL3_READ_ADDR_TRIG_2: u8 = 0,
CH8_AL3_READ_ADDR_TRIG_3: u8 = 0,
};
/// Alias for channel 8 READ_ADDR register\n
pub const CH8_AL3_READ_ADDR_TRIG = Register(CH8_AL3_READ_ADDR_TRIG_val).init(base_address + 0x23c);
/// CH8_AL3_TRANS_COUNT
const CH8_AL3_TRANS_COUNT_val = packed struct {
CH8_AL3_TRANS_COUNT_0: u8 = 0,
CH8_AL3_TRANS_COUNT_1: u8 = 0,
CH8_AL3_TRANS_COUNT_2: u8 = 0,
CH8_AL3_TRANS_COUNT_3: u8 = 0,
};
/// Alias for channel 8 TRANS_COUNT register
pub const CH8_AL3_TRANS_COUNT = Register(CH8_AL3_TRANS_COUNT_val).init(base_address + 0x238);
/// CH8_AL3_WRITE_ADDR
const CH8_AL3_WRITE_ADDR_val = packed struct {
CH8_AL3_WRITE_ADDR_0: u8 = 0,
CH8_AL3_WRITE_ADDR_1: u8 = 0,
CH8_AL3_WRITE_ADDR_2: u8 = 0,
CH8_AL3_WRITE_ADDR_3: u8 = 0,
};
/// Alias for channel 8 WRITE_ADDR register
pub const CH8_AL3_WRITE_ADDR = Register(CH8_AL3_WRITE_ADDR_val).init(base_address + 0x234);
/// CH8_AL3_CTRL
const CH8_AL3_CTRL_val = packed struct {
CH8_AL3_CTRL_0: u8 = 0,
CH8_AL3_CTRL_1: u8 = 0,
CH8_AL3_CTRL_2: u8 = 0,
CH8_AL3_CTRL_3: u8 = 0,
};
/// Alias for channel 8 CTRL register
pub const CH8_AL3_CTRL = Register(CH8_AL3_CTRL_val).init(base_address + 0x230);
/// CH8_AL2_WRITE_ADDR_TRIG
const CH8_AL2_WRITE_ADDR_TRIG_val = packed struct {
CH8_AL2_WRITE_ADDR_TRIG_0: u8 = 0,
CH8_AL2_WRITE_ADDR_TRIG_1: u8 = 0,
CH8_AL2_WRITE_ADDR_TRIG_2: u8 = 0,
CH8_AL2_WRITE_ADDR_TRIG_3: u8 = 0,
};
/// Alias for channel 8 WRITE_ADDR register\n
pub const CH8_AL2_WRITE_ADDR_TRIG = Register(CH8_AL2_WRITE_ADDR_TRIG_val).init(base_address + 0x22c);
/// CH8_AL2_READ_ADDR
const CH8_AL2_READ_ADDR_val = packed struct {
CH8_AL2_READ_ADDR_0: u8 = 0,
CH8_AL2_READ_ADDR_1: u8 = 0,
CH8_AL2_READ_ADDR_2: u8 = 0,
CH8_AL2_READ_ADDR_3: u8 = 0,
};
/// Alias for channel 8 READ_ADDR register
pub const CH8_AL2_READ_ADDR = Register(CH8_AL2_READ_ADDR_val).init(base_address + 0x228);
/// CH8_AL2_TRANS_COUNT
const CH8_AL2_TRANS_COUNT_val = packed struct {
CH8_AL2_TRANS_COUNT_0: u8 = 0,
CH8_AL2_TRANS_COUNT_1: u8 = 0,
CH8_AL2_TRANS_COUNT_2: u8 = 0,
CH8_AL2_TRANS_COUNT_3: u8 = 0,
};
/// Alias for channel 8 TRANS_COUNT register
pub const CH8_AL2_TRANS_COUNT = Register(CH8_AL2_TRANS_COUNT_val).init(base_address + 0x224);
/// CH8_AL2_CTRL
const CH8_AL2_CTRL_val = packed struct {
CH8_AL2_CTRL_0: u8 = 0,
CH8_AL2_CTRL_1: u8 = 0,
CH8_AL2_CTRL_2: u8 = 0,
CH8_AL2_CTRL_3: u8 = 0,
};
/// Alias for channel 8 CTRL register
pub const CH8_AL2_CTRL = Register(CH8_AL2_CTRL_val).init(base_address + 0x220);
/// CH8_AL1_TRANS_COUNT_TRIG
const CH8_AL1_TRANS_COUNT_TRIG_val = packed struct {
CH8_AL1_TRANS_COUNT_TRIG_0: u8 = 0,
CH8_AL1_TRANS_COUNT_TRIG_1: u8 = 0,
CH8_AL1_TRANS_COUNT_TRIG_2: u8 = 0,
CH8_AL1_TRANS_COUNT_TRIG_3: u8 = 0,
};
/// Alias for channel 8 TRANS_COUNT register\n
pub const CH8_AL1_TRANS_COUNT_TRIG = Register(CH8_AL1_TRANS_COUNT_TRIG_val).init(base_address + 0x21c);
/// CH8_AL1_WRITE_ADDR
const CH8_AL1_WRITE_ADDR_val = packed struct {
CH8_AL1_WRITE_ADDR_0: u8 = 0,
CH8_AL1_WRITE_ADDR_1: u8 = 0,
CH8_AL1_WRITE_ADDR_2: u8 = 0,
CH8_AL1_WRITE_ADDR_3: u8 = 0,
};
/// Alias for channel 8 WRITE_ADDR register
pub const CH8_AL1_WRITE_ADDR = Register(CH8_AL1_WRITE_ADDR_val).init(base_address + 0x218);
/// CH8_AL1_READ_ADDR
const CH8_AL1_READ_ADDR_val = packed struct {
CH8_AL1_READ_ADDR_0: u8 = 0,
CH8_AL1_READ_ADDR_1: u8 = 0,
CH8_AL1_READ_ADDR_2: u8 = 0,
CH8_AL1_READ_ADDR_3: u8 = 0,
};
/// Alias for channel 8 READ_ADDR register
pub const CH8_AL1_READ_ADDR = Register(CH8_AL1_READ_ADDR_val).init(base_address + 0x214);
/// CH8_AL1_CTRL
const CH8_AL1_CTRL_val = packed struct {
CH8_AL1_CTRL_0: u8 = 0,
CH8_AL1_CTRL_1: u8 = 0,
CH8_AL1_CTRL_2: u8 = 0,
CH8_AL1_CTRL_3: u8 = 0,
};
/// Alias for channel 8 CTRL register
pub const CH8_AL1_CTRL = Register(CH8_AL1_CTRL_val).init(base_address + 0x210);
/// CH8_CTRL_TRIG
const CH8_CTRL_TRIG_val = packed struct {
/// EN [0:0]
/// DMA Channel Enable.\n
EN: u1 = 0,
/// HIGH_PRIORITY [1:1]
/// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
HIGH_PRIORITY: u1 = 0,
/// DATA_SIZE [2:3]
/// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
DATA_SIZE: u2 = 0,
/// INCR_READ [4:4]
/// If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
INCR_READ: u1 = 0,
/// INCR_WRITE [5:5]
/// If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
INCR_WRITE: u1 = 0,
/// RING_SIZE [6:9]
/// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
RING_SIZE: u4 = 0,
/// RING_SEL [10:10]
/// Select whether RING_SIZE applies to read or write addresses.\n
RING_SEL: u1 = 0,
/// CHAIN_TO [11:14]
/// When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n
CHAIN_TO: u4 = 8,
/// TREQ_SEL [15:20]
/// Select a Transfer Request signal.\n
TREQ_SEL: u6 = 0,
/// IRQ_QUIET [21:21]
/// In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
IRQ_QUIET: u1 = 0,
/// BSWAP [22:22]
/// Apply byte-swap transformation to DMA data.\n
BSWAP: u1 = 0,
/// SNIFF_EN [23:23]
/// If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
SNIFF_EN: u1 = 0,
/// BUSY [24:24]
/// This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
BUSY: u1 = 0,
/// unused [25:28]
_unused25: u4 = 0,
/// WRITE_ERROR [29:29]
/// If 1, the channel received a write bus error. Write one to clear.\n
WRITE_ERROR: u1 = 0,
/// READ_ERROR [30:30]
/// If 1, the channel received a read bus error. Write one to clear.\n
READ_ERROR: u1 = 0,
/// AHB_ERROR [31:31]
/// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
AHB_ERROR: u1 = 0,
};
/// DMA Channel 8 Control and Status
pub const CH8_CTRL_TRIG = Register(CH8_CTRL_TRIG_val).init(base_address + 0x20c);
/// CH8_TRANS_COUNT
const CH8_TRANS_COUNT_val = packed struct {
CH8_TRANS_COUNT_0: u8 = 0,
CH8_TRANS_COUNT_1: u8 = 0,
CH8_TRANS_COUNT_2: u8 = 0,
CH8_TRANS_COUNT_3: u8 = 0,
};
/// DMA Channel 8 Transfer Count\n
pub const CH8_TRANS_COUNT = Register(CH8_TRANS_COUNT_val).init(base_address + 0x208);
/// CH8_WRITE_ADDR
const CH8_WRITE_ADDR_val = packed struct {
CH8_WRITE_ADDR_0: u8 = 0,
CH8_WRITE_ADDR_1: u8 = 0,
CH8_WRITE_ADDR_2: u8 = 0,
CH8_WRITE_ADDR_3: u8 = 0,
};
/// DMA Channel 8 Write Address pointer\n
pub const CH8_WRITE_ADDR = Register(CH8_WRITE_ADDR_val).init(base_address + 0x204);
/// CH8_READ_ADDR
const CH8_READ_ADDR_val = packed struct {
CH8_READ_ADDR_0: u8 = 0,
CH8_READ_ADDR_1: u8 = 0,
CH8_READ_ADDR_2: u8 = 0,
CH8_READ_ADDR_3: u8 = 0,
};
/// DMA Channel 8 Read Address pointer\n
pub const CH8_READ_ADDR = Register(CH8_READ_ADDR_val).init(base_address + 0x200);
/// CH7_AL3_READ_ADDR_TRIG
const CH7_AL3_READ_ADDR_TRIG_val = packed struct {
CH7_AL3_READ_ADDR_TRIG_0: u8 = 0,
CH7_AL3_READ_ADDR_TRIG_1: u8 = 0,
CH7_AL3_READ_ADDR_TRIG_2: u8 = 0,
CH7_AL3_READ_ADDR_TRIG_3: u8 = 0,
};
/// Alias for channel 7 READ_ADDR register\n
pub const CH7_AL3_READ_ADDR_TRIG = Register(CH7_AL3_READ_ADDR_TRIG_val).init(base_address + 0x1fc);
/// CH7_AL3_TRANS_COUNT
const CH7_AL3_TRANS_COUNT_val = packed struct {
CH7_AL3_TRANS_COUNT_0: u8 = 0,
CH7_AL3_TRANS_COUNT_1: u8 = 0,
CH7_AL3_TRANS_COUNT_2: u8 = 0,
CH7_AL3_TRANS_COUNT_3: u8 = 0,
};
/// Alias for channel 7 TRANS_COUNT register
pub const CH7_AL3_TRANS_COUNT = Register(CH7_AL3_TRANS_COUNT_val).init(base_address + 0x1f8);
/// CH7_AL3_WRITE_ADDR
const CH7_AL3_WRITE_ADDR_val = packed struct {
CH7_AL3_WRITE_ADDR_0: u8 = 0,
CH7_AL3_WRITE_ADDR_1: u8 = 0,
CH7_AL3_WRITE_ADDR_2: u8 = 0,
CH7_AL3_WRITE_ADDR_3: u8 = 0,
};
/// Alias for channel 7 WRITE_ADDR register
pub const CH7_AL3_WRITE_ADDR = Register(CH7_AL3_WRITE_ADDR_val).init(base_address + 0x1f4);
/// CH7_AL3_CTRL
const CH7_AL3_CTRL_val = packed struct {
CH7_AL3_CTRL_0: u8 = 0,
CH7_AL3_CTRL_1: u8 = 0,
CH7_AL3_CTRL_2: u8 = 0,
CH7_AL3_CTRL_3: u8 = 0,
};
/// Alias for channel 7 CTRL register
pub const CH7_AL3_CTRL = Register(CH7_AL3_CTRL_val).init(base_address + 0x1f0);
/// CH7_AL2_WRITE_ADDR_TRIG
const CH7_AL2_WRITE_ADDR_TRIG_val = packed struct {
CH7_AL2_WRITE_ADDR_TRIG_0: u8 = 0,
CH7_AL2_WRITE_ADDR_TRIG_1: u8 = 0,
CH7_AL2_WRITE_ADDR_TRIG_2: u8 = 0,
CH7_AL2_WRITE_ADDR_TRIG_3: u8 = 0,
};
/// Alias for channel 7 WRITE_ADDR register\n
pub const CH7_AL2_WRITE_ADDR_TRIG = Register(CH7_AL2_WRITE_ADDR_TRIG_val).init(base_address + 0x1ec);
/// CH7_AL2_READ_ADDR
const CH7_AL2_READ_ADDR_val = packed struct {
CH7_AL2_READ_ADDR_0: u8 = 0,
CH7_AL2_READ_ADDR_1: u8 = 0,
CH7_AL2_READ_ADDR_2: u8 = 0,
CH7_AL2_READ_ADDR_3: u8 = 0,
};
/// Alias for channel 7 READ_ADDR register
pub const CH7_AL2_READ_ADDR = Register(CH7_AL2_READ_ADDR_val).init(base_address + 0x1e8);
/// CH7_AL2_TRANS_COUNT
const CH7_AL2_TRANS_COUNT_val = packed struct {
CH7_AL2_TRANS_COUNT_0: u8 = 0,
CH7_AL2_TRANS_COUNT_1: u8 = 0,
CH7_AL2_TRANS_COUNT_2: u8 = 0,
CH7_AL2_TRANS_COUNT_3: u8 = 0,
};
/// Alias for channel 7 TRANS_COUNT register
pub const CH7_AL2_TRANS_COUNT = Register(CH7_AL2_TRANS_COUNT_val).init(base_address + 0x1e4);
/// CH7_AL2_CTRL
const CH7_AL2_CTRL_val = packed struct {
CH7_AL2_CTRL_0: u8 = 0,
CH7_AL2_CTRL_1: u8 = 0,
CH7_AL2_CTRL_2: u8 = 0,
CH7_AL2_CTRL_3: u8 = 0,
};
/// Alias for channel 7 CTRL register
pub const CH7_AL2_CTRL = Register(CH7_AL2_CTRL_val).init(base_address + 0x1e0);
/// CH7_AL1_TRANS_COUNT_TRIG
const CH7_AL1_TRANS_COUNT_TRIG_val = packed struct {
CH7_AL1_TRANS_COUNT_TRIG_0: u8 = 0,
CH7_AL1_TRANS_COUNT_TRIG_1: u8 = 0,
CH7_AL1_TRANS_COUNT_TRIG_2: u8 = 0,
CH7_AL1_TRANS_COUNT_TRIG_3: u8 = 0,
};
/// Alias for channel 7 TRANS_COUNT register\n
pub const CH7_AL1_TRANS_COUNT_TRIG = Register(CH7_AL1_TRANS_COUNT_TRIG_val).init(base_address + 0x1dc);
/// CH7_AL1_WRITE_ADDR
const CH7_AL1_WRITE_ADDR_val = packed struct {
CH7_AL1_WRITE_ADDR_0: u8 = 0,
CH7_AL1_WRITE_ADDR_1: u8 = 0,
CH7_AL1_WRITE_ADDR_2: u8 = 0,
CH7_AL1_WRITE_ADDR_3: u8 = 0,
};
/// Alias for channel 7 WRITE_ADDR register
pub const CH7_AL1_WRITE_ADDR = Register(CH7_AL1_WRITE_ADDR_val).init(base_address + 0x1d8);
/// CH7_AL1_READ_ADDR
const CH7_AL1_READ_ADDR_val = packed struct {
CH7_AL1_READ_ADDR_0: u8 = 0,
CH7_AL1_READ_ADDR_1: u8 = 0,
CH7_AL1_READ_ADDR_2: u8 = 0,
CH7_AL1_READ_ADDR_3: u8 = 0,
};
/// Alias for channel 7 READ_ADDR register
pub const CH7_AL1_READ_ADDR = Register(CH7_AL1_READ_ADDR_val).init(base_address + 0x1d4);
/// CH7_AL1_CTRL
const CH7_AL1_CTRL_val = packed struct {
CH7_AL1_CTRL_0: u8 = 0,
CH7_AL1_CTRL_1: u8 = 0,
CH7_AL1_CTRL_2: u8 = 0,
CH7_AL1_CTRL_3: u8 = 0,
};
/// Alias for channel 7 CTRL register
pub const CH7_AL1_CTRL = Register(CH7_AL1_CTRL_val).init(base_address + 0x1d0);
/// CH7_CTRL_TRIG
const CH7_CTRL_TRIG_val = packed struct {
/// EN [0:0]
/// DMA Channel Enable.\n
EN: u1 = 0,
/// HIGH_PRIORITY [1:1]
/// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
HIGH_PRIORITY: u1 = 0,
/// DATA_SIZE [2:3]
/// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
DATA_SIZE: u2 = 0,
/// INCR_READ [4:4]
/// If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
INCR_READ: u1 = 0,
/// INCR_WRITE [5:5]
/// If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
INCR_WRITE: u1 = 0,
/// RING_SIZE [6:9]
/// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
RING_SIZE: u4 = 0,
/// RING_SEL [10:10]
/// Select whether RING_SIZE applies to read or write addresses.\n
RING_SEL: u1 = 0,
/// CHAIN_TO [11:14]
/// When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n
CHAIN_TO: u4 = 7,
/// TREQ_SEL [15:20]
/// Select a Transfer Request signal.\n
TREQ_SEL: u6 = 0,
/// IRQ_QUIET [21:21]
/// In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
IRQ_QUIET: u1 = 0,
/// BSWAP [22:22]
/// Apply byte-swap transformation to DMA data.\n
BSWAP: u1 = 0,
/// SNIFF_EN [23:23]
/// If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
SNIFF_EN: u1 = 0,
/// BUSY [24:24]
/// This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
BUSY: u1 = 0,
/// unused [25:28]
_unused25: u4 = 0,
/// WRITE_ERROR [29:29]
/// If 1, the channel received a write bus error. Write one to clear.\n
WRITE_ERROR: u1 = 0,
/// READ_ERROR [30:30]
/// If 1, the channel received a read bus error. Write one to clear.\n
READ_ERROR: u1 = 0,
/// AHB_ERROR [31:31]
/// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
AHB_ERROR: u1 = 0,
};
/// DMA Channel 7 Control and Status
pub const CH7_CTRL_TRIG = Register(CH7_CTRL_TRIG_val).init(base_address + 0x1cc);
/// CH7_TRANS_COUNT
const CH7_TRANS_COUNT_val = packed struct {
CH7_TRANS_COUNT_0: u8 = 0,
CH7_TRANS_COUNT_1: u8 = 0,
CH7_TRANS_COUNT_2: u8 = 0,
CH7_TRANS_COUNT_3: u8 = 0,
};
/// DMA Channel 7 Transfer Count\n
pub const CH7_TRANS_COUNT = Register(CH7_TRANS_COUNT_val).init(base_address + 0x1c8);
/// CH7_WRITE_ADDR
const CH7_WRITE_ADDR_val = packed struct {
CH7_WRITE_ADDR_0: u8 = 0,
CH7_WRITE_ADDR_1: u8 = 0,
CH7_WRITE_ADDR_2: u8 = 0,
CH7_WRITE_ADDR_3: u8 = 0,
};
/// DMA Channel 7 Write Address pointer\n
pub const CH7_WRITE_ADDR = Register(CH7_WRITE_ADDR_val).init(base_address + 0x1c4);
/// CH7_READ_ADDR
const CH7_READ_ADDR_val = packed struct {
CH7_READ_ADDR_0: u8 = 0,
CH7_READ_ADDR_1: u8 = 0,
CH7_READ_ADDR_2: u8 = 0,
CH7_READ_ADDR_3: u8 = 0,
};
/// DMA Channel 7 Read Address pointer\n
pub const CH7_READ_ADDR = Register(CH7_READ_ADDR_val).init(base_address + 0x1c0);
/// CH6_AL3_READ_ADDR_TRIG
const CH6_AL3_READ_ADDR_TRIG_val = packed struct {
CH6_AL3_READ_ADDR_TRIG_0: u8 = 0,
CH6_AL3_READ_ADDR_TRIG_1: u8 = 0,
CH6_AL3_READ_ADDR_TRIG_2: u8 = 0,
CH6_AL3_READ_ADDR_TRIG_3: u8 = 0,
};
/// Alias for channel 6 READ_ADDR register\n
pub const CH6_AL3_READ_ADDR_TRIG = Register(CH6_AL3_READ_ADDR_TRIG_val).init(base_address + 0x1bc);
/// CH6_AL3_TRANS_COUNT
const CH6_AL3_TRANS_COUNT_val = packed struct {
CH6_AL3_TRANS_COUNT_0: u8 = 0,
CH6_AL3_TRANS_COUNT_1: u8 = 0,
CH6_AL3_TRANS_COUNT_2: u8 = 0,
CH6_AL3_TRANS_COUNT_3: u8 = 0,
};
/// Alias for channel 6 TRANS_COUNT register
pub const CH6_AL3_TRANS_COUNT = Register(CH6_AL3_TRANS_COUNT_val).init(base_address + 0x1b8);
/// CH6_AL3_WRITE_ADDR
const CH6_AL3_WRITE_ADDR_val = packed struct {
CH6_AL3_WRITE_ADDR_0: u8 = 0,
CH6_AL3_WRITE_ADDR_1: u8 = 0,
CH6_AL3_WRITE_ADDR_2: u8 = 0,
CH6_AL3_WRITE_ADDR_3: u8 = 0,
};
/// Alias for channel 6 WRITE_ADDR register
pub const CH6_AL3_WRITE_ADDR = Register(CH6_AL3_WRITE_ADDR_val).init(base_address + 0x1b4);
/// CH6_AL3_CTRL
const CH6_AL3_CTRL_val = packed struct {
CH6_AL3_CTRL_0: u8 = 0,
CH6_AL3_CTRL_1: u8 = 0,
CH6_AL3_CTRL_2: u8 = 0,
CH6_AL3_CTRL_3: u8 = 0,
};
/// Alias for channel 6 CTRL register
pub const CH6_AL3_CTRL = Register(CH6_AL3_CTRL_val).init(base_address + 0x1b0);
/// CH6_AL2_WRITE_ADDR_TRIG
const CH6_AL2_WRITE_ADDR_TRIG_val = packed struct {
CH6_AL2_WRITE_ADDR_TRIG_0: u8 = 0,
CH6_AL2_WRITE_ADDR_TRIG_1: u8 = 0,
CH6_AL2_WRITE_ADDR_TRIG_2: u8 = 0,
CH6_AL2_WRITE_ADDR_TRIG_3: u8 = 0,
};
/// Alias for channel 6 WRITE_ADDR register\n
pub const CH6_AL2_WRITE_ADDR_TRIG = Register(CH6_AL2_WRITE_ADDR_TRIG_val).init(base_address + 0x1ac);
/// CH6_AL2_READ_ADDR
const CH6_AL2_READ_ADDR_val = packed struct {
CH6_AL2_READ_ADDR_0: u8 = 0,
CH6_AL2_READ_ADDR_1: u8 = 0,
CH6_AL2_READ_ADDR_2: u8 = 0,
CH6_AL2_READ_ADDR_3: u8 = 0,
};
/// Alias for channel 6 READ_ADDR register
pub const CH6_AL2_READ_ADDR = Register(CH6_AL2_READ_ADDR_val).init(base_address + 0x1a8);
/// CH6_AL2_TRANS_COUNT
const CH6_AL2_TRANS_COUNT_val = packed struct {
CH6_AL2_TRANS_COUNT_0: u8 = 0,
CH6_AL2_TRANS_COUNT_1: u8 = 0,
CH6_AL2_TRANS_COUNT_2: u8 = 0,
CH6_AL2_TRANS_COUNT_3: u8 = 0,
};
/// Alias for channel 6 TRANS_COUNT register
pub const CH6_AL2_TRANS_COUNT = Register(CH6_AL2_TRANS_COUNT_val).init(base_address + 0x1a4);
/// CH6_AL2_CTRL
const CH6_AL2_CTRL_val = packed struct {
CH6_AL2_CTRL_0: u8 = 0,
CH6_AL2_CTRL_1: u8 = 0,
CH6_AL2_CTRL_2: u8 = 0,
CH6_AL2_CTRL_3: u8 = 0,
};
/// Alias for channel 6 CTRL register
pub const CH6_AL2_CTRL = Register(CH6_AL2_CTRL_val).init(base_address + 0x1a0);
/// CH6_AL1_TRANS_COUNT_TRIG
const CH6_AL1_TRANS_COUNT_TRIG_val = packed struct {
CH6_AL1_TRANS_COUNT_TRIG_0: u8 = 0,
CH6_AL1_TRANS_COUNT_TRIG_1: u8 = 0,
CH6_AL1_TRANS_COUNT_TRIG_2: u8 = 0,
CH6_AL1_TRANS_COUNT_TRIG_3: u8 = 0,
};
/// Alias for channel 6 TRANS_COUNT register\n
pub const CH6_AL1_TRANS_COUNT_TRIG = Register(CH6_AL1_TRANS_COUNT_TRIG_val).init(base_address + 0x19c);
/// CH6_AL1_WRITE_ADDR
const CH6_AL1_WRITE_ADDR_val = packed struct {
CH6_AL1_WRITE_ADDR_0: u8 = 0,
CH6_AL1_WRITE_ADDR_1: u8 = 0,
CH6_AL1_WRITE_ADDR_2: u8 = 0,
CH6_AL1_WRITE_ADDR_3: u8 = 0,
};
/// Alias for channel 6 WRITE_ADDR register
pub const CH6_AL1_WRITE_ADDR = Register(CH6_AL1_WRITE_ADDR_val).init(base_address + 0x198);
/// CH6_AL1_READ_ADDR
const CH6_AL1_READ_ADDR_val = packed struct {
CH6_AL1_READ_ADDR_0: u8 = 0,
CH6_AL1_READ_ADDR_1: u8 = 0,
CH6_AL1_READ_ADDR_2: u8 = 0,
CH6_AL1_READ_ADDR_3: u8 = 0,
};
/// Alias for channel 6 READ_ADDR register
pub const CH6_AL1_READ_ADDR = Register(CH6_AL1_READ_ADDR_val).init(base_address + 0x194);
/// CH6_AL1_CTRL
const CH6_AL1_CTRL_val = packed struct {
CH6_AL1_CTRL_0: u8 = 0,
CH6_AL1_CTRL_1: u8 = 0,
CH6_AL1_CTRL_2: u8 = 0,
CH6_AL1_CTRL_3: u8 = 0,
};
/// Alias for channel 6 CTRL register
pub const CH6_AL1_CTRL = Register(CH6_AL1_CTRL_val).init(base_address + 0x190);
/// CH6_CTRL_TRIG
const CH6_CTRL_TRIG_val = packed struct {
/// EN [0:0]
/// DMA Channel Enable.\n
EN: u1 = 0,
/// HIGH_PRIORITY [1:1]
/// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
HIGH_PRIORITY: u1 = 0,
/// DATA_SIZE [2:3]
/// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
DATA_SIZE: u2 = 0,
/// INCR_READ [4:4]
/// If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
INCR_READ: u1 = 0,
/// INCR_WRITE [5:5]
/// If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
INCR_WRITE: u1 = 0,
/// RING_SIZE [6:9]
/// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
RING_SIZE: u4 = 0,
/// RING_SEL [10:10]
/// Select whether RING_SIZE applies to read or write addresses.\n
RING_SEL: u1 = 0,
/// CHAIN_TO [11:14]
/// When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n
CHAIN_TO: u4 = 6,
/// TREQ_SEL [15:20]
/// Select a Transfer Request signal.\n
TREQ_SEL: u6 = 0,
/// IRQ_QUIET [21:21]
/// In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
IRQ_QUIET: u1 = 0,
/// BSWAP [22:22]
/// Apply byte-swap transformation to DMA data.\n
BSWAP: u1 = 0,
/// SNIFF_EN [23:23]
/// If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
SNIFF_EN: u1 = 0,
/// BUSY [24:24]
/// This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
BUSY: u1 = 0,
/// unused [25:28]
_unused25: u4 = 0,
/// WRITE_ERROR [29:29]
/// If 1, the channel received a write bus error. Write one to clear.\n
WRITE_ERROR: u1 = 0,
/// READ_ERROR [30:30]
/// If 1, the channel received a read bus error. Write one to clear.\n
READ_ERROR: u1 = 0,
/// AHB_ERROR [31:31]
/// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
AHB_ERROR: u1 = 0,
};
/// DMA Channel 6 Control and Status
pub const CH6_CTRL_TRIG = Register(CH6_CTRL_TRIG_val).init(base_address + 0x18c);
/// CH6_TRANS_COUNT
const CH6_TRANS_COUNT_val = packed struct {
CH6_TRANS_COUNT_0: u8 = 0,
CH6_TRANS_COUNT_1: u8 = 0,
CH6_TRANS_COUNT_2: u8 = 0,
CH6_TRANS_COUNT_3: u8 = 0,
};
/// DMA Channel 6 Transfer Count\n
pub const CH6_TRANS_COUNT = Register(CH6_TRANS_COUNT_val).init(base_address + 0x188);
/// CH6_WRITE_ADDR
const CH6_WRITE_ADDR_val = packed struct {
CH6_WRITE_ADDR_0: u8 = 0,
CH6_WRITE_ADDR_1: u8 = 0,
CH6_WRITE_ADDR_2: u8 = 0,
CH6_WRITE_ADDR_3: u8 = 0,
};
/// DMA Channel 6 Write Address pointer\n
pub const CH6_WRITE_ADDR = Register(CH6_WRITE_ADDR_val).init(base_address + 0x184);
/// CH6_READ_ADDR
const CH6_READ_ADDR_val = packed struct {
CH6_READ_ADDR_0: u8 = 0,
CH6_READ_ADDR_1: u8 = 0,
CH6_READ_ADDR_2: u8 = 0,
CH6_READ_ADDR_3: u8 = 0,
};
/// DMA Channel 6 Read Address pointer\n
pub const CH6_READ_ADDR = Register(CH6_READ_ADDR_val).init(base_address + 0x180);
/// CH5_AL3_READ_ADDR_TRIG
const CH5_AL3_READ_ADDR_TRIG_val = packed struct {
CH5_AL3_READ_ADDR_TRIG_0: u8 = 0,
CH5_AL3_READ_ADDR_TRIG_1: u8 = 0,
CH5_AL3_READ_ADDR_TRIG_2: u8 = 0,
CH5_AL3_READ_ADDR_TRIG_3: u8 = 0,
};
/// Alias for channel 5 READ_ADDR register\n
pub const CH5_AL3_READ_ADDR_TRIG = Register(CH5_AL3_READ_ADDR_TRIG_val).init(base_address + 0x17c);
/// CH5_AL3_TRANS_COUNT
const CH5_AL3_TRANS_COUNT_val = packed struct {
CH5_AL3_TRANS_COUNT_0: u8 = 0,
CH5_AL3_TRANS_COUNT_1: u8 = 0,
CH5_AL3_TRANS_COUNT_2: u8 = 0,
CH5_AL3_TRANS_COUNT_3: u8 = 0,
};
/// Alias for channel 5 TRANS_COUNT register
pub const CH5_AL3_TRANS_COUNT = Register(CH5_AL3_TRANS_COUNT_val).init(base_address + 0x178);
/// CH5_AL3_WRITE_ADDR
const CH5_AL3_WRITE_ADDR_val = packed struct {
CH5_AL3_WRITE_ADDR_0: u8 = 0,
CH5_AL3_WRITE_ADDR_1: u8 = 0,
CH5_AL3_WRITE_ADDR_2: u8 = 0,
CH5_AL3_WRITE_ADDR_3: u8 = 0,
};
/// Alias for channel 5 WRITE_ADDR register
pub const CH5_AL3_WRITE_ADDR = Register(CH5_AL3_WRITE_ADDR_val).init(base_address + 0x174);
/// CH5_AL3_CTRL
const CH5_AL3_CTRL_val = packed struct {
CH5_AL3_CTRL_0: u8 = 0,
CH5_AL3_CTRL_1: u8 = 0,
CH5_AL3_CTRL_2: u8 = 0,
CH5_AL3_CTRL_3: u8 = 0,
};
/// Alias for channel 5 CTRL register
pub const CH5_AL3_CTRL = Register(CH5_AL3_CTRL_val).init(base_address + 0x170);
/// CH5_AL2_WRITE_ADDR_TRIG
const CH5_AL2_WRITE_ADDR_TRIG_val = packed struct {
CH5_AL2_WRITE_ADDR_TRIG_0: u8 = 0,
CH5_AL2_WRITE_ADDR_TRIG_1: u8 = 0,
CH5_AL2_WRITE_ADDR_TRIG_2: u8 = 0,
CH5_AL2_WRITE_ADDR_TRIG_3: u8 = 0,
};
/// Alias for channel 5 WRITE_ADDR register\n
pub const CH5_AL2_WRITE_ADDR_TRIG = Register(CH5_AL2_WRITE_ADDR_TRIG_val).init(base_address + 0x16c);
/// CH5_AL2_READ_ADDR
const CH5_AL2_READ_ADDR_val = packed struct {
CH5_AL2_READ_ADDR_0: u8 = 0,
CH5_AL2_READ_ADDR_1: u8 = 0,
CH5_AL2_READ_ADDR_2: u8 = 0,
CH5_AL2_READ_ADDR_3: u8 = 0,
};
/// Alias for channel 5 READ_ADDR register
pub const CH5_AL2_READ_ADDR = Register(CH5_AL2_READ_ADDR_val).init(base_address + 0x168);
/// CH5_AL2_TRANS_COUNT
const CH5_AL2_TRANS_COUNT_val = packed struct {
CH5_AL2_TRANS_COUNT_0: u8 = 0,
CH5_AL2_TRANS_COUNT_1: u8 = 0,
CH5_AL2_TRANS_COUNT_2: u8 = 0,
CH5_AL2_TRANS_COUNT_3: u8 = 0,
};
/// Alias for channel 5 TRANS_COUNT register
pub const CH5_AL2_TRANS_COUNT = Register(CH5_AL2_TRANS_COUNT_val).init(base_address + 0x164);
/// CH5_AL2_CTRL
const CH5_AL2_CTRL_val = packed struct {
CH5_AL2_CTRL_0: u8 = 0,
CH5_AL2_CTRL_1: u8 = 0,
CH5_AL2_CTRL_2: u8 = 0,
CH5_AL2_CTRL_3: u8 = 0,
};
/// Alias for channel 5 CTRL register
pub const CH5_AL2_CTRL = Register(CH5_AL2_CTRL_val).init(base_address + 0x160);
/// CH5_AL1_TRANS_COUNT_TRIG
const CH5_AL1_TRANS_COUNT_TRIG_val = packed struct {
CH5_AL1_TRANS_COUNT_TRIG_0: u8 = 0,
CH5_AL1_TRANS_COUNT_TRIG_1: u8 = 0,
CH5_AL1_TRANS_COUNT_TRIG_2: u8 = 0,
CH5_AL1_TRANS_COUNT_TRIG_3: u8 = 0,
};
/// Alias for channel 5 TRANS_COUNT register\n
pub const CH5_AL1_TRANS_COUNT_TRIG = Register(CH5_AL1_TRANS_COUNT_TRIG_val).init(base_address + 0x15c);
/// CH5_AL1_WRITE_ADDR
const CH5_AL1_WRITE_ADDR_val = packed struct {
CH5_AL1_WRITE_ADDR_0: u8 = 0,
CH5_AL1_WRITE_ADDR_1: u8 = 0,
CH5_AL1_WRITE_ADDR_2: u8 = 0,
CH5_AL1_WRITE_ADDR_3: u8 = 0,
};
/// Alias for channel 5 WRITE_ADDR register
pub const CH5_AL1_WRITE_ADDR = Register(CH5_AL1_WRITE_ADDR_val).init(base_address + 0x158);
/// CH5_AL1_READ_ADDR
const CH5_AL1_READ_ADDR_val = packed struct {
CH5_AL1_READ_ADDR_0: u8 = 0,
CH5_AL1_READ_ADDR_1: u8 = 0,
CH5_AL1_READ_ADDR_2: u8 = 0,
CH5_AL1_READ_ADDR_3: u8 = 0,
};
/// Alias for channel 5 READ_ADDR register
pub const CH5_AL1_READ_ADDR = Register(CH5_AL1_READ_ADDR_val).init(base_address + 0x154);
/// CH5_AL1_CTRL
const CH5_AL1_CTRL_val = packed struct {
CH5_AL1_CTRL_0: u8 = 0,
CH5_AL1_CTRL_1: u8 = 0,
CH5_AL1_CTRL_2: u8 = 0,
CH5_AL1_CTRL_3: u8 = 0,
};
/// Alias for channel 5 CTRL register
pub const CH5_AL1_CTRL = Register(CH5_AL1_CTRL_val).init(base_address + 0x150);
/// CH5_CTRL_TRIG
const CH5_CTRL_TRIG_val = packed struct {
/// EN [0:0]
/// DMA Channel Enable.\n
EN: u1 = 0,
/// HIGH_PRIORITY [1:1]
/// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
HIGH_PRIORITY: u1 = 0,
/// DATA_SIZE [2:3]
/// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
DATA_SIZE: u2 = 0,
/// INCR_READ [4:4]
/// If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
INCR_READ: u1 = 0,
/// INCR_WRITE [5:5]
/// If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
INCR_WRITE: u1 = 0,
/// RING_SIZE [6:9]
/// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
RING_SIZE: u4 = 0,
/// RING_SEL [10:10]
/// Select whether RING_SIZE applies to read or write addresses.\n
RING_SEL: u1 = 0,
/// CHAIN_TO [11:14]
/// When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n
CHAIN_TO: u4 = 5,
/// TREQ_SEL [15:20]
/// Select a Transfer Request signal.\n
TREQ_SEL: u6 = 0,
/// IRQ_QUIET [21:21]
/// In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
IRQ_QUIET: u1 = 0,
/// BSWAP [22:22]
/// Apply byte-swap transformation to DMA data.\n
BSWAP: u1 = 0,
/// SNIFF_EN [23:23]
/// If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
SNIFF_EN: u1 = 0,
/// BUSY [24:24]
/// This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
BUSY: u1 = 0,
/// unused [25:28]
_unused25: u4 = 0,
/// WRITE_ERROR [29:29]
/// If 1, the channel received a write bus error. Write one to clear.\n
WRITE_ERROR: u1 = 0,
/// READ_ERROR [30:30]
/// If 1, the channel received a read bus error. Write one to clear.\n
READ_ERROR: u1 = 0,
/// AHB_ERROR [31:31]
/// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
AHB_ERROR: u1 = 0,
};
/// DMA Channel 5 Control and Status
pub const CH5_CTRL_TRIG = Register(CH5_CTRL_TRIG_val).init(base_address + 0x14c);
/// CH5_TRANS_COUNT
const CH5_TRANS_COUNT_val = packed struct {
CH5_TRANS_COUNT_0: u8 = 0,
CH5_TRANS_COUNT_1: u8 = 0,
CH5_TRANS_COUNT_2: u8 = 0,
CH5_TRANS_COUNT_3: u8 = 0,
};
/// DMA Channel 5 Transfer Count\n
pub const CH5_TRANS_COUNT = Register(CH5_TRANS_COUNT_val).init(base_address + 0x148);
/// CH5_WRITE_ADDR
const CH5_WRITE_ADDR_val = packed struct {
CH5_WRITE_ADDR_0: u8 = 0,
CH5_WRITE_ADDR_1: u8 = 0,
CH5_WRITE_ADDR_2: u8 = 0,
CH5_WRITE_ADDR_3: u8 = 0,
};
/// DMA Channel 5 Write Address pointer\n
pub const CH5_WRITE_ADDR = Register(CH5_WRITE_ADDR_val).init(base_address + 0x144);
/// CH5_READ_ADDR
const CH5_READ_ADDR_val = packed struct {
CH5_READ_ADDR_0: u8 = 0,
CH5_READ_ADDR_1: u8 = 0,
CH5_READ_ADDR_2: u8 = 0,
CH5_READ_ADDR_3: u8 = 0,
};
/// DMA Channel 5 Read Address pointer\n
pub const CH5_READ_ADDR = Register(CH5_READ_ADDR_val).init(base_address + 0x140);
/// CH4_AL3_READ_ADDR_TRIG
const CH4_AL3_READ_ADDR_TRIG_val = packed struct {
CH4_AL3_READ_ADDR_TRIG_0: u8 = 0,
CH4_AL3_READ_ADDR_TRIG_1: u8 = 0,
CH4_AL3_READ_ADDR_TRIG_2: u8 = 0,
CH4_AL3_READ_ADDR_TRIG_3: u8 = 0,
};
/// Alias for channel 4 READ_ADDR register\n
pub const CH4_AL3_READ_ADDR_TRIG = Register(CH4_AL3_READ_ADDR_TRIG_val).init(base_address + 0x13c);
/// CH4_AL3_TRANS_COUNT
const CH4_AL3_TRANS_COUNT_val = packed struct {
CH4_AL3_TRANS_COUNT_0: u8 = 0,
CH4_AL3_TRANS_COUNT_1: u8 = 0,
CH4_AL3_TRANS_COUNT_2: u8 = 0,
CH4_AL3_TRANS_COUNT_3: u8 = 0,
};
/// Alias for channel 4 TRANS_COUNT register
pub const CH4_AL3_TRANS_COUNT = Register(CH4_AL3_TRANS_COUNT_val).init(base_address + 0x138);
/// CH4_AL3_WRITE_ADDR
const CH4_AL3_WRITE_ADDR_val = packed struct {
CH4_AL3_WRITE_ADDR_0: u8 = 0,
CH4_AL3_WRITE_ADDR_1: u8 = 0,
CH4_AL3_WRITE_ADDR_2: u8 = 0,
CH4_AL3_WRITE_ADDR_3: u8 = 0,
};
/// Alias for channel 4 WRITE_ADDR register
pub const CH4_AL3_WRITE_ADDR = Register(CH4_AL3_WRITE_ADDR_val).init(base_address + 0x134);
/// CH4_AL3_CTRL
const CH4_AL3_CTRL_val = packed struct {
CH4_AL3_CTRL_0: u8 = 0,
CH4_AL3_CTRL_1: u8 = 0,
CH4_AL3_CTRL_2: u8 = 0,
CH4_AL3_CTRL_3: u8 = 0,
};
/// Alias for channel 4 CTRL register
pub const CH4_AL3_CTRL = Register(CH4_AL3_CTRL_val).init(base_address + 0x130);
/// CH4_AL2_WRITE_ADDR_TRIG
const CH4_AL2_WRITE_ADDR_TRIG_val = packed struct {
CH4_AL2_WRITE_ADDR_TRIG_0: u8 = 0,
CH4_AL2_WRITE_ADDR_TRIG_1: u8 = 0,
CH4_AL2_WRITE_ADDR_TRIG_2: u8 = 0,
CH4_AL2_WRITE_ADDR_TRIG_3: u8 = 0,
};
/// Alias for channel 4 WRITE_ADDR register\n
pub const CH4_AL2_WRITE_ADDR_TRIG = Register(CH4_AL2_WRITE_ADDR_TRIG_val).init(base_address + 0x12c);
/// CH4_AL2_READ_ADDR
const CH4_AL2_READ_ADDR_val = packed struct {
CH4_AL2_READ_ADDR_0: u8 = 0,
CH4_AL2_READ_ADDR_1: u8 = 0,
CH4_AL2_READ_ADDR_2: u8 = 0,
CH4_AL2_READ_ADDR_3: u8 = 0,
};
/// Alias for channel 4 READ_ADDR register
pub const CH4_AL2_READ_ADDR = Register(CH4_AL2_READ_ADDR_val).init(base_address + 0x128);
/// CH4_AL2_TRANS_COUNT
const CH4_AL2_TRANS_COUNT_val = packed struct {
CH4_AL2_TRANS_COUNT_0: u8 = 0,
CH4_AL2_TRANS_COUNT_1: u8 = 0,
CH4_AL2_TRANS_COUNT_2: u8 = 0,
CH4_AL2_TRANS_COUNT_3: u8 = 0,
};
/// Alias for channel 4 TRANS_COUNT register
pub const CH4_AL2_TRANS_COUNT = Register(CH4_AL2_TRANS_COUNT_val).init(base_address + 0x124);
/// CH4_AL2_CTRL
const CH4_AL2_CTRL_val = packed struct {
CH4_AL2_CTRL_0: u8 = 0,
CH4_AL2_CTRL_1: u8 = 0,
CH4_AL2_CTRL_2: u8 = 0,
CH4_AL2_CTRL_3: u8 = 0,
};
/// Alias for channel 4 CTRL register
pub const CH4_AL2_CTRL = Register(CH4_AL2_CTRL_val).init(base_address + 0x120);
/// CH4_AL1_TRANS_COUNT_TRIG
const CH4_AL1_TRANS_COUNT_TRIG_val = packed struct {
CH4_AL1_TRANS_COUNT_TRIG_0: u8 = 0,
CH4_AL1_TRANS_COUNT_TRIG_1: u8 = 0,
CH4_AL1_TRANS_COUNT_TRIG_2: u8 = 0,
CH4_AL1_TRANS_COUNT_TRIG_3: u8 = 0,
};
/// Alias for channel 4 TRANS_COUNT register\n
pub const CH4_AL1_TRANS_COUNT_TRIG = Register(CH4_AL1_TRANS_COUNT_TRIG_val).init(base_address + 0x11c);
/// CH4_AL1_WRITE_ADDR
const CH4_AL1_WRITE_ADDR_val = packed struct {
CH4_AL1_WRITE_ADDR_0: u8 = 0,
CH4_AL1_WRITE_ADDR_1: u8 = 0,
CH4_AL1_WRITE_ADDR_2: u8 = 0,
CH4_AL1_WRITE_ADDR_3: u8 = 0,
};
/// Alias for channel 4 WRITE_ADDR register
pub const CH4_AL1_WRITE_ADDR = Register(CH4_AL1_WRITE_ADDR_val).init(base_address + 0x118);
/// CH4_AL1_READ_ADDR
const CH4_AL1_READ_ADDR_val = packed struct {
CH4_AL1_READ_ADDR_0: u8 = 0,
CH4_AL1_READ_ADDR_1: u8 = 0,
CH4_AL1_READ_ADDR_2: u8 = 0,
CH4_AL1_READ_ADDR_3: u8 = 0,
};
/// Alias for channel 4 READ_ADDR register
pub const CH4_AL1_READ_ADDR = Register(CH4_AL1_READ_ADDR_val).init(base_address + 0x114);
/// CH4_AL1_CTRL
const CH4_AL1_CTRL_val = packed struct {
CH4_AL1_CTRL_0: u8 = 0,
CH4_AL1_CTRL_1: u8 = 0,
CH4_AL1_CTRL_2: u8 = 0,
CH4_AL1_CTRL_3: u8 = 0,
};
/// Alias for channel 4 CTRL register
pub const CH4_AL1_CTRL = Register(CH4_AL1_CTRL_val).init(base_address + 0x110);
/// CH4_CTRL_TRIG
const CH4_CTRL_TRIG_val = packed struct {
/// EN [0:0]
/// DMA Channel Enable.\n
EN: u1 = 0,
/// HIGH_PRIORITY [1:1]
/// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
HIGH_PRIORITY: u1 = 0,
/// DATA_SIZE [2:3]
/// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
DATA_SIZE: u2 = 0,
/// INCR_READ [4:4]
/// If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
INCR_READ: u1 = 0,
/// INCR_WRITE [5:5]
/// If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
INCR_WRITE: u1 = 0,
/// RING_SIZE [6:9]
/// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
RING_SIZE: u4 = 0,
/// RING_SEL [10:10]
/// Select whether RING_SIZE applies to read or write addresses.\n
RING_SEL: u1 = 0,
/// CHAIN_TO [11:14]
/// When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n
CHAIN_TO: u4 = 4,
/// TREQ_SEL [15:20]
/// Select a Transfer Request signal.\n
TREQ_SEL: u6 = 0,
/// IRQ_QUIET [21:21]
/// In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
IRQ_QUIET: u1 = 0,
/// BSWAP [22:22]
/// Apply byte-swap transformation to DMA data.\n
BSWAP: u1 = 0,
/// SNIFF_EN [23:23]
/// If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
SNIFF_EN: u1 = 0,
/// BUSY [24:24]
/// This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
BUSY: u1 = 0,
/// unused [25:28]
_unused25: u4 = 0,
/// WRITE_ERROR [29:29]
/// If 1, the channel received a write bus error. Write one to clear.\n
WRITE_ERROR: u1 = 0,
/// READ_ERROR [30:30]
/// If 1, the channel received a read bus error. Write one to clear.\n
READ_ERROR: u1 = 0,
/// AHB_ERROR [31:31]
/// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
AHB_ERROR: u1 = 0,
};
/// DMA Channel 4 Control and Status
pub const CH4_CTRL_TRIG = Register(CH4_CTRL_TRIG_val).init(base_address + 0x10c);
/// CH4_TRANS_COUNT
const CH4_TRANS_COUNT_val = packed struct {
CH4_TRANS_COUNT_0: u8 = 0,
CH4_TRANS_COUNT_1: u8 = 0,
CH4_TRANS_COUNT_2: u8 = 0,
CH4_TRANS_COUNT_3: u8 = 0,
};
/// DMA Channel 4 Transfer Count\n
pub const CH4_TRANS_COUNT = Register(CH4_TRANS_COUNT_val).init(base_address + 0x108);
/// CH4_WRITE_ADDR
const CH4_WRITE_ADDR_val = packed struct {
CH4_WRITE_ADDR_0: u8 = 0,
CH4_WRITE_ADDR_1: u8 = 0,
CH4_WRITE_ADDR_2: u8 = 0,
CH4_WRITE_ADDR_3: u8 = 0,
};
/// DMA Channel 4 Write Address pointer\n
pub const CH4_WRITE_ADDR = Register(CH4_WRITE_ADDR_val).init(base_address + 0x104);
/// CH4_READ_ADDR
const CH4_READ_ADDR_val = packed struct {
CH4_READ_ADDR_0: u8 = 0,
CH4_READ_ADDR_1: u8 = 0,
CH4_READ_ADDR_2: u8 = 0,
CH4_READ_ADDR_3: u8 = 0,
};
/// DMA Channel 4 Read Address pointer\n
pub const CH4_READ_ADDR = Register(CH4_READ_ADDR_val).init(base_address + 0x100);
/// CH3_AL3_READ_ADDR_TRIG
const CH3_AL3_READ_ADDR_TRIG_val = packed struct {
CH3_AL3_READ_ADDR_TRIG_0: u8 = 0,
CH3_AL3_READ_ADDR_TRIG_1: u8 = 0,
CH3_AL3_READ_ADDR_TRIG_2: u8 = 0,
CH3_AL3_READ_ADDR_TRIG_3: u8 = 0,
};
/// Alias for channel 3 READ_ADDR register\n
pub const CH3_AL3_READ_ADDR_TRIG = Register(CH3_AL3_READ_ADDR_TRIG_val).init(base_address + 0xfc);
/// CH3_AL3_TRANS_COUNT
const CH3_AL3_TRANS_COUNT_val = packed struct {
CH3_AL3_TRANS_COUNT_0: u8 = 0,
CH3_AL3_TRANS_COUNT_1: u8 = 0,
CH3_AL3_TRANS_COUNT_2: u8 = 0,
CH3_AL3_TRANS_COUNT_3: u8 = 0,
};
/// Alias for channel 3 TRANS_COUNT register
pub const CH3_AL3_TRANS_COUNT = Register(CH3_AL3_TRANS_COUNT_val).init(base_address + 0xf8);
/// CH3_AL3_WRITE_ADDR
const CH3_AL3_WRITE_ADDR_val = packed struct {
CH3_AL3_WRITE_ADDR_0: u8 = 0,
CH3_AL3_WRITE_ADDR_1: u8 = 0,
CH3_AL3_WRITE_ADDR_2: u8 = 0,
CH3_AL3_WRITE_ADDR_3: u8 = 0,
};
/// Alias for channel 3 WRITE_ADDR register
pub const CH3_AL3_WRITE_ADDR = Register(CH3_AL3_WRITE_ADDR_val).init(base_address + 0xf4);
/// CH3_AL3_CTRL
const CH3_AL3_CTRL_val = packed struct {
CH3_AL3_CTRL_0: u8 = 0,
CH3_AL3_CTRL_1: u8 = 0,
CH3_AL3_CTRL_2: u8 = 0,
CH3_AL3_CTRL_3: u8 = 0,
};
/// Alias for channel 3 CTRL register
pub const CH3_AL3_CTRL = Register(CH3_AL3_CTRL_val).init(base_address + 0xf0);
/// CH3_AL2_WRITE_ADDR_TRIG
const CH3_AL2_WRITE_ADDR_TRIG_val = packed struct {
CH3_AL2_WRITE_ADDR_TRIG_0: u8 = 0,
CH3_AL2_WRITE_ADDR_TRIG_1: u8 = 0,
CH3_AL2_WRITE_ADDR_TRIG_2: u8 = 0,
CH3_AL2_WRITE_ADDR_TRIG_3: u8 = 0,
};
/// Alias for channel 3 WRITE_ADDR register\n
pub const CH3_AL2_WRITE_ADDR_TRIG = Register(CH3_AL2_WRITE_ADDR_TRIG_val).init(base_address + 0xec);
/// CH3_AL2_READ_ADDR
const CH3_AL2_READ_ADDR_val = packed struct {
CH3_AL2_READ_ADDR_0: u8 = 0,
CH3_AL2_READ_ADDR_1: u8 = 0,
CH3_AL2_READ_ADDR_2: u8 = 0,
CH3_AL2_READ_ADDR_3: u8 = 0,
};
/// Alias for channel 3 READ_ADDR register
pub const CH3_AL2_READ_ADDR = Register(CH3_AL2_READ_ADDR_val).init(base_address + 0xe8);
/// CH3_AL2_TRANS_COUNT
const CH3_AL2_TRANS_COUNT_val = packed struct {
CH3_AL2_TRANS_COUNT_0: u8 = 0,
CH3_AL2_TRANS_COUNT_1: u8 = 0,
CH3_AL2_TRANS_COUNT_2: u8 = 0,
CH3_AL2_TRANS_COUNT_3: u8 = 0,
};
/// Alias for channel 3 TRANS_COUNT register
pub const CH3_AL2_TRANS_COUNT = Register(CH3_AL2_TRANS_COUNT_val).init(base_address + 0xe4);
/// CH3_AL2_CTRL
const CH3_AL2_CTRL_val = packed struct {
CH3_AL2_CTRL_0: u8 = 0,
CH3_AL2_CTRL_1: u8 = 0,
CH3_AL2_CTRL_2: u8 = 0,
CH3_AL2_CTRL_3: u8 = 0,
};
/// Alias for channel 3 CTRL register
pub const CH3_AL2_CTRL = Register(CH3_AL2_CTRL_val).init(base_address + 0xe0);
/// CH3_AL1_TRANS_COUNT_TRIG
const CH3_AL1_TRANS_COUNT_TRIG_val = packed struct {
CH3_AL1_TRANS_COUNT_TRIG_0: u8 = 0,
CH3_AL1_TRANS_COUNT_TRIG_1: u8 = 0,
CH3_AL1_TRANS_COUNT_TRIG_2: u8 = 0,
CH3_AL1_TRANS_COUNT_TRIG_3: u8 = 0,
};
/// Alias for channel 3 TRANS_COUNT register\n
pub const CH3_AL1_TRANS_COUNT_TRIG = Register(CH3_AL1_TRANS_COUNT_TRIG_val).init(base_address + 0xdc);
/// CH3_AL1_WRITE_ADDR
const CH3_AL1_WRITE_ADDR_val = packed struct {
CH3_AL1_WRITE_ADDR_0: u8 = 0,
CH3_AL1_WRITE_ADDR_1: u8 = 0,
CH3_AL1_WRITE_ADDR_2: u8 = 0,
CH3_AL1_WRITE_ADDR_3: u8 = 0,
};
/// Alias for channel 3 WRITE_ADDR register
pub const CH3_AL1_WRITE_ADDR = Register(CH3_AL1_WRITE_ADDR_val).init(base_address + 0xd8);
/// CH3_AL1_READ_ADDR
const CH3_AL1_READ_ADDR_val = packed struct {
CH3_AL1_READ_ADDR_0: u8 = 0,
CH3_AL1_READ_ADDR_1: u8 = 0,
CH3_AL1_READ_ADDR_2: u8 = 0,
CH3_AL1_READ_ADDR_3: u8 = 0,
};
/// Alias for channel 3 READ_ADDR register
pub const CH3_AL1_READ_ADDR = Register(CH3_AL1_READ_ADDR_val).init(base_address + 0xd4);
/// CH3_AL1_CTRL
const CH3_AL1_CTRL_val = packed struct {
CH3_AL1_CTRL_0: u8 = 0,
CH3_AL1_CTRL_1: u8 = 0,
CH3_AL1_CTRL_2: u8 = 0,
CH3_AL1_CTRL_3: u8 = 0,
};
/// Alias for channel 3 CTRL register
pub const CH3_AL1_CTRL = Register(CH3_AL1_CTRL_val).init(base_address + 0xd0);
/// CH3_CTRL_TRIG
const CH3_CTRL_TRIG_val = packed struct {
/// EN [0:0]
/// DMA Channel Enable.\n
EN: u1 = 0,
/// HIGH_PRIORITY [1:1]
/// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
HIGH_PRIORITY: u1 = 0,
/// DATA_SIZE [2:3]
/// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
DATA_SIZE: u2 = 0,
/// INCR_READ [4:4]
/// If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
INCR_READ: u1 = 0,
/// INCR_WRITE [5:5]
/// If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
INCR_WRITE: u1 = 0,
/// RING_SIZE [6:9]
/// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
RING_SIZE: u4 = 0,
/// RING_SEL [10:10]
/// Select whether RING_SIZE applies to read or write addresses.\n
RING_SEL: u1 = 0,
/// CHAIN_TO [11:14]
/// When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n
CHAIN_TO: u4 = 3,
/// TREQ_SEL [15:20]
/// Select a Transfer Request signal.\n
TREQ_SEL: u6 = 0,
/// IRQ_QUIET [21:21]
/// In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
IRQ_QUIET: u1 = 0,
/// BSWAP [22:22]
/// Apply byte-swap transformation to DMA data.\n
BSWAP: u1 = 0,
/// SNIFF_EN [23:23]
/// If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
SNIFF_EN: u1 = 0,
/// BUSY [24:24]
/// This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
BUSY: u1 = 0,
/// unused [25:28]
_unused25: u4 = 0,
/// WRITE_ERROR [29:29]
/// If 1, the channel received a write bus error. Write one to clear.\n
WRITE_ERROR: u1 = 0,
/// READ_ERROR [30:30]
/// If 1, the channel received a read bus error. Write one to clear.\n
READ_ERROR: u1 = 0,
/// AHB_ERROR [31:31]
/// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
AHB_ERROR: u1 = 0,
};
/// DMA Channel 3 Control and Status
pub const CH3_CTRL_TRIG = Register(CH3_CTRL_TRIG_val).init(base_address + 0xcc);
/// CH3_TRANS_COUNT
const CH3_TRANS_COUNT_val = packed struct {
CH3_TRANS_COUNT_0: u8 = 0,
CH3_TRANS_COUNT_1: u8 = 0,
CH3_TRANS_COUNT_2: u8 = 0,
CH3_TRANS_COUNT_3: u8 = 0,
};
/// DMA Channel 3 Transfer Count\n
pub const CH3_TRANS_COUNT = Register(CH3_TRANS_COUNT_val).init(base_address + 0xc8);
/// CH3_WRITE_ADDR
const CH3_WRITE_ADDR_val = packed struct {
CH3_WRITE_ADDR_0: u8 = 0,
CH3_WRITE_ADDR_1: u8 = 0,
CH3_WRITE_ADDR_2: u8 = 0,
CH3_WRITE_ADDR_3: u8 = 0,
};
/// DMA Channel 3 Write Address pointer\n
pub const CH3_WRITE_ADDR = Register(CH3_WRITE_ADDR_val).init(base_address + 0xc4);
/// CH3_READ_ADDR
const CH3_READ_ADDR_val = packed struct {
CH3_READ_ADDR_0: u8 = 0,
CH3_READ_ADDR_1: u8 = 0,
CH3_READ_ADDR_2: u8 = 0,
CH3_READ_ADDR_3: u8 = 0,
};
/// DMA Channel 3 Read Address pointer\n
pub const CH3_READ_ADDR = Register(CH3_READ_ADDR_val).init(base_address + 0xc0);
/// CH2_AL3_READ_ADDR_TRIG
const CH2_AL3_READ_ADDR_TRIG_val = packed struct {
CH2_AL3_READ_ADDR_TRIG_0: u8 = 0,
CH2_AL3_READ_ADDR_TRIG_1: u8 = 0,
CH2_AL3_READ_ADDR_TRIG_2: u8 = 0,
CH2_AL3_READ_ADDR_TRIG_3: u8 = 0,
};
/// Alias for channel 2 READ_ADDR register\n
pub const CH2_AL3_READ_ADDR_TRIG = Register(CH2_AL3_READ_ADDR_TRIG_val).init(base_address + 0xbc);
/// CH2_AL3_TRANS_COUNT
const CH2_AL3_TRANS_COUNT_val = packed struct {
CH2_AL3_TRANS_COUNT_0: u8 = 0,
CH2_AL3_TRANS_COUNT_1: u8 = 0,
CH2_AL3_TRANS_COUNT_2: u8 = 0,
CH2_AL3_TRANS_COUNT_3: u8 = 0,
};
/// Alias for channel 2 TRANS_COUNT register
pub const CH2_AL3_TRANS_COUNT = Register(CH2_AL3_TRANS_COUNT_val).init(base_address + 0xb8);
/// CH2_AL3_WRITE_ADDR
const CH2_AL3_WRITE_ADDR_val = packed struct {
CH2_AL3_WRITE_ADDR_0: u8 = 0,
CH2_AL3_WRITE_ADDR_1: u8 = 0,
CH2_AL3_WRITE_ADDR_2: u8 = 0,
CH2_AL3_WRITE_ADDR_3: u8 = 0,
};
/// Alias for channel 2 WRITE_ADDR register
pub const CH2_AL3_WRITE_ADDR = Register(CH2_AL3_WRITE_ADDR_val).init(base_address + 0xb4);
/// CH2_AL3_CTRL
const CH2_AL3_CTRL_val = packed struct {
CH2_AL3_CTRL_0: u8 = 0,
CH2_AL3_CTRL_1: u8 = 0,
CH2_AL3_CTRL_2: u8 = 0,
CH2_AL3_CTRL_3: u8 = 0,
};
/// Alias for channel 2 CTRL register
pub const CH2_AL3_CTRL = Register(CH2_AL3_CTRL_val).init(base_address + 0xb0);
/// CH2_AL2_WRITE_ADDR_TRIG
const CH2_AL2_WRITE_ADDR_TRIG_val = packed struct {
CH2_AL2_WRITE_ADDR_TRIG_0: u8 = 0,
CH2_AL2_WRITE_ADDR_TRIG_1: u8 = 0,
CH2_AL2_WRITE_ADDR_TRIG_2: u8 = 0,
CH2_AL2_WRITE_ADDR_TRIG_3: u8 = 0,
};
/// Alias for channel 2 WRITE_ADDR register\n
pub const CH2_AL2_WRITE_ADDR_TRIG = Register(CH2_AL2_WRITE_ADDR_TRIG_val).init(base_address + 0xac);
/// CH2_AL2_READ_ADDR
const CH2_AL2_READ_ADDR_val = packed struct {
CH2_AL2_READ_ADDR_0: u8 = 0,
CH2_AL2_READ_ADDR_1: u8 = 0,
CH2_AL2_READ_ADDR_2: u8 = 0,
CH2_AL2_READ_ADDR_3: u8 = 0,
};
/// Alias for channel 2 READ_ADDR register
pub const CH2_AL2_READ_ADDR = Register(CH2_AL2_READ_ADDR_val).init(base_address + 0xa8);
/// CH2_AL2_TRANS_COUNT
const CH2_AL2_TRANS_COUNT_val = packed struct {
CH2_AL2_TRANS_COUNT_0: u8 = 0,
CH2_AL2_TRANS_COUNT_1: u8 = 0,
CH2_AL2_TRANS_COUNT_2: u8 = 0,
CH2_AL2_TRANS_COUNT_3: u8 = 0,
};
/// Alias for channel 2 TRANS_COUNT register
pub const CH2_AL2_TRANS_COUNT = Register(CH2_AL2_TRANS_COUNT_val).init(base_address + 0xa4);
/// CH2_AL2_CTRL
const CH2_AL2_CTRL_val = packed struct {
CH2_AL2_CTRL_0: u8 = 0,
CH2_AL2_CTRL_1: u8 = 0,
CH2_AL2_CTRL_2: u8 = 0,
CH2_AL2_CTRL_3: u8 = 0,
};
/// Alias for channel 2 CTRL register
pub const CH2_AL2_CTRL = Register(CH2_AL2_CTRL_val).init(base_address + 0xa0);
/// CH2_AL1_TRANS_COUNT_TRIG
const CH2_AL1_TRANS_COUNT_TRIG_val = packed struct {
CH2_AL1_TRANS_COUNT_TRIG_0: u8 = 0,
CH2_AL1_TRANS_COUNT_TRIG_1: u8 = 0,
CH2_AL1_TRANS_COUNT_TRIG_2: u8 = 0,
CH2_AL1_TRANS_COUNT_TRIG_3: u8 = 0,
};
/// Alias for channel 2 TRANS_COUNT register\n
pub const CH2_AL1_TRANS_COUNT_TRIG = Register(CH2_AL1_TRANS_COUNT_TRIG_val).init(base_address + 0x9c);
/// CH2_AL1_WRITE_ADDR
const CH2_AL1_WRITE_ADDR_val = packed struct {
CH2_AL1_WRITE_ADDR_0: u8 = 0,
CH2_AL1_WRITE_ADDR_1: u8 = 0,
CH2_AL1_WRITE_ADDR_2: u8 = 0,
CH2_AL1_WRITE_ADDR_3: u8 = 0,
};
/// Alias for channel 2 WRITE_ADDR register
pub const CH2_AL1_WRITE_ADDR = Register(CH2_AL1_WRITE_ADDR_val).init(base_address + 0x98);
/// CH2_AL1_READ_ADDR
const CH2_AL1_READ_ADDR_val = packed struct {
CH2_AL1_READ_ADDR_0: u8 = 0,
CH2_AL1_READ_ADDR_1: u8 = 0,
CH2_AL1_READ_ADDR_2: u8 = 0,
CH2_AL1_READ_ADDR_3: u8 = 0,
};
/// Alias for channel 2 READ_ADDR register
pub const CH2_AL1_READ_ADDR = Register(CH2_AL1_READ_ADDR_val).init(base_address + 0x94);
/// CH2_AL1_CTRL
const CH2_AL1_CTRL_val = packed struct {
CH2_AL1_CTRL_0: u8 = 0,
CH2_AL1_CTRL_1: u8 = 0,
CH2_AL1_CTRL_2: u8 = 0,
CH2_AL1_CTRL_3: u8 = 0,
};
/// Alias for channel 2 CTRL register
pub const CH2_AL1_CTRL = Register(CH2_AL1_CTRL_val).init(base_address + 0x90);
/// CH2_CTRL_TRIG
const CH2_CTRL_TRIG_val = packed struct {
/// EN [0:0]
/// DMA Channel Enable.\n
EN: u1 = 0,
/// HIGH_PRIORITY [1:1]
/// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
HIGH_PRIORITY: u1 = 0,
/// DATA_SIZE [2:3]
/// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
DATA_SIZE: u2 = 0,
/// INCR_READ [4:4]
/// If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
INCR_READ: u1 = 0,
/// INCR_WRITE [5:5]
/// If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
INCR_WRITE: u1 = 0,
/// RING_SIZE [6:9]
/// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
RING_SIZE: u4 = 0,
/// RING_SEL [10:10]
/// Select whether RING_SIZE applies to read or write addresses.\n
RING_SEL: u1 = 0,
/// CHAIN_TO [11:14]
/// When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n
CHAIN_TO: u4 = 2,
/// TREQ_SEL [15:20]
/// Select a Transfer Request signal.\n
TREQ_SEL: u6 = 0,
/// IRQ_QUIET [21:21]
/// In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
IRQ_QUIET: u1 = 0,
/// BSWAP [22:22]
/// Apply byte-swap transformation to DMA data.\n
BSWAP: u1 = 0,
/// SNIFF_EN [23:23]
/// If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
SNIFF_EN: u1 = 0,
/// BUSY [24:24]
/// This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
BUSY: u1 = 0,
/// unused [25:28]
_unused25: u4 = 0,
/// WRITE_ERROR [29:29]
/// If 1, the channel received a write bus error. Write one to clear.\n
WRITE_ERROR: u1 = 0,
/// READ_ERROR [30:30]
/// If 1, the channel received a read bus error. Write one to clear.\n
READ_ERROR: u1 = 0,
/// AHB_ERROR [31:31]
/// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
AHB_ERROR: u1 = 0,
};
/// DMA Channel 2 Control and Status
pub const CH2_CTRL_TRIG = Register(CH2_CTRL_TRIG_val).init(base_address + 0x8c);
/// CH2_TRANS_COUNT
const CH2_TRANS_COUNT_val = packed struct {
CH2_TRANS_COUNT_0: u8 = 0,
CH2_TRANS_COUNT_1: u8 = 0,
CH2_TRANS_COUNT_2: u8 = 0,
CH2_TRANS_COUNT_3: u8 = 0,
};
/// DMA Channel 2 Transfer Count\n
pub const CH2_TRANS_COUNT = Register(CH2_TRANS_COUNT_val).init(base_address + 0x88);
/// CH2_WRITE_ADDR
const CH2_WRITE_ADDR_val = packed struct {
CH2_WRITE_ADDR_0: u8 = 0,
CH2_WRITE_ADDR_1: u8 = 0,
CH2_WRITE_ADDR_2: u8 = 0,
CH2_WRITE_ADDR_3: u8 = 0,
};
/// DMA Channel 2 Write Address pointer\n
pub const CH2_WRITE_ADDR = Register(CH2_WRITE_ADDR_val).init(base_address + 0x84);
/// CH2_READ_ADDR
const CH2_READ_ADDR_val = packed struct {
CH2_READ_ADDR_0: u8 = 0,
CH2_READ_ADDR_1: u8 = 0,
CH2_READ_ADDR_2: u8 = 0,
CH2_READ_ADDR_3: u8 = 0,
};
/// DMA Channel 2 Read Address pointer\n
pub const CH2_READ_ADDR = Register(CH2_READ_ADDR_val).init(base_address + 0x80);
/// CH1_AL3_READ_ADDR_TRIG
const CH1_AL3_READ_ADDR_TRIG_val = packed struct {
CH1_AL3_READ_ADDR_TRIG_0: u8 = 0,
CH1_AL3_READ_ADDR_TRIG_1: u8 = 0,
CH1_AL3_READ_ADDR_TRIG_2: u8 = 0,
CH1_AL3_READ_ADDR_TRIG_3: u8 = 0,
};
/// Alias for channel 1 READ_ADDR register\n
pub const CH1_AL3_READ_ADDR_TRIG = Register(CH1_AL3_READ_ADDR_TRIG_val).init(base_address + 0x7c);
/// CH1_AL3_TRANS_COUNT
const CH1_AL3_TRANS_COUNT_val = packed struct {
CH1_AL3_TRANS_COUNT_0: u8 = 0,
CH1_AL3_TRANS_COUNT_1: u8 = 0,
CH1_AL3_TRANS_COUNT_2: u8 = 0,
CH1_AL3_TRANS_COUNT_3: u8 = 0,
};
/// Alias for channel 1 TRANS_COUNT register
pub const CH1_AL3_TRANS_COUNT = Register(CH1_AL3_TRANS_COUNT_val).init(base_address + 0x78);
/// CH1_AL3_WRITE_ADDR
const CH1_AL3_WRITE_ADDR_val = packed struct {
CH1_AL3_WRITE_ADDR_0: u8 = 0,
CH1_AL3_WRITE_ADDR_1: u8 = 0,
CH1_AL3_WRITE_ADDR_2: u8 = 0,
CH1_AL3_WRITE_ADDR_3: u8 = 0,
};
/// Alias for channel 1 WRITE_ADDR register
pub const CH1_AL3_WRITE_ADDR = Register(CH1_AL3_WRITE_ADDR_val).init(base_address + 0x74);
/// CH1_AL3_CTRL
const CH1_AL3_CTRL_val = packed struct {
CH1_AL3_CTRL_0: u8 = 0,
CH1_AL3_CTRL_1: u8 = 0,
CH1_AL3_CTRL_2: u8 = 0,
CH1_AL3_CTRL_3: u8 = 0,
};
/// Alias for channel 1 CTRL register
pub const CH1_AL3_CTRL = Register(CH1_AL3_CTRL_val).init(base_address + 0x70);
/// CH1_AL2_WRITE_ADDR_TRIG
const CH1_AL2_WRITE_ADDR_TRIG_val = packed struct {
CH1_AL2_WRITE_ADDR_TRIG_0: u8 = 0,
CH1_AL2_WRITE_ADDR_TRIG_1: u8 = 0,
CH1_AL2_WRITE_ADDR_TRIG_2: u8 = 0,
CH1_AL2_WRITE_ADDR_TRIG_3: u8 = 0,
};
/// Alias for channel 1 WRITE_ADDR register\n
pub const CH1_AL2_WRITE_ADDR_TRIG = Register(CH1_AL2_WRITE_ADDR_TRIG_val).init(base_address + 0x6c);
/// CH1_AL2_READ_ADDR
const CH1_AL2_READ_ADDR_val = packed struct {
CH1_AL2_READ_ADDR_0: u8 = 0,
CH1_AL2_READ_ADDR_1: u8 = 0,
CH1_AL2_READ_ADDR_2: u8 = 0,
CH1_AL2_READ_ADDR_3: u8 = 0,
};
/// Alias for channel 1 READ_ADDR register
pub const CH1_AL2_READ_ADDR = Register(CH1_AL2_READ_ADDR_val).init(base_address + 0x68);
/// CH1_AL2_TRANS_COUNT
const CH1_AL2_TRANS_COUNT_val = packed struct {
CH1_AL2_TRANS_COUNT_0: u8 = 0,
CH1_AL2_TRANS_COUNT_1: u8 = 0,
CH1_AL2_TRANS_COUNT_2: u8 = 0,
CH1_AL2_TRANS_COUNT_3: u8 = 0,
};
/// Alias for channel 1 TRANS_COUNT register
pub const CH1_AL2_TRANS_COUNT = Register(CH1_AL2_TRANS_COUNT_val).init(base_address + 0x64);
/// CH1_AL2_CTRL
const CH1_AL2_CTRL_val = packed struct {
CH1_AL2_CTRL_0: u8 = 0,
CH1_AL2_CTRL_1: u8 = 0,
CH1_AL2_CTRL_2: u8 = 0,
CH1_AL2_CTRL_3: u8 = 0,
};
/// Alias for channel 1 CTRL register
pub const CH1_AL2_CTRL = Register(CH1_AL2_CTRL_val).init(base_address + 0x60);
/// CH1_AL1_TRANS_COUNT_TRIG
const CH1_AL1_TRANS_COUNT_TRIG_val = packed struct {
CH1_AL1_TRANS_COUNT_TRIG_0: u8 = 0,
CH1_AL1_TRANS_COUNT_TRIG_1: u8 = 0,
CH1_AL1_TRANS_COUNT_TRIG_2: u8 = 0,
CH1_AL1_TRANS_COUNT_TRIG_3: u8 = 0,
};
/// Alias for channel 1 TRANS_COUNT register\n
pub const CH1_AL1_TRANS_COUNT_TRIG = Register(CH1_AL1_TRANS_COUNT_TRIG_val).init(base_address + 0x5c);
/// CH1_AL1_WRITE_ADDR
const CH1_AL1_WRITE_ADDR_val = packed struct {
CH1_AL1_WRITE_ADDR_0: u8 = 0,
CH1_AL1_WRITE_ADDR_1: u8 = 0,
CH1_AL1_WRITE_ADDR_2: u8 = 0,
CH1_AL1_WRITE_ADDR_3: u8 = 0,
};
/// Alias for channel 1 WRITE_ADDR register
pub const CH1_AL1_WRITE_ADDR = Register(CH1_AL1_WRITE_ADDR_val).init(base_address + 0x58);
/// CH1_AL1_READ_ADDR
const CH1_AL1_READ_ADDR_val = packed struct {
CH1_AL1_READ_ADDR_0: u8 = 0,
CH1_AL1_READ_ADDR_1: u8 = 0,
CH1_AL1_READ_ADDR_2: u8 = 0,
CH1_AL1_READ_ADDR_3: u8 = 0,
};
/// Alias for channel 1 READ_ADDR register
pub const CH1_AL1_READ_ADDR = Register(CH1_AL1_READ_ADDR_val).init(base_address + 0x54);
/// CH1_AL1_CTRL
const CH1_AL1_CTRL_val = packed struct {
CH1_AL1_CTRL_0: u8 = 0,
CH1_AL1_CTRL_1: u8 = 0,
CH1_AL1_CTRL_2: u8 = 0,
CH1_AL1_CTRL_3: u8 = 0,
};
/// Alias for channel 1 CTRL register
pub const CH1_AL1_CTRL = Register(CH1_AL1_CTRL_val).init(base_address + 0x50);
/// CH1_CTRL_TRIG
const CH1_CTRL_TRIG_val = packed struct {
/// EN [0:0]
/// DMA Channel Enable.\n
EN: u1 = 0,
/// HIGH_PRIORITY [1:1]
/// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
HIGH_PRIORITY: u1 = 0,
/// DATA_SIZE [2:3]
/// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
DATA_SIZE: u2 = 0,
/// INCR_READ [4:4]
/// If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
INCR_READ: u1 = 0,
/// INCR_WRITE [5:5]
/// If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
INCR_WRITE: u1 = 0,
/// RING_SIZE [6:9]
/// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
RING_SIZE: u4 = 0,
/// RING_SEL [10:10]
/// Select whether RING_SIZE applies to read or write addresses.\n
RING_SEL: u1 = 0,
/// CHAIN_TO [11:14]
/// When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n
CHAIN_TO: u4 = 1,
/// TREQ_SEL [15:20]
/// Select a Transfer Request signal.\n
TREQ_SEL: u6 = 0,
/// IRQ_QUIET [21:21]
/// In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
IRQ_QUIET: u1 = 0,
/// BSWAP [22:22]
/// Apply byte-swap transformation to DMA data.\n
BSWAP: u1 = 0,
/// SNIFF_EN [23:23]
/// If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
SNIFF_EN: u1 = 0,
/// BUSY [24:24]
/// This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
BUSY: u1 = 0,
/// unused [25:28]
_unused25: u4 = 0,
/// WRITE_ERROR [29:29]
/// If 1, the channel received a write bus error. Write one to clear.\n
WRITE_ERROR: u1 = 0,
/// READ_ERROR [30:30]
/// If 1, the channel received a read bus error. Write one to clear.\n
READ_ERROR: u1 = 0,
/// AHB_ERROR [31:31]
/// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
AHB_ERROR: u1 = 0,
};
/// DMA Channel 1 Control and Status
pub const CH1_CTRL_TRIG = Register(CH1_CTRL_TRIG_val).init(base_address + 0x4c);
/// CH1_TRANS_COUNT
const CH1_TRANS_COUNT_val = packed struct {
CH1_TRANS_COUNT_0: u8 = 0,
CH1_TRANS_COUNT_1: u8 = 0,
CH1_TRANS_COUNT_2: u8 = 0,
CH1_TRANS_COUNT_3: u8 = 0,
};
/// DMA Channel 1 Transfer Count\n
pub const CH1_TRANS_COUNT = Register(CH1_TRANS_COUNT_val).init(base_address + 0x48);
/// CH1_WRITE_ADDR
const CH1_WRITE_ADDR_val = packed struct {
CH1_WRITE_ADDR_0: u8 = 0,
CH1_WRITE_ADDR_1: u8 = 0,
CH1_WRITE_ADDR_2: u8 = 0,
CH1_WRITE_ADDR_3: u8 = 0,
};
/// DMA Channel 1 Write Address pointer\n
pub const CH1_WRITE_ADDR = Register(CH1_WRITE_ADDR_val).init(base_address + 0x44);
/// CH1_READ_ADDR
const CH1_READ_ADDR_val = packed struct {
CH1_READ_ADDR_0: u8 = 0,
CH1_READ_ADDR_1: u8 = 0,
CH1_READ_ADDR_2: u8 = 0,
CH1_READ_ADDR_3: u8 = 0,
};
/// DMA Channel 1 Read Address pointer\n
pub const CH1_READ_ADDR = Register(CH1_READ_ADDR_val).init(base_address + 0x40);
/// CH0_AL3_READ_ADDR_TRIG
const CH0_AL3_READ_ADDR_TRIG_val = packed struct {
CH0_AL3_READ_ADDR_TRIG_0: u8 = 0,
CH0_AL3_READ_ADDR_TRIG_1: u8 = 0,
CH0_AL3_READ_ADDR_TRIG_2: u8 = 0,
CH0_AL3_READ_ADDR_TRIG_3: u8 = 0,
};
/// Alias for channel 0 READ_ADDR register\n
pub const CH0_AL3_READ_ADDR_TRIG = Register(CH0_AL3_READ_ADDR_TRIG_val).init(base_address + 0x3c);
/// CH0_AL3_TRANS_COUNT
const CH0_AL3_TRANS_COUNT_val = packed struct {
CH0_AL3_TRANS_COUNT_0: u8 = 0,
CH0_AL3_TRANS_COUNT_1: u8 = 0,
CH0_AL3_TRANS_COUNT_2: u8 = 0,
CH0_AL3_TRANS_COUNT_3: u8 = 0,
};
/// Alias for channel 0 TRANS_COUNT register
pub const CH0_AL3_TRANS_COUNT = Register(CH0_AL3_TRANS_COUNT_val).init(base_address + 0x38);
/// CH0_AL3_WRITE_ADDR
const CH0_AL3_WRITE_ADDR_val = packed struct {
CH0_AL3_WRITE_ADDR_0: u8 = 0,
CH0_AL3_WRITE_ADDR_1: u8 = 0,
CH0_AL3_WRITE_ADDR_2: u8 = 0,
CH0_AL3_WRITE_ADDR_3: u8 = 0,
};
/// Alias for channel 0 WRITE_ADDR register
pub const CH0_AL3_WRITE_ADDR = Register(CH0_AL3_WRITE_ADDR_val).init(base_address + 0x34);
/// CH0_AL3_CTRL
const CH0_AL3_CTRL_val = packed struct {
CH0_AL3_CTRL_0: u8 = 0,
CH0_AL3_CTRL_1: u8 = 0,
CH0_AL3_CTRL_2: u8 = 0,
CH0_AL3_CTRL_3: u8 = 0,
};
/// Alias for channel 0 CTRL register
pub const CH0_AL3_CTRL = Register(CH0_AL3_CTRL_val).init(base_address + 0x30);
/// CH0_AL2_WRITE_ADDR_TRIG
const CH0_AL2_WRITE_ADDR_TRIG_val = packed struct {
CH0_AL2_WRITE_ADDR_TRIG_0: u8 = 0,
CH0_AL2_WRITE_ADDR_TRIG_1: u8 = 0,
CH0_AL2_WRITE_ADDR_TRIG_2: u8 = 0,
CH0_AL2_WRITE_ADDR_TRIG_3: u8 = 0,
};
/// Alias for channel 0 WRITE_ADDR register\n
pub const CH0_AL2_WRITE_ADDR_TRIG = Register(CH0_AL2_WRITE_ADDR_TRIG_val).init(base_address + 0x2c);
/// CH0_AL2_READ_ADDR
const CH0_AL2_READ_ADDR_val = packed struct {
CH0_AL2_READ_ADDR_0: u8 = 0,
CH0_AL2_READ_ADDR_1: u8 = 0,
CH0_AL2_READ_ADDR_2: u8 = 0,
CH0_AL2_READ_ADDR_3: u8 = 0,
};
/// Alias for channel 0 READ_ADDR register
pub const CH0_AL2_READ_ADDR = Register(CH0_AL2_READ_ADDR_val).init(base_address + 0x28);
/// CH0_AL2_TRANS_COUNT
const CH0_AL2_TRANS_COUNT_val = packed struct {
CH0_AL2_TRANS_COUNT_0: u8 = 0,
CH0_AL2_TRANS_COUNT_1: u8 = 0,
CH0_AL2_TRANS_COUNT_2: u8 = 0,
CH0_AL2_TRANS_COUNT_3: u8 = 0,
};
/// Alias for channel 0 TRANS_COUNT register
pub const CH0_AL2_TRANS_COUNT = Register(CH0_AL2_TRANS_COUNT_val).init(base_address + 0x24);
/// CH0_AL2_CTRL
const CH0_AL2_CTRL_val = packed struct {
CH0_AL2_CTRL_0: u8 = 0,
CH0_AL2_CTRL_1: u8 = 0,
CH0_AL2_CTRL_2: u8 = 0,
CH0_AL2_CTRL_3: u8 = 0,
};
/// Alias for channel 0 CTRL register
pub const CH0_AL2_CTRL = Register(CH0_AL2_CTRL_val).init(base_address + 0x20);
/// CH0_AL1_TRANS_COUNT_TRIG
const CH0_AL1_TRANS_COUNT_TRIG_val = packed struct {
CH0_AL1_TRANS_COUNT_TRIG_0: u8 = 0,
CH0_AL1_TRANS_COUNT_TRIG_1: u8 = 0,
CH0_AL1_TRANS_COUNT_TRIG_2: u8 = 0,
CH0_AL1_TRANS_COUNT_TRIG_3: u8 = 0,
};
/// Alias for channel 0 TRANS_COUNT register\n
pub const CH0_AL1_TRANS_COUNT_TRIG = Register(CH0_AL1_TRANS_COUNT_TRIG_val).init(base_address + 0x1c);
/// CH0_AL1_WRITE_ADDR
const CH0_AL1_WRITE_ADDR_val = packed struct {
CH0_AL1_WRITE_ADDR_0: u8 = 0,
CH0_AL1_WRITE_ADDR_1: u8 = 0,
CH0_AL1_WRITE_ADDR_2: u8 = 0,
CH0_AL1_WRITE_ADDR_3: u8 = 0,
};
/// Alias for channel 0 WRITE_ADDR register
pub const CH0_AL1_WRITE_ADDR = Register(CH0_AL1_WRITE_ADDR_val).init(base_address + 0x18);
/// CH0_AL1_READ_ADDR
const CH0_AL1_READ_ADDR_val = packed struct {
CH0_AL1_READ_ADDR_0: u8 = 0,
CH0_AL1_READ_ADDR_1: u8 = 0,
CH0_AL1_READ_ADDR_2: u8 = 0,
CH0_AL1_READ_ADDR_3: u8 = 0,
};
/// Alias for channel 0 READ_ADDR register
pub const CH0_AL1_READ_ADDR = Register(CH0_AL1_READ_ADDR_val).init(base_address + 0x14);
/// CH0_AL1_CTRL
const CH0_AL1_CTRL_val = packed struct {
CH0_AL1_CTRL_0: u8 = 0,
CH0_AL1_CTRL_1: u8 = 0,
CH0_AL1_CTRL_2: u8 = 0,
CH0_AL1_CTRL_3: u8 = 0,
};
/// Alias for channel 0 CTRL register
pub const CH0_AL1_CTRL = Register(CH0_AL1_CTRL_val).init(base_address + 0x10);
/// CH0_CTRL_TRIG
const CH0_CTRL_TRIG_val = packed struct {
/// EN [0:0]
/// DMA Channel Enable.\n
EN: u1 = 0,
/// HIGH_PRIORITY [1:1]
/// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
HIGH_PRIORITY: u1 = 0,
/// DATA_SIZE [2:3]
/// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
DATA_SIZE: u2 = 0,
/// INCR_READ [4:4]
/// If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
INCR_READ: u1 = 0,
/// INCR_WRITE [5:5]
/// If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
INCR_WRITE: u1 = 0,
/// RING_SIZE [6:9]
/// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
RING_SIZE: u4 = 0,
/// RING_SEL [10:10]
/// Select whether RING_SIZE applies to read or write addresses.\n
RING_SEL: u1 = 0,
/// CHAIN_TO [11:14]
/// When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n
CHAIN_TO: u4 = 0,
/// TREQ_SEL [15:20]
/// Select a Transfer Request signal.\n
TREQ_SEL: u6 = 0,
/// IRQ_QUIET [21:21]
/// In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
IRQ_QUIET: u1 = 0,
/// BSWAP [22:22]
/// Apply byte-swap transformation to DMA data.\n
BSWAP: u1 = 0,
/// SNIFF_EN [23:23]
/// If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
SNIFF_EN: u1 = 0,
/// BUSY [24:24]
/// This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
BUSY: u1 = 0,
/// unused [25:28]
_unused25: u4 = 0,
/// WRITE_ERROR [29:29]
/// If 1, the channel received a write bus error. Write one to clear.\n
WRITE_ERROR: u1 = 0,
/// READ_ERROR [30:30]
/// If 1, the channel received a read bus error. Write one to clear.\n
READ_ERROR: u1 = 0,
/// AHB_ERROR [31:31]
/// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
AHB_ERROR: u1 = 0,
};
/// DMA Channel 0 Control and Status
pub const CH0_CTRL_TRIG = Register(CH0_CTRL_TRIG_val).init(base_address + 0xc);
/// CH0_TRANS_COUNT
const CH0_TRANS_COUNT_val = packed struct {
CH0_TRANS_COUNT_0: u8 = 0,
CH0_TRANS_COUNT_1: u8 = 0,
CH0_TRANS_COUNT_2: u8 = 0,
CH0_TRANS_COUNT_3: u8 = 0,
};
/// DMA Channel 0 Transfer Count\n
pub const CH0_TRANS_COUNT = Register(CH0_TRANS_COUNT_val).init(base_address + 0x8);
/// CH0_WRITE_ADDR
const CH0_WRITE_ADDR_val = packed struct {
CH0_WRITE_ADDR_0: u8 = 0,
CH0_WRITE_ADDR_1: u8 = 0,
CH0_WRITE_ADDR_2: u8 = 0,
CH0_WRITE_ADDR_3: u8 = 0,
};
/// DMA Channel 0 Write Address pointer\n
pub const CH0_WRITE_ADDR = Register(CH0_WRITE_ADDR_val).init(base_address + 0x4);
/// CH0_READ_ADDR
const CH0_READ_ADDR_val = packed struct {
CH0_READ_ADDR_0: u8 = 0,
CH0_READ_ADDR_1: u8 = 0,
CH0_READ_ADDR_2: u8 = 0,
CH0_READ_ADDR_3: u8 = 0,
};
/// DMA Channel 0 Read Address pointer\n
pub const CH0_READ_ADDR = Register(CH0_READ_ADDR_val).init(base_address + 0x0);
};
/// DPRAM layout for USB device.
pub const USBCTRL_DPRAM = struct {
const base_address = 0x50100000;
/// EP15_OUT_BUFFER_CONTROL
const EP15_OUT_BUFFER_CONTROL_val = packed struct {
/// LENGTH_0 [0:9]
/// The length of the data in buffer 1.
LENGTH_0: u10 = 0,
/// AVAILABLE_0 [10:10]
/// Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_0: u1 = 0,
/// STALL [11:11]
/// Reply with a stall (valid for both buffers).
STALL: u1 = 0,
/// RESET [12:12]
/// Reset the buffer selector to buffer 0.
RESET: u1 = 0,
/// PID_0 [13:13]
/// The data pid of buffer 0.
PID_0: u1 = 0,
/// LAST_0 [14:14]
/// Buffer 0 is the last buffer of the transfer.
LAST_0: u1 = 0,
/// FULL_0 [15:15]
/// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_0: u1 = 0,
/// LENGTH_1 [16:25]
/// The length of the data in buffer 1.
LENGTH_1: u10 = 0,
/// AVAILABLE_1 [26:26]
/// Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_1: u1 = 0,
/// DOUBLE_BUFFER_ISO_OFFSET [27:28]
/// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
DOUBLE_BUFFER_ISO_OFFSET: u2 = 0,
/// PID_1 [29:29]
/// The data pid of buffer 1.
PID_1: u1 = 0,
/// LAST_1 [30:30]
/// Buffer 1 is the last buffer of the transfer.
LAST_1: u1 = 0,
/// FULL_1 [31:31]
/// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_1: u1 = 0,
};
/// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
pub const EP15_OUT_BUFFER_CONTROL = Register(EP15_OUT_BUFFER_CONTROL_val).init(base_address + 0xfc);
/// EP15_IN_BUFFER_CONTROL
const EP15_IN_BUFFER_CONTROL_val = packed struct {
/// LENGTH_0 [0:9]
/// The length of the data in buffer 1.
LENGTH_0: u10 = 0,
/// AVAILABLE_0 [10:10]
/// Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_0: u1 = 0,
/// STALL [11:11]
/// Reply with a stall (valid for both buffers).
STALL: u1 = 0,
/// RESET [12:12]
/// Reset the buffer selector to buffer 0.
RESET: u1 = 0,
/// PID_0 [13:13]
/// The data pid of buffer 0.
PID_0: u1 = 0,
/// LAST_0 [14:14]
/// Buffer 0 is the last buffer of the transfer.
LAST_0: u1 = 0,
/// FULL_0 [15:15]
/// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_0: u1 = 0,
/// LENGTH_1 [16:25]
/// The length of the data in buffer 1.
LENGTH_1: u10 = 0,
/// AVAILABLE_1 [26:26]
/// Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_1: u1 = 0,
/// DOUBLE_BUFFER_ISO_OFFSET [27:28]
/// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
DOUBLE_BUFFER_ISO_OFFSET: u2 = 0,
/// PID_1 [29:29]
/// The data pid of buffer 1.
PID_1: u1 = 0,
/// LAST_1 [30:30]
/// Buffer 1 is the last buffer of the transfer.
LAST_1: u1 = 0,
/// FULL_1 [31:31]
/// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_1: u1 = 0,
};
/// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
pub const EP15_IN_BUFFER_CONTROL = Register(EP15_IN_BUFFER_CONTROL_val).init(base_address + 0xf8);
/// EP14_OUT_BUFFER_CONTROL
const EP14_OUT_BUFFER_CONTROL_val = packed struct {
/// LENGTH_0 [0:9]
/// The length of the data in buffer 1.
LENGTH_0: u10 = 0,
/// AVAILABLE_0 [10:10]
/// Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_0: u1 = 0,
/// STALL [11:11]
/// Reply with a stall (valid for both buffers).
STALL: u1 = 0,
/// RESET [12:12]
/// Reset the buffer selector to buffer 0.
RESET: u1 = 0,
/// PID_0 [13:13]
/// The data pid of buffer 0.
PID_0: u1 = 0,
/// LAST_0 [14:14]
/// Buffer 0 is the last buffer of the transfer.
LAST_0: u1 = 0,
/// FULL_0 [15:15]
/// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_0: u1 = 0,
/// LENGTH_1 [16:25]
/// The length of the data in buffer 1.
LENGTH_1: u10 = 0,
/// AVAILABLE_1 [26:26]
/// Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_1: u1 = 0,
/// DOUBLE_BUFFER_ISO_OFFSET [27:28]
/// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
DOUBLE_BUFFER_ISO_OFFSET: u2 = 0,
/// PID_1 [29:29]
/// The data pid of buffer 1.
PID_1: u1 = 0,
/// LAST_1 [30:30]
/// Buffer 1 is the last buffer of the transfer.
LAST_1: u1 = 0,
/// FULL_1 [31:31]
/// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_1: u1 = 0,
};
/// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
pub const EP14_OUT_BUFFER_CONTROL = Register(EP14_OUT_BUFFER_CONTROL_val).init(base_address + 0xf4);
/// EP14_IN_BUFFER_CONTROL
const EP14_IN_BUFFER_CONTROL_val = packed struct {
/// LENGTH_0 [0:9]
/// The length of the data in buffer 1.
LENGTH_0: u10 = 0,
/// AVAILABLE_0 [10:10]
/// Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_0: u1 = 0,
/// STALL [11:11]
/// Reply with a stall (valid for both buffers).
STALL: u1 = 0,
/// RESET [12:12]
/// Reset the buffer selector to buffer 0.
RESET: u1 = 0,
/// PID_0 [13:13]
/// The data pid of buffer 0.
PID_0: u1 = 0,
/// LAST_0 [14:14]
/// Buffer 0 is the last buffer of the transfer.
LAST_0: u1 = 0,
/// FULL_0 [15:15]
/// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_0: u1 = 0,
/// LENGTH_1 [16:25]
/// The length of the data in buffer 1.
LENGTH_1: u10 = 0,
/// AVAILABLE_1 [26:26]
/// Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_1: u1 = 0,
/// DOUBLE_BUFFER_ISO_OFFSET [27:28]
/// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
DOUBLE_BUFFER_ISO_OFFSET: u2 = 0,
/// PID_1 [29:29]
/// The data pid of buffer 1.
PID_1: u1 = 0,
/// LAST_1 [30:30]
/// Buffer 1 is the last buffer of the transfer.
LAST_1: u1 = 0,
/// FULL_1 [31:31]
/// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_1: u1 = 0,
};
/// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
pub const EP14_IN_BUFFER_CONTROL = Register(EP14_IN_BUFFER_CONTROL_val).init(base_address + 0xf0);
/// EP13_OUT_BUFFER_CONTROL
const EP13_OUT_BUFFER_CONTROL_val = packed struct {
/// LENGTH_0 [0:9]
/// The length of the data in buffer 1.
LENGTH_0: u10 = 0,
/// AVAILABLE_0 [10:10]
/// Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_0: u1 = 0,
/// STALL [11:11]
/// Reply with a stall (valid for both buffers).
STALL: u1 = 0,
/// RESET [12:12]
/// Reset the buffer selector to buffer 0.
RESET: u1 = 0,
/// PID_0 [13:13]
/// The data pid of buffer 0.
PID_0: u1 = 0,
/// LAST_0 [14:14]
/// Buffer 0 is the last buffer of the transfer.
LAST_0: u1 = 0,
/// FULL_0 [15:15]
/// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_0: u1 = 0,
/// LENGTH_1 [16:25]
/// The length of the data in buffer 1.
LENGTH_1: u10 = 0,
/// AVAILABLE_1 [26:26]
/// Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_1: u1 = 0,
/// DOUBLE_BUFFER_ISO_OFFSET [27:28]
/// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
DOUBLE_BUFFER_ISO_OFFSET: u2 = 0,
/// PID_1 [29:29]
/// The data pid of buffer 1.
PID_1: u1 = 0,
/// LAST_1 [30:30]
/// Buffer 1 is the last buffer of the transfer.
LAST_1: u1 = 0,
/// FULL_1 [31:31]
/// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_1: u1 = 0,
};
/// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
pub const EP13_OUT_BUFFER_CONTROL = Register(EP13_OUT_BUFFER_CONTROL_val).init(base_address + 0xec);
/// EP13_IN_BUFFER_CONTROL
const EP13_IN_BUFFER_CONTROL_val = packed struct {
/// LENGTH_0 [0:9]
/// The length of the data in buffer 1.
LENGTH_0: u10 = 0,
/// AVAILABLE_0 [10:10]
/// Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_0: u1 = 0,
/// STALL [11:11]
/// Reply with a stall (valid for both buffers).
STALL: u1 = 0,
/// RESET [12:12]
/// Reset the buffer selector to buffer 0.
RESET: u1 = 0,
/// PID_0 [13:13]
/// The data pid of buffer 0.
PID_0: u1 = 0,
/// LAST_0 [14:14]
/// Buffer 0 is the last buffer of the transfer.
LAST_0: u1 = 0,
/// FULL_0 [15:15]
/// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_0: u1 = 0,
/// LENGTH_1 [16:25]
/// The length of the data in buffer 1.
LENGTH_1: u10 = 0,
/// AVAILABLE_1 [26:26]
/// Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_1: u1 = 0,
/// DOUBLE_BUFFER_ISO_OFFSET [27:28]
/// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
DOUBLE_BUFFER_ISO_OFFSET: u2 = 0,
/// PID_1 [29:29]
/// The data pid of buffer 1.
PID_1: u1 = 0,
/// LAST_1 [30:30]
/// Buffer 1 is the last buffer of the transfer.
LAST_1: u1 = 0,
/// FULL_1 [31:31]
/// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_1: u1 = 0,
};
/// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
pub const EP13_IN_BUFFER_CONTROL = Register(EP13_IN_BUFFER_CONTROL_val).init(base_address + 0xe8);
/// EP12_OUT_BUFFER_CONTROL
const EP12_OUT_BUFFER_CONTROL_val = packed struct {
/// LENGTH_0 [0:9]
/// The length of the data in buffer 1.
LENGTH_0: u10 = 0,
/// AVAILABLE_0 [10:10]
/// Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_0: u1 = 0,
/// STALL [11:11]
/// Reply with a stall (valid for both buffers).
STALL: u1 = 0,
/// RESET [12:12]
/// Reset the buffer selector to buffer 0.
RESET: u1 = 0,
/// PID_0 [13:13]
/// The data pid of buffer 0.
PID_0: u1 = 0,
/// LAST_0 [14:14]
/// Buffer 0 is the last buffer of the transfer.
LAST_0: u1 = 0,
/// FULL_0 [15:15]
/// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_0: u1 = 0,
/// LENGTH_1 [16:25]
/// The length of the data in buffer 1.
LENGTH_1: u10 = 0,
/// AVAILABLE_1 [26:26]
/// Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_1: u1 = 0,
/// DOUBLE_BUFFER_ISO_OFFSET [27:28]
/// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
DOUBLE_BUFFER_ISO_OFFSET: u2 = 0,
/// PID_1 [29:29]
/// The data pid of buffer 1.
PID_1: u1 = 0,
/// LAST_1 [30:30]
/// Buffer 1 is the last buffer of the transfer.
LAST_1: u1 = 0,
/// FULL_1 [31:31]
/// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_1: u1 = 0,
};
/// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
pub const EP12_OUT_BUFFER_CONTROL = Register(EP12_OUT_BUFFER_CONTROL_val).init(base_address + 0xe4);
/// EP12_IN_BUFFER_CONTROL
const EP12_IN_BUFFER_CONTROL_val = packed struct {
/// LENGTH_0 [0:9]
/// The length of the data in buffer 1.
LENGTH_0: u10 = 0,
/// AVAILABLE_0 [10:10]
/// Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_0: u1 = 0,
/// STALL [11:11]
/// Reply with a stall (valid for both buffers).
STALL: u1 = 0,
/// RESET [12:12]
/// Reset the buffer selector to buffer 0.
RESET: u1 = 0,
/// PID_0 [13:13]
/// The data pid of buffer 0.
PID_0: u1 = 0,
/// LAST_0 [14:14]
/// Buffer 0 is the last buffer of the transfer.
LAST_0: u1 = 0,
/// FULL_0 [15:15]
/// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_0: u1 = 0,
/// LENGTH_1 [16:25]
/// The length of the data in buffer 1.
LENGTH_1: u10 = 0,
/// AVAILABLE_1 [26:26]
/// Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_1: u1 = 0,
/// DOUBLE_BUFFER_ISO_OFFSET [27:28]
/// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
DOUBLE_BUFFER_ISO_OFFSET: u2 = 0,
/// PID_1 [29:29]
/// The data pid of buffer 1.
PID_1: u1 = 0,
/// LAST_1 [30:30]
/// Buffer 1 is the last buffer of the transfer.
LAST_1: u1 = 0,
/// FULL_1 [31:31]
/// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_1: u1 = 0,
};
/// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
pub const EP12_IN_BUFFER_CONTROL = Register(EP12_IN_BUFFER_CONTROL_val).init(base_address + 0xe0);
/// EP11_OUT_BUFFER_CONTROL
const EP11_OUT_BUFFER_CONTROL_val = packed struct {
/// LENGTH_0 [0:9]
/// The length of the data in buffer 1.
LENGTH_0: u10 = 0,
/// AVAILABLE_0 [10:10]
/// Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_0: u1 = 0,
/// STALL [11:11]
/// Reply with a stall (valid for both buffers).
STALL: u1 = 0,
/// RESET [12:12]
/// Reset the buffer selector to buffer 0.
RESET: u1 = 0,
/// PID_0 [13:13]
/// The data pid of buffer 0.
PID_0: u1 = 0,
/// LAST_0 [14:14]
/// Buffer 0 is the last buffer of the transfer.
LAST_0: u1 = 0,
/// FULL_0 [15:15]
/// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_0: u1 = 0,
/// LENGTH_1 [16:25]
/// The length of the data in buffer 1.
LENGTH_1: u10 = 0,
/// AVAILABLE_1 [26:26]
/// Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_1: u1 = 0,
/// DOUBLE_BUFFER_ISO_OFFSET [27:28]
/// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
DOUBLE_BUFFER_ISO_OFFSET: u2 = 0,
/// PID_1 [29:29]
/// The data pid of buffer 1.
PID_1: u1 = 0,
/// LAST_1 [30:30]
/// Buffer 1 is the last buffer of the transfer.
LAST_1: u1 = 0,
/// FULL_1 [31:31]
/// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_1: u1 = 0,
};
/// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
pub const EP11_OUT_BUFFER_CONTROL = Register(EP11_OUT_BUFFER_CONTROL_val).init(base_address + 0xdc);
/// EP11_IN_BUFFER_CONTROL
const EP11_IN_BUFFER_CONTROL_val = packed struct {
/// LENGTH_0 [0:9]
/// The length of the data in buffer 1.
LENGTH_0: u10 = 0,
/// AVAILABLE_0 [10:10]
/// Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_0: u1 = 0,
/// STALL [11:11]
/// Reply with a stall (valid for both buffers).
STALL: u1 = 0,
/// RESET [12:12]
/// Reset the buffer selector to buffer 0.
RESET: u1 = 0,
/// PID_0 [13:13]
/// The data pid of buffer 0.
PID_0: u1 = 0,
/// LAST_0 [14:14]
/// Buffer 0 is the last buffer of the transfer.
LAST_0: u1 = 0,
/// FULL_0 [15:15]
/// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_0: u1 = 0,
/// LENGTH_1 [16:25]
/// The length of the data in buffer 1.
LENGTH_1: u10 = 0,
/// AVAILABLE_1 [26:26]
/// Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_1: u1 = 0,
/// DOUBLE_BUFFER_ISO_OFFSET [27:28]
/// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
DOUBLE_BUFFER_ISO_OFFSET: u2 = 0,
/// PID_1 [29:29]
/// The data pid of buffer 1.
PID_1: u1 = 0,
/// LAST_1 [30:30]
/// Buffer 1 is the last buffer of the transfer.
LAST_1: u1 = 0,
/// FULL_1 [31:31]
/// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_1: u1 = 0,
};
/// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
pub const EP11_IN_BUFFER_CONTROL = Register(EP11_IN_BUFFER_CONTROL_val).init(base_address + 0xd8);
/// EP10_OUT_BUFFER_CONTROL
const EP10_OUT_BUFFER_CONTROL_val = packed struct {
/// LENGTH_0 [0:9]
/// The length of the data in buffer 1.
LENGTH_0: u10 = 0,
/// AVAILABLE_0 [10:10]
/// Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_0: u1 = 0,
/// STALL [11:11]
/// Reply with a stall (valid for both buffers).
STALL: u1 = 0,
/// RESET [12:12]
/// Reset the buffer selector to buffer 0.
RESET: u1 = 0,
/// PID_0 [13:13]
/// The data pid of buffer 0.
PID_0: u1 = 0,
/// LAST_0 [14:14]
/// Buffer 0 is the last buffer of the transfer.
LAST_0: u1 = 0,
/// FULL_0 [15:15]
/// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_0: u1 = 0,
/// LENGTH_1 [16:25]
/// The length of the data in buffer 1.
LENGTH_1: u10 = 0,
/// AVAILABLE_1 [26:26]
/// Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_1: u1 = 0,
/// DOUBLE_BUFFER_ISO_OFFSET [27:28]
/// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
DOUBLE_BUFFER_ISO_OFFSET: u2 = 0,
/// PID_1 [29:29]
/// The data pid of buffer 1.
PID_1: u1 = 0,
/// LAST_1 [30:30]
/// Buffer 1 is the last buffer of the transfer.
LAST_1: u1 = 0,
/// FULL_1 [31:31]
/// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_1: u1 = 0,
};
/// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
pub const EP10_OUT_BUFFER_CONTROL = Register(EP10_OUT_BUFFER_CONTROL_val).init(base_address + 0xd4);
/// EP10_IN_BUFFER_CONTROL
const EP10_IN_BUFFER_CONTROL_val = packed struct {
/// LENGTH_0 [0:9]
/// The length of the data in buffer 1.
LENGTH_0: u10 = 0,
/// AVAILABLE_0 [10:10]
/// Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_0: u1 = 0,
/// STALL [11:11]
/// Reply with a stall (valid for both buffers).
STALL: u1 = 0,
/// RESET [12:12]
/// Reset the buffer selector to buffer 0.
RESET: u1 = 0,
/// PID_0 [13:13]
/// The data pid of buffer 0.
PID_0: u1 = 0,
/// LAST_0 [14:14]
/// Buffer 0 is the last buffer of the transfer.
LAST_0: u1 = 0,
/// FULL_0 [15:15]
/// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_0: u1 = 0,
/// LENGTH_1 [16:25]
/// The length of the data in buffer 1.
LENGTH_1: u10 = 0,
/// AVAILABLE_1 [26:26]
/// Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_1: u1 = 0,
/// DOUBLE_BUFFER_ISO_OFFSET [27:28]
/// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
DOUBLE_BUFFER_ISO_OFFSET: u2 = 0,
/// PID_1 [29:29]
/// The data pid of buffer 1.
PID_1: u1 = 0,
/// LAST_1 [30:30]
/// Buffer 1 is the last buffer of the transfer.
LAST_1: u1 = 0,
/// FULL_1 [31:31]
/// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_1: u1 = 0,
};
/// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
pub const EP10_IN_BUFFER_CONTROL = Register(EP10_IN_BUFFER_CONTROL_val).init(base_address + 0xd0);
/// EP9_OUT_BUFFER_CONTROL
const EP9_OUT_BUFFER_CONTROL_val = packed struct {
/// LENGTH_0 [0:9]
/// The length of the data in buffer 1.
LENGTH_0: u10 = 0,
/// AVAILABLE_0 [10:10]
/// Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_0: u1 = 0,
/// STALL [11:11]
/// Reply with a stall (valid for both buffers).
STALL: u1 = 0,
/// RESET [12:12]
/// Reset the buffer selector to buffer 0.
RESET: u1 = 0,
/// PID_0 [13:13]
/// The data pid of buffer 0.
PID_0: u1 = 0,
/// LAST_0 [14:14]
/// Buffer 0 is the last buffer of the transfer.
LAST_0: u1 = 0,
/// FULL_0 [15:15]
/// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_0: u1 = 0,
/// LENGTH_1 [16:25]
/// The length of the data in buffer 1.
LENGTH_1: u10 = 0,
/// AVAILABLE_1 [26:26]
/// Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_1: u1 = 0,
/// DOUBLE_BUFFER_ISO_OFFSET [27:28]
/// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
DOUBLE_BUFFER_ISO_OFFSET: u2 = 0,
/// PID_1 [29:29]
/// The data pid of buffer 1.
PID_1: u1 = 0,
/// LAST_1 [30:30]
/// Buffer 1 is the last buffer of the transfer.
LAST_1: u1 = 0,
/// FULL_1 [31:31]
/// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_1: u1 = 0,
};
/// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
pub const EP9_OUT_BUFFER_CONTROL = Register(EP9_OUT_BUFFER_CONTROL_val).init(base_address + 0xcc);
/// EP9_IN_BUFFER_CONTROL
const EP9_IN_BUFFER_CONTROL_val = packed struct {
/// LENGTH_0 [0:9]
/// The length of the data in buffer 1.
LENGTH_0: u10 = 0,
/// AVAILABLE_0 [10:10]
/// Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_0: u1 = 0,
/// STALL [11:11]
/// Reply with a stall (valid for both buffers).
STALL: u1 = 0,
/// RESET [12:12]
/// Reset the buffer selector to buffer 0.
RESET: u1 = 0,
/// PID_0 [13:13]
/// The data pid of buffer 0.
PID_0: u1 = 0,
/// LAST_0 [14:14]
/// Buffer 0 is the last buffer of the transfer.
LAST_0: u1 = 0,
/// FULL_0 [15:15]
/// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_0: u1 = 0,
/// LENGTH_1 [16:25]
/// The length of the data in buffer 1.
LENGTH_1: u10 = 0,
/// AVAILABLE_1 [26:26]
/// Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_1: u1 = 0,
/// DOUBLE_BUFFER_ISO_OFFSET [27:28]
/// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
DOUBLE_BUFFER_ISO_OFFSET: u2 = 0,
/// PID_1 [29:29]
/// The data pid of buffer 1.
PID_1: u1 = 0,
/// LAST_1 [30:30]
/// Buffer 1 is the last buffer of the transfer.
LAST_1: u1 = 0,
/// FULL_1 [31:31]
/// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_1: u1 = 0,
};
/// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
pub const EP9_IN_BUFFER_CONTROL = Register(EP9_IN_BUFFER_CONTROL_val).init(base_address + 0xc8);
/// EP8_OUT_BUFFER_CONTROL
const EP8_OUT_BUFFER_CONTROL_val = packed struct {
/// LENGTH_0 [0:9]
/// The length of the data in buffer 1.
LENGTH_0: u10 = 0,
/// AVAILABLE_0 [10:10]
/// Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_0: u1 = 0,
/// STALL [11:11]
/// Reply with a stall (valid for both buffers).
STALL: u1 = 0,
/// RESET [12:12]
/// Reset the buffer selector to buffer 0.
RESET: u1 = 0,
/// PID_0 [13:13]
/// The data pid of buffer 0.
PID_0: u1 = 0,
/// LAST_0 [14:14]
/// Buffer 0 is the last buffer of the transfer.
LAST_0: u1 = 0,
/// FULL_0 [15:15]
/// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_0: u1 = 0,
/// LENGTH_1 [16:25]
/// The length of the data in buffer 1.
LENGTH_1: u10 = 0,
/// AVAILABLE_1 [26:26]
/// Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_1: u1 = 0,
/// DOUBLE_BUFFER_ISO_OFFSET [27:28]
/// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
DOUBLE_BUFFER_ISO_OFFSET: u2 = 0,
/// PID_1 [29:29]
/// The data pid of buffer 1.
PID_1: u1 = 0,
/// LAST_1 [30:30]
/// Buffer 1 is the last buffer of the transfer.
LAST_1: u1 = 0,
/// FULL_1 [31:31]
/// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_1: u1 = 0,
};
/// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
pub const EP8_OUT_BUFFER_CONTROL = Register(EP8_OUT_BUFFER_CONTROL_val).init(base_address + 0xc4);
/// EP8_IN_BUFFER_CONTROL
const EP8_IN_BUFFER_CONTROL_val = packed struct {
/// LENGTH_0 [0:9]
/// The length of the data in buffer 1.
LENGTH_0: u10 = 0,
/// AVAILABLE_0 [10:10]
/// Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_0: u1 = 0,
/// STALL [11:11]
/// Reply with a stall (valid for both buffers).
STALL: u1 = 0,
/// RESET [12:12]
/// Reset the buffer selector to buffer 0.
RESET: u1 = 0,
/// PID_0 [13:13]
/// The data pid of buffer 0.
PID_0: u1 = 0,
/// LAST_0 [14:14]
/// Buffer 0 is the last buffer of the transfer.
LAST_0: u1 = 0,
/// FULL_0 [15:15]
/// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_0: u1 = 0,
/// LENGTH_1 [16:25]
/// The length of the data in buffer 1.
LENGTH_1: u10 = 0,
/// AVAILABLE_1 [26:26]
/// Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_1: u1 = 0,
/// DOUBLE_BUFFER_ISO_OFFSET [27:28]
/// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
DOUBLE_BUFFER_ISO_OFFSET: u2 = 0,
/// PID_1 [29:29]
/// The data pid of buffer 1.
PID_1: u1 = 0,
/// LAST_1 [30:30]
/// Buffer 1 is the last buffer of the transfer.
LAST_1: u1 = 0,
/// FULL_1 [31:31]
/// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_1: u1 = 0,
};
/// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
pub const EP8_IN_BUFFER_CONTROL = Register(EP8_IN_BUFFER_CONTROL_val).init(base_address + 0xc0);
/// EP7_OUT_BUFFER_CONTROL
const EP7_OUT_BUFFER_CONTROL_val = packed struct {
/// LENGTH_0 [0:9]
/// The length of the data in buffer 1.
LENGTH_0: u10 = 0,
/// AVAILABLE_0 [10:10]
/// Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_0: u1 = 0,
/// STALL [11:11]
/// Reply with a stall (valid for both buffers).
STALL: u1 = 0,
/// RESET [12:12]
/// Reset the buffer selector to buffer 0.
RESET: u1 = 0,
/// PID_0 [13:13]
/// The data pid of buffer 0.
PID_0: u1 = 0,
/// LAST_0 [14:14]
/// Buffer 0 is the last buffer of the transfer.
LAST_0: u1 = 0,
/// FULL_0 [15:15]
/// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_0: u1 = 0,
/// LENGTH_1 [16:25]
/// The length of the data in buffer 1.
LENGTH_1: u10 = 0,
/// AVAILABLE_1 [26:26]
/// Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_1: u1 = 0,
/// DOUBLE_BUFFER_ISO_OFFSET [27:28]
/// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
DOUBLE_BUFFER_ISO_OFFSET: u2 = 0,
/// PID_1 [29:29]
/// The data pid of buffer 1.
PID_1: u1 = 0,
/// LAST_1 [30:30]
/// Buffer 1 is the last buffer of the transfer.
LAST_1: u1 = 0,
/// FULL_1 [31:31]
/// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_1: u1 = 0,
};
/// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
pub const EP7_OUT_BUFFER_CONTROL = Register(EP7_OUT_BUFFER_CONTROL_val).init(base_address + 0xbc);
/// EP7_IN_BUFFER_CONTROL
const EP7_IN_BUFFER_CONTROL_val = packed struct {
/// LENGTH_0 [0:9]
/// The length of the data in buffer 1.
LENGTH_0: u10 = 0,
/// AVAILABLE_0 [10:10]
/// Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_0: u1 = 0,
/// STALL [11:11]
/// Reply with a stall (valid for both buffers).
STALL: u1 = 0,
/// RESET [12:12]
/// Reset the buffer selector to buffer 0.
RESET: u1 = 0,
/// PID_0 [13:13]
/// The data pid of buffer 0.
PID_0: u1 = 0,
/// LAST_0 [14:14]
/// Buffer 0 is the last buffer of the transfer.
LAST_0: u1 = 0,
/// FULL_0 [15:15]
/// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_0: u1 = 0,
/// LENGTH_1 [16:25]
/// The length of the data in buffer 1.
LENGTH_1: u10 = 0,
/// AVAILABLE_1 [26:26]
/// Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_1: u1 = 0,
/// DOUBLE_BUFFER_ISO_OFFSET [27:28]
/// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
DOUBLE_BUFFER_ISO_OFFSET: u2 = 0,
/// PID_1 [29:29]
/// The data pid of buffer 1.
PID_1: u1 = 0,
/// LAST_1 [30:30]
/// Buffer 1 is the last buffer of the transfer.
LAST_1: u1 = 0,
/// FULL_1 [31:31]
/// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_1: u1 = 0,
};
/// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
pub const EP7_IN_BUFFER_CONTROL = Register(EP7_IN_BUFFER_CONTROL_val).init(base_address + 0xb8);
/// EP6_OUT_BUFFER_CONTROL
const EP6_OUT_BUFFER_CONTROL_val = packed struct {
/// LENGTH_0 [0:9]
/// The length of the data in buffer 1.
LENGTH_0: u10 = 0,
/// AVAILABLE_0 [10:10]
/// Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_0: u1 = 0,
/// STALL [11:11]
/// Reply with a stall (valid for both buffers).
STALL: u1 = 0,
/// RESET [12:12]
/// Reset the buffer selector to buffer 0.
RESET: u1 = 0,
/// PID_0 [13:13]
/// The data pid of buffer 0.
PID_0: u1 = 0,
/// LAST_0 [14:14]
/// Buffer 0 is the last buffer of the transfer.
LAST_0: u1 = 0,
/// FULL_0 [15:15]
/// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_0: u1 = 0,
/// LENGTH_1 [16:25]
/// The length of the data in buffer 1.
LENGTH_1: u10 = 0,
/// AVAILABLE_1 [26:26]
/// Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_1: u1 = 0,
/// DOUBLE_BUFFER_ISO_OFFSET [27:28]
/// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
DOUBLE_BUFFER_ISO_OFFSET: u2 = 0,
/// PID_1 [29:29]
/// The data pid of buffer 1.
PID_1: u1 = 0,
/// LAST_1 [30:30]
/// Buffer 1 is the last buffer of the transfer.
LAST_1: u1 = 0,
/// FULL_1 [31:31]
/// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_1: u1 = 0,
};
/// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
pub const EP6_OUT_BUFFER_CONTROL = Register(EP6_OUT_BUFFER_CONTROL_val).init(base_address + 0xb4);
/// EP6_IN_BUFFER_CONTROL
const EP6_IN_BUFFER_CONTROL_val = packed struct {
/// LENGTH_0 [0:9]
/// The length of the data in buffer 1.
LENGTH_0: u10 = 0,
/// AVAILABLE_0 [10:10]
/// Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_0: u1 = 0,
/// STALL [11:11]
/// Reply with a stall (valid for both buffers).
STALL: u1 = 0,
/// RESET [12:12]
/// Reset the buffer selector to buffer 0.
RESET: u1 = 0,
/// PID_0 [13:13]
/// The data pid of buffer 0.
PID_0: u1 = 0,
/// LAST_0 [14:14]
/// Buffer 0 is the last buffer of the transfer.
LAST_0: u1 = 0,
/// FULL_0 [15:15]
/// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_0: u1 = 0,
/// LENGTH_1 [16:25]
/// The length of the data in buffer 1.
LENGTH_1: u10 = 0,
/// AVAILABLE_1 [26:26]
/// Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_1: u1 = 0,
/// DOUBLE_BUFFER_ISO_OFFSET [27:28]
/// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
DOUBLE_BUFFER_ISO_OFFSET: u2 = 0,
/// PID_1 [29:29]
/// The data pid of buffer 1.
PID_1: u1 = 0,
/// LAST_1 [30:30]
/// Buffer 1 is the last buffer of the transfer.
LAST_1: u1 = 0,
/// FULL_1 [31:31]
/// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_1: u1 = 0,
};
/// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
pub const EP6_IN_BUFFER_CONTROL = Register(EP6_IN_BUFFER_CONTROL_val).init(base_address + 0xb0);
/// EP5_OUT_BUFFER_CONTROL
const EP5_OUT_BUFFER_CONTROL_val = packed struct {
/// LENGTH_0 [0:9]
/// The length of the data in buffer 1.
LENGTH_0: u10 = 0,
/// AVAILABLE_0 [10:10]
/// Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_0: u1 = 0,
/// STALL [11:11]
/// Reply with a stall (valid for both buffers).
STALL: u1 = 0,
/// RESET [12:12]
/// Reset the buffer selector to buffer 0.
RESET: u1 = 0,
/// PID_0 [13:13]
/// The data pid of buffer 0.
PID_0: u1 = 0,
/// LAST_0 [14:14]
/// Buffer 0 is the last buffer of the transfer.
LAST_0: u1 = 0,
/// FULL_0 [15:15]
/// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_0: u1 = 0,
/// LENGTH_1 [16:25]
/// The length of the data in buffer 1.
LENGTH_1: u10 = 0,
/// AVAILABLE_1 [26:26]
/// Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_1: u1 = 0,
/// DOUBLE_BUFFER_ISO_OFFSET [27:28]
/// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
DOUBLE_BUFFER_ISO_OFFSET: u2 = 0,
/// PID_1 [29:29]
/// The data pid of buffer 1.
PID_1: u1 = 0,
/// LAST_1 [30:30]
/// Buffer 1 is the last buffer of the transfer.
LAST_1: u1 = 0,
/// FULL_1 [31:31]
/// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_1: u1 = 0,
};
/// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
pub const EP5_OUT_BUFFER_CONTROL = Register(EP5_OUT_BUFFER_CONTROL_val).init(base_address + 0xac);
/// EP5_IN_BUFFER_CONTROL
const EP5_IN_BUFFER_CONTROL_val = packed struct {
/// LENGTH_0 [0:9]
/// The length of the data in buffer 1.
LENGTH_0: u10 = 0,
/// AVAILABLE_0 [10:10]
/// Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_0: u1 = 0,
/// STALL [11:11]
/// Reply with a stall (valid for both buffers).
STALL: u1 = 0,
/// RESET [12:12]
/// Reset the buffer selector to buffer 0.
RESET: u1 = 0,
/// PID_0 [13:13]
/// The data pid of buffer 0.
PID_0: u1 = 0,
/// LAST_0 [14:14]
/// Buffer 0 is the last buffer of the transfer.
LAST_0: u1 = 0,
/// FULL_0 [15:15]
/// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_0: u1 = 0,
/// LENGTH_1 [16:25]
/// The length of the data in buffer 1.
LENGTH_1: u10 = 0,
/// AVAILABLE_1 [26:26]
/// Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_1: u1 = 0,
/// DOUBLE_BUFFER_ISO_OFFSET [27:28]
/// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
DOUBLE_BUFFER_ISO_OFFSET: u2 = 0,
/// PID_1 [29:29]
/// The data pid of buffer 1.
PID_1: u1 = 0,
/// LAST_1 [30:30]
/// Buffer 1 is the last buffer of the transfer.
LAST_1: u1 = 0,
/// FULL_1 [31:31]
/// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_1: u1 = 0,
};
/// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
pub const EP5_IN_BUFFER_CONTROL = Register(EP5_IN_BUFFER_CONTROL_val).init(base_address + 0xa8);
/// EP4_OUT_BUFFER_CONTROL
const EP4_OUT_BUFFER_CONTROL_val = packed struct {
/// LENGTH_0 [0:9]
/// The length of the data in buffer 1.
LENGTH_0: u10 = 0,
/// AVAILABLE_0 [10:10]
/// Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_0: u1 = 0,
/// STALL [11:11]
/// Reply with a stall (valid for both buffers).
STALL: u1 = 0,
/// RESET [12:12]
/// Reset the buffer selector to buffer 0.
RESET: u1 = 0,
/// PID_0 [13:13]
/// The data pid of buffer 0.
PID_0: u1 = 0,
/// LAST_0 [14:14]
/// Buffer 0 is the last buffer of the transfer.
LAST_0: u1 = 0,
/// FULL_0 [15:15]
/// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_0: u1 = 0,
/// LENGTH_1 [16:25]
/// The length of the data in buffer 1.
LENGTH_1: u10 = 0,
/// AVAILABLE_1 [26:26]
/// Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_1: u1 = 0,
/// DOUBLE_BUFFER_ISO_OFFSET [27:28]
/// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
DOUBLE_BUFFER_ISO_OFFSET: u2 = 0,
/// PID_1 [29:29]
/// The data pid of buffer 1.
PID_1: u1 = 0,
/// LAST_1 [30:30]
/// Buffer 1 is the last buffer of the transfer.
LAST_1: u1 = 0,
/// FULL_1 [31:31]
/// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_1: u1 = 0,
};
/// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
pub const EP4_OUT_BUFFER_CONTROL = Register(EP4_OUT_BUFFER_CONTROL_val).init(base_address + 0xa4);
/// EP4_IN_BUFFER_CONTROL
const EP4_IN_BUFFER_CONTROL_val = packed struct {
/// LENGTH_0 [0:9]
/// The length of the data in buffer 1.
LENGTH_0: u10 = 0,
/// AVAILABLE_0 [10:10]
/// Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_0: u1 = 0,
/// STALL [11:11]
/// Reply with a stall (valid for both buffers).
STALL: u1 = 0,
/// RESET [12:12]
/// Reset the buffer selector to buffer 0.
RESET: u1 = 0,
/// PID_0 [13:13]
/// The data pid of buffer 0.
PID_0: u1 = 0,
/// LAST_0 [14:14]
/// Buffer 0 is the last buffer of the transfer.
LAST_0: u1 = 0,
/// FULL_0 [15:15]
/// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_0: u1 = 0,
/// LENGTH_1 [16:25]
/// The length of the data in buffer 1.
LENGTH_1: u10 = 0,
/// AVAILABLE_1 [26:26]
/// Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_1: u1 = 0,
/// DOUBLE_BUFFER_ISO_OFFSET [27:28]
/// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
DOUBLE_BUFFER_ISO_OFFSET: u2 = 0,
/// PID_1 [29:29]
/// The data pid of buffer 1.
PID_1: u1 = 0,
/// LAST_1 [30:30]
/// Buffer 1 is the last buffer of the transfer.
LAST_1: u1 = 0,
/// FULL_1 [31:31]
/// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_1: u1 = 0,
};
/// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
pub const EP4_IN_BUFFER_CONTROL = Register(EP4_IN_BUFFER_CONTROL_val).init(base_address + 0xa0);
/// EP3_OUT_BUFFER_CONTROL
const EP3_OUT_BUFFER_CONTROL_val = packed struct {
/// LENGTH_0 [0:9]
/// The length of the data in buffer 1.
LENGTH_0: u10 = 0,
/// AVAILABLE_0 [10:10]
/// Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_0: u1 = 0,
/// STALL [11:11]
/// Reply with a stall (valid for both buffers).
STALL: u1 = 0,
/// RESET [12:12]
/// Reset the buffer selector to buffer 0.
RESET: u1 = 0,
/// PID_0 [13:13]
/// The data pid of buffer 0.
PID_0: u1 = 0,
/// LAST_0 [14:14]
/// Buffer 0 is the last buffer of the transfer.
LAST_0: u1 = 0,
/// FULL_0 [15:15]
/// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_0: u1 = 0,
/// LENGTH_1 [16:25]
/// The length of the data in buffer 1.
LENGTH_1: u10 = 0,
/// AVAILABLE_1 [26:26]
/// Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_1: u1 = 0,
/// DOUBLE_BUFFER_ISO_OFFSET [27:28]
/// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
DOUBLE_BUFFER_ISO_OFFSET: u2 = 0,
/// PID_1 [29:29]
/// The data pid of buffer 1.
PID_1: u1 = 0,
/// LAST_1 [30:30]
/// Buffer 1 is the last buffer of the transfer.
LAST_1: u1 = 0,
/// FULL_1 [31:31]
/// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_1: u1 = 0,
};
/// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
pub const EP3_OUT_BUFFER_CONTROL = Register(EP3_OUT_BUFFER_CONTROL_val).init(base_address + 0x9c);
/// EP3_IN_BUFFER_CONTROL
const EP3_IN_BUFFER_CONTROL_val = packed struct {
/// LENGTH_0 [0:9]
/// The length of the data in buffer 1.
LENGTH_0: u10 = 0,
/// AVAILABLE_0 [10:10]
/// Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_0: u1 = 0,
/// STALL [11:11]
/// Reply with a stall (valid for both buffers).
STALL: u1 = 0,
/// RESET [12:12]
/// Reset the buffer selector to buffer 0.
RESET: u1 = 0,
/// PID_0 [13:13]
/// The data pid of buffer 0.
PID_0: u1 = 0,
/// LAST_0 [14:14]
/// Buffer 0 is the last buffer of the transfer.
LAST_0: u1 = 0,
/// FULL_0 [15:15]
/// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_0: u1 = 0,
/// LENGTH_1 [16:25]
/// The length of the data in buffer 1.
LENGTH_1: u10 = 0,
/// AVAILABLE_1 [26:26]
/// Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_1: u1 = 0,
/// DOUBLE_BUFFER_ISO_OFFSET [27:28]
/// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
DOUBLE_BUFFER_ISO_OFFSET: u2 = 0,
/// PID_1 [29:29]
/// The data pid of buffer 1.
PID_1: u1 = 0,
/// LAST_1 [30:30]
/// Buffer 1 is the last buffer of the transfer.
LAST_1: u1 = 0,
/// FULL_1 [31:31]
/// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_1: u1 = 0,
};
/// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
pub const EP3_IN_BUFFER_CONTROL = Register(EP3_IN_BUFFER_CONTROL_val).init(base_address + 0x98);
/// EP2_OUT_BUFFER_CONTROL
const EP2_OUT_BUFFER_CONTROL_val = packed struct {
/// LENGTH_0 [0:9]
/// The length of the data in buffer 1.
LENGTH_0: u10 = 0,
/// AVAILABLE_0 [10:10]
/// Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_0: u1 = 0,
/// STALL [11:11]
/// Reply with a stall (valid for both buffers).
STALL: u1 = 0,
/// RESET [12:12]
/// Reset the buffer selector to buffer 0.
RESET: u1 = 0,
/// PID_0 [13:13]
/// The data pid of buffer 0.
PID_0: u1 = 0,
/// LAST_0 [14:14]
/// Buffer 0 is the last buffer of the transfer.
LAST_0: u1 = 0,
/// FULL_0 [15:15]
/// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_0: u1 = 0,
/// LENGTH_1 [16:25]
/// The length of the data in buffer 1.
LENGTH_1: u10 = 0,
/// AVAILABLE_1 [26:26]
/// Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_1: u1 = 0,
/// DOUBLE_BUFFER_ISO_OFFSET [27:28]
/// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
DOUBLE_BUFFER_ISO_OFFSET: u2 = 0,
/// PID_1 [29:29]
/// The data pid of buffer 1.
PID_1: u1 = 0,
/// LAST_1 [30:30]
/// Buffer 1 is the last buffer of the transfer.
LAST_1: u1 = 0,
/// FULL_1 [31:31]
/// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_1: u1 = 0,
};
/// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
pub const EP2_OUT_BUFFER_CONTROL = Register(EP2_OUT_BUFFER_CONTROL_val).init(base_address + 0x94);
/// EP2_IN_BUFFER_CONTROL
const EP2_IN_BUFFER_CONTROL_val = packed struct {
/// LENGTH_0 [0:9]
/// The length of the data in buffer 1.
LENGTH_0: u10 = 0,
/// AVAILABLE_0 [10:10]
/// Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_0: u1 = 0,
/// STALL [11:11]
/// Reply with a stall (valid for both buffers).
STALL: u1 = 0,
/// RESET [12:12]
/// Reset the buffer selector to buffer 0.
RESET: u1 = 0,
/// PID_0 [13:13]
/// The data pid of buffer 0.
PID_0: u1 = 0,
/// LAST_0 [14:14]
/// Buffer 0 is the last buffer of the transfer.
LAST_0: u1 = 0,
/// FULL_0 [15:15]
/// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_0: u1 = 0,
/// LENGTH_1 [16:25]
/// The length of the data in buffer 1.
LENGTH_1: u10 = 0,
/// AVAILABLE_1 [26:26]
/// Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_1: u1 = 0,
/// DOUBLE_BUFFER_ISO_OFFSET [27:28]
/// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
DOUBLE_BUFFER_ISO_OFFSET: u2 = 0,
/// PID_1 [29:29]
/// The data pid of buffer 1.
PID_1: u1 = 0,
/// LAST_1 [30:30]
/// Buffer 1 is the last buffer of the transfer.
LAST_1: u1 = 0,
/// FULL_1 [31:31]
/// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_1: u1 = 0,
};
/// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
pub const EP2_IN_BUFFER_CONTROL = Register(EP2_IN_BUFFER_CONTROL_val).init(base_address + 0x90);
/// EP1_OUT_BUFFER_CONTROL
const EP1_OUT_BUFFER_CONTROL_val = packed struct {
/// LENGTH_0 [0:9]
/// The length of the data in buffer 1.
LENGTH_0: u10 = 0,
/// AVAILABLE_0 [10:10]
/// Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_0: u1 = 0,
/// STALL [11:11]
/// Reply with a stall (valid for both buffers).
STALL: u1 = 0,
/// RESET [12:12]
/// Reset the buffer selector to buffer 0.
RESET: u1 = 0,
/// PID_0 [13:13]
/// The data pid of buffer 0.
PID_0: u1 = 0,
/// LAST_0 [14:14]
/// Buffer 0 is the last buffer of the transfer.
LAST_0: u1 = 0,
/// FULL_0 [15:15]
/// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_0: u1 = 0,
/// LENGTH_1 [16:25]
/// The length of the data in buffer 1.
LENGTH_1: u10 = 0,
/// AVAILABLE_1 [26:26]
/// Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_1: u1 = 0,
/// DOUBLE_BUFFER_ISO_OFFSET [27:28]
/// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
DOUBLE_BUFFER_ISO_OFFSET: u2 = 0,
/// PID_1 [29:29]
/// The data pid of buffer 1.
PID_1: u1 = 0,
/// LAST_1 [30:30]
/// Buffer 1 is the last buffer of the transfer.
LAST_1: u1 = 0,
/// FULL_1 [31:31]
/// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_1: u1 = 0,
};
/// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
pub const EP1_OUT_BUFFER_CONTROL = Register(EP1_OUT_BUFFER_CONTROL_val).init(base_address + 0x8c);
/// EP1_IN_BUFFER_CONTROL
const EP1_IN_BUFFER_CONTROL_val = packed struct {
/// LENGTH_0 [0:9]
/// The length of the data in buffer 1.
LENGTH_0: u10 = 0,
/// AVAILABLE_0 [10:10]
/// Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_0: u1 = 0,
/// STALL [11:11]
/// Reply with a stall (valid for both buffers).
STALL: u1 = 0,
/// RESET [12:12]
/// Reset the buffer selector to buffer 0.
RESET: u1 = 0,
/// PID_0 [13:13]
/// The data pid of buffer 0.
PID_0: u1 = 0,
/// LAST_0 [14:14]
/// Buffer 0 is the last buffer of the transfer.
LAST_0: u1 = 0,
/// FULL_0 [15:15]
/// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_0: u1 = 0,
/// LENGTH_1 [16:25]
/// The length of the data in buffer 1.
LENGTH_1: u10 = 0,
/// AVAILABLE_1 [26:26]
/// Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_1: u1 = 0,
/// DOUBLE_BUFFER_ISO_OFFSET [27:28]
/// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
DOUBLE_BUFFER_ISO_OFFSET: u2 = 0,
/// PID_1 [29:29]
/// The data pid of buffer 1.
PID_1: u1 = 0,
/// LAST_1 [30:30]
/// Buffer 1 is the last buffer of the transfer.
LAST_1: u1 = 0,
/// FULL_1 [31:31]
/// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_1: u1 = 0,
};
/// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
pub const EP1_IN_BUFFER_CONTROL = Register(EP1_IN_BUFFER_CONTROL_val).init(base_address + 0x88);
/// EP0_OUT_BUFFER_CONTROL
const EP0_OUT_BUFFER_CONTROL_val = packed struct {
/// LENGTH_0 [0:9]
/// The length of the data in buffer 1.
LENGTH_0: u10 = 0,
/// AVAILABLE_0 [10:10]
/// Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_0: u1 = 0,
/// STALL [11:11]
/// Reply with a stall (valid for both buffers).
STALL: u1 = 0,
/// RESET [12:12]
/// Reset the buffer selector to buffer 0.
RESET: u1 = 0,
/// PID_0 [13:13]
/// The data pid of buffer 0.
PID_0: u1 = 0,
/// LAST_0 [14:14]
/// Buffer 0 is the last buffer of the transfer.
LAST_0: u1 = 0,
/// FULL_0 [15:15]
/// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_0: u1 = 0,
/// LENGTH_1 [16:25]
/// The length of the data in buffer 1.
LENGTH_1: u10 = 0,
/// AVAILABLE_1 [26:26]
/// Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_1: u1 = 0,
/// DOUBLE_BUFFER_ISO_OFFSET [27:28]
/// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
DOUBLE_BUFFER_ISO_OFFSET: u2 = 0,
/// PID_1 [29:29]
/// The data pid of buffer 1.
PID_1: u1 = 0,
/// LAST_1 [30:30]
/// Buffer 1 is the last buffer of the transfer.
LAST_1: u1 = 0,
/// FULL_1 [31:31]
/// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_1: u1 = 0,
};
/// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
pub const EP0_OUT_BUFFER_CONTROL = Register(EP0_OUT_BUFFER_CONTROL_val).init(base_address + 0x84);
/// EP0_IN_BUFFER_CONTROL
const EP0_IN_BUFFER_CONTROL_val = packed struct {
/// LENGTH_0 [0:9]
/// The length of the data in buffer 1.
LENGTH_0: u10 = 0,
/// AVAILABLE_0 [10:10]
/// Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_0: u1 = 0,
/// STALL [11:11]
/// Reply with a stall (valid for both buffers).
STALL: u1 = 0,
/// RESET [12:12]
/// Reset the buffer selector to buffer 0.
RESET: u1 = 0,
/// PID_0 [13:13]
/// The data pid of buffer 0.
PID_0: u1 = 0,
/// LAST_0 [14:14]
/// Buffer 0 is the last buffer of the transfer.
LAST_0: u1 = 0,
/// FULL_0 [15:15]
/// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_0: u1 = 0,
/// LENGTH_1 [16:25]
/// The length of the data in buffer 1.
LENGTH_1: u10 = 0,
/// AVAILABLE_1 [26:26]
/// Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
AVAILABLE_1: u1 = 0,
/// DOUBLE_BUFFER_ISO_OFFSET [27:28]
/// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
DOUBLE_BUFFER_ISO_OFFSET: u2 = 0,
/// PID_1 [29:29]
/// The data pid of buffer 1.
PID_1: u1 = 0,
/// LAST_1 [30:30]
/// Buffer 1 is the last buffer of the transfer.
LAST_1: u1 = 0,
/// FULL_1 [31:31]
/// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
FULL_1: u1 = 0,
};
/// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
pub const EP0_IN_BUFFER_CONTROL = Register(EP0_IN_BUFFER_CONTROL_val).init(base_address + 0x80);
/// EP15_OUT_CONTROL
const EP15_OUT_CONTROL_val = packed struct {
/// BUFFER_ADDRESS [0:15]
/// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
BUFFER_ADDRESS: u16 = 0,
/// INTERRUPT_ON_NAK [16:16]
/// Trigger an interrupt if a NAK is sent. Intended for debug only.
INTERRUPT_ON_NAK: u1 = 0,
/// INTERRUPT_ON_STALL [17:17]
/// Trigger an interrupt if a STALL is sent. Intended for debug only.
INTERRUPT_ON_STALL: u1 = 0,
/// unused [18:25]
_unused18: u6 = 0,
_unused24: u2 = 0,
/// ENDPOINT_TYPE [26:27]
/// No description
ENDPOINT_TYPE: u2 = 0,
/// INTERRUPT_PER_DOUBLE_BUFF [28:28]
/// Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
INTERRUPT_PER_DOUBLE_BUFF: u1 = 0,
/// INTERRUPT_PER_BUFF [29:29]
/// Trigger an interrupt each time a buffer is done.
INTERRUPT_PER_BUFF: u1 = 0,
/// DOUBLE_BUFFERED [30:30]
/// This endpoint is double buffered.
DOUBLE_BUFFERED: u1 = 0,
/// ENABLE [31:31]
/// Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
ENABLE: u1 = 0,
};
/// No description
pub const EP15_OUT_CONTROL = Register(EP15_OUT_CONTROL_val).init(base_address + 0x7c);
/// EP15_IN_CONTROL
const EP15_IN_CONTROL_val = packed struct {
/// BUFFER_ADDRESS [0:15]
/// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
BUFFER_ADDRESS: u16 = 0,
/// INTERRUPT_ON_NAK [16:16]
/// Trigger an interrupt if a NAK is sent. Intended for debug only.
INTERRUPT_ON_NAK: u1 = 0,
/// INTERRUPT_ON_STALL [17:17]
/// Trigger an interrupt if a STALL is sent. Intended for debug only.
INTERRUPT_ON_STALL: u1 = 0,
/// unused [18:25]
_unused18: u6 = 0,
_unused24: u2 = 0,
/// ENDPOINT_TYPE [26:27]
/// No description
ENDPOINT_TYPE: u2 = 0,
/// INTERRUPT_PER_DOUBLE_BUFF [28:28]
/// Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
INTERRUPT_PER_DOUBLE_BUFF: u1 = 0,
/// INTERRUPT_PER_BUFF [29:29]
/// Trigger an interrupt each time a buffer is done.
INTERRUPT_PER_BUFF: u1 = 0,
/// DOUBLE_BUFFERED [30:30]
/// This endpoint is double buffered.
DOUBLE_BUFFERED: u1 = 0,
/// ENABLE [31:31]
/// Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
ENABLE: u1 = 0,
};
/// No description
pub const EP15_IN_CONTROL = Register(EP15_IN_CONTROL_val).init(base_address + 0x78);
/// EP14_OUT_CONTROL
const EP14_OUT_CONTROL_val = packed struct {
/// BUFFER_ADDRESS [0:15]
/// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
BUFFER_ADDRESS: u16 = 0,
/// INTERRUPT_ON_NAK [16:16]
/// Trigger an interrupt if a NAK is sent. Intended for debug only.
INTERRUPT_ON_NAK: u1 = 0,
/// INTERRUPT_ON_STALL [17:17]
/// Trigger an interrupt if a STALL is sent. Intended for debug only.
INTERRUPT_ON_STALL: u1 = 0,
/// unused [18:25]
_unused18: u6 = 0,
_unused24: u2 = 0,
/// ENDPOINT_TYPE [26:27]
/// No description
ENDPOINT_TYPE: u2 = 0,
/// INTERRUPT_PER_DOUBLE_BUFF [28:28]
/// Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
INTERRUPT_PER_DOUBLE_BUFF: u1 = 0,
/// INTERRUPT_PER_BUFF [29:29]
/// Trigger an interrupt each time a buffer is done.
INTERRUPT_PER_BUFF: u1 = 0,
/// DOUBLE_BUFFERED [30:30]
/// This endpoint is double buffered.
DOUBLE_BUFFERED: u1 = 0,
/// ENABLE [31:31]
/// Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
ENABLE: u1 = 0,
};
/// No description
pub const EP14_OUT_CONTROL = Register(EP14_OUT_CONTROL_val).init(base_address + 0x74);
/// EP14_IN_CONTROL
const EP14_IN_CONTROL_val = packed struct {
/// BUFFER_ADDRESS [0:15]
/// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
BUFFER_ADDRESS: u16 = 0,
/// INTERRUPT_ON_NAK [16:16]
/// Trigger an interrupt if a NAK is sent. Intended for debug only.
INTERRUPT_ON_NAK: u1 = 0,
/// INTERRUPT_ON_STALL [17:17]
/// Trigger an interrupt if a STALL is sent. Intended for debug only.
INTERRUPT_ON_STALL: u1 = 0,
/// unused [18:25]
_unused18: u6 = 0,
_unused24: u2 = 0,
/// ENDPOINT_TYPE [26:27]
/// No description
ENDPOINT_TYPE: u2 = 0,
/// INTERRUPT_PER_DOUBLE_BUFF [28:28]
/// Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
INTERRUPT_PER_DOUBLE_BUFF: u1 = 0,
/// INTERRUPT_PER_BUFF [29:29]
/// Trigger an interrupt each time a buffer is done.
INTERRUPT_PER_BUFF: u1 = 0,
/// DOUBLE_BUFFERED [30:30]
/// This endpoint is double buffered.
DOUBLE_BUFFERED: u1 = 0,
/// ENABLE [31:31]
/// Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
ENABLE: u1 = 0,
};
/// No description
pub const EP14_IN_CONTROL = Register(EP14_IN_CONTROL_val).init(base_address + 0x70);
/// EP13_OUT_CONTROL
const EP13_OUT_CONTROL_val = packed struct {
/// BUFFER_ADDRESS [0:15]
/// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
BUFFER_ADDRESS: u16 = 0,
/// INTERRUPT_ON_NAK [16:16]
/// Trigger an interrupt if a NAK is sent. Intended for debug only.
INTERRUPT_ON_NAK: u1 = 0,
/// INTERRUPT_ON_STALL [17:17]
/// Trigger an interrupt if a STALL is sent. Intended for debug only.
INTERRUPT_ON_STALL: u1 = 0,
/// unused [18:25]
_unused18: u6 = 0,
_unused24: u2 = 0,
/// ENDPOINT_TYPE [26:27]
/// No description
ENDPOINT_TYPE: u2 = 0,
/// INTERRUPT_PER_DOUBLE_BUFF [28:28]
/// Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
INTERRUPT_PER_DOUBLE_BUFF: u1 = 0,
/// INTERRUPT_PER_BUFF [29:29]
/// Trigger an interrupt each time a buffer is done.
INTERRUPT_PER_BUFF: u1 = 0,
/// DOUBLE_BUFFERED [30:30]
/// This endpoint is double buffered.
DOUBLE_BUFFERED: u1 = 0,
/// ENABLE [31:31]
/// Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
ENABLE: u1 = 0,
};
/// No description
pub const EP13_OUT_CONTROL = Register(EP13_OUT_CONTROL_val).init(base_address + 0x6c);
/// EP13_IN_CONTROL
const EP13_IN_CONTROL_val = packed struct {
/// BUFFER_ADDRESS [0:15]
/// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
BUFFER_ADDRESS: u16 = 0,
/// INTERRUPT_ON_NAK [16:16]
/// Trigger an interrupt if a NAK is sent. Intended for debug only.
INTERRUPT_ON_NAK: u1 = 0,
/// INTERRUPT_ON_STALL [17:17]
/// Trigger an interrupt if a STALL is sent. Intended for debug only.
INTERRUPT_ON_STALL: u1 = 0,
/// unused [18:25]
_unused18: u6 = 0,
_unused24: u2 = 0,
/// ENDPOINT_TYPE [26:27]
/// No description
ENDPOINT_TYPE: u2 = 0,
/// INTERRUPT_PER_DOUBLE_BUFF [28:28]
/// Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
INTERRUPT_PER_DOUBLE_BUFF: u1 = 0,
/// INTERRUPT_PER_BUFF [29:29]
/// Trigger an interrupt each time a buffer is done.
INTERRUPT_PER_BUFF: u1 = 0,
/// DOUBLE_BUFFERED [30:30]
/// This endpoint is double buffered.
DOUBLE_BUFFERED: u1 = 0,
/// ENABLE [31:31]
/// Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
ENABLE: u1 = 0,
};
/// No description
pub const EP13_IN_CONTROL = Register(EP13_IN_CONTROL_val).init(base_address + 0x68);
/// EP12_OUT_CONTROL
const EP12_OUT_CONTROL_val = packed struct {
/// BUFFER_ADDRESS [0:15]
/// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
BUFFER_ADDRESS: u16 = 0,
/// INTERRUPT_ON_NAK [16:16]
/// Trigger an interrupt if a NAK is sent. Intended for debug only.
INTERRUPT_ON_NAK: u1 = 0,
/// INTERRUPT_ON_STALL [17:17]
/// Trigger an interrupt if a STALL is sent. Intended for debug only.
INTERRUPT_ON_STALL: u1 = 0,
/// unused [18:25]
_unused18: u6 = 0,
_unused24: u2 = 0,
/// ENDPOINT_TYPE [26:27]
/// No description
ENDPOINT_TYPE: u2 = 0,
/// INTERRUPT_PER_DOUBLE_BUFF [28:28]
/// Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
INTERRUPT_PER_DOUBLE_BUFF: u1 = 0,
/// INTERRUPT_PER_BUFF [29:29]
/// Trigger an interrupt each time a buffer is done.
INTERRUPT_PER_BUFF: u1 = 0,
/// DOUBLE_BUFFERED [30:30]
/// This endpoint is double buffered.
DOUBLE_BUFFERED: u1 = 0,
/// ENABLE [31:31]
/// Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
ENABLE: u1 = 0,
};
/// No description
pub const EP12_OUT_CONTROL = Register(EP12_OUT_CONTROL_val).init(base_address + 0x64);
/// EP12_IN_CONTROL
const EP12_IN_CONTROL_val = packed struct {
/// BUFFER_ADDRESS [0:15]
/// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
BUFFER_ADDRESS: u16 = 0,
/// INTERRUPT_ON_NAK [16:16]
/// Trigger an interrupt if a NAK is sent. Intended for debug only.
INTERRUPT_ON_NAK: u1 = 0,
/// INTERRUPT_ON_STALL [17:17]
/// Trigger an interrupt if a STALL is sent. Intended for debug only.
INTERRUPT_ON_STALL: u1 = 0,
/// unused [18:25]
_unused18: u6 = 0,
_unused24: u2 = 0,
/// ENDPOINT_TYPE [26:27]
/// No description
ENDPOINT_TYPE: u2 = 0,
/// INTERRUPT_PER_DOUBLE_BUFF [28:28]
/// Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
INTERRUPT_PER_DOUBLE_BUFF: u1 = 0,
/// INTERRUPT_PER_BUFF [29:29]
/// Trigger an interrupt each time a buffer is done.
INTERRUPT_PER_BUFF: u1 = 0,
/// DOUBLE_BUFFERED [30:30]
/// This endpoint is double buffered.
DOUBLE_BUFFERED: u1 = 0,
/// ENABLE [31:31]
/// Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
ENABLE: u1 = 0,
};
/// No description
pub const EP12_IN_CONTROL = Register(EP12_IN_CONTROL_val).init(base_address + 0x60);
/// EP11_OUT_CONTROL
const EP11_OUT_CONTROL_val = packed struct {
/// BUFFER_ADDRESS [0:15]
/// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
BUFFER_ADDRESS: u16 = 0,
/// INTERRUPT_ON_NAK [16:16]
/// Trigger an interrupt if a NAK is sent. Intended for debug only.
INTERRUPT_ON_NAK: u1 = 0,
/// INTERRUPT_ON_STALL [17:17]
/// Trigger an interrupt if a STALL is sent. Intended for debug only.
INTERRUPT_ON_STALL: u1 = 0,
/// unused [18:25]
_unused18: u6 = 0,
_unused24: u2 = 0,
/// ENDPOINT_TYPE [26:27]
/// No description
ENDPOINT_TYPE: u2 = 0,
/// INTERRUPT_PER_DOUBLE_BUFF [28:28]
/// Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
INTERRUPT_PER_DOUBLE_BUFF: u1 = 0,
/// INTERRUPT_PER_BUFF [29:29]
/// Trigger an interrupt each time a buffer is done.
INTERRUPT_PER_BUFF: u1 = 0,
/// DOUBLE_BUFFERED [30:30]
/// This endpoint is double buffered.
DOUBLE_BUFFERED: u1 = 0,
/// ENABLE [31:31]
/// Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
ENABLE: u1 = 0,
};
/// No description
pub const EP11_OUT_CONTROL = Register(EP11_OUT_CONTROL_val).init(base_address + 0x5c);
/// EP11_IN_CONTROL
const EP11_IN_CONTROL_val = packed struct {
/// BUFFER_ADDRESS [0:15]
/// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
BUFFER_ADDRESS: u16 = 0,
/// INTERRUPT_ON_NAK [16:16]
/// Trigger an interrupt if a NAK is sent. Intended for debug only.
INTERRUPT_ON_NAK: u1 = 0,
/// INTERRUPT_ON_STALL [17:17]
/// Trigger an interrupt if a STALL is sent. Intended for debug only.
INTERRUPT_ON_STALL: u1 = 0,
/// unused [18:25]
_unused18: u6 = 0,
_unused24: u2 = 0,
/// ENDPOINT_TYPE [26:27]
/// No description
ENDPOINT_TYPE: u2 = 0,
/// INTERRUPT_PER_DOUBLE_BUFF [28:28]
/// Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
INTERRUPT_PER_DOUBLE_BUFF: u1 = 0,
/// INTERRUPT_PER_BUFF [29:29]
/// Trigger an interrupt each time a buffer is done.
INTERRUPT_PER_BUFF: u1 = 0,
/// DOUBLE_BUFFERED [30:30]
/// This endpoint is double buffered.
DOUBLE_BUFFERED: u1 = 0,
/// ENABLE [31:31]
/// Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
ENABLE: u1 = 0,
};
/// No description
pub const EP11_IN_CONTROL = Register(EP11_IN_CONTROL_val).init(base_address + 0x58);
/// EP10_OUT_CONTROL
const EP10_OUT_CONTROL_val = packed struct {
/// BUFFER_ADDRESS [0:15]
/// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
BUFFER_ADDRESS: u16 = 0,
/// INTERRUPT_ON_NAK [16:16]
/// Trigger an interrupt if a NAK is sent. Intended for debug only.
INTERRUPT_ON_NAK: u1 = 0,
/// INTERRUPT_ON_STALL [17:17]
/// Trigger an interrupt if a STALL is sent. Intended for debug only.
INTERRUPT_ON_STALL: u1 = 0,
/// unused [18:25]
_unused18: u6 = 0,
_unused24: u2 = 0,
/// ENDPOINT_TYPE [26:27]
/// No description
ENDPOINT_TYPE: u2 = 0,
/// INTERRUPT_PER_DOUBLE_BUFF [28:28]
/// Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
INTERRUPT_PER_DOUBLE_BUFF: u1 = 0,
/// INTERRUPT_PER_BUFF [29:29]
/// Trigger an interrupt each time a buffer is done.
INTERRUPT_PER_BUFF: u1 = 0,
/// DOUBLE_BUFFERED [30:30]
/// This endpoint is double buffered.
DOUBLE_BUFFERED: u1 = 0,
/// ENABLE [31:31]
/// Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
ENABLE: u1 = 0,
};
/// No description
pub const EP10_OUT_CONTROL = Register(EP10_OUT_CONTROL_val).init(base_address + 0x54);
/// EP10_IN_CONTROL
const EP10_IN_CONTROL_val = packed struct {
/// BUFFER_ADDRESS [0:15]
/// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
BUFFER_ADDRESS: u16 = 0,
/// INTERRUPT_ON_NAK [16:16]
/// Trigger an interrupt if a NAK is sent. Intended for debug only.
INTERRUPT_ON_NAK: u1 = 0,
/// INTERRUPT_ON_STALL [17:17]
/// Trigger an interrupt if a STALL is sent. Intended for debug only.
INTERRUPT_ON_STALL: u1 = 0,
/// unused [18:25]
_unused18: u6 = 0,
_unused24: u2 = 0,
/// ENDPOINT_TYPE [26:27]
/// No description
ENDPOINT_TYPE: u2 = 0,
/// INTERRUPT_PER_DOUBLE_BUFF [28:28]
/// Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
INTERRUPT_PER_DOUBLE_BUFF: u1 = 0,
/// INTERRUPT_PER_BUFF [29:29]
/// Trigger an interrupt each time a buffer is done.
INTERRUPT_PER_BUFF: u1 = 0,
/// DOUBLE_BUFFERED [30:30]
/// This endpoint is double buffered.
DOUBLE_BUFFERED: u1 = 0,
/// ENABLE [31:31]
/// Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
ENABLE: u1 = 0,
};
/// No description
pub const EP10_IN_CONTROL = Register(EP10_IN_CONTROL_val).init(base_address + 0x50);
/// EP9_OUT_CONTROL
const EP9_OUT_CONTROL_val = packed struct {
/// BUFFER_ADDRESS [0:15]
/// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
BUFFER_ADDRESS: u16 = 0,
/// INTERRUPT_ON_NAK [16:16]
/// Trigger an interrupt if a NAK is sent. Intended for debug only.
INTERRUPT_ON_NAK: u1 = 0,
/// INTERRUPT_ON_STALL [17:17]
/// Trigger an interrupt if a STALL is sent. Intended for debug only.
INTERRUPT_ON_STALL: u1 = 0,
/// unused [18:25]
_unused18: u6 = 0,
_unused24: u2 = 0,
/// ENDPOINT_TYPE [26:27]
/// No description
ENDPOINT_TYPE: u2 = 0,
/// INTERRUPT_PER_DOUBLE_BUFF [28:28]
/// Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
INTERRUPT_PER_DOUBLE_BUFF: u1 = 0,
/// INTERRUPT_PER_BUFF [29:29]
/// Trigger an interrupt each time a buffer is done.
INTERRUPT_PER_BUFF: u1 = 0,
/// DOUBLE_BUFFERED [30:30]
/// This endpoint is double buffered.
DOUBLE_BUFFERED: u1 = 0,
/// ENABLE [31:31]
/// Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
ENABLE: u1 = 0,
};
/// No description
pub const EP9_OUT_CONTROL = Register(EP9_OUT_CONTROL_val).init(base_address + 0x4c);
/// EP9_IN_CONTROL
const EP9_IN_CONTROL_val = packed struct {
/// BUFFER_ADDRESS [0:15]
/// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
BUFFER_ADDRESS: u16 = 0,
/// INTERRUPT_ON_NAK [16:16]
/// Trigger an interrupt if a NAK is sent. Intended for debug only.
INTERRUPT_ON_NAK: u1 = 0,
/// INTERRUPT_ON_STALL [17:17]
/// Trigger an interrupt if a STALL is sent. Intended for debug only.
INTERRUPT_ON_STALL: u1 = 0,
/// unused [18:25]
_unused18: u6 = 0,
_unused24: u2 = 0,
/// ENDPOINT_TYPE [26:27]
/// No description
ENDPOINT_TYPE: u2 = 0,
/// INTERRUPT_PER_DOUBLE_BUFF [28:28]
/// Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
INTERRUPT_PER_DOUBLE_BUFF: u1 = 0,
/// INTERRUPT_PER_BUFF [29:29]
/// Trigger an interrupt each time a buffer is done.
INTERRUPT_PER_BUFF: u1 = 0,
/// DOUBLE_BUFFERED [30:30]
/// This endpoint is double buffered.
DOUBLE_BUFFERED: u1 = 0,
/// ENABLE [31:31]
/// Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
ENABLE: u1 = 0,
};
/// No description
pub const EP9_IN_CONTROL = Register(EP9_IN_CONTROL_val).init(base_address + 0x48);
/// EP8_OUT_CONTROL
const EP8_OUT_CONTROL_val = packed struct {
/// BUFFER_ADDRESS [0:15]
/// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
BUFFER_ADDRESS: u16 = 0,
/// INTERRUPT_ON_NAK [16:16]
/// Trigger an interrupt if a NAK is sent. Intended for debug only.
INTERRUPT_ON_NAK: u1 = 0,
/// INTERRUPT_ON_STALL [17:17]
/// Trigger an interrupt if a STALL is sent. Intended for debug only.
INTERRUPT_ON_STALL: u1 = 0,
/// unused [18:25]
_unused18: u6 = 0,
_unused24: u2 = 0,
/// ENDPOINT_TYPE [26:27]
/// No description
ENDPOINT_TYPE: u2 = 0,
/// INTERRUPT_PER_DOUBLE_BUFF [28:28]
/// Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
INTERRUPT_PER_DOUBLE_BUFF: u1 = 0,
/// INTERRUPT_PER_BUFF [29:29]
/// Trigger an interrupt each time a buffer is done.
INTERRUPT_PER_BUFF: u1 = 0,
/// DOUBLE_BUFFERED [30:30]
/// This endpoint is double buffered.
DOUBLE_BUFFERED: u1 = 0,
/// ENABLE [31:31]
/// Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
ENABLE: u1 = 0,
};
/// No description
pub const EP8_OUT_CONTROL = Register(EP8_OUT_CONTROL_val).init(base_address + 0x44);
/// EP8_IN_CONTROL
const EP8_IN_CONTROL_val = packed struct {
/// BUFFER_ADDRESS [0:15]
/// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
BUFFER_ADDRESS: u16 = 0,
/// INTERRUPT_ON_NAK [16:16]
/// Trigger an interrupt if a NAK is sent. Intended for debug only.
INTERRUPT_ON_NAK: u1 = 0,
/// INTERRUPT_ON_STALL [17:17]
/// Trigger an interrupt if a STALL is sent. Intended for debug only.
INTERRUPT_ON_STALL: u1 = 0,
/// unused [18:25]
_unused18: u6 = 0,
_unused24: u2 = 0,
/// ENDPOINT_TYPE [26:27]
/// No description
ENDPOINT_TYPE: u2 = 0,
/// INTERRUPT_PER_DOUBLE_BUFF [28:28]
/// Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
INTERRUPT_PER_DOUBLE_BUFF: u1 = 0,
/// INTERRUPT_PER_BUFF [29:29]
/// Trigger an interrupt each time a buffer is done.
INTERRUPT_PER_BUFF: u1 = 0,
/// DOUBLE_BUFFERED [30:30]
/// This endpoint is double buffered.
DOUBLE_BUFFERED: u1 = 0,
/// ENABLE [31:31]
/// Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
ENABLE: u1 = 0,
};
/// No description
pub const EP8_IN_CONTROL = Register(EP8_IN_CONTROL_val).init(base_address + 0x40);
/// EP7_OUT_CONTROL
const EP7_OUT_CONTROL_val = packed struct {
/// BUFFER_ADDRESS [0:15]
/// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
BUFFER_ADDRESS: u16 = 0,
/// INTERRUPT_ON_NAK [16:16]
/// Trigger an interrupt if a NAK is sent. Intended for debug only.
INTERRUPT_ON_NAK: u1 = 0,
/// INTERRUPT_ON_STALL [17:17]
/// Trigger an interrupt if a STALL is sent. Intended for debug only.
INTERRUPT_ON_STALL: u1 = 0,
/// unused [18:25]
_unused18: u6 = 0,
_unused24: u2 = 0,
/// ENDPOINT_TYPE [26:27]
/// No description
ENDPOINT_TYPE: u2 = 0,
/// INTERRUPT_PER_DOUBLE_BUFF [28:28]
/// Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
INTERRUPT_PER_DOUBLE_BUFF: u1 = 0,
/// INTERRUPT_PER_BUFF [29:29]
/// Trigger an interrupt each time a buffer is done.
INTERRUPT_PER_BUFF: u1 = 0,
/// DOUBLE_BUFFERED [30:30]
/// This endpoint is double buffered.
DOUBLE_BUFFERED: u1 = 0,
/// ENABLE [31:31]
/// Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
ENABLE: u1 = 0,
};
/// No description
pub const EP7_OUT_CONTROL = Register(EP7_OUT_CONTROL_val).init(base_address + 0x3c);
/// EP7_IN_CONTROL
const EP7_IN_CONTROL_val = packed struct {
/// BUFFER_ADDRESS [0:15]
/// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
BUFFER_ADDRESS: u16 = 0,
/// INTERRUPT_ON_NAK [16:16]
/// Trigger an interrupt if a NAK is sent. Intended for debug only.
INTERRUPT_ON_NAK: u1 = 0,
/// INTERRUPT_ON_STALL [17:17]
/// Trigger an interrupt if a STALL is sent. Intended for debug only.
INTERRUPT_ON_STALL: u1 = 0,
/// unused [18:25]
_unused18: u6 = 0,
_unused24: u2 = 0,
/// ENDPOINT_TYPE [26:27]
/// No description
ENDPOINT_TYPE: u2 = 0,
/// INTERRUPT_PER_DOUBLE_BUFF [28:28]
/// Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
INTERRUPT_PER_DOUBLE_BUFF: u1 = 0,
/// INTERRUPT_PER_BUFF [29:29]
/// Trigger an interrupt each time a buffer is done.
INTERRUPT_PER_BUFF: u1 = 0,
/// DOUBLE_BUFFERED [30:30]
/// This endpoint is double buffered.
DOUBLE_BUFFERED: u1 = 0,
/// ENABLE [31:31]
/// Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
ENABLE: u1 = 0,
};
/// No description
pub const EP7_IN_CONTROL = Register(EP7_IN_CONTROL_val).init(base_address + 0x38);
/// EP6_OUT_CONTROL
const EP6_OUT_CONTROL_val = packed struct {
/// BUFFER_ADDRESS [0:15]
/// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
BUFFER_ADDRESS: u16 = 0,
/// INTERRUPT_ON_NAK [16:16]
/// Trigger an interrupt if a NAK is sent. Intended for debug only.
INTERRUPT_ON_NAK: u1 = 0,
/// INTERRUPT_ON_STALL [17:17]
/// Trigger an interrupt if a STALL is sent. Intended for debug only.
INTERRUPT_ON_STALL: u1 = 0,
/// unused [18:25]
_unused18: u6 = 0,
_unused24: u2 = 0,
/// ENDPOINT_TYPE [26:27]
/// No description
ENDPOINT_TYPE: u2 = 0,
/// INTERRUPT_PER_DOUBLE_BUFF [28:28]
/// Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
INTERRUPT_PER_DOUBLE_BUFF: u1 = 0,
/// INTERRUPT_PER_BUFF [29:29]
/// Trigger an interrupt each time a buffer is done.
INTERRUPT_PER_BUFF: u1 = 0,
/// DOUBLE_BUFFERED [30:30]
/// This endpoint is double buffered.
DOUBLE_BUFFERED: u1 = 0,
/// ENABLE [31:31]
/// Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
ENABLE: u1 = 0,
};
/// No description
pub const EP6_OUT_CONTROL = Register(EP6_OUT_CONTROL_val).init(base_address + 0x34);
/// EP6_IN_CONTROL
const EP6_IN_CONTROL_val = packed struct {
/// BUFFER_ADDRESS [0:15]
/// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
BUFFER_ADDRESS: u16 = 0,
/// INTERRUPT_ON_NAK [16:16]
/// Trigger an interrupt if a NAK is sent. Intended for debug only.
INTERRUPT_ON_NAK: u1 = 0,
/// INTERRUPT_ON_STALL [17:17]
/// Trigger an interrupt if a STALL is sent. Intended for debug only.
INTERRUPT_ON_STALL: u1 = 0,
/// unused [18:25]
_unused18: u6 = 0,
_unused24: u2 = 0,
/// ENDPOINT_TYPE [26:27]
/// No description
ENDPOINT_TYPE: u2 = 0,
/// INTERRUPT_PER_DOUBLE_BUFF [28:28]
/// Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
INTERRUPT_PER_DOUBLE_BUFF: u1 = 0,
/// INTERRUPT_PER_BUFF [29:29]
/// Trigger an interrupt each time a buffer is done.
INTERRUPT_PER_BUFF: u1 = 0,
/// DOUBLE_BUFFERED [30:30]
/// This endpoint is double buffered.
DOUBLE_BUFFERED: u1 = 0,
/// ENABLE [31:31]
/// Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
ENABLE: u1 = 0,
};
/// No description
pub const EP6_IN_CONTROL = Register(EP6_IN_CONTROL_val).init(base_address + 0x30);
/// EP5_OUT_CONTROL
const EP5_OUT_CONTROL_val = packed struct {
/// BUFFER_ADDRESS [0:15]
/// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
BUFFER_ADDRESS: u16 = 0,
/// INTERRUPT_ON_NAK [16:16]
/// Trigger an interrupt if a NAK is sent. Intended for debug only.
INTERRUPT_ON_NAK: u1 = 0,
/// INTERRUPT_ON_STALL [17:17]
/// Trigger an interrupt if a STALL is sent. Intended for debug only.
INTERRUPT_ON_STALL: u1 = 0,
/// unused [18:25]
_unused18: u6 = 0,
_unused24: u2 = 0,
/// ENDPOINT_TYPE [26:27]
/// No description
ENDPOINT_TYPE: u2 = 0,
/// INTERRUPT_PER_DOUBLE_BUFF [28:28]
/// Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
INTERRUPT_PER_DOUBLE_BUFF: u1 = 0,
/// INTERRUPT_PER_BUFF [29:29]
/// Trigger an interrupt each time a buffer is done.
INTERRUPT_PER_BUFF: u1 = 0,
/// DOUBLE_BUFFERED [30:30]
/// This endpoint is double buffered.
DOUBLE_BUFFERED: u1 = 0,
/// ENABLE [31:31]
/// Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
ENABLE: u1 = 0,
};
/// No description
pub const EP5_OUT_CONTROL = Register(EP5_OUT_CONTROL_val).init(base_address + 0x2c);
/// EP5_IN_CONTROL
const EP5_IN_CONTROL_val = packed struct {
/// BUFFER_ADDRESS [0:15]
/// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
BUFFER_ADDRESS: u16 = 0,
/// INTERRUPT_ON_NAK [16:16]
/// Trigger an interrupt if a NAK is sent. Intended for debug only.
INTERRUPT_ON_NAK: u1 = 0,
/// INTERRUPT_ON_STALL [17:17]
/// Trigger an interrupt if a STALL is sent. Intended for debug only.
INTERRUPT_ON_STALL: u1 = 0,
/// unused [18:25]
_unused18: u6 = 0,
_unused24: u2 = 0,
/// ENDPOINT_TYPE [26:27]
/// No description
ENDPOINT_TYPE: u2 = 0,
/// INTERRUPT_PER_DOUBLE_BUFF [28:28]
/// Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
INTERRUPT_PER_DOUBLE_BUFF: u1 = 0,
/// INTERRUPT_PER_BUFF [29:29]
/// Trigger an interrupt each time a buffer is done.
INTERRUPT_PER_BUFF: u1 = 0,
/// DOUBLE_BUFFERED [30:30]
/// This endpoint is double buffered.
DOUBLE_BUFFERED: u1 = 0,
/// ENABLE [31:31]
/// Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
ENABLE: u1 = 0,
};
/// No description
pub const EP5_IN_CONTROL = Register(EP5_IN_CONTROL_val).init(base_address + 0x28);
/// EP4_OUT_CONTROL
const EP4_OUT_CONTROL_val = packed struct {
/// BUFFER_ADDRESS [0:15]
/// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
BUFFER_ADDRESS: u16 = 0,
/// INTERRUPT_ON_NAK [16:16]
/// Trigger an interrupt if a NAK is sent. Intended for debug only.
INTERRUPT_ON_NAK: u1 = 0,
/// INTERRUPT_ON_STALL [17:17]
/// Trigger an interrupt if a STALL is sent. Intended for debug only.
INTERRUPT_ON_STALL: u1 = 0,
/// unused [18:25]
_unused18: u6 = 0,
_unused24: u2 = 0,
/// ENDPOINT_TYPE [26:27]
/// No description
ENDPOINT_TYPE: u2 = 0,
/// INTERRUPT_PER_DOUBLE_BUFF [28:28]
/// Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
INTERRUPT_PER_DOUBLE_BUFF: u1 = 0,
/// INTERRUPT_PER_BUFF [29:29]
/// Trigger an interrupt each time a buffer is done.
INTERRUPT_PER_BUFF: u1 = 0,
/// DOUBLE_BUFFERED [30:30]
/// This endpoint is double buffered.
DOUBLE_BUFFERED: u1 = 0,
/// ENABLE [31:31]
/// Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
ENABLE: u1 = 0,
};
/// No description
pub const EP4_OUT_CONTROL = Register(EP4_OUT_CONTROL_val).init(base_address + 0x24);
/// EP4_IN_CONTROL
const EP4_IN_CONTROL_val = packed struct {
/// BUFFER_ADDRESS [0:15]
/// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
BUFFER_ADDRESS: u16 = 0,
/// INTERRUPT_ON_NAK [16:16]
/// Trigger an interrupt if a NAK is sent. Intended for debug only.
INTERRUPT_ON_NAK: u1 = 0,
/// INTERRUPT_ON_STALL [17:17]
/// Trigger an interrupt if a STALL is sent. Intended for debug only.
INTERRUPT_ON_STALL: u1 = 0,
/// unused [18:25]
_unused18: u6 = 0,
_unused24: u2 = 0,
/// ENDPOINT_TYPE [26:27]
/// No description
ENDPOINT_TYPE: u2 = 0,
/// INTERRUPT_PER_DOUBLE_BUFF [28:28]
/// Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
INTERRUPT_PER_DOUBLE_BUFF: u1 = 0,
/// INTERRUPT_PER_BUFF [29:29]
/// Trigger an interrupt each time a buffer is done.
INTERRUPT_PER_BUFF: u1 = 0,
/// DOUBLE_BUFFERED [30:30]
/// This endpoint is double buffered.
DOUBLE_BUFFERED: u1 = 0,
/// ENABLE [31:31]
/// Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
ENABLE: u1 = 0,
};
/// No description
pub const EP4_IN_CONTROL = Register(EP4_IN_CONTROL_val).init(base_address + 0x20);
/// EP3_OUT_CONTROL
const EP3_OUT_CONTROL_val = packed struct {
/// BUFFER_ADDRESS [0:15]
/// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
BUFFER_ADDRESS: u16 = 0,
/// INTERRUPT_ON_NAK [16:16]
/// Trigger an interrupt if a NAK is sent. Intended for debug only.
INTERRUPT_ON_NAK: u1 = 0,
/// INTERRUPT_ON_STALL [17:17]
/// Trigger an interrupt if a STALL is sent. Intended for debug only.
INTERRUPT_ON_STALL: u1 = 0,
/// unused [18:25]
_unused18: u6 = 0,
_unused24: u2 = 0,
/// ENDPOINT_TYPE [26:27]
/// No description
ENDPOINT_TYPE: u2 = 0,
/// INTERRUPT_PER_DOUBLE_BUFF [28:28]
/// Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
INTERRUPT_PER_DOUBLE_BUFF: u1 = 0,
/// INTERRUPT_PER_BUFF [29:29]
/// Trigger an interrupt each time a buffer is done.
INTERRUPT_PER_BUFF: u1 = 0,
/// DOUBLE_BUFFERED [30:30]
/// This endpoint is double buffered.
DOUBLE_BUFFERED: u1 = 0,
/// ENABLE [31:31]
/// Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
ENABLE: u1 = 0,
};
/// No description
pub const EP3_OUT_CONTROL = Register(EP3_OUT_CONTROL_val).init(base_address + 0x1c);
/// EP3_IN_CONTROL
const EP3_IN_CONTROL_val = packed struct {
/// BUFFER_ADDRESS [0:15]
/// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
BUFFER_ADDRESS: u16 = 0,
/// INTERRUPT_ON_NAK [16:16]
/// Trigger an interrupt if a NAK is sent. Intended for debug only.
INTERRUPT_ON_NAK: u1 = 0,
/// INTERRUPT_ON_STALL [17:17]
/// Trigger an interrupt if a STALL is sent. Intended for debug only.
INTERRUPT_ON_STALL: u1 = 0,
/// unused [18:25]
_unused18: u6 = 0,
_unused24: u2 = 0,
/// ENDPOINT_TYPE [26:27]
/// No description
ENDPOINT_TYPE: u2 = 0,
/// INTERRUPT_PER_DOUBLE_BUFF [28:28]
/// Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
INTERRUPT_PER_DOUBLE_BUFF: u1 = 0,
/// INTERRUPT_PER_BUFF [29:29]
/// Trigger an interrupt each time a buffer is done.
INTERRUPT_PER_BUFF: u1 = 0,
/// DOUBLE_BUFFERED [30:30]
/// This endpoint is double buffered.
DOUBLE_BUFFERED: u1 = 0,
/// ENABLE [31:31]
/// Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
ENABLE: u1 = 0,
};
/// No description
pub const EP3_IN_CONTROL = Register(EP3_IN_CONTROL_val).init(base_address + 0x18);
/// EP2_OUT_CONTROL
const EP2_OUT_CONTROL_val = packed struct {
/// BUFFER_ADDRESS [0:15]
/// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
BUFFER_ADDRESS: u16 = 0,
/// INTERRUPT_ON_NAK [16:16]
/// Trigger an interrupt if a NAK is sent. Intended for debug only.
INTERRUPT_ON_NAK: u1 = 0,
/// INTERRUPT_ON_STALL [17:17]
/// Trigger an interrupt if a STALL is sent. Intended for debug only.
INTERRUPT_ON_STALL: u1 = 0,
/// unused [18:25]
_unused18: u6 = 0,
_unused24: u2 = 0,
/// ENDPOINT_TYPE [26:27]
/// No description
ENDPOINT_TYPE: u2 = 0,
/// INTERRUPT_PER_DOUBLE_BUFF [28:28]
/// Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
INTERRUPT_PER_DOUBLE_BUFF: u1 = 0,
/// INTERRUPT_PER_BUFF [29:29]
/// Trigger an interrupt each time a buffer is done.
INTERRUPT_PER_BUFF: u1 = 0,
/// DOUBLE_BUFFERED [30:30]
/// This endpoint is double buffered.
DOUBLE_BUFFERED: u1 = 0,
/// ENABLE [31:31]
/// Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
ENABLE: u1 = 0,
};
/// No description
pub const EP2_OUT_CONTROL = Register(EP2_OUT_CONTROL_val).init(base_address + 0x14);
/// EP2_IN_CONTROL
const EP2_IN_CONTROL_val = packed struct {
/// BUFFER_ADDRESS [0:15]
/// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
BUFFER_ADDRESS: u16 = 0,
/// INTERRUPT_ON_NAK [16:16]
/// Trigger an interrupt if a NAK is sent. Intended for debug only.
INTERRUPT_ON_NAK: u1 = 0,
/// INTERRUPT_ON_STALL [17:17]
/// Trigger an interrupt if a STALL is sent. Intended for debug only.
INTERRUPT_ON_STALL: u1 = 0,
/// unused [18:25]
_unused18: u6 = 0,
_unused24: u2 = 0,
/// ENDPOINT_TYPE [26:27]
/// No description
ENDPOINT_TYPE: u2 = 0,
/// INTERRUPT_PER_DOUBLE_BUFF [28:28]
/// Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
INTERRUPT_PER_DOUBLE_BUFF: u1 = 0,
/// INTERRUPT_PER_BUFF [29:29]
/// Trigger an interrupt each time a buffer is done.
INTERRUPT_PER_BUFF: u1 = 0,
/// DOUBLE_BUFFERED [30:30]
/// This endpoint is double buffered.
DOUBLE_BUFFERED: u1 = 0,
/// ENABLE [31:31]
/// Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
ENABLE: u1 = 0,
};
/// No description
pub const EP2_IN_CONTROL = Register(EP2_IN_CONTROL_val).init(base_address + 0x10);
/// EP1_OUT_CONTROL
const EP1_OUT_CONTROL_val = packed struct {
/// BUFFER_ADDRESS [0:15]
/// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
BUFFER_ADDRESS: u16 = 0,
/// INTERRUPT_ON_NAK [16:16]
/// Trigger an interrupt if a NAK is sent. Intended for debug only.
INTERRUPT_ON_NAK: u1 = 0,
/// INTERRUPT_ON_STALL [17:17]
/// Trigger an interrupt if a STALL is sent. Intended for debug only.
INTERRUPT_ON_STALL: u1 = 0,
/// unused [18:25]
_unused18: u6 = 0,
_unused24: u2 = 0,
/// ENDPOINT_TYPE [26:27]
/// No description
ENDPOINT_TYPE: u2 = 0,
/// INTERRUPT_PER_DOUBLE_BUFF [28:28]
/// Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
INTERRUPT_PER_DOUBLE_BUFF: u1 = 0,
/// INTERRUPT_PER_BUFF [29:29]
/// Trigger an interrupt each time a buffer is done.
INTERRUPT_PER_BUFF: u1 = 0,
/// DOUBLE_BUFFERED [30:30]
/// This endpoint is double buffered.
DOUBLE_BUFFERED: u1 = 0,
/// ENABLE [31:31]
/// Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
ENABLE: u1 = 0,
};
/// No description
pub const EP1_OUT_CONTROL = Register(EP1_OUT_CONTROL_val).init(base_address + 0xc);
/// EP1_IN_CONTROL
const EP1_IN_CONTROL_val = packed struct {
/// BUFFER_ADDRESS [0:15]
/// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
BUFFER_ADDRESS: u16 = 0,
/// INTERRUPT_ON_NAK [16:16]
/// Trigger an interrupt if a NAK is sent. Intended for debug only.
INTERRUPT_ON_NAK: u1 = 0,
/// INTERRUPT_ON_STALL [17:17]
/// Trigger an interrupt if a STALL is sent. Intended for debug only.
INTERRUPT_ON_STALL: u1 = 0,
/// unused [18:25]
_unused18: u6 = 0,
_unused24: u2 = 0,
/// ENDPOINT_TYPE [26:27]
/// No description
ENDPOINT_TYPE: u2 = 0,
/// INTERRUPT_PER_DOUBLE_BUFF [28:28]
/// Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
INTERRUPT_PER_DOUBLE_BUFF: u1 = 0,
/// INTERRUPT_PER_BUFF [29:29]
/// Trigger an interrupt each time a buffer is done.
INTERRUPT_PER_BUFF: u1 = 0,
/// DOUBLE_BUFFERED [30:30]
/// This endpoint is double buffered.
DOUBLE_BUFFERED: u1 = 0,
/// ENABLE [31:31]
/// Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
ENABLE: u1 = 0,
};
/// No description
pub const EP1_IN_CONTROL = Register(EP1_IN_CONTROL_val).init(base_address + 0x8);
/// SETUP_PACKET_HIGH
const SETUP_PACKET_HIGH_val = packed struct {
/// WINDEX [0:15]
/// No description
WINDEX: u16 = 0,
/// WLENGTH [16:31]
/// No description
WLENGTH: u16 = 0,
};
/// Bytes 4-7 of the setup packet from the host.
pub const SETUP_PACKET_HIGH = Register(SETUP_PACKET_HIGH_val).init(base_address + 0x4);
/// SETUP_PACKET_LOW
const SETUP_PACKET_LOW_val = packed struct {
/// BMREQUESTTYPE [0:7]
/// No description
BMREQUESTTYPE: u8 = 0,
/// BREQUEST [8:15]
/// No description
BREQUEST: u8 = 0,
/// WVALUE [16:31]
/// No description
WVALUE: u16 = 0,
};
/// Bytes 0-3 of the SETUP packet from the host.
pub const SETUP_PACKET_LOW = Register(SETUP_PACKET_LOW_val).init(base_address + 0x0);
};
/// USB FS/LS controller device registers
pub const USBCTRL_REGS = struct {
const base_address = 0x50110000;
/// INTS
const INTS_val = packed struct {
/// HOST_CONN_DIS [0:0]
/// Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED
HOST_CONN_DIS: u1 = 0,
/// HOST_RESUME [1:1]
/// Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME
HOST_RESUME: u1 = 0,
/// HOST_SOF [2:2]
/// Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD
HOST_SOF: u1 = 0,
/// TRANS_COMPLETE [3:3]
/// Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.
TRANS_COMPLETE: u1 = 0,
/// BUFF_STATUS [4:4]
/// Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.
BUFF_STATUS: u1 = 0,
/// ERROR_DATA_SEQ [5:5]
/// Source: SIE_STATUS.DATA_SEQ_ERROR
ERROR_DATA_SEQ: u1 = 0,
/// ERROR_RX_TIMEOUT [6:6]
/// Source: SIE_STATUS.RX_TIMEOUT
ERROR_RX_TIMEOUT: u1 = 0,
/// ERROR_RX_OVERFLOW [7:7]
/// Source: SIE_STATUS.RX_OVERFLOW
ERROR_RX_OVERFLOW: u1 = 0,
/// ERROR_BIT_STUFF [8:8]
/// Source: SIE_STATUS.BIT_STUFF_ERROR
ERROR_BIT_STUFF: u1 = 0,
/// ERROR_CRC [9:9]
/// Source: SIE_STATUS.CRC_ERROR
ERROR_CRC: u1 = 0,
/// STALL [10:10]
/// Source: SIE_STATUS.STALL_REC
STALL: u1 = 0,
/// VBUS_DETECT [11:11]
/// Source: SIE_STATUS.VBUS_DETECT
VBUS_DETECT: u1 = 0,
/// BUS_RESET [12:12]
/// Source: SIE_STATUS.BUS_RESET
BUS_RESET: u1 = 0,
/// DEV_CONN_DIS [13:13]
/// Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED
DEV_CONN_DIS: u1 = 0,
/// DEV_SUSPEND [14:14]
/// Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED
DEV_SUSPEND: u1 = 0,
/// DEV_RESUME_FROM_HOST [15:15]
/// Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME
DEV_RESUME_FROM_HOST: u1 = 0,
/// SETUP_REQ [16:16]
/// Device. Source: SIE_STATUS.SETUP_REC
SETUP_REQ: u1 = 0,
/// DEV_SOF [17:17]
/// Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD
DEV_SOF: u1 = 0,
/// ABORT_DONE [18:18]
/// Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.
ABORT_DONE: u1 = 0,
/// EP_STALL_NAK [19:19]
/// Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.
EP_STALL_NAK: u1 = 0,
/// unused [20:31]
_unused20: u4 = 0,
_unused24: u8 = 0,
};
/// Interrupt status after masking & forcing
pub const INTS = Register(INTS_val).init(base_address + 0x98);
/// INTF
const INTF_val = packed struct {
/// HOST_CONN_DIS [0:0]
/// Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED
HOST_CONN_DIS: u1 = 0,
/// HOST_RESUME [1:1]
/// Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME
HOST_RESUME: u1 = 0,
/// HOST_SOF [2:2]
/// Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD
HOST_SOF: u1 = 0,
/// TRANS_COMPLETE [3:3]
/// Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.
TRANS_COMPLETE: u1 = 0,
/// BUFF_STATUS [4:4]
/// Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.
BUFF_STATUS: u1 = 0,
/// ERROR_DATA_SEQ [5:5]
/// Source: SIE_STATUS.DATA_SEQ_ERROR
ERROR_DATA_SEQ: u1 = 0,
/// ERROR_RX_TIMEOUT [6:6]
/// Source: SIE_STATUS.RX_TIMEOUT
ERROR_RX_TIMEOUT: u1 = 0,
/// ERROR_RX_OVERFLOW [7:7]
/// Source: SIE_STATUS.RX_OVERFLOW
ERROR_RX_OVERFLOW: u1 = 0,
/// ERROR_BIT_STUFF [8:8]
/// Source: SIE_STATUS.BIT_STUFF_ERROR
ERROR_BIT_STUFF: u1 = 0,
/// ERROR_CRC [9:9]
/// Source: SIE_STATUS.CRC_ERROR
ERROR_CRC: u1 = 0,
/// STALL [10:10]
/// Source: SIE_STATUS.STALL_REC
STALL: u1 = 0,
/// VBUS_DETECT [11:11]
/// Source: SIE_STATUS.VBUS_DETECT
VBUS_DETECT: u1 = 0,
/// BUS_RESET [12:12]
/// Source: SIE_STATUS.BUS_RESET
BUS_RESET: u1 = 0,
/// DEV_CONN_DIS [13:13]
/// Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED
DEV_CONN_DIS: u1 = 0,
/// DEV_SUSPEND [14:14]
/// Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED
DEV_SUSPEND: u1 = 0,
/// DEV_RESUME_FROM_HOST [15:15]
/// Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME
DEV_RESUME_FROM_HOST: u1 = 0,
/// SETUP_REQ [16:16]
/// Device. Source: SIE_STATUS.SETUP_REC
SETUP_REQ: u1 = 0,
/// DEV_SOF [17:17]
/// Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD
DEV_SOF: u1 = 0,
/// ABORT_DONE [18:18]
/// Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.
ABORT_DONE: u1 = 0,
/// EP_STALL_NAK [19:19]
/// Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.
EP_STALL_NAK: u1 = 0,
/// unused [20:31]
_unused20: u4 = 0,
_unused24: u8 = 0,
};
/// Interrupt Force
pub const INTF = Register(INTF_val).init(base_address + 0x94);
/// INTE
const INTE_val = packed struct {
/// HOST_CONN_DIS [0:0]
/// Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED
HOST_CONN_DIS: u1 = 0,
/// HOST_RESUME [1:1]
/// Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME
HOST_RESUME: u1 = 0,
/// HOST_SOF [2:2]
/// Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD
HOST_SOF: u1 = 0,
/// TRANS_COMPLETE [3:3]
/// Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.
TRANS_COMPLETE: u1 = 0,
/// BUFF_STATUS [4:4]
/// Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.
BUFF_STATUS: u1 = 0,
/// ERROR_DATA_SEQ [5:5]
/// Source: SIE_STATUS.DATA_SEQ_ERROR
ERROR_DATA_SEQ: u1 = 0,
/// ERROR_RX_TIMEOUT [6:6]
/// Source: SIE_STATUS.RX_TIMEOUT
ERROR_RX_TIMEOUT: u1 = 0,
/// ERROR_RX_OVERFLOW [7:7]
/// Source: SIE_STATUS.RX_OVERFLOW
ERROR_RX_OVERFLOW: u1 = 0,
/// ERROR_BIT_STUFF [8:8]
/// Source: SIE_STATUS.BIT_STUFF_ERROR
ERROR_BIT_STUFF: u1 = 0,
/// ERROR_CRC [9:9]
/// Source: SIE_STATUS.CRC_ERROR
ERROR_CRC: u1 = 0,
/// STALL [10:10]
/// Source: SIE_STATUS.STALL_REC
STALL: u1 = 0,
/// VBUS_DETECT [11:11]
/// Source: SIE_STATUS.VBUS_DETECT
VBUS_DETECT: u1 = 0,
/// BUS_RESET [12:12]
/// Source: SIE_STATUS.BUS_RESET
BUS_RESET: u1 = 0,
/// DEV_CONN_DIS [13:13]
/// Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED
DEV_CONN_DIS: u1 = 0,
/// DEV_SUSPEND [14:14]
/// Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED
DEV_SUSPEND: u1 = 0,
/// DEV_RESUME_FROM_HOST [15:15]
/// Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME
DEV_RESUME_FROM_HOST: u1 = 0,
/// SETUP_REQ [16:16]
/// Device. Source: SIE_STATUS.SETUP_REC
SETUP_REQ: u1 = 0,
/// DEV_SOF [17:17]
/// Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD
DEV_SOF: u1 = 0,
/// ABORT_DONE [18:18]
/// Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.
ABORT_DONE: u1 = 0,
/// EP_STALL_NAK [19:19]
/// Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.
EP_STALL_NAK: u1 = 0,
/// unused [20:31]
_unused20: u4 = 0,
_unused24: u8 = 0,
};
/// Interrupt Enable
pub const INTE = Register(INTE_val).init(base_address + 0x90);
/// INTR
const INTR_val = packed struct {
/// HOST_CONN_DIS [0:0]
/// Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED
HOST_CONN_DIS: u1 = 0,
/// HOST_RESUME [1:1]
/// Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME
HOST_RESUME: u1 = 0,
/// HOST_SOF [2:2]
/// Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD
HOST_SOF: u1 = 0,
/// TRANS_COMPLETE [3:3]
/// Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.
TRANS_COMPLETE: u1 = 0,
/// BUFF_STATUS [4:4]
/// Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.
BUFF_STATUS: u1 = 0,
/// ERROR_DATA_SEQ [5:5]
/// Source: SIE_STATUS.DATA_SEQ_ERROR
ERROR_DATA_SEQ: u1 = 0,
/// ERROR_RX_TIMEOUT [6:6]
/// Source: SIE_STATUS.RX_TIMEOUT
ERROR_RX_TIMEOUT: u1 = 0,
/// ERROR_RX_OVERFLOW [7:7]
/// Source: SIE_STATUS.RX_OVERFLOW
ERROR_RX_OVERFLOW: u1 = 0,
/// ERROR_BIT_STUFF [8:8]
/// Source: SIE_STATUS.BIT_STUFF_ERROR
ERROR_BIT_STUFF: u1 = 0,
/// ERROR_CRC [9:9]
/// Source: SIE_STATUS.CRC_ERROR
ERROR_CRC: u1 = 0,
/// STALL [10:10]
/// Source: SIE_STATUS.STALL_REC
STALL: u1 = 0,
/// VBUS_DETECT [11:11]
/// Source: SIE_STATUS.VBUS_DETECT
VBUS_DETECT: u1 = 0,
/// BUS_RESET [12:12]
/// Source: SIE_STATUS.BUS_RESET
BUS_RESET: u1 = 0,
/// DEV_CONN_DIS [13:13]
/// Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED
DEV_CONN_DIS: u1 = 0,
/// DEV_SUSPEND [14:14]
/// Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED
DEV_SUSPEND: u1 = 0,
/// DEV_RESUME_FROM_HOST [15:15]
/// Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME
DEV_RESUME_FROM_HOST: u1 = 0,
/// SETUP_REQ [16:16]
/// Device. Source: SIE_STATUS.SETUP_REC
SETUP_REQ: u1 = 0,
/// DEV_SOF [17:17]
/// Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD
DEV_SOF: u1 = 0,
/// ABORT_DONE [18:18]
/// Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.
ABORT_DONE: u1 = 0,
/// EP_STALL_NAK [19:19]
/// Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.
EP_STALL_NAK: u1 = 0,
/// unused [20:31]
_unused20: u4 = 0,
_unused24: u8 = 0,
};
/// Raw Interrupts
pub const INTR = Register(INTR_val).init(base_address + 0x8c);
/// USBPHY_TRIM
const USBPHY_TRIM_val = packed struct {
/// DP_PULLDN_TRIM [0:4]
/// Value to drive to USB PHY\n
DP_PULLDN_TRIM: u5 = 31,
/// unused [5:7]
_unused5: u3 = 0,
/// DM_PULLDN_TRIM [8:12]
/// Value to drive to USB PHY\n
DM_PULLDN_TRIM: u5 = 31,
/// unused [13:31]
_unused13: u3 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Used to adjust trim values of USB phy pull down resistors.
pub const USBPHY_TRIM = Register(USBPHY_TRIM_val).init(base_address + 0x84);
/// USBPHY_DIRECT_OVERRIDE
const USBPHY_DIRECT_OVERRIDE_val = packed struct {
/// DP_PULLUP_HISEL_OVERRIDE_EN [0:0]
/// No description
DP_PULLUP_HISEL_OVERRIDE_EN: u1 = 0,
/// DM_PULLUP_HISEL_OVERRIDE_EN [1:1]
/// No description
DM_PULLUP_HISEL_OVERRIDE_EN: u1 = 0,
/// DP_PULLUP_EN_OVERRIDE_EN [2:2]
/// No description
DP_PULLUP_EN_OVERRIDE_EN: u1 = 0,
/// DP_PULLDN_EN_OVERRIDE_EN [3:3]
/// No description
DP_PULLDN_EN_OVERRIDE_EN: u1 = 0,
/// DM_PULLDN_EN_OVERRIDE_EN [4:4]
/// No description
DM_PULLDN_EN_OVERRIDE_EN: u1 = 0,
/// TX_DP_OE_OVERRIDE_EN [5:5]
/// No description
TX_DP_OE_OVERRIDE_EN: u1 = 0,
/// TX_DM_OE_OVERRIDE_EN [6:6]
/// No description
TX_DM_OE_OVERRIDE_EN: u1 = 0,
/// TX_DP_OVERRIDE_EN [7:7]
/// No description
TX_DP_OVERRIDE_EN: u1 = 0,
/// TX_DM_OVERRIDE_EN [8:8]
/// No description
TX_DM_OVERRIDE_EN: u1 = 0,
/// RX_PD_OVERRIDE_EN [9:9]
/// No description
RX_PD_OVERRIDE_EN: u1 = 0,
/// TX_PD_OVERRIDE_EN [10:10]
/// No description
TX_PD_OVERRIDE_EN: u1 = 0,
/// TX_FSSLEW_OVERRIDE_EN [11:11]
/// No description
TX_FSSLEW_OVERRIDE_EN: u1 = 0,
/// DM_PULLUP_OVERRIDE_EN [12:12]
/// No description
DM_PULLUP_OVERRIDE_EN: u1 = 0,
/// unused [13:14]
_unused13: u2 = 0,
/// TX_DIFFMODE_OVERRIDE_EN [15:15]
/// No description
TX_DIFFMODE_OVERRIDE_EN: u1 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Override enable for each control in usbphy_direct
pub const USBPHY_DIRECT_OVERRIDE = Register(USBPHY_DIRECT_OVERRIDE_val).init(base_address + 0x80);
/// USBPHY_DIRECT
const USBPHY_DIRECT_val = packed struct {
/// DP_PULLUP_HISEL [0:0]
/// Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2
DP_PULLUP_HISEL: u1 = 0,
/// DP_PULLUP_EN [1:1]
/// DP pull up enable
DP_PULLUP_EN: u1 = 0,
/// DP_PULLDN_EN [2:2]
/// DP pull down enable
DP_PULLDN_EN: u1 = 0,
/// unused [3:3]
_unused3: u1 = 0,
/// DM_PULLUP_HISEL [4:4]
/// Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2
DM_PULLUP_HISEL: u1 = 0,
/// DM_PULLUP_EN [5:5]
/// DM pull up enable
DM_PULLUP_EN: u1 = 0,
/// DM_PULLDN_EN [6:6]
/// DM pull down enable
DM_PULLDN_EN: u1 = 0,
/// unused [7:7]
_unused7: u1 = 0,
/// TX_DP_OE [8:8]
/// Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving\n
TX_DP_OE: u1 = 0,
/// TX_DM_OE [9:9]
/// Output enable. If TX_DIFFMODE=1, Ignored.\n
TX_DM_OE: u1 = 0,
/// TX_DP [10:10]
/// Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP\n
TX_DP: u1 = 0,
/// TX_DM [11:11]
/// Output data. TX_DIFFMODE=1, Ignored\n
TX_DM: u1 = 0,
/// RX_PD [12:12]
/// RX power down override (if override enable is set). 1 = powered down.
RX_PD: u1 = 0,
/// TX_PD [13:13]
/// TX power down override (if override enable is set). 1 = powered down.
TX_PD: u1 = 0,
/// TX_FSSLEW [14:14]
/// TX_FSSLEW=0: Low speed slew rate\n
TX_FSSLEW: u1 = 0,
/// TX_DIFFMODE [15:15]
/// TX_DIFFMODE=0: Single ended mode\n
TX_DIFFMODE: u1 = 0,
/// RX_DD [16:16]
/// Differential RX
RX_DD: u1 = 0,
/// RX_DP [17:17]
/// DPP pin state
RX_DP: u1 = 0,
/// RX_DM [18:18]
/// DPM pin state
RX_DM: u1 = 0,
/// DP_OVCN [19:19]
/// DP overcurrent
DP_OVCN: u1 = 0,
/// DM_OVCN [20:20]
/// DM overcurrent
DM_OVCN: u1 = 0,
/// DP_OVV [21:21]
/// DP over voltage
DP_OVV: u1 = 0,
/// DM_OVV [22:22]
/// DM over voltage
DM_OVV: u1 = 0,
/// unused [23:31]
_unused23: u1 = 0,
_unused24: u8 = 0,
};
/// This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit.
pub const USBPHY_DIRECT = Register(USBPHY_DIRECT_val).init(base_address + 0x7c);
/// USB_PWR
const USB_PWR_val = packed struct {
/// VBUS_EN [0:0]
/// No description
VBUS_EN: u1 = 0,
/// VBUS_EN_OVERRIDE_EN [1:1]
/// No description
VBUS_EN_OVERRIDE_EN: u1 = 0,
/// VBUS_DETECT [2:2]
/// No description
VBUS_DETECT: u1 = 0,
/// VBUS_DETECT_OVERRIDE_EN [3:3]
/// No description
VBUS_DETECT_OVERRIDE_EN: u1 = 0,
/// OVERCURR_DETECT [4:4]
/// No description
OVERCURR_DETECT: u1 = 0,
/// OVERCURR_DETECT_EN [5:5]
/// No description
OVERCURR_DETECT_EN: u1 = 0,
/// unused [6:31]
_unused6: u2 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value.
pub const USB_PWR = Register(USB_PWR_val).init(base_address + 0x78);
/// USB_MUXING
const USB_MUXING_val = packed struct {
/// TO_PHY [0:0]
/// No description
TO_PHY: u1 = 0,
/// TO_EXTPHY [1:1]
/// No description
TO_EXTPHY: u1 = 0,
/// TO_DIGITAL_PAD [2:2]
/// No description
TO_DIGITAL_PAD: u1 = 0,
/// SOFTCON [3:3]
/// No description
SOFTCON: u1 = 0,
/// unused [4:31]
_unused4: u4 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Where to connect the USB controller. Should be to_phy by default.
pub const USB_MUXING = Register(USB_MUXING_val).init(base_address + 0x74);
/// EP_STATUS_STALL_NAK
const EP_STATUS_STALL_NAK_val = packed struct {
/// EP0_IN [0:0]
/// No description
EP0_IN: u1 = 0,
/// EP0_OUT [1:1]
/// No description
EP0_OUT: u1 = 0,
/// EP1_IN [2:2]
/// No description
EP1_IN: u1 = 0,
/// EP1_OUT [3:3]
/// No description
EP1_OUT: u1 = 0,
/// EP2_IN [4:4]
/// No description
EP2_IN: u1 = 0,
/// EP2_OUT [5:5]
/// No description
EP2_OUT: u1 = 0,
/// EP3_IN [6:6]
/// No description
EP3_IN: u1 = 0,
/// EP3_OUT [7:7]
/// No description
EP3_OUT: u1 = 0,
/// EP4_IN [8:8]
/// No description
EP4_IN: u1 = 0,
/// EP4_OUT [9:9]
/// No description
EP4_OUT: u1 = 0,
/// EP5_IN [10:10]
/// No description
EP5_IN: u1 = 0,
/// EP5_OUT [11:11]
/// No description
EP5_OUT: u1 = 0,
/// EP6_IN [12:12]
/// No description
EP6_IN: u1 = 0,
/// EP6_OUT [13:13]
/// No description
EP6_OUT: u1 = 0,
/// EP7_IN [14:14]
/// No description
EP7_IN: u1 = 0,
/// EP7_OUT [15:15]
/// No description
EP7_OUT: u1 = 0,
/// EP8_IN [16:16]
/// No description
EP8_IN: u1 = 0,
/// EP8_OUT [17:17]
/// No description
EP8_OUT: u1 = 0,
/// EP9_IN [18:18]
/// No description
EP9_IN: u1 = 0,
/// EP9_OUT [19:19]
/// No description
EP9_OUT: u1 = 0,
/// EP10_IN [20:20]
/// No description
EP10_IN: u1 = 0,
/// EP10_OUT [21:21]
/// No description
EP10_OUT: u1 = 0,
/// EP11_IN [22:22]
/// No description
EP11_IN: u1 = 0,
/// EP11_OUT [23:23]
/// No description
EP11_OUT: u1 = 0,
/// EP12_IN [24:24]
/// No description
EP12_IN: u1 = 0,
/// EP12_OUT [25:25]
/// No description
EP12_OUT: u1 = 0,
/// EP13_IN [26:26]
/// No description
EP13_IN: u1 = 0,
/// EP13_OUT [27:27]
/// No description
EP13_OUT: u1 = 0,
/// EP14_IN [28:28]
/// No description
EP14_IN: u1 = 0,
/// EP14_OUT [29:29]
/// No description
EP14_OUT: u1 = 0,
/// EP15_IN [30:30]
/// No description
EP15_IN: u1 = 0,
/// EP15_OUT [31:31]
/// No description
EP15_OUT: u1 = 0,
};
/// Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register.
pub const EP_STATUS_STALL_NAK = Register(EP_STATUS_STALL_NAK_val).init(base_address + 0x70);
/// NAK_POLL
const NAK_POLL_val = packed struct {
/// DELAY_LS [0:9]
/// NAK polling interval for a low speed device
DELAY_LS: u10 = 16,
/// unused [10:15]
_unused10: u6 = 0,
/// DELAY_FS [16:25]
/// NAK polling interval for a full speed device
DELAY_FS: u10 = 16,
/// unused [26:31]
_unused26: u6 = 0,
};
/// Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK.
pub const NAK_POLL = Register(NAK_POLL_val).init(base_address + 0x6c);
/// EP_STALL_ARM
const EP_STALL_ARM_val = packed struct {
/// EP0_IN [0:0]
/// No description
EP0_IN: u1 = 0,
/// EP0_OUT [1:1]
/// No description
EP0_OUT: u1 = 0,
/// unused [2:31]
_unused2: u6 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received.
pub const EP_STALL_ARM = Register(EP_STALL_ARM_val).init(base_address + 0x68);
/// EP_ABORT_DONE
const EP_ABORT_DONE_val = packed struct {
/// EP0_IN [0:0]
/// No description
EP0_IN: u1 = 0,
/// EP0_OUT [1:1]
/// No description
EP0_OUT: u1 = 0,
/// EP1_IN [2:2]
/// No description
EP1_IN: u1 = 0,
/// EP1_OUT [3:3]
/// No description
EP1_OUT: u1 = 0,
/// EP2_IN [4:4]
/// No description
EP2_IN: u1 = 0,
/// EP2_OUT [5:5]
/// No description
EP2_OUT: u1 = 0,
/// EP3_IN [6:6]
/// No description
EP3_IN: u1 = 0,
/// EP3_OUT [7:7]
/// No description
EP3_OUT: u1 = 0,
/// EP4_IN [8:8]
/// No description
EP4_IN: u1 = 0,
/// EP4_OUT [9:9]
/// No description
EP4_OUT: u1 = 0,
/// EP5_IN [10:10]
/// No description
EP5_IN: u1 = 0,
/// EP5_OUT [11:11]
/// No description
EP5_OUT: u1 = 0,
/// EP6_IN [12:12]
/// No description
EP6_IN: u1 = 0,
/// EP6_OUT [13:13]
/// No description
EP6_OUT: u1 = 0,
/// EP7_IN [14:14]
/// No description
EP7_IN: u1 = 0,
/// EP7_OUT [15:15]
/// No description
EP7_OUT: u1 = 0,
/// EP8_IN [16:16]
/// No description
EP8_IN: u1 = 0,
/// EP8_OUT [17:17]
/// No description
EP8_OUT: u1 = 0,
/// EP9_IN [18:18]
/// No description
EP9_IN: u1 = 0,
/// EP9_OUT [19:19]
/// No description
EP9_OUT: u1 = 0,
/// EP10_IN [20:20]
/// No description
EP10_IN: u1 = 0,
/// EP10_OUT [21:21]
/// No description
EP10_OUT: u1 = 0,
/// EP11_IN [22:22]
/// No description
EP11_IN: u1 = 0,
/// EP11_OUT [23:23]
/// No description
EP11_OUT: u1 = 0,
/// EP12_IN [24:24]
/// No description
EP12_IN: u1 = 0,
/// EP12_OUT [25:25]
/// No description
EP12_OUT: u1 = 0,
/// EP13_IN [26:26]
/// No description
EP13_IN: u1 = 0,
/// EP13_OUT [27:27]
/// No description
EP13_OUT: u1 = 0,
/// EP14_IN [28:28]
/// No description
EP14_IN: u1 = 0,
/// EP14_OUT [29:29]
/// No description
EP14_OUT: u1 = 0,
/// EP15_IN [30:30]
/// No description
EP15_IN: u1 = 0,
/// EP15_OUT [31:31]
/// No description
EP15_OUT: u1 = 0,
};
/// Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register.
pub const EP_ABORT_DONE = Register(EP_ABORT_DONE_val).init(base_address + 0x64);
/// EP_ABORT
const EP_ABORT_val = packed struct {
/// EP0_IN [0:0]
/// No description
EP0_IN: u1 = 0,
/// EP0_OUT [1:1]
/// No description
EP0_OUT: u1 = 0,
/// EP1_IN [2:2]
/// No description
EP1_IN: u1 = 0,
/// EP1_OUT [3:3]
/// No description
EP1_OUT: u1 = 0,
/// EP2_IN [4:4]
/// No description
EP2_IN: u1 = 0,
/// EP2_OUT [5:5]
/// No description
EP2_OUT: u1 = 0,
/// EP3_IN [6:6]
/// No description
EP3_IN: u1 = 0,
/// EP3_OUT [7:7]
/// No description
EP3_OUT: u1 = 0,
/// EP4_IN [8:8]
/// No description
EP4_IN: u1 = 0,
/// EP4_OUT [9:9]
/// No description
EP4_OUT: u1 = 0,
/// EP5_IN [10:10]
/// No description
EP5_IN: u1 = 0,
/// EP5_OUT [11:11]
/// No description
EP5_OUT: u1 = 0,
/// EP6_IN [12:12]
/// No description
EP6_IN: u1 = 0,
/// EP6_OUT [13:13]
/// No description
EP6_OUT: u1 = 0,
/// EP7_IN [14:14]
/// No description
EP7_IN: u1 = 0,
/// EP7_OUT [15:15]
/// No description
EP7_OUT: u1 = 0,
/// EP8_IN [16:16]
/// No description
EP8_IN: u1 = 0,
/// EP8_OUT [17:17]
/// No description
EP8_OUT: u1 = 0,
/// EP9_IN [18:18]
/// No description
EP9_IN: u1 = 0,
/// EP9_OUT [19:19]
/// No description
EP9_OUT: u1 = 0,
/// EP10_IN [20:20]
/// No description
EP10_IN: u1 = 0,
/// EP10_OUT [21:21]
/// No description
EP10_OUT: u1 = 0,
/// EP11_IN [22:22]
/// No description
EP11_IN: u1 = 0,
/// EP11_OUT [23:23]
/// No description
EP11_OUT: u1 = 0,
/// EP12_IN [24:24]
/// No description
EP12_IN: u1 = 0,
/// EP12_OUT [25:25]
/// No description
EP12_OUT: u1 = 0,
/// EP13_IN [26:26]
/// No description
EP13_IN: u1 = 0,
/// EP13_OUT [27:27]
/// No description
EP13_OUT: u1 = 0,
/// EP14_IN [28:28]
/// No description
EP14_IN: u1 = 0,
/// EP14_OUT [29:29]
/// No description
EP14_OUT: u1 = 0,
/// EP15_IN [30:30]
/// No description
EP15_IN: u1 = 0,
/// EP15_OUT [31:31]
/// No description
EP15_OUT: u1 = 0,
};
/// Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register.
pub const EP_ABORT = Register(EP_ABORT_val).init(base_address + 0x60);
/// BUFF_CPU_SHOULD_HANDLE
const BUFF_CPU_SHOULD_HANDLE_val = packed struct {
/// EP0_IN [0:0]
/// No description
EP0_IN: u1 = 0,
/// EP0_OUT [1:1]
/// No description
EP0_OUT: u1 = 0,
/// EP1_IN [2:2]
/// No description
EP1_IN: u1 = 0,
/// EP1_OUT [3:3]
/// No description
EP1_OUT: u1 = 0,
/// EP2_IN [4:4]
/// No description
EP2_IN: u1 = 0,
/// EP2_OUT [5:5]
/// No description
EP2_OUT: u1 = 0,
/// EP3_IN [6:6]
/// No description
EP3_IN: u1 = 0,
/// EP3_OUT [7:7]
/// No description
EP3_OUT: u1 = 0,
/// EP4_IN [8:8]
/// No description
EP4_IN: u1 = 0,
/// EP4_OUT [9:9]
/// No description
EP4_OUT: u1 = 0,
/// EP5_IN [10:10]
/// No description
EP5_IN: u1 = 0,
/// EP5_OUT [11:11]
/// No description
EP5_OUT: u1 = 0,
/// EP6_IN [12:12]
/// No description
EP6_IN: u1 = 0,
/// EP6_OUT [13:13]
/// No description
EP6_OUT: u1 = 0,
/// EP7_IN [14:14]
/// No description
EP7_IN: u1 = 0,
/// EP7_OUT [15:15]
/// No description
EP7_OUT: u1 = 0,
/// EP8_IN [16:16]
/// No description
EP8_IN: u1 = 0,
/// EP8_OUT [17:17]
/// No description
EP8_OUT: u1 = 0,
/// EP9_IN [18:18]
/// No description
EP9_IN: u1 = 0,
/// EP9_OUT [19:19]
/// No description
EP9_OUT: u1 = 0,
/// EP10_IN [20:20]
/// No description
EP10_IN: u1 = 0,
/// EP10_OUT [21:21]
/// No description
EP10_OUT: u1 = 0,
/// EP11_IN [22:22]
/// No description
EP11_IN: u1 = 0,
/// EP11_OUT [23:23]
/// No description
EP11_OUT: u1 = 0,
/// EP12_IN [24:24]
/// No description
EP12_IN: u1 = 0,
/// EP12_OUT [25:25]
/// No description
EP12_OUT: u1 = 0,
/// EP13_IN [26:26]
/// No description
EP13_IN: u1 = 0,
/// EP13_OUT [27:27]
/// No description
EP13_OUT: u1 = 0,
/// EP14_IN [28:28]
/// No description
EP14_IN: u1 = 0,
/// EP14_OUT [29:29]
/// No description
EP14_OUT: u1 = 0,
/// EP15_IN [30:30]
/// No description
EP15_IN: u1 = 0,
/// EP15_OUT [31:31]
/// No description
EP15_OUT: u1 = 0,
};
/// Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered.
pub const BUFF_CPU_SHOULD_HANDLE = Register(BUFF_CPU_SHOULD_HANDLE_val).init(base_address + 0x5c);
/// BUFF_STATUS
const BUFF_STATUS_val = packed struct {
/// EP0_IN [0:0]
/// No description
EP0_IN: u1 = 0,
/// EP0_OUT [1:1]
/// No description
EP0_OUT: u1 = 0,
/// EP1_IN [2:2]
/// No description
EP1_IN: u1 = 0,
/// EP1_OUT [3:3]
/// No description
EP1_OUT: u1 = 0,
/// EP2_IN [4:4]
/// No description
EP2_IN: u1 = 0,
/// EP2_OUT [5:5]
/// No description
EP2_OUT: u1 = 0,
/// EP3_IN [6:6]
/// No description
EP3_IN: u1 = 0,
/// EP3_OUT [7:7]
/// No description
EP3_OUT: u1 = 0,
/// EP4_IN [8:8]
/// No description
EP4_IN: u1 = 0,
/// EP4_OUT [9:9]
/// No description
EP4_OUT: u1 = 0,
/// EP5_IN [10:10]
/// No description
EP5_IN: u1 = 0,
/// EP5_OUT [11:11]
/// No description
EP5_OUT: u1 = 0,
/// EP6_IN [12:12]
/// No description
EP6_IN: u1 = 0,
/// EP6_OUT [13:13]
/// No description
EP6_OUT: u1 = 0,
/// EP7_IN [14:14]
/// No description
EP7_IN: u1 = 0,
/// EP7_OUT [15:15]
/// No description
EP7_OUT: u1 = 0,
/// EP8_IN [16:16]
/// No description
EP8_IN: u1 = 0,
/// EP8_OUT [17:17]
/// No description
EP8_OUT: u1 = 0,
/// EP9_IN [18:18]
/// No description
EP9_IN: u1 = 0,
/// EP9_OUT [19:19]
/// No description
EP9_OUT: u1 = 0,
/// EP10_IN [20:20]
/// No description
EP10_IN: u1 = 0,
/// EP10_OUT [21:21]
/// No description
EP10_OUT: u1 = 0,
/// EP11_IN [22:22]
/// No description
EP11_IN: u1 = 0,
/// EP11_OUT [23:23]
/// No description
EP11_OUT: u1 = 0,
/// EP12_IN [24:24]
/// No description
EP12_IN: u1 = 0,
/// EP12_OUT [25:25]
/// No description
EP12_OUT: u1 = 0,
/// EP13_IN [26:26]
/// No description
EP13_IN: u1 = 0,
/// EP13_OUT [27:27]
/// No description
EP13_OUT: u1 = 0,
/// EP14_IN [28:28]
/// No description
EP14_IN: u1 = 0,
/// EP14_OUT [29:29]
/// No description
EP14_OUT: u1 = 0,
/// EP15_IN [30:30]
/// No description
EP15_IN: u1 = 0,
/// EP15_OUT [31:31]
/// No description
EP15_OUT: u1 = 0,
};
/// Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle.
pub const BUFF_STATUS = Register(BUFF_STATUS_val).init(base_address + 0x58);
/// INT_EP_CTRL
const INT_EP_CTRL_val = packed struct {
/// unused [0:0]
_unused0: u1 = 0,
/// INT_EP_ACTIVE [1:15]
/// Host: Enable interrupt endpoint 1 -> 15
INT_EP_ACTIVE: u15 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// interrupt endpoint control register
pub const INT_EP_CTRL = Register(INT_EP_CTRL_val).init(base_address + 0x54);
/// SIE_STATUS
const SIE_STATUS_val = packed struct {
/// VBUS_DETECTED [0:0]
/// Device: VBUS Detected
VBUS_DETECTED: u1 = 0,
/// unused [1:1]
_unused1: u1 = 0,
/// LINE_STATE [2:3]
/// USB bus line state
LINE_STATE: u2 = 0,
/// SUSPENDED [4:4]
/// Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled.
SUSPENDED: u1 = 0,
/// unused [5:7]
_unused5: u3 = 0,
/// SPEED [8:9]
/// Host: device speed. Disconnected = 00, LS = 01, FS = 10
SPEED: u2 = 0,
/// VBUS_OVER_CURR [10:10]
/// VBUS over current detected
VBUS_OVER_CURR: u1 = 0,
/// RESUME [11:11]
/// Host: Device has initiated a remote resume. Device: host has initiated a resume.
RESUME: u1 = 0,
/// unused [12:15]
_unused12: u4 = 0,
/// CONNECTED [16:16]
/// Device: connected
CONNECTED: u1 = 0,
/// SETUP_REC [17:17]
/// Device: Setup packet received
SETUP_REC: u1 = 0,
/// TRANS_COMPLETE [18:18]
/// Transaction complete.\n\n
TRANS_COMPLETE: u1 = 0,
/// BUS_RESET [19:19]
/// Device: bus reset received
BUS_RESET: u1 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// CRC_ERROR [24:24]
/// CRC Error. Raised by the Serial RX engine.
CRC_ERROR: u1 = 0,
/// BIT_STUFF_ERROR [25:25]
/// Bit Stuff Error. Raised by the Serial RX engine.
BIT_STUFF_ERROR: u1 = 0,
/// RX_OVERFLOW [26:26]
/// RX overflow is raised by the Serial RX engine if the incoming data is too fast.
RX_OVERFLOW: u1 = 0,
/// RX_TIMEOUT [27:27]
/// RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec.
RX_TIMEOUT: u1 = 0,
/// NAK_REC [28:28]
/// Host: NAK received
NAK_REC: u1 = 0,
/// STALL_REC [29:29]
/// Host: STALL received
STALL_REC: u1 = 0,
/// ACK_REC [30:30]
/// ACK received. Raised by both host and device.
ACK_REC: u1 = 0,
/// DATA_SEQ_ERROR [31:31]
/// Data Sequence Error.\n\n
DATA_SEQ_ERROR: u1 = 0,
};
/// SIE status register
pub const SIE_STATUS = Register(SIE_STATUS_val).init(base_address + 0x50);
/// SIE_CTRL
const SIE_CTRL_val = packed struct {
/// START_TRANS [0:0]
/// Host: Start transaction
START_TRANS: u1 = 0,
/// SEND_SETUP [1:1]
/// Host: Send Setup packet
SEND_SETUP: u1 = 0,
/// SEND_DATA [2:2]
/// Host: Send transaction (OUT from host)
SEND_DATA: u1 = 0,
/// RECEIVE_DATA [3:3]
/// Host: Receive transaction (IN to host)
RECEIVE_DATA: u1 = 0,
/// STOP_TRANS [4:4]
/// Host: Stop transaction
STOP_TRANS: u1 = 0,
/// unused [5:5]
_unused5: u1 = 0,
/// PREAMBLE_EN [6:6]
/// Host: Preable enable for LS device on FS hub
PREAMBLE_EN: u1 = 0,
/// unused [7:7]
_unused7: u1 = 0,
/// SOF_SYNC [8:8]
/// Host: Delay packet(s) until after SOF
SOF_SYNC: u1 = 0,
/// SOF_EN [9:9]
/// Host: Enable SOF generation (for full speed bus)
SOF_EN: u1 = 0,
/// KEEP_ALIVE_EN [10:10]
/// Host: Enable keep alive packet (for low speed bus)
KEEP_ALIVE_EN: u1 = 0,
/// VBUS_EN [11:11]
/// Host: Enable VBUS
VBUS_EN: u1 = 0,
/// RESUME [12:12]
/// Device: Remote wakeup. Device can initiate its own resume after suspend.
RESUME: u1 = 0,
/// RESET_BUS [13:13]
/// Host: Reset bus
RESET_BUS: u1 = 0,
/// unused [14:14]
_unused14: u1 = 0,
/// PULLDOWN_EN [15:15]
/// Host: Enable pull down resistors
PULLDOWN_EN: u1 = 0,
/// PULLUP_EN [16:16]
/// Device: Enable pull up resistor
PULLUP_EN: u1 = 0,
/// RPU_OPT [17:17]
/// Device: Pull-up strength (0=1K2, 1=2k3)
RPU_OPT: u1 = 0,
/// TRANSCEIVER_PD [18:18]
/// Power down bus transceiver
TRANSCEIVER_PD: u1 = 0,
/// unused [19:23]
_unused19: u5 = 0,
/// DIRECT_DM [24:24]
/// Direct control of DM
DIRECT_DM: u1 = 0,
/// DIRECT_DP [25:25]
/// Direct control of DP
DIRECT_DP: u1 = 0,
/// DIRECT_EN [26:26]
/// Direct bus drive enable
DIRECT_EN: u1 = 0,
/// EP0_INT_NAK [27:27]
/// Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK
EP0_INT_NAK: u1 = 0,
/// EP0_INT_2BUF [28:28]
/// Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0
EP0_INT_2BUF: u1 = 0,
/// EP0_INT_1BUF [29:29]
/// Device: Set bit in BUFF_STATUS for every buffer completed on EP0
EP0_INT_1BUF: u1 = 0,
/// EP0_DOUBLE_BUF [30:30]
/// Device: EP0 single buffered = 0, double buffered = 1
EP0_DOUBLE_BUF: u1 = 0,
/// EP0_INT_STALL [31:31]
/// Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL
EP0_INT_STALL: u1 = 0,
};
/// SIE control register
pub const SIE_CTRL = Register(SIE_CTRL_val).init(base_address + 0x4c);
/// SOF_RD
const SOF_RD_val = packed struct {
/// COUNT [0:10]
/// No description
COUNT: u11 = 0,
/// unused [11:31]
_unused11: u5 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host.
pub const SOF_RD = Register(SOF_RD_val).init(base_address + 0x48);
/// SOF_WR
const SOF_WR_val = packed struct {
/// COUNT [0:10]
/// No description
COUNT: u11 = 0,
/// unused [11:31]
_unused11: u5 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time.
pub const SOF_WR = Register(SOF_WR_val).init(base_address + 0x44);
/// MAIN_CTRL
const MAIN_CTRL_val = packed struct {
/// CONTROLLER_EN [0:0]
/// Enable controller
CONTROLLER_EN: u1 = 0,
/// HOST_NDEVICE [1:1]
/// Device mode = 0, Host mode = 1
HOST_NDEVICE: u1 = 0,
/// unused [2:30]
_unused2: u6 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u7 = 0,
/// SIM_TIMING [31:31]
/// Reduced timings for simulation
SIM_TIMING: u1 = 0,
};
/// Main control register
pub const MAIN_CTRL = Register(MAIN_CTRL_val).init(base_address + 0x40);
/// ADDR_ENDP15
const ADDR_ENDP15_val = packed struct {
/// ADDRESS [0:6]
/// Device address
ADDRESS: u7 = 0,
/// unused [7:15]
_unused7: u1 = 0,
_unused8: u8 = 0,
/// ENDPOINT [16:19]
/// Endpoint number of the interrupt endpoint
ENDPOINT: u4 = 0,
/// unused [20:24]
_unused20: u4 = 0,
_unused24: u1 = 0,
/// INTEP_DIR [25:25]
/// Direction of the interrupt endpoint. In=0, Out=1
INTEP_DIR: u1 = 0,
/// INTEP_PREAMBLE [26:26]
/// Interrupt EP requires preamble (is a low speed device on a full speed hub)
INTEP_PREAMBLE: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// Interrupt endpoint 15. Only valid for HOST mode.
pub const ADDR_ENDP15 = Register(ADDR_ENDP15_val).init(base_address + 0x3c);
/// ADDR_ENDP14
const ADDR_ENDP14_val = packed struct {
/// ADDRESS [0:6]
/// Device address
ADDRESS: u7 = 0,
/// unused [7:15]
_unused7: u1 = 0,
_unused8: u8 = 0,
/// ENDPOINT [16:19]
/// Endpoint number of the interrupt endpoint
ENDPOINT: u4 = 0,
/// unused [20:24]
_unused20: u4 = 0,
_unused24: u1 = 0,
/// INTEP_DIR [25:25]
/// Direction of the interrupt endpoint. In=0, Out=1
INTEP_DIR: u1 = 0,
/// INTEP_PREAMBLE [26:26]
/// Interrupt EP requires preamble (is a low speed device on a full speed hub)
INTEP_PREAMBLE: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// Interrupt endpoint 14. Only valid for HOST mode.
pub const ADDR_ENDP14 = Register(ADDR_ENDP14_val).init(base_address + 0x38);
/// ADDR_ENDP13
const ADDR_ENDP13_val = packed struct {
/// ADDRESS [0:6]
/// Device address
ADDRESS: u7 = 0,
/// unused [7:15]
_unused7: u1 = 0,
_unused8: u8 = 0,
/// ENDPOINT [16:19]
/// Endpoint number of the interrupt endpoint
ENDPOINT: u4 = 0,
/// unused [20:24]
_unused20: u4 = 0,
_unused24: u1 = 0,
/// INTEP_DIR [25:25]
/// Direction of the interrupt endpoint. In=0, Out=1
INTEP_DIR: u1 = 0,
/// INTEP_PREAMBLE [26:26]
/// Interrupt EP requires preamble (is a low speed device on a full speed hub)
INTEP_PREAMBLE: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// Interrupt endpoint 13. Only valid for HOST mode.
pub const ADDR_ENDP13 = Register(ADDR_ENDP13_val).init(base_address + 0x34);
/// ADDR_ENDP12
const ADDR_ENDP12_val = packed struct {
/// ADDRESS [0:6]
/// Device address
ADDRESS: u7 = 0,
/// unused [7:15]
_unused7: u1 = 0,
_unused8: u8 = 0,
/// ENDPOINT [16:19]
/// Endpoint number of the interrupt endpoint
ENDPOINT: u4 = 0,
/// unused [20:24]
_unused20: u4 = 0,
_unused24: u1 = 0,
/// INTEP_DIR [25:25]
/// Direction of the interrupt endpoint. In=0, Out=1
INTEP_DIR: u1 = 0,
/// INTEP_PREAMBLE [26:26]
/// Interrupt EP requires preamble (is a low speed device on a full speed hub)
INTEP_PREAMBLE: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// Interrupt endpoint 12. Only valid for HOST mode.
pub const ADDR_ENDP12 = Register(ADDR_ENDP12_val).init(base_address + 0x30);
/// ADDR_ENDP11
const ADDR_ENDP11_val = packed struct {
/// ADDRESS [0:6]
/// Device address
ADDRESS: u7 = 0,
/// unused [7:15]
_unused7: u1 = 0,
_unused8: u8 = 0,
/// ENDPOINT [16:19]
/// Endpoint number of the interrupt endpoint
ENDPOINT: u4 = 0,
/// unused [20:24]
_unused20: u4 = 0,
_unused24: u1 = 0,
/// INTEP_DIR [25:25]
/// Direction of the interrupt endpoint. In=0, Out=1
INTEP_DIR: u1 = 0,
/// INTEP_PREAMBLE [26:26]
/// Interrupt EP requires preamble (is a low speed device on a full speed hub)
INTEP_PREAMBLE: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// Interrupt endpoint 11. Only valid for HOST mode.
pub const ADDR_ENDP11 = Register(ADDR_ENDP11_val).init(base_address + 0x2c);
/// ADDR_ENDP10
const ADDR_ENDP10_val = packed struct {
/// ADDRESS [0:6]
/// Device address
ADDRESS: u7 = 0,
/// unused [7:15]
_unused7: u1 = 0,
_unused8: u8 = 0,
/// ENDPOINT [16:19]
/// Endpoint number of the interrupt endpoint
ENDPOINT: u4 = 0,
/// unused [20:24]
_unused20: u4 = 0,
_unused24: u1 = 0,
/// INTEP_DIR [25:25]
/// Direction of the interrupt endpoint. In=0, Out=1
INTEP_DIR: u1 = 0,
/// INTEP_PREAMBLE [26:26]
/// Interrupt EP requires preamble (is a low speed device on a full speed hub)
INTEP_PREAMBLE: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// Interrupt endpoint 10. Only valid for HOST mode.
pub const ADDR_ENDP10 = Register(ADDR_ENDP10_val).init(base_address + 0x28);
/// ADDR_ENDP9
const ADDR_ENDP9_val = packed struct {
/// ADDRESS [0:6]
/// Device address
ADDRESS: u7 = 0,
/// unused [7:15]
_unused7: u1 = 0,
_unused8: u8 = 0,
/// ENDPOINT [16:19]
/// Endpoint number of the interrupt endpoint
ENDPOINT: u4 = 0,
/// unused [20:24]
_unused20: u4 = 0,
_unused24: u1 = 0,
/// INTEP_DIR [25:25]
/// Direction of the interrupt endpoint. In=0, Out=1
INTEP_DIR: u1 = 0,
/// INTEP_PREAMBLE [26:26]
/// Interrupt EP requires preamble (is a low speed device on a full speed hub)
INTEP_PREAMBLE: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// Interrupt endpoint 9. Only valid for HOST mode.
pub const ADDR_ENDP9 = Register(ADDR_ENDP9_val).init(base_address + 0x24);
/// ADDR_ENDP8
const ADDR_ENDP8_val = packed struct {
/// ADDRESS [0:6]
/// Device address
ADDRESS: u7 = 0,
/// unused [7:15]
_unused7: u1 = 0,
_unused8: u8 = 0,
/// ENDPOINT [16:19]
/// Endpoint number of the interrupt endpoint
ENDPOINT: u4 = 0,
/// unused [20:24]
_unused20: u4 = 0,
_unused24: u1 = 0,
/// INTEP_DIR [25:25]
/// Direction of the interrupt endpoint. In=0, Out=1
INTEP_DIR: u1 = 0,
/// INTEP_PREAMBLE [26:26]
/// Interrupt EP requires preamble (is a low speed device on a full speed hub)
INTEP_PREAMBLE: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// Interrupt endpoint 8. Only valid for HOST mode.
pub const ADDR_ENDP8 = Register(ADDR_ENDP8_val).init(base_address + 0x20);
/// ADDR_ENDP7
const ADDR_ENDP7_val = packed struct {
/// ADDRESS [0:6]
/// Device address
ADDRESS: u7 = 0,
/// unused [7:15]
_unused7: u1 = 0,
_unused8: u8 = 0,
/// ENDPOINT [16:19]
/// Endpoint number of the interrupt endpoint
ENDPOINT: u4 = 0,
/// unused [20:24]
_unused20: u4 = 0,
_unused24: u1 = 0,
/// INTEP_DIR [25:25]
/// Direction of the interrupt endpoint. In=0, Out=1
INTEP_DIR: u1 = 0,
/// INTEP_PREAMBLE [26:26]
/// Interrupt EP requires preamble (is a low speed device on a full speed hub)
INTEP_PREAMBLE: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// Interrupt endpoint 7. Only valid for HOST mode.
pub const ADDR_ENDP7 = Register(ADDR_ENDP7_val).init(base_address + 0x1c);
/// ADDR_ENDP6
const ADDR_ENDP6_val = packed struct {
/// ADDRESS [0:6]
/// Device address
ADDRESS: u7 = 0,
/// unused [7:15]
_unused7: u1 = 0,
_unused8: u8 = 0,
/// ENDPOINT [16:19]
/// Endpoint number of the interrupt endpoint
ENDPOINT: u4 = 0,
/// unused [20:24]
_unused20: u4 = 0,
_unused24: u1 = 0,
/// INTEP_DIR [25:25]
/// Direction of the interrupt endpoint. In=0, Out=1
INTEP_DIR: u1 = 0,
/// INTEP_PREAMBLE [26:26]
/// Interrupt EP requires preamble (is a low speed device on a full speed hub)
INTEP_PREAMBLE: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// Interrupt endpoint 6. Only valid for HOST mode.
pub const ADDR_ENDP6 = Register(ADDR_ENDP6_val).init(base_address + 0x18);
/// ADDR_ENDP5
const ADDR_ENDP5_val = packed struct {
/// ADDRESS [0:6]
/// Device address
ADDRESS: u7 = 0,
/// unused [7:15]
_unused7: u1 = 0,
_unused8: u8 = 0,
/// ENDPOINT [16:19]
/// Endpoint number of the interrupt endpoint
ENDPOINT: u4 = 0,
/// unused [20:24]
_unused20: u4 = 0,
_unused24: u1 = 0,
/// INTEP_DIR [25:25]
/// Direction of the interrupt endpoint. In=0, Out=1
INTEP_DIR: u1 = 0,
/// INTEP_PREAMBLE [26:26]
/// Interrupt EP requires preamble (is a low speed device on a full speed hub)
INTEP_PREAMBLE: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// Interrupt endpoint 5. Only valid for HOST mode.
pub const ADDR_ENDP5 = Register(ADDR_ENDP5_val).init(base_address + 0x14);
/// ADDR_ENDP4
const ADDR_ENDP4_val = packed struct {
/// ADDRESS [0:6]
/// Device address
ADDRESS: u7 = 0,
/// unused [7:15]
_unused7: u1 = 0,
_unused8: u8 = 0,
/// ENDPOINT [16:19]
/// Endpoint number of the interrupt endpoint
ENDPOINT: u4 = 0,
/// unused [20:24]
_unused20: u4 = 0,
_unused24: u1 = 0,
/// INTEP_DIR [25:25]
/// Direction of the interrupt endpoint. In=0, Out=1
INTEP_DIR: u1 = 0,
/// INTEP_PREAMBLE [26:26]
/// Interrupt EP requires preamble (is a low speed device on a full speed hub)
INTEP_PREAMBLE: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// Interrupt endpoint 4. Only valid for HOST mode.
pub const ADDR_ENDP4 = Register(ADDR_ENDP4_val).init(base_address + 0x10);
/// ADDR_ENDP3
const ADDR_ENDP3_val = packed struct {
/// ADDRESS [0:6]
/// Device address
ADDRESS: u7 = 0,
/// unused [7:15]
_unused7: u1 = 0,
_unused8: u8 = 0,
/// ENDPOINT [16:19]
/// Endpoint number of the interrupt endpoint
ENDPOINT: u4 = 0,
/// unused [20:24]
_unused20: u4 = 0,
_unused24: u1 = 0,
/// INTEP_DIR [25:25]
/// Direction of the interrupt endpoint. In=0, Out=1
INTEP_DIR: u1 = 0,
/// INTEP_PREAMBLE [26:26]
/// Interrupt EP requires preamble (is a low speed device on a full speed hub)
INTEP_PREAMBLE: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// Interrupt endpoint 3. Only valid for HOST mode.
pub const ADDR_ENDP3 = Register(ADDR_ENDP3_val).init(base_address + 0xc);
/// ADDR_ENDP2
const ADDR_ENDP2_val = packed struct {
/// ADDRESS [0:6]
/// Device address
ADDRESS: u7 = 0,
/// unused [7:15]
_unused7: u1 = 0,
_unused8: u8 = 0,
/// ENDPOINT [16:19]
/// Endpoint number of the interrupt endpoint
ENDPOINT: u4 = 0,
/// unused [20:24]
_unused20: u4 = 0,
_unused24: u1 = 0,
/// INTEP_DIR [25:25]
/// Direction of the interrupt endpoint. In=0, Out=1
INTEP_DIR: u1 = 0,
/// INTEP_PREAMBLE [26:26]
/// Interrupt EP requires preamble (is a low speed device on a full speed hub)
INTEP_PREAMBLE: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// Interrupt endpoint 2. Only valid for HOST mode.
pub const ADDR_ENDP2 = Register(ADDR_ENDP2_val).init(base_address + 0x8);
/// ADDR_ENDP1
const ADDR_ENDP1_val = packed struct {
/// ADDRESS [0:6]
/// Device address
ADDRESS: u7 = 0,
/// unused [7:15]
_unused7: u1 = 0,
_unused8: u8 = 0,
/// ENDPOINT [16:19]
/// Endpoint number of the interrupt endpoint
ENDPOINT: u4 = 0,
/// unused [20:24]
_unused20: u4 = 0,
_unused24: u1 = 0,
/// INTEP_DIR [25:25]
/// Direction of the interrupt endpoint. In=0, Out=1
INTEP_DIR: u1 = 0,
/// INTEP_PREAMBLE [26:26]
/// Interrupt EP requires preamble (is a low speed device on a full speed hub)
INTEP_PREAMBLE: u1 = 0,
/// unused [27:31]
_unused27: u5 = 0,
};
/// Interrupt endpoint 1. Only valid for HOST mode.
pub const ADDR_ENDP1 = Register(ADDR_ENDP1_val).init(base_address + 0x4);
/// ADDR_ENDP
const ADDR_ENDP_val = packed struct {
/// ADDRESS [0:6]
/// In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with.
ADDRESS: u7 = 0,
/// unused [7:15]
_unused7: u1 = 0,
_unused8: u8 = 0,
/// ENDPOINT [16:19]
/// Device endpoint to send data to. Only valid for HOST mode.
ENDPOINT: u4 = 0,
/// unused [20:31]
_unused20: u4 = 0,
_unused24: u8 = 0,
};
/// Device address and endpoint control
pub const ADDR_ENDP = Register(ADDR_ENDP_val).init(base_address + 0x0);
};
/// Programmable IO block
pub const PIO0 = struct {
const base_address = 0x50200000;
/// IRQ1_INTS
const IRQ1_INTS_val = packed struct {
/// SM0_RXNEMPTY [0:0]
/// No description
SM0_RXNEMPTY: u1 = 0,
/// SM1_RXNEMPTY [1:1]
/// No description
SM1_RXNEMPTY: u1 = 0,
/// SM2_RXNEMPTY [2:2]
/// No description
SM2_RXNEMPTY: u1 = 0,
/// SM3_RXNEMPTY [3:3]
/// No description
SM3_RXNEMPTY: u1 = 0,
/// SM0_TXNFULL [4:4]
/// No description
SM0_TXNFULL: u1 = 0,
/// SM1_TXNFULL [5:5]
/// No description
SM1_TXNFULL: u1 = 0,
/// SM2_TXNFULL [6:6]
/// No description
SM2_TXNFULL: u1 = 0,
/// SM3_TXNFULL [7:7]
/// No description
SM3_TXNFULL: u1 = 0,
/// SM0 [8:8]
/// No description
SM0: u1 = 0,
/// SM1 [9:9]
/// No description
SM1: u1 = 0,
/// SM2 [10:10]
/// No description
SM2: u1 = 0,
/// SM3 [11:11]
/// No description
SM3: u1 = 0,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt status after masking & forcing for irq1
pub const IRQ1_INTS = Register(IRQ1_INTS_val).init(base_address + 0x140);
/// IRQ1_INTF
const IRQ1_INTF_val = packed struct {
/// SM0_RXNEMPTY [0:0]
/// No description
SM0_RXNEMPTY: u1 = 0,
/// SM1_RXNEMPTY [1:1]
/// No description
SM1_RXNEMPTY: u1 = 0,
/// SM2_RXNEMPTY [2:2]
/// No description
SM2_RXNEMPTY: u1 = 0,
/// SM3_RXNEMPTY [3:3]
/// No description
SM3_RXNEMPTY: u1 = 0,
/// SM0_TXNFULL [4:4]
/// No description
SM0_TXNFULL: u1 = 0,
/// SM1_TXNFULL [5:5]
/// No description
SM1_TXNFULL: u1 = 0,
/// SM2_TXNFULL [6:6]
/// No description
SM2_TXNFULL: u1 = 0,
/// SM3_TXNFULL [7:7]
/// No description
SM3_TXNFULL: u1 = 0,
/// SM0 [8:8]
/// No description
SM0: u1 = 0,
/// SM1 [9:9]
/// No description
SM1: u1 = 0,
/// SM2 [10:10]
/// No description
SM2: u1 = 0,
/// SM3 [11:11]
/// No description
SM3: u1 = 0,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt Force for irq1
pub const IRQ1_INTF = Register(IRQ1_INTF_val).init(base_address + 0x13c);
/// IRQ1_INTE
const IRQ1_INTE_val = packed struct {
/// SM0_RXNEMPTY [0:0]
/// No description
SM0_RXNEMPTY: u1 = 0,
/// SM1_RXNEMPTY [1:1]
/// No description
SM1_RXNEMPTY: u1 = 0,
/// SM2_RXNEMPTY [2:2]
/// No description
SM2_RXNEMPTY: u1 = 0,
/// SM3_RXNEMPTY [3:3]
/// No description
SM3_RXNEMPTY: u1 = 0,
/// SM0_TXNFULL [4:4]
/// No description
SM0_TXNFULL: u1 = 0,
/// SM1_TXNFULL [5:5]
/// No description
SM1_TXNFULL: u1 = 0,
/// SM2_TXNFULL [6:6]
/// No description
SM2_TXNFULL: u1 = 0,
/// SM3_TXNFULL [7:7]
/// No description
SM3_TXNFULL: u1 = 0,
/// SM0 [8:8]
/// No description
SM0: u1 = 0,
/// SM1 [9:9]
/// No description
SM1: u1 = 0,
/// SM2 [10:10]
/// No description
SM2: u1 = 0,
/// SM3 [11:11]
/// No description
SM3: u1 = 0,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt Enable for irq1
pub const IRQ1_INTE = Register(IRQ1_INTE_val).init(base_address + 0x138);
/// IRQ0_INTS
const IRQ0_INTS_val = packed struct {
/// SM0_RXNEMPTY [0:0]
/// No description
SM0_RXNEMPTY: u1 = 0,
/// SM1_RXNEMPTY [1:1]
/// No description
SM1_RXNEMPTY: u1 = 0,
/// SM2_RXNEMPTY [2:2]
/// No description
SM2_RXNEMPTY: u1 = 0,
/// SM3_RXNEMPTY [3:3]
/// No description
SM3_RXNEMPTY: u1 = 0,
/// SM0_TXNFULL [4:4]
/// No description
SM0_TXNFULL: u1 = 0,
/// SM1_TXNFULL [5:5]
/// No description
SM1_TXNFULL: u1 = 0,
/// SM2_TXNFULL [6:6]
/// No description
SM2_TXNFULL: u1 = 0,
/// SM3_TXNFULL [7:7]
/// No description
SM3_TXNFULL: u1 = 0,
/// SM0 [8:8]
/// No description
SM0: u1 = 0,
/// SM1 [9:9]
/// No description
SM1: u1 = 0,
/// SM2 [10:10]
/// No description
SM2: u1 = 0,
/// SM3 [11:11]
/// No description
SM3: u1 = 0,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt status after masking & forcing for irq0
pub const IRQ0_INTS = Register(IRQ0_INTS_val).init(base_address + 0x134);
/// IRQ0_INTF
const IRQ0_INTF_val = packed struct {
/// SM0_RXNEMPTY [0:0]
/// No description
SM0_RXNEMPTY: u1 = 0,
/// SM1_RXNEMPTY [1:1]
/// No description
SM1_RXNEMPTY: u1 = 0,
/// SM2_RXNEMPTY [2:2]
/// No description
SM2_RXNEMPTY: u1 = 0,
/// SM3_RXNEMPTY [3:3]
/// No description
SM3_RXNEMPTY: u1 = 0,
/// SM0_TXNFULL [4:4]
/// No description
SM0_TXNFULL: u1 = 0,
/// SM1_TXNFULL [5:5]
/// No description
SM1_TXNFULL: u1 = 0,
/// SM2_TXNFULL [6:6]
/// No description
SM2_TXNFULL: u1 = 0,
/// SM3_TXNFULL [7:7]
/// No description
SM3_TXNFULL: u1 = 0,
/// SM0 [8:8]
/// No description
SM0: u1 = 0,
/// SM1 [9:9]
/// No description
SM1: u1 = 0,
/// SM2 [10:10]
/// No description
SM2: u1 = 0,
/// SM3 [11:11]
/// No description
SM3: u1 = 0,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt Force for irq0
pub const IRQ0_INTF = Register(IRQ0_INTF_val).init(base_address + 0x130);
/// IRQ0_INTE
const IRQ0_INTE_val = packed struct {
/// SM0_RXNEMPTY [0:0]
/// No description
SM0_RXNEMPTY: u1 = 0,
/// SM1_RXNEMPTY [1:1]
/// No description
SM1_RXNEMPTY: u1 = 0,
/// SM2_RXNEMPTY [2:2]
/// No description
SM2_RXNEMPTY: u1 = 0,
/// SM3_RXNEMPTY [3:3]
/// No description
SM3_RXNEMPTY: u1 = 0,
/// SM0_TXNFULL [4:4]
/// No description
SM0_TXNFULL: u1 = 0,
/// SM1_TXNFULL [5:5]
/// No description
SM1_TXNFULL: u1 = 0,
/// SM2_TXNFULL [6:6]
/// No description
SM2_TXNFULL: u1 = 0,
/// SM3_TXNFULL [7:7]
/// No description
SM3_TXNFULL: u1 = 0,
/// SM0 [8:8]
/// No description
SM0: u1 = 0,
/// SM1 [9:9]
/// No description
SM1: u1 = 0,
/// SM2 [10:10]
/// No description
SM2: u1 = 0,
/// SM3 [11:11]
/// No description
SM3: u1 = 0,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt Enable for irq0
pub const IRQ0_INTE = Register(IRQ0_INTE_val).init(base_address + 0x12c);
/// INTR
const INTR_val = packed struct {
/// SM0_RXNEMPTY [0:0]
/// No description
SM0_RXNEMPTY: u1 = 0,
/// SM1_RXNEMPTY [1:1]
/// No description
SM1_RXNEMPTY: u1 = 0,
/// SM2_RXNEMPTY [2:2]
/// No description
SM2_RXNEMPTY: u1 = 0,
/// SM3_RXNEMPTY [3:3]
/// No description
SM3_RXNEMPTY: u1 = 0,
/// SM0_TXNFULL [4:4]
/// No description
SM0_TXNFULL: u1 = 0,
/// SM1_TXNFULL [5:5]
/// No description
SM1_TXNFULL: u1 = 0,
/// SM2_TXNFULL [6:6]
/// No description
SM2_TXNFULL: u1 = 0,
/// SM3_TXNFULL [7:7]
/// No description
SM3_TXNFULL: u1 = 0,
/// SM0 [8:8]
/// No description
SM0: u1 = 0,
/// SM1 [9:9]
/// No description
SM1: u1 = 0,
/// SM2 [10:10]
/// No description
SM2: u1 = 0,
/// SM3 [11:11]
/// No description
SM3: u1 = 0,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Raw Interrupts
pub const INTR = Register(INTR_val).init(base_address + 0x128);
/// SM3_PINCTRL
const SM3_PINCTRL_val = packed struct {
/// OUT_BASE [0:4]
/// The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.
OUT_BASE: u5 = 0,
/// SET_BASE [5:9]
/// The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.
SET_BASE: u5 = 0,
/// SIDESET_BASE [10:14]
/// The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.
SIDESET_BASE: u5 = 0,
/// IN_BASE [15:19]
/// The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.
IN_BASE: u5 = 0,
/// OUT_COUNT [20:25]
/// The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.
OUT_COUNT: u6 = 0,
/// SET_COUNT [26:28]
/// The number of pins asserted by a SET. In the range 0 to 5 inclusive.
SET_COUNT: u3 = 5,
/// SIDESET_COUNT [29:31]
/// The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).
SIDESET_COUNT: u3 = 0,
};
/// State machine pin control
pub const SM3_PINCTRL = Register(SM3_PINCTRL_val).init(base_address + 0x124);
/// SM3_INSTR
const SM3_INSTR_val = packed struct {
/// SM3_INSTR [0:15]
/// No description
SM3_INSTR: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Read to see the instruction currently addressed by state machine 3's program counter\n
pub const SM3_INSTR = Register(SM3_INSTR_val).init(base_address + 0x120);
/// SM3_ADDR
const SM3_ADDR_val = packed struct {
/// SM3_ADDR [0:4]
/// No description
SM3_ADDR: u5 = 0,
/// unused [5:31]
_unused5: u3 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Current instruction address of state machine 3
pub const SM3_ADDR = Register(SM3_ADDR_val).init(base_address + 0x11c);
/// SM3_SHIFTCTRL
const SM3_SHIFTCTRL_val = packed struct {
/// unused [0:15]
_unused0: u8 = 0,
_unused8: u8 = 0,
/// AUTOPUSH [16:16]
/// Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.
AUTOPUSH: u1 = 0,
/// AUTOPULL [17:17]
/// Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.
AUTOPULL: u1 = 0,
/// IN_SHIFTDIR [18:18]
/// 1 = shift input shift register to right (data enters from left). 0 = to left.
IN_SHIFTDIR: u1 = 1,
/// OUT_SHIFTDIR [19:19]
/// 1 = shift out of output shift register to right. 0 = to left.
OUT_SHIFTDIR: u1 = 1,
/// PUSH_THRESH [20:24]
/// Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n
PUSH_THRESH: u5 = 0,
/// PULL_THRESH [25:29]
/// Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n
PULL_THRESH: u5 = 0,
/// FJOIN_TX [30:30]
/// When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n
FJOIN_TX: u1 = 0,
/// FJOIN_RX [31:31]
/// When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n
FJOIN_RX: u1 = 0,
};
/// Control behaviour of the input/output shift registers for state machine 3
pub const SM3_SHIFTCTRL = Register(SM3_SHIFTCTRL_val).init(base_address + 0x118);
/// SM3_EXECCTRL
const SM3_EXECCTRL_val = packed struct {
/// STATUS_N [0:3]
/// Comparison level for the MOV x, STATUS instruction
STATUS_N: u4 = 0,
/// STATUS_SEL [4:4]
/// Comparison used for the MOV x, STATUS instruction.
STATUS_SEL: u1 = 0,
/// unused [5:6]
_unused5: u2 = 0,
/// WRAP_BOTTOM [7:11]
/// After reaching wrap_top, execution is wrapped to this address.
WRAP_BOTTOM: u5 = 0,
/// WRAP_TOP [12:16]
/// After reaching this address, execution is wrapped to wrap_bottom.\n
WRAP_TOP: u5 = 31,
/// OUT_STICKY [17:17]
/// Continuously assert the most recent OUT/SET to the pins
OUT_STICKY: u1 = 0,
/// INLINE_OUT_EN [18:18]
/// If 1, use a bit of OUT data as an auxiliary write enable\n
INLINE_OUT_EN: u1 = 0,
/// OUT_EN_SEL [19:23]
/// Which data bit to use for inline OUT enable
OUT_EN_SEL: u5 = 0,
/// JMP_PIN [24:28]
/// The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.
JMP_PIN: u5 = 0,
/// SIDE_PINDIR [29:29]
/// If 1, side-set data is asserted to pin directions, instead of pin values
SIDE_PINDIR: u1 = 0,
/// SIDE_EN [30:30]
/// If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
SIDE_EN: u1 = 0,
/// EXEC_STALLED [31:31]
/// If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.
EXEC_STALLED: u1 = 0,
};
/// Execution/behavioural settings for state machine 3
pub const SM3_EXECCTRL = Register(SM3_EXECCTRL_val).init(base_address + 0x114);
/// SM3_CLKDIV
const SM3_CLKDIV_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// FRAC [8:15]
/// Fractional part of clock divisor
FRAC: u8 = 0,
/// INT [16:31]
/// Effective frequency is sysclk/(int + frac/256).\n
INT: u16 = 1,
};
/// Clock divisor register for state machine 3\n
pub const SM3_CLKDIV = Register(SM3_CLKDIV_val).init(base_address + 0x110);
/// SM2_PINCTRL
const SM2_PINCTRL_val = packed struct {
/// OUT_BASE [0:4]
/// The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.
OUT_BASE: u5 = 0,
/// SET_BASE [5:9]
/// The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.
SET_BASE: u5 = 0,
/// SIDESET_BASE [10:14]
/// The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.
SIDESET_BASE: u5 = 0,
/// IN_BASE [15:19]
/// The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.
IN_BASE: u5 = 0,
/// OUT_COUNT [20:25]
/// The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.
OUT_COUNT: u6 = 0,
/// SET_COUNT [26:28]
/// The number of pins asserted by a SET. In the range 0 to 5 inclusive.
SET_COUNT: u3 = 5,
/// SIDESET_COUNT [29:31]
/// The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).
SIDESET_COUNT: u3 = 0,
};
/// State machine pin control
pub const SM2_PINCTRL = Register(SM2_PINCTRL_val).init(base_address + 0x10c);
/// SM2_INSTR
const SM2_INSTR_val = packed struct {
/// SM2_INSTR [0:15]
/// No description
SM2_INSTR: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Read to see the instruction currently addressed by state machine 2's program counter\n
pub const SM2_INSTR = Register(SM2_INSTR_val).init(base_address + 0x108);
/// SM2_ADDR
const SM2_ADDR_val = packed struct {
/// SM2_ADDR [0:4]
/// No description
SM2_ADDR: u5 = 0,
/// unused [5:31]
_unused5: u3 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Current instruction address of state machine 2
pub const SM2_ADDR = Register(SM2_ADDR_val).init(base_address + 0x104);
/// SM2_SHIFTCTRL
const SM2_SHIFTCTRL_val = packed struct {
/// unused [0:15]
_unused0: u8 = 0,
_unused8: u8 = 0,
/// AUTOPUSH [16:16]
/// Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.
AUTOPUSH: u1 = 0,
/// AUTOPULL [17:17]
/// Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.
AUTOPULL: u1 = 0,
/// IN_SHIFTDIR [18:18]
/// 1 = shift input shift register to right (data enters from left). 0 = to left.
IN_SHIFTDIR: u1 = 1,
/// OUT_SHIFTDIR [19:19]
/// 1 = shift out of output shift register to right. 0 = to left.
OUT_SHIFTDIR: u1 = 1,
/// PUSH_THRESH [20:24]
/// Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n
PUSH_THRESH: u5 = 0,
/// PULL_THRESH [25:29]
/// Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n
PULL_THRESH: u5 = 0,
/// FJOIN_TX [30:30]
/// When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n
FJOIN_TX: u1 = 0,
/// FJOIN_RX [31:31]
/// When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n
FJOIN_RX: u1 = 0,
};
/// Control behaviour of the input/output shift registers for state machine 2
pub const SM2_SHIFTCTRL = Register(SM2_SHIFTCTRL_val).init(base_address + 0x100);
/// SM2_EXECCTRL
const SM2_EXECCTRL_val = packed struct {
/// STATUS_N [0:3]
/// Comparison level for the MOV x, STATUS instruction
STATUS_N: u4 = 0,
/// STATUS_SEL [4:4]
/// Comparison used for the MOV x, STATUS instruction.
STATUS_SEL: u1 = 0,
/// unused [5:6]
_unused5: u2 = 0,
/// WRAP_BOTTOM [7:11]
/// After reaching wrap_top, execution is wrapped to this address.
WRAP_BOTTOM: u5 = 0,
/// WRAP_TOP [12:16]
/// After reaching this address, execution is wrapped to wrap_bottom.\n
WRAP_TOP: u5 = 31,
/// OUT_STICKY [17:17]
/// Continuously assert the most recent OUT/SET to the pins
OUT_STICKY: u1 = 0,
/// INLINE_OUT_EN [18:18]
/// If 1, use a bit of OUT data as an auxiliary write enable\n
INLINE_OUT_EN: u1 = 0,
/// OUT_EN_SEL [19:23]
/// Which data bit to use for inline OUT enable
OUT_EN_SEL: u5 = 0,
/// JMP_PIN [24:28]
/// The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.
JMP_PIN: u5 = 0,
/// SIDE_PINDIR [29:29]
/// If 1, side-set data is asserted to pin directions, instead of pin values
SIDE_PINDIR: u1 = 0,
/// SIDE_EN [30:30]
/// If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
SIDE_EN: u1 = 0,
/// EXEC_STALLED [31:31]
/// If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.
EXEC_STALLED: u1 = 0,
};
/// Execution/behavioural settings for state machine 2
pub const SM2_EXECCTRL = Register(SM2_EXECCTRL_val).init(base_address + 0xfc);
/// SM2_CLKDIV
const SM2_CLKDIV_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// FRAC [8:15]
/// Fractional part of clock divisor
FRAC: u8 = 0,
/// INT [16:31]
/// Effective frequency is sysclk/(int + frac/256).\n
INT: u16 = 1,
};
/// Clock divisor register for state machine 2\n
pub const SM2_CLKDIV = Register(SM2_CLKDIV_val).init(base_address + 0xf8);
/// SM1_PINCTRL
const SM1_PINCTRL_val = packed struct {
/// OUT_BASE [0:4]
/// The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.
OUT_BASE: u5 = 0,
/// SET_BASE [5:9]
/// The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.
SET_BASE: u5 = 0,
/// SIDESET_BASE [10:14]
/// The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.
SIDESET_BASE: u5 = 0,
/// IN_BASE [15:19]
/// The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.
IN_BASE: u5 = 0,
/// OUT_COUNT [20:25]
/// The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.
OUT_COUNT: u6 = 0,
/// SET_COUNT [26:28]
/// The number of pins asserted by a SET. In the range 0 to 5 inclusive.
SET_COUNT: u3 = 5,
/// SIDESET_COUNT [29:31]
/// The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).
SIDESET_COUNT: u3 = 0,
};
/// State machine pin control
pub const SM1_PINCTRL = Register(SM1_PINCTRL_val).init(base_address + 0xf4);
/// SM1_INSTR
const SM1_INSTR_val = packed struct {
/// SM1_INSTR [0:15]
/// No description
SM1_INSTR: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Read to see the instruction currently addressed by state machine 1's program counter\n
pub const SM1_INSTR = Register(SM1_INSTR_val).init(base_address + 0xf0);
/// SM1_ADDR
const SM1_ADDR_val = packed struct {
/// SM1_ADDR [0:4]
/// No description
SM1_ADDR: u5 = 0,
/// unused [5:31]
_unused5: u3 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Current instruction address of state machine 1
pub const SM1_ADDR = Register(SM1_ADDR_val).init(base_address + 0xec);
/// SM1_SHIFTCTRL
const SM1_SHIFTCTRL_val = packed struct {
/// unused [0:15]
_unused0: u8 = 0,
_unused8: u8 = 0,
/// AUTOPUSH [16:16]
/// Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.
AUTOPUSH: u1 = 0,
/// AUTOPULL [17:17]
/// Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.
AUTOPULL: u1 = 0,
/// IN_SHIFTDIR [18:18]
/// 1 = shift input shift register to right (data enters from left). 0 = to left.
IN_SHIFTDIR: u1 = 1,
/// OUT_SHIFTDIR [19:19]
/// 1 = shift out of output shift register to right. 0 = to left.
OUT_SHIFTDIR: u1 = 1,
/// PUSH_THRESH [20:24]
/// Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n
PUSH_THRESH: u5 = 0,
/// PULL_THRESH [25:29]
/// Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n
PULL_THRESH: u5 = 0,
/// FJOIN_TX [30:30]
/// When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n
FJOIN_TX: u1 = 0,
/// FJOIN_RX [31:31]
/// When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n
FJOIN_RX: u1 = 0,
};
/// Control behaviour of the input/output shift registers for state machine 1
pub const SM1_SHIFTCTRL = Register(SM1_SHIFTCTRL_val).init(base_address + 0xe8);
/// SM1_EXECCTRL
const SM1_EXECCTRL_val = packed struct {
/// STATUS_N [0:3]
/// Comparison level for the MOV x, STATUS instruction
STATUS_N: u4 = 0,
/// STATUS_SEL [4:4]
/// Comparison used for the MOV x, STATUS instruction.
STATUS_SEL: u1 = 0,
/// unused [5:6]
_unused5: u2 = 0,
/// WRAP_BOTTOM [7:11]
/// After reaching wrap_top, execution is wrapped to this address.
WRAP_BOTTOM: u5 = 0,
/// WRAP_TOP [12:16]
/// After reaching this address, execution is wrapped to wrap_bottom.\n
WRAP_TOP: u5 = 31,
/// OUT_STICKY [17:17]
/// Continuously assert the most recent OUT/SET to the pins
OUT_STICKY: u1 = 0,
/// INLINE_OUT_EN [18:18]
/// If 1, use a bit of OUT data as an auxiliary write enable\n
INLINE_OUT_EN: u1 = 0,
/// OUT_EN_SEL [19:23]
/// Which data bit to use for inline OUT enable
OUT_EN_SEL: u5 = 0,
/// JMP_PIN [24:28]
/// The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.
JMP_PIN: u5 = 0,
/// SIDE_PINDIR [29:29]
/// If 1, side-set data is asserted to pin directions, instead of pin values
SIDE_PINDIR: u1 = 0,
/// SIDE_EN [30:30]
/// If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
SIDE_EN: u1 = 0,
/// EXEC_STALLED [31:31]
/// If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.
EXEC_STALLED: u1 = 0,
};
/// Execution/behavioural settings for state machine 1
pub const SM1_EXECCTRL = Register(SM1_EXECCTRL_val).init(base_address + 0xe4);
/// SM1_CLKDIV
const SM1_CLKDIV_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// FRAC [8:15]
/// Fractional part of clock divisor
FRAC: u8 = 0,
/// INT [16:31]
/// Effective frequency is sysclk/(int + frac/256).\n
INT: u16 = 1,
};
/// Clock divisor register for state machine 1\n
pub const SM1_CLKDIV = Register(SM1_CLKDIV_val).init(base_address + 0xe0);
/// SM0_PINCTRL
const SM0_PINCTRL_val = packed struct {
/// OUT_BASE [0:4]
/// The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.
OUT_BASE: u5 = 0,
/// SET_BASE [5:9]
/// The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.
SET_BASE: u5 = 0,
/// SIDESET_BASE [10:14]
/// The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.
SIDESET_BASE: u5 = 0,
/// IN_BASE [15:19]
/// The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.
IN_BASE: u5 = 0,
/// OUT_COUNT [20:25]
/// The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.
OUT_COUNT: u6 = 0,
/// SET_COUNT [26:28]
/// The number of pins asserted by a SET. In the range 0 to 5 inclusive.
SET_COUNT: u3 = 5,
/// SIDESET_COUNT [29:31]
/// The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).
SIDESET_COUNT: u3 = 0,
};
/// State machine pin control
pub const SM0_PINCTRL = Register(SM0_PINCTRL_val).init(base_address + 0xdc);
/// SM0_INSTR
const SM0_INSTR_val = packed struct {
/// SM0_INSTR [0:15]
/// No description
SM0_INSTR: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Read to see the instruction currently addressed by state machine 0's program counter\n
pub const SM0_INSTR = Register(SM0_INSTR_val).init(base_address + 0xd8);
/// SM0_ADDR
const SM0_ADDR_val = packed struct {
/// SM0_ADDR [0:4]
/// No description
SM0_ADDR: u5 = 0,
/// unused [5:31]
_unused5: u3 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Current instruction address of state machine 0
pub const SM0_ADDR = Register(SM0_ADDR_val).init(base_address + 0xd4);
/// SM0_SHIFTCTRL
const SM0_SHIFTCTRL_val = packed struct {
/// unused [0:15]
_unused0: u8 = 0,
_unused8: u8 = 0,
/// AUTOPUSH [16:16]
/// Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.
AUTOPUSH: u1 = 0,
/// AUTOPULL [17:17]
/// Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.
AUTOPULL: u1 = 0,
/// IN_SHIFTDIR [18:18]
/// 1 = shift input shift register to right (data enters from left). 0 = to left.
IN_SHIFTDIR: u1 = 1,
/// OUT_SHIFTDIR [19:19]
/// 1 = shift out of output shift register to right. 0 = to left.
OUT_SHIFTDIR: u1 = 1,
/// PUSH_THRESH [20:24]
/// Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n
PUSH_THRESH: u5 = 0,
/// PULL_THRESH [25:29]
/// Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n
PULL_THRESH: u5 = 0,
/// FJOIN_TX [30:30]
/// When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n
FJOIN_TX: u1 = 0,
/// FJOIN_RX [31:31]
/// When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n
FJOIN_RX: u1 = 0,
};
/// Control behaviour of the input/output shift registers for state machine 0
pub const SM0_SHIFTCTRL = Register(SM0_SHIFTCTRL_val).init(base_address + 0xd0);
/// SM0_EXECCTRL
const SM0_EXECCTRL_val = packed struct {
/// STATUS_N [0:3]
/// Comparison level for the MOV x, STATUS instruction
STATUS_N: u4 = 0,
/// STATUS_SEL [4:4]
/// Comparison used for the MOV x, STATUS instruction.
STATUS_SEL: u1 = 0,
/// unused [5:6]
_unused5: u2 = 0,
/// WRAP_BOTTOM [7:11]
/// After reaching wrap_top, execution is wrapped to this address.
WRAP_BOTTOM: u5 = 0,
/// WRAP_TOP [12:16]
/// After reaching this address, execution is wrapped to wrap_bottom.\n
WRAP_TOP: u5 = 31,
/// OUT_STICKY [17:17]
/// Continuously assert the most recent OUT/SET to the pins
OUT_STICKY: u1 = 0,
/// INLINE_OUT_EN [18:18]
/// If 1, use a bit of OUT data as an auxiliary write enable\n
INLINE_OUT_EN: u1 = 0,
/// OUT_EN_SEL [19:23]
/// Which data bit to use for inline OUT enable
OUT_EN_SEL: u5 = 0,
/// JMP_PIN [24:28]
/// The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.
JMP_PIN: u5 = 0,
/// SIDE_PINDIR [29:29]
/// If 1, side-set data is asserted to pin directions, instead of pin values
SIDE_PINDIR: u1 = 0,
/// SIDE_EN [30:30]
/// If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
SIDE_EN: u1 = 0,
/// EXEC_STALLED [31:31]
/// If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.
EXEC_STALLED: u1 = 0,
};
/// Execution/behavioural settings for state machine 0
pub const SM0_EXECCTRL = Register(SM0_EXECCTRL_val).init(base_address + 0xcc);
/// SM0_CLKDIV
const SM0_CLKDIV_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// FRAC [8:15]
/// Fractional part of clock divisor
FRAC: u8 = 0,
/// INT [16:31]
/// Effective frequency is sysclk/(int + frac/256).\n
INT: u16 = 1,
};
/// Clock divisor register for state machine 0\n
pub const SM0_CLKDIV = Register(SM0_CLKDIV_val).init(base_address + 0xc8);
/// INSTR_MEM31
const INSTR_MEM31_val = packed struct {
/// INSTR_MEM31 [0:15]
/// No description
INSTR_MEM31: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 31
pub const INSTR_MEM31 = Register(INSTR_MEM31_val).init(base_address + 0xc4);
/// INSTR_MEM30
const INSTR_MEM30_val = packed struct {
/// INSTR_MEM30 [0:15]
/// No description
INSTR_MEM30: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 30
pub const INSTR_MEM30 = Register(INSTR_MEM30_val).init(base_address + 0xc0);
/// INSTR_MEM29
const INSTR_MEM29_val = packed struct {
/// INSTR_MEM29 [0:15]
/// No description
INSTR_MEM29: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 29
pub const INSTR_MEM29 = Register(INSTR_MEM29_val).init(base_address + 0xbc);
/// INSTR_MEM28
const INSTR_MEM28_val = packed struct {
/// INSTR_MEM28 [0:15]
/// No description
INSTR_MEM28: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 28
pub const INSTR_MEM28 = Register(INSTR_MEM28_val).init(base_address + 0xb8);
/// INSTR_MEM27
const INSTR_MEM27_val = packed struct {
/// INSTR_MEM27 [0:15]
/// No description
INSTR_MEM27: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 27
pub const INSTR_MEM27 = Register(INSTR_MEM27_val).init(base_address + 0xb4);
/// INSTR_MEM26
const INSTR_MEM26_val = packed struct {
/// INSTR_MEM26 [0:15]
/// No description
INSTR_MEM26: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 26
pub const INSTR_MEM26 = Register(INSTR_MEM26_val).init(base_address + 0xb0);
/// INSTR_MEM25
const INSTR_MEM25_val = packed struct {
/// INSTR_MEM25 [0:15]
/// No description
INSTR_MEM25: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 25
pub const INSTR_MEM25 = Register(INSTR_MEM25_val).init(base_address + 0xac);
/// INSTR_MEM24
const INSTR_MEM24_val = packed struct {
/// INSTR_MEM24 [0:15]
/// No description
INSTR_MEM24: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 24
pub const INSTR_MEM24 = Register(INSTR_MEM24_val).init(base_address + 0xa8);
/// INSTR_MEM23
const INSTR_MEM23_val = packed struct {
/// INSTR_MEM23 [0:15]
/// No description
INSTR_MEM23: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 23
pub const INSTR_MEM23 = Register(INSTR_MEM23_val).init(base_address + 0xa4);
/// INSTR_MEM22
const INSTR_MEM22_val = packed struct {
/// INSTR_MEM22 [0:15]
/// No description
INSTR_MEM22: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 22
pub const INSTR_MEM22 = Register(INSTR_MEM22_val).init(base_address + 0xa0);
/// INSTR_MEM21
const INSTR_MEM21_val = packed struct {
/// INSTR_MEM21 [0:15]
/// No description
INSTR_MEM21: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 21
pub const INSTR_MEM21 = Register(INSTR_MEM21_val).init(base_address + 0x9c);
/// INSTR_MEM20
const INSTR_MEM20_val = packed struct {
/// INSTR_MEM20 [0:15]
/// No description
INSTR_MEM20: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 20
pub const INSTR_MEM20 = Register(INSTR_MEM20_val).init(base_address + 0x98);
/// INSTR_MEM19
const INSTR_MEM19_val = packed struct {
/// INSTR_MEM19 [0:15]
/// No description
INSTR_MEM19: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 19
pub const INSTR_MEM19 = Register(INSTR_MEM19_val).init(base_address + 0x94);
/// INSTR_MEM18
const INSTR_MEM18_val = packed struct {
/// INSTR_MEM18 [0:15]
/// No description
INSTR_MEM18: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 18
pub const INSTR_MEM18 = Register(INSTR_MEM18_val).init(base_address + 0x90);
/// INSTR_MEM17
const INSTR_MEM17_val = packed struct {
/// INSTR_MEM17 [0:15]
/// No description
INSTR_MEM17: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 17
pub const INSTR_MEM17 = Register(INSTR_MEM17_val).init(base_address + 0x8c);
/// INSTR_MEM16
const INSTR_MEM16_val = packed struct {
/// INSTR_MEM16 [0:15]
/// No description
INSTR_MEM16: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 16
pub const INSTR_MEM16 = Register(INSTR_MEM16_val).init(base_address + 0x88);
/// INSTR_MEM15
const INSTR_MEM15_val = packed struct {
/// INSTR_MEM15 [0:15]
/// No description
INSTR_MEM15: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 15
pub const INSTR_MEM15 = Register(INSTR_MEM15_val).init(base_address + 0x84);
/// INSTR_MEM14
const INSTR_MEM14_val = packed struct {
/// INSTR_MEM14 [0:15]
/// No description
INSTR_MEM14: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 14
pub const INSTR_MEM14 = Register(INSTR_MEM14_val).init(base_address + 0x80);
/// INSTR_MEM13
const INSTR_MEM13_val = packed struct {
/// INSTR_MEM13 [0:15]
/// No description
INSTR_MEM13: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 13
pub const INSTR_MEM13 = Register(INSTR_MEM13_val).init(base_address + 0x7c);
/// INSTR_MEM12
const INSTR_MEM12_val = packed struct {
/// INSTR_MEM12 [0:15]
/// No description
INSTR_MEM12: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 12
pub const INSTR_MEM12 = Register(INSTR_MEM12_val).init(base_address + 0x78);
/// INSTR_MEM11
const INSTR_MEM11_val = packed struct {
/// INSTR_MEM11 [0:15]
/// No description
INSTR_MEM11: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 11
pub const INSTR_MEM11 = Register(INSTR_MEM11_val).init(base_address + 0x74);
/// INSTR_MEM10
const INSTR_MEM10_val = packed struct {
/// INSTR_MEM10 [0:15]
/// No description
INSTR_MEM10: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 10
pub const INSTR_MEM10 = Register(INSTR_MEM10_val).init(base_address + 0x70);
/// INSTR_MEM9
const INSTR_MEM9_val = packed struct {
/// INSTR_MEM9 [0:15]
/// No description
INSTR_MEM9: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 9
pub const INSTR_MEM9 = Register(INSTR_MEM9_val).init(base_address + 0x6c);
/// INSTR_MEM8
const INSTR_MEM8_val = packed struct {
/// INSTR_MEM8 [0:15]
/// No description
INSTR_MEM8: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 8
pub const INSTR_MEM8 = Register(INSTR_MEM8_val).init(base_address + 0x68);
/// INSTR_MEM7
const INSTR_MEM7_val = packed struct {
/// INSTR_MEM7 [0:15]
/// No description
INSTR_MEM7: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 7
pub const INSTR_MEM7 = Register(INSTR_MEM7_val).init(base_address + 0x64);
/// INSTR_MEM6
const INSTR_MEM6_val = packed struct {
/// INSTR_MEM6 [0:15]
/// No description
INSTR_MEM6: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 6
pub const INSTR_MEM6 = Register(INSTR_MEM6_val).init(base_address + 0x60);
/// INSTR_MEM5
const INSTR_MEM5_val = packed struct {
/// INSTR_MEM5 [0:15]
/// No description
INSTR_MEM5: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 5
pub const INSTR_MEM5 = Register(INSTR_MEM5_val).init(base_address + 0x5c);
/// INSTR_MEM4
const INSTR_MEM4_val = packed struct {
/// INSTR_MEM4 [0:15]
/// No description
INSTR_MEM4: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 4
pub const INSTR_MEM4 = Register(INSTR_MEM4_val).init(base_address + 0x58);
/// INSTR_MEM3
const INSTR_MEM3_val = packed struct {
/// INSTR_MEM3 [0:15]
/// No description
INSTR_MEM3: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 3
pub const INSTR_MEM3 = Register(INSTR_MEM3_val).init(base_address + 0x54);
/// INSTR_MEM2
const INSTR_MEM2_val = packed struct {
/// INSTR_MEM2 [0:15]
/// No description
INSTR_MEM2: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 2
pub const INSTR_MEM2 = Register(INSTR_MEM2_val).init(base_address + 0x50);
/// INSTR_MEM1
const INSTR_MEM1_val = packed struct {
/// INSTR_MEM1 [0:15]
/// No description
INSTR_MEM1: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 1
pub const INSTR_MEM1 = Register(INSTR_MEM1_val).init(base_address + 0x4c);
/// INSTR_MEM0
const INSTR_MEM0_val = packed struct {
/// INSTR_MEM0 [0:15]
/// No description
INSTR_MEM0: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 0
pub const INSTR_MEM0 = Register(INSTR_MEM0_val).init(base_address + 0x48);
/// DBG_CFGINFO
const DBG_CFGINFO_val = packed struct {
/// FIFO_DEPTH [0:5]
/// The depth of the state machine TX/RX FIFOs, measured in words.\n
FIFO_DEPTH: u6 = 0,
/// unused [6:7]
_unused6: u2 = 0,
/// SM_COUNT [8:11]
/// The number of state machines this PIO instance is equipped with.
SM_COUNT: u4 = 0,
/// unused [12:15]
_unused12: u4 = 0,
/// IMEM_SIZE [16:21]
/// The size of the instruction memory, measured in units of one instruction
IMEM_SIZE: u6 = 0,
/// unused [22:31]
_unused22: u2 = 0,
_unused24: u8 = 0,
};
/// The PIO hardware has some free parameters that may vary between chip products.\n
pub const DBG_CFGINFO = Register(DBG_CFGINFO_val).init(base_address + 0x44);
/// DBG_PADOE
const DBG_PADOE_val = packed struct {
DBG_PADOE_0: u8 = 0,
DBG_PADOE_1: u8 = 0,
DBG_PADOE_2: u8 = 0,
DBG_PADOE_3: u8 = 0,
};
/// Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs.
pub const DBG_PADOE = Register(DBG_PADOE_val).init(base_address + 0x40);
/// DBG_PADOUT
const DBG_PADOUT_val = packed struct {
DBG_PADOUT_0: u8 = 0,
DBG_PADOUT_1: u8 = 0,
DBG_PADOUT_2: u8 = 0,
DBG_PADOUT_3: u8 = 0,
};
/// Read to sample the pad output values PIO is currently driving to the GPIOs.
pub const DBG_PADOUT = Register(DBG_PADOUT_val).init(base_address + 0x3c);
/// INPUT_SYNC_BYPASS
const INPUT_SYNC_BYPASS_val = packed struct {
INPUT_SYNC_BYPASS_0: u8 = 0,
INPUT_SYNC_BYPASS_1: u8 = 0,
INPUT_SYNC_BYPASS_2: u8 = 0,
INPUT_SYNC_BYPASS_3: u8 = 0,
};
/// There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO.\n
pub const INPUT_SYNC_BYPASS = Register(INPUT_SYNC_BYPASS_val).init(base_address + 0x38);
/// IRQ_FORCE
const IRQ_FORCE_val = packed struct {
/// IRQ_FORCE [0:7]
/// No description
IRQ_FORCE: u8 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines.
pub const IRQ_FORCE = Register(IRQ_FORCE_val).init(base_address + 0x34);
/// IRQ
const IRQ_val = packed struct {
/// IRQ [0:7]
/// No description
IRQ: u8 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag.\n\n
pub const IRQ = Register(IRQ_val).init(base_address + 0x30);
/// RXF3
const RXF3_val = packed struct {
RXF3_0: u8 = 0,
RXF3_1: u8 = 0,
RXF3_2: u8 = 0,
RXF3_3: u8 = 0,
};
/// Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.
pub const RXF3 = Register(RXF3_val).init(base_address + 0x2c);
/// RXF2
const RXF2_val = packed struct {
RXF2_0: u8 = 0,
RXF2_1: u8 = 0,
RXF2_2: u8 = 0,
RXF2_3: u8 = 0,
};
/// Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.
pub const RXF2 = Register(RXF2_val).init(base_address + 0x28);
/// RXF1
const RXF1_val = packed struct {
RXF1_0: u8 = 0,
RXF1_1: u8 = 0,
RXF1_2: u8 = 0,
RXF1_3: u8 = 0,
};
/// Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.
pub const RXF1 = Register(RXF1_val).init(base_address + 0x24);
/// RXF0
const RXF0_val = packed struct {
RXF0_0: u8 = 0,
RXF0_1: u8 = 0,
RXF0_2: u8 = 0,
RXF0_3: u8 = 0,
};
/// Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.
pub const RXF0 = Register(RXF0_val).init(base_address + 0x20);
/// TXF3
const TXF3_val = packed struct {
TXF3_0: u8 = 0,
TXF3_1: u8 = 0,
TXF3_2: u8 = 0,
TXF3_3: u8 = 0,
};
/// Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.
pub const TXF3 = Register(TXF3_val).init(base_address + 0x1c);
/// TXF2
const TXF2_val = packed struct {
TXF2_0: u8 = 0,
TXF2_1: u8 = 0,
TXF2_2: u8 = 0,
TXF2_3: u8 = 0,
};
/// Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.
pub const TXF2 = Register(TXF2_val).init(base_address + 0x18);
/// TXF1
const TXF1_val = packed struct {
TXF1_0: u8 = 0,
TXF1_1: u8 = 0,
TXF1_2: u8 = 0,
TXF1_3: u8 = 0,
};
/// Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.
pub const TXF1 = Register(TXF1_val).init(base_address + 0x14);
/// TXF0
const TXF0_val = packed struct {
TXF0_0: u8 = 0,
TXF0_1: u8 = 0,
TXF0_2: u8 = 0,
TXF0_3: u8 = 0,
};
/// Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.
pub const TXF0 = Register(TXF0_val).init(base_address + 0x10);
/// FLEVEL
const FLEVEL_val = packed struct {
/// TX0 [0:3]
/// No description
TX0: u4 = 0,
/// RX0 [4:7]
/// No description
RX0: u4 = 0,
/// TX1 [8:11]
/// No description
TX1: u4 = 0,
/// RX1 [12:15]
/// No description
RX1: u4 = 0,
/// TX2 [16:19]
/// No description
TX2: u4 = 0,
/// RX2 [20:23]
/// No description
RX2: u4 = 0,
/// TX3 [24:27]
/// No description
TX3: u4 = 0,
/// RX3 [28:31]
/// No description
RX3: u4 = 0,
};
/// FIFO levels
pub const FLEVEL = Register(FLEVEL_val).init(base_address + 0xc);
/// FDEBUG
const FDEBUG_val = packed struct {
/// RXSTALL [0:3]
/// State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear.
RXSTALL: u4 = 0,
/// unused [4:7]
_unused4: u4 = 0,
/// RXUNDER [8:11]
/// RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error.
RXUNDER: u4 = 0,
/// unused [12:15]
_unused12: u4 = 0,
/// TXOVER [16:19]
/// TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor.
TXOVER: u4 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// TXSTALL [24:27]
/// State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear.
TXSTALL: u4 = 0,
/// unused [28:31]
_unused28: u4 = 0,
};
/// FIFO debug register
pub const FDEBUG = Register(FDEBUG_val).init(base_address + 0x8);
/// FSTAT
const FSTAT_val = packed struct {
/// RXFULL [0:3]
/// State machine RX FIFO is full
RXFULL: u4 = 0,
/// unused [4:7]
_unused4: u4 = 0,
/// RXEMPTY [8:11]
/// State machine RX FIFO is empty
RXEMPTY: u4 = 15,
/// unused [12:15]
_unused12: u4 = 0,
/// TXFULL [16:19]
/// State machine TX FIFO is full
TXFULL: u4 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// TXEMPTY [24:27]
/// State machine TX FIFO is empty
TXEMPTY: u4 = 15,
/// unused [28:31]
_unused28: u4 = 0,
};
/// FIFO status register
pub const FSTAT = Register(FSTAT_val).init(base_address + 0x4);
/// CTRL
const CTRL_val = packed struct {
/// SM_ENABLE [0:3]
/// Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously.
SM_ENABLE: u4 = 0,
/// SM_RESTART [4:7]
/// Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution.\n\n
SM_RESTART: u4 = 0,
/// CLKDIV_RESTART [8:11]
/// Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep.\n\n
CLKDIV_RESTART: u4 = 0,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// PIO control register
pub const CTRL = Register(CTRL_val).init(base_address + 0x0);
};
/// Programmable IO block
pub const PIO1 = struct {
const base_address = 0x50300000;
/// IRQ1_INTS
const IRQ1_INTS_val = packed struct {
/// SM0_RXNEMPTY [0:0]
/// No description
SM0_RXNEMPTY: u1 = 0,
/// SM1_RXNEMPTY [1:1]
/// No description
SM1_RXNEMPTY: u1 = 0,
/// SM2_RXNEMPTY [2:2]
/// No description
SM2_RXNEMPTY: u1 = 0,
/// SM3_RXNEMPTY [3:3]
/// No description
SM3_RXNEMPTY: u1 = 0,
/// SM0_TXNFULL [4:4]
/// No description
SM0_TXNFULL: u1 = 0,
/// SM1_TXNFULL [5:5]
/// No description
SM1_TXNFULL: u1 = 0,
/// SM2_TXNFULL [6:6]
/// No description
SM2_TXNFULL: u1 = 0,
/// SM3_TXNFULL [7:7]
/// No description
SM3_TXNFULL: u1 = 0,
/// SM0 [8:8]
/// No description
SM0: u1 = 0,
/// SM1 [9:9]
/// No description
SM1: u1 = 0,
/// SM2 [10:10]
/// No description
SM2: u1 = 0,
/// SM3 [11:11]
/// No description
SM3: u1 = 0,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt status after masking & forcing for irq1
pub const IRQ1_INTS = Register(IRQ1_INTS_val).init(base_address + 0x140);
/// IRQ1_INTF
const IRQ1_INTF_val = packed struct {
/// SM0_RXNEMPTY [0:0]
/// No description
SM0_RXNEMPTY: u1 = 0,
/// SM1_RXNEMPTY [1:1]
/// No description
SM1_RXNEMPTY: u1 = 0,
/// SM2_RXNEMPTY [2:2]
/// No description
SM2_RXNEMPTY: u1 = 0,
/// SM3_RXNEMPTY [3:3]
/// No description
SM3_RXNEMPTY: u1 = 0,
/// SM0_TXNFULL [4:4]
/// No description
SM0_TXNFULL: u1 = 0,
/// SM1_TXNFULL [5:5]
/// No description
SM1_TXNFULL: u1 = 0,
/// SM2_TXNFULL [6:6]
/// No description
SM2_TXNFULL: u1 = 0,
/// SM3_TXNFULL [7:7]
/// No description
SM3_TXNFULL: u1 = 0,
/// SM0 [8:8]
/// No description
SM0: u1 = 0,
/// SM1 [9:9]
/// No description
SM1: u1 = 0,
/// SM2 [10:10]
/// No description
SM2: u1 = 0,
/// SM3 [11:11]
/// No description
SM3: u1 = 0,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt Force for irq1
pub const IRQ1_INTF = Register(IRQ1_INTF_val).init(base_address + 0x13c);
/// IRQ1_INTE
const IRQ1_INTE_val = packed struct {
/// SM0_RXNEMPTY [0:0]
/// No description
SM0_RXNEMPTY: u1 = 0,
/// SM1_RXNEMPTY [1:1]
/// No description
SM1_RXNEMPTY: u1 = 0,
/// SM2_RXNEMPTY [2:2]
/// No description
SM2_RXNEMPTY: u1 = 0,
/// SM3_RXNEMPTY [3:3]
/// No description
SM3_RXNEMPTY: u1 = 0,
/// SM0_TXNFULL [4:4]
/// No description
SM0_TXNFULL: u1 = 0,
/// SM1_TXNFULL [5:5]
/// No description
SM1_TXNFULL: u1 = 0,
/// SM2_TXNFULL [6:6]
/// No description
SM2_TXNFULL: u1 = 0,
/// SM3_TXNFULL [7:7]
/// No description
SM3_TXNFULL: u1 = 0,
/// SM0 [8:8]
/// No description
SM0: u1 = 0,
/// SM1 [9:9]
/// No description
SM1: u1 = 0,
/// SM2 [10:10]
/// No description
SM2: u1 = 0,
/// SM3 [11:11]
/// No description
SM3: u1 = 0,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt Enable for irq1
pub const IRQ1_INTE = Register(IRQ1_INTE_val).init(base_address + 0x138);
/// IRQ0_INTS
const IRQ0_INTS_val = packed struct {
/// SM0_RXNEMPTY [0:0]
/// No description
SM0_RXNEMPTY: u1 = 0,
/// SM1_RXNEMPTY [1:1]
/// No description
SM1_RXNEMPTY: u1 = 0,
/// SM2_RXNEMPTY [2:2]
/// No description
SM2_RXNEMPTY: u1 = 0,
/// SM3_RXNEMPTY [3:3]
/// No description
SM3_RXNEMPTY: u1 = 0,
/// SM0_TXNFULL [4:4]
/// No description
SM0_TXNFULL: u1 = 0,
/// SM1_TXNFULL [5:5]
/// No description
SM1_TXNFULL: u1 = 0,
/// SM2_TXNFULL [6:6]
/// No description
SM2_TXNFULL: u1 = 0,
/// SM3_TXNFULL [7:7]
/// No description
SM3_TXNFULL: u1 = 0,
/// SM0 [8:8]
/// No description
SM0: u1 = 0,
/// SM1 [9:9]
/// No description
SM1: u1 = 0,
/// SM2 [10:10]
/// No description
SM2: u1 = 0,
/// SM3 [11:11]
/// No description
SM3: u1 = 0,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt status after masking & forcing for irq0
pub const IRQ0_INTS = Register(IRQ0_INTS_val).init(base_address + 0x134);
/// IRQ0_INTF
const IRQ0_INTF_val = packed struct {
/// SM0_RXNEMPTY [0:0]
/// No description
SM0_RXNEMPTY: u1 = 0,
/// SM1_RXNEMPTY [1:1]
/// No description
SM1_RXNEMPTY: u1 = 0,
/// SM2_RXNEMPTY [2:2]
/// No description
SM2_RXNEMPTY: u1 = 0,
/// SM3_RXNEMPTY [3:3]
/// No description
SM3_RXNEMPTY: u1 = 0,
/// SM0_TXNFULL [4:4]
/// No description
SM0_TXNFULL: u1 = 0,
/// SM1_TXNFULL [5:5]
/// No description
SM1_TXNFULL: u1 = 0,
/// SM2_TXNFULL [6:6]
/// No description
SM2_TXNFULL: u1 = 0,
/// SM3_TXNFULL [7:7]
/// No description
SM3_TXNFULL: u1 = 0,
/// SM0 [8:8]
/// No description
SM0: u1 = 0,
/// SM1 [9:9]
/// No description
SM1: u1 = 0,
/// SM2 [10:10]
/// No description
SM2: u1 = 0,
/// SM3 [11:11]
/// No description
SM3: u1 = 0,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt Force for irq0
pub const IRQ0_INTF = Register(IRQ0_INTF_val).init(base_address + 0x130);
/// IRQ0_INTE
const IRQ0_INTE_val = packed struct {
/// SM0_RXNEMPTY [0:0]
/// No description
SM0_RXNEMPTY: u1 = 0,
/// SM1_RXNEMPTY [1:1]
/// No description
SM1_RXNEMPTY: u1 = 0,
/// SM2_RXNEMPTY [2:2]
/// No description
SM2_RXNEMPTY: u1 = 0,
/// SM3_RXNEMPTY [3:3]
/// No description
SM3_RXNEMPTY: u1 = 0,
/// SM0_TXNFULL [4:4]
/// No description
SM0_TXNFULL: u1 = 0,
/// SM1_TXNFULL [5:5]
/// No description
SM1_TXNFULL: u1 = 0,
/// SM2_TXNFULL [6:6]
/// No description
SM2_TXNFULL: u1 = 0,
/// SM3_TXNFULL [7:7]
/// No description
SM3_TXNFULL: u1 = 0,
/// SM0 [8:8]
/// No description
SM0: u1 = 0,
/// SM1 [9:9]
/// No description
SM1: u1 = 0,
/// SM2 [10:10]
/// No description
SM2: u1 = 0,
/// SM3 [11:11]
/// No description
SM3: u1 = 0,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Interrupt Enable for irq0
pub const IRQ0_INTE = Register(IRQ0_INTE_val).init(base_address + 0x12c);
/// INTR
const INTR_val = packed struct {
/// SM0_RXNEMPTY [0:0]
/// No description
SM0_RXNEMPTY: u1 = 0,
/// SM1_RXNEMPTY [1:1]
/// No description
SM1_RXNEMPTY: u1 = 0,
/// SM2_RXNEMPTY [2:2]
/// No description
SM2_RXNEMPTY: u1 = 0,
/// SM3_RXNEMPTY [3:3]
/// No description
SM3_RXNEMPTY: u1 = 0,
/// SM0_TXNFULL [4:4]
/// No description
SM0_TXNFULL: u1 = 0,
/// SM1_TXNFULL [5:5]
/// No description
SM1_TXNFULL: u1 = 0,
/// SM2_TXNFULL [6:6]
/// No description
SM2_TXNFULL: u1 = 0,
/// SM3_TXNFULL [7:7]
/// No description
SM3_TXNFULL: u1 = 0,
/// SM0 [8:8]
/// No description
SM0: u1 = 0,
/// SM1 [9:9]
/// No description
SM1: u1 = 0,
/// SM2 [10:10]
/// No description
SM2: u1 = 0,
/// SM3 [11:11]
/// No description
SM3: u1 = 0,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Raw Interrupts
pub const INTR = Register(INTR_val).init(base_address + 0x128);
/// SM3_PINCTRL
const SM3_PINCTRL_val = packed struct {
/// OUT_BASE [0:4]
/// The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.
OUT_BASE: u5 = 0,
/// SET_BASE [5:9]
/// The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.
SET_BASE: u5 = 0,
/// SIDESET_BASE [10:14]
/// The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.
SIDESET_BASE: u5 = 0,
/// IN_BASE [15:19]
/// The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.
IN_BASE: u5 = 0,
/// OUT_COUNT [20:25]
/// The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.
OUT_COUNT: u6 = 0,
/// SET_COUNT [26:28]
/// The number of pins asserted by a SET. In the range 0 to 5 inclusive.
SET_COUNT: u3 = 5,
/// SIDESET_COUNT [29:31]
/// The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).
SIDESET_COUNT: u3 = 0,
};
/// State machine pin control
pub const SM3_PINCTRL = Register(SM3_PINCTRL_val).init(base_address + 0x124);
/// SM3_INSTR
const SM3_INSTR_val = packed struct {
/// SM3_INSTR [0:15]
/// No description
SM3_INSTR: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Read to see the instruction currently addressed by state machine 3's program counter\n
pub const SM3_INSTR = Register(SM3_INSTR_val).init(base_address + 0x120);
/// SM3_ADDR
const SM3_ADDR_val = packed struct {
/// SM3_ADDR [0:4]
/// No description
SM3_ADDR: u5 = 0,
/// unused [5:31]
_unused5: u3 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Current instruction address of state machine 3
pub const SM3_ADDR = Register(SM3_ADDR_val).init(base_address + 0x11c);
/// SM3_SHIFTCTRL
const SM3_SHIFTCTRL_val = packed struct {
/// unused [0:15]
_unused0: u8 = 0,
_unused8: u8 = 0,
/// AUTOPUSH [16:16]
/// Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.
AUTOPUSH: u1 = 0,
/// AUTOPULL [17:17]
/// Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.
AUTOPULL: u1 = 0,
/// IN_SHIFTDIR [18:18]
/// 1 = shift input shift register to right (data enters from left). 0 = to left.
IN_SHIFTDIR: u1 = 1,
/// OUT_SHIFTDIR [19:19]
/// 1 = shift out of output shift register to right. 0 = to left.
OUT_SHIFTDIR: u1 = 1,
/// PUSH_THRESH [20:24]
/// Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n
PUSH_THRESH: u5 = 0,
/// PULL_THRESH [25:29]
/// Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n
PULL_THRESH: u5 = 0,
/// FJOIN_TX [30:30]
/// When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n
FJOIN_TX: u1 = 0,
/// FJOIN_RX [31:31]
/// When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n
FJOIN_RX: u1 = 0,
};
/// Control behaviour of the input/output shift registers for state machine 3
pub const SM3_SHIFTCTRL = Register(SM3_SHIFTCTRL_val).init(base_address + 0x118);
/// SM3_EXECCTRL
const SM3_EXECCTRL_val = packed struct {
/// STATUS_N [0:3]
/// Comparison level for the MOV x, STATUS instruction
STATUS_N: u4 = 0,
/// STATUS_SEL [4:4]
/// Comparison used for the MOV x, STATUS instruction.
STATUS_SEL: u1 = 0,
/// unused [5:6]
_unused5: u2 = 0,
/// WRAP_BOTTOM [7:11]
/// After reaching wrap_top, execution is wrapped to this address.
WRAP_BOTTOM: u5 = 0,
/// WRAP_TOP [12:16]
/// After reaching this address, execution is wrapped to wrap_bottom.\n
WRAP_TOP: u5 = 31,
/// OUT_STICKY [17:17]
/// Continuously assert the most recent OUT/SET to the pins
OUT_STICKY: u1 = 0,
/// INLINE_OUT_EN [18:18]
/// If 1, use a bit of OUT data as an auxiliary write enable\n
INLINE_OUT_EN: u1 = 0,
/// OUT_EN_SEL [19:23]
/// Which data bit to use for inline OUT enable
OUT_EN_SEL: u5 = 0,
/// JMP_PIN [24:28]
/// The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.
JMP_PIN: u5 = 0,
/// SIDE_PINDIR [29:29]
/// If 1, side-set data is asserted to pin directions, instead of pin values
SIDE_PINDIR: u1 = 0,
/// SIDE_EN [30:30]
/// If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
SIDE_EN: u1 = 0,
/// EXEC_STALLED [31:31]
/// If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.
EXEC_STALLED: u1 = 0,
};
/// Execution/behavioural settings for state machine 3
pub const SM3_EXECCTRL = Register(SM3_EXECCTRL_val).init(base_address + 0x114);
/// SM3_CLKDIV
const SM3_CLKDIV_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// FRAC [8:15]
/// Fractional part of clock divisor
FRAC: u8 = 0,
/// INT [16:31]
/// Effective frequency is sysclk/(int + frac/256).\n
INT: u16 = 1,
};
/// Clock divisor register for state machine 3\n
pub const SM3_CLKDIV = Register(SM3_CLKDIV_val).init(base_address + 0x110);
/// SM2_PINCTRL
const SM2_PINCTRL_val = packed struct {
/// OUT_BASE [0:4]
/// The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.
OUT_BASE: u5 = 0,
/// SET_BASE [5:9]
/// The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.
SET_BASE: u5 = 0,
/// SIDESET_BASE [10:14]
/// The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.
SIDESET_BASE: u5 = 0,
/// IN_BASE [15:19]
/// The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.
IN_BASE: u5 = 0,
/// OUT_COUNT [20:25]
/// The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.
OUT_COUNT: u6 = 0,
/// SET_COUNT [26:28]
/// The number of pins asserted by a SET. In the range 0 to 5 inclusive.
SET_COUNT: u3 = 5,
/// SIDESET_COUNT [29:31]
/// The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).
SIDESET_COUNT: u3 = 0,
};
/// State machine pin control
pub const SM2_PINCTRL = Register(SM2_PINCTRL_val).init(base_address + 0x10c);
/// SM2_INSTR
const SM2_INSTR_val = packed struct {
/// SM2_INSTR [0:15]
/// No description
SM2_INSTR: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Read to see the instruction currently addressed by state machine 2's program counter\n
pub const SM2_INSTR = Register(SM2_INSTR_val).init(base_address + 0x108);
/// SM2_ADDR
const SM2_ADDR_val = packed struct {
/// SM2_ADDR [0:4]
/// No description
SM2_ADDR: u5 = 0,
/// unused [5:31]
_unused5: u3 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Current instruction address of state machine 2
pub const SM2_ADDR = Register(SM2_ADDR_val).init(base_address + 0x104);
/// SM2_SHIFTCTRL
const SM2_SHIFTCTRL_val = packed struct {
/// unused [0:15]
_unused0: u8 = 0,
_unused8: u8 = 0,
/// AUTOPUSH [16:16]
/// Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.
AUTOPUSH: u1 = 0,
/// AUTOPULL [17:17]
/// Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.
AUTOPULL: u1 = 0,
/// IN_SHIFTDIR [18:18]
/// 1 = shift input shift register to right (data enters from left). 0 = to left.
IN_SHIFTDIR: u1 = 1,
/// OUT_SHIFTDIR [19:19]
/// 1 = shift out of output shift register to right. 0 = to left.
OUT_SHIFTDIR: u1 = 1,
/// PUSH_THRESH [20:24]
/// Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n
PUSH_THRESH: u5 = 0,
/// PULL_THRESH [25:29]
/// Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n
PULL_THRESH: u5 = 0,
/// FJOIN_TX [30:30]
/// When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n
FJOIN_TX: u1 = 0,
/// FJOIN_RX [31:31]
/// When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n
FJOIN_RX: u1 = 0,
};
/// Control behaviour of the input/output shift registers for state machine 2
pub const SM2_SHIFTCTRL = Register(SM2_SHIFTCTRL_val).init(base_address + 0x100);
/// SM2_EXECCTRL
const SM2_EXECCTRL_val = packed struct {
/// STATUS_N [0:3]
/// Comparison level for the MOV x, STATUS instruction
STATUS_N: u4 = 0,
/// STATUS_SEL [4:4]
/// Comparison used for the MOV x, STATUS instruction.
STATUS_SEL: u1 = 0,
/// unused [5:6]
_unused5: u2 = 0,
/// WRAP_BOTTOM [7:11]
/// After reaching wrap_top, execution is wrapped to this address.
WRAP_BOTTOM: u5 = 0,
/// WRAP_TOP [12:16]
/// After reaching this address, execution is wrapped to wrap_bottom.\n
WRAP_TOP: u5 = 31,
/// OUT_STICKY [17:17]
/// Continuously assert the most recent OUT/SET to the pins
OUT_STICKY: u1 = 0,
/// INLINE_OUT_EN [18:18]
/// If 1, use a bit of OUT data as an auxiliary write enable\n
INLINE_OUT_EN: u1 = 0,
/// OUT_EN_SEL [19:23]
/// Which data bit to use for inline OUT enable
OUT_EN_SEL: u5 = 0,
/// JMP_PIN [24:28]
/// The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.
JMP_PIN: u5 = 0,
/// SIDE_PINDIR [29:29]
/// If 1, side-set data is asserted to pin directions, instead of pin values
SIDE_PINDIR: u1 = 0,
/// SIDE_EN [30:30]
/// If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
SIDE_EN: u1 = 0,
/// EXEC_STALLED [31:31]
/// If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.
EXEC_STALLED: u1 = 0,
};
/// Execution/behavioural settings for state machine 2
pub const SM2_EXECCTRL = Register(SM2_EXECCTRL_val).init(base_address + 0xfc);
/// SM2_CLKDIV
const SM2_CLKDIV_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// FRAC [8:15]
/// Fractional part of clock divisor
FRAC: u8 = 0,
/// INT [16:31]
/// Effective frequency is sysclk/(int + frac/256).\n
INT: u16 = 1,
};
/// Clock divisor register for state machine 2\n
pub const SM2_CLKDIV = Register(SM2_CLKDIV_val).init(base_address + 0xf8);
/// SM1_PINCTRL
const SM1_PINCTRL_val = packed struct {
/// OUT_BASE [0:4]
/// The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.
OUT_BASE: u5 = 0,
/// SET_BASE [5:9]
/// The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.
SET_BASE: u5 = 0,
/// SIDESET_BASE [10:14]
/// The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.
SIDESET_BASE: u5 = 0,
/// IN_BASE [15:19]
/// The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.
IN_BASE: u5 = 0,
/// OUT_COUNT [20:25]
/// The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.
OUT_COUNT: u6 = 0,
/// SET_COUNT [26:28]
/// The number of pins asserted by a SET. In the range 0 to 5 inclusive.
SET_COUNT: u3 = 5,
/// SIDESET_COUNT [29:31]
/// The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).
SIDESET_COUNT: u3 = 0,
};
/// State machine pin control
pub const SM1_PINCTRL = Register(SM1_PINCTRL_val).init(base_address + 0xf4);
/// SM1_INSTR
const SM1_INSTR_val = packed struct {
/// SM1_INSTR [0:15]
/// No description
SM1_INSTR: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Read to see the instruction currently addressed by state machine 1's program counter\n
pub const SM1_INSTR = Register(SM1_INSTR_val).init(base_address + 0xf0);
/// SM1_ADDR
const SM1_ADDR_val = packed struct {
/// SM1_ADDR [0:4]
/// No description
SM1_ADDR: u5 = 0,
/// unused [5:31]
_unused5: u3 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Current instruction address of state machine 1
pub const SM1_ADDR = Register(SM1_ADDR_val).init(base_address + 0xec);
/// SM1_SHIFTCTRL
const SM1_SHIFTCTRL_val = packed struct {
/// unused [0:15]
_unused0: u8 = 0,
_unused8: u8 = 0,
/// AUTOPUSH [16:16]
/// Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.
AUTOPUSH: u1 = 0,
/// AUTOPULL [17:17]
/// Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.
AUTOPULL: u1 = 0,
/// IN_SHIFTDIR [18:18]
/// 1 = shift input shift register to right (data enters from left). 0 = to left.
IN_SHIFTDIR: u1 = 1,
/// OUT_SHIFTDIR [19:19]
/// 1 = shift out of output shift register to right. 0 = to left.
OUT_SHIFTDIR: u1 = 1,
/// PUSH_THRESH [20:24]
/// Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n
PUSH_THRESH: u5 = 0,
/// PULL_THRESH [25:29]
/// Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n
PULL_THRESH: u5 = 0,
/// FJOIN_TX [30:30]
/// When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n
FJOIN_TX: u1 = 0,
/// FJOIN_RX [31:31]
/// When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n
FJOIN_RX: u1 = 0,
};
/// Control behaviour of the input/output shift registers for state machine 1
pub const SM1_SHIFTCTRL = Register(SM1_SHIFTCTRL_val).init(base_address + 0xe8);
/// SM1_EXECCTRL
const SM1_EXECCTRL_val = packed struct {
/// STATUS_N [0:3]
/// Comparison level for the MOV x, STATUS instruction
STATUS_N: u4 = 0,
/// STATUS_SEL [4:4]
/// Comparison used for the MOV x, STATUS instruction.
STATUS_SEL: u1 = 0,
/// unused [5:6]
_unused5: u2 = 0,
/// WRAP_BOTTOM [7:11]
/// After reaching wrap_top, execution is wrapped to this address.
WRAP_BOTTOM: u5 = 0,
/// WRAP_TOP [12:16]
/// After reaching this address, execution is wrapped to wrap_bottom.\n
WRAP_TOP: u5 = 31,
/// OUT_STICKY [17:17]
/// Continuously assert the most recent OUT/SET to the pins
OUT_STICKY: u1 = 0,
/// INLINE_OUT_EN [18:18]
/// If 1, use a bit of OUT data as an auxiliary write enable\n
INLINE_OUT_EN: u1 = 0,
/// OUT_EN_SEL [19:23]
/// Which data bit to use for inline OUT enable
OUT_EN_SEL: u5 = 0,
/// JMP_PIN [24:28]
/// The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.
JMP_PIN: u5 = 0,
/// SIDE_PINDIR [29:29]
/// If 1, side-set data is asserted to pin directions, instead of pin values
SIDE_PINDIR: u1 = 0,
/// SIDE_EN [30:30]
/// If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
SIDE_EN: u1 = 0,
/// EXEC_STALLED [31:31]
/// If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.
EXEC_STALLED: u1 = 0,
};
/// Execution/behavioural settings for state machine 1
pub const SM1_EXECCTRL = Register(SM1_EXECCTRL_val).init(base_address + 0xe4);
/// SM1_CLKDIV
const SM1_CLKDIV_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// FRAC [8:15]
/// Fractional part of clock divisor
FRAC: u8 = 0,
/// INT [16:31]
/// Effective frequency is sysclk/(int + frac/256).\n
INT: u16 = 1,
};
/// Clock divisor register for state machine 1\n
pub const SM1_CLKDIV = Register(SM1_CLKDIV_val).init(base_address + 0xe0);
/// SM0_PINCTRL
const SM0_PINCTRL_val = packed struct {
/// OUT_BASE [0:4]
/// The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.
OUT_BASE: u5 = 0,
/// SET_BASE [5:9]
/// The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.
SET_BASE: u5 = 0,
/// SIDESET_BASE [10:14]
/// The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.
SIDESET_BASE: u5 = 0,
/// IN_BASE [15:19]
/// The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.
IN_BASE: u5 = 0,
/// OUT_COUNT [20:25]
/// The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.
OUT_COUNT: u6 = 0,
/// SET_COUNT [26:28]
/// The number of pins asserted by a SET. In the range 0 to 5 inclusive.
SET_COUNT: u3 = 5,
/// SIDESET_COUNT [29:31]
/// The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).
SIDESET_COUNT: u3 = 0,
};
/// State machine pin control
pub const SM0_PINCTRL = Register(SM0_PINCTRL_val).init(base_address + 0xdc);
/// SM0_INSTR
const SM0_INSTR_val = packed struct {
/// SM0_INSTR [0:15]
/// No description
SM0_INSTR: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Read to see the instruction currently addressed by state machine 0's program counter\n
pub const SM0_INSTR = Register(SM0_INSTR_val).init(base_address + 0xd8);
/// SM0_ADDR
const SM0_ADDR_val = packed struct {
/// SM0_ADDR [0:4]
/// No description
SM0_ADDR: u5 = 0,
/// unused [5:31]
_unused5: u3 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Current instruction address of state machine 0
pub const SM0_ADDR = Register(SM0_ADDR_val).init(base_address + 0xd4);
/// SM0_SHIFTCTRL
const SM0_SHIFTCTRL_val = packed struct {
/// unused [0:15]
_unused0: u8 = 0,
_unused8: u8 = 0,
/// AUTOPUSH [16:16]
/// Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.
AUTOPUSH: u1 = 0,
/// AUTOPULL [17:17]
/// Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.
AUTOPULL: u1 = 0,
/// IN_SHIFTDIR [18:18]
/// 1 = shift input shift register to right (data enters from left). 0 = to left.
IN_SHIFTDIR: u1 = 1,
/// OUT_SHIFTDIR [19:19]
/// 1 = shift out of output shift register to right. 0 = to left.
OUT_SHIFTDIR: u1 = 1,
/// PUSH_THRESH [20:24]
/// Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n
PUSH_THRESH: u5 = 0,
/// PULL_THRESH [25:29]
/// Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n
PULL_THRESH: u5 = 0,
/// FJOIN_TX [30:30]
/// When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n
FJOIN_TX: u1 = 0,
/// FJOIN_RX [31:31]
/// When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n
FJOIN_RX: u1 = 0,
};
/// Control behaviour of the input/output shift registers for state machine 0
pub const SM0_SHIFTCTRL = Register(SM0_SHIFTCTRL_val).init(base_address + 0xd0);
/// SM0_EXECCTRL
const SM0_EXECCTRL_val = packed struct {
/// STATUS_N [0:3]
/// Comparison level for the MOV x, STATUS instruction
STATUS_N: u4 = 0,
/// STATUS_SEL [4:4]
/// Comparison used for the MOV x, STATUS instruction.
STATUS_SEL: u1 = 0,
/// unused [5:6]
_unused5: u2 = 0,
/// WRAP_BOTTOM [7:11]
/// After reaching wrap_top, execution is wrapped to this address.
WRAP_BOTTOM: u5 = 0,
/// WRAP_TOP [12:16]
/// After reaching this address, execution is wrapped to wrap_bottom.\n
WRAP_TOP: u5 = 31,
/// OUT_STICKY [17:17]
/// Continuously assert the most recent OUT/SET to the pins
OUT_STICKY: u1 = 0,
/// INLINE_OUT_EN [18:18]
/// If 1, use a bit of OUT data as an auxiliary write enable\n
INLINE_OUT_EN: u1 = 0,
/// OUT_EN_SEL [19:23]
/// Which data bit to use for inline OUT enable
OUT_EN_SEL: u5 = 0,
/// JMP_PIN [24:28]
/// The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.
JMP_PIN: u5 = 0,
/// SIDE_PINDIR [29:29]
/// If 1, side-set data is asserted to pin directions, instead of pin values
SIDE_PINDIR: u1 = 0,
/// SIDE_EN [30:30]
/// If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
SIDE_EN: u1 = 0,
/// EXEC_STALLED [31:31]
/// If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.
EXEC_STALLED: u1 = 0,
};
/// Execution/behavioural settings for state machine 0
pub const SM0_EXECCTRL = Register(SM0_EXECCTRL_val).init(base_address + 0xcc);
/// SM0_CLKDIV
const SM0_CLKDIV_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// FRAC [8:15]
/// Fractional part of clock divisor
FRAC: u8 = 0,
/// INT [16:31]
/// Effective frequency is sysclk/(int + frac/256).\n
INT: u16 = 1,
};
/// Clock divisor register for state machine 0\n
pub const SM0_CLKDIV = Register(SM0_CLKDIV_val).init(base_address + 0xc8);
/// INSTR_MEM31
const INSTR_MEM31_val = packed struct {
/// INSTR_MEM31 [0:15]
/// No description
INSTR_MEM31: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 31
pub const INSTR_MEM31 = Register(INSTR_MEM31_val).init(base_address + 0xc4);
/// INSTR_MEM30
const INSTR_MEM30_val = packed struct {
/// INSTR_MEM30 [0:15]
/// No description
INSTR_MEM30: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 30
pub const INSTR_MEM30 = Register(INSTR_MEM30_val).init(base_address + 0xc0);
/// INSTR_MEM29
const INSTR_MEM29_val = packed struct {
/// INSTR_MEM29 [0:15]
/// No description
INSTR_MEM29: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 29
pub const INSTR_MEM29 = Register(INSTR_MEM29_val).init(base_address + 0xbc);
/// INSTR_MEM28
const INSTR_MEM28_val = packed struct {
/// INSTR_MEM28 [0:15]
/// No description
INSTR_MEM28: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 28
pub const INSTR_MEM28 = Register(INSTR_MEM28_val).init(base_address + 0xb8);
/// INSTR_MEM27
const INSTR_MEM27_val = packed struct {
/// INSTR_MEM27 [0:15]
/// No description
INSTR_MEM27: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 27
pub const INSTR_MEM27 = Register(INSTR_MEM27_val).init(base_address + 0xb4);
/// INSTR_MEM26
const INSTR_MEM26_val = packed struct {
/// INSTR_MEM26 [0:15]
/// No description
INSTR_MEM26: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 26
pub const INSTR_MEM26 = Register(INSTR_MEM26_val).init(base_address + 0xb0);
/// INSTR_MEM25
const INSTR_MEM25_val = packed struct {
/// INSTR_MEM25 [0:15]
/// No description
INSTR_MEM25: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 25
pub const INSTR_MEM25 = Register(INSTR_MEM25_val).init(base_address + 0xac);
/// INSTR_MEM24
const INSTR_MEM24_val = packed struct {
/// INSTR_MEM24 [0:15]
/// No description
INSTR_MEM24: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 24
pub const INSTR_MEM24 = Register(INSTR_MEM24_val).init(base_address + 0xa8);
/// INSTR_MEM23
const INSTR_MEM23_val = packed struct {
/// INSTR_MEM23 [0:15]
/// No description
INSTR_MEM23: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 23
pub const INSTR_MEM23 = Register(INSTR_MEM23_val).init(base_address + 0xa4);
/// INSTR_MEM22
const INSTR_MEM22_val = packed struct {
/// INSTR_MEM22 [0:15]
/// No description
INSTR_MEM22: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 22
pub const INSTR_MEM22 = Register(INSTR_MEM22_val).init(base_address + 0xa0);
/// INSTR_MEM21
const INSTR_MEM21_val = packed struct {
/// INSTR_MEM21 [0:15]
/// No description
INSTR_MEM21: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 21
pub const INSTR_MEM21 = Register(INSTR_MEM21_val).init(base_address + 0x9c);
/// INSTR_MEM20
const INSTR_MEM20_val = packed struct {
/// INSTR_MEM20 [0:15]
/// No description
INSTR_MEM20: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 20
pub const INSTR_MEM20 = Register(INSTR_MEM20_val).init(base_address + 0x98);
/// INSTR_MEM19
const INSTR_MEM19_val = packed struct {
/// INSTR_MEM19 [0:15]
/// No description
INSTR_MEM19: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 19
pub const INSTR_MEM19 = Register(INSTR_MEM19_val).init(base_address + 0x94);
/// INSTR_MEM18
const INSTR_MEM18_val = packed struct {
/// INSTR_MEM18 [0:15]
/// No description
INSTR_MEM18: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 18
pub const INSTR_MEM18 = Register(INSTR_MEM18_val).init(base_address + 0x90);
/// INSTR_MEM17
const INSTR_MEM17_val = packed struct {
/// INSTR_MEM17 [0:15]
/// No description
INSTR_MEM17: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 17
pub const INSTR_MEM17 = Register(INSTR_MEM17_val).init(base_address + 0x8c);
/// INSTR_MEM16
const INSTR_MEM16_val = packed struct {
/// INSTR_MEM16 [0:15]
/// No description
INSTR_MEM16: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 16
pub const INSTR_MEM16 = Register(INSTR_MEM16_val).init(base_address + 0x88);
/// INSTR_MEM15
const INSTR_MEM15_val = packed struct {
/// INSTR_MEM15 [0:15]
/// No description
INSTR_MEM15: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 15
pub const INSTR_MEM15 = Register(INSTR_MEM15_val).init(base_address + 0x84);
/// INSTR_MEM14
const INSTR_MEM14_val = packed struct {
/// INSTR_MEM14 [0:15]
/// No description
INSTR_MEM14: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 14
pub const INSTR_MEM14 = Register(INSTR_MEM14_val).init(base_address + 0x80);
/// INSTR_MEM13
const INSTR_MEM13_val = packed struct {
/// INSTR_MEM13 [0:15]
/// No description
INSTR_MEM13: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 13
pub const INSTR_MEM13 = Register(INSTR_MEM13_val).init(base_address + 0x7c);
/// INSTR_MEM12
const INSTR_MEM12_val = packed struct {
/// INSTR_MEM12 [0:15]
/// No description
INSTR_MEM12: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 12
pub const INSTR_MEM12 = Register(INSTR_MEM12_val).init(base_address + 0x78);
/// INSTR_MEM11
const INSTR_MEM11_val = packed struct {
/// INSTR_MEM11 [0:15]
/// No description
INSTR_MEM11: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 11
pub const INSTR_MEM11 = Register(INSTR_MEM11_val).init(base_address + 0x74);
/// INSTR_MEM10
const INSTR_MEM10_val = packed struct {
/// INSTR_MEM10 [0:15]
/// No description
INSTR_MEM10: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 10
pub const INSTR_MEM10 = Register(INSTR_MEM10_val).init(base_address + 0x70);
/// INSTR_MEM9
const INSTR_MEM9_val = packed struct {
/// INSTR_MEM9 [0:15]
/// No description
INSTR_MEM9: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 9
pub const INSTR_MEM9 = Register(INSTR_MEM9_val).init(base_address + 0x6c);
/// INSTR_MEM8
const INSTR_MEM8_val = packed struct {
/// INSTR_MEM8 [0:15]
/// No description
INSTR_MEM8: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 8
pub const INSTR_MEM8 = Register(INSTR_MEM8_val).init(base_address + 0x68);
/// INSTR_MEM7
const INSTR_MEM7_val = packed struct {
/// INSTR_MEM7 [0:15]
/// No description
INSTR_MEM7: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 7
pub const INSTR_MEM7 = Register(INSTR_MEM7_val).init(base_address + 0x64);
/// INSTR_MEM6
const INSTR_MEM6_val = packed struct {
/// INSTR_MEM6 [0:15]
/// No description
INSTR_MEM6: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 6
pub const INSTR_MEM6 = Register(INSTR_MEM6_val).init(base_address + 0x60);
/// INSTR_MEM5
const INSTR_MEM5_val = packed struct {
/// INSTR_MEM5 [0:15]
/// No description
INSTR_MEM5: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 5
pub const INSTR_MEM5 = Register(INSTR_MEM5_val).init(base_address + 0x5c);
/// INSTR_MEM4
const INSTR_MEM4_val = packed struct {
/// INSTR_MEM4 [0:15]
/// No description
INSTR_MEM4: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 4
pub const INSTR_MEM4 = Register(INSTR_MEM4_val).init(base_address + 0x58);
/// INSTR_MEM3
const INSTR_MEM3_val = packed struct {
/// INSTR_MEM3 [0:15]
/// No description
INSTR_MEM3: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 3
pub const INSTR_MEM3 = Register(INSTR_MEM3_val).init(base_address + 0x54);
/// INSTR_MEM2
const INSTR_MEM2_val = packed struct {
/// INSTR_MEM2 [0:15]
/// No description
INSTR_MEM2: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 2
pub const INSTR_MEM2 = Register(INSTR_MEM2_val).init(base_address + 0x50);
/// INSTR_MEM1
const INSTR_MEM1_val = packed struct {
/// INSTR_MEM1 [0:15]
/// No description
INSTR_MEM1: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 1
pub const INSTR_MEM1 = Register(INSTR_MEM1_val).init(base_address + 0x4c);
/// INSTR_MEM0
const INSTR_MEM0_val = packed struct {
/// INSTR_MEM0 [0:15]
/// No description
INSTR_MEM0: u16 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Write-only access to instruction memory location 0
pub const INSTR_MEM0 = Register(INSTR_MEM0_val).init(base_address + 0x48);
/// DBG_CFGINFO
const DBG_CFGINFO_val = packed struct {
/// FIFO_DEPTH [0:5]
/// The depth of the state machine TX/RX FIFOs, measured in words.\n
FIFO_DEPTH: u6 = 0,
/// unused [6:7]
_unused6: u2 = 0,
/// SM_COUNT [8:11]
/// The number of state machines this PIO instance is equipped with.
SM_COUNT: u4 = 0,
/// unused [12:15]
_unused12: u4 = 0,
/// IMEM_SIZE [16:21]
/// The size of the instruction memory, measured in units of one instruction
IMEM_SIZE: u6 = 0,
/// unused [22:31]
_unused22: u2 = 0,
_unused24: u8 = 0,
};
/// The PIO hardware has some free parameters that may vary between chip products.\n
pub const DBG_CFGINFO = Register(DBG_CFGINFO_val).init(base_address + 0x44);
/// DBG_PADOE
const DBG_PADOE_val = packed struct {
DBG_PADOE_0: u8 = 0,
DBG_PADOE_1: u8 = 0,
DBG_PADOE_2: u8 = 0,
DBG_PADOE_3: u8 = 0,
};
/// Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs.
pub const DBG_PADOE = Register(DBG_PADOE_val).init(base_address + 0x40);
/// DBG_PADOUT
const DBG_PADOUT_val = packed struct {
DBG_PADOUT_0: u8 = 0,
DBG_PADOUT_1: u8 = 0,
DBG_PADOUT_2: u8 = 0,
DBG_PADOUT_3: u8 = 0,
};
/// Read to sample the pad output values PIO is currently driving to the GPIOs.
pub const DBG_PADOUT = Register(DBG_PADOUT_val).init(base_address + 0x3c);
/// INPUT_SYNC_BYPASS
const INPUT_SYNC_BYPASS_val = packed struct {
INPUT_SYNC_BYPASS_0: u8 = 0,
INPUT_SYNC_BYPASS_1: u8 = 0,
INPUT_SYNC_BYPASS_2: u8 = 0,
INPUT_SYNC_BYPASS_3: u8 = 0,
};
/// There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO.\n
pub const INPUT_SYNC_BYPASS = Register(INPUT_SYNC_BYPASS_val).init(base_address + 0x38);
/// IRQ_FORCE
const IRQ_FORCE_val = packed struct {
/// IRQ_FORCE [0:7]
/// No description
IRQ_FORCE: u8 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines.
pub const IRQ_FORCE = Register(IRQ_FORCE_val).init(base_address + 0x34);
/// IRQ
const IRQ_val = packed struct {
/// IRQ [0:7]
/// No description
IRQ: u8 = 0,
/// unused [8:31]
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag.\n\n
pub const IRQ = Register(IRQ_val).init(base_address + 0x30);
/// RXF3
const RXF3_val = packed struct {
RXF3_0: u8 = 0,
RXF3_1: u8 = 0,
RXF3_2: u8 = 0,
RXF3_3: u8 = 0,
};
/// Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.
pub const RXF3 = Register(RXF3_val).init(base_address + 0x2c);
/// RXF2
const RXF2_val = packed struct {
RXF2_0: u8 = 0,
RXF2_1: u8 = 0,
RXF2_2: u8 = 0,
RXF2_3: u8 = 0,
};
/// Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.
pub const RXF2 = Register(RXF2_val).init(base_address + 0x28);
/// RXF1
const RXF1_val = packed struct {
RXF1_0: u8 = 0,
RXF1_1: u8 = 0,
RXF1_2: u8 = 0,
RXF1_3: u8 = 0,
};
/// Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.
pub const RXF1 = Register(RXF1_val).init(base_address + 0x24);
/// RXF0
const RXF0_val = packed struct {
RXF0_0: u8 = 0,
RXF0_1: u8 = 0,
RXF0_2: u8 = 0,
RXF0_3: u8 = 0,
};
/// Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.
pub const RXF0 = Register(RXF0_val).init(base_address + 0x20);
/// TXF3
const TXF3_val = packed struct {
TXF3_0: u8 = 0,
TXF3_1: u8 = 0,
TXF3_2: u8 = 0,
TXF3_3: u8 = 0,
};
/// Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.
pub const TXF3 = Register(TXF3_val).init(base_address + 0x1c);
/// TXF2
const TXF2_val = packed struct {
TXF2_0: u8 = 0,
TXF2_1: u8 = 0,
TXF2_2: u8 = 0,
TXF2_3: u8 = 0,
};
/// Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.
pub const TXF2 = Register(TXF2_val).init(base_address + 0x18);
/// TXF1
const TXF1_val = packed struct {
TXF1_0: u8 = 0,
TXF1_1: u8 = 0,
TXF1_2: u8 = 0,
TXF1_3: u8 = 0,
};
/// Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.
pub const TXF1 = Register(TXF1_val).init(base_address + 0x14);
/// TXF0
const TXF0_val = packed struct {
TXF0_0: u8 = 0,
TXF0_1: u8 = 0,
TXF0_2: u8 = 0,
TXF0_3: u8 = 0,
};
/// Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.
pub const TXF0 = Register(TXF0_val).init(base_address + 0x10);
/// FLEVEL
const FLEVEL_val = packed struct {
/// TX0 [0:3]
/// No description
TX0: u4 = 0,
/// RX0 [4:7]
/// No description
RX0: u4 = 0,
/// TX1 [8:11]
/// No description
TX1: u4 = 0,
/// RX1 [12:15]
/// No description
RX1: u4 = 0,
/// TX2 [16:19]
/// No description
TX2: u4 = 0,
/// RX2 [20:23]
/// No description
RX2: u4 = 0,
/// TX3 [24:27]
/// No description
TX3: u4 = 0,
/// RX3 [28:31]
/// No description
RX3: u4 = 0,
};
/// FIFO levels
pub const FLEVEL = Register(FLEVEL_val).init(base_address + 0xc);
/// FDEBUG
const FDEBUG_val = packed struct {
/// RXSTALL [0:3]
/// State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear.
RXSTALL: u4 = 0,
/// unused [4:7]
_unused4: u4 = 0,
/// RXUNDER [8:11]
/// RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error.
RXUNDER: u4 = 0,
/// unused [12:15]
_unused12: u4 = 0,
/// TXOVER [16:19]
/// TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor.
TXOVER: u4 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// TXSTALL [24:27]
/// State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear.
TXSTALL: u4 = 0,
/// unused [28:31]
_unused28: u4 = 0,
};
/// FIFO debug register
pub const FDEBUG = Register(FDEBUG_val).init(base_address + 0x8);
/// FSTAT
const FSTAT_val = packed struct {
/// RXFULL [0:3]
/// State machine RX FIFO is full
RXFULL: u4 = 0,
/// unused [4:7]
_unused4: u4 = 0,
/// RXEMPTY [8:11]
/// State machine RX FIFO is empty
RXEMPTY: u4 = 15,
/// unused [12:15]
_unused12: u4 = 0,
/// TXFULL [16:19]
/// State machine TX FIFO is full
TXFULL: u4 = 0,
/// unused [20:23]
_unused20: u4 = 0,
/// TXEMPTY [24:27]
/// State machine TX FIFO is empty
TXEMPTY: u4 = 15,
/// unused [28:31]
_unused28: u4 = 0,
};
/// FIFO status register
pub const FSTAT = Register(FSTAT_val).init(base_address + 0x4);
/// CTRL
const CTRL_val = packed struct {
/// SM_ENABLE [0:3]
/// Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously.
SM_ENABLE: u4 = 0,
/// SM_RESTART [4:7]
/// Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution.\n\n
SM_RESTART: u4 = 0,
/// CLKDIV_RESTART [8:11]
/// Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep.\n\n
CLKDIV_RESTART: u4 = 0,
/// unused [12:31]
_unused12: u4 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// PIO control register
pub const CTRL = Register(CTRL_val).init(base_address + 0x0);
};
/// Single-cycle IO block\n
pub const SIO = struct {
const base_address = 0xd0000000;
/// SPINLOCK31
const SPINLOCK31_val = packed struct {
SPINLOCK31_0: u8 = 0,
SPINLOCK31_1: u8 = 0,
SPINLOCK31_2: u8 = 0,
SPINLOCK31_3: u8 = 0,
};
/// Reading from a spinlock address will:\n
pub const SPINLOCK31 = Register(SPINLOCK31_val).init(base_address + 0x17c);
/// SPINLOCK30
const SPINLOCK30_val = packed struct {
SPINLOCK30_0: u8 = 0,
SPINLOCK30_1: u8 = 0,
SPINLOCK30_2: u8 = 0,
SPINLOCK30_3: u8 = 0,
};
/// Reading from a spinlock address will:\n
pub const SPINLOCK30 = Register(SPINLOCK30_val).init(base_address + 0x178);
/// SPINLOCK29
const SPINLOCK29_val = packed struct {
SPINLOCK29_0: u8 = 0,
SPINLOCK29_1: u8 = 0,
SPINLOCK29_2: u8 = 0,
SPINLOCK29_3: u8 = 0,
};
/// Reading from a spinlock address will:\n
pub const SPINLOCK29 = Register(SPINLOCK29_val).init(base_address + 0x174);
/// SPINLOCK28
const SPINLOCK28_val = packed struct {
SPINLOCK28_0: u8 = 0,
SPINLOCK28_1: u8 = 0,
SPINLOCK28_2: u8 = 0,
SPINLOCK28_3: u8 = 0,
};
/// Reading from a spinlock address will:\n
pub const SPINLOCK28 = Register(SPINLOCK28_val).init(base_address + 0x170);
/// SPINLOCK27
const SPINLOCK27_val = packed struct {
SPINLOCK27_0: u8 = 0,
SPINLOCK27_1: u8 = 0,
SPINLOCK27_2: u8 = 0,
SPINLOCK27_3: u8 = 0,
};
/// Reading from a spinlock address will:\n
pub const SPINLOCK27 = Register(SPINLOCK27_val).init(base_address + 0x16c);
/// SPINLOCK26
const SPINLOCK26_val = packed struct {
SPINLOCK26_0: u8 = 0,
SPINLOCK26_1: u8 = 0,
SPINLOCK26_2: u8 = 0,
SPINLOCK26_3: u8 = 0,
};
/// Reading from a spinlock address will:\n
pub const SPINLOCK26 = Register(SPINLOCK26_val).init(base_address + 0x168);
/// SPINLOCK25
const SPINLOCK25_val = packed struct {
SPINLOCK25_0: u8 = 0,
SPINLOCK25_1: u8 = 0,
SPINLOCK25_2: u8 = 0,
SPINLOCK25_3: u8 = 0,
};
/// Reading from a spinlock address will:\n
pub const SPINLOCK25 = Register(SPINLOCK25_val).init(base_address + 0x164);
/// SPINLOCK24
const SPINLOCK24_val = packed struct {
SPINLOCK24_0: u8 = 0,
SPINLOCK24_1: u8 = 0,
SPINLOCK24_2: u8 = 0,
SPINLOCK24_3: u8 = 0,
};
/// Reading from a spinlock address will:\n
pub const SPINLOCK24 = Register(SPINLOCK24_val).init(base_address + 0x160);
/// SPINLOCK23
const SPINLOCK23_val = packed struct {
SPINLOCK23_0: u8 = 0,
SPINLOCK23_1: u8 = 0,
SPINLOCK23_2: u8 = 0,
SPINLOCK23_3: u8 = 0,
};
/// Reading from a spinlock address will:\n
pub const SPINLOCK23 = Register(SPINLOCK23_val).init(base_address + 0x15c);
/// SPINLOCK22
const SPINLOCK22_val = packed struct {
SPINLOCK22_0: u8 = 0,
SPINLOCK22_1: u8 = 0,
SPINLOCK22_2: u8 = 0,
SPINLOCK22_3: u8 = 0,
};
/// Reading from a spinlock address will:\n
pub const SPINLOCK22 = Register(SPINLOCK22_val).init(base_address + 0x158);
/// SPINLOCK21
const SPINLOCK21_val = packed struct {
SPINLOCK21_0: u8 = 0,
SPINLOCK21_1: u8 = 0,
SPINLOCK21_2: u8 = 0,
SPINLOCK21_3: u8 = 0,
};
/// Reading from a spinlock address will:\n
pub const SPINLOCK21 = Register(SPINLOCK21_val).init(base_address + 0x154);
/// SPINLOCK20
const SPINLOCK20_val = packed struct {
SPINLOCK20_0: u8 = 0,
SPINLOCK20_1: u8 = 0,
SPINLOCK20_2: u8 = 0,
SPINLOCK20_3: u8 = 0,
};
/// Reading from a spinlock address will:\n
pub const SPINLOCK20 = Register(SPINLOCK20_val).init(base_address + 0x150);
/// SPINLOCK19
const SPINLOCK19_val = packed struct {
SPINLOCK19_0: u8 = 0,
SPINLOCK19_1: u8 = 0,
SPINLOCK19_2: u8 = 0,
SPINLOCK19_3: u8 = 0,
};
/// Reading from a spinlock address will:\n
pub const SPINLOCK19 = Register(SPINLOCK19_val).init(base_address + 0x14c);
/// SPINLOCK18
const SPINLOCK18_val = packed struct {
SPINLOCK18_0: u8 = 0,
SPINLOCK18_1: u8 = 0,
SPINLOCK18_2: u8 = 0,
SPINLOCK18_3: u8 = 0,
};
/// Reading from a spinlock address will:\n
pub const SPINLOCK18 = Register(SPINLOCK18_val).init(base_address + 0x148);
/// SPINLOCK17
const SPINLOCK17_val = packed struct {
SPINLOCK17_0: u8 = 0,
SPINLOCK17_1: u8 = 0,
SPINLOCK17_2: u8 = 0,
SPINLOCK17_3: u8 = 0,
};
/// Reading from a spinlock address will:\n
pub const SPINLOCK17 = Register(SPINLOCK17_val).init(base_address + 0x144);
/// SPINLOCK16
const SPINLOCK16_val = packed struct {
SPINLOCK16_0: u8 = 0,
SPINLOCK16_1: u8 = 0,
SPINLOCK16_2: u8 = 0,
SPINLOCK16_3: u8 = 0,
};
/// Reading from a spinlock address will:\n
pub const SPINLOCK16 = Register(SPINLOCK16_val).init(base_address + 0x140);
/// SPINLOCK15
const SPINLOCK15_val = packed struct {
SPINLOCK15_0: u8 = 0,
SPINLOCK15_1: u8 = 0,
SPINLOCK15_2: u8 = 0,
SPINLOCK15_3: u8 = 0,
};
/// Reading from a spinlock address will:\n
pub const SPINLOCK15 = Register(SPINLOCK15_val).init(base_address + 0x13c);
/// SPINLOCK14
const SPINLOCK14_val = packed struct {
SPINLOCK14_0: u8 = 0,
SPINLOCK14_1: u8 = 0,
SPINLOCK14_2: u8 = 0,
SPINLOCK14_3: u8 = 0,
};
/// Reading from a spinlock address will:\n
pub const SPINLOCK14 = Register(SPINLOCK14_val).init(base_address + 0x138);
/// SPINLOCK13
const SPINLOCK13_val = packed struct {
SPINLOCK13_0: u8 = 0,
SPINLOCK13_1: u8 = 0,
SPINLOCK13_2: u8 = 0,
SPINLOCK13_3: u8 = 0,
};
/// Reading from a spinlock address will:\n
pub const SPINLOCK13 = Register(SPINLOCK13_val).init(base_address + 0x134);
/// SPINLOCK12
const SPINLOCK12_val = packed struct {
SPINLOCK12_0: u8 = 0,
SPINLOCK12_1: u8 = 0,
SPINLOCK12_2: u8 = 0,
SPINLOCK12_3: u8 = 0,
};
/// Reading from a spinlock address will:\n
pub const SPINLOCK12 = Register(SPINLOCK12_val).init(base_address + 0x130);
/// SPINLOCK11
const SPINLOCK11_val = packed struct {
SPINLOCK11_0: u8 = 0,
SPINLOCK11_1: u8 = 0,
SPINLOCK11_2: u8 = 0,
SPINLOCK11_3: u8 = 0,
};
/// Reading from a spinlock address will:\n
pub const SPINLOCK11 = Register(SPINLOCK11_val).init(base_address + 0x12c);
/// SPINLOCK10
const SPINLOCK10_val = packed struct {
SPINLOCK10_0: u8 = 0,
SPINLOCK10_1: u8 = 0,
SPINLOCK10_2: u8 = 0,
SPINLOCK10_3: u8 = 0,
};
/// Reading from a spinlock address will:\n
pub const SPINLOCK10 = Register(SPINLOCK10_val).init(base_address + 0x128);
/// SPINLOCK9
const SPINLOCK9_val = packed struct {
SPINLOCK9_0: u8 = 0,
SPINLOCK9_1: u8 = 0,
SPINLOCK9_2: u8 = 0,
SPINLOCK9_3: u8 = 0,
};
/// Reading from a spinlock address will:\n
pub const SPINLOCK9 = Register(SPINLOCK9_val).init(base_address + 0x124);
/// SPINLOCK8
const SPINLOCK8_val = packed struct {
SPINLOCK8_0: u8 = 0,
SPINLOCK8_1: u8 = 0,
SPINLOCK8_2: u8 = 0,
SPINLOCK8_3: u8 = 0,
};
/// Reading from a spinlock address will:\n
pub const SPINLOCK8 = Register(SPINLOCK8_val).init(base_address + 0x120);
/// SPINLOCK7
const SPINLOCK7_val = packed struct {
SPINLOCK7_0: u8 = 0,
SPINLOCK7_1: u8 = 0,
SPINLOCK7_2: u8 = 0,
SPINLOCK7_3: u8 = 0,
};
/// Reading from a spinlock address will:\n
pub const SPINLOCK7 = Register(SPINLOCK7_val).init(base_address + 0x11c);
/// SPINLOCK6
const SPINLOCK6_val = packed struct {
SPINLOCK6_0: u8 = 0,
SPINLOCK6_1: u8 = 0,
SPINLOCK6_2: u8 = 0,
SPINLOCK6_3: u8 = 0,
};
/// Reading from a spinlock address will:\n
pub const SPINLOCK6 = Register(SPINLOCK6_val).init(base_address + 0x118);
/// SPINLOCK5
const SPINLOCK5_val = packed struct {
SPINLOCK5_0: u8 = 0,
SPINLOCK5_1: u8 = 0,
SPINLOCK5_2: u8 = 0,
SPINLOCK5_3: u8 = 0,
};
/// Reading from a spinlock address will:\n
pub const SPINLOCK5 = Register(SPINLOCK5_val).init(base_address + 0x114);
/// SPINLOCK4
const SPINLOCK4_val = packed struct {
SPINLOCK4_0: u8 = 0,
SPINLOCK4_1: u8 = 0,
SPINLOCK4_2: u8 = 0,
SPINLOCK4_3: u8 = 0,
};
/// Reading from a spinlock address will:\n
pub const SPINLOCK4 = Register(SPINLOCK4_val).init(base_address + 0x110);
/// SPINLOCK3
const SPINLOCK3_val = packed struct {
SPINLOCK3_0: u8 = 0,
SPINLOCK3_1: u8 = 0,
SPINLOCK3_2: u8 = 0,
SPINLOCK3_3: u8 = 0,
};
/// Reading from a spinlock address will:\n
pub const SPINLOCK3 = Register(SPINLOCK3_val).init(base_address + 0x10c);
/// SPINLOCK2
const SPINLOCK2_val = packed struct {
SPINLOCK2_0: u8 = 0,
SPINLOCK2_1: u8 = 0,
SPINLOCK2_2: u8 = 0,
SPINLOCK2_3: u8 = 0,
};
/// Reading from a spinlock address will:\n
pub const SPINLOCK2 = Register(SPINLOCK2_val).init(base_address + 0x108);
/// SPINLOCK1
const SPINLOCK1_val = packed struct {
SPINLOCK1_0: u8 = 0,
SPINLOCK1_1: u8 = 0,
SPINLOCK1_2: u8 = 0,
SPINLOCK1_3: u8 = 0,
};
/// Reading from a spinlock address will:\n
pub const SPINLOCK1 = Register(SPINLOCK1_val).init(base_address + 0x104);
/// SPINLOCK0
const SPINLOCK0_val = packed struct {
SPINLOCK0_0: u8 = 0,
SPINLOCK0_1: u8 = 0,
SPINLOCK0_2: u8 = 0,
SPINLOCK0_3: u8 = 0,
};
/// Reading from a spinlock address will:\n
pub const SPINLOCK0 = Register(SPINLOCK0_val).init(base_address + 0x100);
/// INTERP1_BASE_1AND0
const INTERP1_BASE_1AND0_val = packed struct {
INTERP1_BASE_1AND0_0: u8 = 0,
INTERP1_BASE_1AND0_1: u8 = 0,
INTERP1_BASE_1AND0_2: u8 = 0,
INTERP1_BASE_1AND0_3: u8 = 0,
};
/// On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.\n
pub const INTERP1_BASE_1AND0 = Register(INTERP1_BASE_1AND0_val).init(base_address + 0xfc);
/// INTERP1_ACCUM1_ADD
const INTERP1_ACCUM1_ADD_val = packed struct {
/// INTERP1_ACCUM1_ADD [0:23]
/// No description
INTERP1_ACCUM1_ADD: u24 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Values written here are atomically added to ACCUM1\n
pub const INTERP1_ACCUM1_ADD = Register(INTERP1_ACCUM1_ADD_val).init(base_address + 0xf8);
/// INTERP1_ACCUM0_ADD
const INTERP1_ACCUM0_ADD_val = packed struct {
/// INTERP1_ACCUM0_ADD [0:23]
/// No description
INTERP1_ACCUM0_ADD: u24 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Values written here are atomically added to ACCUM0\n
pub const INTERP1_ACCUM0_ADD = Register(INTERP1_ACCUM0_ADD_val).init(base_address + 0xf4);
/// INTERP1_CTRL_LANE1
const INTERP1_CTRL_LANE1_val = packed struct {
/// SHIFT [0:4]
/// Logical right-shift applied to accumulator before masking
SHIFT: u5 = 0,
/// MASK_LSB [5:9]
/// The least-significant bit allowed to pass by the mask (inclusive)
MASK_LSB: u5 = 0,
/// MASK_MSB [10:14]
/// The most-significant bit allowed to pass by the mask (inclusive)\n
MASK_MSB: u5 = 0,
/// SIGNED [15:15]
/// If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n
SIGNED: u1 = 0,
/// CROSS_INPUT [16:16]
/// If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n
CROSS_INPUT: u1 = 0,
/// CROSS_RESULT [17:17]
/// If 1, feed the opposite lane's result into this lane's accumulator on POP.
CROSS_RESULT: u1 = 0,
/// ADD_RAW [18:18]
/// If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.
ADD_RAW: u1 = 0,
/// FORCE_MSB [19:20]
/// ORed into bits 29:28 of the lane result presented to the processor on the bus.\n
FORCE_MSB: u2 = 0,
/// unused [21:31]
_unused21: u3 = 0,
_unused24: u8 = 0,
};
/// Control register for lane 1
pub const INTERP1_CTRL_LANE1 = Register(INTERP1_CTRL_LANE1_val).init(base_address + 0xf0);
/// INTERP1_CTRL_LANE0
const INTERP1_CTRL_LANE0_val = packed struct {
/// SHIFT [0:4]
/// Logical right-shift applied to accumulator before masking
SHIFT: u5 = 0,
/// MASK_LSB [5:9]
/// The least-significant bit allowed to pass by the mask (inclusive)
MASK_LSB: u5 = 0,
/// MASK_MSB [10:14]
/// The most-significant bit allowed to pass by the mask (inclusive)\n
MASK_MSB: u5 = 0,
/// SIGNED [15:15]
/// If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n
SIGNED: u1 = 0,
/// CROSS_INPUT [16:16]
/// If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n
CROSS_INPUT: u1 = 0,
/// CROSS_RESULT [17:17]
/// If 1, feed the opposite lane's result into this lane's accumulator on POP.
CROSS_RESULT: u1 = 0,
/// ADD_RAW [18:18]
/// If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.
ADD_RAW: u1 = 0,
/// FORCE_MSB [19:20]
/// ORed into bits 29:28 of the lane result presented to the processor on the bus.\n
FORCE_MSB: u2 = 0,
/// unused [21:21]
_unused21: u1 = 0,
/// CLAMP [22:22]
/// Only present on INTERP1 on each core. If CLAMP mode is enabled:\n
CLAMP: u1 = 0,
/// OVERF0 [23:23]
/// Indicates if any masked-off MSBs in ACCUM0 are set.
OVERF0: u1 = 0,
/// OVERF1 [24:24]
/// Indicates if any masked-off MSBs in ACCUM1 are set.
OVERF1: u1 = 0,
/// OVERF [25:25]
/// Set if either OVERF0 or OVERF1 is set.
OVERF: u1 = 0,
/// unused [26:31]
_unused26: u6 = 0,
};
/// Control register for lane 0
pub const INTERP1_CTRL_LANE0 = Register(INTERP1_CTRL_LANE0_val).init(base_address + 0xec);
/// INTERP1_PEEK_FULL
const INTERP1_PEEK_FULL_val = packed struct {
INTERP1_PEEK_FULL_0: u8 = 0,
INTERP1_PEEK_FULL_1: u8 = 0,
INTERP1_PEEK_FULL_2: u8 = 0,
INTERP1_PEEK_FULL_3: u8 = 0,
};
/// Read FULL result, without altering any internal state (PEEK).
pub const INTERP1_PEEK_FULL = Register(INTERP1_PEEK_FULL_val).init(base_address + 0xe8);
/// INTERP1_PEEK_LANE1
const INTERP1_PEEK_LANE1_val = packed struct {
INTERP1_PEEK_LANE1_0: u8 = 0,
INTERP1_PEEK_LANE1_1: u8 = 0,
INTERP1_PEEK_LANE1_2: u8 = 0,
INTERP1_PEEK_LANE1_3: u8 = 0,
};
/// Read LANE1 result, without altering any internal state (PEEK).
pub const INTERP1_PEEK_LANE1 = Register(INTERP1_PEEK_LANE1_val).init(base_address + 0xe4);
/// INTERP1_PEEK_LANE0
const INTERP1_PEEK_LANE0_val = packed struct {
INTERP1_PEEK_LANE0_0: u8 = 0,
INTERP1_PEEK_LANE0_1: u8 = 0,
INTERP1_PEEK_LANE0_2: u8 = 0,
INTERP1_PEEK_LANE0_3: u8 = 0,
};
/// Read LANE0 result, without altering any internal state (PEEK).
pub const INTERP1_PEEK_LANE0 = Register(INTERP1_PEEK_LANE0_val).init(base_address + 0xe0);
/// INTERP1_POP_FULL
const INTERP1_POP_FULL_val = packed struct {
INTERP1_POP_FULL_0: u8 = 0,
INTERP1_POP_FULL_1: u8 = 0,
INTERP1_POP_FULL_2: u8 = 0,
INTERP1_POP_FULL_3: u8 = 0,
};
/// Read FULL result, and simultaneously write lane results to both accumulators (POP).
pub const INTERP1_POP_FULL = Register(INTERP1_POP_FULL_val).init(base_address + 0xdc);
/// INTERP1_POP_LANE1
const INTERP1_POP_LANE1_val = packed struct {
INTERP1_POP_LANE1_0: u8 = 0,
INTERP1_POP_LANE1_1: u8 = 0,
INTERP1_POP_LANE1_2: u8 = 0,
INTERP1_POP_LANE1_3: u8 = 0,
};
/// Read LANE1 result, and simultaneously write lane results to both accumulators (POP).
pub const INTERP1_POP_LANE1 = Register(INTERP1_POP_LANE1_val).init(base_address + 0xd8);
/// INTERP1_POP_LANE0
const INTERP1_POP_LANE0_val = packed struct {
INTERP1_POP_LANE0_0: u8 = 0,
INTERP1_POP_LANE0_1: u8 = 0,
INTERP1_POP_LANE0_2: u8 = 0,
INTERP1_POP_LANE0_3: u8 = 0,
};
/// Read LANE0 result, and simultaneously write lane results to both accumulators (POP).
pub const INTERP1_POP_LANE0 = Register(INTERP1_POP_LANE0_val).init(base_address + 0xd4);
/// INTERP1_BASE2
const INTERP1_BASE2_val = packed struct {
INTERP1_BASE2_0: u8 = 0,
INTERP1_BASE2_1: u8 = 0,
INTERP1_BASE2_2: u8 = 0,
INTERP1_BASE2_3: u8 = 0,
};
/// Read/write access to BASE2 register.
pub const INTERP1_BASE2 = Register(INTERP1_BASE2_val).init(base_address + 0xd0);
/// INTERP1_BASE1
const INTERP1_BASE1_val = packed struct {
INTERP1_BASE1_0: u8 = 0,
INTERP1_BASE1_1: u8 = 0,
INTERP1_BASE1_2: u8 = 0,
INTERP1_BASE1_3: u8 = 0,
};
/// Read/write access to BASE1 register.
pub const INTERP1_BASE1 = Register(INTERP1_BASE1_val).init(base_address + 0xcc);
/// INTERP1_BASE0
const INTERP1_BASE0_val = packed struct {
INTERP1_BASE0_0: u8 = 0,
INTERP1_BASE0_1: u8 = 0,
INTERP1_BASE0_2: u8 = 0,
INTERP1_BASE0_3: u8 = 0,
};
/// Read/write access to BASE0 register.
pub const INTERP1_BASE0 = Register(INTERP1_BASE0_val).init(base_address + 0xc8);
/// INTERP1_ACCUM1
const INTERP1_ACCUM1_val = packed struct {
INTERP1_ACCUM1_0: u8 = 0,
INTERP1_ACCUM1_1: u8 = 0,
INTERP1_ACCUM1_2: u8 = 0,
INTERP1_ACCUM1_3: u8 = 0,
};
/// Read/write access to accumulator 1
pub const INTERP1_ACCUM1 = Register(INTERP1_ACCUM1_val).init(base_address + 0xc4);
/// INTERP1_ACCUM0
const INTERP1_ACCUM0_val = packed struct {
INTERP1_ACCUM0_0: u8 = 0,
INTERP1_ACCUM0_1: u8 = 0,
INTERP1_ACCUM0_2: u8 = 0,
INTERP1_ACCUM0_3: u8 = 0,
};
/// Read/write access to accumulator 0
pub const INTERP1_ACCUM0 = Register(INTERP1_ACCUM0_val).init(base_address + 0xc0);
/// INTERP0_BASE_1AND0
const INTERP0_BASE_1AND0_val = packed struct {
INTERP0_BASE_1AND0_0: u8 = 0,
INTERP0_BASE_1AND0_1: u8 = 0,
INTERP0_BASE_1AND0_2: u8 = 0,
INTERP0_BASE_1AND0_3: u8 = 0,
};
/// On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.\n
pub const INTERP0_BASE_1AND0 = Register(INTERP0_BASE_1AND0_val).init(base_address + 0xbc);
/// INTERP0_ACCUM1_ADD
const INTERP0_ACCUM1_ADD_val = packed struct {
/// INTERP0_ACCUM1_ADD [0:23]
/// No description
INTERP0_ACCUM1_ADD: u24 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Values written here are atomically added to ACCUM1\n
pub const INTERP0_ACCUM1_ADD = Register(INTERP0_ACCUM1_ADD_val).init(base_address + 0xb8);
/// INTERP0_ACCUM0_ADD
const INTERP0_ACCUM0_ADD_val = packed struct {
/// INTERP0_ACCUM0_ADD [0:23]
/// No description
INTERP0_ACCUM0_ADD: u24 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Values written here are atomically added to ACCUM0\n
pub const INTERP0_ACCUM0_ADD = Register(INTERP0_ACCUM0_ADD_val).init(base_address + 0xb4);
/// INTERP0_CTRL_LANE1
const INTERP0_CTRL_LANE1_val = packed struct {
/// SHIFT [0:4]
/// Logical right-shift applied to accumulator before masking
SHIFT: u5 = 0,
/// MASK_LSB [5:9]
/// The least-significant bit allowed to pass by the mask (inclusive)
MASK_LSB: u5 = 0,
/// MASK_MSB [10:14]
/// The most-significant bit allowed to pass by the mask (inclusive)\n
MASK_MSB: u5 = 0,
/// SIGNED [15:15]
/// If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n
SIGNED: u1 = 0,
/// CROSS_INPUT [16:16]
/// If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n
CROSS_INPUT: u1 = 0,
/// CROSS_RESULT [17:17]
/// If 1, feed the opposite lane's result into this lane's accumulator on POP.
CROSS_RESULT: u1 = 0,
/// ADD_RAW [18:18]
/// If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.
ADD_RAW: u1 = 0,
/// FORCE_MSB [19:20]
/// ORed into bits 29:28 of the lane result presented to the processor on the bus.\n
FORCE_MSB: u2 = 0,
/// unused [21:31]
_unused21: u3 = 0,
_unused24: u8 = 0,
};
/// Control register for lane 1
pub const INTERP0_CTRL_LANE1 = Register(INTERP0_CTRL_LANE1_val).init(base_address + 0xb0);
/// INTERP0_CTRL_LANE0
const INTERP0_CTRL_LANE0_val = packed struct {
/// SHIFT [0:4]
/// Logical right-shift applied to accumulator before masking
SHIFT: u5 = 0,
/// MASK_LSB [5:9]
/// The least-significant bit allowed to pass by the mask (inclusive)
MASK_LSB: u5 = 0,
/// MASK_MSB [10:14]
/// The most-significant bit allowed to pass by the mask (inclusive)\n
MASK_MSB: u5 = 0,
/// SIGNED [15:15]
/// If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n
SIGNED: u1 = 0,
/// CROSS_INPUT [16:16]
/// If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n
CROSS_INPUT: u1 = 0,
/// CROSS_RESULT [17:17]
/// If 1, feed the opposite lane's result into this lane's accumulator on POP.
CROSS_RESULT: u1 = 0,
/// ADD_RAW [18:18]
/// If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.
ADD_RAW: u1 = 0,
/// FORCE_MSB [19:20]
/// ORed into bits 29:28 of the lane result presented to the processor on the bus.\n
FORCE_MSB: u2 = 0,
/// BLEND [21:21]
/// Only present on INTERP0 on each core. If BLEND mode is enabled:\n
BLEND: u1 = 0,
/// unused [22:22]
_unused22: u1 = 0,
/// OVERF0 [23:23]
/// Indicates if any masked-off MSBs in ACCUM0 are set.
OVERF0: u1 = 0,
/// OVERF1 [24:24]
/// Indicates if any masked-off MSBs in ACCUM1 are set.
OVERF1: u1 = 0,
/// OVERF [25:25]
/// Set if either OVERF0 or OVERF1 is set.
OVERF: u1 = 0,
/// unused [26:31]
_unused26: u6 = 0,
};
/// Control register for lane 0
pub const INTERP0_CTRL_LANE0 = Register(INTERP0_CTRL_LANE0_val).init(base_address + 0xac);
/// INTERP0_PEEK_FULL
const INTERP0_PEEK_FULL_val = packed struct {
INTERP0_PEEK_FULL_0: u8 = 0,
INTERP0_PEEK_FULL_1: u8 = 0,
INTERP0_PEEK_FULL_2: u8 = 0,
INTERP0_PEEK_FULL_3: u8 = 0,
};
/// Read FULL result, without altering any internal state (PEEK).
pub const INTERP0_PEEK_FULL = Register(INTERP0_PEEK_FULL_val).init(base_address + 0xa8);
/// INTERP0_PEEK_LANE1
const INTERP0_PEEK_LANE1_val = packed struct {
INTERP0_PEEK_LANE1_0: u8 = 0,
INTERP0_PEEK_LANE1_1: u8 = 0,
INTERP0_PEEK_LANE1_2: u8 = 0,
INTERP0_PEEK_LANE1_3: u8 = 0,
};
/// Read LANE1 result, without altering any internal state (PEEK).
pub const INTERP0_PEEK_LANE1 = Register(INTERP0_PEEK_LANE1_val).init(base_address + 0xa4);
/// INTERP0_PEEK_LANE0
const INTERP0_PEEK_LANE0_val = packed struct {
INTERP0_PEEK_LANE0_0: u8 = 0,
INTERP0_PEEK_LANE0_1: u8 = 0,
INTERP0_PEEK_LANE0_2: u8 = 0,
INTERP0_PEEK_LANE0_3: u8 = 0,
};
/// Read LANE0 result, without altering any internal state (PEEK).
pub const INTERP0_PEEK_LANE0 = Register(INTERP0_PEEK_LANE0_val).init(base_address + 0xa0);
/// INTERP0_POP_FULL
const INTERP0_POP_FULL_val = packed struct {
INTERP0_POP_FULL_0: u8 = 0,
INTERP0_POP_FULL_1: u8 = 0,
INTERP0_POP_FULL_2: u8 = 0,
INTERP0_POP_FULL_3: u8 = 0,
};
/// Read FULL result, and simultaneously write lane results to both accumulators (POP).
pub const INTERP0_POP_FULL = Register(INTERP0_POP_FULL_val).init(base_address + 0x9c);
/// INTERP0_POP_LANE1
const INTERP0_POP_LANE1_val = packed struct {
INTERP0_POP_LANE1_0: u8 = 0,
INTERP0_POP_LANE1_1: u8 = 0,
INTERP0_POP_LANE1_2: u8 = 0,
INTERP0_POP_LANE1_3: u8 = 0,
};
/// Read LANE1 result, and simultaneously write lane results to both accumulators (POP).
pub const INTERP0_POP_LANE1 = Register(INTERP0_POP_LANE1_val).init(base_address + 0x98);
/// INTERP0_POP_LANE0
const INTERP0_POP_LANE0_val = packed struct {
INTERP0_POP_LANE0_0: u8 = 0,
INTERP0_POP_LANE0_1: u8 = 0,
INTERP0_POP_LANE0_2: u8 = 0,
INTERP0_POP_LANE0_3: u8 = 0,
};
/// Read LANE0 result, and simultaneously write lane results to both accumulators (POP).
pub const INTERP0_POP_LANE0 = Register(INTERP0_POP_LANE0_val).init(base_address + 0x94);
/// INTERP0_BASE2
const INTERP0_BASE2_val = packed struct {
INTERP0_BASE2_0: u8 = 0,
INTERP0_BASE2_1: u8 = 0,
INTERP0_BASE2_2: u8 = 0,
INTERP0_BASE2_3: u8 = 0,
};
/// Read/write access to BASE2 register.
pub const INTERP0_BASE2 = Register(INTERP0_BASE2_val).init(base_address + 0x90);
/// INTERP0_BASE1
const INTERP0_BASE1_val = packed struct {
INTERP0_BASE1_0: u8 = 0,
INTERP0_BASE1_1: u8 = 0,
INTERP0_BASE1_2: u8 = 0,
INTERP0_BASE1_3: u8 = 0,
};
/// Read/write access to BASE1 register.
pub const INTERP0_BASE1 = Register(INTERP0_BASE1_val).init(base_address + 0x8c);
/// INTERP0_BASE0
const INTERP0_BASE0_val = packed struct {
INTERP0_BASE0_0: u8 = 0,
INTERP0_BASE0_1: u8 = 0,
INTERP0_BASE0_2: u8 = 0,
INTERP0_BASE0_3: u8 = 0,
};
/// Read/write access to BASE0 register.
pub const INTERP0_BASE0 = Register(INTERP0_BASE0_val).init(base_address + 0x88);
/// INTERP0_ACCUM1
const INTERP0_ACCUM1_val = packed struct {
INTERP0_ACCUM1_0: u8 = 0,
INTERP0_ACCUM1_1: u8 = 0,
INTERP0_ACCUM1_2: u8 = 0,
INTERP0_ACCUM1_3: u8 = 0,
};
/// Read/write access to accumulator 1
pub const INTERP0_ACCUM1 = Register(INTERP0_ACCUM1_val).init(base_address + 0x84);
/// INTERP0_ACCUM0
const INTERP0_ACCUM0_val = packed struct {
INTERP0_ACCUM0_0: u8 = 0,
INTERP0_ACCUM0_1: u8 = 0,
INTERP0_ACCUM0_2: u8 = 0,
INTERP0_ACCUM0_3: u8 = 0,
};
/// Read/write access to accumulator 0
pub const INTERP0_ACCUM0 = Register(INTERP0_ACCUM0_val).init(base_address + 0x80);
/// DIV_CSR
const DIV_CSR_val = packed struct {
/// READY [0:0]
/// Reads as 0 when a calculation is in progress, 1 otherwise.\n
READY: u1 = 1,
/// DIRTY [1:1]
/// Changes to 1 when any register is written, and back to 0 when QUOTIENT is read.\n
DIRTY: u1 = 0,
/// unused [2:31]
_unused2: u6 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Control and status register for divider.
pub const DIV_CSR = Register(DIV_CSR_val).init(base_address + 0x78);
/// DIV_REMAINDER
const DIV_REMAINDER_val = packed struct {
DIV_REMAINDER_0: u8 = 0,
DIV_REMAINDER_1: u8 = 0,
DIV_REMAINDER_2: u8 = 0,
DIV_REMAINDER_3: u8 = 0,
};
/// Divider result remainder\n
pub const DIV_REMAINDER = Register(DIV_REMAINDER_val).init(base_address + 0x74);
/// DIV_QUOTIENT
const DIV_QUOTIENT_val = packed struct {
DIV_QUOTIENT_0: u8 = 0,
DIV_QUOTIENT_1: u8 = 0,
DIV_QUOTIENT_2: u8 = 0,
DIV_QUOTIENT_3: u8 = 0,
};
/// Divider result quotient\n
pub const DIV_QUOTIENT = Register(DIV_QUOTIENT_val).init(base_address + 0x70);
/// DIV_SDIVISOR
const DIV_SDIVISOR_val = packed struct {
DIV_SDIVISOR_0: u8 = 0,
DIV_SDIVISOR_1: u8 = 0,
DIV_SDIVISOR_2: u8 = 0,
DIV_SDIVISOR_3: u8 = 0,
};
/// Divider signed divisor\n
pub const DIV_SDIVISOR = Register(DIV_SDIVISOR_val).init(base_address + 0x6c);
/// DIV_SDIVIDEND
const DIV_SDIVIDEND_val = packed struct {
DIV_SDIVIDEND_0: u8 = 0,
DIV_SDIVIDEND_1: u8 = 0,
DIV_SDIVIDEND_2: u8 = 0,
DIV_SDIVIDEND_3: u8 = 0,
};
/// Divider signed dividend\n
pub const DIV_SDIVIDEND = Register(DIV_SDIVIDEND_val).init(base_address + 0x68);
/// DIV_UDIVISOR
const DIV_UDIVISOR_val = packed struct {
DIV_UDIVISOR_0: u8 = 0,
DIV_UDIVISOR_1: u8 = 0,
DIV_UDIVISOR_2: u8 = 0,
DIV_UDIVISOR_3: u8 = 0,
};
/// Divider unsigned divisor\n
pub const DIV_UDIVISOR = Register(DIV_UDIVISOR_val).init(base_address + 0x64);
/// DIV_UDIVIDEND
const DIV_UDIVIDEND_val = packed struct {
DIV_UDIVIDEND_0: u8 = 0,
DIV_UDIVIDEND_1: u8 = 0,
DIV_UDIVIDEND_2: u8 = 0,
DIV_UDIVIDEND_3: u8 = 0,
};
/// Divider unsigned dividend\n
pub const DIV_UDIVIDEND = Register(DIV_UDIVIDEND_val).init(base_address + 0x60);
/// SPINLOCK_ST
const SPINLOCK_ST_val = packed struct {
SPINLOCK_ST_0: u8 = 0,
SPINLOCK_ST_1: u8 = 0,
SPINLOCK_ST_2: u8 = 0,
SPINLOCK_ST_3: u8 = 0,
};
/// Spinlock state\n
pub const SPINLOCK_ST = Register(SPINLOCK_ST_val).init(base_address + 0x5c);
/// FIFO_RD
const FIFO_RD_val = packed struct {
FIFO_RD_0: u8 = 0,
FIFO_RD_1: u8 = 0,
FIFO_RD_2: u8 = 0,
FIFO_RD_3: u8 = 0,
};
/// Read access to this core's RX FIFO
pub const FIFO_RD = Register(FIFO_RD_val).init(base_address + 0x58);
/// FIFO_WR
const FIFO_WR_val = packed struct {
FIFO_WR_0: u8 = 0,
FIFO_WR_1: u8 = 0,
FIFO_WR_2: u8 = 0,
FIFO_WR_3: u8 = 0,
};
/// Write access to this core's TX FIFO
pub const FIFO_WR = Register(FIFO_WR_val).init(base_address + 0x54);
/// FIFO_ST
const FIFO_ST_val = packed struct {
/// VLD [0:0]
/// Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid)
VLD: u1 = 0,
/// RDY [1:1]
/// Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data)
RDY: u1 = 1,
/// WOF [2:2]
/// Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO.
WOF: u1 = 0,
/// ROE [3:3]
/// Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO.
ROE: u1 = 0,
/// unused [4:31]
_unused4: u4 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Status register for inter-core FIFOs (mailboxes).\n
pub const FIFO_ST = Register(FIFO_ST_val).init(base_address + 0x50);
/// GPIO_HI_OE_XOR
const GPIO_HI_OE_XOR_val = packed struct {
/// GPIO_HI_OE_XOR [0:5]
/// Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata`
GPIO_HI_OE_XOR: u6 = 0,
/// unused [6:31]
_unused6: u2 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// QSPI output enable XOR
pub const GPIO_HI_OE_XOR = Register(GPIO_HI_OE_XOR_val).init(base_address + 0x4c);
/// GPIO_HI_OE_CLR
const GPIO_HI_OE_CLR_val = packed struct {
/// GPIO_HI_OE_CLR [0:5]
/// Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata`
GPIO_HI_OE_CLR: u6 = 0,
/// unused [6:31]
_unused6: u2 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// QSPI output enable clear
pub const GPIO_HI_OE_CLR = Register(GPIO_HI_OE_CLR_val).init(base_address + 0x48);
/// GPIO_HI_OE_SET
const GPIO_HI_OE_SET_val = packed struct {
/// GPIO_HI_OE_SET [0:5]
/// Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata`
GPIO_HI_OE_SET: u6 = 0,
/// unused [6:31]
_unused6: u2 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// QSPI output enable set
pub const GPIO_HI_OE_SET = Register(GPIO_HI_OE_SET_val).init(base_address + 0x44);
/// GPIO_HI_OE
const GPIO_HI_OE_val = packed struct {
/// GPIO_HI_OE [0:5]
/// Set output enable (1/0 -> output/input) for QSPI IO0...5.\n
GPIO_HI_OE: u6 = 0,
/// unused [6:31]
_unused6: u2 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// QSPI output enable
pub const GPIO_HI_OE = Register(GPIO_HI_OE_val).init(base_address + 0x40);
/// GPIO_HI_OUT_XOR
const GPIO_HI_OUT_XOR_val = packed struct {
/// GPIO_HI_OUT_XOR [0:5]
/// Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata`
GPIO_HI_OUT_XOR: u6 = 0,
/// unused [6:31]
_unused6: u2 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// QSPI output value XOR
pub const GPIO_HI_OUT_XOR = Register(GPIO_HI_OUT_XOR_val).init(base_address + 0x3c);
/// GPIO_HI_OUT_CLR
const GPIO_HI_OUT_CLR_val = packed struct {
/// GPIO_HI_OUT_CLR [0:5]
/// Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata`
GPIO_HI_OUT_CLR: u6 = 0,
/// unused [6:31]
_unused6: u2 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// QSPI output value clear
pub const GPIO_HI_OUT_CLR = Register(GPIO_HI_OUT_CLR_val).init(base_address + 0x38);
/// GPIO_HI_OUT_SET
const GPIO_HI_OUT_SET_val = packed struct {
/// GPIO_HI_OUT_SET [0:5]
/// Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata`
GPIO_HI_OUT_SET: u6 = 0,
/// unused [6:31]
_unused6: u2 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// QSPI output value set
pub const GPIO_HI_OUT_SET = Register(GPIO_HI_OUT_SET_val).init(base_address + 0x34);
/// GPIO_HI_OUT
const GPIO_HI_OUT_val = packed struct {
/// GPIO_HI_OUT [0:5]
/// Set output level (1/0 -> high/low) for QSPI IO0...5.\n
GPIO_HI_OUT: u6 = 0,
/// unused [6:31]
_unused6: u2 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// QSPI output value
pub const GPIO_HI_OUT = Register(GPIO_HI_OUT_val).init(base_address + 0x30);
/// GPIO_OE_XOR
const GPIO_OE_XOR_val = packed struct {
/// GPIO_OE_XOR [0:29]
/// Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata`
GPIO_OE_XOR: u30 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO output enable XOR
pub const GPIO_OE_XOR = Register(GPIO_OE_XOR_val).init(base_address + 0x2c);
/// GPIO_OE_CLR
const GPIO_OE_CLR_val = packed struct {
/// GPIO_OE_CLR [0:29]
/// Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= ~wdata`
GPIO_OE_CLR: u30 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO output enable clear
pub const GPIO_OE_CLR = Register(GPIO_OE_CLR_val).init(base_address + 0x28);
/// GPIO_OE_SET
const GPIO_OE_SET_val = packed struct {
/// GPIO_OE_SET [0:29]
/// Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata`
GPIO_OE_SET: u30 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO output enable set
pub const GPIO_OE_SET = Register(GPIO_OE_SET_val).init(base_address + 0x24);
/// GPIO_OE
const GPIO_OE_val = packed struct {
/// GPIO_OE [0:29]
/// Set output enable (1/0 -> output/input) for GPIO0...29.\n
GPIO_OE: u30 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO output enable
pub const GPIO_OE = Register(GPIO_OE_val).init(base_address + 0x20);
/// GPIO_OUT_XOR
const GPIO_OUT_XOR_val = packed struct {
/// GPIO_OUT_XOR [0:29]
/// Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata`
GPIO_OUT_XOR: u30 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO output value XOR
pub const GPIO_OUT_XOR = Register(GPIO_OUT_XOR_val).init(base_address + 0x1c);
/// GPIO_OUT_CLR
const GPIO_OUT_CLR_val = packed struct {
/// GPIO_OUT_CLR [0:29]
/// Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= ~wdata`
GPIO_OUT_CLR: u30 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO output value clear
pub const GPIO_OUT_CLR = Register(GPIO_OUT_CLR_val).init(base_address + 0x18);
/// GPIO_OUT_SET
const GPIO_OUT_SET_val = packed struct {
/// GPIO_OUT_SET [0:29]
/// Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata`
GPIO_OUT_SET: u30 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO output value set
pub const GPIO_OUT_SET = Register(GPIO_OUT_SET_val).init(base_address + 0x14);
/// GPIO_OUT
const GPIO_OUT_val = packed struct {
/// GPIO_OUT [0:29]
/// Set output level (1/0 -> high/low) for GPIO0...29.\n
GPIO_OUT: u30 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// GPIO output value
pub const GPIO_OUT = Register(GPIO_OUT_val).init(base_address + 0x10);
/// GPIO_HI_IN
const GPIO_HI_IN_val = packed struct {
/// GPIO_HI_IN [0:5]
/// Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2, SD3
GPIO_HI_IN: u6 = 0,
/// unused [6:31]
_unused6: u2 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Input value for QSPI pins
pub const GPIO_HI_IN = Register(GPIO_HI_IN_val).init(base_address + 0x8);
/// GPIO_IN
const GPIO_IN_val = packed struct {
/// GPIO_IN [0:29]
/// Input value for GPIO0...29
GPIO_IN: u30 = 0,
/// unused [30:31]
_unused30: u2 = 0,
};
/// Input value for GPIO pins
pub const GPIO_IN = Register(GPIO_IN_val).init(base_address + 0x4);
/// CPUID
const CPUID_val = packed struct {
CPUID_0: u8 = 0,
CPUID_1: u8 = 0,
CPUID_2: u8 = 0,
CPUID_3: u8 = 0,
};
/// Processor core identifier\n
pub const CPUID = Register(CPUID_val).init(base_address + 0x0);
};
/// No description
pub const PPB = struct {
const base_address = 0xe0000000;
/// MPU_RASR
const MPU_RASR_val = packed struct {
/// ENABLE [0:0]
/// Enables the region.
ENABLE: u1 = 0,
/// SIZE [1:5]
/// Indicates the region size. Region size in bytes = 2^(SIZE+1). The minimum permitted value is 7 (b00111) = 256Bytes
SIZE: u5 = 0,
/// unused [6:7]
_unused6: u2 = 0,
/// SRD [8:15]
/// Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled.
SRD: u8 = 0,
/// ATTRS [16:31]
/// The MPU Region Attribute field. Use to define the region attribute control.\n
ATTRS: u16 = 0,
};
/// Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region.
pub const MPU_RASR = Register(MPU_RASR_val).init(base_address + 0xeda0);
/// MPU_RBAR
const MPU_RBAR_val = packed struct {
/// REGION [0:3]
/// On writes, specifies the number of the region whose base address to update provided VALID is set written as 1. On reads, returns bits [3:0] of MPU_RNR.
REGION: u4 = 0,
/// VALID [4:4]
/// On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region.\n
VALID: u1 = 0,
/// unused [5:7]
_unused5: u3 = 0,
/// ADDR [8:31]
/// Base address of the region.
ADDR: u24 = 0,
};
/// Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated.
pub const MPU_RBAR = Register(MPU_RBAR_val).init(base_address + 0xed9c);
/// MPU_RNR
const MPU_RNR_val = packed struct {
/// REGION [0:3]
/// Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers.\n
REGION: u4 = 0,
/// unused [4:31]
_unused4: u4 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR.
pub const MPU_RNR = Register(MPU_RNR_val).init(base_address + 0xed98);
/// MPU_CTRL
const MPU_CTRL_val = packed struct {
/// ENABLE [0:0]
/// Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map.\n
ENABLE: u1 = 0,
/// HFNMIENA [1:1]
/// Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour.\n
HFNMIENA: u1 = 0,
/// PRIVDEFENA [2:2]
/// Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear.\n
PRIVDEFENA: u1 = 0,
/// unused [3:31]
_unused3: u5 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs.
pub const MPU_CTRL = Register(MPU_CTRL_val).init(base_address + 0xed94);
/// MPU_TYPE
const MPU_TYPE_val = packed struct {
/// SEPARATE [0:0]
/// Indicates support for separate instruction and data address maps. Reads as 0 as ARMv6-M only supports a unified MPU.
SEPARATE: u1 = 0,
/// unused [1:7]
_unused1: u7 = 0,
/// DREGION [8:15]
/// Number of regions supported by the MPU.
DREGION: u8 = 8,
/// IREGION [16:23]
/// Instruction region. Reads as zero as ARMv6-M only supports a unified MPU.
IREGION: u8 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports.
pub const MPU_TYPE = Register(MPU_TYPE_val).init(base_address + 0xed90);
/// SHCSR
const SHCSR_val = packed struct {
/// unused [0:14]
_unused0: u8 = 0,
_unused8: u7 = 0,
/// SVCALLPENDED [15:15]
/// Reads as 1 if SVCall is Pending. Write 1 to set pending SVCall, write 0 to clear pending SVCall.
SVCALLPENDED: u1 = 0,
/// unused [16:31]
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// Use the System Handler Control and State Register to determine or clear the pending status of SVCall.
pub const SHCSR = Register(SHCSR_val).init(base_address + 0xed24);
/// SHPR3
const SHPR3_val = packed struct {
/// unused [0:21]
_unused0: u8 = 0,
_unused8: u8 = 0,
_unused16: u6 = 0,
/// PRI_14 [22:23]
/// Priority of system handler 14, PendSV
PRI_14: u2 = 0,
/// unused [24:29]
_unused24: u6 = 0,
/// PRI_15 [30:31]
/// Priority of system handler 15, SysTick
PRI_15: u2 = 0,
};
/// System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick.
pub const SHPR3 = Register(SHPR3_val).init(base_address + 0xed20);
/// SHPR2
const SHPR2_val = packed struct {
/// unused [0:29]
_unused0: u8 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u6 = 0,
/// PRI_11 [30:31]
/// Priority of system handler 11, SVCall
PRI_11: u2 = 0,
};
/// System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall.
pub const SHPR2 = Register(SHPR2_val).init(base_address + 0xed1c);
/// CCR
const CCR_val = packed struct {
/// unused [0:2]
_unused0: u3 = 0,
/// UNALIGN_TRP [3:3]
/// Always reads as one, indicates that all unaligned accesses generate a HardFault.
UNALIGN_TRP: u1 = 0,
/// unused [4:8]
_unused4: u4 = 0,
_unused8: u1 = 0,
/// STKALIGN [9:9]
/// Always reads as one, indicates 8-byte stack alignment on exception entry. On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack alignment. On return from the exception it uses this stacked bit to restore the correct stack alignment.
STKALIGN: u1 = 0,
/// unused [10:31]
_unused10: u6 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault.
pub const CCR = Register(CCR_val).init(base_address + 0xed14);
/// SCR
const SCR_val = packed struct {
/// unused [0:0]
_unused0: u1 = 0,
/// SLEEPONEXIT [1:1]
/// Indicates sleep-on-exit when returning from Handler mode to Thread mode:\n
SLEEPONEXIT: u1 = 0,
/// SLEEPDEEP [2:2]
/// Controls whether the processor uses sleep or deep sleep as its low power mode:\n
SLEEPDEEP: u1 = 0,
/// unused [3:3]
_unused3: u1 = 0,
/// SEVONPEND [4:4]
/// Send Event on Pending bit:\n
SEVONPEND: u1 = 0,
/// unused [5:31]
_unused5: u3 = 0,
_unused8: u8 = 0,
_unused16: u8 = 0,
_unused24: u8 = 0,
};
/// System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states.
pub const SCR = Register(SCR_val).init(base_address + 0xed10);
/// AIRCR
const AIRCR_val = packed struct {
/// unused [0:0]
_unused0: u1 = 0,
/// VECTCLRACTIVE [1:1]
/// Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack.
VECTCLRACTIVE: u1 = 0,
/// SYSRESETREQ [2:2]
/// Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device.
SYSRESETREQ: u1 = 0,
/// unused [3:14]
_unused3: u5 = 0,
_unused8: u7 = 0,
/// ENDIANESS [15:15]
/// Data endianness implemented:\n
ENDIANESS: u1 = 0,
/// VECTKEY [16:31]
/// Register key:\n
VECTKEY: u16 = 0,
};
/// Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset.
pub const AIRCR = Register(AIRCR_val).init(base_address + 0xed0c);
/// VTOR
const VTOR_val = packed struct {
/// unused [0:7]
_unused0: u8 = 0,
/// TBLOFF [8:31]
/// Bits [31:8] of the indicate the vector table offset address.
TBLOFF: u24 = 0,
};
/// The VTOR holds the vector table offset address.
pub const VTOR = Register(VTOR_val).init(base_address + 0xed08);
/// ICSR
const ICSR_val = packed struct {
/// VECTACTIVE [0:8]
/// Active exception number field. Reset clears the VECTACTIVE field.
VECTACTIVE: u9 = 0,
/// unused [9:11]
_unused9: u3 = 0,
/// VECTPENDING [12:20]
/// Indicates the exception number for the highest priority pending exception: 0 = no pending exceptions. Non zero = The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier.
VECTPENDING: u9 = 0,
/// unused [21:21]
_unused21: u1 = 0,
/// ISRPENDING [22:22]
/// External interrupt pending flag
ISRPENDING: u1 = 0,
/// ISRPREEMPT [23:23]
/// The system can only access this bit when the core is halted. It indicates that a pending interrupt is to be taken in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced.
ISRPREEMPT: u1 = 0,
/// unused [24:24]
_unused24: u1 = 0,
/// PENDSTCLR [25:25]
/// SysTick exception clear-pending bit.\n
PENDSTCLR: u1 = 0,
/// PENDSTSET [26:26]
/// SysTick exception set-pending bit.\n
PENDSTSET: u1 = 0,
/// PENDSVCLR [27:27]
/// PendSV clear-pending bit.\n
PENDSVCLR: u1 = 0,
/// PENDSVSET [28:28]
/// PendSV set-pending bit.\n
PENDSVSET: u1 = 0,
/// unused [29:30]
_unused29: u2 = 0,
/// NMIPENDSET [31:31]
/// Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered.\n
NMIPENDSET: u1 = 0,
};
/// Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception.
pub const ICSR = Register(ICSR_val).init(base_address + 0xed04);
/// CPUID
const CPUID_val = packed struct {
/// REVISION [0:3]
/// Minor revision number m in the rnpm revision status:\n
REVISION: u4 = 1,
/// PARTNO [4:15]
/// Number of processor within family: 0xC60 = Cortex-M0+
PARTNO: u12 = 3168,
/// ARCHITECTURE [16:19]
/// Constant that defines the architecture of the processor:\n
ARCHITECTURE: u4 = 12,
/// VARIANT [20:23]
/// Major revision number n in the rnpm revision status:\n
VARIANT: u4 = 0,
/// IMPLEMENTER [24:31]
/// Implementor code: 0x41 = ARM
IMPLEMENTER: u8 = 65,
};
/// Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core.
pub const CPUID = Register(CPUID_val).init(base_address + 0xed00);
/// NVIC_IPR7
const NVIC_IPR7_val = packed struct {
/// unused [0:5]
_unused0: u6 = 0,
/// IP_28 [6:7]
/// Priority of interrupt 28
IP_28: u2 = 0,
/// unused [8:13]
_unused8: u6 = 0,
/// IP_29 [14:15]
/// Priority of interrupt 29
IP_29: u2 = 0,
/// unused [16:21]
_unused16: u6 = 0,
/// IP_30 [22:23]
/// Priority of interrupt 30
IP_30: u2 = 0,
/// unused [24:29]
_unused24: u6 = 0,
/// IP_31 [30:31]
/// Priority of interrupt 31
IP_31: u2 = 0,
};
/// Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
pub const NVIC_IPR7 = Register(NVIC_IPR7_val).init(base_address + 0xe41c);
/// NVIC_IPR6
const NVIC_IPR6_val = packed struct {
/// unused [0:5]
_unused0: u6 = 0,
/// IP_24 [6:7]
/// Priority of interrupt 24
IP_24: u2 = 0,
/// unused [8:13]
_unused8: u6 = 0,
/// IP_25 [14:15]
/// Priority of interrupt 25
IP_25: u2 = 0,
/// unused [16:21]
_unused16: u6 = 0,
/// IP_26 [22:23]
/// Priority of interrupt 26
IP_26: u2 = 0,
/// unused [24:29]
_unused24: u6 = 0,
/// IP_27 [30:31]
/// Priority of interrupt 27
IP_27: u2 = 0,
};
/// Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
pub const NVIC_IPR6 = Register(NVIC_IPR6_val).init(base_address + 0xe418);
/// NVIC_IPR5
const NVIC_IPR5_val = packed struct {
/// unused [0:5]
_unused0: u6 = 0,
/// IP_20 [6:7]
/// Priority of interrupt 20
IP_20: u2 = 0,
/// unused [8:13]
_unused8: u6 = 0,
/// IP_21 [14:15]
/// Priority of interrupt 21
IP_21: u2 = 0,
/// unused [16:21]
_unused16: u6 = 0,
/// IP_22 [22:23]
/// Priority of interrupt 22
IP_22: u2 = 0,
/// unused [24:29]
_unused24: u6 = 0,
/// IP_23 [30:31]
/// Priority of interrupt 23
IP_23: u2 = 0,
};
/// Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
pub const NVIC_IPR5 = Register(NVIC_IPR5_val).init(base_address + 0xe414);
/// NVIC_IPR4
const NVIC_IPR4_val = packed struct {
/// unused [0:5]
_unused0: u6 = 0,
/// IP_16 [6:7]
/// Priority of interrupt 16
IP_16: u2 = 0,
/// unused [8:13]
_unused8: u6 = 0,
/// IP_17 [14:15]
/// Priority of interrupt 17
IP_17: u2 = 0,
/// unused [16:21]
_unused16: u6 = 0,
/// IP_18 [22:23]
/// Priority of interrupt 18
IP_18: u2 = 0,
/// unused [24:29]
_unused24: u6 = 0,
/// IP_19 [30:31]
/// Priority of interrupt 19
IP_19: u2 = 0,
};
/// Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
pub const NVIC_IPR4 = Register(NVIC_IPR4_val).init(base_address + 0xe410);
/// NVIC_IPR3
const NVIC_IPR3_val = packed struct {
/// unused [0:5]
_unused0: u6 = 0,
/// IP_12 [6:7]
/// Priority of interrupt 12
IP_12: u2 = 0,
/// unused [8:13]
_unused8: u6 = 0,
/// IP_13 [14:15]
/// Priority of interrupt 13
IP_13: u2 = 0,
/// unused [16:21]
_unused16: u6 = 0,
/// IP_14 [22:23]
/// Priority of interrupt 14
IP_14: u2 = 0,
/// unused [24:29]
_unused24: u6 = 0,
/// IP_15 [30:31]
/// Priority of interrupt 15
IP_15: u2 = 0,
};
/// Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
pub const NVIC_IPR3 = Register(NVIC_IPR3_val).init(base_address + 0xe40c);
/// NVIC_IPR2
const NVIC_IPR2_val = packed struct {
/// unused [0:5]
_unused0: u6 = 0,
/// IP_8 [6:7]
/// Priority of interrupt 8
IP_8: u2 = 0,
/// unused [8:13]
_unused8: u6 = 0,
/// IP_9 [14:15]
/// Priority of interrupt 9
IP_9: u2 = 0,
/// unused [16:21]
_unused16: u6 = 0,
/// IP_10 [22:23]
/// Priority of interrupt 10
IP_10: u2 = 0,
/// unused [24:29]
_unused24: u6 = 0,
/// IP_11 [30:31]
/// Priority of interrupt 11
IP_11: u2 = 0,
};
/// Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
pub const NVIC_IPR2 = Register(NVIC_IPR2_val).init(base_address + 0xe408);
/// NVIC_IPR1
const NVIC_IPR1_val = packed struct {
/// unused [0:5]
_unused0: u6 = 0,
/// IP_4 [6:7]
/// Priority of interrupt 4
IP_4: u2 = 0,
/// unused [8:13]
_unused8: u6 = 0,
/// IP_5 [14:15]
/// Priority of interrupt 5
IP_5: u2 = 0,
/// unused [16:21]
_unused16: u6 = 0,
/// IP_6 [22:23]
/// Priority of interrupt 6
IP_6: u2 = 0,
/// unused [24:29]
_unused24: u6 = 0,
/// IP_7 [30:31]
/// Priority of interrupt 7
IP_7: u2 = 0,
};
/// Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
pub const NVIC_IPR1 = Register(NVIC_IPR1_val).init(base_address + 0xe404);
/// NVIC_IPR0
const NVIC_IPR0_val = packed struct {
/// unused [0:5]
_unused0: u6 = 0,
/// IP_0 [6:7]
/// Priority of interrupt 0
IP_0: u2 = 0,
/// unused [8:13]
_unused8: u6 = 0,
/// IP_1 [14:15]
/// Priority of interrupt 1
IP_1: u2 = 0,
/// unused [16:21]
_unused16: u6 = 0,
/// IP_2 [22:23]
/// Priority of interrupt 2
IP_2: u2 = 0,
/// unused [24:29]
_unused24: u6 = 0,
/// IP_3 [30:31]
/// Priority of interrupt 3
IP_3: u2 = 0,
};
/// Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.\n
pub const NVIC_IPR0 = Register(NVIC_IPR0_val).init(base_address + 0xe400);
/// NVIC_ICPR
const NVIC_ICPR_val = packed struct {
/// CLRPEND [0:31]
/// Interrupt clear-pending bits.\n
CLRPEND: u32 = 0,
};
/// Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending.
pub const NVIC_ICPR = Register(NVIC_ICPR_val).init(base_address + 0xe280);
/// NVIC_ISPR
const NVIC_ISPR_val = packed struct {
/// SETPEND [0:31]
/// Interrupt set-pending bits.\n
SETPEND: u32 = 0,
};
/// The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending.
pub const NVIC_ISPR = Register(NVIC_ISPR_val).init(base_address + 0xe200);
/// NVIC_ICER
const NVIC_ICER_val = packed struct {
/// CLRENA [0:31]
/// Interrupt clear-enable bits.\n
CLRENA: u32 = 0,
};
/// Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled.
pub const NVIC_ICER = Register(NVIC_ICER_val).init(base_address + 0xe180);
/// NVIC_ISER
const NVIC_ISER_val = packed struct {
/// SETENA [0:31]
/// Interrupt set-enable bits.\n
SETENA: u32 = 0,
};
/// Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled.\n
pub const NVIC_ISER = Register(NVIC_ISER_val).init(base_address + 0xe100);
/// SYST_CALIB
const SYST_CALIB_val = packed struct {
/// TENMS [0:23]
/// An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known.
TENMS: u24 = 0,
/// unused [24:29]
_unused24: u6 = 0,
/// SKEW [30:30]
/// If reads as 1, the calibration value for 10ms is inexact (due to clock frequency).
SKEW: u1 = 0,
/// NOREF [31:31]
/// If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0.
NOREF: u1 = 0,
};
/// Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply.
pub const SYST_CALIB = Register(SYST_CALIB_val).init(base_address + 0xe01c);
/// SYST_CVR
const SYST_CVR_val = packed struct {
/// CURRENT [0:23]
/// Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register.
CURRENT: u24 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN.
pub const SYST_CVR = Register(SYST_CVR_val).init(base_address + 0xe018);
/// SYST_RVR
const SYST_RVR_val = packed struct {
/// RELOAD [0:23]
/// Value to load into the SysTick Current Value Register when the counter reaches 0.
RELOAD: u24 = 0,
/// unused [24:31]
_unused24: u8 = 0,
};
/// Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN.\n
pub const SYST_RVR = Register(SYST_RVR_val).init(base_address + 0xe014);
/// SYST_CSR
const SYST_CSR_val = packed struct {
/// ENABLE [0:0]
/// Enable SysTick counter:\n
ENABLE: u1 = 0,
/// TICKINT [1:1]
/// Enables SysTick exception request:\n
TICKINT: u1 = 0,
/// CLKSOURCE [2:2]
/// SysTick clock source. Always reads as one if SYST_CALIB reports NOREF.\n
CLKSOURCE: u1 = 0,
/// unused [3:15]
_unused3: u5 = 0,
_unused8: u8 = 0,
/// COUNTFLAG [16:16]
/// Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger.
COUNTFLAG: u1 = 0,
/// unused [17:31]
_unused17: u7 = 0,
_unused24: u8 = 0,
};
/// Use the SysTick Control and Status Register to enable the SysTick features.
pub const SYST_CSR = Register(SYST_CSR_val).init(base_address + 0xe010);
};
pub const interrupts = struct {
pub const TIMER_IRQ_3 = 3;
pub const ADC_IRQ_FIFO = 22;
pub const CLOCKS_IRQ = 17;
pub const PIO1_IRQ_0 = 9;
pub const I2C0_IRQ = 23;
pub const XIP_IRQ = 6;
pub const TIMER_IRQ_2 = 2;
pub const UART1_IRQ = 21;
pub const PIO0_IRQ_0 = 7;
pub const DMA_IRQ_1 = 12;
pub const SPI0_IRQ = 18;
pub const IO_IRQ_QSPI = 14;
pub const TIMER_IRQ_0 = 0;
pub const USBCTRL_IRQ = 5;
pub const PIO0_IRQ_1 = 8;
pub const RTC_IRQ = 25;
pub const SIO_IRQ_PROC1 = 16;
pub const UART0_IRQ = 20;
pub const SPI1_IRQ = 19;
pub const PWM_IRQ_WRAP = 4;
pub const TIMER_IRQ_1 = 1;
pub const IO_IRQ_BANK0 = 13;
pub const I2C1_IRQ = 24;
pub const DMA_IRQ_0 = 11;
pub const SIO_IRQ_PROC0 = 15;
pub const PIO1_IRQ_1 = 10;
}; | rp2040_ras/rp2040_ras.zig |
const std = @import("std");
const os = std.os;
const assert = std.debug.assert;
const log = std.log.scoped(.io);
const config = @import("../config.zig");
const FIFO = @import("../fifo.zig").FIFO;
const Time = @import("../time.zig").Time;
const buffer_limit = @import("../io.zig").buffer_limit;
pub const IO = struct {
iocp: os.windows.HANDLE,
timer: Time = .{},
io_pending: usize = 0,
timeouts: FIFO(Completion) = .{},
completed: FIFO(Completion) = .{},
pub fn init(entries: u12, flags: u32) !IO {
_ = entries;
_ = flags;
_ = try os.windows.WSAStartup(2, 2);
errdefer os.windows.WSACleanup() catch unreachable;
const iocp = try os.windows.CreateIoCompletionPort(os.windows.INVALID_HANDLE_VALUE, null, 0, 0);
return IO{ .iocp = iocp };
}
pub fn deinit(self: *IO) void {
assert(self.iocp != os.windows.INVALID_HANDLE_VALUE);
os.windows.CloseHandle(self.iocp);
self.iocp = os.windows.INVALID_HANDLE_VALUE;
os.windows.WSACleanup() catch unreachable;
}
pub fn tick(self: *IO) !void {
return self.flush(.non_blocking);
}
pub fn run_for_ns(self: *IO, nanoseconds: u63) !void {
const Callback = struct {
fn on_timeout(timed_out: *bool, completion: *Completion, result: TimeoutError!void) void {
_ = result catch unreachable;
_ = completion;
timed_out.* = true;
}
};
var timed_out = false;
var completion: Completion = undefined;
self.timeout(*bool, &timed_out, Callback.on_timeout, &completion, nanoseconds);
while (!timed_out) {
try self.flush(.blocking);
}
}
const FlushMode = enum {
blocking,
non_blocking,
};
fn flush(self: *IO, mode: FlushMode) !void {
if (self.completed.peek() == null) {
// Compute how long to poll by flushing timeout completions.
// NOTE: this may push to completed queue
var timeout_ms: ?os.windows.DWORD = null;
if (self.flush_timeouts()) |expires_ns| {
// 0ns expires should have been completed not returned
assert(expires_ns != 0);
// Round up sub-millisecond expire times to the next millisecond
const expires_ms = (expires_ns + (std.time.ns_per_ms / 2)) / std.time.ns_per_ms;
// Saturating cast to DWORD milliseconds
const expires = std.math.cast(os.windows.DWORD, expires_ms) catch std.math.maxInt(os.windows.DWORD);
// max DWORD is reserved for INFINITE so cap the cast at max - 1
timeout_ms = if (expires == os.windows.INFINITE) expires - 1 else expires;
}
// Poll for IO iff theres IO pending and flush_timeouts() found no ready completions
if (self.io_pending > 0 and self.completed.peek() == null) {
// In blocking mode, we're always waiting at least until the timeout by run_for_ns.
// In non-blocking mode, we shouldn't wait at all.
const io_timeout = switch (mode) {
.blocking => timeout_ms orelse @panic("IO.flush blocking unbounded"),
.non_blocking => 0,
};
var events: [64]os.windows.OVERLAPPED_ENTRY = undefined;
const num_events = os.windows.GetQueuedCompletionStatusEx(
self.iocp,
&events,
io_timeout,
false, // non-alertable wait
) catch |err| switch (err) {
error.Timeout => 0,
error.Aborted => unreachable,
else => |e| return e,
};
assert(self.io_pending >= num_events);
self.io_pending -= num_events;
for (events[0..num_events]) |event| {
const raw_overlapped = event.lpOverlapped;
const overlapped = @fieldParentPtr(Completion.Overlapped, "raw", raw_overlapped);
const completion = overlapped.completion;
completion.next = null;
self.completed.push(completion);
}
}
}
// Dequeue and invoke all the completions currently ready.
// Must read all `completions` before invoking the callbacks
// as the callbacks could potentially submit more completions.
var completed = self.completed;
self.completed = .{};
while (completed.pop()) |completion| {
(completion.callback)(Completion.Context{
.io = self,
.completion = completion,
});
}
}
fn flush_timeouts(self: *IO) ?u64 {
var min_expires: ?u64 = null;
var current_time: ?u64 = null;
var timeouts: ?*Completion = self.timeouts.peek();
// iterate through the timeouts, returning min_expires at the end
while (timeouts) |completion| {
timeouts = completion.next;
// lazily get the current time
const now = current_time orelse self.timer.monotonic();
current_time = now;
// move the completion to completed if it expired
if (now >= completion.operation.timeout.deadline) {
self.timeouts.remove(completion);
self.completed.push(completion);
continue;
}
// if it's still waiting, update min_timeout
const expires = completion.operation.timeout.deadline - now;
if (min_expires) |current_min_expires| {
min_expires = std.math.min(expires, current_min_expires);
} else {
min_expires = expires;
}
}
return min_expires;
}
/// This struct holds the data needed for a single IO operation
pub const Completion = struct {
next: ?*Completion,
context: ?*anyopaque,
callback: fn (Context) void,
operation: Operation,
const Context = struct {
io: *IO,
completion: *Completion,
};
const Overlapped = struct {
raw: os.windows.OVERLAPPED,
completion: *Completion,
};
const Transfer = struct {
socket: os.socket_t,
buf: os.windows.ws2_32.WSABUF,
overlapped: Overlapped,
pending: bool,
};
const Operation = union(enum) {
accept: struct {
overlapped: Overlapped,
listen_socket: os.socket_t,
client_socket: os.socket_t,
addr_buffer: [(@sizeOf(std.net.Address) + 16) * 2]u8 align(4),
},
connect: struct {
socket: os.socket_t,
address: std.net.Address,
overlapped: Overlapped,
pending: bool,
},
send: Transfer,
recv: Transfer,
read: struct {
fd: os.fd_t,
buf: [*]u8,
len: u32,
offset: u64,
},
write: struct {
fd: os.fd_t,
buf: [*]const u8,
len: u32,
offset: u64,
},
close: struct {
fd: os.fd_t,
},
timeout: struct {
deadline: u64,
},
};
};
fn submit(
self: *IO,
context: anytype,
comptime callback: anytype,
completion: *Completion,
comptime op_tag: std.meta.Tag(Completion.Operation),
op_data: anytype,
comptime OperationImpl: type,
) void {
const Context = @TypeOf(context);
const Callback = struct {
fn onComplete(ctx: Completion.Context) void {
// Perform the operation and get the result
const data = &@field(ctx.completion.operation, @tagName(op_tag));
const result = OperationImpl.do_operation(ctx, data);
// For OVERLAPPED IO, error.WouldBlock assumes that it will be completed by IOCP.
switch (op_tag) {
.accept, .read, .recv, .connect, .write, .send => {
_ = result catch |err| switch (err) {
error.WouldBlock => {
ctx.io.io_pending += 1;
return;
},
else => {},
};
},
else => {},
}
// The completion is finally ready to invoke the callback
callback(
@intToPtr(Context, @ptrToInt(ctx.completion.context)),
ctx.completion,
result,
);
}
};
// Setup the completion with the callback wrapper above
completion.* = .{
.next = null,
.context = @ptrCast(?*anyopaque, context),
.callback = Callback.onComplete,
.operation = @unionInit(Completion.Operation, @tagName(op_tag), op_data),
};
// Submit the completion onto the right queue
switch (op_tag) {
.timeout => self.timeouts.push(completion),
else => self.completed.push(completion),
}
}
pub const AcceptError = os.AcceptError || os.SetSockOptError;
pub fn accept(
self: *IO,
comptime Context: type,
context: Context,
comptime callback: fn (
context: Context,
completion: *Completion,
result: AcceptError!os.socket_t,
) void,
completion: *Completion,
socket: os.socket_t,
) void {
self.submit(
context,
callback,
completion,
.accept,
.{
.overlapped = undefined,
.listen_socket = socket,
.client_socket = INVALID_SOCKET,
.addr_buffer = undefined,
},
struct {
fn do_operation(ctx: Completion.Context, op: anytype) AcceptError!os.socket_t {
var flags: os.windows.DWORD = undefined;
var transferred: os.windows.DWORD = undefined;
const rc = switch (op.client_socket) {
// When first called, the client_socket is invalid so we start the op.
INVALID_SOCKET => blk: {
// Create the socket that will be used for accept.
op.client_socket = ctx.io.open_socket(
os.AF.INET,
os.SOCK.STREAM,
os.IPPROTO.TCP,
) catch |err| switch (err) {
error.AddressFamilyNotSupported, error.ProtocolNotSupported => unreachable,
else => |e| return e,
};
var sync_bytes_read: os.windows.DWORD = undefined;
op.overlapped = .{
.raw = std.mem.zeroes(os.windows.OVERLAPPED),
.completion = ctx.completion,
};
// Start the asynchronous accept with the created socket.
break :blk os.windows.ws2_32.AcceptEx(
op.listen_socket,
op.client_socket,
&op.addr_buffer,
0,
@sizeOf(std.net.Address) + 16,
@sizeOf(std.net.Address) + 16,
&sync_bytes_read,
&op.overlapped.raw,
);
},
// Called after accept was started, so get the result
else => os.windows.ws2_32.WSAGetOverlappedResult(
op.listen_socket,
&op.overlapped.raw,
&transferred,
os.windows.FALSE, // dont wait
&flags,
),
};
// return the socket if we succeed in accepting.
if (rc != os.windows.FALSE) {
// enables getsockopt, setsockopt, getsockname, getpeername
_ = os.windows.ws2_32.setsockopt(
op.client_socket,
os.windows.ws2_32.SOL.SOCKET,
os.windows.ws2_32.SO.UPDATE_ACCEPT_CONTEXT,
null,
0,
);
return op.client_socket;
}
// destroy the client_socket we created if we get a non WouldBlock error
errdefer |result| {
_ = result catch |err| switch (err) {
error.WouldBlock => {},
else => {
os.closeSocket(op.client_socket);
op.client_socket = INVALID_SOCKET;
},
};
}
return switch (os.windows.ws2_32.WSAGetLastError()) {
.WSA_IO_PENDING, .WSAEWOULDBLOCK, .WSA_IO_INCOMPLETE => error.WouldBlock,
.WSANOTINITIALISED => unreachable, // WSAStartup() was called
.WSAENETDOWN => unreachable, // WinSock error
.WSAENOTSOCK => error.FileDescriptorNotASocket,
.WSAEOPNOTSUPP => error.OperationNotSupported,
.WSA_INVALID_HANDLE => unreachable, // we dont use hEvent in OVERLAPPED
.WSAEFAULT, .WSA_INVALID_PARAMETER => unreachable, // params should be ok
.WSAECONNRESET => error.ConnectionAborted,
.WSAEMFILE => unreachable, // we create our own descriptor so its available
.WSAENOBUFS => error.SystemResources,
.WSAEINTR, .WSAEINPROGRESS => unreachable, // no blocking calls
else => |err| os.windows.unexpectedWSAError(err),
};
}
},
);
}
pub const CloseError = error{
FileDescriptorInvalid,
DiskQuota,
InputOutput,
NoSpaceLeft,
} || os.UnexpectedError;
pub const ConnectError = os.ConnectError || error{FileDescriptorNotASocket};
pub fn connect(
self: *IO,
comptime Context: type,
context: Context,
comptime callback: fn (
context: Context,
completion: *Completion,
result: ConnectError!void,
) void,
completion: *Completion,
socket: os.socket_t,
address: std.net.Address,
) void {
self.submit(
context,
callback,
completion,
.connect,
.{
.socket = socket,
.address = address,
.overlapped = undefined,
.pending = false,
},
struct {
fn do_operation(ctx: Completion.Context, op: anytype) ConnectError!void {
var flags: os.windows.DWORD = undefined;
var transferred: os.windows.DWORD = undefined;
const rc = blk: {
// Poll for the result if we've already started the connect op.
if (op.pending) {
break :blk os.windows.ws2_32.WSAGetOverlappedResult(
op.socket,
&op.overlapped.raw,
&transferred,
os.windows.FALSE, // dont wait
&flags,
);
}
// ConnectEx requires the socket to be initially bound (INADDR_ANY)
const inaddr_any = std.mem.zeroes([4]u8);
const bind_addr = std.net.Address.initIp4(inaddr_any, 0);
os.bind(
op.socket,
&bind_addr.any,
bind_addr.getOsSockLen(),
) catch |err| switch (err) {
error.AccessDenied => unreachable,
error.SymLinkLoop => unreachable,
error.NameTooLong => unreachable,
error.NotDir => unreachable,
error.ReadOnlyFileSystem => unreachable,
error.NetworkSubsystemFailed => unreachable,
error.AlreadyBound => unreachable,
else => |e| return e,
};
const LPFN_CONNECTEX = fn (
Socket: os.windows.ws2_32.SOCKET,
SockAddr: *const os.windows.ws2_32.sockaddr,
SockLen: os.socklen_t,
SendBuf: ?*const anyopaque,
SendBufLen: os.windows.DWORD,
BytesSent: *os.windows.DWORD,
Overlapped: *os.windows.OVERLAPPED,
) callconv(os.windows.WINAPI) os.windows.BOOL;
// Find the ConnectEx function by dynamically looking it up on the socket.
const connect_ex = os.windows.loadWinsockExtensionFunction(
LPFN_CONNECTEX,
op.socket,
os.windows.ws2_32.WSAID_CONNECTEX,
) catch |err| switch (err) {
error.OperationNotSupported => unreachable,
error.ShortRead => unreachable,
else => |e| return e,
};
op.pending = true;
op.overlapped = .{
.raw = std.mem.zeroes(os.windows.OVERLAPPED),
.completion = ctx.completion,
};
// Start the connect operation.
break :blk (connect_ex)(
op.socket,
&op.address.any,
op.address.getOsSockLen(),
null,
0,
&transferred,
&op.overlapped.raw,
);
};
// return if we succeeded in connecting
if (rc != os.windows.FALSE) {
// enables getsockopt, setsockopt, getsockname, getpeername
_ = os.windows.ws2_32.setsockopt(
op.socket,
os.windows.ws2_32.SOL.SOCKET,
os.windows.ws2_32.SO.UPDATE_CONNECT_CONTEXT,
null,
0,
);
return;
}
return switch (os.windows.ws2_32.WSAGetLastError()) {
.WSA_IO_PENDING, .WSAEWOULDBLOCK, .WSA_IO_INCOMPLETE, .WSAEALREADY => error.WouldBlock,
.WSANOTINITIALISED => unreachable, // WSAStartup() was called
.WSAENETDOWN => unreachable, // network subsystem is down
.WSAEADDRNOTAVAIL => error.AddressNotAvailable,
.WSAEAFNOSUPPORT => error.AddressFamilyNotSupported,
.WSAECONNREFUSED => error.ConnectionRefused,
.WSAEFAULT => unreachable, // all addresses should be valid
.WSAEINVAL => unreachable, // invalid socket type
.WSAEHOSTUNREACH, .WSAENETUNREACH => error.NetworkUnreachable,
.WSAENOBUFS => error.SystemResources,
.WSAENOTSOCK => unreachable, // socket is not bound or is listening
.WSAETIMEDOUT => error.ConnectionTimedOut,
.WSA_INVALID_HANDLE => unreachable, // we dont use hEvent in OVERLAPPED
else => |err| os.windows.unexpectedWSAError(err),
};
}
},
);
}
pub const SendError = os.SendError;
pub fn send(
self: *IO,
comptime Context: type,
context: Context,
comptime callback: fn (
context: Context,
completion: *Completion,
result: SendError!usize,
) void,
completion: *Completion,
socket: os.socket_t,
buffer: []const u8,
) void {
const transfer = Completion.Transfer{
.socket = socket,
.buf = os.windows.ws2_32.WSABUF{
.len = @intCast(u32, buffer_limit(buffer.len)),
.buf = @intToPtr([*]u8, @ptrToInt(buffer.ptr)),
},
.overlapped = undefined,
.pending = false,
};
self.submit(
context,
callback,
completion,
.send,
transfer,
struct {
fn do_operation(ctx: Completion.Context, op: anytype) SendError!usize {
var flags: os.windows.DWORD = undefined;
var transferred: os.windows.DWORD = undefined;
const rc = blk: {
// Poll for the result if we've already started the send op.
if (op.pending) {
break :blk os.windows.ws2_32.WSAGetOverlappedResult(
op.socket,
&op.overlapped.raw,
&transferred,
os.windows.FALSE, // dont wait
&flags,
);
}
op.pending = true;
op.overlapped = .{
.raw = std.mem.zeroes(os.windows.OVERLAPPED),
.completion = ctx.completion,
};
// Start the send operation.
break :blk switch (os.windows.ws2_32.WSASend(
op.socket,
@ptrCast([*]os.windows.ws2_32.WSABUF, &op.buf),
1, // one buffer
&transferred,
0, // no flags
&op.overlapped.raw,
null,
)) {
os.windows.ws2_32.SOCKET_ERROR => @as(os.windows.BOOL, os.windows.FALSE),
0 => os.windows.TRUE,
else => unreachable,
};
};
// Return bytes transferred on success.
if (rc != os.windows.FALSE)
return transferred;
return switch (os.windows.ws2_32.WSAGetLastError()) {
.WSA_IO_PENDING, .WSAEWOULDBLOCK, .WSA_IO_INCOMPLETE => error.WouldBlock,
.WSANOTINITIALISED => unreachable, // WSAStartup() was called
.WSA_INVALID_HANDLE => unreachable, // we dont use OVERLAPPED.hEvent
.WSA_INVALID_PARAMETER => unreachable, // parameters are fine
.WSAECONNABORTED => error.ConnectionResetByPeer,
.WSAECONNRESET => error.ConnectionResetByPeer,
.WSAEFAULT => unreachable, // invalid buffer
.WSAEINTR => unreachable, // this is non blocking
.WSAEINPROGRESS => unreachable, // this is non blocking
.WSAEINVAL => unreachable, // invalid socket type
.WSAEMSGSIZE => error.MessageTooBig,
.WSAENETDOWN => error.NetworkSubsystemFailed,
.WSAENETRESET => error.ConnectionResetByPeer,
.WSAENOBUFS => error.SystemResources,
.WSAENOTCONN => error.FileDescriptorNotASocket,
.WSAEOPNOTSUPP => unreachable, // we dont use MSG_OOB or MSG_PARTIAL
.WSAESHUTDOWN => error.BrokenPipe,
.WSA_OPERATION_ABORTED => unreachable, // operation was cancelled
else => |err| os.windows.unexpectedWSAError(err),
};
}
},
);
}
pub const RecvError = os.RecvFromError;
pub fn recv(
self: *IO,
comptime Context: type,
context: Context,
comptime callback: fn (
context: Context,
completion: *Completion,
result: RecvError!usize,
) void,
completion: *Completion,
socket: os.socket_t,
buffer: []u8,
) void {
const transfer = Completion.Transfer{
.socket = socket,
.buf = os.windows.ws2_32.WSABUF{
.len = @intCast(u32, buffer_limit(buffer.len)),
.buf = buffer.ptr,
},
.overlapped = undefined,
.pending = false,
};
self.submit(
context,
callback,
completion,
.recv,
transfer,
struct {
fn do_operation(ctx: Completion.Context, op: anytype) RecvError!usize {
var flags: os.windows.DWORD = 0; // used both as input and output
var transferred: os.windows.DWORD = undefined;
const rc = blk: {
// Poll for the result if we've already started the recv op.
if (op.pending) {
break :blk os.windows.ws2_32.WSAGetOverlappedResult(
op.socket,
&op.overlapped.raw,
&transferred,
os.windows.FALSE, // dont wait
&flags,
);
}
op.pending = true;
op.overlapped = .{
.raw = std.mem.zeroes(os.windows.OVERLAPPED),
.completion = ctx.completion,
};
// Start the recv operation.
break :blk switch (os.windows.ws2_32.WSARecv(
op.socket,
@ptrCast([*]os.windows.ws2_32.WSABUF, &op.buf),
1, // one buffer
&transferred,
&flags,
&op.overlapped.raw,
null,
)) {
os.windows.ws2_32.SOCKET_ERROR => @as(os.windows.BOOL, os.windows.FALSE),
0 => os.windows.TRUE,
else => unreachable,
};
};
// Return bytes received on success.
if (rc != os.windows.FALSE)
return transferred;
return switch (os.windows.ws2_32.WSAGetLastError()) {
.WSA_IO_PENDING, .WSAEWOULDBLOCK, .WSA_IO_INCOMPLETE => error.WouldBlock,
.WSANOTINITIALISED => unreachable, // WSAStartup() was called
.WSA_INVALID_HANDLE => unreachable, // we dont use OVERLAPPED.hEvent
.WSA_INVALID_PARAMETER => unreachable, // parameters are fine
.WSAECONNABORTED => error.ConnectionRefused,
.WSAECONNRESET => error.ConnectionResetByPeer,
.WSAEDISCON => unreachable, // we only stream sockets
.WSAEFAULT => unreachable, // invalid buffer
.WSAEINTR => unreachable, // this is non blocking
.WSAEINPROGRESS => unreachable, // this is non blocking
.WSAEINVAL => unreachable, // invalid socket type
.WSAEMSGSIZE => error.MessageTooBig,
.WSAENETDOWN => error.NetworkSubsystemFailed,
.WSAENETRESET => error.ConnectionResetByPeer,
.WSAENOTCONN => error.SocketNotConnected,
.WSAEOPNOTSUPP => unreachable, // we dont use MSG_OOB or MSG_PARTIAL
.WSAESHUTDOWN => error.SocketNotConnected,
.WSAETIMEDOUT => error.ConnectionRefused,
.WSA_OPERATION_ABORTED => unreachable, // operation was cancelled
else => |err| os.windows.unexpectedWSAError(err),
};
}
},
);
}
pub const ReadError = error{
WouldBlock,
NotOpenForReading,
ConnectionResetByPeer,
Alignment,
InputOutput,
IsDir,
SystemResources,
Unseekable,
} || os.UnexpectedError;
pub fn read(
self: *IO,
comptime Context: type,
context: Context,
comptime callback: fn (
context: Context,
completion: *Completion,
result: ReadError!usize,
) void,
completion: *Completion,
fd: os.fd_t,
buffer: []u8,
offset: u64,
) void {
self.submit(
context,
callback,
completion,
.read,
.{
.fd = fd,
.buf = buffer.ptr,
.len = @intCast(u32, buffer_limit(buffer.len)),
.offset = offset,
},
struct {
fn do_operation(ctx: Completion.Context, op: anytype) ReadError!usize {
// Do a synchronous read for now.
_ = ctx;
return os.pread(op.fd, op.buf[0..op.len], op.offset) catch |err| switch (err) {
error.OperationAborted => unreachable,
error.BrokenPipe => unreachable,
error.ConnectionTimedOut => unreachable,
error.AccessDenied => error.InputOutput,
else => |e| e,
};
}
},
);
}
pub const WriteError = os.PWriteError;
pub fn write(
self: *IO,
comptime Context: type,
context: Context,
comptime callback: fn (
context: Context,
completion: *Completion,
result: WriteError!usize,
) void,
completion: *Completion,
fd: os.fd_t,
buffer: []const u8,
offset: u64,
) void {
self.submit(
context,
callback,
completion,
.write,
.{
.fd = fd,
.buf = buffer.ptr,
.len = @intCast(u32, buffer_limit(buffer.len)),
.offset = offset,
},
struct {
fn do_operation(ctx: Completion.Context, op: anytype) WriteError!usize {
// Do a synchronous write for now.
_ = ctx;
return os.pwrite(op.fd, op.buf[0..op.len], op.offset);
}
},
);
}
pub fn close(
self: *IO,
comptime Context: type,
context: Context,
comptime callback: fn (
context: Context,
completion: *Completion,
result: CloseError!void,
) void,
completion: *Completion,
fd: os.fd_t,
) void {
self.submit(
context,
callback,
completion,
.close,
.{ .fd = fd },
struct {
fn do_operation(ctx: Completion.Context, op: anytype) CloseError!void {
_ = ctx;
// Check if the fd is a SOCKET by seeing if getsockopt() returns ENOTSOCK
// https://stackoverflow.com/a/50981652
const socket = @ptrCast(os.socket_t, op.fd);
getsockoptError(socket) catch |err| switch (err) {
error.FileDescriptorNotASocket => return os.windows.CloseHandle(op.fd),
else => {},
};
os.closeSocket(socket);
}
},
);
}
pub const TimeoutError = error{Canceled} || os.UnexpectedError;
pub fn timeout(
self: *IO,
comptime Context: type,
context: Context,
comptime callback: fn (
context: Context,
completion: *Completion,
result: TimeoutError!void,
) void,
completion: *Completion,
nanoseconds: u63,
) void {
self.submit(
context,
callback,
completion,
.timeout,
.{ .deadline = self.timer.monotonic() + nanoseconds },
struct {
fn do_operation(ctx: Completion.Context, op: anytype) TimeoutError!void {
_ = ctx;
_ = op;
return;
}
},
);
}
pub const INVALID_SOCKET = os.windows.ws2_32.INVALID_SOCKET;
/// Creates a socket that can be used for async operations with the IO instance.
pub fn open_socket(self: *IO, family: u32, sock_type: u32, protocol: u32) !os.socket_t {
// SOCK_NONBLOCK | SOCK_CLOEXEC
var flags: os.windows.DWORD = 0;
flags |= os.windows.ws2_32.WSA_FLAG_OVERLAPPED;
flags |= os.windows.ws2_32.WSA_FLAG_NO_HANDLE_INHERIT;
const socket = try os.windows.WSASocketW(
@bitCast(i32, family),
@bitCast(i32, sock_type),
@bitCast(i32, protocol),
null,
0,
flags,
);
errdefer os.closeSocket(socket);
const socket_iocp = try os.windows.CreateIoCompletionPort(socket, self.iocp, 0, 0);
assert(socket_iocp == self.iocp);
// Ensure that synchronous IO completion doesn't queue an unneeded overlapped
// and that the event for the socket (WaitForSingleObject) doesn't need to be set.
var mode: os.windows.BYTE = 0;
mode |= os.windows.FILE_SKIP_COMPLETION_PORT_ON_SUCCESS;
mode |= os.windows.FILE_SKIP_SET_EVENT_ON_HANDLE;
const handle = @ptrCast(os.windows.HANDLE, socket);
try os.windows.SetFileCompletionNotificationModes(handle, mode);
return socket;
}
/// Opens a directory with read only access.
pub fn open_dir(dir_path: [:0]const u8) !os.fd_t {
const dir = try std.fs.cwd().openDirZ(dir_path, .{});
return dir.fd;
}
/// Opens or creates a journal file:
/// - For reading and writing.
/// - For Direct I/O (required on windows).
/// - Obtains an advisory exclusive lock to the file descriptor.
/// - Allocates the file contiguously on disk if this is supported by the file system.
/// - Ensures that the file data is durable on disk.
/// The caller is responsible for ensuring that the parent directory inode is durable.
/// - Verifies that the file size matches the expected file size before returning.
pub fn open_file(
self: *IO,
dir_handle: os.fd_t,
relative_path: [:0]const u8,
size: u64,
must_create: bool,
) !os.fd_t {
_ = self;
assert(relative_path.len > 0);
assert(size >= config.sector_size);
assert(size % config.sector_size == 0);
const path_w = try os.windows.sliceToPrefixedFileW(relative_path);
// FILE_CREATE = O_CREAT | O_EXCL
var creation_disposition: os.windows.DWORD = 0;
if (must_create) {
log.info("creating \"{s}\"...", .{relative_path});
creation_disposition = os.windows.FILE_CREATE;
} else {
log.info("opening \"{s}\"...", .{relative_path});
creation_disposition = os.windows.OPEN_EXISTING;
}
// O_EXCL
var shared_mode: os.windows.DWORD = 0;
// O_RDWR
var access_mask: os.windows.DWORD = 0;
access_mask |= os.windows.GENERIC_READ;
access_mask |= os.windows.GENERIC_WRITE;
// O_DIRECT | O_DSYNC
var attributes: os.windows.DWORD = 0;
attributes |= os.windows.FILE_FLAG_NO_BUFFERING;
attributes |= os.windows.FILE_FLAG_WRITE_THROUGH;
// This is critical as we rely on O_DSYNC for fsync() whenever we write to the file:
assert((attributes & os.windows.FILE_FLAG_WRITE_THROUGH) > 0);
// TODO: Add ReadFileEx/WriteFileEx support.
// Not currently needed for O_DIRECT disk IO.
// attributes |= os.windows.FILE_FLAG_OVERLAPPED;
const handle = os.windows.kernel32.CreateFileW(
path_w.span(),
access_mask,
shared_mode,
null, // no security attributes required
creation_disposition,
attributes,
null, // no existing template file
);
if (handle == os.windows.INVALID_HANDLE_VALUE) {
return switch (os.windows.kernel32.GetLastError()) {
.ACCESS_DENIED => error.AccessDenied,
else => |err| os.windows.unexpectedError(err),
};
}
errdefer os.windows.CloseHandle(handle);
// Obtain an advisory exclusive lock
// even when we haven't given shared access to other processes.
fs_lock(handle, size) catch |err| switch (err) {
error.WouldBlock => @panic("another process holds the data file lock"),
else => return err,
};
// Ask the file system to allocate contiguous sectors for the file (if possible):
if (must_create) {
log.info("allocating {}...", .{std.fmt.fmtIntSizeBin(size)});
fs_allocate(handle, size) catch {
log.warn("file system failed to preallocate the file memory", .{});
log.info("allocating by writing to the last sector of the file instead...", .{});
const sector_size = config.sector_size;
const sector: [sector_size]u8 align(sector_size) = [_]u8{0} ** sector_size;
// Handle partial writes where the physical sector is less than a logical sector:
const write_offset = size - sector.len;
var written: usize = 0;
while (written < sector.len) {
written += try os.pwrite(handle, sector[written..], write_offset + written);
}
};
}
// The best fsync strategy is always to fsync before reading because this prevents us from
// making decisions on data that was never durably written by a previously crashed process.
// We therefore always fsync when we open the path, also to wait for any pending O_DSYNC.
// Thanks to <NAME> from FoundationDB for diving into our source and pointing this out.
try os.fsync(handle);
// We cannot fsync the directory handle on Windows.
// We have no way to open a directory with write access.
//
// try os.fsync(dir_handle);
_ = dir_handle;
const file_size = try os.windows.GetFileSizeEx(handle);
if (file_size != size) @panic("data file inode size was truncated or corrupted");
return handle;
}
fn fs_lock(handle: os.fd_t, size: u64) !void {
// TODO: Look into using SetFileIoOverlappedRange() for better unbuffered async IO perf
// NOTE: Requires SeLockMemoryPrivilege.
const kernel32 = struct {
const LOCKFILE_EXCLUSIVE_LOCK = 0x2;
const LOCKFILE_FAIL_IMMEDIATELY = 01;
extern "kernel32" fn LockFileEx(
hFile: os.windows.HANDLE,
dwFlags: os.windows.DWORD,
dwReserved: os.windows.DWORD,
nNumberOfBytesToLockLow: os.windows.DWORD,
nNumberOfBytesToLockHigh: os.windows.DWORD,
lpOverlapped: ?*os.windows.OVERLAPPED,
) callconv(os.windows.WINAPI) os.windows.BOOL;
};
// hEvent = null
// Offset & OffsetHigh = 0
var lock_overlapped = std.mem.zeroes(os.windows.OVERLAPPED);
// LOCK_EX | LOCK_NB
var lock_flags: os.windows.DWORD = 0;
lock_flags |= kernel32.LOCKFILE_EXCLUSIVE_LOCK;
lock_flags |= kernel32.LOCKFILE_FAIL_IMMEDIATELY;
const locked = kernel32.LockFileEx(
handle,
lock_flags,
0, // reserved param is always zero
@truncate(u32, size), // low bits of size
@truncate(u32, size >> 32), // high bits of size
&lock_overlapped,
);
if (locked == os.windows.FALSE) {
return switch (os.windows.kernel32.GetLastError()) {
.IO_PENDING => error.WouldBlock,
else => |err| os.windows.unexpectedError(err),
};
}
}
fn fs_allocate(handle: os.fd_t, size: u64) !void {
// TODO: Look into using SetFileValidData() instead
// NOTE: Requires SE_MANAGE_VOLUME_NAME privilege
// Move the file pointer to the start + size
const seeked = os.windows.kernel32.SetFilePointerEx(
handle,
@intCast(i64, size),
null, // no reference to new file pointer
os.windows.FILE_BEGIN,
);
if (seeked == os.windows.FALSE) {
return switch (os.windows.kernel32.GetLastError()) {
.INVALID_HANDLE => unreachable,
.INVALID_PARAMETER => unreachable,
else => |err| os.windows.unexpectedError(err),
};
}
// Mark the moved file pointer (start + size) as the physical EOF.
const allocated = os.windows.kernel32.SetEndOfFile(handle);
if (allocated == os.windows.FALSE) {
const err = os.windows.kernel32.GetLastError();
return os.windows.unexpectedError(err);
}
}
};
// TODO: use os.getsockoptError when fixed for windows in stdlib
fn getsockoptError(socket: os.socket_t) IO.ConnectError!void {
var err_code: u32 = undefined;
var size: i32 = @sizeOf(u32);
const rc = os.windows.ws2_32.getsockopt(
socket,
os.SOL.SOCKET,
os.SO.ERROR,
std.mem.asBytes(&err_code),
&size,
);
if (rc != 0) {
switch (os.windows.ws2_32.WSAGetLastError()) {
.WSAENETDOWN => return error.NetworkUnreachable,
.WSANOTINITIALISED => unreachable, // WSAStartup() was never called
.WSAEFAULT => unreachable, // The address pointed to by optval or optlen is not in a valid part of the process address space.
.WSAEINVAL => unreachable, // The level parameter is unknown or invalid
.WSAENOPROTOOPT => unreachable, // The option is unknown at the level indicated.
.WSAENOTSOCK => return error.FileDescriptorNotASocket,
else => |err| return os.windows.unexpectedWSAError(err),
}
}
assert(size == 4);
if (err_code == 0)
return;
const ws_err = @intToEnum(os.windows.ws2_32.WinsockError, @intCast(u16, err_code));
return switch (ws_err) {
.WSAEACCES => error.PermissionDenied,
.WSAEADDRINUSE => error.AddressInUse,
.WSAEADDRNOTAVAIL => error.AddressNotAvailable,
.WSAEAFNOSUPPORT => error.AddressFamilyNotSupported,
.WSAEALREADY => error.ConnectionPending,
.WSAEBADF => unreachable,
.WSAECONNREFUSED => error.ConnectionRefused,
.WSAEFAULT => unreachable,
.WSAEISCONN => unreachable, // error.AlreadyConnected,
.WSAENETUNREACH => error.NetworkUnreachable,
.WSAENOTSOCK => error.FileDescriptorNotASocket,
.WSAEPROTOTYPE => unreachable,
.WSAETIMEDOUT => error.ConnectionTimedOut,
.WSAECONNRESET => error.ConnectionResetByPeer,
else => |e| os.windows.unexpectedWSAError(e),
};
} | src/io/windows.zig |
const std = @import("std");
const c = @import("../c.zig");
const gui = @import("../gui.zig");
const widgets = @import("../gui/widgets.zig");
const Primitive = @import("primitive.zig").Primitive;
const Material = @import("material.zig").Material;
pub const Shape = struct {
const Self = @This();
prim: Primitive,
mat: u32, // Index into the materials list
pub fn new_sphere(center: c.vec3, radius: f32, mat: u32) Self {
return Self{
.prim = Primitive.new_sphere(center, radius),
.mat = mat,
};
}
pub fn new_infinite_plane(normal: c.vec3, offset: f32, mat: u32) Self {
return Self{
.prim = Primitive.new_infinite_plane(normal, offset),
.mat = mat,
};
}
pub fn new_finite_plane(normal: c.vec3, offset: f32, q: c.vec3, bounds: c.vec4, mat: u32) Self {
return Self{
.prim = Primitive.new_finite_plane(normal, offset, q, bounds),
.mat = mat,
};
}
pub fn new_capped_cylinder(start: c.vec3, end: c.vec3, r: f32, mat: u32) Self {
return Self{
.prim = Primitive.new_capped_cylinder(start, end, r),
.mat = mat,
};
}
pub fn new_cylinder(pos: c.vec3, dir: c.vec3, r: f32) Self {
return Self{
.prim = Primitive.new_cylinder(pos, dir, r),
.mat = mat,
};
}
pub fn encode(self: Self, buf: *std.ArrayList(c.vec4)) !void {
try self.prim.encode(buf);
}
pub fn draw_gui(self: *Self, num_materials: usize) !bool {
var changed = false;
if (widgets.draw_enum_combo(Primitive, self.prim)) |s| {
changed = true;
switch (s) {
.Sphere => self.prim = .{
.Sphere = .{
.center = .{ .x = 0, .y = 0, .z = 0 },
.radius = 0.5,
},
},
.InfinitePlane => self.prim = .{
.InfinitePlane = .{
.normal = .{ .x = 0, .y = 0, .z = 1 },
.offset = 0,
},
},
.FinitePlane => self.prim = .{
.FinitePlane = .{
.normal = .{ .x = 0, .y = 0, .z = 1 },
.offset = 0,
.q = .{ .x = 1, .y = 0, .z = 0 },
.bounds = .{ .x = -1, .y = 1, .z = -1, .w = 1 },
},
},
.Cylinder => self.prim = .{
.Cylinder = .{
.pos = .{ .x = 0, .y = 0, .z = 0 },
.dir = .{ .x = 0, .y = 1, .z = 0 },
.radius = 0.2,
},
},
.CappedCylinder => self.prim = .{
.CappedCylinder = .{
.pos = .{ .x = 0, .y = 0, .z = 0 },
.end = .{ .x = 0.5, .y = 1, .z = 0 },
.radius = 0.2,
},
},
}
}
var mat: c_int = @intCast(c_int, self.mat);
c.igPushItemWidth(c.igGetWindowWidth() * 0.6);
if (c.igDragInt("mat", &mat, 0.1, 0, @intCast(c_int, num_materials - 1), "%i", 0)) {
self.mat = @intCast(u32, mat);
changed = true;
}
changed = self.prim.draw_gui() or changed;
c.igPopItemWidth();
return changed;
}
}; | src/scene/shape.zig |
const std = @import("std");
const c = @import("../c.zig");
const shaderc = @import("../shaderc.zig");
const util = @import("../util.zig");
const Font = @import("font.zig").Font;
const FONT_SIZE: u32 = 18;
pub const Backend = struct {
const Self = @This();
alloc: *std.mem.Allocator,
initialized: bool = false,
pixel_density: f32,
font_ttf: []u8,
device: c.WGPUDeviceId,
queue: c.WGPUQueueId,
uniform_buf: c.WGPUBufferId,
bind_group_layout: c.WGPUBindGroupLayoutId,
// The font texture lives in io.TexID, but we save it here so that we
// can destroy it when the Gui is deleted
font_tex: c.WGPUTextureId,
font_tex_view: c.WGPUTextureViewId,
tex_sampler: c.WGPUSamplerId, // Used for any texture
// These buffers are dynamically resized as needed.
//
// This requires recreating the bind group, so we don't shrink them
// if the GUI buffer size becomes smaller.
vertex_buf: c.WGPUBufferId,
vertex_buf_size: usize,
index_buf: c.WGPUBufferId,
index_buf_size: usize,
render_pipeline: c.WGPURenderPipelineId,
pub fn init(alloc: *std.mem.Allocator, window: *c.GLFWwindow, device: c.WGPUDeviceId) !Self {
// TIME FOR WGPU
var arena = std.heap.ArenaAllocator.init(alloc);
const tmp_alloc: *std.mem.Allocator = &arena.allocator;
defer arena.deinit();
// We lie and pretend to be OpenGL here
_ = c.ImGui_ImplGlfw_InitForOpenGL(window, true);
// Use the Inconsolata font for the GUI, instead of Proggy Clean
var io = c.igGetIO() orelse std.debug.panic("Could not get io\n", .{});
// We need a non-const pointer here, so duplicate the data (which may
// be embedded in the executable if this is a release image, so it
// must be const).
const font_ttf: []u8 = try alloc.dupe(
u8,
try util.file_contents(&arena, "font/Inconsolata-Regular.ttf"),
);
////////////////////////////////////////////////////////////////////////
// This is the only available queue right now
const queue = c.wgpu_device_get_default_queue(device);
// Build the shaders using shaderc
const vert_spv = try shaderc.build_shader_from_file(tmp_alloc, "shaders/gui.vert");
const vert_shader = c.wgpu_device_create_shader_module(
device,
&(c.WGPUShaderModuleDescriptor){
.label = "",
.bytes = vert_spv.ptr,
.length = vert_spv.len,
.flags = c.WGPUShaderFlags_VALIDATION,
},
);
defer c.wgpu_shader_module_destroy(vert_shader);
const frag_spv = try shaderc.build_shader_from_file(tmp_alloc, "shaders/gui.frag");
const frag_shader = c.wgpu_device_create_shader_module(
device,
&(c.WGPUShaderModuleDescriptor){
.label = "",
.bytes = frag_spv.ptr,
.length = frag_spv.len,
.flags = c.WGPUShaderFlags_VALIDATION,
},
);
defer c.wgpu_shader_module_destroy(frag_shader);
////////////////////////////////////////////////////////////////////////
// Uniform buffers
const uniform_buf = c.wgpu_device_create_buffer(
device,
&(c.WGPUBufferDescriptor){
.label = "gui uniforms",
.size = @sizeOf(f32) * 4 * 4, // mat4
.usage = c.WGPUBufferUsage_UNIFORM | c.WGPUBufferUsage_COPY_DST,
.mapped_at_creation = false,
},
);
///////////////////////////////////////////////////////////////////////
// Texture sampler (the font texture is handled above)
const tex_sampler = c.wgpu_device_create_sampler(device, &(c.WGPUSamplerDescriptor){
.next_in_chain = null,
.label = "gui tex sampler",
.address_mode_u = c.WGPUAddressMode._ClampToEdge,
.address_mode_v = c.WGPUAddressMode._ClampToEdge,
.address_mode_w = c.WGPUAddressMode._ClampToEdge,
.mag_filter = c.WGPUFilterMode._Nearest,
.min_filter = c.WGPUFilterMode._Nearest,
.mipmap_filter = c.WGPUFilterMode._Nearest,
.lod_min_clamp = 0.0,
.lod_max_clamp = std.math.f32_max,
.compare = c.WGPUCompareFunction_Undefined,
.border_color = c.WGPUSamplerBorderColor._TransparentBlack,
});
////////////////////////////////////////////////////////////////////////////
// Bind groups
const bind_group_layout_entries = [_]c.WGPUBindGroupLayoutEntry{
(c.WGPUBindGroupLayoutEntry){ // Uniforms buffer
.binding = 0,
.visibility = c.WGPUShaderStage_VERTEX,
.ty = c.WGPUBindingType_UniformBuffer,
.has_dynamic_offset = false,
.min_buffer_binding_size = 0,
.multisampled = undefined,
.filtering = undefined,
.view_dimension = undefined,
.texture_component_type = undefined,
.storage_texture_format = undefined,
.count = undefined,
},
(c.WGPUBindGroupLayoutEntry){
.binding = 1,
.visibility = c.WGPUShaderStage_FRAGMENT,
.ty = c.WGPUBindingType_SampledTexture,
.multisampled = false,
.filtering = false,
.view_dimension = c.WGPUTextureViewDimension._D2,
.texture_component_type = c.WGPUTextureComponentType_Float,
.storage_texture_format = c.WGPUTextureFormat._Rgba8Unorm,
.count = undefined,
.has_dynamic_offset = undefined,
.min_buffer_binding_size = undefined,
},
(c.WGPUBindGroupLayoutEntry){
.binding = 2,
.visibility = c.WGPUShaderStage_FRAGMENT,
.ty = c.WGPUBindingType_Sampler,
.multisampled = undefined,
.filtering = undefined,
.view_dimension = undefined,
.texture_component_type = undefined,
.storage_texture_format = undefined,
.count = undefined,
.has_dynamic_offset = undefined,
.min_buffer_binding_size = undefined,
},
};
const bind_group_layout = c.wgpu_device_create_bind_group_layout(
device,
&(c.WGPUBindGroupLayoutDescriptor){
.label = "gui bind group",
.entries = &bind_group_layout_entries,
.entries_length = bind_group_layout_entries.len,
},
);
const bind_group_layouts = [_]c.WGPUBindGroupId{bind_group_layout};
////////////////////////////////////////////////////////////////////////////
// Vertex buffers (new!)
const vertex_buffer_attributes = [_]c.WGPUVertexAttributeDescriptor{
.{
.offset = @byteOffsetOf(c.ImDrawVert, "pos"),
.format = c.WGPUVertexFormat._Float2,
.shader_location = 0,
},
.{
.offset = @byteOffsetOf(c.ImDrawVert, "uv"),
.format = c.WGPUVertexFormat._Float2,
.shader_location = 1,
},
.{
.offset = @byteOffsetOf(c.ImDrawVert, "col"),
.format = c.WGPUVertexFormat._Uchar4Norm,
.shader_location = 2,
},
};
const vertex_buffer_layout_entries = [_]c.WGPUVertexBufferDescriptor{
.{
.stride = @sizeOf(c.ImDrawVert),
.step_mode = c.WGPUInputStepMode._Vertex,
.attributes = &vertex_buffer_attributes,
.attributes_length = vertex_buffer_attributes.len,
},
};
////////////////////////////////////////////////////////////////////////////
// Render pipelines
const pipeline_layout = c.wgpu_device_create_pipeline_layout(
device,
&(c.WGPUPipelineLayoutDescriptor){
.label = "imgui backend pipeline layout",
.bind_group_layouts = &bind_group_layouts,
.bind_group_layouts_length = bind_group_layouts.len,
},
);
defer c.wgpu_pipeline_layout_destroy(pipeline_layout);
const render_pipeline = c.wgpu_device_create_render_pipeline(
device,
&(c.WGPURenderPipelineDescriptor){
.label = "imgui backend pipeline",
.layout = pipeline_layout,
.vertex_stage = (c.WGPUProgrammableStageDescriptor){
.module = vert_shader,
.entry_point = "main",
},
.fragment_stage = &(c.WGPUProgrammableStageDescriptor){
.module = frag_shader,
.entry_point = "main",
},
.rasterization_state = &(c.WGPURasterizationStateDescriptor){
.front_face = c.WGPUFrontFace._Ccw,
.cull_mode = c.WGPUCullMode._None,
.depth_bias = 0,
.depth_bias_slope_scale = 0.0,
.depth_bias_clamp = 0.0,
.polygon_mode = c.WGPUPolygonMode._Fill,
.clamp_depth = false,
},
.primitive_topology = c.WGPUPrimitiveTopology._TriangleList,
.color_states = &(c.WGPUColorStateDescriptor){
.format = c.WGPUTextureFormat._Bgra8Unorm,
.alpha_blend = (c.WGPUBlendDescriptor){
.src_factor = c.WGPUBlendFactor._SrcAlpha,
.dst_factor = c.WGPUBlendFactor._OneMinusSrcAlpha,
.operation = c.WGPUBlendOperation._Add,
},
.color_blend = (c.WGPUBlendDescriptor){
.src_factor = c.WGPUBlendFactor._SrcAlpha,
.dst_factor = c.WGPUBlendFactor._OneMinusSrcAlpha,
.operation = c.WGPUBlendOperation._Add,
},
.write_mask = c.WGPUColorWrite_ALL,
},
.color_states_length = 1,
.depth_stencil_state = null,
.vertex_state = (c.WGPUVertexStateDescriptor){
.index_format = c.WGPUIndexFormat_Uint32,
.vertex_buffers = &vertex_buffer_layout_entries,
.vertex_buffers_length = vertex_buffer_layout_entries.len,
},
.sample_count = 1,
.sample_mask = 0,
.alpha_to_coverage = false,
},
);
////////////////////////////////////////////////////////////////////////
var out = Self{
.alloc = alloc,
.pixel_density = 2,
.font_ttf = font_ttf,
.device = device,
.queue = queue,
.bind_group_layout = bind_group_layout,
// populated in rebuild_font below
.font_tex = undefined,
.font_tex_view = undefined,
.tex_sampler = tex_sampler,
.uniform_buf = uniform_buf,
// Populated in ensure_buf_size_ below
.vertex_buf = undefined,
.vertex_buf_size = 0,
.index_buf = undefined,
.index_buf_size = 0,
.render_pipeline = render_pipeline,
};
// Create the initial vertices and bind groups
out.ensure_buf_size(@sizeOf(c.ImDrawVert), @sizeOf(c.ImDrawIdx));
out.rebuild_font(io, 1);
out.initialized = true;
return out;
}
fn bind_group_for(self: *const Self, tex_view: c.WGPUTextureViewId) c.WGPUBindGroupId {
const bind_group_entries = [_]c.WGPUBindGroupEntry{
(c.WGPUBindGroupEntry){
.binding = 0,
.buffer = self.uniform_buf,
.offset = 0,
.size = @sizeOf(f32) * 4 * 4,
.sampler = 0, // None
.texture_view = 0, // None
},
(c.WGPUBindGroupEntry){
.binding = 1,
.texture_view = tex_view,
.sampler = 0, // None
.buffer = 0, // None
.offset = undefined,
.size = undefined,
},
(c.WGPUBindGroupEntry){
.binding = 2,
.sampler = self.tex_sampler,
.texture_view = 0, // None
.buffer = 0, // None
.offset = undefined,
.size = undefined,
},
};
return c.wgpu_device_create_bind_group(
self.device,
&(c.WGPUBindGroupDescriptor){
.label = "gui bind group",
.layout = self.bind_group_layout,
.entries = &bind_group_entries,
.entries_length = bind_group_entries.len,
},
);
}
fn rebuild_font(self: *Self, io: [*c]c.ImGuiIO, pixel_density: f32) void {
// Clear any existing font atlas
c.ImFontAtlas_Clear(io.*.Fonts);
// We need a non-const pointer here, so duplicate the data (which may
// be embedded in the executable if this is a release image, so it
// must be const).
var font_config = c.ImFontConfig_ImFontConfig();
defer c.ImFontConfig_destroy(font_config);
font_config.*.FontDataOwnedByAtlas = false;
_ = c.ImFontAtlas_AddFontFromMemoryTTF(
io.*.Fonts,
@ptrCast(*c_void, self.font_ttf.ptr),
@intCast(c_int, self.font_ttf.len),
@intToFloat(f32, FONT_SIZE) * pixel_density,
font_config,
null,
);
//_ = c.igFt_BuildFontAtlas(io.*.Fonts, 0);
io.*.FontGlobalScale = 1 / pixel_density;
self.pixel_density = pixel_density;
///////////////////////////////////////////////////////////////////////
// Font texture
const font = Font.from_io(io);
if (self.initialized) {
c.wgpu_texture_destroy(self.font_tex, true);
c.wgpu_texture_view_destroy(self.font_tex_view, true);
}
self.font_tex = c.wgpu_device_create_texture(
self.device,
&(c.WGPUTextureDescriptor){
.size = .{
.width = font.width,
.height = font.height,
.depth = 1,
},
.mip_level_count = 1,
.sample_count = 1,
.dimension = c.WGPUTextureDimension._D2,
.format = c.WGPUTextureFormat._Rgba8Unorm,
.usage = (c.WGPUTextureUsage_COPY_DST |
c.WGPUTextureUsage_SAMPLED),
.label = "gui font tex",
},
);
self.font_tex_view = c.wgpu_texture_create_view(
self.font_tex,
&(c.WGPUTextureViewDescriptor){
.label = "font font view",
.dimension = c.WGPUTextureViewDimension._D2,
.format = c.WGPUTextureFormat._Rgba8Unorm,
.aspect = c.WGPUTextureAspect._All,
.base_mip_level = 0,
.level_count = 1,
.base_array_layer = 0,
.array_layer_count = 1,
},
);
const font_tex_size = (c.WGPUExtent3d){
.width = font.width,
.height = font.height,
.depth = 1,
};
c.wgpu_queue_write_texture(
self.queue,
&(c.WGPUTextureCopyView){
.texture = self.font_tex,
.mip_level = 0,
.origin = (c.WGPUOrigin3d){ .x = 0, .y = 0, .z = 0 },
},
@ptrCast([*]const u8, font.pixels),
font.width * font.height * font.bytes_per_pixel,
&(c.WGPUTextureDataLayout){
.offset = 0,
.bytes_per_row = font.width * font.bytes_per_pixel,
.rows_per_image = font.height,
},
&font_tex_size,
);
io.*.Fonts.*.TexID = @intToPtr(*c_void, self.font_tex_view);
}
pub fn deinit(self: *Self) void {
self.alloc.free(self.font_ttf);
c.wgpu_buffer_destroy(self.uniform_buf, true);
c.wgpu_bind_group_layout_destroy(self.bind_group_layout);
c.wgpu_texture_destroy(self.font_tex, true);
c.wgpu_texture_view_destroy(self.font_tex_view, true);
c.wgpu_sampler_destroy(self.tex_sampler);
c.wgpu_buffer_destroy(self.vertex_buf, true);
c.wgpu_buffer_destroy(self.index_buf, true);
c.wgpu_render_pipeline_destroy(self.render_pipeline);
}
fn ensure_buf_size(self: *Self, vtx_bytes: usize, idx_bytes: usize) void {
if (vtx_bytes <= self.vertex_buf_size and idx_bytes <= self.index_buf_size) {
return;
}
if (vtx_bytes > self.vertex_buf_size) {
// Regenerate vertex buf
if (self.initialized) {
c.wgpu_buffer_destroy(self.vertex_buf, true);
}
self.vertex_buf_size = vtx_bytes;
self.vertex_buf = c.wgpu_device_create_buffer(
self.device,
&(c.WGPUBufferDescriptor){
.label = "gui vertices",
.size = vtx_bytes,
.usage = c.WGPUBufferUsage_VERTEX | c.WGPUBufferUsage_COPY_DST,
.mapped_at_creation = false,
},
);
}
if (idx_bytes > self.index_buf_size) {
// Regenerate index buf
if (self.initialized) {
c.wgpu_buffer_destroy(self.index_buf, true);
}
self.index_buf = c.wgpu_device_create_buffer(
self.device,
&(c.WGPUBufferDescriptor){
.label = "gui indexes",
.size = idx_bytes,
.usage = c.WGPUBufferUsage_INDEX | c.WGPUBufferUsage_COPY_DST,
.mapped_at_creation = false,
},
);
self.index_buf_size = idx_bytes;
}
}
pub fn new_frame(self: *Self) void {
const io = c.igGetIO() orelse std.debug.panic("Could not get io\n", .{});
const pixel_density = io.*.DisplayFramebufferScale.x;
if (pixel_density != self.pixel_density) {
self.rebuild_font(io, pixel_density);
}
}
fn setup_render_state(self: *const Self, draw_data: [*c]c.ImDrawData) void {
const L = draw_data.*.DisplayPos.x;
const R = draw_data.*.DisplayPos.x + draw_data.*.DisplaySize.x;
const T = draw_data.*.DisplayPos.y;
const B = draw_data.*.DisplayPos.y + draw_data.*.DisplaySize.y;
const ortho_projection: [4][4]f32 = .{
.{ 2.0 / (R - L), 0.0, 0.0, 0.0 },
.{ 0.0, 2.0 / (T - B), 0.0, 0.0 },
.{ 0.0, 0.0, -1.0, 0.0 },
.{ (R + L) / (L - R), (T + B) / (B - T), 0.0, 1.0 },
};
std.debug.assert(@sizeOf(@TypeOf(ortho_projection)) == 4 * 4 * 4);
c.wgpu_queue_write_buffer(
self.queue,
self.uniform_buf,
0,
@ptrCast([*c]const u8, &ortho_projection),
@sizeOf(@TypeOf(ortho_projection)),
);
return;
}
pub fn render_draw_data(
self: *Self,
next_texture: c.WGPUOption_TextureViewId,
cmd_encoder: c.WGPUCommandEncoderId,
draw_data: [*c]c.ImDrawData,
) void {
self.setup_render_state(draw_data);
// Will project scissor/clipping rectangles into framebuffer space
const clip_off = draw_data.*.DisplayPos; // (0,0) unless using multi-viewports
const clip_scale = draw_data.*.FramebufferScale; // (1,1) unless using retina display which are often (2,2)
// Render to the main view
const color_attachments = [_]c.WGPUColorAttachmentDescriptor{
(c.WGPUColorAttachmentDescriptor){
.attachment = next_texture,
.resolve_target = 0,
.channel = (c.WGPUPassChannel_Color){
.load_op = c.WGPULoadOp._Load,
.store_op = c.WGPUStoreOp._Store,
.clear_value = (c.WGPUColor){
.r = 0.0,
.g = 0.0,
.b = 0.0,
.a = 1.0,
},
.read_only = false,
},
},
};
// We'll pack all of the draw buffer data into our buffers here,
// to avoid using invalid data in the case of multiple command lists.
var sum_vtx_buf_size: usize = 0;
var sum_idx_buf_size: usize = 0;
var n: usize = 0;
while (n < draw_data.*.CmdListsCount) : (n += 1) {
const cmd_list = draw_data.*.CmdLists[n];
sum_vtx_buf_size += @intCast(usize, cmd_list.*.VtxBuffer.Size) * @sizeOf(c.ImDrawVert);
sum_idx_buf_size += @intCast(usize, cmd_list.*.IdxBuffer.Size) * @sizeOf(c.ImDrawIdx);
}
self.ensure_buf_size(sum_vtx_buf_size, sum_idx_buf_size);
var vtx_buf_offset: usize = 0;
var idx_buf_offset: usize = 0;
n = 0;
while (n < draw_data.*.CmdListsCount) : (n += 1) {
const cmd_list = draw_data.*.CmdLists[n];
// We've already copied buffer data above
var cmd_i: usize = 0;
// Copy this command list data into the buffers, then accumulate
// offset after the draw loop
const vtx_buf_size = @intCast(usize, cmd_list.*.VtxBuffer.Size) * @sizeOf(c.ImDrawVert);
const idx_buf_size = @intCast(usize, cmd_list.*.IdxBuffer.Size) * @sizeOf(c.ImDrawIdx);
c.wgpu_queue_write_buffer(
self.queue,
self.vertex_buf,
vtx_buf_offset,
@ptrCast([*c]const u8, cmd_list.*.VtxBuffer.Data),
vtx_buf_size,
);
c.wgpu_queue_write_buffer(
self.queue,
self.index_buf,
idx_buf_offset,
@ptrCast([*c]const u8, cmd_list.*.IdxBuffer.Data),
idx_buf_size,
);
while (cmd_i < cmd_list.*.CmdBuffer.Size) : (cmd_i += 1) {
const pcmd = &cmd_list.*.CmdBuffer.Data[cmd_i];
std.debug.assert(pcmd.*.UserCallback == null);
const rpass = c.wgpu_command_encoder_begin_render_pass(
cmd_encoder,
&(c.WGPURenderPassDescriptor){
.label = "backend rpass",
.color_attachments = &color_attachments,
.color_attachments_length = color_attachments.len,
.depth_stencil_attachment = null,
},
);
const bind_group = self.bind_group_for(@intCast(c.WGPUTextureViewId, @ptrToInt(pcmd.*.TextureId)));
defer c.wgpu_bind_group_destroy(bind_group);
c.wgpu_render_pass_set_pipeline(rpass, self.render_pipeline);
c.wgpu_render_pass_set_vertex_buffer(
rpass,
0,
self.vertex_buf,
vtx_buf_offset,
vtx_buf_size,
);
c.wgpu_render_pass_set_index_buffer(
rpass,
self.index_buf,
c.WGPUIndexFormat_Uint32,
@intCast(u32, idx_buf_offset),
idx_buf_size,
);
c.wgpu_render_pass_set_bind_group(rpass, 0, bind_group, null, 0);
const clip_rect_x = (pcmd.*.ClipRect.x - clip_off.x) * clip_scale.x;
const clip_rect_y = (pcmd.*.ClipRect.y - clip_off.y) * clip_scale.y;
const clip_rect_z = (pcmd.*.ClipRect.z - clip_off.x) * clip_scale.x;
const clip_rect_w = (pcmd.*.ClipRect.w - clip_off.y) * clip_scale.y;
c.wgpu_render_pass_set_scissor_rect(
rpass,
@floatToInt(u32, clip_rect_x),
@floatToInt(u32, clip_rect_y),
@floatToInt(u32, clip_rect_z - clip_rect_x),
@floatToInt(u32, clip_rect_w - clip_rect_y),
);
c.wgpu_render_pass_draw_indexed(rpass, pcmd.*.ElemCount, 1, pcmd.*.IdxOffset, 0, 0);
c.wgpu_render_pass_end_pass(rpass);
}
vtx_buf_offset += vtx_buf_size;
idx_buf_offset += idx_buf_size;
}
}
}; | src/gui/backend.zig |
pub const GuiRenderer = @This();
const std = @import("std");
const assert = std.debug.assert;
const zwin32 = @import("zwin32");
const w32 = zwin32.base;
const d3d12 = zwin32.d3d12;
const hrPanic = zwin32.hrPanic;
const hrPanicOnFail = zwin32.hrPanicOnFail;
const zd3d12 = @import("zd3d12");
const c = @import("common.zig").c;
font: zd3d12.ResourceHandle,
font_srv: d3d12.CPU_DESCRIPTOR_HANDLE,
pipeline: zd3d12.PipelineHandle,
vb: [zd3d12.GraphicsContext.max_num_buffered_frames]zd3d12.ResourceHandle,
ib: [zd3d12.GraphicsContext.max_num_buffered_frames]zd3d12.ResourceHandle,
vb_cpu_addr: [zd3d12.GraphicsContext.max_num_buffered_frames][]align(8) u8,
ib_cpu_addr: [zd3d12.GraphicsContext.max_num_buffered_frames][]align(8) u8,
pub fn init(
arena: std.mem.Allocator,
gctx: *zd3d12.GraphicsContext,
num_msaa_samples: u32,
comptime content_dir: []const u8,
) GuiRenderer {
assert(gctx.is_cmdlist_opened);
assert(c.igGetCurrentContext() != null);
const io = c.igGetIO().?;
_ = c.ImFontAtlas_AddFontFromFileTTF(io.*.Fonts, content_dir ++ "Roboto-Medium.ttf", 25.0, null, null);
const font_info = blk: {
var pp: [*c]u8 = undefined;
var ww: i32 = undefined;
var hh: i32 = undefined;
c.ImFontAtlas_GetTexDataAsRGBA32(io.*.Fonts, &pp, &ww, &hh, null);
break :blk .{
.pixels = pp[0..@intCast(usize, ww * hh * 4)],
.width = @intCast(u32, ww),
.height = @intCast(u32, hh),
};
};
const font = gctx.createCommittedResource(
.DEFAULT,
d3d12.HEAP_FLAG_NONE,
&d3d12.RESOURCE_DESC.initTex2d(.R8G8B8A8_UNORM, font_info.width, font_info.height, 1),
d3d12.RESOURCE_STATE_COPY_DEST,
null,
) catch |err| hrPanic(err);
gctx.updateTex2dSubresource(font, 0, font_info.pixels, font_info.width * 4);
gctx.addTransitionBarrier(font, d3d12.RESOURCE_STATE_PIXEL_SHADER_RESOURCE);
const font_srv = gctx.allocateCpuDescriptors(.CBV_SRV_UAV, 1);
gctx.device.CreateShaderResourceView(gctx.lookupResource(font).?, null, font_srv);
const pipeline = blk: {
const input_layout_desc = [_]d3d12.INPUT_ELEMENT_DESC{
d3d12.INPUT_ELEMENT_DESC.init("POSITION", 0, .R32G32_FLOAT, 0, 0, .PER_VERTEX_DATA, 0),
d3d12.INPUT_ELEMENT_DESC.init("_Uv", 0, .R32G32_FLOAT, 0, 8, .PER_VERTEX_DATA, 0),
d3d12.INPUT_ELEMENT_DESC.init("_Color", 0, .R8G8B8A8_UNORM, 0, 16, .PER_VERTEX_DATA, 0),
};
var pso_desc = d3d12.GRAPHICS_PIPELINE_STATE_DESC.initDefault();
pso_desc.RasterizerState.CullMode = .NONE;
pso_desc.DepthStencilState.DepthEnable = w32.FALSE;
pso_desc.BlendState.RenderTarget[0].BlendEnable = w32.TRUE;
pso_desc.BlendState.RenderTarget[0].SrcBlend = .SRC_ALPHA;
pso_desc.BlendState.RenderTarget[0].DestBlend = .INV_SRC_ALPHA;
pso_desc.BlendState.RenderTarget[0].BlendOp = .ADD;
pso_desc.BlendState.RenderTarget[0].SrcBlendAlpha = .INV_SRC_ALPHA;
pso_desc.BlendState.RenderTarget[0].DestBlendAlpha = .ZERO;
pso_desc.BlendState.RenderTarget[0].BlendOpAlpha = .ADD;
pso_desc.InputLayout = .{
.pInputElementDescs = &input_layout_desc,
.NumElements = input_layout_desc.len,
};
pso_desc.RTVFormats[0] = .R8G8B8A8_UNORM;
pso_desc.NumRenderTargets = 1;
pso_desc.BlendState.RenderTarget[0].RenderTargetWriteMask = 0xf;
pso_desc.PrimitiveTopologyType = .TRIANGLE;
pso_desc.SampleDesc = .{ .Count = num_msaa_samples, .Quality = 0 };
break :blk gctx.createGraphicsShaderPipeline(
arena,
&pso_desc,
content_dir ++ "shaders/imgui.vs.cso",
content_dir ++ "shaders/imgui.ps.cso",
);
};
return GuiRenderer{
.font = font,
.font_srv = font_srv,
.pipeline = pipeline,
.vb = .{.{}} ** zd3d12.GraphicsContext.max_num_buffered_frames,
.ib = .{.{}} ** zd3d12.GraphicsContext.max_num_buffered_frames,
.vb_cpu_addr = [_][]align(8) u8{&.{}} ** zd3d12.GraphicsContext.max_num_buffered_frames,
.ib_cpu_addr = [_][]align(8) u8{&.{}} ** zd3d12.GraphicsContext.max_num_buffered_frames,
};
}
pub fn deinit(gui: *GuiRenderer, gctx: *zd3d12.GraphicsContext) void {
gctx.finishGpuCommands();
gctx.destroyResource(gui.font);
for (gui.vb) |vb|
gctx.destroyResource(vb);
for (gui.ib) |ib|
gctx.destroyResource(ib);
gui.* = undefined;
}
pub fn draw(gui: *GuiRenderer, gctx: *zd3d12.GraphicsContext) void {
assert(gctx.is_cmdlist_opened);
assert(c.igGetCurrentContext() != null);
c.igRender();
const draw_data = c.igGetDrawData();
if (draw_data == null or draw_data.?.*.TotalVtxCount == 0) {
return;
}
const num_vertices = @intCast(u32, draw_data.?.*.TotalVtxCount);
const num_indices = @intCast(u32, draw_data.?.*.TotalIdxCount);
var vb = gui.vb[gctx.frame_index];
var ib = gui.ib[gctx.frame_index];
if (gctx.getResourceSize(vb) < num_vertices * @sizeOf(c.ImDrawVert)) {
gctx.destroyResource(vb);
const new_size = (num_vertices + 5_000) * @sizeOf(c.ImDrawVert);
vb = gctx.createCommittedResource(
.UPLOAD,
d3d12.HEAP_FLAG_NONE,
&d3d12.RESOURCE_DESC.initBuffer(new_size),
d3d12.RESOURCE_STATE_GENERIC_READ,
null,
) catch |err| hrPanic(err);
gui.vb[gctx.frame_index] = vb;
gui.vb_cpu_addr[gctx.frame_index] = blk: {
var ptr: ?[*]align(8) u8 = null;
hrPanicOnFail(gctx.lookupResource(vb).?.Map(
0,
&.{ .Begin = 0, .End = 0 },
@ptrCast(*?*anyopaque, &ptr),
));
break :blk ptr.?[0..new_size];
};
}
if (gctx.getResourceSize(ib) < num_indices * @sizeOf(c.ImDrawIdx)) {
gctx.destroyResource(ib);
const new_size = (num_indices + 10_000) * @sizeOf(c.ImDrawIdx);
ib = gctx.createCommittedResource(
.UPLOAD,
d3d12.HEAP_FLAG_NONE,
&d3d12.RESOURCE_DESC.initBuffer(new_size),
d3d12.RESOURCE_STATE_GENERIC_READ,
null,
) catch |err| hrPanic(err);
gui.ib[gctx.frame_index] = ib;
gui.ib_cpu_addr[gctx.frame_index] = blk: {
var ptr: ?[*]align(8) u8 = null;
hrPanicOnFail(gctx.lookupResource(ib).?.Map(
0,
&.{ .Begin = 0, .End = 0 },
@ptrCast(*?*anyopaque, &ptr),
));
break :blk ptr.?[0..new_size];
};
}
// Update vertex and index buffers.
{
var vb_slice = std.mem.bytesAsSlice(c.ImDrawVert, gui.vb_cpu_addr[gctx.frame_index]);
var ib_slice = std.mem.bytesAsSlice(c.ImDrawIdx, gui.ib_cpu_addr[gctx.frame_index]);
var vb_idx: u32 = 0;
var ib_idx: u32 = 0;
var cmdlist_idx: u32 = 0;
const num_cmdlists = @intCast(u32, draw_data.?.*.CmdListsCount);
while (cmdlist_idx < num_cmdlists) : (cmdlist_idx += 1) {
const list = draw_data.?.*.CmdLists[cmdlist_idx];
const list_vb_size = @intCast(u32, list.*.VtxBuffer.Size);
const list_ib_size = @intCast(u32, list.*.IdxBuffer.Size);
std.mem.copy(
c.ImDrawVert,
vb_slice[vb_idx .. vb_idx + list_vb_size],
list.*.VtxBuffer.Data[0..list_vb_size],
);
std.mem.copy(
c.ImDrawIdx,
ib_slice[ib_idx .. ib_idx + list_ib_size],
list.*.IdxBuffer.Data[0..list_ib_size],
);
vb_idx += list_vb_size;
ib_idx += list_ib_size;
}
}
const display_x = draw_data.?.*.DisplayPos.x;
const display_y = draw_data.?.*.DisplayPos.y;
const display_w = draw_data.?.*.DisplaySize.x;
const display_h = draw_data.?.*.DisplaySize.y;
gctx.cmdlist.RSSetViewports(1, &[_]d3d12.VIEWPORT{.{
.TopLeftX = 0.0,
.TopLeftY = 0.0,
.Width = display_w,
.Height = display_h,
.MinDepth = 0.0,
.MaxDepth = 1.0,
}});
gctx.cmdlist.IASetPrimitiveTopology(.TRIANGLELIST);
gctx.setCurrentPipeline(gui.pipeline);
{
const l = draw_data.?.*.DisplayPos.x;
const r = draw_data.?.*.DisplayPos.x + draw_data.?.*.DisplaySize.x;
const t = draw_data.?.*.DisplayPos.y;
const b = draw_data.?.*.DisplayPos.y + draw_data.?.*.DisplaySize.y;
const mem = gctx.allocateUploadMemory([4][4]f32, 1);
mem.cpu_slice[0] = [4][4]f32{
[4]f32{ 2.0 / (r - l), 0.0, 0.0, 0.0 },
[4]f32{ 0.0, 2.0 / (t - b), 0.0, 0.0 },
[4]f32{ 0.0, 0.0, 0.5, 0.0 },
[4]f32{ (r + l) / (l - r), (t + b) / (b - t), 0.5, 1.0 },
};
gctx.cmdlist.SetGraphicsRootConstantBufferView(0, mem.gpu_base);
}
gctx.cmdlist.SetGraphicsRootDescriptorTable(1, gctx.copyDescriptorsToGpuHeap(1, gui.font_srv));
gctx.cmdlist.IASetVertexBuffers(0, 1, &[_]d3d12.VERTEX_BUFFER_VIEW{.{
.BufferLocation = gctx.lookupResource(vb).?.GetGPUVirtualAddress(),
.SizeInBytes = num_vertices * @sizeOf(c.ImDrawVert),
.StrideInBytes = @sizeOf(c.ImDrawVert),
}});
gctx.cmdlist.IASetIndexBuffer(&.{
.BufferLocation = gctx.lookupResource(ib).?.GetGPUVirtualAddress(),
.SizeInBytes = num_indices * @sizeOf(c.ImDrawIdx),
.Format = if (@sizeOf(c.ImDrawIdx) == 2) .R16_UINT else .R32_UINT,
});
var global_vtx_offset: i32 = 0;
var global_idx_offset: u32 = 0;
var cmdlist_idx: u32 = 0;
const num_cmdlists = @intCast(u32, draw_data.?.*.CmdListsCount);
while (cmdlist_idx < num_cmdlists) : (cmdlist_idx += 1) {
const cmdlist = draw_data.?.*.CmdLists[cmdlist_idx];
var cmd_idx: u32 = 0;
const num_cmds = cmdlist.*.CmdBuffer.Size;
while (cmd_idx < num_cmds) : (cmd_idx += 1) {
const cmd = &cmdlist.*.CmdBuffer.Data[cmd_idx];
if (cmd.*.UserCallback != null) {
// TODO(mziulek): Call the callback.
} else {
const rect = [1]d3d12.RECT{.{
.left = @floatToInt(i32, cmd.*.ClipRect.x - display_x),
.top = @floatToInt(i32, cmd.*.ClipRect.y - display_y),
.right = @floatToInt(i32, cmd.*.ClipRect.z - display_x),
.bottom = @floatToInt(i32, cmd.*.ClipRect.w - display_y),
}};
if (rect[0].right > rect[0].left and rect[0].bottom > rect[0].top) {
gctx.cmdlist.RSSetScissorRects(1, &rect);
gctx.cmdlist.DrawIndexedInstanced(
cmd.*.ElemCount,
1,
cmd.*.IdxOffset + global_idx_offset,
@intCast(i32, cmd.*.VtxOffset) + global_vtx_offset,
0,
);
}
}
}
global_idx_offset += @intCast(u32, cmdlist.*.IdxBuffer.Size);
global_vtx_offset += cmdlist.*.VtxBuffer.Size;
}
} | libs/common/src/GuiRenderer.zig |
const std = @import("std");
const allocators = @import("allocators.zig");
const zlib = @import("zlib.zig");
const lua = @import("lua.zig");
const c = lua.c;
const L = ?*c.lua_State;
pub export fn registerUtilLib(l: L) c_int {
c.luaL_requiref(l, "util", openUtil, 1);
return 0;
}
fn openUtil(l: L) callconv(.C) c_int {
var funcs = [_]c.luaL_Reg{
.{ .name = "deflate", .func = utilDeflate },
.{ .name = "inflate", .func = utilInflate },
.{ .name = null, .func = null },
};
c.lua_createtable(l, 0, funcs.len - 1);
c.luaL_setfuncs(l, &funcs, 0);
return 1;
}
fn utilDeflate(l: L) callconv(.C) c_int {
var temp = lua.getTempAlloc(l);
defer temp.reset(65536) catch {};
var uncompressed: []const u8 = undefined;
uncompressed.ptr = c.luaL_checklstring(l, 1, &uncompressed.len);
var num_params = c.lua_gettop(l);
if (num_params > 3) {
_ = c.luaL_error(l, "Expected 1 to 3 parameters (data, level, encode_length)");
unreachable;
}
var level: i8 = 8;
if (num_params >= 2) {
level = @intCast(i8, c.luaL_checkinteger(l, 2));
}
var encode_length = false;
if (c.lua_gettop(l) >= 3) {
if (!c.lua_isboolean(l, 3)) {
_ = c.luaL_error(l, "Expected third parameter to be a boolean (encode_length)");
unreachable;
}
encode_length = c.lua_toboolean(l, 3) != 0;
}
var compressed = zlib.deflate(temp, uncompressed, encode_length, level) catch |err| {
var error_name: [:0]const u8 = undefined;
switch (err) {
error.OutOfMemory => error_name = "Out of memory",
error.InvalidLevel => error_name = "Invalid compression level",
error.Unexpected => error_name = "Unexpected zlib error",
}
_ = c.luaL_error(l, error_name.ptr);
unreachable;
};
_ = c.lua_pushlstring(l, compressed.ptr, compressed.len);
return 1;
}
fn utilInflate(l: L) callconv(.C) c_int {
var temp = lua.getTempAlloc(l);
defer temp.reset(65536) catch {};
var compressed: []const u8 = undefined;
compressed.ptr = c.luaL_checklstring(l, 1, &compressed.len);
var uncompressed_length: usize = undefined;
if (c.lua_gettop(l) > 1) {
uncompressed_length = @intCast(usize, c.luaL_checkinteger(l, 2));
} else {
uncompressed_length = zlib.getUncompressedLength(compressed);
compressed = zlib.stripUncompressedLength(compressed);
}
var uncompressed = zlib.inflate(temp, compressed, uncompressed_length) catch |err| {
var error_name: [:0]const u8 = undefined;
switch (err) {
error.OutOfMemory => error_name = "Out of memory",
error.DataCorrupted => error_name = "Data corrupted or not deflated",
error.Unexpected => error_name = "Unexpected zlib error",
}
_ = c.luaL_error(l, error_name.ptr);
unreachable;
};
_ = c.lua_pushlstring(l, uncompressed.ptr, uncompressed.len);
return 1;
} | limp/lua-util.zig |
const c = @cImport({
@cInclude("SDL.h");
});
const assert = @import("std").debug.assert;
pub fn main() !void {
if (c.SDL_Init(c.SDL_INIT_VIDEO) != 0) {
c.SDL_Log("Unable to initialize SDL: %s", c.SDL_GetError());
return error.SDLInitializationFailed;
}
defer c.SDL_Quit();
const screen = c.SDL_CreateWindow("My Game Window", c.SDL_WINDOWPOS_UNDEFINED, c.SDL_WINDOWPOS_UNDEFINED, 300, 73, c.SDL_WINDOW_OPENGL) orelse
{
c.SDL_Log("Unable to create window: %s", c.SDL_GetError());
return error.SDLInitializationFailed;
};
defer c.SDL_DestroyWindow(screen);
const renderer = c.SDL_CreateRenderer(screen, -1, 0) orelse {
c.SDL_Log("Unable to create renderer: %s", c.SDL_GetError());
return error.SDLInitializationFailed;
};
defer c.SDL_DestroyRenderer(renderer);
const zig_bmp = @embedFile("zig.bmp");
const rw = c.SDL_RWFromConstMem(
@ptrCast(*const c_void, &zig_bmp[0]),
@intCast(c_int, zig_bmp.len),
);
if (rw == 0) {
c.SDL_Log("Unable to get RWFromConstMem: %s", c.SDL_GetError());
return error.SDLInitializationFailed;
}
defer assert(c.SDL_RWclose(rw) == 0);
const zig_surface = c.SDL_LoadBMP_RW(rw, 0);
if (zig_surface == 0) {
c.SDL_Log("Unable to load bmp: %s", c.SDL_GetError());
return error.SDLInitializationFailed;
}
defer c.SDL_FreeSurface(zig_surface);
const zig_texture = c.SDL_CreateTextureFromSurface(renderer, zig_surface) orelse {
c.SDL_Log("Unable to create texture from surface: %s", c.SDL_GetError());
return error.SDLInitializationFailed;
};
defer c.SDL_DestroyTexture(zig_texture);
var quit = false;
while (!quit) {
var event: c.SDL_Event = undefined;
while (c.SDL_PollEvent(&event) != 0) {
switch (event.@"type") {
c.SDL_QUIT => {
quit = true;
},
else => {},
}
}
_ = c.SDL_RenderClear(renderer);
_ = c.SDL_RenderCopy(renderer, zig_texture, 0, 0);
c.SDL_RenderPresent(renderer);
c.SDL_Delay(17);
}
} | example/main.zig |
// Minimum number of stack bytes
const STACK_SIZE = 1024;
/// Executes the equivilent of the PAUSE instruction for
/// x86_64 CPUs. This provides a hint to the processor
/// that the code sequence is a spin-wait loop.
pub fn cpu_relax() void {
asm volatile ("rep; nop");
}
/// Implements the `out` instruction for an x86 processor.
/// `type` must be one of `u8`, `u16`, `u32`, `port` is the
/// port number and `value` will be sent to that port.
pub inline fn out(comptime T: type, port: u16, value: T) void {
switch (T) {
u8 => return outb(port, value),
u16 => return outw(port, value),
u32 => return outl(port, value),
else => @compileError("Only u8, u16 or u32 are allowed for port I/O!"),
}
}
/// Implements the `in` instruction for an x86 processor.
/// `type` must be one of `u8`, `u16`, `u32`, `port` is the
/// port number and the value received from that port will be returned.
pub inline fn in(comptime T: type, port: u16) T {
switch (T) {
u8 => return inb(port),
u16 => return inw(port),
u32 => return inl(port),
else => @compileError("Only u8, u16 or u32 are allowed for port I/O!"),
}
}
pub inline fn outb(port: u16, data: u8) void {
asm volatile ("outb %[data],%[port]"
:
: [port] "{dx}" (port),
[data] "{al}" (data)
);
}
pub inline fn inb(port: u16) u8 {
return asm volatile ("inb %[port],%[result]"
: [result] "={al}" (-> u8)
: [port] "{dx}" (port)
);
}
pub inline fn outw(port: u16, data: u16) void {
asm volatile ("outw %[data],%[port]"
:
: [port] "{dx}" (port),
[data] "{ax}" (data)
);
}
pub inline fn inw(port: u16) void {
return asm volatile ("inw %[port],%[result]"
: [result] "={ax}" (-> u16)
: [port] "{dx}" (port)
);
}
pub inline fn outl(port: u16, data: u32) void {
asm volatile ("outl %[data],%[port]"
:
: [port] "{dx}" (port),
[data] "{eax}" (data)
);
}
pub inline fn inl(port: u16) u16 {
return asm volatile ("inl %[port],%[result]"
: [result] "={eax}" (-> u32)
: [data] "{dx}" (data)
);
}
pub inline fn ioDelay() void {
const delayPort = 0x80;
asm volatile ("outb %%al,%0"
:
: [delayPort] "dN" (delayPort)
);
}
pub inline fn memcmp_fs(s1: ?*const c_void, s2: c_uint, len: usize) bool {
return asm volatile ("fs; repe; cmpsb"
: [diff] "=@cc" (-> bool),
[s1] "+D" (s1),
[s2] "+S" (s2),
[len] "+c" (len)
);
}
pub inline fn memcmp_gs(s1: ?*const c_void, s2: c_uint, len: usize) bool {
return asm volatile ("gs; repe; cmpsb"
: [diff] "=@cc" (-> bool),
[s1] "+D" (s1),
[s2] "+S" (s2),
[len] "+c" (len)
);
} | src/kernel/arch/x86/boot/io.zig |
const std = @import("std");
const ArrayList = std.ArrayList;
const json = std.json;
pub const ImplementationClientCapabilities = struct {
textDocument: ?TextDocument,
pub const TextDocument = struct {
implementation: ?Implementation,
pub const Implementation = struct {
dynamicRegistration: ?bool,
linkSupport: ?bool,
};
};
};
pub const ImplementationServerCapabilities = struct {
implementationProvider: ?bool,
};
pub const TypeDefinitionClientCapabilities = struct {
textDocument: ?TextDocument,
pub const TextDocument = struct {
typeDefinition: ?TypeDefinition,
pub const TypeDefinition = struct {
dynamicRegistration: ?bool,
linkSupport: ?bool,
};
};
};
pub const TypeDefinitionServerCapabilities = struct {
typeDefinitionProvider: ?bool,
};
pub const WorkspaceFoldersInitializeParams = struct {
workspaceFolders: ArrayList(WorkspaceFolder),
};
pub const WorkspaceFoldersClientCapabilities = struct {
workspace: ?Workspace,
pub const Workspace = struct {
workspaceFolders: ?bool,
};
};
pub const WorkspaceFoldersServerCapabilities = struct {
workspace: ?Workspace,
pub const Workspace = struct {
workspaceFolders: ?WorkspaceFolders,
pub const WorkspaceFolders = struct {
supported: ?bool,
changeNotifications: ?[]const u8,
};
};
};
pub const WorkspaceFolder = struct {
uRI: []const u8,
name: []const u8,
};
/// /**
/// * The parameters of a `workspace/didChangeWorkspaceFolders` notification.
/// */
pub const DidChangeWorkspaceFoldersParams = struct {
event: WorkspaceFoldersChangeEvent,
};
/// /**
/// * The workspace folder change event.
/// */
pub const WorkspaceFoldersChangeEvent = struct {
added: ArrayList(WorkspaceFolder),
removed: ArrayList(WorkspaceFolder),
};
pub const ConfigurationClientCapabilities = struct {
workspace: ?Workspace,
pub const Workspace = struct {
configuration: ?bool,
};
};
pub const ConfigurationItem = struct {
scopeUri: ?[]const u8,
section: ?[]const u8,
};
/// /**
/// * The parameters of a configuration request.
/// */
pub const ConfigurationParams = struct {
items: ArrayList(ConfigurationItem),
};
pub const ColorClientCapabilities = struct {
textDocument: ?TextDocument,
pub const TextDocument = struct {
colorProvider: ?ColorProvider,
pub const ColorProvider = struct {
dynamicRegistration: ?bool,
};
};
};
pub const ColorProviderOptions = struct {};
pub const ColorServerCapabilities = struct {
colorProvider: ?bool,
};
/// /**
/// * Parameters for a [DocumentColorRequest](#DocumentColorRequest).
/// */
pub const DocumentColorParams = struct {
textDocument: TextDocumentIdentifier,
};
/// /**
/// * Parameters for a [ColorPresentationRequest](#ColorPresentationRequest).
/// */
pub const ColorPresentationParams = struct {
textDocument: TextDocumentIdentifier,
color: Color,
range: Range,
};
pub const FoldingRangeClientCapabilities = struct {
textDocument: ?TextDocument,
pub const TextDocument = struct {
foldingRange: ?FoldingRange,
pub const FoldingRange = struct {
dynamicRegistration: ?bool,
rangeLimit: ?f64,
lineFoldingOnly: ?bool,
};
};
};
pub const FoldingRangeProviderOptions = struct {};
pub const FoldingRangeServerCapabilities = struct {
foldingRangeProvider: ?bool,
};
/// /**
/// * Represents a folding range.
/// */
pub const FoldingRange = struct {
startLine: f64,
startCharacter: ?f64,
endLine: f64,
endCharacter: ?f64,
kind: ?[]const u8,
};
/// /**
/// * Parameters for a [FoldingRangeRequest](#FoldingRangeRequest).
/// */
pub const FoldingRangeParams = struct {
textDocument: TextDocumentIdentifier,
};
pub const DeclarationClientCapabilities = struct {
textDocument: ?TextDocument,
pub const TextDocument = struct {
declaration: ?Declaration,
pub const Declaration = struct {
dynamicRegistration: ?bool,
linkSupport: ?bool,
};
};
};
pub const DeclarationServerCapabilities = struct {
declarationProvider: ?bool,
};
/// /**
/// * General parameters to to register for an notification or to register a provider.
/// */
pub const Registration = struct {
iD: []const u8,
method: []const u8,
registerOptions: ?json.Value,
};
pub const RegistrationParams = struct {
registrations: ArrayList(Registration),
};
/// /**
/// * General parameters to unregister a request or notification.
/// */
pub const Unregistration = struct {
iD: []const u8,
method: []const u8,
};
pub const UnregistrationParams = struct {
unregisterations: ArrayList(Unregistration),
};
/// /**
/// * A parameter literal used in requests to pass a text document and a position inside that
/// * document.
/// */
pub const TextDocumentPositionParams = struct {
textDocument: TextDocumentIdentifier,
position: Position,
};
/// /**
/// * Workspace specific client capabilities.
/// */
pub const WorkspaceClientCapabilities = struct {
applyEdit: ?bool,
workspaceEdit: ?WorkspaceEdit,
didChangeConfiguration: ?DidChangeConfiguration,
didChangeWatchedFiles: ?DidChangeWatchedFiles,
symbol: ?Symbol,
executeCommand: ?ExecuteCommand,
pub const WorkspaceEdit = struct {
documentChanges: ?bool,
resourceOperations: ?ArrayList(ResourceOperationKind),
failureHandling: ?FailureHandlingKind,
};
pub const DidChangeConfiguration = struct {
dynamicRegistration: ?bool,
};
pub const DidChangeWatchedFiles = struct {
dynamicRegistration: ?bool,
};
pub const Symbol = struct {
dynamicRegistration: ?bool,
symbolKind: ?SymbolKind,
pub const SymbolKind = struct {
valueSet: ?ArrayList(SymbolKind),
};
};
pub const ExecuteCommand = struct {
dynamicRegistration: ?bool,
};
};
/// /**
/// * Text document specific client capabilities.
/// */
pub const TextDocumentClientCapabilities = struct {
synchronization: ?Synchronization,
completion: ?Completion,
hover: ?Hover,
signatureHelp: ?SignatureHelp,
references: ?References,
documentHighlight: ?DocumentHighlight,
documentSymbol: ?DocumentSymbol,
formatting: ?Formatting,
rangeFormatting: ?RangeFormatting,
onTypeFormatting: ?OnTypeFormatting,
definition: ?Definition,
codeAction: ?CodeAction,
codeLens: ?CodeLens,
documentLink: ?DocumentLink,
rename: ?Rename,
publishDiagnostics: ?PublishDiagnostics,
pub const Synchronization = struct {
dynamicRegistration: ?bool,
willSave: ?bool,
willSaveWaitUntil: ?bool,
didSave: ?bool,
};
pub const Completion = struct {
dynamicRegistration: ?bool,
completionItem: ?CompletionItem,
completionItemKind: ?CompletionItemKind,
contextSupport: ?bool,
pub const CompletionItem = struct {
snippetSupport: ?bool,
commitCharactersSupport: ?bool,
documentationFormat: ?ArrayList(MarkupKind),
deprecatedSupport: ?bool,
preselectSupport: ?bool,
};
pub const CompletionItemKind = struct {
valueSet: ?ArrayList(CompletionItemKind),
};
};
pub const Hover = struct {
dynamicRegistration: ?bool,
contentFormat: ?ArrayList(MarkupKind),
};
pub const SignatureHelp = struct {
dynamicRegistration: ?bool,
signatureInformation: ?SignatureInformation,
pub const SignatureInformation = struct {
documentationFormat: ?ArrayList(MarkupKind),
parameterInformation: ?ParameterInformation,
pub const ParameterInformation = struct {
labelOffsetSupport: ?bool,
};
};
};
pub const References = struct {
dynamicRegistration: ?bool,
};
pub const DocumentHighlight = struct {
dynamicRegistration: ?bool,
};
pub const DocumentSymbol = struct {
dynamicRegistration: ?bool,
symbolKind: ?SymbolKind,
hierarchicalDocumentSymbolSupport: ?bool,
pub const SymbolKind = struct {
valueSet: ?ArrayList(SymbolKind),
};
};
pub const Formatting = struct {
dynamicRegistration: ?bool,
};
pub const RangeFormatting = struct {
dynamicRegistration: ?bool,
};
pub const OnTypeFormatting = struct {
dynamicRegistration: ?bool,
};
pub const Definition = struct {
dynamicRegistration: ?bool,
linkSupport: ?bool,
};
pub const CodeAction = struct {
dynamicRegistration: ?bool,
codeActionLiteralSupport: ?CodeActionLiteralSupport,
pub const CodeActionLiteralSupport = struct {
codeActionKind: CodeActionKind,
pub const CodeActionKind = struct {
valueSet: ArrayList(CodeActionKind),
};
};
};
pub const CodeLens = struct {
dynamicRegistration: ?bool,
};
pub const DocumentLink = struct {
dynamicRegistration: ?bool,
};
pub const Rename = struct {
dynamicRegistration: ?bool,
prepareSupport: ?bool,
};
pub const PublishDiagnostics = struct {
relatedInformation: ?bool,
tagSupport: ?bool,
};
};
/// /**
/// * Window specific client capabilities.
/// */
pub const WindowClientCapabilities = struct {
progress: ?bool,
};
/// /**
/// * Defines the capabilities provided by the client.
/// */
pub const InnerClientCapabilities = struct {
workspace: ?WorkspaceClientCapabilities,
textDocument: ?TextDocumentClientCapabilities,
window: ?WindowClientCapabilities,
experimental: ?json.Value,
};
pub const ClientCapabilities = struct {
workspace: ?WorkspaceClientCapabilities,
textDocument: ?TextDocumentClientCapabilities,
window: ?WindowClientCapabilities,
experimental: ?json.Value,
textDocument: ?TextDocument,
textDocument: ?TextDocument,
workspace: ?Workspace,
workspace: ?Workspace,
textDocument: ?TextDocument,
textDocument: ?TextDocument,
textDocument: ?TextDocument,
pub const TextDocument = struct {
implementation: ?Implementation,
pub const Implementation = struct {
dynamicRegistration: ?bool,
linkSupport: ?bool,
};
};
pub const TextDocument = struct {
typeDefinition: ?TypeDefinition,
pub const TypeDefinition = struct {
dynamicRegistration: ?bool,
linkSupport: ?bool,
};
};
pub const Workspace = struct {
workspaceFolders: ?bool,
};
pub const Workspace = struct {
configuration: ?bool,
};
pub const TextDocument = struct {
colorProvider: ?ColorProvider,
pub const ColorProvider = struct {
dynamicRegistration: ?bool,
};
};
pub const TextDocument = struct {
foldingRange: ?FoldingRange,
pub const FoldingRange = struct {
dynamicRegistration: ?bool,
rangeLimit: ?f64,
lineFoldingOnly: ?bool,
};
};
pub const TextDocument = struct {
declaration: ?Declaration,
pub const Declaration = struct {
dynamicRegistration: ?bool,
linkSupport: ?bool,
};
};
};
/// /**
/// * Static registration options to be returned in the initialize
/// * request.
/// */
pub const StaticRegistrationOptions = struct {
iD: ?[]const u8,
};
/// /**
/// * General text document registration options.
/// */
pub const TextDocumentRegistrationOptions = struct {
documentSelector: DocumentSelector,
};
/// /**
/// * Completion options.
/// */
pub const CompletionOptions = struct {
triggerCharacters: ?ArrayList([]const u8),
allCommitCharacters: ?ArrayList([]const u8),
resolveProvider: ?bool,
};
/// /**
/// * Signature help options.
/// */
pub const SignatureHelpOptions = struct {
triggerCharacters: ?ArrayList([]const u8),
};
/// /**
/// * Code Action options.
/// */
pub const CodeActionOptions = struct {
codeActionKinds: ?ArrayList(CodeActionKind),
};
/// /**
/// * Code Lens options.
/// */
pub const CodeLensOptions = struct {
resolveProvider: ?bool,
};
/// /**
/// * Format document on type options
/// */
pub const DocumentOnTypeFormattingOptions = struct {
firstTriggerCharacter: []const u8,
moreTriggerCharacter: ?ArrayList([]const u8),
};
/// /**
/// * Rename options
/// */
pub const RenameOptions = struct {
prepareProvider: ?bool,
};
/// /**
/// * Document link options
/// */
pub const DocumentLinkOptions = struct {
resolveProvider: ?bool,
};
/// /**
/// * Execute command options.
/// */
pub const ExecuteCommandOptions = struct {
commands: ArrayList([]const u8),
};
/// /**
/// * Save options.
/// */
pub const SaveOptions = struct {
includeText: ?bool,
};
pub const TextDocumentSyncOptions = struct {
openClose: ?bool,
change: TextDocumentSyncKind,
willSave: ?bool,
willSaveWaitUntil: ?bool,
save: ?SaveOptions,
};
/// /**
/// * Defines the capabilities provided by a language
/// * server.
/// */
pub const InnerServerCapabilities = struct {
textDocumentSync: ?json.Value,
hoverProvider: ?bool,
completionProvider: ?CompletionOptions,
signatureHelpProvider: ?SignatureHelpOptions,
definitionProvider: ?bool,
referencesProvider: ?bool,
documentHighlightProvider: ?bool,
documentSymbolProvider: ?bool,
workspaceSymbolProvider: ?bool,
codeActionProvider: ?bool,
codeLensProvider: ?CodeLensOptions,
documentFormattingProvider: ?bool,
documentRangeFormattingProvider: ?bool,
documentOnTypeFormattingProvider: ?DocumentOnTypeFormattingProvider,
renameProvider: ?bool,
documentLinkProvider: ?DocumentLinkOptions,
executeCommandProvider: ?ExecuteCommandOptions,
experimental: ?json.Value,
pub const DocumentOnTypeFormattingProvider = struct {
firstTriggerCharacter: []const u8,
moreTriggerCharacter: ?ArrayList([]const u8),
};
};
pub const ServerCapabilities = struct {
textDocumentSync: ?json.Value,
hoverProvider: ?bool,
completionProvider: ?CompletionOptions,
signatureHelpProvider: ?SignatureHelpOptions,
definitionProvider: ?bool,
referencesProvider: ?bool,
documentHighlightProvider: ?bool,
documentSymbolProvider: ?bool,
workspaceSymbolProvider: ?bool,
codeActionProvider: ?bool,
codeLensProvider: ?CodeLensOptions,
documentFormattingProvider: ?bool,
documentRangeFormattingProvider: ?bool,
documentOnTypeFormattingProvider: ?DocumentOnTypeFormattingProvider,
renameProvider: ?bool,
documentLinkProvider: ?DocumentLinkOptions,
executeCommandProvider: ?ExecuteCommandOptions,
experimental: ?json.Value,
implementationProvider: ?bool,
typeDefinitionProvider: ?bool,
workspace: ?Workspace,
colorProvider: ?bool,
foldingRangeProvider: ?bool,
declarationProvider: ?bool,
pub const DocumentOnTypeFormattingProvider = struct {
firstTriggerCharacter: []const u8,
moreTriggerCharacter: ?ArrayList([]const u8),
};
pub const Workspace = struct {
workspaceFolders: ?WorkspaceFolders,
pub const WorkspaceFolders = struct {
supported: ?bool,
changeNotifications: ?[]const u8,
};
};
};
/// /**
/// * The initialize parameters
/// */
pub const InnerInitializeParams = struct {
processId: f64,
rootPath: ?[]const u8,
rootUri: []const u8,
capabilities: ClientCapabilities,
initializationOptions: ?json.Value,
trace: ?[]const u8,
};
pub const InitializeParams = struct {
processId: f64,
rootPath: ?[]const u8,
rootUri: []const u8,
capabilities: ClientCapabilities,
initializationOptions: ?json.Value,
trace: ?[]const u8,
workspaceFolders: ArrayList(WorkspaceFolder),
};
/// /**
/// * The result returned from an initialize request.
/// */
pub const InitializeResult = struct {
capabilities: ServerCapabilities,
custom: json.ObjectMap,
};
pub const InitializedParams = struct {};
pub const DidChangeConfigurationRegistrationOptions = struct {
section: ?[]const u8,
};
/// /**
/// * The parameters of a change configuration notification.
/// */
pub const DidChangeConfigurationParams = struct {
settings: json.Value,
};
/// /**
/// * The parameters of a notification message.
/// */
pub const ShowMessageParams = struct {
type: MessageType,
message: []const u8,
};
pub const MessageActionItem = struct {
title: []const u8,
};
pub const ShowMessageRequestParams = struct {
type: MessageType,
message: []const u8,
actions: ?ArrayList(MessageActionItem),
};
/// /**
/// * The log message parameters.
/// */
pub const LogMessageParams = struct {
type: MessageType,
message: []const u8,
};
/// /**
/// * The parameters send in a open text document notification
/// */
pub const DidOpenTextDocumentParams = struct {
textDocument: TextDocumentItem,
};
/// /**
/// * The change text document notification's parameters.
/// */
pub const DidChangeTextDocumentParams = struct {
textDocument: VersionedTextDocumentIdentifier,
contentChanges: ArrayList(TextDocumentContentChangeEvent),
};
/// /**
/// * Describe options to be used when registered for text document change events.
/// */
pub const TextDocumentChangeRegistrationOptions = struct {
documentSelector: DocumentSelector,
syncKind: TextDocumentSyncKind,
};
/// /**
/// * The parameters send in a close text document notification
/// */
pub const DidCloseTextDocumentParams = struct {
textDocument: TextDocumentIdentifier,
};
/// /**
/// * The parameters send in a save text document notification
/// */
pub const DidSaveTextDocumentParams = struct {
textDocument: VersionedTextDocumentIdentifier,
text: ?[]const u8,
};
/// /**
/// * Save registration options.
/// */
pub const TextDocumentSaveRegistrationOptions = struct {
documentSelector: DocumentSelector,
includeText: ?bool,
};
/// /**
/// * The parameters send in a will save text document notification.
/// */
pub const WillSaveTextDocumentParams = struct {
textDocument: TextDocumentIdentifier,
reason: TextDocumentSaveReason,
};
/// /**
/// * The watched files change notification's parameters.
/// */
pub const DidChangeWatchedFilesParams = struct {
changes: ArrayList(FileEvent),
};
/// /**
/// * An event describing a file change.
/// */
pub const FileEvent = struct {
uRI: []const u8,
type: FileChangeType,
};
/// /**
/// * Describe options to be used when registered for text document change events.
/// */
pub const DidChangeWatchedFilesRegistrationOptions = struct {
watchers: ArrayList(FileSystemWatcher),
};
pub const FileSystemWatcher = struct {
globPattern: []const u8,
kind: ?f64,
};
/// /**
/// * The publish diagnostic notification's parameters.
/// */
pub const PublishDiagnosticsParams = struct {
uRI: []const u8,
version: ?f64,
diagnostics: ArrayList(Diagnostic),
};
/// /**
/// * Completion registration options.
/// */
pub const CompletionRegistrationOptions = struct {
documentSelector: DocumentSelector,
triggerCharacters: ?ArrayList([]const u8),
allCommitCharacters: ?ArrayList([]const u8),
resolveProvider: ?bool,
};
/// /**
/// * Contains additional information about the context in which a completion request is triggered.
/// */
pub const CompletionContext = struct {
triggerKind: CompletionTriggerKind,
triggerCharacter: ?[]const u8,
};
/// /**
/// * Completion parameters
/// */
pub const CompletionParams = struct {
textDocument: TextDocumentIdentifier,
position: Position,
context: ?CompletionContext,
};
/// /**
/// * Signature help registration options.
/// */
pub const SignatureHelpRegistrationOptions = struct {
documentSelector: DocumentSelector,
triggerCharacters: ?ArrayList([]const u8),
};
/// /**
/// * Parameters for a [ReferencesRequest](#ReferencesRequest).
/// */
pub const ReferenceParams = struct {
textDocument: TextDocumentIdentifier,
position: Position,
context: ReferenceContext,
};
/// /**
/// * Params for the CodeActionRequest
/// */
pub const CodeActionParams = struct {
textDocument: TextDocumentIdentifier,
range: Range,
context: CodeActionContext,
};
pub const CodeActionRegistrationOptions = struct {
documentSelector: DocumentSelector,
codeActionKinds: ?ArrayList(CodeActionKind),
};
/// /**
/// * Params for the Code Lens request.
/// */
pub const CodeLensParams = struct {
textDocument: TextDocumentIdentifier,
};
/// /**
/// * Code Lens registration options.
/// */
pub const CodeLensRegistrationOptions = struct {
documentSelector: DocumentSelector,
resolveProvider: ?bool,
};
pub const DocumentFormattingParams = struct {
textDocument: TextDocumentIdentifier,
options: FormattingOptions,
};
pub const DocumentRangeFormattingParams = struct {
textDocument: TextDocumentIdentifier,
range: Range,
options: FormattingOptions,
};
pub const DocumentOnTypeFormattingParams = struct {
textDocument: TextDocumentIdentifier,
position: Position,
ch: []const u8,
options: FormattingOptions,
};
/// /**
/// * Format document on type options
/// */
pub const DocumentOnTypeFormattingRegistrationOptions = struct {
documentSelector: DocumentSelector,
firstTriggerCharacter: []const u8,
moreTriggerCharacter: ?ArrayList([]const u8),
};
pub const RenameParams = struct {
textDocument: TextDocumentIdentifier,
position: Position,
newName: []const u8,
};
/// /**
/// * Rename registration options.
/// */
pub const RenameRegistrationOptions = struct {
documentSelector: DocumentSelector,
prepareProvider: ?bool,
};
pub const DocumentLinkParams = struct {
textDocument: TextDocumentIdentifier,
};
/// /**
/// * Document link registration options
/// */
pub const DocumentLinkRegistrationOptions = struct {
documentSelector: DocumentSelector,
resolveProvider: ?bool,
};
pub const ExecuteCommandParams = struct {
command: []const u8,
arguments: ?ArrayList(interface{}),
};
/// /**
/// * Execute command registration options.
/// */
pub const ExecuteCommandRegistrationOptions = struct {
commands: ArrayList([]const u8),
};
/// /**
/// * The parameters passed via a apply workspace edit request.
/// */
pub const ApplyWorkspaceEditParams = struct {
label: ?[]const u8,
edit: WorkspaceEdit,
};
/// /**
/// * A response returned from the apply workspace edit request.
/// */
pub const ApplyWorkspaceEditResponse = struct {
applied: bool,
failureReason: ?[]const u8,
failedChange: ?f64,
};
/// /**
/// * Position in a text document expressed as zero-based line and character offset.
/// * The offsets are based on a UTF-16 string representation. So a string of the form
/// * `a𐐀b` the character offset of the character `a` is 0, the character offset of `𐐀`
/// * is 1 and the character offset of b is 3 since `𐐀` is represented using two code
/// * units in UTF-16.
/// *
/// * Positions are line end character agnostic. So you can not specify a position that
/// * denotes `\r|\n` or `\n|` where `|` represents the character offset.
/// */
pub const Position = struct {
line: f64,
character: f64,
};
/// /**
/// * A range in a text document expressed as (zero-based) start and end positions.
/// *
/// * If you want to specify a range that contains a line including the line ending
/// * character(s) then use an end position denoting the start of the next line.
/// * For example:
/// * ```ts
/// * {
/// * start: { line: 5, character: 23 }
/// * end : { line 6, character : 0 }
/// * }
/// * ```
/// */
pub const Range = struct {
start: Position,
end: Position,
};
/// /**
/// * Represents a location inside a resource, such as a line
/// * inside a text file.
/// */
pub const Location = struct {
uRI: []const u8,
range: Range,
};
/// /**
/// * Represents the connection of two locations. Provides additional metadata over normal [locations](#Location),
/// * including an origin range.
/// */
pub const LocationLink = struct {
originSelectionRange: ?Range,
targetUri: []const u8,
targetRange: Range,
targetSelectionRange: Range,
};
/// /**
/// * Represents a color in RGBA space.
/// */
pub const Color = struct {
red: f64,
green: f64,
blue: f64,
alpha: f64,
};
/// /**
/// * Represents a color range from a document.
/// */
pub const ColorInformation = struct {
range: Range,
color: Color,
};
pub const ColorPresentation = struct {
label: []const u8,
textEdit: ?TextEdit,
additionalTextEdits: ?ArrayList(TextEdit),
};
/// /**
/// * Represents a related message and source code location for a diagnostic. This should be
/// * used to point to code locations that cause or related to a diagnostics, e.g when duplicating
/// * a symbol in a scope.
/// */
pub const DiagnosticRelatedInformation = struct {
location: Location,
message: []const u8,
};
/// /**
/// * Represents a diagnostic, such as a compiler error or warning. Diagnostic objects
/// * are only valid in the scope of a resource.
/// */
pub const Diagnostic = struct {
range: Range,
severity: DiagnosticSeverity,
code: ?json.Value,
source: ?[]const u8,
message: []const u8,
tags: ?ArrayList(DiagnosticTag),
relatedInformation: ?ArrayList(DiagnosticRelatedInformation),
};
/// /**
/// * Represents a reference to a command. Provides a title which
/// * will be used to represent a command in the UI and, optionally,
/// * an array of arguments which will be passed to the command handler
/// * function when invoked.
/// */
pub const Command = struct {
title: []const u8,
command: []const u8,
arguments: ?ArrayList(interface{}),
};
/// /**
/// * A text edit applicable to a text document.
/// */
pub const TextEdit = struct {
range: Range,
newText: []const u8,
};
/// /**
/// * Describes textual changes on a text document.
/// */
pub const TextDocumentEdit = struct {
textDocument: VersionedTextDocumentIdentifier,
edits: ArrayList(TextEdit),
};
pub const ResourceOperation = struct {
kind: []const u8,
};
/// /**
/// * Options to create a file.
/// */
pub const CreateFileOptions = struct {
overwrite: ?bool,
ignoreIfExists: ?bool,
};
/// /**
/// * Create file operation.
/// */
pub const CreateFile = struct {
kind: []const u8,
kind: []const u8,
uRI: []const u8,
options: ?CreateFileOptions,
};
/// /**
/// * Rename file options
/// */
pub const RenameFileOptions = struct {
overwrite: ?bool,
ignoreIfExists: ?bool,
};
/// /**
/// * Rename file operation
/// */
pub const RenameFile = struct {
kind: []const u8,
kind: []const u8,
oldUri: []const u8,
newUri: []const u8,
options: ?RenameFileOptions,
};
/// /**
/// * Delete file options
/// */
pub const DeleteFileOptions = struct {
recursive: ?bool,
ignoreIfNotExists: ?bool,
};
/// /**
/// * Delete file operation
/// */
pub const DeleteFile = struct {
kind: []const u8,
kind: []const u8,
uRI: []const u8,
options: ?DeleteFileOptions,
};
/// /**
/// * A workspace edit represents changes to many resources managed in the workspace. The edit
/// * should either provide `changes` or `documentChanges`. If documentChanges are present
/// * they are preferred over `changes` if the client can handle versioned document edits.
/// */
pub const WorkspaceEdit = struct {
changes: ?json.ObjectMap,
documentChanges: ?ArrayList(TextDocumentEdit),
};
/// /**
/// * A change to capture text edits for existing resources.
/// */
pub const TextEditChange = struct {};
/// /**
/// * A literal to identify a text document in the client.
/// */
pub const TextDocumentIdentifier = struct {
uRI: []const u8,
};
/// /**
/// * An identifier to denote a specific version of a text document.
/// */
pub const VersionedTextDocumentIdentifier = struct {
uRI: []const u8,
version: f64,
};
/// /**
/// * An item to transfer a text document from the client to the
/// * server.
/// */
pub const TextDocumentItem = struct {
uRI: []const u8,
languageId: []const u8,
version: f64,
text: []const u8,
};
/// /**
/// * A `MarkupContent` literal represents a string value which content is interpreted base on its
/// * kind flag. Currently the protocol supports `plaintext` and `markdown` as markup kinds.
/// *
/// * If the kind is `markdown` then the value can contain fenced code blocks like in GitHub issues.
/// * See https://help.github.com/articles/creating-and-highlighting-code-blocks/#syntax-highlighting
/// *
/// * Here is an example how such a string can be constructed using JavaScript / TypeScript:
/// * ```ts
/// * let markdown: MarkdownContent = {
/// * kind: MarkupKind.Markdown,
/// * value: [
/// * '# Header',
/// * 'Some text',
/// * '```typescript',
/// * 'someCode();',
/// * '```'
/// * ].join('\n')
/// * };
/// * ```
/// *
/// * *Please Note* that clients might sanitize the return markdown. A client could decide to
/// * remove HTML from the markdown to avoid script execution.
/// */
pub const MarkupContent = struct {
kind: MarkupKind,
value: []const u8,
};
/// /**
/// * A completion item represents a text snippet that is
/// * proposed to complete text that is being typed.
/// */
pub const CompletionItem = struct {
label: []const u8,
kind: CompletionItemKind,
detail: ?[]const u8,
documentation: ?[]const u8,
deprecated: ?bool,
preselect: ?bool,
sortText: ?[]const u8,
filterText: ?[]const u8,
insertText: ?[]const u8,
insertTextFormat: InsertTextFormat,
textEdit: ?TextEdit,
additionalTextEdits: ?ArrayList(TextEdit),
commitCharacters: ?ArrayList([]const u8),
command: ?Command,
data: ?json.Value,
};
/// /**
/// * Represents a collection of [completion items](#CompletionItem) to be presented
/// * in the editor.
/// */
pub const CompletionList = struct {
isIncomplete: bool,
items: ArrayList(CompletionItem),
};
/// /**
/// * The result of a hover request.
/// */
pub const Hover = struct {
contents: MarkupContent,
range: ?Range,
};
/// /**
/// * Represents a parameter of a callable-signature. A parameter can
/// * have a label and a doc-comment.
/// */
pub const ParameterInformation = struct {
label: []const u8,
documentation: ?[]const u8,
};
/// /**
/// * Represents the signature of something callable. A signature
/// * can have a label, like a function-name, a doc-comment, and
/// * a set of parameters.
/// */
pub const SignatureInformation = struct {
label: []const u8,
documentation: ?[]const u8,
parameters: ?ArrayList(ParameterInformation),
};
/// /**
/// * Signature help represents the signature of something
/// * callable. There can be multiple signature but only one
/// * active and only one active parameter.
/// */
pub const SignatureHelp = struct {
signatures: ArrayList(SignatureInformation),
activeSignature: f64,
activeParameter: f64,
};
/// /**
/// * Value-object that contains additional information when
/// * requesting references.
/// */
pub const ReferenceContext = struct {
includeDeclaration: bool,
};
/// /**
/// * A document highlight is a range inside a text document which deserves
/// * special attention. Usually a document highlight is visualized by changing
/// * the background color of its range.
/// */
pub const DocumentHighlight = struct {
range: Range,
kind: ?DocumentHighlightKind,
};
/// /**
/// * Represents information about programming constructs like variables, classes,
/// * interfaces etc.
/// */
pub const SymbolInformation = struct {
name: []const u8,
kind: SymbolKind,
deprecated: ?bool,
location: Location,
containerName: ?[]const u8,
};
/// /**
/// * Represents programming constructs like variables, classes, interfaces etc.
/// * that appear in a document. Document symbols can be hierarchical and they
/// * have two ranges: one that encloses its definition and one that points to
/// * its most interesting range, e.g. the range of an identifier.
/// */
pub const DocumentSymbol = struct {
name: []const u8,
detail: ?[]const u8,
kind: SymbolKind,
deprecated: ?bool,
range: Range,
selectionRange: Range,
children: ?ArrayList(DocumentSymbol),
};
/// /**
/// * Parameters for a [DocumentSymbolRequest](#DocumentSymbolRequest).
/// */
pub const DocumentSymbolParams = struct {
textDocument: TextDocumentIdentifier,
};
/// /**
/// * The parameters of a [WorkspaceSymbolRequest](#WorkspaceSymbolRequest).
/// */
pub const WorkspaceSymbolParams = struct {
query: []const u8,
};
/// /**
/// * Contains additional diagnostic information about the context in which
/// * a [code action](#CodeActionProvider.provideCodeActions) is run.
/// */
pub const CodeActionContext = struct {
diagnostics: ArrayList(Diagnostic),
only: ?ArrayList(CodeActionKind),
};
/// /**
/// * A code action represents a change that can be performed in code, e.g. to fix a problem or
/// * to refactor code.
/// *
/// * A CodeAction must set either `edit` and/or a `command`. If both are supplied, the `edit` is applied first, then the `command` is executed.
/// */
pub const CodeAction = struct {
title: []const u8,
kind: CodeActionKind,
diagnostics: ?ArrayList(Diagnostic),
edit: ?WorkspaceEdit,
command: ?Command,
};
/// /**
/// * A code lens represents a [command](#Command) that should be shown along with
/// * source text, like the number of references, a way to run tests, etc.
/// *
/// * A code lens is _unresolved_ when no command is associated to it. For performance
/// * reasons the creation of a code lens and resolving should be done to two stages.
/// */
pub const CodeLens = struct {
range: Range,
command: ?Command,
data: ?json.Value,
};
/// /**
/// * Value-object describing what options formatting should use.
/// */
pub const FormattingOptions = struct {
tabSize: f64,
insertSpaces: bool,
trimTrailingWhitespace: ?bool,
insertFinalNewline: ?bool,
trimFinalNewlines: ?bool,
key: json.ObjectMap,
};
/// /**
/// * A document link is a range in a text document that links to an internal or external resource, like another
/// * text document or a web site.
/// */
pub const DocumentLink = struct {
range: Range,
target: ?[]const u8,
data: ?json.Value,
};
/// /**
/// * A simple text document. Not to be implemented.
/// */
pub const TextDocument = struct {
uRI: []const u8,
languageId: []const u8,
version: f64,
lineCount: f64,
};
/// /**
/// * Event to signal changes to a simple text document.
/// */
pub const TextDocumentChangeEvent = struct {
document: TextDocument,
};
pub const TextDocumentWillSaveEvent = struct {
document: TextDocument,
reason: TextDocumentSaveReason,
};
/// /**
/// * An event describing a change to a text document. If range and rangeLength are omitted
/// * the new text is considered to be the full content of the document.
/// */
pub const TextDocumentContentChangeEvent = struct {
range: ?Range,
rangeLength: ?f64,
text: []const u8,
};
const FoldingRangeKind = enum {
Comment,
Imports,
Region,
Comment,
Imports,
Region,
pub fn toString(self: FoldingRangeKind) []const u8 {
return switch (self) {
FoldingRangeKind.Comment => "comment",
FoldingRangeKind.Imports => "imports",
FoldingRangeKind.Region => "region",
FoldingRangeKind.Comment => "comment",
FoldingRangeKind.Imports => "imports",
FoldingRangeKind.Region => "region",
else => "",
};
}
};
const ResourceOperationKind = enum {
Create,
Rename,
Delete,
pub fn toString(self: ResourceOperationKind) []const u8 {
return switch (self) {
ResourceOperationKind.Create => "create",
ResourceOperationKind.Rename => "rename",
ResourceOperationKind.Delete => "delete",
else => "",
};
}
};
const FailureHandlingKind = enum {
Abort,
Transactional,
TextOnlyTransactional,
Undo,
pub fn toString(self: FailureHandlingKind) []const u8 {
return switch (self) {
FailureHandlingKind.Abort => "abort",
FailureHandlingKind.Transactional => "transactional",
FailureHandlingKind.TextOnlyTransactional => "textOnlyTransactional",
FailureHandlingKind.Undo => "undo",
else => "",
};
}
};
const TextDocumentSyncKind = enum(f64) {
None = 0,
Full = 1,
Incremental = 2,
};
const InitializeError = enum(f64) {
UnknownProtocolVersion = 1,
};
const MessageType = enum(f64) {
Error = 1,
Warning = 2,
Info = 3,
Log = 4,
};
const FileChangeType = enum(f64) {
Created = 1,
Changed = 2,
Deleted = 3,
};
const WatchKind = enum(f64) {
Create = 1,
Change = 2,
Delete = 4,
};
const CompletionTriggerKind = enum(f64) {
Invoked = 1,
TriggerCharacter = 2,
TriggerForIncompleteCompletions = 3,
};
const DiagnosticSeverity = enum(f64) {
Error = 1,
Warning = 2,
Information = 3,
Hint = 4,
};
const DiagnosticTag = enum(f64) {
Unnecessary = 1,
};
const MarkupKind = enum {
PlainText,
Markdown,
pub fn toString(self: MarkupKind) []const u8 {
return switch (self) {
MarkupKind.PlainText => "plaintext",
MarkupKind.Markdown => "markdown",
else => "",
};
}
};
const CompletionItemKind = enum(f64) {
Text = 1,
Method = 2,
Function = 3,
Constructor = 4,
Field = 5,
Variable = 6,
Class = 7,
Interface = 8,
Module = 9,
Property = 10,
Unit = 11,
Value = 12,
Enum = 13,
Keyword = 14,
Snippet = 15,
Color = 16,
File = 17,
Reference = 18,
Folder = 19,
EnumMember = 20,
Constant = 21,
Struct = 22,
Event = 23,
Operator = 24,
TypeParameter = 25,
};
const InsertTextFormat = enum(f64) {
PlainText = 1,
Snippet = 2,
};
const DocumentHighlightKind = enum(f64) {
Text = 1,
Read = 2,
Write = 3,
};
const SymbolKind = enum(f64) {
File = 1,
Module = 2,
Namespace = 3,
Package = 4,
Class = 5,
Method = 6,
Property = 7,
Field = 8,
Constructor = 9,
Enum = 10,
Interface = 11,
Function = 12,
Variable = 13,
Constant = 14,
String = 15,
Number = 16,
Boolean = 17,
Array = 18,
Object = 19,
Key = 20,
Null = 21,
EnumMember = 22,
Struct = 23,
Event = 24,
Operator = 25,
TypeParameter = 26,
};
const CodeActionKind = enum {
QuickFix,
Refactor,
RefactorExtract,
RefactorInline,
RefactorRewrite,
Source,
SourceOrganizeImports,
pub fn toString(self: CodeActionKind) []const u8 {
return switch (self) {
CodeActionKind.QuickFix => "quickfix",
CodeActionKind.Refactor => "refactor",
CodeActionKind.RefactorExtract => "refactor.extract",
CodeActionKind.RefactorInline => "refactor.inline",
CodeActionKind.RefactorRewrite => "refactor.rewrite",
CodeActionKind.Source => "source",
CodeActionKind.SourceOrganizeImports => "source.organizeImports",
else => "",
};
}
};
const TextDocumentSaveReason = enum(f64) {
Manual = 1,
AfterDelay = 2,
FocusOut = 3,
};
// DocumentFilter is a type
const DocumentFilter = struct {
language: []const u8,
scheme: ?[]const u8,
pattern: ?[]const u8,
};
const DocumentSelector = ArrayList(DocumentFilter);
const DefinitionLink = LocationLink;
const DeclarationLink = LocationLink; | src/lsp/protocol/protocol.zig |
const std = @import("std");
const assert = std.debug.assert;
const img = @import("Image.zig");
const ImageType = img.ImageType;
const MinFilter = img.MinFilter;
const Texture2D = img.Texture2D;
const window = @import("Window.zig");
const c = @import("c.zig").c;
const ReferenceCounter = @import("../RefCount.zig").ReferenceCounter;
// Framebuffer with 2D backing texture
pub const FrameBuffer = struct {
ref_count: ReferenceCounter = ReferenceCounter{},
id: u32,
textures: [8]?*Texture2D = [_]?*Texture2D{null} ** 8,
texture_count: u32 = 0,
depth_texture: ?*Texture2D,
pub const DepthType = enum {
None,
I16,
I24,
I32,
F32,
};
depth_type: DepthType,
// If not null then the texture and/or depth texture were created with this and will be freed with it
allocator: ?*std.mem.Allocator = null,
pub fn init3(textures: []*Texture2D, depth_texture: ?*Texture2D) !FrameBuffer {
if (textures.len > 0) {
const w = textures[0].width;
const h = textures[0].height;
for (textures) |t| {
if (t.width != w or t.height != h) {
return error.InconsistentTextureDimensions;
}
t.ref_count.inc();
errdefer t.ref_count.dec();
}
}
if (depth_texture != null) {
depth_texture.?.ref_count.inc();
errdefer depth_texture.?.ref_count.dec();
}
// Create FBO
var id: u32 = 0;
c.glGenFramebuffers(1, @ptrCast([*c]c_uint, &id));
if (id == 0) {
assert(false);
return error.OpenGLError;
}
errdefer c.glDeleteFramebuffers(1, @ptrCast([*c]c_uint, &id));
c.glBindFramebuffer(c.GL_FRAMEBUFFER, id);
// Get image types
var depth_type: DepthType = DepthType.None;
if (depth_texture != null) {
const t = depth_texture.?.imageType;
if (t == ImageType.Depth16) {
depth_type = DepthType.I16;
} else if (t == ImageType.Depth24) {
depth_type = DepthType.I24;
} else if (t == ImageType.Depth32) {
depth_type = DepthType.I32;
} else if (t == ImageType.Depth32F) {
depth_type = DepthType.F32;
}
}
// Create object
var frameBuffer = FrameBuffer{
.id = id,
.depth_type = depth_type,
.depth_texture = depth_texture,
};
// Configure framebuffer
if (depth_type != DepthType.None) {
c.glFramebufferTexture2D(c.GL_FRAMEBUFFER, c.GL_DEPTH_ATTACHMENT, c.GL_TEXTURE_2D, depth_texture.?.id, 0);
}
if (textures.len == 0) {
c.glDrawBuffer(c.GL_NONE);
c.glReadBuffer(c.GL_NONE);
} else {
try frameBuffer.addMoreTextures(textures);
}
// Validate framebuffer
const status = c.glCheckFramebufferStatus(c.GL_FRAMEBUFFER);
if (status != c.GL_FRAMEBUFFER_COMPLETE) {
std.debug.warn("Framebuffer incomplete. Error: {}\n", .{status});
assert(false);
return error.OpenGLError;
}
c.glBindFramebuffer(c.GL_FRAMEBUFFER, 0);
return frameBuffer;
}
pub fn addMoreTextures(self: *FrameBuffer, textures: []*Texture2D) !void {
if (textures.len == 0) {
return;
}
var drawBuffers: [8]c_uint = [_]c_uint{c.GL_NONE} ** 8;
var i: u32 = 0;
for (self.textures) |t| {
if (t == null) {
break;
}
drawBuffers[i] = c.GL_COLOR_ATTACHMENT0 + @intCast(c_uint, i);
i += 1;
}
if (i + textures.len > 8) {
assert(false);
return error.TooManyTextures;
}
for (textures) |t| {
self.textures[i] = t;
drawBuffers[i] = c.GL_COLOR_ATTACHMENT0 + @intCast(c_uint, i);
self.texture_count += 1;
c.glFramebufferTexture2D(c.GL_FRAMEBUFFER, c.GL_COLOR_ATTACHMENT0 + @intCast(c_uint, i), c.GL_TEXTURE_2D, t.id, 0);
t.ref_count.inc();
i += 1;
}
c.glDrawBuffers(@intCast(c_int, textures.len), drawBuffers[0..textures.len].ptr);
}
pub fn init2(texture: ?*Texture2D, depth_texture: ?*Texture2D) !FrameBuffer {
if (texture == null and depth_texture == null) {
return error.ParameterError;
}
if (texture != null) {
var p = [1]*Texture2D{texture.?};
return try init3(p[0..], depth_texture);
} else {
return try init3(&[0]*Texture2D{}, depth_texture);
}
}
// image_type: If null then no colour buffer is created
pub fn init(image_type: ?ImageType, width: u32, height: u32, depth_type: DepthType, allocator: *std.mem.Allocator) !FrameBuffer {
if (depth_type == DepthType.None and image_type == null) {
return error.NoTexture;
}
if (image_type != null and (image_type.? == ImageType.Depth16 or image_type.? == ImageType.Depth24 or image_type.? == ImageType.Depth32 or image_type.? == ImageType.Depth32)) {
return error.ColourTextureCannotHaveDepthType;
}
// Create backing texture
var texture: ?*Texture2D = null;
var depth_texture: ?*Texture2D = null;
if (image_type != null) {
texture = try allocator.create(Texture2D);
texture.?.* = try Texture2D.init(false, img.MinFilter.Nearest);
errdefer texture.?.free();
try texture.?.upload(width, height, image_type.?, null);
}
if (depth_type != DepthType.None) {
// Create depth buffer
depth_texture = &(try allocator.alloc(Texture2D, 1))[0];
depth_texture.?.* = try Texture2D.init(false, img.MinFilter.Nearest);
errdefer depth_texture.?.free();
if (depth_type == DepthType.I16) {
try depth_texture.?.upload(width, height, ImageType.Depth16, null);
} else if (depth_type == DepthType.I24) {
try depth_texture.?.upload(width, height, ImageType.Depth24, null);
} else if (depth_type == DepthType.I32) {
try depth_texture.?.upload(width, height, ImageType.Depth32, null);
} else if (depth_type == DepthType.F32) {
try depth_texture.?.upload(width, height, ImageType.Depth32F, null);
}
}
var fb = try init2(texture, depth_texture);
fb.allocator = allocator;
return fb;
}
pub fn setTextureFiltering(self: *FrameBuffer, min_blur: bool, mag_blur: bool) !void {
try self.bindTexture();
for (self.textures) |*t| {
if (t.* == null) {
break;
}
if (min_blur) {
try t.*.?.setFiltering(mag_blur, MinFilter.Linear);
} else {
try t.*.?.setFiltering(mag_blur, MinFilter.Nearest);
}
}
}
// Bind for drawing
pub fn bind(self: *FrameBuffer) !void {
if (self.id == 0) {
assert(false);
return error.InvalidState;
}
c.glBindFramebuffer(c.GL_DRAW_FRAMEBUFFER, self.id);
if (self.textures[0] == null) {
c.glViewport(0, 0, @intCast(c_int, self.depth_texture.?.width), @intCast(c_int, self.depth_texture.?.height));
} else {
c.glViewport(0, 0, @intCast(c_int, self.textures[0].?.width), @intCast(c_int, self.textures[0].?.height));
}
}
pub fn bindTexture(self: FrameBuffer) !void {
try self.textures[0].?.bind();
}
pub fn bindTextureToUnit(self: FrameBuffer, unit: u32) !void {
try self.textures[0].?.bindToUnit(unit);
}
pub fn bindDepthTexture(self: FrameBuffer) !void {
try self.depth_texture.?.bind();
}
pub fn bindDepthTextureToUnit(self: FrameBuffer, unit: u32) !void {
try self.depth_texture.?.bindToUnit(unit);
}
pub fn free(self: *FrameBuffer) void {
if (self.id == 0) {
assert(false);
return;
}
self.ref_count.deinit();
for (self.textures) |t| {
if (t != null) {
t.?.ref_count.dec();
}
}
if (self.depth_texture != null) {
self.depth_texture.?.ref_count.dec();
}
c.glDeleteFramebuffers(1, @ptrCast([*c]const c_uint, &self.id));
if (self.allocator != null) {
for (self.textures) |t| {
if (t != null) {
self.allocator.?.destroy(t.?);
}
}
if (self.depth_texture != null) {
self.allocator.?.destroy(self.depth_texture.?);
}
}
}
pub fn bindDefaultFrameBuffer() void {
c.glBindFramebuffer(c.GL_FRAMEBUFFER, 0);
var window_width: u32 = 0;
var window_height: u32 = 0;
window.getSize(&window_width, &window_height);
c.glViewport(0, 0, @intCast(c_int, window_width), @intCast(c_int, window_height));
}
fn setTextureSizes(self: *FrameBuffer, new_width: u32, new_height: u32) !void {
for (self.textures) |t| {
if (t != null) {
try t.?.upload(new_width, new_height, t.?.imageType, null);
}
}
if (self.depth_texture != null) {
if (self.depth_type == DepthType.I16) {
try self.depth_texture.?.upload(new_width, new_height, ImageType.Depth16, null);
} else if (self.depth_type == DepthType.I24) {
try self.depth_texture.?.upload(new_width, new_height, ImageType.Depth24, null);
} else if (self.depth_type == DepthType.I32) {
try self.depth_texture.?.upload(new_width, new_height, ImageType.Depth32, null);
} else if (self.depth_type == DepthType.F32) {
try self.depth_texture.?.upload(new_width, new_height, ImageType.Depth32F, null);
} else {
assert(false);
}
}
}
// Active framebuffer will be unbound
pub fn resize(self: *FrameBuffer, new_width: u32, new_height: u32) !void {
c.glBindFramebuffer(c.GL_FRAMEBUFFER, 0);
try self.setTextureSizes(new_width, new_height);
}
};
test "framebuffer" {
try window.createWindow(false, 200, 200, "test", true, 0);
var a = std.heap.c_allocator;
var fb: FrameBuffer = try FrameBuffer.init(ImageType.R, 200, 200, FrameBuffer.DepthType.I16, a);
try fb.bind();
fb.free();
window.closeWindow();
} | src/WindowGraphicsInput/FrameBuffer.zig |
const vk = @import("vulkan.zig");
// TODO:
// - generate wrapers to convert
// \b([a-z])([a-zA-Z]*)Count: u32, p\u\2s: \[\*c\]
// to
// \1\2s: []
//
// - remove common enum suffixes
pub const createInstance = vk.vkCreateInstance;
pub const destroyInstance = vk.vkDestroyInstance;
pub const enumeratePhysicalDevices = vk.vkEnumeratePhysicalDevices;
pub const getPhysicalDeviceFeatures = vk.vkGetPhysicalDeviceFeatures;
pub const getPhysicalDeviceFormatProperties = vk.vkGetPhysicalDeviceFormatProperties;
pub const getPhysicalDeviceImageFormatProperties = vk.vkGetPhysicalDeviceImageFormatProperties;
pub const getPhysicalDeviceProperties = vk.vkGetPhysicalDeviceProperties;
pub const getPhysicalDeviceQueueFamilyProperties = vk.vkGetPhysicalDeviceQueueFamilyProperties;
pub const getPhysicalDeviceMemoryProperties = vk.vkGetPhysicalDeviceMemoryProperties;
pub const getInstanceProcAddr = vk.vkGetInstanceProcAddr;
pub const getDeviceProcAddr = vk.vkGetDeviceProcAddr;
pub const createDevice = vk.vkCreateDevice;
pub const destroyDevice = vk.vkDestroyDevice;
pub const enumerateInstanceExtensionProperties = vk.vkEnumerateInstanceExtensionProperties;
pub const enumerateDeviceExtensionProperties = vk.vkEnumerateDeviceExtensionProperties;
pub const enumerateInstanceLayerProperties = vk.vkEnumerateInstanceLayerProperties;
pub const enumerateDeviceLayerProperties = vk.vkEnumerateDeviceLayerProperties;
pub const getDeviceQueue = vk.vkGetDeviceQueue;
pub const queueSubmit = vk.vkQueueSubmit;
pub const queueWaitIdle = vk.vkQueueWaitIdle;
pub const deviceWaitIdle = vk.vkDeviceWaitIdle;
pub const allocateMemory = vk.vkAllocateMemory;
pub const freeMemory = vk.vkFreeMemory;
pub const mapMemory = vk.vkMapMemory;
pub const unmapMemory = vk.vkUnmapMemory;
pub const flushMappedMemoryRanges = vk.vkFlushMappedMemoryRanges;
pub const invalidateMappedMemoryRanges = vk.vkInvalidateMappedMemoryRanges;
pub const getDeviceMemoryCommitment = vk.vkGetDeviceMemoryCommitment;
pub const bindBufferMemory = vk.vkBindBufferMemory;
pub const bindImageMemory = vk.vkBindImageMemory;
pub const getBufferMemoryRequirements = vk.vkGetBufferMemoryRequirements;
pub const getImageMemoryRequirements = vk.vkGetImageMemoryRequirements;
pub const getImageSparseMemoryRequirements = vk.vkGetImageSparseMemoryRequirements;
pub const getPhysicalDeviceSparseImageFormatProperties = vk.vkGetPhysicalDeviceSparseImageFormatProperties;
pub const queueBindSparse = vk.vkQueueBindSparse;
pub const createFence = vk.vkCreateFence;
pub const destroyFence = vk.vkDestroyFence;
pub const resetFences = vk.vkResetFences;
pub const getFenceStatus = vk.vkGetFenceStatus;
pub const waitForFences = vk.vkWaitForFences;
pub const createSemaphore = vk.vkCreateSemaphore;
pub const destroySemaphore = vk.vkDestroySemaphore;
pub const createEvent = vk.vkCreateEvent;
pub const destroyEvent = vk.vkDestroyEvent;
pub const getEventStatus = vk.vkGetEventStatus;
pub const setEvent = vk.vkSetEvent;
pub const resetEvent = vk.vkResetEvent;
pub const createQueryPool = vk.vkCreateQueryPool;
pub const destroyQueryPool = vk.vkDestroyQueryPool;
pub const getQueryPoolResults = vk.vkGetQueryPoolResults;
pub const createBuffer = vk.vkCreateBuffer;
pub const destroyBuffer = vk.vkDestroyBuffer;
pub const createBufferView = vk.vkCreateBufferView;
pub const destroyBufferView = vk.vkDestroyBufferView;
pub const createImage = vk.vkCreateImage;
pub const destroyImage = vk.vkDestroyImage;
pub const getImageSubresourceLayout = vk.vkGetImageSubresourceLayout;
pub const createImageView = vk.vkCreateImageView;
pub const destroyImageView = vk.vkDestroyImageView;
pub const createShaderModule = vk.vkCreateShaderModule;
pub const destroyShaderModule = vk.vkDestroyShaderModule;
pub const createPipelineCache = vk.vkCreatePipelineCache;
pub const destroyPipelineCache = vk.vkDestroyPipelineCache;
pub const getPipelineCacheData = vk.vkGetPipelineCacheData;
pub const mergePipelineCaches = vk.vkMergePipelineCaches;
pub const createGraphicsPipelines = vk.vkCreateGraphicsPipelines;
pub const createComputePipelines = vk.vkCreateComputePipelines;
pub const destroyPipeline = vk.vkDestroyPipeline;
pub const createPipelineLayout = vk.vkCreatePipelineLayout;
pub const destroyPipelineLayout = vk.vkDestroyPipelineLayout;
pub const createSampler = vk.vkCreateSampler;
pub const destroySampler = vk.vkDestroySampler;
pub const createDescriptorSetLayout = vk.vkCreateDescriptorSetLayout;
pub const destroyDescriptorSetLayout = vk.vkDestroyDescriptorSetLayout;
pub const createDescriptorPool = vk.vkCreateDescriptorPool;
pub const destroyDescriptorPool = vk.vkDestroyDescriptorPool;
pub const resetDescriptorPool = vk.vkResetDescriptorPool;
pub const allocateDescriptorSets = vk.vkAllocateDescriptorSets;
pub const freeDescriptorSets = vk.vkFreeDescriptorSets;
pub const updateDescriptorSets = vk.vkUpdateDescriptorSets;
pub const createFramebuffer = vk.vkCreateFramebuffer;
pub const destroyFramebuffer = vk.vkDestroyFramebuffer;
pub const createRenderPass = vk.vkCreateRenderPass;
pub const destroyRenderPass = vk.vkDestroyRenderPass;
pub const getRenderAreaGranularity = vk.vkGetRenderAreaGranularity;
pub const createCommandPool = vk.vkCreateCommandPool;
pub const destroyCommandPool = vk.vkDestroyCommandPool;
pub const resetCommandPool = vk.vkResetCommandPool;
pub const allocateCommandBuffers = vk.vkAllocateCommandBuffers;
pub const freeCommandBuffers = vk.vkFreeCommandBuffers;
pub const beginCommandBuffer = vk.vkBeginCommandBuffer;
pub const endCommandBuffer = vk.vkEndCommandBuffer;
pub const resetCommandBuffer = vk.vkResetCommandBuffer;
pub const cmdBindPipeline = vk.vkCmdBindPipeline;
pub const cmdSetViewport = vk.vkCmdSetViewport;
pub const cmdSetScissor = vk.vkCmdSetScissor;
pub const cmdSetLineWidth = vk.vkCmdSetLineWidth;
pub const cmdSetDepthBias = vk.vkCmdSetDepthBias;
pub const cmdSetBlendConstants = vk.vkCmdSetBlendConstants;
pub const cmdSetDepthBounds = vk.vkCmdSetDepthBounds;
pub const cmdSetStencilCompareMask = vk.vkCmdSetStencilCompareMask;
pub const cmdSetStencilWriteMask = vk.vkCmdSetStencilWriteMask;
pub const cmdSetStencilReference = vk.vkCmdSetStencilReference;
pub const cmdBindDescriptorSets = vk.vkCmdBindDescriptorSets;
pub const cmdBindIndexBuffer = vk.vkCmdBindIndexBuffer;
pub const cmdBindVertexBuffers = vk.vkCmdBindVertexBuffers;
pub const cmdDraw = vk.vkCmdDraw;
pub const cmdDrawIndexed = vk.vkCmdDrawIndexed;
pub const cmdDrawIndirect = vk.vkCmdDrawIndirect;
pub const cmdDrawIndexedIndirect = vk.vkCmdDrawIndexedIndirect;
pub const cmdDispatch = vk.vkCmdDispatch;
pub const cmdDispatchIndirect = vk.vkCmdDispatchIndirect;
pub const cmdCopyBuffer = vk.vkCmdCopyBuffer;
pub const cmdCopyImage = vk.vkCmdCopyImage;
pub const cmdBlitImage = vk.vkCmdBlitImage;
pub const cmdCopyBufferToImage = vk.vkCmdCopyBufferToImage;
pub const cmdCopyImageToBuffer = vk.vkCmdCopyImageToBuffer;
pub const cmdUpdateBuffer = vk.vkCmdUpdateBuffer;
pub const cmdFillBuffer = vk.vkCmdFillBuffer;
pub const cmdClearColorImage = vk.vkCmdClearColorImage;
pub const cmdClearDepthStencilImage = vk.vkCmdClearDepthStencilImage;
pub const cmdClearAttachments = vk.vkCmdClearAttachments;
pub const cmdResolveImage = vk.vkCmdResolveImage;
pub const cmdSetEvent = vk.vkCmdSetEvent;
pub const cmdResetEvent = vk.vkCmdResetEvent;
pub const cmdWaitEvents = vk.vkCmdWaitEvents;
pub const cmdPipelineBarrier = vk.vkCmdPipelineBarrier;
pub const cmdBeginQuery = vk.vkCmdBeginQuery;
pub const cmdEndQuery = vk.vkCmdEndQuery;
pub const cmdResetQueryPool = vk.vkCmdResetQueryPool;
pub const cmdWriteTimestamp = vk.vkCmdWriteTimestamp;
pub const cmdCopyQueryPoolResults = vk.vkCmdCopyQueryPoolResults;
pub const cmdPushConstants = vk.vkCmdPushConstants;
pub const cmdBeginRenderPass = vk.vkCmdBeginRenderPass;
pub const cmdNextSubpass = vk.vkCmdNextSubpass;
pub const cmdEndRenderPass = vk.vkCmdEndRenderPass;
pub const cmdExecuteCommands = vk.vkCmdExecuteCommands;
pub const enumerateInstanceVersion = vk.vkEnumerateInstanceVersion;
pub const bindBufferMemory2 = vk.vkBindBufferMemory2;
pub const bindImageMemory2 = vk.vkBindImageMemory2;
pub const getDeviceGroupPeerMemoryFeatures = vk.vkGetDeviceGroupPeerMemoryFeatures;
pub const cmdSetDeviceMask = vk.vkCmdSetDeviceMask;
pub const cmdDispatchBase = vk.vkCmdDispatchBase;
pub const enumeratePhysicalDeviceGroups = vk.vkEnumeratePhysicalDeviceGroups;
pub const getImageMemoryRequirements2 = vk.vkGetImageMemoryRequirements2;
pub const getBufferMemoryRequirements2 = vk.vkGetBufferMemoryRequirements2;
pub const getImageSparseMemoryRequirements2 = vk.vkGetImageSparseMemoryRequirements2;
pub const getPhysicalDeviceFeatures2 = vk.vkGetPhysicalDeviceFeatures2;
pub const getPhysicalDeviceProperties2 = vk.vkGetPhysicalDeviceProperties2;
pub const getPhysicalDeviceFormatProperties2 = vk.vkGetPhysicalDeviceFormatProperties2;
pub const getPhysicalDeviceImageFormatProperties2 = vk.vkGetPhysicalDeviceImageFormatProperties2;
pub const getPhysicalDeviceQueueFamilyProperties2 = vk.vkGetPhysicalDeviceQueueFamilyProperties2;
pub const getPhysicalDeviceMemoryProperties2 = vk.vkGetPhysicalDeviceMemoryProperties2;
pub const getPhysicalDeviceSparseImageFormatProperties2 = vk.vkGetPhysicalDeviceSparseImageFormatProperties2;
pub const trimCommandPool = vk.vkTrimCommandPool;
pub const getDeviceQueue2 = vk.vkGetDeviceQueue2;
pub const createSamplerYcbcrConversion = vk.vkCreateSamplerYcbcrConversion;
pub const destroySamplerYcbcrConversion = vk.vkDestroySamplerYcbcrConversion;
pub const createDescriptorUpdateTemplate = vk.vkCreateDescriptorUpdateTemplate;
pub const destroyDescriptorUpdateTemplate = vk.vkDestroyDescriptorUpdateTemplate;
pub const updateDescriptorSetWithTemplate = vk.vkUpdateDescriptorSetWithTemplate;
pub const getPhysicalDeviceExternalBufferProperties = vk.vkGetPhysicalDeviceExternalBufferProperties;
pub const getPhysicalDeviceExternalFenceProperties = vk.vkGetPhysicalDeviceExternalFenceProperties;
pub const getPhysicalDeviceExternalSemaphoreProperties = vk.vkGetPhysicalDeviceExternalSemaphoreProperties;
pub const getDescriptorSetLayoutSupport = vk.vkGetDescriptorSetLayoutSupport;
pub const cmdDrawIndirectCount = vk.vkCmdDrawIndirectCount;
pub const cmdDrawIndexedIndirectCount = vk.vkCmdDrawIndexedIndirectCount;
pub const createRenderPass2 = vk.vkCreateRenderPass2;
pub const cmdBeginRenderPass2 = vk.vkCmdBeginRenderPass2;
pub const cmdNextSubpass2 = vk.vkCmdNextSubpass2;
pub const cmdEndRenderPass2 = vk.vkCmdEndRenderPass2;
pub const resetQueryPool = vk.vkResetQueryPool;
pub const getSemaphoreCounterValue = vk.vkGetSemaphoreCounterValue;
pub const waitSemaphores = vk.vkWaitSemaphores;
pub const signalSemaphore = vk.vkSignalSemaphore;
pub const getBufferDeviceAddress = vk.vkGetBufferDeviceAddress;
pub const getBufferOpaqueCaptureAddress = vk.vkGetBufferOpaqueCaptureAddress;
pub const getDeviceMemoryOpaqueCaptureAddress = vk.vkGetDeviceMemoryOpaqueCaptureAddress;
pub const destroySurfaceKHR = vk.vkDestroySurfaceKHR;
pub const getPhysicalDeviceSurfaceSupportKHR = vk.vkGetPhysicalDeviceSurfaceSupportKHR;
pub const getPhysicalDeviceSurfaceCapabilitiesKHR = vk.vkGetPhysicalDeviceSurfaceCapabilitiesKHR;
pub const getPhysicalDeviceSurfaceFormatsKHR = vk.vkGetPhysicalDeviceSurfaceFormatsKHR;
pub const getPhysicalDeviceSurfacePresentModesKHR = vk.vkGetPhysicalDeviceSurfacePresentModesKHR;
pub const createSwapchainKHR = vk.vkCreateSwapchainKHR;
pub const destroySwapchainKHR = vk.vkDestroySwapchainKHR;
pub const getSwapchainImagesKHR = vk.vkGetSwapchainImagesKHR;
pub const acquireNextImageKHR = vk.vkAcquireNextImageKHR;
pub const queuePresentKHR = vk.vkQueuePresentKHR;
pub const getDeviceGroupPresentCapabilitiesKHR = vk.vkGetDeviceGroupPresentCapabilitiesKHR;
pub const getDeviceGroupSurfacePresentModesKHR = vk.vkGetDeviceGroupSurfacePresentModesKHR;
pub const getPhysicalDevicePresentRectanglesKHR = vk.vkGetPhysicalDevicePresentRectanglesKHR;
pub const acquireNextImage2KHR = vk.vkAcquireNextImage2KHR;
pub const getPhysicalDeviceDisplayPropertiesKHR = vk.vkGetPhysicalDeviceDisplayPropertiesKHR;
pub const getPhysicalDeviceDisplayPlanePropertiesKHR = vk.vkGetPhysicalDeviceDisplayPlanePropertiesKHR;
pub const getDisplayPlaneSupportedDisplaysKHR = vk.vkGetDisplayPlaneSupportedDisplaysKHR;
pub const getDisplayModePropertiesKHR = vk.vkGetDisplayModePropertiesKHR;
pub const createDisplayModeKHR = vk.vkCreateDisplayModeKHR;
pub const getDisplayPlaneCapabilitiesKHR = vk.vkGetDisplayPlaneCapabilitiesKHR;
pub const createDisplayPlaneSurfaceKHR = vk.vkCreateDisplayPlaneSurfaceKHR;
pub const createSharedSwapchainsKHR = vk.vkCreateSharedSwapchainsKHR;
pub const getPhysicalDeviceFeatures2KHR = vk.vkGetPhysicalDeviceFeatures2KHR;
pub const getPhysicalDeviceProperties2KHR = vk.vkGetPhysicalDeviceProperties2KHR;
pub const getPhysicalDeviceFormatProperties2KHR = vk.vkGetPhysicalDeviceFormatProperties2KHR;
pub const getPhysicalDeviceImageFormatProperties2KHR = vk.vkGetPhysicalDeviceImageFormatProperties2KHR;
pub const getPhysicalDeviceQueueFamilyProperties2KHR = vk.vkGetPhysicalDeviceQueueFamilyProperties2KHR;
pub const getPhysicalDeviceMemoryProperties2KHR = vk.vkGetPhysicalDeviceMemoryProperties2KHR;
pub const getPhysicalDeviceSparseImageFormatProperties2KHR = vk.vkGetPhysicalDeviceSparseImageFormatProperties2KHR;
pub const getDeviceGroupPeerMemoryFeaturesKHR = vk.vkGetDeviceGroupPeerMemoryFeaturesKHR;
pub const cmdSetDeviceMaskKHR = vk.vkCmdSetDeviceMaskKHR;
pub const cmdDispatchBaseKHR = vk.vkCmdDispatchBaseKHR;
pub const trimCommandPoolKHR = vk.vkTrimCommandPoolKHR;
pub const enumeratePhysicalDeviceGroupsKHR = vk.vkEnumeratePhysicalDeviceGroupsKHR;
pub const getPhysicalDeviceExternalBufferPropertiesKHR = vk.vkGetPhysicalDeviceExternalBufferPropertiesKHR;
pub const getMemoryFdKHR = vk.vkGetMemoryFdKHR;
pub const getMemoryFdPropertiesKHR = vk.vkGetMemoryFdPropertiesKHR;
pub const getPhysicalDeviceExternalSemaphorePropertiesKHR = vk.vkGetPhysicalDeviceExternalSemaphorePropertiesKHR;
pub const importSemaphoreFdKHR = vk.vkImportSemaphoreFdKHR;
pub const getSemaphoreFdKHR = vk.vkGetSemaphoreFdKHR;
pub const cmdPushDescriptorSetKHR = vk.vkCmdPushDescriptorSetKHR;
pub const cmdPushDescriptorSetWithTemplateKHR = vk.vkCmdPushDescriptorSetWithTemplateKHR;
pub const createDescriptorUpdateTemplateKHR = vk.vkCreateDescriptorUpdateTemplateKHR;
pub const destroyDescriptorUpdateTemplateKHR = vk.vkDestroyDescriptorUpdateTemplateKHR;
pub const updateDescriptorSetWithTemplateKHR = vk.vkUpdateDescriptorSetWithTemplateKHR;
pub const createRenderPass2KHR = vk.vkCreateRenderPass2KHR;
pub const cmdBeginRenderPass2KHR = vk.vkCmdBeginRenderPass2KHR;
pub const cmdNextSubpass2KHR = vk.vkCmdNextSubpass2KHR;
pub const cmdEndRenderPass2KHR = vk.vkCmdEndRenderPass2KHR;
pub const getSwapchainStatusKHR = vk.vkGetSwapchainStatusKHR;
pub const getPhysicalDeviceExternalFencePropertiesKHR = vk.vkGetPhysicalDeviceExternalFencePropertiesKHR;
pub const importFenceFdKHR = vk.vkImportFenceFdKHR;
pub const getFenceFdKHR = vk.vkGetFenceFdKHR;
pub const enumeratePhysicalDeviceQueueFamilyPerformanceQueryCountersKHR = vk.vkEnumeratePhysicalDeviceQueueFamilyPerformanceQueryCountersKHR;
pub const getPhysicalDeviceQueueFamilyPerformanceQueryPassesKHR = vk.vkGetPhysicalDeviceQueueFamilyPerformanceQueryPassesKHR;
pub const acquireProfilingLockKHR = vk.vkAcquireProfilingLockKHR;
pub const releaseProfilingLockKHR = vk.vkReleaseProfilingLockKHR;
pub const getPhysicalDeviceSurfaceCapabilities2KHR = vk.vkGetPhysicalDeviceSurfaceCapabilities2KHR;
pub const getPhysicalDeviceSurfaceFormats2KHR = vk.vkGetPhysicalDeviceSurfaceFormats2KHR;
pub const getPhysicalDeviceDisplayProperties2KHR = vk.vkGetPhysicalDeviceDisplayProperties2KHR;
pub const getPhysicalDeviceDisplayPlaneProperties2KHR = vk.vkGetPhysicalDeviceDisplayPlaneProperties2KHR;
pub const getDisplayModeProperties2KHR = vk.vkGetDisplayModeProperties2KHR;
pub const getDisplayPlaneCapabilities2KHR = vk.vkGetDisplayPlaneCapabilities2KHR;
pub const getImageMemoryRequirements2KHR = vk.vkGetImageMemoryRequirements2KHR;
pub const getBufferMemoryRequirements2KHR = vk.vkGetBufferMemoryRequirements2KHR;
pub const getImageSparseMemoryRequirements2KHR = vk.vkGetImageSparseMemoryRequirements2KHR;
pub const createSamplerYcbcrConversionKHR = vk.vkCreateSamplerYcbcrConversionKHR;
pub const destroySamplerYcbcrConversionKHR = vk.vkDestroySamplerYcbcrConversionKHR;
pub const bindBufferMemory2KHR = vk.vkBindBufferMemory2KHR;
pub const bindImageMemory2KHR = vk.vkBindImageMemory2KHR;
pub const getDescriptorSetLayoutSupportKHR = vk.vkGetDescriptorSetLayoutSupportKHR;
pub const cmdDrawIndirectCountKHR = vk.vkCmdDrawIndirectCountKHR;
pub const cmdDrawIndexedIndirectCountKHR = vk.vkCmdDrawIndexedIndirectCountKHR;
pub const getSemaphoreCounterValueKHR = vk.vkGetSemaphoreCounterValueKHR;
pub const waitSemaphoresKHR = vk.vkWaitSemaphoresKHR;
pub const signalSemaphoreKHR = vk.vkSignalSemaphoreKHR;
pub const getPhysicalDeviceFragmentShadingRatesKHR = vk.vkGetPhysicalDeviceFragmentShadingRatesKHR;
pub const cmdSetFragmentShadingRateKHR = vk.vkCmdSetFragmentShadingRateKHR;
pub const getBufferDeviceAddressKHR = vk.vkGetBufferDeviceAddressKHR;
pub const getBufferOpaqueCaptureAddressKHR = vk.vkGetBufferOpaqueCaptureAddressKHR;
pub const getDeviceMemoryOpaqueCaptureAddressKHR = vk.vkGetDeviceMemoryOpaqueCaptureAddressKHR;
pub const getPipelineExecutablePropertiesKHR = vk.vkGetPipelineExecutablePropertiesKHR;
pub const getPipelineExecutableStatisticsKHR = vk.vkGetPipelineExecutableStatisticsKHR;
pub const getPipelineExecutableInternalRepresentationsKHR = vk.vkGetPipelineExecutableInternalRepresentationsKHR;
pub const cmdCopyBuffer2KHR = vk.vkCmdCopyBuffer2KHR;
pub const cmdCopyImage2KHR = vk.vkCmdCopyImage2KHR;
pub const cmdCopyBufferToImage2KHR = vk.vkCmdCopyBufferToImage2KHR;
pub const cmdCopyImageToBuffer2KHR = vk.vkCmdCopyImageToBuffer2KHR;
pub const cmdBlitImage2KHR = vk.vkCmdBlitImage2KHR;
pub const cmdResolveImage2KHR = vk.vkCmdResolveImage2KHR;
pub const createDebugReportCallbackEXT = vk.vkCreateDebugReportCallbackEXT;
pub const destroyDebugReportCallbackEXT = vk.vkDestroyDebugReportCallbackEXT;
pub const debugReportMessageEXT = vk.vkDebugReportMessageEXT;
pub const debugMarkerSetObjectTagEXT = vk.vkDebugMarkerSetObjectTagEXT;
pub const debugMarkerSetObjectNameEXT = vk.vkDebugMarkerSetObjectNameEXT;
pub const cmdDebugMarkerBeginEXT = vk.vkCmdDebugMarkerBeginEXT;
pub const cmdDebugMarkerEndEXT = vk.vkCmdDebugMarkerEndEXT;
pub const cmdDebugMarkerInsertEXT = vk.vkCmdDebugMarkerInsertEXT;
pub const cmdBindTransformFeedbackBuffersEXT = vk.vkCmdBindTransformFeedbackBuffersEXT;
pub const cmdBeginTransformFeedbackEXT = vk.vkCmdBeginTransformFeedbackEXT;
pub const cmdEndTransformFeedbackEXT = vk.vkCmdEndTransformFeedbackEXT;
pub const cmdBeginQueryIndexedEXT = vk.vkCmdBeginQueryIndexedEXT;
pub const cmdEndQueryIndexedEXT = vk.vkCmdEndQueryIndexedEXT;
pub const cmdDrawIndirectByteCountEXT = vk.vkCmdDrawIndirectByteCountEXT;
pub const getImageViewHandleNVX = vk.vkGetImageViewHandleNVX;
pub const getImageViewAddressNVX = vk.vkGetImageViewAddressNVX;
pub const cmdDrawIndirectCountAMD = vk.vkCmdDrawIndirectCountAMD;
pub const cmdDrawIndexedIndirectCountAMD = vk.vkCmdDrawIndexedIndirectCountAMD;
pub const getShaderInfoAMD = vk.vkGetShaderInfoAMD;
pub const getPhysicalDeviceExternalImageFormatPropertiesNV = vk.vkGetPhysicalDeviceExternalImageFormatPropertiesNV;
pub const cmdBeginConditionalRenderingEXT = vk.vkCmdBeginConditionalRenderingEXT;
pub const cmdEndConditionalRenderingEXT = vk.vkCmdEndConditionalRenderingEXT;
pub const cmdSetViewportWScalingNV = vk.vkCmdSetViewportWScalingNV;
pub const releaseDisplayEXT = vk.vkReleaseDisplayEXT;
pub const getPhysicalDeviceSurfaceCapabilities2EXT = vk.vkGetPhysicalDeviceSurfaceCapabilities2EXT;
pub const displayPowerControlEXT = vk.vkDisplayPowerControlEXT;
pub const registerDeviceEventEXT = vk.vkRegisterDeviceEventEXT;
pub const registerDisplayEventEXT = vk.vkRegisterDisplayEventEXT;
pub const getSwapchainCounterEXT = vk.vkGetSwapchainCounterEXT;
pub const getRefreshCycleDurationGOOGLE = vk.vkGetRefreshCycleDurationGOOGLE;
pub const getPastPresentationTimingGOOGLE = vk.vkGetPastPresentationTimingGOOGLE;
pub const cmdSetDiscardRectangleEXT = vk.vkCmdSetDiscardRectangleEXT;
pub const setHdrMetadataEXT = vk.vkSetHdrMetadataEXT;
pub const setDebugUtilsObjectNameEXT = vk.vkSetDebugUtilsObjectNameEXT;
pub const setDebugUtilsObjectTagEXT = vk.vkSetDebugUtilsObjectTagEXT;
pub const queueBeginDebugUtilsLabelEXT = vk.vkQueueBeginDebugUtilsLabelEXT;
pub const queueEndDebugUtilsLabelEXT = vk.vkQueueEndDebugUtilsLabelEXT;
pub const queueInsertDebugUtilsLabelEXT = vk.vkQueueInsertDebugUtilsLabelEXT;
pub const cmdBeginDebugUtilsLabelEXT = vk.vkCmdBeginDebugUtilsLabelEXT;
pub const cmdEndDebugUtilsLabelEXT = vk.vkCmdEndDebugUtilsLabelEXT;
pub const cmdInsertDebugUtilsLabelEXT = vk.vkCmdInsertDebugUtilsLabelEXT;
pub const createDebugUtilsMessengerEXT = vk.vkCreateDebugUtilsMessengerEXT;
pub const destroyDebugUtilsMessengerEXT = vk.vkDestroyDebugUtilsMessengerEXT;
pub const submitDebugUtilsMessageEXT = vk.vkSubmitDebugUtilsMessageEXT;
pub const cmdSetSampleLocationsEXT = vk.vkCmdSetSampleLocationsEXT;
pub const getPhysicalDeviceMultisamplePropertiesEXT = vk.vkGetPhysicalDeviceMultisamplePropertiesEXT;
pub const getImageDrmFormatModifierPropertiesEXT = vk.vkGetImageDrmFormatModifierPropertiesEXT;
pub const createValidationCacheEXT = vk.vkCreateValidationCacheEXT;
pub const destroyValidationCacheEXT = vk.vkDestroyValidationCacheEXT;
pub const mergeValidationCachesEXT = vk.vkMergeValidationCachesEXT;
pub const getValidationCacheDataEXT = vk.vkGetValidationCacheDataEXT;
pub const cmdBindShadingRateImageNV = vk.vkCmdBindShadingRateImageNV;
pub const cmdSetViewportShadingRatePaletteNV = vk.vkCmdSetViewportShadingRatePaletteNV;
pub const cmdSetCoarseSampleOrderNV = vk.vkCmdSetCoarseSampleOrderNV;
pub const createAccelerationStructureNV = vk.vkCreateAccelerationStructureNV;
pub const destroyAccelerationStructureKHR = vk.vkDestroyAccelerationStructureKHR;
pub const destroyAccelerationStructureNV = vk.vkDestroyAccelerationStructureNV;
pub const getAccelerationStructureMemoryRequirementsNV = vk.vkGetAccelerationStructureMemoryRequirementsNV;
pub const bindAccelerationStructureMemoryKHR = vk.vkBindAccelerationStructureMemoryKHR;
pub const bindAccelerationStructureMemoryNV = vk.vkBindAccelerationStructureMemoryNV;
pub const cmdBuildAccelerationStructureNV = vk.vkCmdBuildAccelerationStructureNV;
pub const cmdCopyAccelerationStructureNV = vk.vkCmdCopyAccelerationStructureNV;
pub const cmdTraceRaysNV = vk.vkCmdTraceRaysNV;
pub const createRayTracingPipelinesNV = vk.vkCreateRayTracingPipelinesNV;
pub const getRayTracingShaderGroupHandlesKHR = vk.vkGetRayTracingShaderGroupHandlesKHR;
pub const getRayTracingShaderGroupHandlesNV = vk.vkGetRayTracingShaderGroupHandlesNV;
pub const getAccelerationStructureHandleNV = vk.vkGetAccelerationStructureHandleNV;
pub const cmdWriteAccelerationStructuresPropertiesKHR = vk.vkCmdWriteAccelerationStructuresPropertiesKHR;
pub const cmdWriteAccelerationStructuresPropertiesNV = vk.vkCmdWriteAccelerationStructuresPropertiesNV;
pub const compileDeferredNV = vk.vkCompileDeferredNV;
pub const getMemoryHostPointerPropertiesEXT = vk.vkGetMemoryHostPointerPropertiesEXT;
pub const cmdWriteBufferMarkerAMD = vk.vkCmdWriteBufferMarkerAMD;
pub const getPhysicalDeviceCalibrateableTimeDomainsEXT = vk.vkGetPhysicalDeviceCalibrateableTimeDomainsEXT;
pub const getCalibratedTimestampsEXT = vk.vkGetCalibratedTimestampsEXT;
pub const cmdDrawMeshTasksNV = vk.vkCmdDrawMeshTasksNV;
pub const cmdDrawMeshTasksIndirectNV = vk.vkCmdDrawMeshTasksIndirectNV;
pub const cmdDrawMeshTasksIndirectCountNV = vk.vkCmdDrawMeshTasksIndirectCountNV;
pub const cmdSetExclusiveScissorNV = vk.vkCmdSetExclusiveScissorNV;
pub const cmdSetCheckpointNV = vk.vkCmdSetCheckpointNV;
pub const getQueueCheckpointDataNV = vk.vkGetQueueCheckpointDataNV;
pub const initializePerformanceApiINTEL = vk.vkInitializePerformanceApiINTEL;
pub const uninitializePerformanceApiINTEL = vk.vkUninitializePerformanceApiINTEL;
pub const cmdSetPerformanceMarkerINTEL = vk.vkCmdSetPerformanceMarkerINTEL;
pub const cmdSetPerformanceStreamMarkerINTEL = vk.vkCmdSetPerformanceStreamMarkerINTEL;
pub const cmdSetPerformanceOverrideINTEL = vk.vkCmdSetPerformanceOverrideINTEL;
pub const acquirePerformanceConfigurationINTEL = vk.vkAcquirePerformanceConfigurationINTEL;
pub const releasePerformanceConfigurationINTEL = vk.vkReleasePerformanceConfigurationINTEL;
pub const queueSetPerformanceConfigurationINTEL = vk.vkQueueSetPerformanceConfigurationINTEL;
pub const getPerformanceParameterINTEL = vk.vkGetPerformanceParameterINTEL;
pub const setLocalDimmingAMD = vk.vkSetLocalDimmingAMD;
pub const getBufferDeviceAddressEXT = vk.vkGetBufferDeviceAddressEXT;
pub const getPhysicalDeviceToolPropertiesEXT = vk.vkGetPhysicalDeviceToolPropertiesEXT;
pub const getPhysicalDeviceCooperativeMatrixPropertiesNV = vk.vkGetPhysicalDeviceCooperativeMatrixPropertiesNV;
pub const getPhysicalDeviceSupportedFramebufferMixedSamplesCombinationsNV = vk.vkGetPhysicalDeviceSupportedFramebufferMixedSamplesCombinationsNV;
pub const createHeadlessSurfaceEXT = vk.vkCreateHeadlessSurfaceEXT;
pub const cmdSetLineStippleEXT = vk.vkCmdSetLineStippleEXT;
pub const resetQueryPoolEXT = vk.vkResetQueryPoolEXT;
pub const cmdSetCullModeEXT = vk.vkCmdSetCullModeEXT;
pub const cmdSetFrontFaceEXT = vk.vkCmdSetFrontFaceEXT;
pub const cmdSetPrimitiveTopologyEXT = vk.vkCmdSetPrimitiveTopologyEXT;
pub const cmdSetViewportWithCountEXT = vk.vkCmdSetViewportWithCountEXT;
pub const cmdSetScissorWithCountEXT = vk.vkCmdSetScissorWithCountEXT;
pub const cmdBindVertexBuffers2EXT = vk.vkCmdBindVertexBuffers2EXT;
pub const cmdSetDepthTestEnableEXT = vk.vkCmdSetDepthTestEnableEXT;
pub const cmdSetDepthWriteEnableEXT = vk.vkCmdSetDepthWriteEnableEXT;
pub const cmdSetDepthCompareOpEXT = vk.vkCmdSetDepthCompareOpEXT;
pub const cmdSetDepthBoundsTestEnableEXT = vk.vkCmdSetDepthBoundsTestEnableEXT;
pub const cmdSetStencilTestEnableEXT = vk.vkCmdSetStencilTestEnableEXT;
pub const cmdSetStencilOpEXT = vk.vkCmdSetStencilOpEXT;
pub const getGeneratedCommandsMemoryRequirementsNV = vk.vkGetGeneratedCommandsMemoryRequirementsNV;
pub const cmdPreprocessGeneratedCommandsNV = vk.vkCmdPreprocessGeneratedCommandsNV;
pub const cmdExecuteGeneratedCommandsNV = vk.vkCmdExecuteGeneratedCommandsNV;
pub const cmdBindPipelineShaderGroupNV = vk.vkCmdBindPipelineShaderGroupNV;
pub const createIndirectCommandsLayoutNV = vk.vkCreateIndirectCommandsLayoutNV;
pub const destroyIndirectCommandsLayoutNV = vk.vkDestroyIndirectCommandsLayoutNV;
pub const createPrivateDataSlotEXT = vk.vkCreatePrivateDataSlotEXT;
pub const destroyPrivateDataSlotEXT = vk.vkDestroyPrivateDataSlotEXT;
pub const setPrivateDataEXT = vk.vkSetPrivateDataEXT;
pub const getPrivateDataEXT = vk.vkGetPrivateDataEXT;
pub const cmdSetFragmentShadingRateEnumNV = vk.vkCmdSetFragmentShadingRateEnumNV; | src/lib/vulkan-l1.zig |
const std = @import("std");
/// Header of a Relic Chunky file
/// This is empty and only used to verify that the file is supported
pub const ChunkyHeader = struct {
const signature = "Relic Chunky\r\n\u{001A}\x00";
pub fn decode(reader: anytype) !ChunkyHeader {
var header: ChunkyHeader = undefined;
var magic: [signature.len]u8 = undefined;
_ = try reader.readAll(&magic);
if (!std.mem.eql(u8, &magic, signature))
return error.InvalidHeader;
var version = try reader.readIntLittle(u32);
var platform = try reader.readIntLittle(u32);
if (version != 4 or platform != 1)
return error.UnsupportedVersion;
return header;
}
};
// TODO: Any benefit to even caring about this?
// const FourCC = enum(u32) {
// _,
// pub fn isByteValid(b: u8) bool {
// return b >= ' ' and b <= '~';
// }
// /// Returns the start index of the encoded FourCC sequence (buf[self.toString()..])
// /// Returns an `error.Invalid`
// pub fn toString(self: FourCC, buf: *[4]u8) error{InvalidArgs}!u3 {
// std.mem.writeIntBig(u32, buf, @enumToInt(self));
// var index: u3 = 0;
// for (buf) |b| {
// if (b != 0 and !isByteValid(b))
// return error.InvalidArgs
// else if (b != 0)
// index += 1;
// }
// return 4 - index;
// }
// pub fn fromString(string: []const u8) error{InvalidArgs}!FourCC {
// if (string.len > 4)
// return error.InvalidArgs;
// if (string[0] == ' ') return error.InvalidArgs;
// for (string) |b|
// if (!isByteValid(b))
// return error.InvalidArgs;
// if (string.len == 4)
// return @intToEnum(FourCC, std.mem.readIntSliceBig(u32, string));
// var s = std.mem.zeroes([4]u8);
// std.mem.copy(u8, s[4 - string.len ..], string);
// return @intToEnum(FourCC, std.mem.readIntBig(u32, &s));
// }
// pub fn format(value: FourCC, comptime fmt: []const u8, options: std.fmt.FormatOptions, writer: anytype) !void {
// _ = options;
// if (fmt.len >= 1 and fmt[0] == 'd')
// try writer.print("{d}", .{@enumToInt(value)})
// else {
// var buf: [4]u8 = undefined;
// try writer.print("FourCC({s} / {d})", .{ buf[(value.toString(&buf) catch unreachable)..], @enumToInt(value) });
// }
// }
// };
/// Header of a Chunky chunk
pub const ChunkHeader = struct {
kind: [4]u8,
id: [4]u8,
version: u32,
size: u32,
name: []u8,
pub fn decode(allocator: std.mem.Allocator, reader: anytype) !ChunkHeader {
var header: ChunkHeader = undefined;
_ = try reader.readAll(&header.kind);
_ = try reader.readAll(&header.id);
header.version = try reader.readIntLittle(u32);
header.size = try reader.readIntLittle(u32);
header.name = try allocator.alloc(u8, try reader.readIntLittle(u32));
_ = try reader.readAll(header.name);
return header;
}
pub fn deinit(self: *ChunkHeader, allocator: std.mem.Allocator) void {
allocator.free(self.name);
self.* = undefined;
}
pub fn format(value: ChunkHeader, comptime fmt: []const u8, options: std.fmt.FormatOptions, writer: anytype) !void {
_ = options;
_ = fmt;
_ = options;
try writer.print("{s} chunk '{s}' (name: '{s}', version: {d}, size: {d})", .{ value.kind, value.id, value.name, value.version, value.size });
}
};
const testmod = @embedFile("../samples/testmod.bin");
test {
const allocator = std.testing.allocator;
var reader = std.io.fixedBufferStream(testmod).reader();
_ = try ChunkyHeader.decode(reader);
while (true) {
var header = ChunkHeader.decode(allocator, reader) catch break;
defer header.deinit(allocator);
if (!std.mem.eql(u8, &header.kind, "DATA") and !std.mem.eql(u8, &header.kind, "FOLD")) break;
reader.context.seekBy(header.size) catch break;
}
} | lib/chunky.zig |
const std = @import("std");
const Allocator = std.mem.Allocator;
const print = std.debug.print;
const data = @embedFile("../inputs/day22.txt");
pub fn main() anyerror!void {
var gpa_impl = std.heap.GeneralPurposeAllocator(.{}){};
defer _ = gpa_impl.deinit();
const gpa = gpa_impl.allocator();
return main_with_allocator(gpa);
}
pub fn main_with_allocator(allocator: Allocator) anyerror!void {
const steps = try parse(allocator, data);
defer allocator.free(steps);
const cuboids = try solve(allocator, steps);
defer cuboids.deinit();
print("Part 1: {d}\n", .{try part1(allocator, cuboids)});
print("Part 2: {d}\n", .{part2(cuboids)});
}
const Pos = struct {
x: isize,
y: isize,
z: isize,
};
const Cuboid = struct {
const Self = @This();
start: Pos,
end: Pos,
fn inside_x(self: Self, p: Pos) bool {
return self.start.x <= p.x and p.x <= self.end.x;
}
fn inside_y(self: Self, p: Pos) bool {
return self.start.y <= p.y and p.y <= self.end.y;
}
fn inside_z(self: Self, p: Pos) bool {
return self.start.z <= p.z and p.z <= self.end.z;
}
fn intersect(self: Self, other: Self) ?Self {
const start_x = std.math.max(self.start.x, other.start.x);
const end_x = std.math.min(self.end.x, other.end.x);
const start_y = std.math.max(self.start.y, other.start.y);
const end_y = std.math.min(self.end.y, other.end.y);
const start_z = std.math.max(self.start.z, other.start.z);
const end_z = std.math.min(self.end.z, other.end.z);
if (start_x > end_x) return null;
if (start_y > end_y) return null;
if (start_z > end_z) return null;
return Self{
.start = Pos{
.x = start_x,
.y = start_y,
.z = start_z,
},
.end = Pos{
.x = end_x,
.y = end_y,
.z = end_z,
},
};
}
fn subtract(self: Self, other: Self, out: *std.ArrayList(Cuboid)) !void {
var overlap_x = other.inside_x(self.start) or other.inside_x(self.end) or self.inside_x(other.start) or self.inside_x(other.end);
var overlap_y = other.inside_y(self.start) or other.inside_y(self.end) or self.inside_y(other.start) or self.inside_y(other.end);
var overlap_z = other.inside_z(self.start) or other.inside_z(self.end) or self.inside_z(other.start) or self.inside_z(other.end);
// fast path
if (!(overlap_x and overlap_y and overlap_z)) {
try out.append(self);
return;
}
// Intersect on x
var center_start_x = self.start.x;
var center_end_x = self.end.x;
if (self.inside_x(other.start)) {
center_start_x = other.start.x;
if (self.start.x != other.start.x) {
try out.append(Cuboid{
.start = self.start,
.end = Pos{
.x = other.start.x - 1,
.y = self.end.y,
.z = self.end.z,
},
});
}
}
if (self.inside_x(other.end)) {
center_end_x = other.end.x;
if (self.end.x != other.end.x) {
try out.append(Cuboid{
.start = Pos{
.x = other.end.x + 1,
.y = self.start.y,
.z = self.start.z,
},
.end = self.end,
});
}
}
// Intersect on y
var center_start_y = self.start.y;
var center_end_y = self.end.y;
if (self.inside_y(other.start)) {
center_start_y = other.start.y;
if (self.start.y != other.start.y) {
try out.append(Cuboid{
.start = Pos{
.x = center_start_x,
.y = self.start.y,
.z = self.start.z,
},
.end = Pos{
.x = center_end_x,
.y = other.start.y - 1,
.z = self.end.z,
},
});
}
}
if (self.inside_y(other.end)) {
center_end_y = other.end.y;
if (self.end.y != other.end.y) {
try out.append(Cuboid{
.start = Pos{
.x = center_start_x,
.y = other.end.y + 1,
.z = self.start.z,
},
.end = Pos{
.x = center_end_x,
.y = self.end.y,
.z = self.end.z,
},
});
}
}
// Intersect on z
var center_start_z = self.start.z;
var center_end_z = self.end.z;
if (self.inside_z(other.start)) {
center_start_z = other.start.z;
if (self.start.z != other.start.z) {
try out.append(Cuboid{
.start = Pos{
.x = center_start_x,
.y = center_start_y,
.z = self.start.z,
},
.end = Pos{
.x = center_end_x,
.y = center_end_y,
.z = other.start.z - 1,
},
});
}
}
if (self.inside_z(other.end)) {
center_end_z = other.end.z;
if (self.end.z != other.end.z) {
try out.append(Cuboid{
.start = Pos{
.x = center_start_x,
.y = center_start_y,
.z = other.end.z + 1,
},
.end = Pos{
.x = center_end_x,
.y = center_end_y,
.z = self.end.z,
},
});
}
}
}
fn count(self: Self) usize {
const dx = @intCast(usize, 1 + self.end.x - self.start.x);
const dy = @intCast(usize, 1 + self.end.y - self.start.y);
const dz = @intCast(usize, 1 + self.end.z - self.start.z);
return dx * dy * dz;
}
};
const Step = struct {
const Self = @This();
turn_on: bool,
cuboid: Cuboid,
fn parse(input: []const u8) !Self {
var it = std.mem.split(u8, input, " ");
const turn_on_str = it.next().?;
const turn_on =
if (std.mem.eql(u8, turn_on_str, "on")) true else if (std.mem.eql(u8, turn_on_str, "off")) false else unreachable;
const cuboid_str = it.next().?;
var it_dim = std.mem.split(u8, cuboid_str, ",");
var it_x = std.mem.split(u8, std.mem.trimLeft(u8, it_dim.next().?, "x="), "..");
var it_y = std.mem.split(u8, std.mem.trimLeft(u8, it_dim.next().?, "y="), "..");
var it_z = std.mem.split(u8, std.mem.trimLeft(u8, it_dim.next().?, "z="), "..");
const start = Pos{
.x = try std.fmt.parseInt(isize, it_x.next().?, 10),
.y = try std.fmt.parseInt(isize, it_y.next().?, 10),
.z = try std.fmt.parseInt(isize, it_z.next().?, 10),
};
const end = Pos{
.x = try std.fmt.parseInt(isize, it_x.next().?, 10),
.y = try std.fmt.parseInt(isize, it_y.next().?, 10),
.z = try std.fmt.parseInt(isize, it_z.next().?, 10),
};
return Self{
.turn_on = turn_on,
.cuboid = Cuboid{
.start = start,
.end = end,
},
};
}
};
const Cuboids = struct {
const Self = @This();
// invariant: No overlap in the cuboids
cuboids: std.ArrayList(Cuboid),
fn deinit(self: Self) void {
self.cuboids.deinit();
}
fn init(allocator: Allocator) Self {
return Self{
.cuboids = std.ArrayList(Cuboid).init(allocator),
};
}
fn apply_step(self: *Self, step: Step) !void {
const allocator = self.cuboids.allocator;
var new_cuboids = try std.ArrayList(Cuboid).initCapacity(allocator, self.cuboids.items.len);
defer new_cuboids.deinit();
for (self.cuboids.items) |*cuboid| {
try cuboid.subtract(step.cuboid, &new_cuboids);
}
if (step.turn_on) {
try new_cuboids.append(step.cuboid);
}
std.mem.swap(std.ArrayList(Cuboid), &self.cuboids, &new_cuboids);
}
fn count(self: Self) usize {
var out: usize = 0;
for (self.cuboids.items) |cuboid| {
out += cuboid.count();
}
return out;
}
};
fn parse(allocator: Allocator, input: []const u8) ![]Step {
var steps = std.ArrayList(Step).init(allocator);
var lines = std.mem.tokenize(u8, input, "\n");
while (lines.next()) |line| {
try steps.append(try Step.parse(line));
}
return steps.toOwnedSlice();
}
fn solve(allocator: Allocator, steps: []const Step) !Cuboids {
var cuboids = Cuboids.init(allocator);
errdefer cuboids.deinit();
for (steps) |step| {
try cuboids.apply_step(step);
}
return cuboids;
}
fn part1(allocator: Allocator, cuboids: Cuboids) !usize {
const limit = Cuboid{
.start = Pos{
.x = -50,
.y = -50,
.z = -50,
},
.end = Pos{
.x = 50,
.y = 50,
.z = 50,
},
};
var limited = Cuboids.init(allocator);
defer limited.deinit();
for (cuboids.cuboids.items) |cuboid| {
if (cuboid.intersect(limit)) |intersection| {
try limited.cuboids.append(intersection);
}
}
return limited.count();
}
fn part2(cuboids: Cuboids) usize {
return cuboids.count();
}
test "cuboid subtract (full)" {
const a = Cuboid{
.start = Pos{
.x = 0,
.y = 0,
.z = 0,
},
.end = Pos{
.x = 10,
.y = 10,
.z = 10,
},
};
const b = Cuboid{
.start = Pos{
.x = 3,
.y = 3,
.z = 3,
},
.end = Pos{
.x = 6,
.y = 6,
.z = 6,
},
};
const allocator = std.testing.allocator;
var out = try a.subtract(b, allocator);
defer allocator.free(out);
const expected = [_]Cuboid{
Cuboid{
.start = Pos{
.x = 0,
.y = 0,
.z = 0,
},
.end = Pos{
.x = 2,
.y = 10,
.z = 10,
},
},
Cuboid{
.start = Pos{
.x = 7,
.y = 0,
.z = 0,
},
.end = Pos{
.x = 10,
.y = 10,
.z = 10,
},
},
Cuboid{
.start = Pos{
.x = 3,
.y = 0,
.z = 0,
},
.end = Pos{
.x = 6,
.y = 2,
.z = 10,
},
},
Cuboid{
.start = Pos{
.x = 3,
.y = 7,
.z = 0,
},
.end = Pos{
.x = 6,
.y = 10,
.z = 10,
},
},
Cuboid{
.start = Pos{
.x = 3,
.y = 3,
.z = 0,
},
.end = Pos{
.x = 6,
.y = 6,
.z = 2,
},
},
Cuboid{
.start = Pos{
.x = 3,
.y = 3,
.z = 7,
},
.end = Pos{
.x = 6,
.y = 6,
.z = 10,
},
},
};
try std.testing.expectEqualSlices(Cuboid, &expected, out);
}
test "cuboid subtract (gone)" {
const a = Cuboid{
.start = Pos{
.x = 0,
.y = 0,
.z = 0,
},
.end = Pos{
.x = 10,
.y = 10,
.z = 10,
},
};
const b = Cuboid{
.start = Pos{
.x = -5,
.y = -5,
.z = -5,
},
.end = Pos{
.x = 15,
.y = 15,
.z = 15,
},
};
const allocator = std.testing.allocator;
var out = try a.subtract(b, allocator);
defer allocator.free(out);
const expected = [_]Cuboid{};
try std.testing.expectEqualSlices(Cuboid, &expected, out);
}
test "cuboid subtract (none)" {
const a = Cuboid{
.start = Pos{
.x = 0,
.y = 0,
.z = 0,
},
.end = Pos{
.x = 10,
.y = 10,
.z = 10,
},
};
const b = Cuboid{
.start = Pos{
.x = -5,
.y = -5,
.z = -5,
},
.end = Pos{
.x = -2,
.y = -2,
.z = -2,
},
};
const allocator = std.testing.allocator;
var out = try a.subtract(b, allocator);
defer allocator.free(out);
const expected = [_]Cuboid{
Cuboid{
.start = Pos{
.x = 0,
.y = 0,
.z = 0,
},
.end = Pos{
.x = 10,
.y = 10,
.z = 10,
},
},
};
try std.testing.expectEqualSlices(Cuboid, &expected, out);
}
test "cuboid subtract (none / 1-dim overlap)" {
const a = Cuboid{
.start = Pos{
.x = 0,
.y = 0,
.z = 0,
},
.end = Pos{
.x = 10,
.y = 10,
.z = 10,
},
};
const b = Cuboid{
.start = Pos{
.x = 3,
.y = -5,
.z = -5,
},
.end = Pos{
.x = 6,
.y = -2,
.z = -2,
},
};
const allocator = std.testing.allocator;
var out = try a.subtract(b, allocator);
defer allocator.free(out);
const expected = [_]Cuboid{a};
try std.testing.expectEqualSlices(Cuboid, &expected, out);
}
test "cuboid subtract (partial 1-dim)" {
const a = Cuboid{
.start = Pos{
.x = 0,
.y = 0,
.z = 0,
},
.end = Pos{
.x = 10,
.y = 10,
.z = 10,
},
};
const b = Cuboid{
.start = Pos{
.x = -2,
.y = 0,
.z = 0,
},
.end = Pos{
.x = 2,
.y = 20,
.z = 20,
},
};
const allocator = std.testing.allocator;
var out = try a.subtract(b, allocator);
defer allocator.free(out);
const expected = [_]Cuboid{
Cuboid{
.start = Pos{
.x = 3,
.y = 0,
.z = 0,
},
.end = Pos{
.x = 10,
.y = 10,
.z = 10,
},
},
};
try std.testing.expectEqualSlices(Cuboid, &expected, out);
}
test "cuboid subtract (partial 2-dim)" {
const a = Cuboid{
.start = Pos{
.x = 0,
.y = 0,
.z = 0,
},
.end = Pos{
.x = 10,
.y = 10,
.z = 10,
},
};
const b = Cuboid{
.start = Pos{
.x = 8,
.y = 8,
.z = 0,
},
.end = Pos{
.x = 20,
.y = 20,
.z = 20,
},
};
const allocator = std.testing.allocator;
var out = try a.subtract(b, allocator);
defer allocator.free(out);
const expected = [_]Cuboid{
Cuboid{
.start = Pos{
.x = 0,
.y = 0,
.z = 0,
},
.end = Pos{
.x = 7,
.y = 10,
.z = 10,
},
},
Cuboid{
.start = Pos{
.x = 8,
.y = 0,
.z = 0,
},
.end = Pos{
.x = 10,
.y = 7,
.z = 10,
},
},
};
try std.testing.expectEqualSlices(Cuboid, &expected, out);
}
test "cuboid subtract (partial 3-dim)" {
const a = Cuboid{
.start = Pos{
.x = 0,
.y = 0,
.z = 0,
},
.end = Pos{
.x = 10,
.y = 10,
.z = 10,
},
};
const b = Cuboid{
.start = Pos{
.x = 8,
.y = 8,
.z = 8,
},
.end = Pos{
.x = 20,
.y = 20,
.z = 20,
},
};
const allocator = std.testing.allocator;
var out = try a.subtract(b, allocator);
defer allocator.free(out);
const expected = [_]Cuboid{
Cuboid{
.start = Pos{
.x = 0,
.y = 0,
.z = 0,
},
.end = Pos{
.x = 7,
.y = 10,
.z = 10,
},
},
Cuboid{
.start = Pos{
.x = 8,
.y = 0,
.z = 0,
},
.end = Pos{
.x = 10,
.y = 7,
.z = 10,
},
},
Cuboid{
.start = Pos{
.x = 8,
.y = 8,
.z = 0,
},
.end = Pos{
.x = 10,
.y = 10,
.z = 7,
},
},
};
try std.testing.expectEqualSlices(Cuboid, &expected, out);
}
test "cuboid simple" {
const input =
\\on x=10..12,y=10..12,z=10..12
\\on x=11..13,y=11..13,z=11..13
\\off x=9..11,y=9..11,z=9..11
\\on x=10..10,y=10..10,z=10..10
;
const allocator = std.testing.allocator;
const steps = try parse(allocator, input);
defer allocator.free(steps);
try std.testing.expectEqual(@as(usize, 39), try part1(allocator, steps));
}
test "cuboid" {
const input =
\\on x=-20..26,y=-36..17,z=-47..7
\\on x=-20..33,y=-21..23,z=-26..28
\\on x=-22..28,y=-29..23,z=-38..16
\\on x=-46..7,y=-6..46,z=-50..-1
\\on x=-49..1,y=-3..46,z=-24..28
\\on x=2..47,y=-22..22,z=-23..27
\\on x=-27..23,y=-28..26,z=-21..29
\\on x=-39..5,y=-6..47,z=-3..44
\\on x=-30..21,y=-8..43,z=-13..34
\\on x=-22..26,y=-27..20,z=-29..19
\\off x=-48..-32,y=26..41,z=-47..-37
\\on x=-12..35,y=6..50,z=-50..-2
\\off x=-48..-32,y=-32..-16,z=-15..-5
\\on x=-18..26,y=-33..15,z=-7..46
\\off x=-40..-22,y=-38..-28,z=23..41
\\on x=-16..35,y=-41..10,z=-47..6
\\off x=-32..-23,y=11..30,z=-14..3
\\on x=-49..-5,y=-3..45,z=-29..18
\\off x=18..30,y=-20..-8,z=-3..13
\\on x=-41..9,y=-7..43,z=-33..15
\\on x=-54112..-39298,y=-85059..-49293,z=-27449..7877
\\on x=967..23432,y=45373..81175,z=27513..53682
;
const allocator = std.testing.allocator;
const steps = try parse(allocator, input);
defer allocator.free(steps);
try std.testing.expectEqual(@as(usize, 590784), try part1(allocator, steps));
} | src/day22.zig |
const std = @import("std");
const expectEqual = @import("testutil.zig").expectEqual;
export fn abort() noreturn {
@panic("abort() from libc was called");
}
export fn abs(n: c_int) c_int {
if (n < 0) {
return -n;
} else {
return n;
}
}
test "abs" {
try expectEqual(10, abs(10));
try expectEqual(10, abs(-10));
try expectEqual(0, abs(0));
}
export fn strtod(str: [*:0]const u8, str_end: ?**const u8) f64 {
var start: usize = 0;
var end: usize = 0;
while (str[start] != 0 and isWhitespace(str[start])) : (start += 1) {}
end = start;
while (str[end] != 0) : (end += 1) {}
const str_float_part = str[start..end];
const result = std.fmt.parseHexFloat(f64, str_float_part) catch std.fmt.parseFloat(f64, str_float_part) catch {
if (str_end) |non_null| {
non_null.* = &str[0];
}
return 0.0;
};
if (str_end) |non_null| {
non_null.* = &str[end];
}
return result;
}
fn isWhitespace(c: u8) bool {
return c == ' ' or c == '\x0c' or c == '\n' or c == '\r' or c == '\x09' or c == '\x0b';
}
test "strtod" {
var end: *u8 = undefined;
try expectEqual(0.0, strtod("0.0", &end));
try expectEqual(0, end.*);
try expectEqual(0.2775, strtod("0.2775", &end));
try expectEqual(0, end.*);
try expectEqual(12424.0, strtod("12424.0", &end));
try expectEqual(0, end.*);
try expectEqual(1394.12998, strtod("1394.12998", &end));
try expectEqual(0, end.*);
try expectEqual(-1394.12998, strtod("-1394.12998", &end));
try expectEqual(0, end.*);
// Lua doesn't try to convert strings with trailing parts, so we don't need
// to support it.
// try expectEqual(1394.12998, strtod("1394.12998def", &end));
// try expectEqual('d', end.*);
try expectEqual(-1394129.98, strtod("-1394.12998e3", &end));
try expectEqual(0, end.*);
try expectEqual(-1394129.98, strtod("-1394.12998E3", &end));
try expectEqual(0, end.*);
try expectEqual(-1394.12998, strtod(" \n\r -1394.12998", &end));
try expectEqual(0, end.*);
try expectEqual(-0x71.3, strtod("-0x71.3", &end));
try expectEqual(0, end.*);
const testString = "not a number";
try expectEqual(0.0, strtod(testString, &end));
try expectEqual(testString[0], end.*);
} | src/libc/stdlib.zig |
const std = @import("std");
const main = @import("../main.zig");
const string = []const u8;
const NodeIndex = std.zig.Ast.Node.Index;
pub fn work(alloc: std.mem.Allocator, file_name: string, src: *main.Source, writer: std.fs.File.Writer) main.WorkError!void {
//
_ = alloc;
const ast = try src.ast();
try checkNamespace(ast, 0, writer, file_name);
}
const CheckError = std.fs.File.Writer.Error || error{};
fn checkNamespace(ast: std.zig.Ast, ns_node: NodeIndex, writer: std.fs.File.Writer, file_name: string) CheckError!void {
const tags = ast.nodes.items(.tag);
const data = ast.nodes.items(.data)[ns_node];
const childs = switch (tags[ns_node]) {
.root => ast.rootDecls(),
.block, .block_semicolon => ast.extra_data[data.lhs..data.rhs],
.container_decl, .container_decl_trailing => ast.containerDecl(ns_node).ast.members,
.container_decl_two, .container_decl_two_trailing => blk: {
var buffer: [2]NodeIndex = undefined;
const x = ast.containerDeclTwo(&buffer, ns_node);
break :blk x.ast.members;
},
else => @panic(@tagName(tags[ns_node])), // namespace
};
for (childs) |item| {
try checkNamespaceItem(ast, childs, item, writer, file_name, ns_node);
}
}
fn checkNamespaceItem(ast: std.zig.Ast, ns_childs: []const NodeIndex, node: NodeIndex, writer: std.fs.File.Writer, file_name: string, owner: NodeIndex) CheckError!void {
const tags = ast.nodes.items(.tag);
switch (tags[node]) {
.simple_var_decl => {
const x = ast.simpleVarDecl(node);
if (x.visib_token) |_| return;
try searchForNameInNamespace(ast, x.ast.mut_token + 1, ns_childs, node, writer, file_name);
},
.aligned_var_decl => {
const x = ast.alignedVarDecl(node);
if (x.visib_token) |_| return;
try searchForNameInNamespace(ast, x.ast.mut_token + 1, ns_childs, node, writer, file_name);
},
.local_var_decl => {
const x = ast.localVarDecl(node);
if (x.visib_token) |_| return;
try searchForNameInNamespace(ast, x.ast.mut_token + 1, ns_childs, node, writer, file_name);
},
.global_var_decl => {
const x = ast.globalVarDecl(node);
if (x.visib_token) |_| return;
try searchForNameInNamespace(ast, x.ast.mut_token + 1, ns_childs, node, writer, file_name);
},
// TODO https://github.com/nektro/ziglint/issues/6
.fn_decl,
.fn_proto,
.fn_proto_simple,
.fn_proto_multi,
.fn_proto_one,
=> {},
// container level tag but not a named decl we need to check, skipping
.container_field_init,
.container_field_align,
.container_field,
.test_decl,
.@"comptime",
.@"usingnamespace",
=> {},
else => {
std.log.warn("{s} has a {s} child", .{ @tagName(tags[owner]), @tagName(tags[node]) });
@panic(@tagName(tags[node])); // decl
},
}
}
fn searchForNameInNamespace(ast: std.zig.Ast, name_node: NodeIndex, ns_childs: []const NodeIndex, self: NodeIndex, writer: std.fs.File.Writer, file_name: string) CheckError!void {
const name = ast.tokenSlice(name_node);
for (ns_childs) |item| {
if (item == self) continue; // definition doesn't count as a use
if (try checkValueForName(ast, name, item, writer, file_name, self)) return;
}
const loc = ast.tokenLocation(0, name_node);
try writer.print("./{s}:{d}:{d}: unused local declaration '{s}'\n", .{ file_name, loc.line + 1, loc.column + 1, name });
}
fn checkValueForName(ast: std.zig.Ast, search_name: string, node: NodeIndex, writer: std.fs.File.Writer, file_name: string, owner: NodeIndex) CheckError!bool {
if (node == 0) return false;
const tags = ast.nodes.items(.tag);
const datas = ast.nodes.items(.data);
const main_tokens = ast.nodes.items(.main_token);
if (node >= datas.len) std.debug.panic("owner node '{s}' indexed {d} out of bounds on slice of length {d}", .{ @tagName(tags[owner]), node, datas.len });
const data = datas[node];
return switch (tags[node]) {
.root => unreachable, // handled above by skipping node 0
.string_literal,
.integer_literal,
.char_literal,
.enum_literal,
.error_set_decl,
.@"continue",
.error_value,
.unreachable_literal,
.float_literal,
.multiline_string_literal,
.asm_output,
.@"anytype",
.anyframe_literal,
=> false,
.builtin_call_two,
.builtin_call_two_comma,
.fn_decl,
.block_two,
.block_two_semicolon,
.assign,
.array_access,
.ptr_type_aligned,
.for_simple,
.call_one,
.call_one_comma,
.async_call_one,
.async_call_one_comma,
.array_cat,
.bool_or,
.bool_and,
.equal_equal,
.@"catch",
.container_field_init,
.struct_init_dot_two,
.struct_init_dot_two_comma,
.struct_init_one,
.struct_init_one_comma,
.array_init_dot_two,
.array_init_dot_two_comma,
.array_type,
.merge_error_sets,
.@"orelse",
.greater_than,
.bang_equal,
.sub,
.assign_add,
.error_union,
.mul,
.less_than,
.add,
.greater_or_equal,
.slice_open,
.shl,
.less_or_equal,
.assign_sub,
.div,
.assign_div,
.assign_mul,
.mod,
.switch_case_one,
.assign_bit_or,
.array_init_one,
.array_init_one_comma,
.array_mult,
.bit_or,
.bit_and,
.assign_add_wrap,
.bit_xor,
.shr,
.switch_range,
.container_field_align,
.assign_mod,
.assign_shl,
.assign_shl_sat,
.assign_shr,
.assign_bit_and,
.assign_bit_xor,
.assign_mul_wrap,
.assign_sub_wrap,
.assign_mul_sat,
.assign_add_sat,
.assign_sub_sat,
.mul_wrap,
.mul_sat,
.add_wrap,
.sub_wrap,
.add_sat,
.sub_sat,
.shl_sat,
=> {
if (try checkValueForName(ast, search_name, data.lhs, writer, file_name, node)) return true;
if (try checkValueForName(ast, search_name, data.rhs, writer, file_name, node)) return true;
return false;
},
.field_access,
.deref,
.unwrap_optional,
.optional_type,
.address_of,
.@"try",
.bool_not,
.@"return",
.grouped_expression,
.@"usingnamespace",
.@"comptime",
.negation,
.asm_input,
.bit_not,
.@"await",
.negation_wrap,
.asm_simple,
.@"suspend",
.@"resume",
.@"nosuspend",
=> {
return try checkValueForName(ast, search_name, data.lhs, writer, file_name, node);
},
.@"defer",
.test_decl,
.@"errdefer",
.@"break",
.anyframe_type,
=> {
return try checkValueForName(ast, search_name, data.rhs, writer, file_name, node);
},
.@"if" => try checkAstValuesForName(ast, search_name, writer, file_name, node, ast.ifFull(node), &.{
.cond_expr,
.then_expr,
.else_expr,
}),
.while_simple => try checkAstValuesForName(ast, search_name, writer, file_name, node, ast.whileSimple(node), &.{
.cond_expr,
.then_expr,
}),
.slice => try checkAstValuesForName(ast, search_name, writer, file_name, node, ast.slice(node), &.{
.sliced,
.start,
.end,
}),
.slice_sentinel => try checkAstValuesForName(ast, search_name, writer, file_name, node, ast.sliceSentinel(node), &.{
.sliced,
.start,
.end,
.sentinel,
}),
.ptr_type_sentinel => try checkAstValuesForName(ast, search_name, writer, file_name, node, ast.ptrTypeSentinel(node), &.{
.sentinel,
.child_type,
}),
.ptr_type => try checkAstValuesForName(ast, search_name, writer, file_name, node, ast.ptrType(node), &.{
.align_node,
.addrspace_node,
.sentinel,
.child_type,
}),
.ptr_type_bit_range => try checkAstValuesForName(ast, search_name, writer, file_name, node, ast.ptrTypeBitRange(node), &.{
.align_node,
.addrspace_node,
.sentinel,
.bit_range_start,
.bit_range_end,
.child_type,
}),
.while_cont => try checkAstValuesForName(ast, search_name, writer, file_name, node, ast.whileCont(node), &.{
.cond_expr,
.cont_expr,
.then_expr,
}),
.array_type_sentinel => try checkAstValuesForName(ast, search_name, writer, file_name, node, ast.arrayTypeSentinel(node), &.{
.elem_count,
.sentinel,
.elem_type,
}),
.@"for" => try checkAstValuesForName(ast, search_name, writer, file_name, node, ast.forFull(node), &.{
.cond_expr,
.then_expr,
.else_expr,
}),
.@"while" => try checkAstValuesForName(ast, search_name, writer, file_name, node, ast.whileFull(node), &.{
.cond_expr,
.cont_expr,
.then_expr,
.else_expr,
}),
.container_field => try checkAstValuesForName(ast, search_name, writer, file_name, node, ast.containerField(node), &.{
.type_expr,
.value_expr,
.align_expr,
}),
// zig fmt: off
.struct_init, .struct_init_comma => try checkAstParentOpForName(ast, search_name, writer, file_name, node, ast.structInit(node), .type_expr, .fields),
.array_init, .array_init_comma => try checkAstParentOpForName(ast, search_name, writer, file_name, node, ast.arrayInit(node), .type_expr, .elements),
.call, .call_comma => try checkAstParentOpForName(ast, search_name, writer, file_name, node, ast.callFull(node), .fn_expr, .params),
.async_call, .async_call_comma => try checkAstParentOpForName(ast, search_name, writer, file_name, node, ast.callFull(node), .fn_expr, .params),
.array_init_dot, .array_init_dot_comma => try checkAstParentOpForName(ast, search_name, writer, file_name, node, ast.arrayInitDot(node), .type_expr, .elements),
.struct_init_dot, .struct_init_dot_comma => try checkAstParentOpForName(ast, search_name, writer, file_name, node, ast.structInitDot(node), .type_expr, .fields),
.switch_case => try checkAstParentOpForName(ast, search_name, writer, file_name, node, ast.switchCase(node), .target_expr, .values),
.tagged_union, .tagged_union_trailing => try checkAstParentOpForName(ast, search_name, writer, file_name, node, ast.taggedUnion(node), .arg, .members),
.@"asm" => try checkAstParentOpForName(ast, search_name, writer, file_name, node, ast.asmFull(node), .template, .items),
.container_decl_arg, .container_decl_arg_trailing => try checkAstParentOpForName(ast, search_name, writer, file_name, node, ast.containerDeclArg(node), .arg, .members),
.tagged_union_enum_tag, .tagged_union_enum_tag_trailing => try checkAstParentOpForName(ast, search_name, writer, file_name, node, ast.taggedUnionEnumTag(node), .arg, .members),
// zig fmt: on
.simple_var_decl => {
const x = ast.simpleVarDecl(node);
const name = ast.tokenSlice(x.ast.mut_token + 1);
if (std.mem.eql(u8, search_name, name)) return true;
if (try checkValueForName(ast, search_name, x.ast.type_node, writer, file_name, node)) return true;
if (try checkValueForName(ast, search_name, x.ast.init_node, writer, file_name, node)) return true;
return false;
},
.local_var_decl => {
const x = ast.localVarDecl(node);
const name = ast.tokenSlice(x.ast.mut_token + 1);
if (std.mem.eql(u8, search_name, name)) return true;
if (try checkValueForName(ast, search_name, x.ast.type_node, writer, file_name, node)) return true;
if (try checkValueForName(ast, search_name, x.ast.init_node, writer, file_name, node)) return true;
return false;
},
.aligned_var_decl => {
const x = ast.alignedVarDecl(node);
const name = ast.tokenSlice(x.ast.mut_token + 1);
if (std.mem.eql(u8, search_name, name)) return true;
if (try checkValueForName(ast, search_name, x.ast.type_node, writer, file_name, node)) return true;
if (try checkValueForName(ast, search_name, x.ast.init_node, writer, file_name, node)) return true;
return false;
},
.global_var_decl => {
const x = ast.globalVarDecl(node);
const name = ast.tokenSlice(x.ast.mut_token + 1);
if (std.mem.eql(u8, search_name, name)) return true;
if (try checkValueForName(ast, search_name, x.ast.type_node, writer, file_name, node)) return true;
if (try checkValueForName(ast, search_name, x.ast.init_node, writer, file_name, node)) return true;
return false;
},
.identifier => {
const name = ast.tokenSlice(main_tokens[node]);
return std.mem.eql(u8, search_name, name);
},
.fn_proto_simple => {
var params: [1]NodeIndex = undefined;
const x = ast.fnProtoSimple(¶ms, node);
if (try checkValuesForName(ast, search_name, x.ast.params, writer, file_name, node)) return true;
return try checkAstValuesForName(ast, search_name, writer, file_name, node, x, &.{
.return_type,
});
},
.fn_proto_multi => {
const x = ast.fnProtoMulti(node);
if (try checkValuesForName(ast, search_name, x.ast.params, writer, file_name, node)) return true;
return try checkAstValuesForName(ast, search_name, writer, file_name, node, x, &.{
.return_type,
});
},
.fn_proto_one => {
var params: [1]NodeIndex = undefined;
const x = ast.fnProtoOne(¶ms, node);
if (try checkValuesForName(ast, search_name, x.ast.params, writer, file_name, node)) return true;
return try checkAstValuesForName(ast, search_name, writer, file_name, node, x, &.{
.return_type,
.align_expr,
.addrspace_expr,
.section_expr,
.callconv_expr,
});
},
.fn_proto => {
const x = ast.fnProto(node);
if (try checkValuesForName(ast, search_name, x.ast.params, writer, file_name, node)) return true;
return try checkAstValuesForName(ast, search_name, writer, file_name, node, x, &.{
.return_type,
.align_expr,
.addrspace_expr,
.section_expr,
.callconv_expr,
});
},
.container_decl_two, .container_decl_two_trailing => {
var buffer: [2]NodeIndex = undefined;
const x = ast.containerDeclTwo(&buffer, node);
if (try checkValuesForName(ast, search_name, x.ast.members, writer, file_name, node)) return true;
try checkNamespace(ast, node, writer, file_name);
return false;
},
.block, .block_semicolon => {
const statements = ast.extra_data[data.lhs..data.rhs];
if (try checkValuesForName(ast, search_name, statements, writer, file_name, node)) return true;
return false;
},
.if_simple => {
if (try checkValueForName(ast, search_name, data.lhs, writer, file_name, node)) return true;
if (try checkValueForName(ast, search_name, data.rhs, writer, file_name, node)) return true;
if (std.mem.eql(u8, search_name, ast.tokenSlice(main_tokens[node]))) return true;
return false;
},
.container_decl, .container_decl_trailing => {
const x = ast.containerDecl(node);
if (try checkValuesForName(ast, search_name, x.ast.members, writer, file_name, node)) return true;
try checkNamespace(ast, node, writer, file_name);
return false;
},
.@"switch", .switch_comma => {
const extra = ast.extraData(data.rhs, std.zig.Ast.Node.SubRange);
const cases = ast.extra_data[extra.start..extra.end];
if (try checkValueForName(ast, search_name, data.lhs, writer, file_name, node)) return true;
if (try checkValuesForName(ast, search_name, cases, writer, file_name, node)) return true;
return false;
},
.tagged_union_two, .tagged_union_two_trailing => {
var params: [2]NodeIndex = undefined;
const x = ast.taggedUnionTwo(¶ms, node);
return try checkAstParentOpForName(ast, search_name, writer, file_name, node, x, .arg, .members);
},
.builtin_call, .builtin_call_comma => {
const nodes = ast.extra_data[data.lhs..data.rhs];
return try checkValuesForName(ast, search_name, nodes, writer, file_name, node);
},
};
}
fn checkValuesForName(ast: std.zig.Ast, search_name: string, nodes: []const NodeIndex, writer: std.fs.File.Writer, file_name: string, owner: NodeIndex) CheckError!bool {
for (nodes) |item| {
if (try checkValueForName(ast, search_name, item, writer, file_name, owner)) return true;
}
return false;
}
fn checkAstValuesForName(ast: std.zig.Ast, search_name: string, writer: std.fs.File.Writer, file_name: string, owner: NodeIndex, inner: anytype, comptime fields: []const std.meta.FieldEnum(@TypeOf(inner.ast))) CheckError!bool {
inline for (fields) |item| {
if (try checkValueForName(ast, search_name, @field(inner.ast, @tagName(item)), writer, file_name, owner)) return true;
}
return false;
}
fn checkAstParentOpForName(ast: std.zig.Ast, search_name: string, writer: std.fs.File.Writer, file_name: string, owner: NodeIndex, inner: anytype, comptime parent: std.meta.FieldEnum(@TypeOf(inner.ast)), comptime childs: @TypeOf(parent)) CheckError!bool {
if (try checkValueForName(ast, search_name, @field(inner.ast, @tagName(parent)), writer, file_name, owner)) return true;
if (try checkValuesForName(ast, search_name, @field(inner.ast, @tagName(childs)), writer, file_name, owner)) return true;
return false;
} | src/tools/unused_decl.zig |
const std = @import("std");
const testing = std.testing;
const c = @import("c.zig").c;
const Error = @import("errors.zig").Error;
const getError = @import("errors.zig").getError;
const Image = @import("Image.zig");
const internal_debug = @import("internal_debug.zig");
const Cursor = @This();
ptr: *c.GLFWcursor,
/// Standard system cursor shapes.
///
/// These are the standard cursor shapes that can be requested from the platform (window system).
pub const Shape = enum(i32) {
/// The regular arrow cursor shape.
arrow = c.GLFW_ARROW_CURSOR,
/// The text input I-beam cursor shape.
ibeam = c.GLFW_IBEAM_CURSOR,
/// The crosshair cursor shape.
crosshair = c.GLFW_CROSSHAIR_CURSOR,
/// The pointing hand cursor shape.
///
/// NOTE: This supersedes the old `hand` enum.
pointing_hand = c.GLFW_POINTING_HAND_CURSOR,
/// The horizontal resize/move arrow shape.
///
/// The horizontal resize/move arrow shape. This is usually a horizontal double-headed arrow.
//
// NOTE: This supersedes the old `hresize` enum.
resize_ew = c.GLFW_RESIZE_EW_CURSOR,
/// The vertical resize/move arrow shape.
///
/// The vertical resize/move shape. This is usually a vertical double-headed arrow.
///
/// NOTE: This supersedes the old `vresize` enum.
resize_ns = c.GLFW_RESIZE_NS_CURSOR,
/// The top-left to bottom-right diagonal resize/move arrow shape.
///
/// The top-left to bottom-right diagonal resize/move shape. This is usually a diagonal
/// double-headed arrow.
///
/// macos: This shape is provided by a private system API and may fail CursorUnavailable in the
/// future.
///
/// x11: This shape is provided by a newer standard not supported by all cursor themes.
///
/// wayland: This shape is provided by a newer standard not supported by all cursor themes.
resize_nwse = c.GLFW_RESIZE_NWSE_CURSOR,
/// The top-right to bottom-left diagonal resize/move arrow shape.
///
/// The top-right to bottom-left diagonal resize/move shape. This is usually a diagonal
/// double-headed arrow.
///
/// macos: This shape is provided by a private system API and may fail with CursorUnavailable
/// in the future.
///
/// x11: This shape is provided by a newer standard not supported by all cursor themes.
///
/// wayland: This shape is provided by a newer standard not supported by all cursor themes.
resize_nesw = c.GLFW_RESIZE_NESW_CURSOR,
/// The omni-directional resize/move cursor shape.
///
/// The omni-directional resize cursor/move shape. This is usually either a combined horizontal
/// and vertical double-headed arrow or a grabbing hand.
resize_all = c.GLFW_RESIZE_ALL_CURSOR,
/// The operation-not-allowed shape.
///
/// The operation-not-allowed shape. This is usually a circle with a diagonal line through it.
///
/// x11: This shape is provided by a newer standard not supported by all cursor themes.
///
/// wayland: This shape is provided by a newer standard not supported by all cursor themes.
not_allowed = c.GLFW_NOT_ALLOWED_CURSOR,
};
/// Creates a custom cursor.
///
/// Creates a new custom cursor image that can be set for a window with glfw.Cursor.set. The cursor
/// can be destroyed with glfwCursor.destroy. Any remaining cursors are destroyed by glfw.terminate.
///
/// The pixels are 32-bit, little-endian, non-premultiplied RGBA, i.e. eight bits per channel with
/// the red channel first. They are arranged canonically as packed sequential rows, starting from
/// the top-left corner.
///
/// The cursor hotspot is specified in pixels, relative to the upper-left corner of the cursor
/// image. Like all other coordinate systems in GLFW, the X-axis points to the right and the Y-axis
/// points down.
///
/// @param[in] image The desired cursor image.
/// @param[in] xhot The desired x-coordinate, in pixels, of the cursor hotspot.
/// @param[in] yhot The desired y-coordinate, in pixels, of the cursor hotspot.
/// @return The handle of the created cursor.
///
/// @pointer_lifetime The specified image data is copied before this function returns.
///
/// @thread_safety This function must only be called from the main thread.
///
/// see also: cursor_object, glfw.Cursor.destroy, glfw.Cursor.createStandard
pub inline fn create(image: Image, xhot: i32, yhot: i32) error{ PlatformError, InvalidValue }!Cursor {
internal_debug.assertInitialized();
const img = image.toC();
if (c.glfwCreateCursor(&img, @intCast(c_int, xhot), @intCast(c_int, yhot))) |cursor| return Cursor{ .ptr = cursor };
getError() catch |err| return switch (err) {
Error.NotInitialized => unreachable,
Error.PlatformError => |e| e,
Error.InvalidValue => |e| e,
else => unreachable,
};
// `glfwCreateCursor` returns `null` only for errors
unreachable;
}
/// Creates a cursor with a standard shape.
///
/// Returns a cursor with a standard shape, that can be set for a window with glfw.Window.setCursor.
/// The images for these cursors come from the system cursor theme and their exact appearance will
/// vary between platforms.
///
/// Most of these shapes are guaranteed to exist on every supported platform but a few may not be
/// present. See the table below for details.
///
/// | Cursor shape | Windows | macOS | X11 | Wayland |
/// |------------------|---------|-----------------|-------------------|-------------------|
/// | `.arrow` | Yes | Yes | Yes | Yes |
/// | `.ibeam` | Yes | Yes | Yes | Yes |
/// | `.crosshair` | Yes | Yes | Yes | Yes |
/// | `.pointing_hand` | Yes | Yes | Yes | Yes |
/// | `.resize_ew` | Yes | Yes | Yes | Yes |
/// | `.resize_ns` | Yes | Yes | Yes | Yes |
/// | `.resize_nwse` | Yes | Yes<sup>1</sup> | Maybe<sup>2</sup> | Maybe<sup>2</sup> |
/// | `.resize_nesw` | Yes | Yes<sup>1</sup> | Maybe<sup>2</sup> | Maybe<sup>2</sup> |
/// | `.resize_all` | Yes | Yes | Yes | Yes |
/// | `.not_allowed` | Yes | Yes | Maybe<sup>2</sup> | Maybe<sup>2</sup> |
///
/// 1. This uses a private system API and may fail in the future.
/// 2. This uses a newer standard that not all cursor themes support.
///
/// If the requested shape is not available, this function emits a CursorUnavailable error
///
/// thread_safety: This function must only be called from the main thread.
///
/// see also: cursor_object, glfwCreateCursor
pub inline fn createStandard(shape: Shape) error{ PlatformError, CursorUnavailable }!Cursor {
internal_debug.assertInitialized();
if (c.glfwCreateStandardCursor(@intCast(c_int, @enumToInt(shape)))) |cursor| return Cursor{ .ptr = cursor };
getError() catch |err| return switch (err) {
Error.NotInitialized => unreachable,
Error.InvalidEnum => unreachable,
Error.CursorUnavailable => |e| e,
Error.PlatformError => |e| e,
else => unreachable,
};
// `glfwCreateStandardCursor` returns `null` only for errors
unreachable;
}
/// Destroys a cursor.
///
/// This function destroys a cursor previously created with glfw.Cursor.create. Any remaining
/// cursors will be destroyed by glfw.terminate.
///
/// If the specified cursor is current for any window, that window will be reverted to the default
/// cursor. This does not affect the cursor mode.
///
/// Possible errors include glfw.Error.NotInitialized and glfw.Error.PlatformError.
///
/// @reentrancy This function must not be called from a callback.
///
/// @thread_safety This function must only be called from the main thread.
///
/// see also: cursor_object, glfw.createCursor
pub inline fn destroy(self: Cursor) void {
internal_debug.assertInitialized();
c.glfwDestroyCursor(self.ptr);
getError() catch |err| return switch (err) {
Error.PlatformError => std.log.err("mach/glfw: unable to destroy Cursor: {}\n", .{err}),
else => unreachable,
};
}
test "create" {
const allocator = testing.allocator;
const glfw = @import("main.zig");
try glfw.init(.{});
defer glfw.terminate();
const image = try Image.init(allocator, 32, 32, 32 * 32 * 4);
defer image.deinit(allocator);
const cursor = glfw.Cursor.create(image, 0, 0) catch |err| {
std.debug.print("failed to create cursor, custom cursors not supported? error={}\n", .{err});
return;
};
cursor.destroy();
}
test "createStandard" {
const glfw = @import("main.zig");
try glfw.init(.{});
defer glfw.terminate();
const cursor = glfw.Cursor.createStandard(.ibeam) catch |err| {
std.debug.print("failed to create cursor, custom cursors not supported? error={}\n", .{err});
return;
};
cursor.destroy();
} | glfw/src/Cursor.zig |
const cmp = @import("cmp.zig");
const testing = @import("std").testing;
fn test__ucmpdi2(a: u64, b: u64, expected: i32) !void {
var result = cmp.__ucmpdi2(a, b);
try testing.expectEqual(expected, result);
}
test "ucmpdi2" {
// minInt == 0
// maxInt == 18446744073709551615
// minInt/2 == 0
// maxInt/2 == 9223372036854775807
// 1. equality minInt, minInt/2, 0, maxInt/2, maxInt
try test__ucmpdi2(0, 0, 1);
try test__ucmpdi2(1, 1, 1);
try test__ucmpdi2(9223372036854775807, 9223372036854775807, 1);
try test__ucmpdi2(18446744073709551614, 18446744073709551614, 1);
try test__ucmpdi2(18446744073709551615, 18446744073709551615, 1);
// 2. cmp minInt, {minInt + 1, maxInt/2, maxInt-1, maxInt}
try test__ucmpdi2(0, 1, 0);
try test__ucmpdi2(0, 9223372036854775807, 0);
try test__ucmpdi2(0, 18446744073709551614, 0);
try test__ucmpdi2(0, 18446744073709551615, 0);
// 3. cmp minInt+1, {minInt, maxInt/2, maxInt-1, maxInt}
try test__ucmpdi2(1, 0, 2);
try test__ucmpdi2(1, 9223372036854775807, 0);
try test__ucmpdi2(1, 18446744073709551614, 0);
try test__ucmpdi2(1, 18446744073709551615, 0);
// 4. cmp minInt/2, {}
// 5. cmp -1, {}
// 6. cmp 0, {}
// 7. cmp 1, {}
// 8. cmp maxInt/2, {minInt, minInt+1, maxInt-1, maxInt}
try test__ucmpdi2(9223372036854775807, 0, 2);
try test__ucmpdi2(9223372036854775807, 1, 2);
try test__ucmpdi2(9223372036854775807, 18446744073709551614, 0);
try test__ucmpdi2(9223372036854775807, 18446744073709551615, 0);
// 9. cmp maxInt-1, {minInt, minInt + 1, maxInt/2, maxInt}
try test__ucmpdi2(18446744073709551614, 0, 2);
try test__ucmpdi2(18446744073709551614, 1, 2);
try test__ucmpdi2(18446744073709551614, 9223372036854775807, 2);
try test__ucmpdi2(18446744073709551614, 18446744073709551615, 0);
// 10.cmp maxInt, {minInt, 1, maxInt/2, maxInt-1}
try test__ucmpdi2(18446744073709551615, 0, 2);
try test__ucmpdi2(18446744073709551615, 1, 2);
try test__ucmpdi2(18446744073709551615, 9223372036854775807, 2);
try test__ucmpdi2(18446744073709551615, 18446744073709551614, 2);
} | lib/std/special/compiler_rt/ucmpdi2_test.zig |
const builtin = @import("builtin");
const std = @import("std");
const expect = std.testing.expect;
const expectEqual = std.testing.expectEqual;
const expectEqualSlices = std.testing.expectEqualSlices;
const maxInt = std.math.maxInt;
const minInt = std.math.minInt;
const mem = std.mem;
test "assignment operators" {
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
var i: u32 = 0;
i += 5;
try expect(i == 5);
i -= 2;
try expect(i == 3);
i *= 20;
try expect(i == 60);
i /= 3;
try expect(i == 20);
i %= 11;
try expect(i == 9);
i <<= 1;
try expect(i == 18);
i >>= 2;
try expect(i == 4);
i = 6;
i &= 5;
try expect(i == 4);
i ^= 6;
try expect(i == 2);
i = 6;
i |= 3;
try expect(i == 7);
}
test "three expr in a row" {
try testThreeExprInARow(false, true);
comptime try testThreeExprInARow(false, true);
}
fn testThreeExprInARow(f: bool, t: bool) !void {
try assertFalse(f or f or f);
try assertFalse(t and t and f);
try assertFalse(1 | 2 | 4 != 7);
try assertFalse(3 ^ 6 ^ 8 != 13);
try assertFalse(7 & 14 & 28 != 4);
try assertFalse(9 << 1 << 2 != 9 << 3);
try assertFalse(90 >> 1 >> 2 != 90 >> 3);
try assertFalse(100 - 1 + 1000 != 1099);
try assertFalse(5 * 4 / 2 % 3 != 1);
try assertFalse(@as(i32, @as(i32, 5)) != 5);
try assertFalse(!!false);
try assertFalse(@as(i32, 7) != --(@as(i32, 7)));
}
fn assertFalse(b: bool) !void {
try expect(!b);
}
test "@clz" {
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
try testClz();
comptime try testClz();
}
fn testClz() !void {
try expect(testOneClz(u8, 0b10001010) == 0);
try expect(testOneClz(u8, 0b00001010) == 4);
try expect(testOneClz(u8, 0b00011010) == 3);
try expect(testOneClz(u8, 0b00000000) == 8);
}
test "@clz big ints" {
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
try testClzBigInts();
comptime try testClzBigInts();
}
fn testClzBigInts() !void {
try expect(testOneClz(u128, 0xffffffffffffffff) == 64);
try expect(testOneClz(u128, 0x10000000000000000) == 63);
}
fn testOneClz(comptime T: type, x: T) u32 {
return @clz(T, x);
}
test "@clz vectors" {
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
try testClzVectors();
comptime try testClzVectors();
}
fn testClzVectors() !void {
@setEvalBranchQuota(10_000);
try testOneClzVector(u8, 64, @splat(64, @as(u8, 0b10001010)), @splat(64, @as(u4, 0)));
try testOneClzVector(u8, 64, @splat(64, @as(u8, 0b00001010)), @splat(64, @as(u4, 4)));
try testOneClzVector(u8, 64, @splat(64, @as(u8, 0b00011010)), @splat(64, @as(u4, 3)));
try testOneClzVector(u8, 64, @splat(64, @as(u8, 0b00000000)), @splat(64, @as(u4, 8)));
try testOneClzVector(u128, 64, @splat(64, @as(u128, 0xffffffffffffffff)), @splat(64, @as(u8, 64)));
try testOneClzVector(u128, 64, @splat(64, @as(u128, 0x10000000000000000)), @splat(64, @as(u8, 63)));
}
fn testOneClzVector(
comptime T: type,
comptime len: u32,
x: @Vector(len, T),
expected: @Vector(len, u32),
) !void {
try expectVectorsEqual(@clz(T, x), expected);
}
fn expectVectorsEqual(a: anytype, b: anytype) !void {
const len_a = @typeInfo(@TypeOf(a)).Vector.len;
const len_b = @typeInfo(@TypeOf(b)).Vector.len;
try expect(len_a == len_b);
var i: usize = 0;
while (i < len_a) : (i += 1) {
try expect(a[i] == b[i]);
}
}
test "@ctz" {
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
try testCtz();
comptime try testCtz();
}
fn testCtz() !void {
try expect(testOneCtz(u8, 0b10100000) == 5);
try expect(testOneCtz(u8, 0b10001010) == 1);
try expect(testOneCtz(u8, 0b00000000) == 8);
try expect(testOneCtz(u16, 0b00000000) == 16);
}
fn testOneCtz(comptime T: type, x: T) u32 {
return @ctz(T, x);
}
test "@ctz vectors" {
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .aarch64) {
// TODO this is tripping an LLVM assert:
// zig: /home/andy/Downloads/llvm-project-13/llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp:198: llvm::LegalizeActionStep llvm::LegalizeRuleSet::apply(const llvm::LegalityQuery&) const: Assertion `mutationIsSane(Rule, Query, Mutation) && "legality mutation invalid for match"' failed.
// I need to report a zig issue and an llvm issue
return error.SkipZigTest;
}
try testCtzVectors();
comptime try testCtzVectors();
}
fn testCtzVectors() !void {
@setEvalBranchQuota(10_000);
try testOneCtzVector(u8, 64, @splat(64, @as(u8, 0b10100000)), @splat(64, @as(u4, 5)));
try testOneCtzVector(u8, 64, @splat(64, @as(u8, 0b10001010)), @splat(64, @as(u4, 1)));
try testOneCtzVector(u8, 64, @splat(64, @as(u8, 0b00000000)), @splat(64, @as(u4, 8)));
try testOneCtzVector(u16, 64, @splat(64, @as(u16, 0b00000000)), @splat(64, @as(u5, 16)));
}
fn testOneCtzVector(
comptime T: type,
comptime len: u32,
x: @Vector(len, T),
expected: @Vector(len, u32),
) !void {
try expectVectorsEqual(@ctz(T, x), expected);
}
test "const number literal" {
const one = 1;
const eleven = ten + one;
try expect(eleven == 11);
}
const ten = 10;
test "float equality" {
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
const x: f64 = 0.012;
const y: f64 = x + 1.0;
try testFloatEqualityImpl(x, y);
comptime try testFloatEqualityImpl(x, y);
}
fn testFloatEqualityImpl(x: f64, y: f64) !void {
const y2 = x + 1.0;
try expect(y == y2);
}
test "hex float literal parsing" {
comptime try expect(0x1.0 == 1.0);
}
test "hex float literal within range" {
const a = 0x1.0p16383;
const b = 0x0.1p16387;
const c = 0x1.0p-16382;
_ = a;
_ = b;
_ = c;
}
test "quad hex float literal parsing in range" {
const a = 0x1.af23456789bbaaab347645365cdep+5;
const b = 0x1.dedafcff354b6ae9758763545432p-9;
const c = 0x1.2f34dd5f437e849b4baab754cdefp+4534;
const d = 0x1.edcbff8ad76ab5bf46463233214fp-435;
_ = a;
_ = b;
_ = c;
_ = d;
}
test "underscore separator parsing" {
try expect(0_0_0_0 == 0);
try expect(1_234_567 == 1234567);
try expect(001_234_567 == 1234567);
try expect(0_0_1_2_3_4_5_6_7 == 1234567);
try expect(0b0_0_0_0 == 0);
try expect(0b1010_1010 == 0b10101010);
try expect(0b0000_1010_1010 == 0b10101010);
try expect(0b1_0_1_0_1_0_1_0 == 0b10101010);
try expect(0o0_0_0_0 == 0);
try expect(0o1010_1010 == 0o10101010);
try expect(0o0000_1010_1010 == 0o10101010);
try expect(0o1_0_1_0_1_0_1_0 == 0o10101010);
try expect(0x0_0_0_0 == 0);
try expect(0x1010_1010 == 0x10101010);
try expect(0x0000_1010_1010 == 0x10101010);
try expect(0x1_0_1_0_1_0_1_0 == 0x10101010);
try expect(123_456.789_000e1_0 == 123456.789000e10);
try expect(0_1_2_3_4_5_6.7_8_9_0_0_0e0_0_1_0 == 123456.789000e10);
try expect(0x1234_5678.9ABC_DEF0p-1_0 == 0x12345678.9ABCDEF0p-10);
try expect(0x1_2_3_4_5_6_7_8.9_A_B_C_D_E_F_0p-0_0_0_1_0 == 0x12345678.9ABCDEF0p-10);
}
test "comptime_int addition" {
comptime {
try expect(35361831660712422535336160538497375248 + 101752735581729509668353361206450473702 == 137114567242441932203689521744947848950);
try expect(594491908217841670578297176641415611445982232488944558774612 + 390603545391089362063884922208143568023166603618446395589768 == 985095453608931032642182098849559179469148836107390954364380);
}
}
test "comptime_int multiplication" {
comptime {
try expect(
45960427431263824329884196484953148229 * 128339149605334697009938835852565949723 == 5898522172026096622534201617172456926982464453350084962781392314016180490567,
);
try expect(
594491908217841670578297176641415611445982232488944558774612 * 390603545391089362063884922208143568023166603618446395589768 == 232210647056203049913662402532976186578842425262306016094292237500303028346593132411865381225871291702600263463125370016,
);
}
}
test "comptime_int shifting" {
comptime {
try expect((@as(u128, 1) << 127) == 0x80000000000000000000000000000000);
}
}
test "comptime_int multi-limb shift and mask" {
comptime {
var a = 0xefffffffa0000001eeeeeeefaaaaaaab;
try expect(@as(u32, a & 0xffffffff) == 0xaaaaaaab);
a >>= 32;
try expect(@as(u32, a & 0xffffffff) == 0xeeeeeeef);
a >>= 32;
try expect(@as(u32, a & 0xffffffff) == 0xa0000001);
a >>= 32;
try expect(@as(u32, a & 0xffffffff) == 0xefffffff);
a >>= 32;
try expect(a == 0);
}
}
test "comptime_int multi-limb partial shift right" {
comptime {
var a = 0x1ffffffffeeeeeeee;
a >>= 16;
try expect(a == 0x1ffffffffeeee);
}
}
test "xor" {
if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
try test_xor();
comptime try test_xor();
}
fn test_xor() !void {
try testOneXor(0xFF, 0x00, 0xFF);
try testOneXor(0xF0, 0x0F, 0xFF);
try testOneXor(0xFF, 0xF0, 0x0F);
try testOneXor(0xFF, 0x0F, 0xF0);
try testOneXor(0xFF, 0xFF, 0x00);
}
fn testOneXor(a: u8, b: u8, c: u8) !void {
try expect(a ^ b == c);
}
test "comptime_int xor" {
comptime {
try expect(0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ^ 0x00000000000000000000000000000000 == 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF);
try expect(0xFFFFFFFFFFFFFFFF0000000000000000 ^ 0x0000000000000000FFFFFFFFFFFFFFFF == 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF);
try expect(0xFFFFFFFFFFFFFFFF0000000000000000 ^ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF == 0x0000000000000000FFFFFFFFFFFFFFFF);
try expect(0x0000000000000000FFFFFFFFFFFFFFFF ^ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF == 0xFFFFFFFFFFFFFFFF0000000000000000);
try expect(0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ^ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF == 0x00000000000000000000000000000000);
try expect(0xFFFFFFFF00000000FFFFFFFF00000000 ^ 0x00000000FFFFFFFF00000000FFFFFFFF == 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF);
try expect(0xFFFFFFFF00000000FFFFFFFF00000000 ^ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF == 0x00000000FFFFFFFF00000000FFFFFFFF);
try expect(0x00000000FFFFFFFF00000000FFFFFFFF ^ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF == 0xFFFFFFFF00000000FFFFFFFF00000000);
}
}
test "comptime_int param and return" {
const a = comptimeAdd(35361831660712422535336160538497375248, 101752735581729509668353361206450473702);
try expect(a == 137114567242441932203689521744947848950);
const b = comptimeAdd(594491908217841670578297176641415611445982232488944558774612, 390603545391089362063884922208143568023166603618446395589768);
try expect(b == 985095453608931032642182098849559179469148836107390954364380);
}
fn comptimeAdd(comptime a: comptime_int, comptime b: comptime_int) comptime_int {
return a + b;
}
test "binary not" {
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
try expect(comptime x: {
break :x ~@as(u16, 0b1010101010101010) == 0b0101010101010101;
});
try expect(comptime x: {
break :x ~@as(u64, 2147483647) == 18446744071562067968;
});
try expect(comptime x: {
break :x ~@as(u0, 0) == 0;
});
try testBinaryNot(0b1010101010101010);
}
fn testBinaryNot(x: u16) !void {
try expect(~x == 0b0101010101010101);
}
test "division" {
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
try testDivision();
comptime try testDivision();
}
fn testDivision() !void {
try expect(div(u32, 13, 3) == 4);
try expect(div(f32, 1.0, 2.0) == 0.5);
try expect(divExact(u32, 55, 11) == 5);
try expect(divExact(i32, -55, 11) == -5);
try expect(divExact(f32, 55.0, 11.0) == 5.0);
try expect(divExact(f32, -55.0, 11.0) == -5.0);
try expect(divFloor(i32, 5, 3) == 1);
try expect(divFloor(i32, -5, 3) == -2);
try expect(divFloor(f32, 5.0, 3.0) == 1.0);
try expect(divFloor(f32, -5.0, 3.0) == -2.0);
try expect(divFloor(i32, -0x80000000, -2) == 0x40000000);
try expect(divFloor(i32, 0, -0x80000000) == 0);
try expect(divFloor(i32, -0x40000001, 0x40000000) == -2);
try expect(divFloor(i32, -0x80000000, 1) == -0x80000000);
try expect(divFloor(i32, 10, 12) == 0);
try expect(divFloor(i32, -14, 12) == -2);
try expect(divFloor(i32, -2, 12) == -1);
try expect(divTrunc(i32, 5, 3) == 1);
try expect(divTrunc(i32, -5, 3) == -1);
try expect(divTrunc(i32, 9, -10) == 0);
try expect(divTrunc(i32, -9, 10) == 0);
try expect(divTrunc(f32, 5.0, 3.0) == 1.0);
try expect(divTrunc(f32, -5.0, 3.0) == -1.0);
try expect(divTrunc(f32, 9.0, -10.0) == 0.0);
try expect(divTrunc(f32, -9.0, 10.0) == 0.0);
try expect(divTrunc(f64, 5.0, 3.0) == 1.0);
try expect(divTrunc(f64, -5.0, 3.0) == -1.0);
try expect(divTrunc(f64, 9.0, -10.0) == 0.0);
try expect(divTrunc(f64, -9.0, 10.0) == 0.0);
try expect(divTrunc(i32, 10, 12) == 0);
try expect(divTrunc(i32, -14, 12) == -1);
try expect(divTrunc(i32, -2, 12) == 0);
try expect(mod(i32, 10, 12) == 10);
try expect(mod(i32, -14, 12) == 10);
try expect(mod(i32, -2, 12) == 10);
comptime {
try expect(
1194735857077236777412821811143690633098347576 % 508740759824825164163191790951174292733114988 == 177254337427586449086438229241342047632117600,
);
try expect(
@rem(-1194735857077236777412821811143690633098347576, 508740759824825164163191790951174292733114988) == -177254337427586449086438229241342047632117600,
);
try expect(
1194735857077236777412821811143690633098347576 / 508740759824825164163191790951174292733114988 == 2,
);
try expect(
@divTrunc(-1194735857077236777412821811143690633098347576, 508740759824825164163191790951174292733114988) == -2,
);
try expect(
@divTrunc(1194735857077236777412821811143690633098347576, -508740759824825164163191790951174292733114988) == -2,
);
try expect(
@divTrunc(-1194735857077236777412821811143690633098347576, -508740759824825164163191790951174292733114988) == 2,
);
try expect(
4126227191251978491697987544882340798050766755606969681711 % 10 == 1,
);
}
}
test "division half-precision floats" {
if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
try testDivisionFP16();
comptime try testDivisionFP16();
}
fn testDivisionFP16() !void {
try expect(div(f16, 1.0, 2.0) == 0.5);
try expect(divExact(f16, 55.0, 11.0) == 5.0);
try expect(divExact(f16, -55.0, 11.0) == -5.0);
try expect(divFloor(f16, 5.0, 3.0) == 1.0);
try expect(divFloor(f16, -5.0, 3.0) == -2.0);
try expect(divTrunc(f16, 5.0, 3.0) == 1.0);
try expect(divTrunc(f16, -5.0, 3.0) == -1.0);
try expect(divTrunc(f16, 9.0, -10.0) == 0.0);
try expect(divTrunc(f16, -9.0, 10.0) == 0.0);
}
fn div(comptime T: type, a: T, b: T) T {
return a / b;
}
fn divExact(comptime T: type, a: T, b: T) T {
return @divExact(a, b);
}
fn divFloor(comptime T: type, a: T, b: T) T {
return @divFloor(a, b);
}
fn divTrunc(comptime T: type, a: T, b: T) T {
return @divTrunc(a, b);
}
fn mod(comptime T: type, a: T, b: T) T {
return @mod(a, b);
}
test "unsigned wrapping" {
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
try testUnsignedWrappingEval(maxInt(u32));
comptime try testUnsignedWrappingEval(maxInt(u32));
}
fn testUnsignedWrappingEval(x: u32) !void {
const zero = x +% 1;
try expect(zero == 0);
const orig = zero -% 1;
try expect(orig == maxInt(u32));
}
test "signed wrapping" {
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
try testSignedWrappingEval(maxInt(i32));
comptime try testSignedWrappingEval(maxInt(i32));
}
fn testSignedWrappingEval(x: i32) !void {
const min_val = x +% 1;
try expect(min_val == minInt(i32));
const max_val = min_val -% 1;
try expect(max_val == maxInt(i32));
}
test "signed negation wrapping" {
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
try testSignedNegationWrappingEval(minInt(i16));
comptime try testSignedNegationWrappingEval(minInt(i16));
}
fn testSignedNegationWrappingEval(x: i16) !void {
try expect(x == -32768);
const neg = -%x;
try expect(neg == -32768);
}
test "unsigned negation wrapping" {
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
try testUnsignedNegationWrappingEval(1);
comptime try testUnsignedNegationWrappingEval(1);
}
fn testUnsignedNegationWrappingEval(x: u16) !void {
try expect(x == 1);
const neg = -%x;
try expect(neg == maxInt(u16));
}
test "unsigned 64-bit division" {
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
try test_u64_div();
comptime try test_u64_div();
}
fn test_u64_div() !void {
const result = divWithResult(1152921504606846976, 34359738365);
try expect(result.quotient == 33554432);
try expect(result.remainder == 100663296);
}
fn divWithResult(a: u64, b: u64) DivResult {
return DivResult{
.quotient = a / b,
.remainder = a % b,
};
}
const DivResult = struct {
quotient: u64,
remainder: u64,
};
test "bit shift a u1" {
var x: u1 = 1;
var y = x << 0;
try expect(y == 1);
}
test "truncating shift right" {
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
try testShrTrunc(maxInt(u16));
comptime try testShrTrunc(maxInt(u16));
}
fn testShrTrunc(x: u16) !void {
const shifted = x >> 1;
try expect(shifted == 32767);
}
test "f128" {
if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
try test_f128();
comptime try test_f128();
}
fn make_f128(x: f128) f128 {
return x;
}
fn test_f128() !void {
try expect(@sizeOf(f128) == 16);
try expect(make_f128(1.0) == 1.0);
try expect(make_f128(1.0) != 1.1);
try expect(make_f128(1.0) > 0.9);
try expect(make_f128(1.0) >= 0.9);
try expect(make_f128(1.0) >= 1.0);
try should_not_be_zero(1.0);
}
fn should_not_be_zero(x: f128) !void {
try expect(x != 0.0);
}
test "128-bit multiplication" {
if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
var a: i128 = 3;
var b: i128 = 2;
var c = a * b;
try expect(c == 6);
}
test "@addWithOverflow" {
if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
var result: u8 = undefined;
try expect(@addWithOverflow(u8, 250, 100, &result));
try expect(result == 94);
try expect(!@addWithOverflow(u8, 100, 150, &result));
try expect(result == 250);
var a: u8 = 200;
var b: u8 = 99;
try expect(@addWithOverflow(u8, a, b, &result));
try expect(result == 43);
b = 55;
try expect(!@addWithOverflow(u8, a, b, &result));
try expect(result == 255);
}
test "small int addition" {
if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
var x: u2 = 0;
try expect(x == 0);
x += 1;
try expect(x == 1);
x += 1;
try expect(x == 2);
x += 1;
try expect(x == 3);
var result: @TypeOf(x) = 3;
try expect(@addWithOverflow(@TypeOf(x), x, 1, &result));
try expect(result == 0);
}
test "@mulWithOverflow" {
if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
var result: u8 = undefined;
try expect(@mulWithOverflow(u8, 86, 3, &result));
try expect(result == 2);
try expect(!@mulWithOverflow(u8, 85, 3, &result));
try expect(result == 255);
var a: u8 = 123;
var b: u8 = 2;
try expect(!@mulWithOverflow(u8, a, b, &result));
try expect(result == 246);
b = 4;
try expect(@mulWithOverflow(u8, a, b, &result));
try expect(result == 236);
}
test "@subWithOverflow" {
if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
var result: u8 = undefined;
try expect(@subWithOverflow(u8, 1, 2, &result));
try expect(result == 255);
try expect(!@subWithOverflow(u8, 1, 1, &result));
try expect(result == 0);
var a: u8 = 1;
var b: u8 = 2;
try expect(@subWithOverflow(u8, a, b, &result));
try expect(result == 255);
b = 1;
try expect(!@subWithOverflow(u8, a, b, &result));
try expect(result == 0);
}
test "@shlWithOverflow" {
if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
var result: u16 = undefined;
try expect(@shlWithOverflow(u16, 0b0010111111111111, 3, &result));
try expect(result == 0b0111111111111000);
try expect(!@shlWithOverflow(u16, 0b0010111111111111, 2, &result));
try expect(result == 0b1011111111111100);
var a: u16 = 0b0000_0000_0000_0011;
var b: u4 = 15;
try expect(@shlWithOverflow(u16, a, b, &result));
try expect(result == 0b1000_0000_0000_0000);
b = 14;
try expect(!@shlWithOverflow(u16, a, b, &result));
try expect(result == 0b1100_0000_0000_0000);
}
test "overflow arithmetic with u0 values" {
if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
var result: u0 = undefined;
try expect(!@addWithOverflow(u0, 0, 0, &result));
try expect(result == 0);
try expect(!@subWithOverflow(u0, 0, 0, &result));
try expect(result == 0);
try expect(!@mulWithOverflow(u0, 0, 0, &result));
try expect(result == 0);
try expect(!@shlWithOverflow(u0, 0, 0, &result));
try expect(result == 0);
}
test "allow signed integer division/remainder when values are comptime known and positive or exact" {
if (builtin.zig_backend == .stage1) return error.SkipZigTest;
try expect(5 / 3 == 1);
try expect(-5 / -3 == 1);
try expect(-6 / 3 == -2);
try expect(5 % 3 == 2);
try expect(-6 % 3 == 0);
var undef: i32 = undefined;
if (0 % undef != 0) {
@compileError("0 as numerator should return comptime zero independent of denominator");
}
}
test "quad hex float literal parsing accurate" {
if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
const a: f128 = 0x1.1111222233334444555566667777p+0;
// implied 1 is dropped, with an exponent of 0 (0x3fff) after biasing.
const expected: u128 = 0x3fff1111222233334444555566667777;
try expect(@bitCast(u128, a) == expected);
// non-normalized
const b: f128 = 0x11.111222233334444555566667777p-4;
try expect(@bitCast(u128, b) == expected);
const S = struct {
fn doTheTest() !void {
{
var f: f128 = 0x1.2eab345678439abcdefea56782346p+5;
try expect(@bitCast(u128, f) == 0x40042eab345678439abcdefea5678234);
}
{
var f: f128 = 0x1.edcb34a235253948765432134674fp-1;
try expect(@bitCast(u128, f) == 0x3ffeedcb34a235253948765432134674);
}
{
var f: f128 = 0x1.353e45674d89abacc3a2ebf3ff4ffp-50;
try expect(@bitCast(u128, f) == 0x3fcd353e45674d89abacc3a2ebf3ff50);
}
{
var f: f128 = 0x1.ed8764648369535adf4be3214567fp-9;
try expect(@bitCast(u128, f) == 0x3ff6ed8764648369535adf4be3214568);
}
const exp2ft = [_]f64{
0x1.6a09e667f3bcdp-1,
0x1.7a11473eb0187p-1,
0x1.8ace5422aa0dbp-1,
0x1.9c49182a3f090p-1,
0x1.ae89f995ad3adp-1,
0x1.c199bdd85529cp-1,
0x1.d5818dcfba487p-1,
0x1.ea4afa2a490dap-1,
0x1.0000000000000p+0,
0x1.0b5586cf9890fp+0,
0x1.172b83c7d517bp+0,
0x1.2387a6e756238p+0,
0x1.306fe0a31b715p+0,
0x1.3dea64c123422p+0,
0x1.4bfdad5362a27p+0,
0x1.5ab07dd485429p+0,
0x1.8p23,
0x1.62e430p-1,
0x1.ebfbe0p-3,
0x1.c6b348p-5,
0x1.3b2c9cp-7,
0x1.0p127,
-0x1.0p-149,
};
const answers = [_]u64{
0x3fe6a09e667f3bcd,
0x3fe7a11473eb0187,
0x3fe8ace5422aa0db,
0x3fe9c49182a3f090,
0x3feae89f995ad3ad,
0x3fec199bdd85529c,
0x3fed5818dcfba487,
0x3feea4afa2a490da,
0x3ff0000000000000,
0x3ff0b5586cf9890f,
0x3ff172b83c7d517b,
0x3ff2387a6e756238,
0x3ff306fe0a31b715,
0x3ff3dea64c123422,
0x3ff4bfdad5362a27,
0x3ff5ab07dd485429,
0x4168000000000000,
0x3fe62e4300000000,
0x3fcebfbe00000000,
0x3fac6b3480000000,
0x3f83b2c9c0000000,
0x47e0000000000000,
0xb6a0000000000000,
};
for (exp2ft) |x, i| {
try expect(@bitCast(u64, x) == answers[i]);
}
}
};
try S.doTheTest();
comptime try S.doTheTest();
}
test "truncating shift left" {
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
try testShlTrunc(maxInt(u16));
comptime try testShlTrunc(maxInt(u16));
}
fn testShlTrunc(x: u16) !void {
const shifted = x << 1;
try expect(shifted == 65534);
}
test "exact shift left" {
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
try testShlExact(0b00110101);
comptime try testShlExact(0b00110101);
}
fn testShlExact(x: u8) !void {
const shifted = @shlExact(x, 2);
try expect(shifted == 0b11010100);
}
test "exact shift right" {
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
try testShrExact(0b10110100);
comptime try testShrExact(0b10110100);
}
fn testShrExact(x: u8) !void {
const shifted = @shrExact(x, 2);
try expect(shifted == 0b00101101);
}
test "shift left/right on u0 operand" {
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
const S = struct {
fn doTheTest() !void {
var x: u0 = 0;
var y: u0 = 0;
try expectEqual(@as(u0, 0), x << 0);
try expectEqual(@as(u0, 0), x >> 0);
try expectEqual(@as(u0, 0), x << y);
try expectEqual(@as(u0, 0), x >> y);
try expectEqual(@as(u0, 0), @shlExact(x, 0));
try expectEqual(@as(u0, 0), @shrExact(x, 0));
try expectEqual(@as(u0, 0), @shlExact(x, y));
try expectEqual(@as(u0, 0), @shrExact(x, y));
}
};
try S.doTheTest();
comptime try S.doTheTest();
}
test "comptime float rem int" {
comptime {
var x = @as(f32, 1) % 2;
try expect(x == 1.0);
}
}
test "remainder division" {
comptime try remdiv(f16);
comptime try remdiv(f32);
comptime try remdiv(f64);
comptime try remdiv(f128);
try remdiv(f16);
try remdiv(f64);
try remdiv(f128);
}
fn remdiv(comptime T: type) !void {
try expect(@as(T, 1) == @as(T, 1) % @as(T, 2));
try expect(@as(T, 1) == @as(T, 7) % @as(T, 3));
}
test "float remainder division using @rem" {
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
comptime try frem(f16);
comptime try frem(f32);
comptime try frem(f64);
comptime try frem(f128);
try frem(f16);
try frem(f32);
try frem(f64);
try frem(f128);
}
fn frem(comptime T: type) !void {
const epsilon = switch (T) {
f16 => 1.0,
f32 => 0.001,
f64 => 0.00001,
f128 => 0.0000001,
else => unreachable,
};
try expect(std.math.fabs(@rem(@as(T, 6.9), @as(T, 4.0)) - @as(T, 2.9)) < epsilon);
try expect(std.math.fabs(@rem(@as(T, -6.9), @as(T, 4.0)) - @as(T, -2.9)) < epsilon);
try expect(std.math.fabs(@rem(@as(T, -5.0), @as(T, 3.0)) - @as(T, -2.0)) < epsilon);
try expect(std.math.fabs(@rem(@as(T, 3.0), @as(T, 2.0)) - @as(T, 1.0)) < epsilon);
try expect(std.math.fabs(@rem(@as(T, 1.0), @as(T, 2.0)) - @as(T, 1.0)) < epsilon);
try expect(std.math.fabs(@rem(@as(T, 0.0), @as(T, 1.0)) - @as(T, 0.0)) < epsilon);
try expect(std.math.fabs(@rem(@as(T, -0.0), @as(T, 1.0)) - @as(T, -0.0)) < epsilon);
}
test "float modulo division using @mod" {
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
comptime try fmod(f16);
comptime try fmod(f32);
comptime try fmod(f64);
comptime try fmod(f128);
try fmod(f16);
try fmod(f32);
try fmod(f64);
try fmod(f128);
}
fn fmod(comptime T: type) !void {
const epsilon = switch (T) {
f16 => 1.0,
f32 => 0.001,
f64 => 0.00001,
f128 => 0.0000001,
else => unreachable,
};
try expect(std.math.fabs(@mod(@as(T, 6.9), @as(T, 4.0)) - @as(T, 2.9)) < epsilon);
try expect(std.math.fabs(@mod(@as(T, -6.9), @as(T, 4.0)) - @as(T, 1.1)) < epsilon);
try expect(std.math.fabs(@mod(@as(T, -5.0), @as(T, 3.0)) - @as(T, 1.0)) < epsilon);
try expect(std.math.fabs(@mod(@as(T, 3.0), @as(T, 2.0)) - @as(T, 1.0)) < epsilon);
try expect(std.math.fabs(@mod(@as(T, 1.0), @as(T, 2.0)) - @as(T, 1.0)) < epsilon);
try expect(std.math.fabs(@mod(@as(T, 0.0), @as(T, 1.0)) - @as(T, 0.0)) < epsilon);
try expect(std.math.fabs(@mod(@as(T, -0.0), @as(T, 1.0)) - @as(T, -0.0)) < epsilon);
}
test "@sqrt" {
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
try testSqrt(f64, 12.0);
comptime try testSqrt(f64, 12.0);
try testSqrt(f32, 13.0);
comptime try testSqrt(f32, 13.0);
try testSqrt(f16, 13.0);
comptime try testSqrt(f16, 13.0);
if (builtin.zig_backend == .stage1) {
const x = 14.0;
const y = x * x;
const z = @sqrt(y);
comptime try expect(z == x);
}
}
fn testSqrt(comptime T: type, x: T) !void {
try expect(@sqrt(x * x) == x);
}
test "@fabs" {
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
try testFabs(f128, 12.0);
comptime try testFabs(f128, 12.0);
try testFabs(f64, 12.0);
comptime try testFabs(f64, 12.0);
try testFabs(f32, 12.0);
comptime try testFabs(f32, 12.0);
try testFabs(f16, 12.0);
comptime try testFabs(f16, 12.0);
const x = 14.0;
const y = -x;
const z = @fabs(y);
comptime try expectEqual(x, z);
}
test "@fabs f80" {
if (true) {
// https://github.com/ziglang/zig/issues/11030
return error.SkipZigTest;
}
try testFabs(f80, 12.0);
comptime try testFabs(f80, 12.0);
}
fn testFabs(comptime T: type, x: T) !void {
const y = -x;
const z = @fabs(y);
try expect(x == z);
}
test "@floor" {
if (builtin.zig_backend != .stage1) return error.SkipZigTest; // TODO
try testFloor(f64, 12.0);
comptime try testFloor(f64, 12.0);
try testFloor(f32, 12.0);
comptime try testFloor(f32, 12.0);
try testFloor(f16, 12.0);
comptime try testFloor(f16, 12.0);
const x = 14.0;
const y = x + 0.7;
const z = @floor(y);
comptime try expect(x == z);
}
test "@floor f80" {
if (true) {
// https://github.com/ziglang/zig/issues/11030
return error.SkipZigTest;
}
try testFloor(f80, 12.0);
comptime try testFloor(f80, 12.0);
}
test "@floor f128" {
if (builtin.zig_backend == .stage1) {
// Fails because it incorrectly lowers to a floorl function call.
return error.SkipZigTest;
}
if (builtin.zig_backend != .stage1) return error.SkipZigTest; // TODO
testFloor(f128, 12.0);
comptime try testFloor(f128, 12.0);
}
fn testFloor(comptime T: type, x: T) !void {
const y = x + 0.6;
const z = @floor(y);
try expect(x == z);
}
test "@ceil" {
if (builtin.zig_backend != .stage1) return error.SkipZigTest; // TODO
try testCeil(f64, 12.0);
comptime try testCeil(f64, 12.0);
try testCeil(f32, 12.0);
comptime try testCeil(f32, 12.0);
try testCeil(f16, 12.0);
comptime try testCeil(f16, 12.0);
const x = 14.0;
const y = x - 0.7;
const z = @ceil(y);
comptime try expect(x == z);
}
test "@ceil f80" {
if (true) {
// https://github.com/ziglang/zig/issues/11030
return error.SkipZigTest;
}
try testCeil(f80, 12.0);
comptime try testCeil(f80, 12.0);
}
test "@ceil f128" {
if (builtin.zig_backend == .stage1) {
// Fails because it incorrectly lowers to a ceill function call.
return error.SkipZigTest;
}
if (builtin.zig_backend != .stage1) return error.SkipZigTest; // TODO
testCeil(f128, 12.0);
comptime try testCeil(f128, 12.0);
}
fn testCeil(comptime T: type, x: T) !void {
const y = x - 0.8;
const z = @ceil(y);
try expect(x == z);
}
test "@trunc" {
if (builtin.zig_backend != .stage1) return error.SkipZigTest; // TODO
try testTrunc(f64, 12.0);
comptime try testTrunc(f64, 12.0);
try testTrunc(f32, 12.0);
comptime try testTrunc(f32, 12.0);
try testTrunc(f16, 12.0);
comptime try testTrunc(f16, 12.0);
const x = 14.0;
const y = x + 0.7;
const z = @trunc(y);
comptime try expect(x == z);
}
test "@trunc f80" {
if (true) {
// https://github.com/ziglang/zig/issues/11030
return error.SkipZigTest;
}
try testTrunc(f80, 12.0);
comptime try testTrunc(f80, 12.0);
comptime {
const x: f80 = 12.0;
const y = x + 0.8;
const z = @trunc(y);
try expect(x == z);
}
}
test "@trunc f128" {
if (builtin.zig_backend == .stage1) {
// Fails because it incorrectly lowers to a truncl function call.
return error.SkipZigTest;
}
if (builtin.zig_backend != .stage1) return error.SkipZigTest; // TODO
testTrunc(f128, 12.0);
comptime try testTrunc(f128, 12.0);
}
fn testTrunc(comptime T: type, x: T) !void {
{
const y = x + 0.8;
const z = @trunc(y);
try expect(x == z);
}
{
const y = -x - 0.8;
const z = @trunc(y);
try expect(-x == z);
}
}
test "@round" {
if (builtin.zig_backend != .stage1) return error.SkipZigTest; // TODO
try testRound(f64, 12.0);
comptime try testRound(f64, 12.0);
try testRound(f32, 12.0);
comptime try testRound(f32, 12.0);
try testRound(f16, 12.0);
comptime try testRound(f16, 12.0);
const x = 14.0;
const y = x + 0.4;
const z = @round(y);
comptime try expect(x == z);
}
test "@round f80" {
if (true) {
// https://github.com/ziglang/zig/issues/11030
return error.SkipZigTest;
}
try testRound(f80, 12.0);
comptime try testRound(f80, 12.0);
}
test "@round f128" {
if (builtin.zig_backend == .stage1) {
// Fails because it incorrectly lowers to a roundl function call.
return error.SkipZigTest;
}
if (builtin.zig_backend != .stage1) return error.SkipZigTest; // TODO
testRound(f128, 12.0);
comptime try testRound(f128, 12.0);
}
fn testRound(comptime T: type, x: T) !void {
const y = x - 0.5;
const z = @round(y);
try expect(x == z);
}
test "vector integer addition" {
if (builtin.zig_backend != .stage1) return error.SkipZigTest; // TODO
const S = struct {
fn doTheTest() !void {
var a: std.meta.Vector(4, i32) = [_]i32{ 1, 2, 3, 4 };
var b: std.meta.Vector(4, i32) = [_]i32{ 5, 6, 7, 8 };
var result = a + b;
var result_array: [4]i32 = result;
const expected = [_]i32{ 6, 8, 10, 12 };
try expectEqualSlices(i32, &expected, &result_array);
}
};
try S.doTheTest();
comptime try S.doTheTest();
}
test "NaN comparison" {
if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
try testNanEqNan(f16);
try testNanEqNan(f32);
try testNanEqNan(f64);
try testNanEqNan(f128);
comptime try testNanEqNan(f16);
comptime try testNanEqNan(f32);
comptime try testNanEqNan(f64);
comptime try testNanEqNan(f128);
}
test "NaN comparison f80" {
if (true) {
// https://github.com/ziglang/zig/issues/11030
return error.SkipZigTest;
}
try testNanEqNan(f80);
comptime try testNanEqNan(f80);
}
fn testNanEqNan(comptime F: type) !void {
var nan1 = std.math.nan(F);
var nan2 = std.math.nan(F);
try expect(nan1 != nan2);
try expect(!(nan1 == nan2));
try expect(!(nan1 > nan2));
try expect(!(nan1 >= nan2));
try expect(!(nan1 < nan2));
try expect(!(nan1 <= nan2));
}
test "vector comparison" {
if (builtin.zig_backend != .stage1) return error.SkipZigTest; // TODO
const S = struct {
fn doTheTest() !void {
var a: std.meta.Vector(6, i32) = [_]i32{ 1, 3, -1, 5, 7, 9 };
var b: std.meta.Vector(6, i32) = [_]i32{ -1, 3, 0, 6, 10, -10 };
try expect(mem.eql(bool, &@as([6]bool, a < b), &[_]bool{ false, false, true, true, true, false }));
try expect(mem.eql(bool, &@as([6]bool, a <= b), &[_]bool{ false, true, true, true, true, false }));
try expect(mem.eql(bool, &@as([6]bool, a == b), &[_]bool{ false, true, false, false, false, false }));
try expect(mem.eql(bool, &@as([6]bool, a != b), &[_]bool{ true, false, true, true, true, true }));
try expect(mem.eql(bool, &@as([6]bool, a > b), &[_]bool{ true, false, false, false, false, true }));
try expect(mem.eql(bool, &@as([6]bool, a >= b), &[_]bool{ true, true, false, false, false, true }));
}
};
try S.doTheTest();
comptime try S.doTheTest();
}
test "compare undefined literal with comptime_int" {
var x = undefined == 1;
// x is now undefined with type bool
x = true;
try expect(x);
}
test "signed zeros are represented properly" {
if (builtin.zig_backend != .stage1) return error.SkipZigTest; // TODO
const S = struct {
fn doTheTest() !void {
inline for ([_]type{ f16, f32, f64, f128 }) |T| {
const ST = std.meta.Int(.unsigned, @typeInfo(T).Float.bits);
var as_fp_val = -@as(T, 0.0);
var as_uint_val = @bitCast(ST, as_fp_val);
// Ensure the sign bit is set.
try expect(as_uint_val >> (@typeInfo(T).Float.bits - 1) == 1);
}
}
};
try S.doTheTest();
comptime try S.doTheTest();
} | test/behavior/math.zig |
const gl = @import("gl");
const std = @import("std");
const zt = @import("../zt.zig");
const builtin = @import("builtin");
fn reportErr(msg: []const u8) void {
if (builtin.mode == .Debug) {
var err = gl.glGetError();
while (err != gl.GL_NO_ERROR) {
switch (err) {
gl.GL_INVALID_ENUM => {
std.debug.print("{s}\nOPENGL ERROR: INVALID ENUM\n", .{msg});
},
gl.GL_INVALID_VALUE => {
std.debug.print("{s}\nOPENGL ERROR: INVALID VALUE\n", .{msg});
},
gl.GL_INVALID_OPERATION => {
std.debug.print("{s}\nOPENGL ERROR: INVALID OPERATION\n", .{msg});
},
gl.GL_OUT_OF_MEMORY => {
std.debug.print("{s}\nOPENGL ERROR: OUT OF MEMORY\n", .{msg});
},
else => {
std.debug.print("{s}\nOPENGL ERROR: UNKNOWN ERROR\n", .{msg});
},
}
err = gl.glGetError();
}
}
}
/// Provide T as a struct to represent a vertex. Compatible types inside of struct are:
/// `f32, zt.math.Vec2, zt.math.Vec3, zt.math.Vec4`
/// and each will be mapped in order to vert shader's layout indices.
/// The resulting buffer can contain many quads and tris together.
/// V is a maximum vertex count before flush is requested by an error on add*() functions.
pub fn GenerateBuffer(comptime T: type, comptime V: usize) type {
return struct {
pub const VertexLimit = V;
pub const IndexLimit = V * 6;
vaoId: c_uint = undefined,
vboId: c_uint = undefined,
iboId: c_uint = undefined,
vertices: [V]T = undefined,
vertCount: usize = 0,
// Worst case scenario every singl.gle draw is a quad, so * 6.
indices: [IndexLimit]c_uint = undefined,
indCount: usize = 0,
shader: zt.gl.Shader = undefined,
dirty: bool = true,
pub fn init(shader: zt.gl.Shader) @This() {
var self = @This(){};
self.shader = shader;
gl.glGenBuffers(1, &self.vboId);
gl.glGenBuffers(1, &self.iboId);
// Create VAO
gl.glGenVertexArrays(1, &self.vaoId);
gl.glBindVertexArray(self.vaoId);
gl.glBindBuffer(gl.GL_ARRAY_BUFFER, self.vboId);
gl.glBindBuffer(gl.GL_ELEMENT_ARRAY_BUFFER, self.iboId);
var currentOffset: usize = 0;
var stride: c_int = @intCast(c_int, @sizeOf(T));
inline for (std.meta.fields(T)) |field, i| {
switch (field.field_type) {
f32 => {
gl.glVertexAttribPointer(@intCast(c_uint, i), 1, gl.GL_FLOAT, gl.GL_FALSE, stride, @intToPtr(*allowzero c_void, currentOffset));
gl.glEnableVertexAttribArray(@intCast(c_uint, i));
currentOffset += 4;
},
zt.math.Vec2 => {
gl.glVertexAttribPointer(@intCast(c_uint, i), 2, gl.GL_FLOAT, gl.GL_FALSE, stride, @intToPtr(*allowzero c_void, currentOffset));
gl.glEnableVertexAttribArray(@intCast(c_uint, i));
currentOffset += 8;
},
zt.math.Vec3 => {
gl.glVertexAttribPointer(@intCast(c_uint, i), 3, gl.GL_FLOAT, gl.GL_FALSE, stride, @intToPtr(*allowzero c_void, currentOffset));
gl.glEnableVertexAttribArray(@intCast(c_uint, i));
currentOffset += 12;
},
zt.math.Vec4 => {
gl.glVertexAttribPointer(@intCast(c_uint, i), 4, gl.GL_FLOAT, gl.GL_FALSE, stride, @intToPtr(*allowzero c_void, currentOffset));
gl.glEnableVertexAttribArray(@intCast(c_uint, i));
currentOffset += 16;
},
else => {
@compileError("Vertex Struct had types incompatible with automatic buffers.");
},
}
}
gl.glBindVertexArray(0);
return self;
}
pub fn deinit(self: *@This()) void {
gl.glDeleteVertexArrays(1, &self.vaoId);
gl.glDeleteBuffers(1, &self.vboId);
gl.glDeleteBuffers(1, &self.iboId);
reportErr("Deleting the buffers:");
}
pub fn bind(self: *@This()) void {
gl.glBindVertexArray(self.vaoId);
self.shader.bind();
gl.glBindBuffer(gl.GL_ARRAY_BUFFER, self.vboId);
gl.glBindBuffer(gl.GL_ELEMENT_ARRAY_BUFFER, self.iboId);
reportErr("Binding the buffers:");
}
pub fn unbind(self: *@This()) void {
_ = self;
gl.glBindVertexArray(0);
self.shader.unbind();
gl.glBindBuffer(gl.GL_ARRAY_BUFFER, 0);
gl.glBindBuffer(gl.GL_ELEMENT_ARRAY_BUFFER, 0);
reportErr("Unbinding the buffers:");
}
pub fn clear(self: *@This()) void {
self.vertCount = 0;
self.indCount = 0;
self.dirty = true;
}
pub fn addTri(self: *@This(), v1: T, v2: T, v3: T) !void {
if (self.vertCount + 3 >= V) {
return error.NeedsFlush;
}
self.vertices[self.vertCount + 0] = v1;
self.vertices[self.vertCount + 1] = v2;
self.vertices[self.vertCount + 2] = v3;
self.indices[self.indCount + 0] = (@intCast(c_uint, self.vertCount + 0));
self.indices[self.indCount + 1] = (@intCast(c_uint, self.vertCount + 1));
self.indices[self.indCount + 2] = (@intCast(c_uint, self.vertCount + 2));
self.indCount += 3;
self.vertCount += 3;
self.dirty = true;
}
pub fn addQuad(self: *@This(), bl: T, tl: T, tr: T, br: T) !void {
if (self.vertCount + 4 >= V) {
return error.NeedsFlush;
}
self.vertices[self.vertCount + 0] = bl;
self.vertices[self.vertCount + 1] = tl;
self.vertices[self.vertCount + 2] = tr;
self.vertices[self.vertCount + 3] = br;
self.indices[self.indCount + 0] = @intCast(c_uint, self.vertCount + 0);
self.indices[self.indCount + 1] = @intCast(c_uint, self.vertCount + 1);
self.indices[self.indCount + 2] = @intCast(c_uint, self.vertCount + 3);
self.indices[self.indCount + 3] = @intCast(c_uint, self.vertCount + 1);
self.indices[self.indCount + 4] = @intCast(c_uint, self.vertCount + 2);
self.indices[self.indCount + 5] = @intCast(c_uint, self.vertCount + 3);
self.vertCount += 4;
self.indCount += 6;
self.dirty = true;
}
/// Commits to opengl.gl with the currently added sprites in a static memory location. Use this if you are going
/// to very rarely push again. You can still flush as many times as needed.
pub fn pushStatic(self: *@This()) void {
if (!self.dirty) {
return;
}
self.bind();
var vertSize: c_longlong = @intCast(c_longlong, @sizeOf(T) * self.vertCount);
var indSize: c_longlong = @intCast(c_longlong, @sizeOf(c_uint) * self.indCount);
gl.glBufferData(gl.GL_ARRAY_BUFFER, vertSize, &self.vertices, gl.GL_STATIC_DRAW);
gl.glBufferData(gl.GL_ELEMENT_ARRAY_BUFFER, indSize, &self.indices, gl.GL_STATIC_DRAW);
self.unbind();
self.dirty = false;
}
/// Commits to opengl.gl with the currently added sprites in a dynamic memory location. Use this if you are pushing
/// and flushing once a frame.
pub fn pushDynamic(self: *@This()) void {
if (!self.dirty) {
return;
}
self.bind();
var vertSize: c_longlong = @intCast(c_longlong, @sizeOf(T) * self.vertCount);
var indSize: c_longlong = @intCast(c_longlong, @sizeOf(c_uint) * self.indCount);
gl.glBufferData(gl.GL_ARRAY_BUFFER, vertSize, &self.vertices, gl.GL_DYNAMIC_DRAW);
gl.glBufferData(gl.GL_ELEMENT_ARRAY_BUFFER, indSize, &self.indices, gl.GL_DYNAMIC_DRAW);
self.unbind();
self.dirty = false;
}
/// Commits to opengl.gl with the currently added sprites in a streaming memory location. Use this if you are going
/// to be pushing and flushing multiple times per frame.
pub fn pushStream(self: *@This()) void {
if (!self.dirty) {
return;
}
self.bind();
var vertSize = @intCast(c_longlong, @sizeOf(T) * self.vertCount);
var indSize = @intCast(c_longlong, @sizeOf(c_uint) * self.indCount);
gl.glBufferData(gl.GL_ARRAY_BUFFER, vertSize, &self.vertices, gl.GL_STREAM_DRAW);
gl.glBufferData(gl.GL_ELEMENT_ARRAY_BUFFER, indSize, &self.indices, gl.GL_STREAM_DRAW);
self.unbind();
self.dirty = false;
reportErr("Pushing the buffers:");
}
/// Draws the currently pushed data to the screen. Note the data is not cleared, leaving you the option to maintain
/// the current vertices every frame if so desired.
pub fn flush(self: *@This()) void {
self.bind();
gl.glDrawElements(gl.GL_TRIANGLES, @intCast(c_int, self.indCount), gl.GL_UNSIGNED_INT, null);
self.unbind();
reportErr("Flushing the buffers:");
}
pub fn setUniform(self: *@This(), comptime uniName: []const u8, uniform: anytype) void {
_ = self;
var loc: c_int = gl.glGetUniformLocation(self.shader.id, uniName.ptr);
self.shader.bind();
if (loc != -1) {
switch (@TypeOf(uniform)) {
bool => {
gl.glUniform1i(loc, if (uniform) 1 else 0);
reportErr("Setting a uniform bool(i32):");
},
i32 => {
gl.glUniform1i(loc, uniform);
reportErr("Setting a uniform i32:");
},
u32 => {
gl.glUniform1ui(loc, uniform);
reportErr("Setting a uniform u32:");
},
f32 => {
gl.glUniform1f(loc, uniform);
reportErr("Setting a uniform f32:");
},
zt.math.Vec2 => {
gl.glUniform2f(loc, uniform.x, uniform.y);
reportErr("Setting a uniform vec2:");
},
zt.math.Vec3 => {
gl.glUniform3f(loc, uniform.x, uniform.y, uniform.z);
reportErr("Setting a uniform vec3:");
},
zt.math.Vec4 => {
gl.glUniform4f(loc, uniform.x, uniform.y, uniform.z, uniform.w);
reportErr("Setting a uniform vec4:");
},
zt.math.Mat4 => {
gl.glUniformMatrix4fv(loc, 1, 0, &uniform.inlined());
reportErr("Setting a uniform mat4:");
},
else => {
@compileError("You cannot use that type in a genbuffer's uniform.");
},
}
}
self.shader.unbind();
reportErr("Setting a uniform (location not found):");
}
};
} | src/zt/generateBuffer.zig |
const std = @import("std");
const hzzp = @import("hzzp");
const iguanaTLS = @import("iguanaTLS");
pub const root_ca = struct {
const pem = @embedFile("../cacert.pem");
var cert_chain: ?iguanaTLS.x509.CertificateChain = null;
/// Initializes the bundled root certificates
/// This is a shared chain that's used whenever an PEM is not passed in
pub fn preload(allocator: *std.mem.Allocator) !void {
std.debug.assert(cert_chain == null);
var fbs = std.io.fixedBufferStream(pem);
cert_chain = try iguanaTLS.x509.CertificateChain.from_pem(allocator, fbs.reader());
}
pub fn deinit() void {
cert_chain.?.deinit();
cert_chain = null;
}
};
pub const Tunnel = struct {
allocator: *std.mem.Allocator,
client: Client,
tcp_conn: std.net.Stream,
state: enum { connected, shutdown },
pub const Client = iguanaTLS.Client(std.net.Stream.Reader, std.net.Stream.Writer, iguanaTLS.ciphersuites.all, false);
pub fn create(args: struct {
allocator: *std.mem.Allocator,
host: []const u8,
port: u16 = 443,
pem: ?[]const u8 = null,
}) !*Tunnel {
const result = try args.allocator.create(Tunnel);
errdefer args.allocator.destroy(result);
result.allocator = args.allocator;
const trusted_chain = if (args.pem) |pem| blk: {
var fbs = std.io.fixedBufferStream(pem);
break :blk try iguanaTLS.x509.CertificateChain.from_pem(args.allocator, fbs.reader());
} else root_ca.cert_chain.?;
defer if (args.pem) |_| trusted_chain.deinit();
result.tcp_conn = try std.net.tcpConnectToHost(args.allocator, args.host, args.port);
errdefer result.tcp_conn.close();
result.client = try iguanaTLS.client_connect(.{
.reader = result.tcp_conn.reader(),
.writer = result.tcp_conn.writer(),
.cert_verifier = .default,
.trusted_certificates = trusted_chain.data.items,
.temp_allocator = args.allocator,
}, args.host);
errdefer client.close_notify() catch {};
return result;
}
pub fn shutdown(self: *Tunnel) !void {
std.debug.assert(self.state == .connected);
const close_err = self.client.close_notify();
try std.os.shutdown(self.tcp_conn.handle, .both);
self.state = .shutdown;
try close_err;
}
pub fn destroy(self: *Tunnel) void {
if (self.state == .connected) {
self.client.close_notify() catch {};
}
self.tcp_conn.close();
self.allocator.destroy(self);
}
};
pub const Request = struct {
allocator: *std.mem.Allocator,
tunnel: *Tunnel,
buffer: []u8,
client: hzzp.base.client.BaseClient(Tunnel.Client.Reader, Tunnel.Client.Writer),
response_code: ?hzzp.StatusCode,
pub const Method = enum { GET, POST, PUT, DELETE, PATCH };
pub fn init(args: struct {
allocator: *std.mem.Allocator,
host: []const u8,
port: u16 = 443,
method: Method,
path: []const u8,
user_agent: []const u8 = "zCord/0.0.1",
pem: ?[]const u8 = null,
}) !Request {
var tunnel = try Tunnel.create(.{
.allocator = args.allocator,
.host = args.host,
.port = args.port,
.pem = args.pem,
});
errdefer tunnel.destroy();
const buffer = try args.allocator.alloc(u8, 0x1000);
errdefer args.allocator.free(buffer);
var client = hzzp.base.client.create(buffer, tunnel.client.reader(), tunnel.client.writer());
try client.writeStatusLine(@tagName(args.method), args.path);
try client.writeHeaderValue("Host", args.host);
try client.writeHeaderValue("User-Agent", args.user_agent);
return Request{
.allocator = args.allocator,
.tunnel = tunnel,
.buffer = buffer,
.client = client,
.response_code = null,
};
}
pub fn deinit(self: *Request) void {
self.tunnel.destroy();
self.allocator.free(self.buffer);
self.* = undefined;
}
pub const printSend = @compileError("Deprecated: please switch to `sendPrint(fmt, args)`");
pub const expectSuccessStatus = @compileError("Deprecated: please switch to `req.response_code.group() == .success`");
// TODO: fix this name
pub fn sendPrint(self: *Request, comptime fmt: []const u8, args: anytype) !hzzp.StatusCode {
try self.client.writeHeaderFormat("Content-Length", "{d}", .{std.fmt.count(fmt, args)});
try self.client.finishHeaders();
try self.client.writer.print(fmt, args);
return try self.initResponseCode();
}
// TODO: fix this name
pub fn sendEmptyBody(self: *Request) !hzzp.StatusCode {
try self.client.finishHeaders();
try self.client.writePayload(null);
return try self.initResponseCode();
}
fn initResponseCode(self: *Request) !hzzp.StatusCode {
if (self.response_code) |code| return code;
const event = (try self.client.next()).?;
if (event != .status) {
return error.MissingStatus;
}
const raw_code = std.math.cast(u10, event.status.code) catch 666;
self.response_code = @intToEnum(hzzp.StatusCode, raw_code);
return self.response_code.?;
}
pub fn completeHeaders(self: *Request) !void {
_ = try self.initResponseCode();
while (try self.client.next()) |event| {
if (event == .head_done) {
return;
}
}
}
pub fn debugDumpResponse(self: *Request, writer: anytype) !void {
try self.initResponseCode();
try self.debugDumpHeaders(writer);
try self.debugDumpBody(writer);
}
pub fn debugDumpHeaders(self: *Request, writer: anytype) !void {
while (try self.client.next()) |event| {
switch (event) {
.header => |header| try writer.print("{s}: {s}\n", .{ header.name, header.value }),
.head_done => return,
else => unreachable,
}
}
}
pub fn debugDumpBody(self: *Request, writer: anytype) !void {
const reader = self.client.reader();
var buf: [0x1000]u8 = undefined;
while (true) {
const len = try reader.read(&buf);
if (len == 0) break;
try writer.writeAll(buf[0..len]);
}
try writer.writeAll("\n");
}
}; | src/https.zig |
const std = @import("std");
const upaya = @import("upaya");
const ts = @import("../tilescript.zig");
const colors = @import("../colors.zig");
const brushes_win = @import("brushes.zig");
usingnamespace @import("imgui");
const Rule = @import("../map.zig").Rule;
const RuleSet = @import("../map.zig").RuleSet;
var rule_label_buf: [25]u8 = undefined;
var group_label_buf: [25]u8 = undefined;
var new_rule_label_buf: [25]u8 = undefined;
var pre_ruleset_tab_buf: [5]u8 = undefined;
var nine_slice_selected: ?usize = null;
var current_ruleset: usize = std.math.maxInt(usize);
var ruleset_delete_index: usize = undefined;
var drag_drop_state = struct {
source: union(enum) {
rule: *Rule,
group: u8,
} = undefined,
from: usize = 0,
to: usize = 0,
above_group: bool = false,
completed: bool = false,
active: bool = false,
rendering_group: bool = false,
dropped_in_group: bool = false,
pub fn isGroup(self: @This()) bool {
return switch (self.source) {
.group => true,
else => false,
};
}
pub fn handle(self: *@This(), rules: *std.ArrayList(Rule)) void {
self.completed = false;
switch (self.source) {
.group => swapGroups(rules),
else => swapRules(rules),
}
self.above_group = false;
}
}{};
/// used by the fllod fill popup
var fill_dirs = struct {
left: bool = true,
right: bool = true,
up: bool = false,
down: bool = true,
pub fn reset(self: *@This()) void {
self.left = true;
self.right = true;
self.down = true;
self.up = false;
}
pub fn valid(self: @This()) bool {
return self.left or self.right or self.down or self.up;
}
}{};
fn drawRuleSetTabButtons(state: *ts.AppState, cursor: ImVec2, open_repeat_popup: *bool) void {
var cur = cursor;
cur.x += igGetWindowContentRegionWidth() - 50;
cur.y -= 1;
igSetCursorPos(cur);
if (igButton(icons.sliders_h, .{})) {
open_repeat_popup.* = true;
}
igSameLine(0, 5);
if (igButton(icons.plus, .{})) {
state.map.addPreRuleSet();
}
ogUnformattedTooltip(20, "Adds a new RuleSet, which is a group of rules that transform the input map before regular rules are run");
}
pub fn draw(state: *ts.AppState) void {
igPushStyleVarVec2(ImGuiStyleVar_WindowMinSize, .{ .x = 365 });
defer igPopStyleVar(1);
current_ruleset = std.math.maxInt(usize);
_ = igBegin("Rules", null, ImGuiWindowFlags_None);
defer igEnd();
// save the cursor position so we can hack a button on the tab bar itself or just aligned right
var cursor = ogGetCursorPos();
var open_repeat_popup = false;
if (state.map.pre_rulesets.items.len > 5) {
drawRuleSetTabButtons(state, cursor, &open_repeat_popup);
igGetCursorStartPos(&cursor);
cursor.y += igGetFrameHeightWithSpacing();
igSetCursorPos(cursor);
}
if (igBeginTabBar("Rules##tabbar", ImGuiTabBarFlags_AutoSelectNewTabs | ImGuiTabBarFlags_FittingPolicyScroll)) {
defer igEndTabBar();
if (state.map.pre_rulesets.items.len <= 5) {
drawRuleSetTabButtons(state, cursor, &open_repeat_popup);
}
if (igBeginTabItem("Final", null, ImGuiTabItemFlags_NoCloseButton)) {
defer igEndTabItem();
drawRulesTab(state);
}
drawPreRulesTabs(state);
if (open_repeat_popup) {
igOpenPopup("##seed-repeat");
}
rulesetSettingsPopup(state);
}
if (drag_drop_state.active and igIsMouseReleased(ImGuiMouseButton_Left)) {
drag_drop_state.active = false;
}
}
/// handles the actual logic to rearrange the Rule for drag/drop when a Rule is reordered
fn swapRules(rules: *std.ArrayList(Rule)) void {
// dont assign the group unless we are swapping into a group proper
if (!drag_drop_state.above_group and drag_drop_state.dropped_in_group) {
const to = if (rules.items.len == drag_drop_state.to) drag_drop_state.to - 1 else drag_drop_state.to;
const group = rules.items[to].group;
rules.items[drag_drop_state.from].group = group;
} else {
rules.items[drag_drop_state.from].group = 0;
}
// get the total number of steps we need to do the swap. We move to index+1 so account for that when moving to a higher index
var total_swaps = if (drag_drop_state.from > drag_drop_state.to) drag_drop_state.from - drag_drop_state.to else drag_drop_state.to - drag_drop_state.from - 1;
while (total_swaps > 0) : (total_swaps -= 1) {
if (drag_drop_state.from > drag_drop_state.to) {
std.mem.swap(Rule, &rules.items[drag_drop_state.from], &rules.items[drag_drop_state.from - 1]);
drag_drop_state.from -= 1;
} else {
std.mem.swap(Rule, &rules.items[drag_drop_state.from], &rules.items[drag_drop_state.from + 1]);
drag_drop_state.from += 1;
}
}
}
/// handles the actual logic to rearrange the Rule for drag/drop when a group is reordered
fn swapGroups(rules: *std.ArrayList(Rule)) void {
var total_in_group = blk: {
var total: usize = 0;
for (rules.items) |rule| {
if (rule.group == drag_drop_state.source.group) total += 1;
}
break :blk total;
};
var total_swaps = if (drag_drop_state.from > drag_drop_state.to) drag_drop_state.from - drag_drop_state.to else drag_drop_state.to - drag_drop_state.from - total_in_group;
if (total_swaps == 0) return;
while (total_swaps > 0) : (total_swaps -= 1) {
// when moving up, we can just move each item in our group up one slot
if (drag_drop_state.from > drag_drop_state.to) {
var j: usize = 0;
while (j < total_in_group) : (j += 1) {
std.mem.swap(Rule, &rules.items[drag_drop_state.from + j], &rules.items[drag_drop_state.from - 1 + j]);
}
drag_drop_state.from -= 1;
} else {
// moving down, we have to move the last item in the group first each step
var j: usize = total_in_group - 1;
while (j >= 0) : (j -= 1) {
std.mem.swap(Rule, &rules.items[drag_drop_state.from + j], &rules.items[drag_drop_state.from + 1 + j]);
if (j == 0) break;
}
drag_drop_state.from += 1;
}
}
}
fn drawRulesTab(state: *ts.AppState) void {
var group: u8 = 0;
var delete_index: usize = std.math.maxInt(usize);
var i: usize = 0;
while (i < state.map.ruleset.rules.items.len) : (i += 1) {
// if we have a Rule in a group render all the Rules in that group at once
if (state.map.ruleset.rules.items[i].group > 0 and state.map.ruleset.rules.items[i].group != group) {
group = state.map.ruleset.rules.items[i].group;
igPushIDInt(@intCast(c_int, group));
groupDropTarget(state.map.ruleset.rules.items[i].group, i);
std.mem.set(u8, &group_label_buf, 0);
std.mem.copy(u8, &group_label_buf, state.map.getGroupName(group));
const header_open = igCollapsingHeaderBoolPtr(&group_label_buf, null, ImGuiTreeNodeFlags_DefaultOpen);
groupDragDrop(state.map.ruleset.rules.items[i].group, i);
if (igIsItemHovered(ImGuiHoveredFlags_None) and igIsMouseClicked(ImGuiMouseButton_Right, false)) {
igOpenPopup("##rename-group");
std.mem.copy(u8, &new_rule_label_buf, state.map.getGroupName(group));
}
igSetNextWindowPos(igGetIO().MousePos, ImGuiCond_Appearing, .{ .x = 0.5 });
if (igBeginPopup("##rename-group", ImGuiWindowFlags_None)) {
_ = ogInputText("##name", &new_rule_label_buf, new_rule_label_buf.len);
if (igButton("Rename Group", .{ .x = -1, .y = 0 })) {
igCloseCurrentPopup();
const label_sentinel_index = std.mem.indexOfScalar(u8, &new_rule_label_buf, 0).?;
state.map.renameGroup(group, new_rule_label_buf[0..label_sentinel_index]);
}
igEndPopup();
}
igPopID();
if (header_open) {
igIndent(10);
drag_drop_state.rendering_group = true;
}
rulesDragDrop(i, &state.map.ruleset.rules.items[i], true, false);
while (i < state.map.ruleset.rules.items.len and state.map.ruleset.rules.items[i].group == group) : (i += 1) {
if (header_open and drawRule(state, &state.map.ruleset, &state.map.ruleset.rules.items[i], i, false)) {
delete_index = i;
}
}
if (header_open) {
igUnindent(10);
drag_drop_state.rendering_group = false;
}
// if a group is the last item dont try to render any more! else decrement and get back to the loop start since we skipped the last item
if (i == state.map.ruleset.rules.items.len) break;
i -= 1;
continue;
}
if (drawRule(state, &state.map.ruleset, &state.map.ruleset.rules.items[i], i, false)) {
delete_index = i;
}
}
if (delete_index < state.map.ruleset.rules.items.len) {
const removed = state.map.ruleset.rules.orderedRemove(delete_index);
if (removed.group > 0) {
state.map.removeGroupIfEmpty(removed.group);
}
state.map_data_dirty = true;
}
// handle drag and drop swapping
if (drag_drop_state.completed) {
drag_drop_state.handle(&state.map.ruleset.rules);
}
if (ogButton("Add Rule")) {
state.map.ruleset.addRule();
}
igSameLine(0, 10);
if (ogButton("Add 9-Slice")) {
igOpenPopup("nine-slice-wizard");
// reset temp state
std.mem.set(u8, &new_rule_label_buf, 0);
nine_slice_selected = null;
}
igSameLine(0, 10);
if (ogButton("Add Inner-4")) {
igOpenPopup("inner-four-wizard");
// reset temp state
std.mem.set(u8, &new_rule_label_buf, 0);
nine_slice_selected = null;
}
igSetNextWindowPos(igGetIO().MousePos, ImGuiCond_Appearing, .{ .x = 0.5 });
if (igBeginPopup("nine-slice-wizard", ImGuiWindowFlags_None)) {
nineSlicePopup(state, 3);
igEndPopup();
}
igSetNextWindowPos(igGetIO().MousePos, ImGuiCond_Appearing, .{ .x = 0.5 });
if (igBeginPopup("inner-four-wizard", ImGuiWindowFlags_None)) {
nineSlicePopup(state, 2);
igEndPopup();
}
}
fn drawPreRulesTabs(state: *ts.AppState) void {
for (state.map.pre_rulesets.items) |*ruleset, i| {
var is_tab_open = true;
igPushIDPtr(ruleset);
std.mem.set(u8, &pre_ruleset_tab_buf, 0);
_ = std.fmt.bufPrint(&pre_ruleset_tab_buf, icons.code_branch ++ "{}", .{i}) catch unreachable;
if (igBeginTabItem(&pre_ruleset_tab_buf, &is_tab_open, ImGuiTabItemFlags_None)) {
defer igEndTabItem();
current_ruleset = i;
var delete_rule_index: usize = std.math.maxInt(usize);
for (ruleset.rules.items) |*rule, j| {
if (drawRule(state, ruleset, rule, j, true)) {
delete_rule_index = j;
}
}
if (ogButton("Add Rule")) {
ruleset.rules.append(Rule.init()) catch unreachable;
}
igSameLine(0, 10);
if (ogButton("Add Flood Fill")) {
igOpenPopup("flood-fill");
// reset temp state
std.mem.set(u8, &new_rule_label_buf, 0);
fill_dirs.reset();
}
if (delete_rule_index < ruleset.rules.items.len) {
_ = ruleset.rules.orderedRemove(delete_rule_index);
}
if (drag_drop_state.completed) {
drag_drop_state.handle(&ruleset.rules);
state.map_data_dirty = true;
}
floodFillPopup(state, ruleset);
}
igPopID();
if (!is_tab_open) {
ruleset_delete_index = i;
igOpenPopup("Delete RuleSet");
}
} // end pre_rules loop
igSetNextWindowPos(igGetIO().MousePos, ImGuiCond_Appearing, .{ .x = 0.5 });
if (igBeginPopupModal("Delete RuleSet", null, ImGuiWindowFlags_AlwaysAutoResize)) {
deletePreRuleSetPopup(state);
igEndPopup();
}
}
fn deletePreRuleSetPopup(state: *ts.AppState) void {
igText("Are you sure you want to delete\nthis RuleSet?");
igSeparator();
var size = ogGetContentRegionAvail();
if (igButton("Cancel", ImVec2{ .x = (size.x - 4) / 2 })) {
igCloseCurrentPopup();
}
igSameLine(0, 4);
igPushStyleColorU32(ImGuiCol_Button, ts.colors.colorRgb(180, 25, 35));
igPushStyleColorU32(ImGuiCol_ButtonHovered, ts.colors.colorRgb(240, 20, 30));
if (igButton("Delete", ImVec2{ .x = -1, .y = 0 })) {
const removed_rules_page = state.map.pre_rulesets.orderedRemove(ruleset_delete_index);
removed_rules_page.deinit();
state.map_data_dirty = true;
igCloseCurrentPopup();
}
igPopStyleColor(2);
}
fn rulesetSettingsPopup(state: *ts.AppState) void {
if (igBeginPopup("##seed-repeat", ImGuiWindowFlags_None)) {
var ruleset = if (current_ruleset == std.math.maxInt(usize)) &state.map.ruleset else &state.map.pre_rulesets.items[current_ruleset];
if (ogDrag(usize, "Seed", &ruleset.seed, 1, 0, 1000)) {
state.map_data_dirty = true;
}
// only pre_rulesets (valid current_ruleset index into their slice) get the repeat control
if (current_ruleset < std.math.maxInt(usize) and ogDrag(u8, "Repeat", &ruleset.repeat, 0.2, 0, 100)) {
state.map_data_dirty = true;
}
igEndPopup();
}
}
fn groupDropTarget(group: u8, index: usize) void {
if (drag_drop_state.active) {
var cursor = ogGetCursorPos();
const old_pos = cursor;
cursor.y -= 5;
igSetCursorPos(cursor);
igPushStyleColorU32(ImGuiCol_Button, colors.colorRgb(0, 255, 0));
_ = igInvisibleButton("", .{ .x = -1, .y = 8 });
igPopStyleColor(1);
igSetCursorPos(old_pos);
}
if (igBeginDragDropTarget()) {
defer igEndDragDropTarget();
if (igAcceptDragDropPayload("RULESET_DRAG", ImGuiDragDropFlags_None)) |payload| {
drag_drop_state.completed = true;
drag_drop_state.to = index;
drag_drop_state.above_group = true;
drag_drop_state.active = false;
}
}
}
fn groupDragDrop(group: u8, index: usize) void {
if (igBeginDragDropSource(ImGuiDragDropFlags_SourceNoHoldToOpenOthers)) {
drag_drop_state.active = true;
drag_drop_state.from = index;
drag_drop_state.source = .{ .group = group };
_ = igSetDragDropPayload("RULESET_DRAG", null, 0, ImGuiCond_Once);
_ = igButton("group move", .{ .x = ogGetContentRegionAvail().x, .y = 20 });
igEndDragDropSource();
}
}
/// handles drag/drop sources and targets
fn rulesDragDrop(index: usize, rule: *Rule, drop_only: bool, is_pre_rule: bool) void {
var cursor = ogGetCursorPos();
if (!drop_only) {
_ = ogButton(icons.grip_horizontal);
ogUnformattedTooltip(20, if (is_pre_rule or rule.group > 0) "Click and drag to reorder" else "Click and drag to reorder\nRight-click to add a group");
igSameLine(0, 4);
if (igBeginDragDropSource(ImGuiDragDropFlags_None)) {
drag_drop_state.active = true;
_ = igSetDragDropPayload("RULESET_DRAG", null, 0, ImGuiCond_Once);
drag_drop_state.from = index;
drag_drop_state.source = .{ .rule = rule };
_ = igButton(&rule.name, .{ .x = ogGetContentRegionAvail().x, .y = 20 });
igEndDragDropSource();
}
}
// if we are dragging a group dont allow dragging it into another group
if (drag_drop_state.active and !(drag_drop_state.isGroup() and rule.group > 0)) {
const old_pos = ogGetCursorPos();
cursor.y -= 5;
igSetCursorPos(cursor);
igPushStyleColorU32(ImGuiCol_Button, colors.colorRgb(255, 0, 0));
_ = igInvisibleButton("", .{ .x = -1, .y = 8 });
igPopStyleColor(1);
igSetCursorPos(old_pos);
if (igBeginDragDropTarget()) {
if (igAcceptDragDropPayload("RULESET_DRAG", ImGuiDragDropFlags_None)) |payload| {
drag_drop_state.dropped_in_group = drag_drop_state.rendering_group;
drag_drop_state.completed = true;
drag_drop_state.to = index;
// if this is a group being dragged, we cant rule out the operation since we could have 1 to n items in our group
if (!drag_drop_state.isGroup()) {
// dont allow swapping to the same location, which is the drop target above or below the dragged item
if (drag_drop_state.from == drag_drop_state.to or (drag_drop_state.to > 0 and drag_drop_state.from == drag_drop_state.to - 1)) {
drag_drop_state.completed = false;
}
}
drag_drop_state.active = false;
}
igEndDragDropTarget();
}
}
}
fn drawRule(state: *ts.AppState, ruleset: *RuleSet, rule: *Rule, index: usize, is_pre_rule: bool) bool {
igPushIDPtr(rule);
defer igPopID();
rulesDragDrop(index, rule, false, is_pre_rule);
// right-click the move button to add the Rule to a group only if not already in a group and not a pre rule
if (!is_pre_rule and rule.group == 0) {
if (igIsItemHovered(ImGuiHoveredFlags_None) and igIsMouseClicked(ImGuiMouseButton_Right, false)) {
igOpenPopup("##group-name");
std.mem.set(u8, &new_rule_label_buf, 0);
}
igSetNextWindowPos(igGetIO().MousePos, ImGuiCond_Appearing, .{ .x = 0.5 });
if (igBeginPopup("##group-name", ImGuiWindowFlags_None)) {
defer igEndPopup();
_ = ogInputText("##group-name", &new_rule_label_buf, new_rule_label_buf.len);
const label_sentinel_index = std.mem.indexOfScalar(u8, &new_rule_label_buf, 0).?;
const disabled = label_sentinel_index == 0;
if (disabled) {
igPushItemFlag(ImGuiItemFlags_Disabled, true);
igPushStyleVarFloat(ImGuiStyleVar_Alpha, 0.5);
}
if (igButton("Add to New Group", .{ .x = -1, .y = 0 })) {
igCloseCurrentPopup();
// get the next available group
rule.group = ruleset.getNextAvailableGroup(&state.map, new_rule_label_buf[0..label_sentinel_index]);
std.mem.set(u8, &new_rule_label_buf, 0);
}
if (disabled) {
igPopItemFlag();
igPopStyleVar(1);
}
}
}
igPushItemWidth(115);
std.mem.copy(u8, &rule_label_buf, &rule.name);
if (ogInputText("##name", &rule_label_buf, rule_label_buf.len)) {
std.mem.copy(u8, &rule.name, &rule_label_buf);
}
igPopItemWidth();
igSameLine(0, 4);
if (ogButton("Pattern")) {
igOpenPopup("##pattern_popup");
}
igSameLine(0, 4);
if (ogButton("Result")) {
igOpenPopup("result_popup");
}
igSameLine(0, 4);
igPushItemWidth(50);
var min: u8 = 0;
var max: u8 = 100;
_ = igDragScalar("", ImGuiDataType_U8, &rule.chance, 1, &min, &max, null, 1);
igSameLine(0, 4);
if (ogButton(icons.copy)) {
ruleset.rules.append(rule.clone()) catch unreachable;
}
igSameLine(0, 4);
if (ogButton(icons.trash)) {
return true;
}
// if this is the last item, add an extra drop zone for reordering
if (index == ruleset.rules.items.len - 1) {
rulesDragDrop(index + 1, rule, true, is_pre_rule);
}
// display the popup a bit to the left to center it under the mouse
igSetNextWindowPos(igGetIO().MousePos, ImGuiCond_Appearing, .{ .x = 0.5 });
if (igBeginPopup("##pattern_popup", ImGuiWindowFlags_None)) {
patternPopup(state, rule);
var size = ogGetContentRegionAvail();
if (igButton("Clear", ImVec2{ .x = (size.x - 4) / 1.7 })) {
rule.clearPatternData();
}
igSameLine(0, 4);
if (igButton("...", .{ .x = -1, .y = 0 })) {
igOpenPopup("rules_hamburger");
}
rulesHamburgerPopup(state, rule);
// quick brush selector
if (ogKeyPressed(upaya.sokol.SAPP_KEYCODE_B)) {
if (igIsPopupOpenID(igGetIDStr("##brushes"))) {
igClosePopupToLevel(1, true);
} else {
igOpenPopup("##brushes");
}
}
brushes_win.drawPopup(state, "##brushes");
igEndPopup();
}
igSetNextWindowPos(igGetIO().MousePos, ImGuiCond_Appearing, .{ .x = 0.5 });
if (igBeginPopup("result_popup", ImGuiWindowFlags_NoResize | ImGuiWindowFlags_AlwaysAutoResize)) {
resultPopup(state, rule, is_pre_rule);
igEndPopup();
}
return false;
}
fn patternPopup(state: *ts.AppState, rule: *Rule) void {
igText("Pattern");
igSameLine(0, igGetWindowContentRegionWidth() - 65);
igText(icons.question_circle);
ogUnformattedTooltip(100, "Left Click: select tile and require\nShift + Left Click: select tile and negate\nRight Click: set as empty required\nShift + Right Click: set as empty negated");
const draw_list = igGetWindowDrawList();
const rect_size: f32 = 16;
const pad: f32 = 4;
const canvas_size = 5 * rect_size + 4 * pad;
const thickness: f32 = 2;
var pos = ImVec2{};
igGetCursorScreenPos(&pos);
_ = igInvisibleButton("##pattern_button", ImVec2{ .x = canvas_size, .y = canvas_size });
const mouse_pos = igGetIO().MousePos;
const hovered = igIsItemHovered(ImGuiHoveredFlags_None);
var y: usize = 0;
while (y < 5) : (y += 1) {
var x: usize = 0;
while (x < 5) : (x += 1) {
const pad_x = @intToFloat(f32, x) * pad;
const pad_y = @intToFloat(f32, y) * pad;
const offset_x = @intToFloat(f32, x) * rect_size;
const offset_y = @intToFloat(f32, y) * rect_size;
var tl = ImVec2{ .x = pos.x + pad_x + offset_x, .y = pos.y + pad_y + offset_y };
var rule_tile = rule.get(x, y);
if (rule_tile.tile > 0) {
brushes_win.drawBrush(rect_size, rule_tile.tile - 1, tl);
} else {
// if empty rule or just with a modifier
ogAddQuadFilled(draw_list, tl, rect_size, colors.colorRgb(0, 0, 0));
}
if (x == 2 and y == 2) {
const size = rect_size - thickness;
var tl2 = tl;
tl2.x += 1;
tl2.y += 1;
ogAddQuad(draw_list, tl2, size, colors.pattern_center, thickness);
}
tl.x -= 1;
tl.y -= 1;
if (rule_tile.state == .negated) {
const size = rect_size + thickness;
ogAddQuad(draw_list, tl, size, colors.brush_negated, thickness);
} else if (rule_tile.state == .required) {
const size = rect_size + thickness;
ogAddQuad(draw_list, tl, size, colors.brush_required, thickness);
}
if (hovered) {
if (tl.x <= mouse_pos.x and mouse_pos.x < tl.x + rect_size and tl.y <= mouse_pos.y and mouse_pos.y < tl.y + rect_size) {
if (igIsMouseClicked(ImGuiMouseButton_Left, false)) {
state.map_data_dirty = true;
if (igGetIO().KeyShift) {
rule_tile.negate(state.selected_brush_index + 1);
} else {
rule_tile.require(state.selected_brush_index + 1);
}
}
if (igIsMouseClicked(ImGuiMouseButton_Right, false)) {
state.map_data_dirty = true;
rule_tile.toggleState(if (igGetIO().KeyShift) .negated else .required);
}
}
}
}
}
}
fn rulesHamburgerPopup(state: *ts.AppState, rule: *Rule) void {
igSetNextWindowPos(igGetIO().MousePos, ImGuiCond_Appearing, .{ .x = 0.5 });
if (igBeginPopup("rules_hamburger", ImGuiWindowFlags_None)) {
defer igEndPopup();
state.map_data_dirty = true;
igText("Shift:");
igSameLine(0, 10);
if (ogButton(icons.arrow_left)) {
rule.shift(.left);
}
igSameLine(0, 7);
if (ogButton(icons.arrow_up)) {
rule.shift(.up);
}
igSameLine(0, 7);
if (ogButton(icons.arrow_down)) {
rule.shift(.down);
}
igSameLine(0, 7);
if (ogButton(icons.arrow_right)) {
rule.shift(.right);
}
igText("Flip: ");
igSameLine(0, 10);
if (ogButton(icons.arrows_alt_h)) {
rule.flip(.horizontal);
}
igSameLine(0, 4);
if (ogButton(icons.arrows_alt_v)) {
rule.flip(.vertical);
}
}
}
fn floodFillPopup(state: *ts.AppState, ruleset: *RuleSet) void {
igSetNextWindowPos(igGetIO().MousePos, ImGuiCond_Appearing, .{ .x = 0.5 });
if (igBeginPopup("flood-fill", ImGuiWindowFlags_None)) {
defer igEndPopup();
igText("Directions:");
igSameLine(0, 10);
_ = igSelectableBoolPtr(icons.arrow_left, &fill_dirs.left, ImGuiSelectableFlags_DontClosePopups, .{ .x = 12, .y = 12 });
igSameLine(0, 7);
_ = igSelectableBoolPtr(icons.arrow_down, &fill_dirs.down, ImGuiSelectableFlags_DontClosePopups, .{ .x = 12, .y = 12 });
igSameLine(0, 7);
_ = igSelectableBoolPtr(icons.arrow_right, &fill_dirs.right, ImGuiSelectableFlags_DontClosePopups, .{ .x = 12, .y = 12 });
igSameLine(0, 7);
_ = igSelectableBoolPtr(icons.arrow_up, &fill_dirs.up, ImGuiSelectableFlags_DontClosePopups, .{ .x = 12, .y = 12 });
igSpacing();
var size = ogGetContentRegionAvail();
igSetNextItemWidth(size.x * 0.6);
_ = ogInputText("##nine-slice-name", &new_rule_label_buf, new_rule_label_buf.len);
igSameLine(0, 5);
const label_sentinel_index = std.mem.indexOfScalar(u8, &new_rule_label_buf, 0).?;
const disabled = label_sentinel_index == 0 or !fill_dirs.valid();
if (disabled) {
igPushItemFlag(ImGuiItemFlags_Disabled, true);
igPushStyleVarFloat(ImGuiStyleVar_Alpha, 0.5);
}
if (igButton("Create", ImVec2{ .x = -1, .y = 0 })) {
igCloseCurrentPopup();
state.map_data_dirty = true;
ruleset.addFloodFill(state.selected_brush_index, new_rule_label_buf[0..label_sentinel_index], fill_dirs.left, fill_dirs.right, fill_dirs.up, fill_dirs.down);
}
if (disabled) {
igPopItemFlag();
igPopStyleVar(1);
}
}
}
/// shows the tileset or brush palette allowing multiple tiles to be selected
fn resultPopup(state: *ts.AppState, ruleset: *Rule, is_pre_rule: bool) void {
var content_start_pos = ogGetCursorScreenPos();
const zoom: usize = if (!is_pre_rule and (state.texture.width < 200 and state.texture.height < 200)) 2 else 1;
const tile_spacing = if (is_pre_rule) 0 else state.map.tile_spacing * zoom;
const tile_size = if (is_pre_rule) 32 else state.map.tile_size * zoom;
if (is_pre_rule) {
brushes_win.draw(state, @intToFloat(f32, tile_size), true);
} else {
ogImage(state.texture.imTextureID(), state.texture.width * @intCast(i32, zoom), state.texture.height * @intCast(i32, zoom));
}
const draw_list = igGetWindowDrawList();
// draw selected tiles
var iter = ruleset.result_tiles.iter();
while (iter.next()) |index| {
const per_row = if (is_pre_rule) 6 else state.tilesPerRow();
ts.addTileToDrawList(tile_size, content_start_pos, index, per_row, tile_spacing);
}
// check input for toggling state
if (igIsItemHovered(ImGuiHoveredFlags_None)) {
if (igIsMouseClicked(0, false)) {
var tile = ts.tileIndexUnderMouse(@intCast(usize, tile_size + tile_spacing), content_start_pos);
const per_row = if (is_pre_rule) 6 else state.tilesPerRow();
ruleset.toggleSelected(@intCast(u8, tile.x + tile.y * per_row));
state.map_data_dirty = true;
}
}
if (igButton("Clear", ImVec2{ .x = -1 })) {
ruleset.result_tiles.clear();
state.map_data_dirty = true;
}
}
fn nineSlicePopup(state: *ts.AppState, selection_size: usize) void {
brushes_win.draw(state, 16, false);
igSameLine(0, 5);
var content_start_pos = ogGetCursorScreenPos();
ogImage(state.texture.imTextureID(), state.texture.width, state.texture.height);
const draw_list = igGetWindowDrawList();
if (nine_slice_selected) |index| {
const x = @mod(index, state.tilesPerRow());
const y = @divTrunc(index, state.tilesPerRow());
var tl = ImVec2{ .x = @intToFloat(f32, x) * @intToFloat(f32, state.map.tile_size + state.map.tile_spacing), .y = @intToFloat(f32, y) * @intToFloat(f32, state.map.tile_size + state.map.tile_spacing) };
tl.x += content_start_pos.x + 1 + @intToFloat(f32, state.map.tile_spacing);
tl.y += content_start_pos.y + 1 + @intToFloat(f32, state.map.tile_spacing);
ogAddQuadFilled(draw_list, tl, @intToFloat(f32, (state.map.tile_size + state.map.tile_spacing) * selection_size), colors.rule_result_selected_fill);
ogAddQuad(draw_list, tl, @intToFloat(f32, (state.map.tile_size + state.map.tile_spacing) * selection_size) - 1, colors.rule_result_selected_outline, 2);
}
// check input for toggling state
if (igIsItemHovered(ImGuiHoveredFlags_None)) {
if (igIsMouseClicked(0, false)) {
var tile = ts.tileIndexUnderMouse(@intCast(usize, state.map.tile_size + state.map.tile_spacing), content_start_pos);
// does the nine-slice fit?
if (tile.x + selection_size <= state.tilesPerRow() and tile.y + selection_size <= state.tilesPerCol()) {
nine_slice_selected = @intCast(usize, tile.x + tile.y * state.tilesPerRow());
}
}
}
var size = ogGetContentRegionAvail();
igSetNextItemWidth(size.x * 0.6);
_ = ogInputText("##nine-slice-name", &new_rule_label_buf, new_rule_label_buf.len);
igSameLine(0, 5);
const label_sentinel_index = std.mem.indexOfScalar(u8, &new_rule_label_buf, 0).?;
const disabled = label_sentinel_index == 0 or nine_slice_selected == null;
if (disabled) {
igPushItemFlag(ImGuiItemFlags_Disabled, true);
igPushStyleVarFloat(ImGuiStyleVar_Alpha, 0.5);
}
if (igButton("Create", ImVec2{ .x = -1, .y = 0 })) {
if (selection_size == 3) {
state.map.ruleset.addNinceSliceRules(&state.map, state.tilesPerRow(), state.selected_brush_index, new_rule_label_buf[0..label_sentinel_index], nine_slice_selected.?);
} else {
state.map.ruleset.addInnerFourRules(&state.map, state.tilesPerRow(), state.selected_brush_index, new_rule_label_buf[0..label_sentinel_index], nine_slice_selected.?);
}
state.map_data_dirty = true;
igCloseCurrentPopup();
}
if (disabled) {
igPopItemFlag();
igPopStyleVar(1);
}
} | tilescript/windows/rules.zig |
const std = @import("std");
// TODO: Revectorize, brainstorm new method
fn dct(comptime T: type, samples: []const T, index: T) T {
var n: usize = 0;
var sum: T = 0;
while (n < samples.len) : (n += 1) {
sum += samples[n] * @cos((std.math.pi / @intToFloat(T, samples.len)) * (@intToFloat(T, n) + 0.5) * index);
}
return sum;
}
pub fn main() !void {
const T = f32;
const allocator = std.heap.page_allocator;
var raw = try std.fs.cwd().openFile("dct.raw", .{});
defer raw.close();
var out = try std.fs.cwd().createFile("myaudio.zsa", .{});
defer out.close();
const reader = raw.reader();
var SAMPLE: usize = 10;
var samples = try std.ArrayList(T).initCapacity(allocator, @divTrunc((try raw.stat()).size, SAMPLE) + 1);
// var z: usize = 0;
while (true) {
try samples.append(@intToFloat(T, @bitCast(i8, reader.readByte() catch break)));
reader.skipBytes(SAMPLE - 1, .{}) catch break;
}
// const block_size = 64;
const N = samples.items.len;
// while (samples.items.len % block_size != 0) try samples.append(0);
// var coeffs_final = try std.ArrayList(T).initCapacity(allocator, N);
try out.writer().writeIntLittle(u32, @intCast(u32, N));
var coeff_index: usize = 0;
var zeroes: u8 = 0;
while (coeff_index < N) : (coeff_index += 1) {
var d = dct(T, samples.items, @intToFloat(T, coeff_index));
if (@fabs(d) <= 10) d = 0;
const final = @floatToInt(i24, @round(d));
if (final == 0) {
zeroes += 1;
} else {
if (zeroes != 0) {
try out.writer().writeByte(0);
try out.writer().writeByte(zeroes);
zeroes = 0;
}
try out.writer().writeByte(1);
try out.writer().writeIntLittle(i24, final);
}
// try std.io.getStdOut().writer().print("{d}, ", .{final});
// try coeffs_final.append(@round(d));
}
if (zeroes != 0) {
try out.writer().writeByte(0);
try out.writer().writeByte(zeroes);
zeroes = 0;
}
// try std.io.getStdOut().writer().print("{d}\n", .{coeffs_final.items[0..N]});
} | src/encoder.zig |
const std = @import("std");
const print = std.debug.print;
var gpa = std.heap.GeneralPurposeAllocator(.{}){};
const alloc = &gpa.allocator;
const MemMap = std.AutoHashMap(usize, usize);
pub fn main() !void {
defer _ = gpa.deinit();
const inputData = try std.fs.cwd().readFileAlloc(alloc, "input", std.math.maxInt(u64));
defer alloc.free(inputData);
const p1 = part1(inputData);
const p2 = part2(inputData);
std.debug.print("{}\n", .{p1});
std.debug.print("{}\n", .{p2});
}
fn part1(inputData: []const u8) !usize {
var lines = std.mem.split(inputData, "\n");
var and_mask: usize = 0;
var or_mask: usize = 0;
var memory = MemMap.init(alloc);
defer memory.deinit();
while (lines.next()) |line| {
if (std.mem.eql(u8, line[0..3], "mas")) {
const mask = line[7..];
std.debug.assert(mask.len == 36);
and_mask = 0;
or_mask = 0;
for (mask) |bit| {
and_mask <<= 1;
or_mask <<=1;
switch (bit) {
'X' => {
and_mask += 1;
},
'1' => {
and_mask += 1;
or_mask += 1;
},
'0' => {
},
else => @panic("HELP"),
}
}
} else if (std.mem.eql(u8, line[0..3], "mem")) {
const start = std.mem.indexOf(u8, line, "[").? + 1;
const end = std.mem.indexOf(u8, line, "]").?;
const eql = std.mem.indexOf(u8, line, "=").?;
const mem_loc = try std.fmt.parseInt(usize, line[start..end], 10);
var value = try std.fmt.parseInt(usize, line[eql + 2..], 10);
value |= or_mask;
value &= and_mask;
try memory.put(mem_loc, value);
} else {
print("LINE: {}\n", .{line});
@panic("Unknown command");
}
}
var it = memory.iterator();
var sum: usize = 0;
while (it.next()) |loc| {
sum += loc.value;
}
return sum;
}
fn part2(inputData: []const u8) !usize {
var lines = std.mem.split(inputData, "\n");
var and_mask: usize = 0;
var or_mask: usize = 0;
var memory = MemMap.init(alloc);
defer memory.deinit();
var masks = std.ArrayList(usize).init(alloc);
defer masks.deinit();
try masks.append(0);
var x_mask: usize = 0; // where the x's are
while (lines.next()) |line| {
if (std.mem.eql(u8, line[0..3], "mas")) {
// print("Mask: {}\n", .{line[7..]});
try masks.resize(1);
x_mask = 0;
masks.items[0] = 0;
const mask = line[7..];
std.debug.assert(mask.len == 36);
for (mask) |bit| {
for (masks.items) |*el| {
el.* <<= 1;
}
x_mask <<= 1;
switch (bit) {
'X' => {
const cur_len = masks.items.len;
var i: usize = 0;
while (i < cur_len) : (i += 1) {
try masks.append(masks.items[i]); // append a "zero" version
masks.items[i] += 1; // make this a "1" version
}
x_mask += 1;
},
'1' => {
for (masks.items) |*m| {
m.* += 1;
}
},
'0' => {
},
else => @panic("HELP"),
}
}
// print("X_MA: {b:0>36}\n", .{x_mask});
// print("N_MA: {b:0>36}\n", .{~x_mask & 0x0000000FFFFFFFFF});
} else if (std.mem.eql(u8, line[0..3], "mem")) {
const start = std.mem.indexOf(u8, line, "[").? + 1;
const end = std.mem.indexOf(u8, line, "]").?;
const eql = std.mem.indexOf(u8, line, "=").?;
var mem_loc = try std.fmt.parseInt(usize, line[start..end], 10);
// ("Mem loc: {}\n", .{mem_loc});
// print("Mem loc x: {}\n", .{mem_loc & ~x_mask});
var value = try std.fmt.parseInt(usize, line[eql + 2..], 10);
// print("N_XMSK: {b:0>36}\n", .{~x_mask & 0x0000000FFFFFFFFF});
// print("MEMLOC: {b:0>36}\n", .{mem_loc});
mem_loc &= ~x_mask;
// print("NEWMEM: {b:0>36}\n", .{mem_loc});
for (masks.items) |m| {
const new_mem_loc = mem_loc | m;
try memory.put(new_mem_loc, value);
}
} else {
print("LINE: {}\n", .{line});
@panic("Unknown command");
}
}
var it = memory.iterator();
var sum: usize = 0;
while (it.next()) |loc| {
sum += loc.value;
}
return sum;
} | Day14/day14.zig |
// DO NOT MODIFY. This is not actually a source file; it is a textual representation of generated code.
// Use only for debugging purposes.
// Auto-generated constructor
// Access: public
Method <init> : V
(
// (no arguments)
) {
ALOAD 0
// Method descriptor: ()V
INVOKESPECIAL java/lang/Object#<init>
RETURN
}
// Access: public
Method deploy_0 : V
(
arg 1 = Lio/quarkus/runtime/StartupContext;,
arg 2 = [Ljava/lang/Object;
) {
** label1
// Field descriptor: Lio/quarkus/runtime/generated/RunTimeConfigRoot;
GETSTATIC io/quarkus/runtime/generated/RunTimeConfig#runConfig
// Field descriptor: Ljava/lang/Object;
GETFIELD io/quarkus/runtime/generated/RunTimeConfigRoot#vertx
ASTORE 3
ALOAD 2
LDC (Integer) 1
ALOAD 3
AASTORE
NEW io/quarkus/vertx/core/runtime/VertxCoreRecorder
DUP
// Method descriptor: ()V
INVOKESPECIAL io/quarkus/vertx/core/runtime/VertxCoreRecorder#<init>
ASTORE 4
ALOAD 2
LDC (Integer) 0
ALOAD 4
AASTORE
ALOAD 1
LDC (String) "proxykey40"
// Method descriptor: (Ljava/lang/String;)Ljava/lang/Object;
INVOKEVIRTUAL io/quarkus/runtime/StartupContext#getValue
ASTORE 8
ALOAD 2
LDC (Integer) 1
AALOAD
ASTORE 7
LDC (String) "NORMAL"
// Method descriptor: (Ljava/lang/String;)Lio/quarkus/runtime/LaunchMode;
INVOKESTATIC io/quarkus/runtime/LaunchMode#valueOf
ASTORE 5
ALOAD 1
LDC (String) "io.quarkus.runtime.ShutdownContext"
// Method descriptor: (Ljava/lang/String;)Ljava/lang/Object;
INVOKEVIRTUAL io/quarkus/runtime/StartupContext#getValue
ASTORE 6
ALOAD 2
LDC (Integer) 0
AALOAD
CHECKCAST io/quarkus/vertx/core/runtime/VertxCoreRecorder
ALOAD 8
CHECKCAST io/quarkus/arc/runtime/BeanContainer
ALOAD 7
CHECKCAST io/quarkus/vertx/core/runtime/config/VertxConfiguration
ALOAD 5
ALOAD 6
CHECKCAST io/quarkus/runtime/ShutdownContext
// Method descriptor: (Lio/quarkus/arc/runtime/BeanContainer;Lio/quarkus/vertx/core/runtime/config/VertxConfiguration;Lio/quarkus/runtime/LaunchMode;Lio/quarkus/runtime/ShutdownContext;)Ljava/util/function/Supplier;
INVOKEVIRTUAL io/quarkus/vertx/core/runtime/VertxCoreRecorder#configureVertx
ASTORE 9
ALOAD 1
LDC (String) "proxykey49"
ALOAD 9
// Method descriptor: (Ljava/lang/String;Ljava/lang/Object;)V
INVOKEVIRTUAL io/quarkus/runtime/StartupContext#putValue
RETURN
** label2
}
// Access: public
Method deploy : V
(
arg 1 = Lio/quarkus/runtime/StartupContext;
) {
** label1
LDC (Integer) 2
ANEWARRAY java/lang/Object
ASTORE 2
ALOAD 0
ALOAD 1
ALOAD 2
// Method descriptor: (Lio/quarkus/runtime/StartupContext;[Ljava/lang/Object;)V
INVOKEVIRTUAL io/quarkus/deployment/steps/VertxCoreProcessor$build22#deploy_0
RETURN
** label2
} | localproxyservice/target/generated-sources/gizmo/io/quarkus/deployment/steps/VertxCoreProcessor$build22.zig |
const GBA = @import("core.zig").GBA;
pub const Input = struct {
var previousInput: u16 = 0;
var currentInput: u16 = 0;
pub const Keys = struct {
pub const A = 1 << 0;
pub const B = 1 << 1;
pub const Select = 1 << 2;
pub const Start = 1 << 3;
pub const Right = 1 << 4;
pub const Left = 1 << 5;
pub const Up = 1 << 6;
pub const Down = 1 << 7;
pub const R = 1 << 8;
pub const L = 1 << 9;
};
pub const KeyIndex = enum {
A,
B,
Select,
Start,
Right,
Left,
Up,
Down,
R,
L,
Count,
};
pub fn readInput() void {
previousInput = currentInput;
currentInput = ~GBA.REG_KEYINPUT.*;
}
pub fn isKeyDown(keys: u16) callconv(.Inline) bool {
return (currentInput & keys) == keys;
}
pub fn isKeyHeld(keys: u16) callconv(.Inline) bool {
return ((previousInput & currentInput) & keys) == keys;
}
pub fn isKeyJustPressed(keys: u16) callconv(.Inline) bool {
return ((~previousInput & currentInput) & keys) == keys;
}
pub fn isKeyJustReleased(keys: u16) callconv(.Inline) bool {
return ((previousInput & ~currentInput) & keys) == keys;
}
pub fn isKeyUp(keys: u16) callconv(.Inline) bool {
return (currentInput & keys) == 0;
}
pub fn getHorizontal() callconv(.Inline) i32 {
return triState(currentInput, KeyIndex.Left, KeyIndex.Right);
}
pub fn getVertical() callconv(.Inline) i32 {
return triState(currentInput, KeyIndex.Up, KeyIndex.Down);
}
pub fn getShoulder() callconv(.Inline) i32 {
return triState(currentInput, KeyIndex.L, KeyIndex.R);
}
pub fn getShoulderJustPressed() callconv(.Inline) i32 {
return triState((~previousInput & currentInput), KeyIndex.L, KeyIndex.R);
}
pub fn triState(input: u16, minus: KeyIndex, plus: KeyIndex) callconv(.Inline) i32 {
return ((@intCast(i32, input) >> @intCast(u5, @enumToInt(plus))) & 1) - ((@intCast(i32, input) >> @intCast(u5, @enumToInt(minus))) & 1);
}
}; | GBA/input.zig |
const std = @import("../index.zig");
const builtin = @import("builtin");
const Lock = std.event.Lock;
const Loop = std.event.Loop;
const AtomicRmwOp = builtin.AtomicRmwOp;
const AtomicOrder = builtin.AtomicOrder;
const testing = std.testing;
/// ReturnType must be `void` or `E!void`
pub fn Group(comptime ReturnType: type) type {
return struct {
coro_stack: Stack,
alloc_stack: Stack,
lock: Lock,
const Self = @This();
const Error = switch (@typeInfo(ReturnType)) {
builtin.TypeId.ErrorUnion => |payload| payload.error_set,
else => void,
};
const Stack = std.atomic.Stack(promise->ReturnType);
pub fn init(loop: *Loop) Self {
return Self{
.coro_stack = Stack.init(),
.alloc_stack = Stack.init(),
.lock = Lock.init(loop),
};
}
/// Cancel all the outstanding promises. Can be called even if wait was already called.
pub fn deinit(self: *Self) void {
while (self.coro_stack.pop()) |node| {
cancel node.data;
}
while (self.alloc_stack.pop()) |node| {
cancel node.data;
self.lock.loop.allocator.destroy(node);
}
}
/// Add a promise to the group. Thread-safe.
pub fn add(self: *Self, handle: promise->ReturnType) (error{OutOfMemory}!void) {
const node = try self.lock.loop.allocator.create(Stack.Node);
node.* = Stack.Node{
.next = undefined,
.data = handle,
};
self.alloc_stack.push(node);
}
/// Add a node to the group. Thread-safe. Cannot fail.
/// `node.data` should be the promise handle to add to the group.
/// The node's memory should be in the coroutine frame of
/// the handle that is in the node, or somewhere guaranteed to live
/// at least as long.
pub fn addNode(self: *Self, node: *Stack.Node) void {
self.coro_stack.push(node);
}
/// This is equivalent to an async call, but the async function is added to the group, instead
/// of returning a promise. func must be async and have return type ReturnType.
/// Thread-safe.
pub fn call(self: *Self, comptime func: var, args: ...) (error{OutOfMemory}!void) {
const S = struct {
async fn asyncFunc(node: **Stack.Node, args2: ...) ReturnType {
// TODO this is a hack to make the memory following be inside the coro frame
suspend {
var my_node: Stack.Node = undefined;
node.* = &my_node;
resume @handle();
}
// TODO this allocation elision should be guaranteed because we await it in
// this coro frame
return await (async func(args2) catch unreachable);
}
};
var node: *Stack.Node = undefined;
const handle = try async<self.lock.loop.allocator> S.asyncFunc(&node, args);
node.* = Stack.Node{
.next = undefined,
.data = handle,
};
self.coro_stack.push(node);
}
/// Wait for all the calls and promises of the group to complete.
/// Thread-safe.
/// Safe to call any number of times.
pub async fn wait(self: *Self) ReturnType {
// TODO catch unreachable because the allocation can be grouped with
// the coro frame allocation
const held = await (async self.lock.acquire() catch unreachable);
defer held.release();
while (self.coro_stack.pop()) |node| {
if (Error == void) {
await node.data;
} else {
(await node.data) catch |err| {
self.deinit();
return err;
};
}
}
while (self.alloc_stack.pop()) |node| {
const handle = node.data;
self.lock.loop.allocator.destroy(node);
if (Error == void) {
await handle;
} else {
(await handle) catch |err| {
self.deinit();
return err;
};
}
}
}
};
}
test "std.event.Group" {
// https://github.com/ziglang/zig/issues/1908
if (builtin.single_threaded) return error.SkipZigTest;
var da = std.heap.DirectAllocator.init();
defer da.deinit();
const allocator = &da.allocator;
var loop: Loop = undefined;
try loop.initMultiThreaded(allocator);
defer loop.deinit();
const handle = try async<allocator> testGroup(&loop);
defer cancel handle;
loop.run();
}
async fn testGroup(loop: *Loop) void {
var count: usize = 0;
var group = Group(void).init(loop);
group.add(async sleepALittle(&count) catch @panic("memory")) catch @panic("memory");
group.call(increaseByTen, &count) catch @panic("memory");
await (async group.wait() catch @panic("memory"));
testing.expect(count == 11);
var another = Group(anyerror!void).init(loop);
another.add(async somethingElse() catch @panic("memory")) catch @panic("memory");
another.call(doSomethingThatFails) catch @panic("memory");
testing.expectError(error.ItBroke, await (async another.wait() catch @panic("memory")));
}
async fn sleepALittle(count: *usize) void {
std.os.time.sleep(1 * std.os.time.millisecond);
_ = @atomicRmw(usize, count, AtomicRmwOp.Add, 1, AtomicOrder.SeqCst);
}
async fn increaseByTen(count: *usize) void {
var i: usize = 0;
while (i < 10) : (i += 1) {
_ = @atomicRmw(usize, count, AtomicRmwOp.Add, 1, AtomicOrder.SeqCst);
}
}
async fn doSomethingThatFails() anyerror!void {}
async fn somethingElse() anyerror!void {
return error.ItBroke;
} | std/event/group.zig |
const std = @import("std");
const pcx = @import("pcx.zig");
var mem: [1000 * 1024]u8 = undefined;
var gfa = std.heap.FixedBufferAllocator.init(&mem);
fn testLoadComptime(
comptime branch_quota: comptime_int,
comptime basename: []const u8,
comptime indexed: bool,
) void {
comptime {
@setEvalBranchQuota(branch_quota);
const pcxfile = @embedFile("testdata/" ++ basename ++ ".pcx");
var fbs = std.io.fixedBufferStream(pcxfile);
var reader = fbs.reader();
const preloaded = try pcx.preload(reader);
const width: usize = preloaded.width;
const height: usize = preloaded.height;
if (indexed) {
var pixels: [width * height]u8 = undefined;
var palette: [768]u8 = undefined;
try pcx.loadIndexed(reader, preloaded, &pixels, &palette);
try std.testing.expect(std.mem.eql(
u8,
&pixels,
@embedFile("testdata/" ++ basename ++ "-raw-indexed.data"),
));
try std.testing.expect(std.mem.eql(
u8,
&palette,
@embedFile("testdata/" ++ basename ++ "-raw-indexed.data.pal"),
));
} else {
var pixels: [width * height * 3]u8 = undefined;
try pcx.loadRGB(reader, preloaded, &pixels);
try std.testing.expect(std.mem.eql(
u8,
&pixels,
@embedFile("testdata/" ++ basename ++ "-raw-r8g8b8.data"),
));
}
}
}
fn testLoadRuntime(comptime basename: []const u8, indexed: bool) !void {
defer gfa.end_index = 0;
const pcxfile = @embedFile("testdata/" ++ basename ++ ".pcx");
var reader = std.io.fixedBufferStream(pcxfile).reader();
const preloaded = try pcx.preload(reader);
const width: usize = preloaded.width;
const height: usize = preloaded.height;
if (indexed) {
var pixels = try gfa.allocator.alloc(u8, width * height);
var palette: [768]u8 = undefined;
try pcx.loadIndexed(reader, preloaded, pixels, &palette);
try std.testing.expect(std.mem.eql(
u8,
pixels,
@embedFile("testdata/" ++ basename ++ "-raw-indexed.data"),
));
try std.testing.expect(std.mem.eql(
u8,
&palette,
@embedFile("testdata/" ++ basename ++ "-raw-indexed.data.pal"),
));
} else {
var rgb = try gfa.allocator.alloc(u8, width * height * 3);
try pcx.loadRGB(reader, preloaded, rgb);
try std.testing.expect(std.mem.eql(
u8,
rgb,
@embedFile("testdata/" ++ basename ++ "-raw-r8g8b8.data"),
));
}
}
test "load space_merc.pcx indexed comptime" {
testLoadComptime(20000, "space_merc", true);
}
test "load space_merc.pcx rgb comptime" {
testLoadComptime(20000, "space_merc", false);
}
test "load space_merc.pcx indexed runtime" {
try testLoadRuntime("space_merc", true);
}
test "load space_merc.pcx rgb runtime" {
try testLoadRuntime("space_merc", false);
}
// comptime loading is slow so skip these tests
test "load lena64.pcx indexed comptime" {
if (true) return error.SkipZigTest;
testLoadComptime(100000, "lena64", true);
}
test "load lena128.pcx indexed comptime" {
if (true) return error.SkipZigTest;
testLoadComptime(200000, "lena128", true);
}
test "load lena256.pcx indexed comptime" {
if (true) return error.SkipZigTest;
testLoadComptime(500000, "lena256", true);
}
// this one crashes after 20 seconds with the message "fork failed"
test "load lena512.pcx indexed comptime" {
if (true) return error.SkipZigTest;
testLoadComptime(20000000, "lena512", true);
}
test "load lena512.pcx indexed runtime" {
try testLoadRuntime("lena512", true);
}
test "load lena512.pcx rgb runtime" {
try testLoadRuntime("lena512", false);
}
// note: these resized lena images are not very useful for testing the loader
// (especially since they have even dimensions and as photos they are not
// suited for RLE), but they are useful for benchmarking, which i want to do
// eventually
test "load lena256.pcx indexed runtime" {
try testLoadRuntime("lena256", true);
}
test "load lena256.pcx rgb runtime" {
try testLoadRuntime("lena256", false);
}
test "load lena128.pcx indexed runtime" {
try testLoadRuntime("lena128", true);
}
test "load lena128.pcx rgb runtime" {
try testLoadRuntime("lena128", false);
}
test "load lena64.pcx indexed runtime" {
try testLoadRuntime("lena64", true);
}
test "load lena64.pcx rgb runtime" {
try testLoadRuntime("lena64", false);
}
fn testSave(comptime basename: []const u8, w: usize, h: usize) !void {
const pcxfile = @embedFile("testdata/" ++ basename ++ ".pcx");
var outbuf: [pcxfile.len]u8 = undefined;
var fbs = std.io.fixedBufferStream(&outbuf);
try pcx.saveIndexed(
fbs.writer(),
w,
h,
@embedFile("testdata/" ++ basename ++ "-raw-indexed.data"),
@embedFile("testdata/" ++ basename ++ "-raw-indexed.data.pal"),
);
const result = fbs.getWritten();
try std.testing.expect(
std.mem.eql(u8, result[0..12], pcxfile[0..12]) and
// skip hres, vres, reserved
std.mem.eql(u8, result[65..70], pcxfile[65..70]) and
// skip padding
std.mem.eql(u8, result[128..], pcxfile[128..]),
);
}
test "save space_merc.pcx comptime" {
comptime {
@setEvalBranchQuota(20000);
try testSave("space_merc", 32, 32);
}
}
test "save lena64.pcx comptime" {
if (true) return error.SkipZigTest;
comptime {
@setEvalBranchQuota(100000);
try testSave("lena64", 64, 64);
}
}
test "save lena128.pcx comptime" {
if (true) return error.SkipZigTest;
comptime {
@setEvalBranchQuota(500000);
try testSave("lena128", 128, 128);
}
}
// this one crashes with "fork failed"
test "save lena256.pcx comptime" {
if (true) return error.SkipZigTest;
comptime {
@setEvalBranchQuota(2000000);
try testSave("lena256", 256, 256);
}
}
// haven't even tried this one
test "save lena512.pcx comptime" {
if (true) return error.SkipZigTest;
comptime {
@setEvalBranchQuota(10000000);
try testSave("lena512", 512, 512);
}
}
test "save space_merc.pcx runtime" {
try testSave("space_merc", 32, 32);
}
test "save lena64.pcx runtime" {
try testSave("lena64", 64, 64);
}
test "save lena128.pcx runtime" {
try testSave("lena128", 128, 128);
}
test "save lena256.pcx runtime" {
try testSave("lena256", 256, 256);
}
test "save lena512.pcx runtime" {
try testSave("lena512", 512, 512);
} | pcx_test.zig |
const url = @import("./url.zig");
const std = @import("std");
const mem = std.mem;
const warn = std.debug.warn;
const Buffer = std.Buffer;
const debug = std.debug;
const UserInfo = url.UserInfo;
const testing = std.testing;
const URL = url.URL;
const EscapeTest = struct {
in: []const u8,
out: []const u8,
err: ?url.Error,
};
const unescapePassingTests = [_]EscapeTest{
EscapeTest{
.in = "",
.out = "",
.err = null,
},
EscapeTest{
.in = "1%41",
.out = "1A",
.err = null,
},
EscapeTest{
.in = "1%41%42%43",
.out = "1ABC",
.err = null,
},
EscapeTest{
.in = "%4a",
.out = "J",
.err = null,
},
EscapeTest{
.in = "%6F",
.out = "o",
.err = null,
},
EscapeTest{
.in = "a+b",
.out = "a b",
.err = null,
},
EscapeTest{
.in = "a%20b",
.out = "a b",
.err = null,
},
};
const unescapeFailingTests = [_]EscapeTest{
EscapeTest{
.in = "%",
.out = "",
.err = url.Error.EscapeError,
},
EscapeTest{
.in = "%a",
.out = "",
.err = url.Error.EscapeError,
},
EscapeTest{
.in = "%1",
.out = "",
.err = url.Error.EscapeError,
},
EscapeTest{
.in = "123%45%6",
.out = "",
.err = url.Error.EscapeError,
},
EscapeTest{
.in = "%zzzzz",
.out = "",
.err = url.Error.EscapeError,
},
};
test "QueryUnEscape" {
var buffer = try std.Buffer.init(debug.global_allocator, "");
var buf = &buffer;
defer buf.deinit();
for (unescapePassingTests) |ts| {
try url.queryUnescape(buf, ts.in);
testing.expectEqualSlices(u8, ts.out, buf.toSlice());
buf.shrink(0);
}
for (unescapeFailingTests) |ts| {
if (ts.err) |err| {
testing.expectError(err, url.queryUnescape(buf, ts.in));
}
buf.shrink(0);
}
}
const queryEscapeTests = [_]EscapeTest{
EscapeTest{
.in = "",
.out = "",
.err = null,
},
EscapeTest{
.in = "abc",
.out = "abc",
.err = null,
},
EscapeTest{
.in = "one two",
.out = "one+two",
.err = null,
},
EscapeTest{
.in = "10%",
.out = "10%25",
.err = null,
},
EscapeTest{
.in = " ?&=#+%!<>#\"{}|\\^[]`☺\t:/@$'()*,;",
.out = "+%3F%26%3D%23%2B%25%21%3C%3E%23%22%7B%7D%7C%5C%5E%5B%5D%60%E2%98%BA%09%3A%2F%40%24%27%28%29%2A%2C%3B",
.err = null,
},
};
test "QueryEscape" {
var buffer = try std.Buffer.init(debug.global_allocator, "");
var buf = &buffer;
defer buf.deinit();
for (queryEscapeTests) |ts| {
try url.queryEscape(buf, ts.in);
testing.expectEqualSlices(u8, ts.out, buf.toSlice());
try buf.resize(0);
try url.queryUnescape(buf, ts.out);
testing.expectEqualSlices(u8, ts.in, buf.toSlice());
try buf.resize(0);
}
}
const pathEscapeTests = [_]EscapeTest{
EscapeTest{
.in = "",
.out = "",
.err = null,
},
EscapeTest{
.in = "abc",
.out = "abc",
.err = null,
},
EscapeTest{
.in = "abc+def",
.out = "abc+def",
.err = null,
},
EscapeTest{
.in = "one two",
.out = "one%20two",
.err = null,
},
EscapeTest{
.in = "10%",
.out = "10%25",
.err = null,
},
EscapeTest{
.in = " ?&=#+%!<>#\"{}|\\^[]`☺\t:/@$'()*,;",
.out = "%20%3F&=%23+%25%21%3C%3E%23%22%7B%7D%7C%5C%5E%5B%5D%60%E2%98%BA%09:%2F@$%27%28%29%2A%2C%3B",
.err = null,
},
};
test "PathEscape" {
var buffer = try std.Buffer.init(debug.global_allocator, "");
var buf = &buffer;
defer buf.deinit();
for (pathEscapeTests) |ts| {
try url.pathEscape(buf, ts.in);
testing.expectEqualSlices(u8, ts.out, buf.toSlice());
try buf.resize(0);
try url.pathUnescape(buf, ts.out);
testing.expectEqualSlices(u8, ts.in, buf.toSlice());
try buf.resize(0);
}
}
const TestURL = struct {
scheme: ?[]const u8,
opaque: ?[]const u8,
user: ?UserInfo,
host: ?[]const u8,
path: ?[]const u8,
raw_path: ?[]const u8,
force_query: ?bool,
raw_query: ?[]const u8,
fragment: ?[]const u8,
fn init(
scheme: ?[]const u8,
opaque: ?[]const u8,
user: ?UserInfo,
host: ?[]const u8,
path: ?[]const u8,
raw_path: ?[]const u8,
force_query: ?bool,
raw_query: ?[]const u8,
fragment: ?[]const u8,
) TestURL {
return TestURL{
.scheme = scheme,
.opaque = opaque,
.user = user,
.host = host,
.path = path,
.raw_path = raw_path,
.force_query = force_query,
.raw_query = raw_query,
.fragment = fragment,
};
}
};
const URLTest = struct {
in: []const u8,
out: TestURL,
round_trip: ?[]const u8,
fn init(
in: []const u8,
out: TestURL,
round_trip: ?[]const u8,
) URLTest {
return URLTest{
.in = in,
.out = out,
.round_trip = round_trip,
};
}
};
const url_tests = [_]URLTest{
// no path
URLTest.init("http://www.google.com", TestURL.init("http", null, null, "www.google.com", null, null, null, null, null), null),
// path
URLTest.init("http://www.google.com/", TestURL.init("http", null, null, "www.google.com", "/", null, null, null, null), null),
// path with hex escaping
URLTest.init("http://www.google.com/file%20one%26two", TestURL.init("http", null, null, "www.google.com", "/file one&two", "/file%20one%26two", null, null, null), null),
// user
URLTest.init("ftp://[email protected]/", TestURL.init("ftp", null, UserInfo.init("webmaster"), "www.google.com", "/", null, null, null, null), null),
// escape sequence in username
URLTest.init("ftp://john%[email protected]/", TestURL.init("ftp", null, UserInfo.init("<NAME>"), "www.google.com", "/", null, null, null, null), "ftp://john%[email protected]/"),
// empty query
URLTest.init("http://www.google.com/?", TestURL.init("http", null, null, "www.google.com", "/", null, true, null, null), null),
// query ending in question mark (Issue 14573)
URLTest.init("http://www.google.com/?foo=bar?", TestURL.init("http", null, null, "www.google.com", "/", null, null, "foo=bar?", null), null),
// query
URLTest.init("http://www.google.com/?q=go+language", TestURL.init("http", null, null, "www.google.com", "/", null, null, "q=go+language", null), null),
// query with hex escaping: NOT parsed
URLTest.init("http://www.google.com/?q=go%20language", TestURL.init("http", null, null, "www.google.com", "/", null, null, "q=go%20language", null), null),
// %20 outside query
URLTest.init("http://www.google.com/a%20b?q=c+d", TestURL.init("http", null, null, "www.google.com", "/a b", null, null, "q=c+d", null), null),
// path without leading /, so no parsing
URLTest.init("http:www.google.com/?q=go+language", TestURL.init("http", "www.google.com/", null, null, null, null, null, "q=go+language", null), "http:www.google.com/?q=go+language"),
// path without leading /, so no parsing
URLTest.init("http:%2f%2fwww.google.com/?q=go+language", TestURL.init("http", "%2f%2fwww.google.com/", null, null, null, null, null, "q=go+language", null), "http:%2f%2fwww.google.com/?q=go+language"),
// non-authority with path
URLTest.init("mailto:/<EMAIL>", TestURL.init("mailto", null, null, null, "/<EMAIL>", null, null, null, null), "mailto:///<EMAIL>"),
// non-authority
URLTest.init("mailto:<EMAIL>", TestURL.init("mailto", "<EMAIL>", null, null, null, null, null, null, null), null),
// unescaped :// in query should not create a scheme
URLTest.init("/foo?query=http://bad", TestURL.init(null, null, null, null, "/foo", null, null, "query=http://bad", null), null),
// leading // without scheme should create an authority
URLTest.init("//foo", TestURL.init(null, null, null, "foo", null, null, null, null, null), null),
// leading // without scheme, with userinfo, path, and query
URLTest.init("//user@foo/path?a=b", TestURL.init(null, null, UserInfo.init("user"), "foo", "/path", null, null, "a=b", null), null),
// Three leading slashes isn't an authority, but doesn't return an error.
// (We can't return an error, as this code is also used via
// ServeHTTP -> ReadRequest -> Parse, which is arguably a
// different URL parsing context, but currently shares the
// same codepath)
URLTest.init("///threeslashes", TestURL.init(null, null, null, null, "///threeslashes", null, null, null, null), null),
URLTest.init("http://user:[email protected]", TestURL.init("http", null, UserInfo.initWithPassword("user", "password"), "google.com", null, null, null, null, null), "http://user:[email protected]"),
// unescaped @ in username should not confuse host
URLTest.init("http://j@ne:[email protected]", TestURL.init("http", null, UserInfo.initWithPassword("<PASSWORD>", "password"), "google.com", null, null, null, null, null), "http://j%40ne:[email protected]"),
// unescaped @ in password should not confuse host
URLTest.init("http://jane:p@[email protected]", TestURL.init("http", null, UserInfo.initWithPassword("<PASSWORD>", "<PASSWORD>"), "google.com", null, null, null, null, null), "http://jane:p%[email protected]"),
URLTest.init("http://j@ne:[email protected]/p@th?q=@go", TestURL.init("http", null, UserInfo.initWithPassword("<PASSWORD>", "password"), "google.com", "/p@th", null, null, "q=@go", null), "http://j%40ne:[email protected]/p@th?q=@go"),
URLTest.init("http://www.google.com/?q=go+language#foo", TestURL.init("http", null, null, "www.google.com", "/", null, null, "q=go+language", "foo"), null),
URLTest.init("http://www.google.com/?q=go+language#foo%26bar", TestURL.init("http", null, null, "www.google.com", "/", null, null, "q=go+language", "foo&bar"), "http://www.google.com/?q=go+language#foo&bar"),
URLTest.init("file:///home/adg/rabbits", TestURL.init("file", null, null, "", "/home/adg/rabbits", null, null, null, null), "file:///home/adg/rabbits"),
// "Windows" paths are no exception to the rule.
// See golang.org/issue/6027, especially comment #9.
URLTest.init("file:///C:/FooBar/Baz.txt", TestURL.init("file", null, null, "", "/C:/FooBar/Baz.txt", null, null, null, null), "file:///C:/FooBar/Baz.txt"),
// case-insensitive scheme
// URLTest.init("MaIlTo:<EMAIL>", TestURL.init("mailto", "<EMAIL>", null, null, null, null, null, null, null), "mailto:<EMAIL>"),
// Relative path
URLTest.init("a/b/c", TestURL.init(null, null, null, null, "a/b/c", null, null, null, null), "a/b/c"),
// escaped '?' in username and password
// URLTest.init("http://%3Fam:pa%[email protected]", TestURL.init("http", null, UserInfo.initWithPassword("?am", "<PASSWORD>"), "google.com", null, null, null, null, null), ""),
};
test "URL.parse" {
var allocator = std.debug.global_allocator;
var buf = &try Buffer.init(allocator, "");
defer buf.deinit();
for (url_tests) |ts, i| {
var u = &try url.parse(allocator, ts.in);
try compare(ts.in, &ts.out, &u.url);
try u.url.encode(buf);
if (ts.round_trip) |expect| {
testing.expectEqualSlices(u8, expect, buf.toSlice());
} else {
testing.expectEqualSlices(u8, ts.in, buf.toSlice());
}
u.deinit();
}
}
const test_failed = error.TestFailed;
fn equal(a: []const u8, b: ?[]const u8) bool {
if (b == null) {
return false;
}
return mem.eql(u8, a, b.?);
}
fn compare(uri: []const u8, a: *const TestURL, b: *const URL) !void {
if (a.scheme) |scheme| {
if (!equal(scheme, b.scheme)) {
warn("{}: expected scheme={} got scheme={}\n", uri, scheme, b.scheme);
return test_failed;
}
}
if (a.opaque) |opaque| {
if (!equal(opaque, b.opaque)) {
warn("{}: expected opaque={} got opaque={}\n", uri, opaque, b.opaque);
return test_failed;
}
}
if (a.user) |user| {
const u = b.user.?;
if (user.username) |username| {
if (!equal(username, u.username)) {
warn("{}: expected username={} got username={}\n", uri, username, u.username);
return test_failed;
}
}
if (user.password) |password| {
if (!equal(password, u.password)) {
warn("{}: expected password={} got password={}\n", uri, password, u.password);
return test_failed;
}
}
}
if (a.host) |host| {
if (!equal(host, b.host)) {
warn("{}: expected host={} got host={}\n", uri, host, b.host);
return test_failed;
}
}
if (a.path) |path| {
if (!equal(path, b.path)) {
warn("{}: expected path={} got path={}\n", uri, path, b.path);
return test_failed;
}
}
if (a.raw_path) |raw_path| {
if (!equal(raw_path, b.raw_path)) {
warn("{}: expected raw_path={} got raw_path={}\n", uri, raw_path, b.raw_path);
return test_failed;
}
}
if (a.force_query) |force_query| {
if (force_query != b.force_query) {
warn("{}: expected force_query={} got force_query={}\n", uri, force_query, b.force_query);
return test_failed;
}
}
if (a.raw_query) |raw_query| {
if (!equal(raw_query, b.raw_query)) {
warn("{}: expected raw_path={} got raw_path={}\n", uri, raw_query, b.raw_query);
return test_failed;
}
}
if (a.fragment) |fragment| {
if (!equal(fragment, b.fragment)) {
warn("{}: expected fragment={} got fragment={}\n", uri, fragment, b.fragment);
return test_failed;
}
}
} | src/url_test.zig |
const std = @import("std");
const mem = std.mem;
const Allocator = std.mem.Allocator;
const ArenaAllocator = std.heap.ArenaAllocator;
const ArrayList = std.ArrayList;
const parse = @import("parse.zig");
const compile = @import("compile.zig");
const Parser = parse.Parser;
const Assertion = parse.Assertion;
const Program = compile.Program;
const InstructionData = compile.InstructionData;
const Input = @import("input.zig").Input;
const Thread = struct {
pc: usize,
// We know the maximum slot entry in advance. Therefore, we allocate the entire array as needed
// as this is easier (and probably quicker) than allocating only what we need in an ArrayList.
slots: []?usize,
};
const ExecState = struct {
const Self = @This();
arena: ArenaAllocator,
slot_count: usize,
pub fn init(allocator: Allocator, program: Program) Self {
return Self{
.arena = ArenaAllocator.init(allocator),
.slot_count = program.slot_count,
};
}
pub fn deinit(self: *Self) void {
self.arena.deinit();
}
pub fn newSlot(self: *Self) ![]?usize {
var slots = try self.arena.allocator().alloc(?usize, self.slot_count);
mem.set(?usize, slots, null);
return slots;
}
pub fn cloneSlots(self: *Self, other: []?usize) ![]?usize {
var slots = try self.arena.allocator().alloc(?usize, self.slot_count);
mem.copy(?usize, slots, other);
return slots;
}
};
pub const VmPike = struct {
const Self = @This();
allocator: Allocator,
pub fn init(allocator: Allocator) Self {
return Self{ .allocator = allocator };
}
pub fn exec(self: *Self, prog: Program, prog_start: usize, input: *Input, slots: *ArrayList(?usize)) !bool {
var clist = ArrayList(Thread).init(self.allocator);
defer clist.deinit();
var nlist = ArrayList(Thread).init(self.allocator);
defer nlist.deinit();
var state = ExecState.init(self.allocator, prog);
defer state.deinit();
const t = Thread{
.pc = prog_start,
.slots = try state.newSlot(),
};
try clist.append(t);
var matched: ?[]?usize = null;
while (!input.isConsumed()) : (input.advance()) {
while (clist.popOrNull()) |thread| {
const inst = prog.insts[thread.pc];
const at = input.current();
switch (inst.data) {
InstructionData.Char => |ch| {
if (at != null and at.? == ch) {
try nlist.append(Thread{
.pc = inst.out,
.slots = thread.slots,
});
}
},
InstructionData.EmptyMatch => |assertion| {
if (input.isEmptyMatch(assertion)) {
try clist.append(Thread{
.pc = inst.out,
.slots = thread.slots,
});
}
},
InstructionData.ByteClass => |class| {
if (at != null and class.contains(at.?)) {
try nlist.append(Thread{
.pc = inst.out,
.slots = thread.slots,
});
}
},
InstructionData.AnyCharNotNL => {
if (at != null and at.? != '\n') {
try nlist.append(Thread{
.pc = inst.out,
.slots = thread.slots,
});
}
},
InstructionData.Match => {
// We always will have a complete capture in the 0, 1 index
if (matched) |last| {
// leftmost
if (thread.slots[0].? > last[0].?) {
continue;
}
// longest
if (thread.slots[1].? - thread.slots[0].? <= last[1].? - last[0].?) {
continue;
}
}
matched = try state.cloneSlots(thread.slots);
// TODO: Handle thread priority correctly so we can immediately finish all
// current threads in clits.
// clist.shrink(0);
},
InstructionData.Save => |slot| {
// We don't need a deep copy here since we only ever advance forward so
// all future captures are valid for any subsequent threads.
var new_thread = Thread{
.pc = inst.out,
.slots = thread.slots,
};
new_thread.slots[slot] = input.byte_pos;
try clist.append(new_thread);
},
InstructionData.Jump => {
try clist.append(Thread{
.pc = inst.out,
.slots = thread.slots,
});
},
InstructionData.Split => |split| {
// Split pushed first since we want to handle the branch secondary to the
// current thread (popped from end).
try clist.append(Thread{
.pc = split,
.slots = try state.cloneSlots(thread.slots),
});
try clist.append(Thread{
.pc = inst.out,
.slots = thread.slots,
});
},
}
}
mem.swap(ArrayList(Thread), &clist, &nlist);
nlist.shrinkRetainingCapacity(0);
}
if (matched) |ok_matched| {
slots.shrinkAndFree(0);
try slots.appendSlice(ok_matched);
return true;
}
return false;
}
}; | src/vm_pike.zig |
const clap = @import("clap");
const std = @import("std");
const util = @import("util");
const common = @import("common.zig");
const gen3 = @import("gen3.zig");
const gen4 = @import("gen4.zig");
const gen5 = @import("gen5.zig");
const rom = @import("rom.zig");
const debug = std.debug;
const fs = std.fs;
const heap = std.heap;
const io = std.io;
const math = std.math;
const mem = std.mem;
const unicode = std.unicode;
const gba = rom.gba;
const nds = rom.nds;
const Program = @This();
allocator: mem.Allocator,
file: []const u8,
pub const main = util.generateMain(Program);
pub const version = "0.0.0";
pub const description =
\\Identify which Pokémon game a file is.
\\
;
pub const params = &[_]clap.Param(clap.Help){
clap.parseParam("-h, --help Display this help text and exit. ") catch unreachable,
clap.parseParam("-v, --version Output version information and exit.") catch unreachable,
clap.parseParam("<ROM> The rom to identify. ") catch unreachable,
};
pub fn init(allocator: mem.Allocator, args: anytype) !Program {
const pos = args.positionals();
const file_name = if (pos.len > 0) pos[0] else return error.MissingFile;
return Program{
.allocator = allocator,
.file = file_name,
};
}
pub fn run(
program: *Program,
comptime Reader: type,
comptime Writer: type,
stdio: util.CustomStdIoStreams(Reader, Writer),
) anyerror!void {
const file = try fs.cwd().openFile(program.file, .{});
const reader = file.reader();
defer file.close();
inline for ([_]type{
gen3.Game,
gen4.Game,
gen5.Game,
}) |Game| {
try file.seekTo(0);
if (Game.identify(reader)) |info| {
try stdio.out.print("Version: Pokémon {s}\nGamecode: {s}\n", .{
info.version.humanString(),
info.gamecode,
});
return;
} else |err| switch (err) {
error.UnknownGame => {},
else => return err,
}
}
return error.InvalidRom;
} | src/core/tm35-identify.zig |
const std = @import("std");
const interop = @import("../interop.zig");
const iup = @import("../iup.zig");
const Impl = @import("../impl.zig").Impl;
const CallbackHandler = @import("../callback_handler.zig").CallbackHandler;
const debug = std.debug;
const trait = std.meta.trait;
const Element = iup.Element;
const Handle = iup.Handle;
const Error = iup.Error;
const ChildrenIterator = iup.ChildrenIterator;
const Size = iup.Size;
const Margin = iup.Margin;
///
/// Creates a void container for composing elements in a irregular grid.
/// It is a box that arranges the elements it contains from top to bottom and
/// from left to right, by distributing the elements in lines or in columns.
/// But its EXPAND attribute does not behave as a regular container, instead it
/// behaves as a regular element expanding into the available space.
/// The child elements are added to the control just like a vbox and hbox, sequentially.
/// Then they are distributed accordingly the ORIENTATION attribute.
/// When ORIENTATION=HORIZONTAL children are distributed from left to right on
/// the first line until the line does not fits more elements according to the
/// multibox current width, then on the second line, and so on.
/// When ORIENTATION=VERTICAL children are distributed from top to bottom on
/// the first column until columns does not fits more elements according to the
/// multibox current height, then on the second column, and so on.
/// Because of that its elements can overlap other elements in the dialog, so
/// the ideal combination is to put the IupMultiBox inside an IupScrollBox.
/// IMPORTANT: the actual element distribution in the container is done only
/// after the natural size of the dialog is computed because it needs the
/// current with or height to determine which elements will fit in the current
/// space according to the orientation.
/// The first time the multibox natural size is computed it returns simply the
/// largest width and the highest height among the children.
/// The next time it will use the size previously calculated with the
/// line/column breaks, to avoid obtaining an outdated layout call IupRefresh
/// or IupMap before showing the dialog (when the layout will be updated again).
/// It does not have a native representation.
pub const MultiBox = opaque {
pub const CLASS_NAME = "multibox";
pub const NATIVE_TYPE = iup.NativeType.Void;
const Self = @This();
pub const OnUpDateAttribfromFontFn = fn (self: *Self) anyerror!void;
///
/// MAP_CB MAP_CB Called right after an element is mapped and its attributes
/// updated in IupMap.
/// When the element is a dialog, it is called after the layout is updated.
/// For all other elements is called before the layout is updated, so the
/// element current size will still be 0x0 during MAP_CB (since 3.14).
/// Callback int function(Ihandle *ih); [in C] ih:map_cb() -> (ret: number) [in
/// Lua] ih: identifier of the element that activated the event.
/// Affects All that have a native representation.
pub const OnMapFn = fn (self: *Self) anyerror!void;
///
/// DESTROY_CB DESTROY_CB Called right before an element is destroyed.
/// Callback int function(Ihandle *ih); [in C] ih:destroy_cb() -> (ret: number)
/// [in Lua] ih: identifier of the element that activated the event.
/// Notes If the dialog is visible then it is hidden before it is destroyed.
/// The callback will be called right after it is hidden.
/// The callback will be called before all other destroy procedures.
/// For instance, if the element has children then it is called before the
/// children are destroyed.
/// For language binding implementations use the callback name "LDESTROY_CB" to
/// release memory allocated by the binding for the element.
/// Also the callback will be called before the language callback.
/// Affects All.
pub const OnDestroyFn = fn (self: *Self) anyerror!void;
///
/// UNMAP_CB UNMAP_CB Called right before an element is unmapped.
/// Callback int function(Ihandle *ih); [in C] ih:unmap_cb() -> (ret: number)
/// [in Lua] ih: identifier of the element that activated the event.
/// Affects All that have a native representation.
pub const OnUnmapFn = fn (self: *Self) anyerror!void;
pub const OnLDestroyFn = fn (self: *Self) anyerror!void;
pub const OnPostMessageFn = fn (self: *Self, arg0: [:0]const u8, arg1: i32, arg2: f64, arg3: *iup.Unknow) anyerror!void;
///
/// EXPAND (non inheritable*): The default value is "YES".
/// See the documentation of the attribute for EXPAND inheritance.
pub const Expand = enum {
Yes,
Horizontal,
Vertical,
HorizontalFree,
VerticalFree,
No,
};
///
/// ORIENTATION (non inheritable): controls the distribution of the children in
/// lines or in columns.
/// Can be: HORIZONTAL or VERTICAL.
/// Default: HORIZONTAL.
pub const Orientation = enum {
Horizontal,
Vertical,
};
pub const Floating = enum {
Yes,
Ignore,
No,
};
pub const Initializer = struct {
last_error: ?anyerror = null,
ref: *Self,
///
/// Returns a pointer to IUP element or an error.
/// Only top-level or detached elements needs to be unwraped,
pub fn unwrap(self: Initializer) !*Self {
if (self.last_error) |e| {
return e;
} else {
return self.ref;
}
}
///
/// Captures a reference into a external variable
/// Allows to capture some references even using full declarative API
pub fn capture(self: *Initializer, ref: **Self) Initializer {
ref.* = self.ref;
return self.*;
}
pub fn setStrAttribute(self: *Initializer, attributeName: [:0]const u8, arg: [:0]const u8) Initializer {
if (self.last_error) |_| return self.*;
Self.setStrAttribute(self.ref, attributeName, arg);
return self.*;
}
pub fn setIntAttribute(self: *Initializer, attributeName: [:0]const u8, arg: i32) Initializer {
if (self.last_error) |_| return self.*;
Self.setIntAttribute(self.ref, attributeName, arg);
return self.*;
}
pub fn setBoolAttribute(self: *Initializer, attributeName: [:0]const u8, arg: bool) Initializer {
if (self.last_error) |_| return self.*;
Self.setBoolAttribute(self.ref, attributeName, arg);
return self.*;
}
pub fn setPtrAttribute(self: *Initializer, comptime T: type, attributeName: [:0]const u8, value: ?*T) Initializer {
if (self.last_error) |_| return self.*;
Self.setPtrAttribute(self.ref, T, attributeName, value);
return self.*;
}
pub fn setHandle(self: *Initializer, arg: [:0]const u8) Initializer {
if (self.last_error) |_| return self.*;
interop.setHandle(self.ref, arg);
return self.*;
}
pub fn setChildren(self: *Initializer, tuple: anytype) Initializer {
if (self.last_error) |_| return self.*;
Self.appendChildren(self.ref, tuple) catch |err| {
self.last_error = err;
};
return self.*;
}
pub fn setHandleName(self: *Initializer, arg: [:0]const u8) Initializer {
if (self.last_error) |_| return self.*;
interop.setStrAttribute(self.ref, "HANDLENAME", .{}, arg);
return self.*;
}
pub fn setMaxSize(self: *Initializer, width: ?i32, height: ?i32) Initializer {
if (self.last_error) |_| return self.*;
var buffer: [128]u8 = undefined;
var value = Size.intIntToString(&buffer, width, height);
interop.setStrAttribute(self.ref, "MAXSIZE", .{}, value);
return self.*;
}
pub fn setPosition(self: *Initializer, x: i32, y: i32) Initializer {
if (self.last_error) |_| return self.*;
var buffer: [128]u8 = undefined;
var value = iup.XYPos.intIntToString(&buffer, x, y, ',');
interop.setStrAttribute(self.ref, "POSITION", .{}, value);
return self.*;
}
pub fn setCanFocus(self: *Initializer, arg: bool) Initializer {
if (self.last_error) |_| return self.*;
interop.setBoolAttribute(self.ref, "CANFOCUS", .{}, arg);
return self.*;
}
pub fn setVisible(self: *Initializer, arg: bool) Initializer {
if (self.last_error) |_| return self.*;
interop.setBoolAttribute(self.ref, "VISIBLE", .{}, arg);
return self.*;
}
pub fn setTheme(self: *Initializer, arg: [:0]const u8) Initializer {
if (self.last_error) |_| return self.*;
interop.setStrAttribute(self.ref, "THEME", .{}, arg);
return self.*;
}
///
/// MARGIN, CMARGIN: Defines a margin in pixels, CMARGIN is in the same units
/// of the SIZE attribute.
/// Its value has the format "widthxheight", where width and height are integer
/// values corresponding to the horizontal and vertical margins, respectively.
/// Default: "0x0" (no margin).
pub fn setCMargin(self: *Initializer, horiz: i32, vert: i32) Initializer {
if (self.last_error) |_| return self.*;
var buffer: [128]u8 = undefined;
var value = Margin.intIntToString(&buffer, horiz, vert);
interop.setStrAttribute(self.ref, "CMARGIN", .{}, value);
return self.*;
}
///
/// EXPAND (non inheritable*): The default value is "YES".
/// See the documentation of the attribute for EXPAND inheritance.
pub fn setExpand(self: *Initializer, arg: ?Expand) Initializer {
if (self.last_error) |_| return self.*;
if (arg) |value| switch (value) {
.Yes => interop.setStrAttribute(self.ref, "EXPAND", .{}, "YES"),
.Horizontal => interop.setStrAttribute(self.ref, "EXPAND", .{}, "HORIZONTAL"),
.Vertical => interop.setStrAttribute(self.ref, "EXPAND", .{}, "VERTICAL"),
.HorizontalFree => interop.setStrAttribute(self.ref, "EXPAND", .{}, "HORIZONTALFREE"),
.VerticalFree => interop.setStrAttribute(self.ref, "EXPAND", .{}, "VERTICALFREE"),
.No => interop.setStrAttribute(self.ref, "EXPAND", .{}, "NO"),
} else {
interop.clearAttribute(self.ref, "EXPAND", .{});
}
return self.*;
}
///
/// SIZE, RASTERSIZE, FONT, CLIENTSIZE, CLIENTOFFSET, POSITION, MINSIZE,
/// MAXSIZE, THEME: also accepted.
pub fn setSize(self: *Initializer, width: ?i32, height: ?i32) Initializer {
if (self.last_error) |_| return self.*;
var buffer: [128]u8 = undefined;
var value = Size.intIntToString(&buffer, width, height);
interop.setStrAttribute(self.ref, "SIZE", .{}, value);
return self.*;
}
///
/// ORIENTATION (non inheritable): controls the distribution of the children in
/// lines or in columns.
/// Can be: HORIZONTAL or VERTICAL.
/// Default: HORIZONTAL.
pub fn setOrientation(self: *Initializer, arg: ?Orientation) Initializer {
if (self.last_error) |_| return self.*;
if (arg) |value| switch (value) {
.Horizontal => interop.setStrAttribute(self.ref, "ORIENTATION", .{}, "HORIZONTAL"),
.Vertical => interop.setStrAttribute(self.ref, "ORIENTATION", .{}, "VERTICAL"),
} else {
interop.clearAttribute(self.ref, "ORIENTATION", .{});
}
return self.*;
}
pub fn setFontSize(self: *Initializer, arg: i32) Initializer {
if (self.last_error) |_| return self.*;
interop.setIntAttribute(self.ref, "FONTSIZE", .{}, arg);
return self.*;
}
pub fn setUserSize(self: *Initializer, width: ?i32, height: ?i32) Initializer {
if (self.last_error) |_| return self.*;
var buffer: [128]u8 = undefined;
var value = Size.intIntToString(&buffer, width, height);
interop.setStrAttribute(self.ref, "USERSIZE", .{}, value);
return self.*;
}
pub fn setPropagateFocus(self: *Initializer, arg: bool) Initializer {
if (self.last_error) |_| return self.*;
interop.setBoolAttribute(self.ref, "PROPAGATEFOCUS", .{}, arg);
return self.*;
}
pub fn setFloating(self: *Initializer, arg: ?Floating) Initializer {
if (self.last_error) |_| return self.*;
if (arg) |value| switch (value) {
.Yes => interop.setStrAttribute(self.ref, "FLOATING", .{}, "YES"),
.Ignore => interop.setStrAttribute(self.ref, "FLOATING", .{}, "IGNORE"),
.No => interop.setStrAttribute(self.ref, "FLOATING", .{}, "NO"),
} else {
interop.clearAttribute(self.ref, "FLOATING", .{});
}
return self.*;
}
///
/// NMARGIN, NCMARGIN (non inheritable): Same as MARGIN but are non inheritable.
pub fn setNMargin(self: *Initializer, horiz: i32, vert: i32) Initializer {
if (self.last_error) |_| return self.*;
var buffer: [128]u8 = undefined;
var value = Margin.intIntToString(&buffer, horiz, vert);
interop.setStrAttribute(self.ref, "NMARGIN", .{}, value);
return self.*;
}
pub fn setNormalizerGroup(self: *Initializer, arg: [:0]const u8) Initializer {
if (self.last_error) |_| return self.*;
interop.setStrAttribute(self.ref, "NORMALIZERGROUP", .{}, arg);
return self.*;
}
pub fn setRasterSize(self: *Initializer, width: ?i32, height: ?i32) Initializer {
if (self.last_error) |_| return self.*;
var buffer: [128]u8 = undefined;
var value = Size.intIntToString(&buffer, width, height);
interop.setStrAttribute(self.ref, "RASTERSIZE", .{}, value);
return self.*;
}
pub fn setFontFace(self: *Initializer, arg: [:0]const u8) Initializer {
if (self.last_error) |_| return self.*;
interop.setStrAttribute(self.ref, "FONTFACE", .{}, arg);
return self.*;
}
pub fn setName(self: *Initializer, arg: [:0]const u8) Initializer {
if (self.last_error) |_| return self.*;
interop.setStrAttribute(self.ref, "NAME", .{}, arg);
return self.*;
}
pub fn setActive(self: *Initializer, arg: bool) Initializer {
if (self.last_error) |_| return self.*;
interop.setBoolAttribute(self.ref, "ACTIVE", .{}, arg);
return self.*;
}
pub fn setExpandWeight(self: *Initializer, arg: f64) Initializer {
if (self.last_error) |_| return self.*;
interop.setDoubleAttribute(self.ref, "EXPANDWEIGHT", .{}, arg);
return self.*;
}
pub fn setMinSize(self: *Initializer, width: ?i32, height: ?i32) Initializer {
if (self.last_error) |_| return self.*;
var buffer: [128]u8 = undefined;
var value = Size.intIntToString(&buffer, width, height);
interop.setStrAttribute(self.ref, "MINSIZE", .{}, value);
return self.*;
}
pub fn setNTheme(self: *Initializer, arg: [:0]const u8) Initializer {
if (self.last_error) |_| return self.*;
interop.setStrAttribute(self.ref, "NTHEME", .{}, arg);
return self.*;
}
pub fn setFontStyle(self: *Initializer, arg: [:0]const u8) Initializer {
if (self.last_error) |_| return self.*;
interop.setStrAttribute(self.ref, "FONTSTYLE", .{}, arg);
return self.*;
}
///
/// NMARGIN, NCMARGIN (non inheritable): Same as MARGIN but are non inheritable.
pub fn setNcMargin(self: *Initializer, horiz: i32, vert: i32) Initializer {
if (self.last_error) |_| return self.*;
var buffer: [128]u8 = undefined;
var value = Margin.intIntToString(&buffer, horiz, vert);
interop.setStrAttribute(self.ref, "NCMARGIN", .{}, value);
return self.*;
}
///
/// MARGIN, CMARGIN: Defines a margin in pixels, CMARGIN is in the same units
/// of the SIZE attribute.
/// Its value has the format "widthxheight", where width and height are integer
/// values corresponding to the horizontal and vertical margins, respectively.
/// Default: "0x0" (no margin).
pub fn setMargin(self: *Initializer, horiz: i32, vert: i32) Initializer {
if (self.last_error) |_| return self.*;
var buffer: [128]u8 = undefined;
var value = Margin.intIntToString(&buffer, horiz, vert);
interop.setStrAttribute(self.ref, "MARGIN", .{}, value);
return self.*;
}
pub fn setFont(self: *Initializer, arg: [:0]const u8) Initializer {
if (self.last_error) |_| return self.*;
interop.setStrAttribute(self.ref, "FONT", .{}, arg);
return self.*;
}
///
/// TABIMAGEn (non inheritable): image name to be used in the respective tab.
/// Use IupSetHandle or IupSetAttributeHandle to associate an image to a name.
/// n starts at 0.
/// See also IupImage.
/// In Motif, the image is shown only if TABTITLEn is NULL.
/// In Windows and Motif set the BGCOLOR attribute before setting the image.
/// When set after map will update the TABIMAGE attribute on the respective
/// child (since 3.10).
/// (since 3.0).
/// TABIMAGE (non inheritable) (at children only): Same as TABIMAGEn but set in
/// each child.
/// Works only if set before the child is added to the tabs.
pub fn setTabImage(self: *Initializer, index: i32, arg: anytype) Initializer {
if (self.last_error) |_| return self.*;
if (interop.validateHandle(.Image, arg)) {
interop.setHandleAttribute(self.ref, "TABIMAGE", .{index}, arg);
} else |err| {
self.last_error = err;
}
return self.*;
}
pub fn setTabImageHandleName(self: *Initializer, index: i32, arg: [:0]const u8) Initializer {
if (self.last_error) |_| return self.*;
interop.setStrAttribute(self.ref, "TABIMAGE", .{index}, arg);
return self.*;
}
///
/// TABTITLEn (non inheritable): Contains the text to be shown in the
/// respective tab title.
/// n starts at 0.
/// If this value is NULL, it will remain empty.
/// The "&" character can be used to define a mnemonic, the next character will
/// be used as key.
/// Use "&&" to show the "&" character instead on defining a mnemonic.
/// The button can be activated from any control in the dialog using the
/// "Alt+key" combination.
/// (mnemonic support since 3.3).
/// When set after map will update the TABTITLE attribute on the respective
/// child (since 3.10).
/// (since 3.0).
/// TABTITLE (non inheritable) (at children only): Same as TABTITLEn but set in
/// each child.
/// Works only if set before the child is added to the tabs.
pub fn setTabTitle(self: *Initializer, index: i32, arg: [:0]const u8) Initializer {
if (self.last_error) |_| return self.*;
interop.setStrAttribute(self.ref, "TABTITLE", .{index}, arg);
return self.*;
}
pub fn setUpDateAttribfromFontCallback(self: *Initializer, callback: ?OnUpDateAttribfromFontFn) Initializer {
const Handler = CallbackHandler(Self, OnUpDateAttribfromFontFn, "UPDATEATTRIBFROMFONT_CB");
Handler.setCallback(self.ref, callback);
return self.*;
}
///
/// MAP_CB MAP_CB Called right after an element is mapped and its attributes
/// updated in IupMap.
/// When the element is a dialog, it is called after the layout is updated.
/// For all other elements is called before the layout is updated, so the
/// element current size will still be 0x0 during MAP_CB (since 3.14).
/// Callback int function(Ihandle *ih); [in C] ih:map_cb() -> (ret: number) [in
/// Lua] ih: identifier of the element that activated the event.
/// Affects All that have a native representation.
pub fn setMapCallback(self: *Initializer, callback: ?OnMapFn) Initializer {
const Handler = CallbackHandler(Self, OnMapFn, "MAP_CB");
Handler.setCallback(self.ref, callback);
return self.*;
}
///
/// DESTROY_CB DESTROY_CB Called right before an element is destroyed.
/// Callback int function(Ihandle *ih); [in C] ih:destroy_cb() -> (ret: number)
/// [in Lua] ih: identifier of the element that activated the event.
/// Notes If the dialog is visible then it is hidden before it is destroyed.
/// The callback will be called right after it is hidden.
/// The callback will be called before all other destroy procedures.
/// For instance, if the element has children then it is called before the
/// children are destroyed.
/// For language binding implementations use the callback name "LDESTROY_CB" to
/// release memory allocated by the binding for the element.
/// Also the callback will be called before the language callback.
/// Affects All.
pub fn setDestroyCallback(self: *Initializer, callback: ?OnDestroyFn) Initializer {
const Handler = CallbackHandler(Self, OnDestroyFn, "DESTROY_CB");
Handler.setCallback(self.ref, callback);
return self.*;
}
///
/// UNMAP_CB UNMAP_CB Called right before an element is unmapped.
/// Callback int function(Ihandle *ih); [in C] ih:unmap_cb() -> (ret: number)
/// [in Lua] ih: identifier of the element that activated the event.
/// Affects All that have a native representation.
pub fn setUnmapCallback(self: *Initializer, callback: ?OnUnmapFn) Initializer {
const Handler = CallbackHandler(Self, OnUnmapFn, "UNMAP_CB");
Handler.setCallback(self.ref, callback);
return self.*;
}
pub fn setLDestroyCallback(self: *Initializer, callback: ?OnLDestroyFn) Initializer {
const Handler = CallbackHandler(Self, OnLDestroyFn, "LDESTROY_CB");
Handler.setCallback(self.ref, callback);
return self.*;
}
pub fn setPostMessageCallback(self: *Initializer, callback: ?OnPostMessageFn) Initializer {
const Handler = CallbackHandler(Self, OnPostMessageFn, "POSTMESSAGE_CB");
Handler.setCallback(self.ref, callback);
return self.*;
}
};
pub fn setStrAttribute(self: *Self, attribute: [:0]const u8, arg: [:0]const u8) void {
interop.setStrAttribute(self, attribute, .{}, arg);
}
pub fn getStrAttribute(self: *Self, attribute: [:0]const u8) [:0]const u8 {
return interop.getStrAttribute(self, attribute, .{});
}
pub fn setIntAttribute(self: *Self, attribute: [:0]const u8, arg: i32) void {
interop.setIntAttribute(self, attribute, .{}, arg);
}
pub fn getIntAttribute(self: *Self, attribute: [:0]const u8) i32 {
return interop.getIntAttribute(self, attribute, .{});
}
pub fn setBoolAttribute(self: *Self, attribute: [:0]const u8, arg: bool) void {
interop.setBoolAttribute(self, attribute, .{}, arg);
}
pub fn getBoolAttribute(self: *Self, attribute: [:0]const u8) bool {
return interop.getBoolAttribute(self, attribute, .{});
}
pub fn getPtrAttribute(self: *Self, comptime T: type, attribute: [:0]const u8) ?*T {
return interop.getPtrAttribute(T, self, attribute, .{});
}
pub fn setPtrAttribute(self: *Self, comptime T: type, attribute: [:0]const u8, value: ?*T) void {
interop.setPtrAttribute(T, self, attribute, .{}, value);
}
pub fn setHandle(self: *Self, arg: [:0]const u8) void {
interop.setHandle(self, arg);
}
pub fn fromHandleName(handle_name: [:0]const u8) ?*Self {
return interop.fromHandleName(Self, handle_name);
}
///
/// Creates an interface element given its class name and parameters.
/// After creation the element still needs to be attached to a container and mapped to the native system so it can be visible.
pub fn init() Initializer {
var handle = interop.create(Self);
if (handle) |valid| {
return .{
.ref = @ptrCast(*Self, valid),
};
} else {
return .{ .ref = undefined, .last_error = Error.NotInitialized };
}
}
///
/// Destroys an interface element and all its children.
/// Only dialogs, timers, popup menus and images should be normally destroyed, but detached elements can also be destroyed.
pub fn deinit(self: *Self) void {
interop.destroy(self);
}
///
/// Creates (maps) the native interface objects corresponding to the given IUP interface elements.
/// It will also called recursively to create the native element of all the children in the element's tree.
/// The element must be already attached to a mapped container, except the dialog. A child can only be mapped if its parent is already mapped.
/// This function is automatically called before the dialog is shown in IupShow, IupShowXY or IupPopup.
/// If the element is a dialog then the abstract layout will be updated even if the dialog is already mapped. If the dialog is visible the elements will be immediately repositioned. Calling IupMap for an already mapped dialog is the same as only calling IupRefresh for the dialog.
/// Calling IupMap for an already mapped element that is not a dialog does nothing.
/// If you add new elements to an already mapped dialog you must call IupMap for that elements. And then call IupRefresh to update the dialog layout.
/// If the WID attribute of an element is NULL, it means the element was not already mapped. Some containers do not have a native element associated, like VBOX and HBOX. In this case their WID is a fake value (void*)(-1).
/// It is useful for the application to call IupMap when the value of the WID attribute must be known, i.e. the native element must exist, before a dialog is made visible.
/// The MAP_CB callback is called at the end of the IupMap function, after all processing, so it can also be used to create other things that depend on the WID attribute. But notice that for non dialog elements it will be called before the dialog layout has been updated, so the element current size will still be 0x0 (since 3.14).
pub fn map(self: *Self) !void {
try interop.map(self);
}
///
/// Adds a tuple of children
pub fn appendChildren(self: *Self, tuple: anytype) !void {
try Impl(Self).appendChildren(self, tuple);
}
///
/// Appends a child on this container
/// child must be an Element or
pub fn appendChild(self: *Self, child: anytype) !void {
try Impl(Self).appendChild(self, child);
}
///
/// Returns a iterator for children elements.
pub fn children(self: *Self) ChildrenIterator {
return ChildrenIterator.init(self);
}
///
///
pub fn getDialog(self: *Self) ?*iup.Dialog {
return interop.getDialog(self);
}
///
/// Returns the the child element that has the NAME attribute equals to the given value on the same dialog hierarchy.
/// Works also for children of a menu that is associated with a dialog.
pub fn getDialogChild(self: *Self, byName: [:0]const u8) ?Element {
return interop.getDialogChild(self, byName);
}
///
/// Updates the size and layout of all controls in the same dialog.
/// To be used after changing size attributes, or attributes that affect the size of the control. Can be used for any element inside a dialog, but the layout of the dialog and all controls will be updated. It can change the layout of all the controls inside the dialog because of the dynamic layout positioning.
pub fn refresh(self: *Self) void {
Impl(Self).refresh(self);
}
pub fn getHandleName(self: *Self) [:0]const u8 {
return interop.getStrAttribute(self, "HANDLENAME", .{});
}
pub fn setHandleName(self: *Self, arg: [:0]const u8) void {
interop.setStrAttribute(self, "HANDLENAME", .{}, arg);
}
pub fn getMaxSize(self: *Self) Size {
var str = interop.getStrAttribute(self, "MAXSIZE", .{});
return Size.parse(str);
}
pub fn setMaxSize(self: *Self, width: ?i32, height: ?i32) void {
var buffer: [128]u8 = undefined;
var value = Size.intIntToString(&buffer, width, height);
interop.setStrAttribute(self, "MAXSIZE", .{}, value);
}
pub fn getPosition(self: *Self) iup.XYPos {
var str = interop.getStrAttribute(self, "POSITION", .{});
return iup.XYPos.parse(str, ',');
}
pub fn setPosition(self: *Self, x: i32, y: i32) void {
var buffer: [128]u8 = undefined;
var value = iup.XYPos.intIntToString(&buffer, x, y, ',');
interop.setStrAttribute(self, "POSITION", .{}, value);
}
pub fn getCanFocus(self: *Self) bool {
return interop.getBoolAttribute(self, "CANFOCUS", .{});
}
pub fn setCanFocus(self: *Self, arg: bool) void {
interop.setBoolAttribute(self, "CANFOCUS", .{}, arg);
}
pub fn getVisible(self: *Self) bool {
return interop.getBoolAttribute(self, "VISIBLE", .{});
}
pub fn setVisible(self: *Self, arg: bool) void {
interop.setBoolAttribute(self, "VISIBLE", .{}, arg);
}
pub fn getTheme(self: *Self) [:0]const u8 {
return interop.getStrAttribute(self, "THEME", .{});
}
pub fn setTheme(self: *Self, arg: [:0]const u8) void {
interop.setStrAttribute(self, "THEME", .{}, arg);
}
///
/// MARGIN, CMARGIN: Defines a margin in pixels, CMARGIN is in the same units
/// of the SIZE attribute.
/// Its value has the format "widthxheight", where width and height are integer
/// values corresponding to the horizontal and vertical margins, respectively.
/// Default: "0x0" (no margin).
pub fn getCMargin(self: *Self) Margin {
var str = interop.getStrAttribute(self, "CMARGIN", .{});
return Margin.parse(str);
}
///
/// MARGIN, CMARGIN: Defines a margin in pixels, CMARGIN is in the same units
/// of the SIZE attribute.
/// Its value has the format "widthxheight", where width and height are integer
/// values corresponding to the horizontal and vertical margins, respectively.
/// Default: "0x0" (no margin).
pub fn setCMargin(self: *Self, horiz: i32, vert: i32) void {
var buffer: [128]u8 = undefined;
var value = Margin.intIntToString(&buffer, horiz, vert);
interop.setStrAttribute(self, "CMARGIN", .{}, value);
}
///
/// EXPAND (non inheritable*): The default value is "YES".
/// See the documentation of the attribute for EXPAND inheritance.
pub fn getExpand(self: *Self) ?Expand {
var ret = interop.getStrAttribute(self, "EXPAND", .{});
if (std.ascii.eqlIgnoreCase("YES", ret)) return .Yes;
if (std.ascii.eqlIgnoreCase("HORIZONTAL", ret)) return .Horizontal;
if (std.ascii.eqlIgnoreCase("VERTICAL", ret)) return .Vertical;
if (std.ascii.eqlIgnoreCase("HORIZONTALFREE", ret)) return .HorizontalFree;
if (std.ascii.eqlIgnoreCase("VERTICALFREE", ret)) return .VerticalFree;
if (std.ascii.eqlIgnoreCase("NO", ret)) return .No;
return null;
}
///
/// EXPAND (non inheritable*): The default value is "YES".
/// See the documentation of the attribute for EXPAND inheritance.
pub fn setExpand(self: *Self, arg: ?Expand) void {
if (arg) |value| switch (value) {
.Yes => interop.setStrAttribute(self, "EXPAND", .{}, "YES"),
.Horizontal => interop.setStrAttribute(self, "EXPAND", .{}, "HORIZONTAL"),
.Vertical => interop.setStrAttribute(self, "EXPAND", .{}, "VERTICAL"),
.HorizontalFree => interop.setStrAttribute(self, "EXPAND", .{}, "HORIZONTALFREE"),
.VerticalFree => interop.setStrAttribute(self, "EXPAND", .{}, "VERTICALFREE"),
.No => interop.setStrAttribute(self, "EXPAND", .{}, "NO"),
} else {
interop.clearAttribute(self, "EXPAND", .{});
}
}
///
/// SIZE, RASTERSIZE, FONT, CLIENTSIZE, CLIENTOFFSET, POSITION, MINSIZE,
/// MAXSIZE, THEME: also accepted.
pub fn getSize(self: *Self) Size {
var str = interop.getStrAttribute(self, "SIZE", .{});
return Size.parse(str);
}
///
/// SIZE, RASTERSIZE, FONT, CLIENTSIZE, CLIENTOFFSET, POSITION, MINSIZE,
/// MAXSIZE, THEME: also accepted.
pub fn setSize(self: *Self, width: ?i32, height: ?i32) void {
var buffer: [128]u8 = undefined;
var value = Size.intIntToString(&buffer, width, height);
interop.setStrAttribute(self, "SIZE", .{}, value);
}
///
/// WID (read-only): returns -1 if mapped.
pub fn getWId(self: *Self) i32 {
return interop.getIntAttribute(self, "WID", .{});
}
///
/// ORIENTATION (non inheritable): controls the distribution of the children in
/// lines or in columns.
/// Can be: HORIZONTAL or VERTICAL.
/// Default: HORIZONTAL.
pub fn getOrientation(self: *Self) ?Orientation {
var ret = interop.getStrAttribute(self, "ORIENTATION", .{});
if (std.ascii.eqlIgnoreCase("HORIZONTAL", ret)) return .Horizontal;
if (std.ascii.eqlIgnoreCase("VERTICAL", ret)) return .Vertical;
return null;
}
///
/// ORIENTATION (non inheritable): controls the distribution of the children in
/// lines or in columns.
/// Can be: HORIZONTAL or VERTICAL.
/// Default: HORIZONTAL.
pub fn setOrientation(self: *Self, arg: ?Orientation) void {
if (arg) |value| switch (value) {
.Horizontal => interop.setStrAttribute(self, "ORIENTATION", .{}, "HORIZONTAL"),
.Vertical => interop.setStrAttribute(self, "ORIENTATION", .{}, "VERTICAL"),
} else {
interop.clearAttribute(self, "ORIENTATION", .{});
}
}
pub fn getFontSize(self: *Self) i32 {
return interop.getIntAttribute(self, "FONTSIZE", .{});
}
pub fn setFontSize(self: *Self, arg: i32) void {
interop.setIntAttribute(self, "FONTSIZE", .{}, arg);
}
pub fn getNaturalSize(self: *Self) Size {
var str = interop.getStrAttribute(self, "NATURALSIZE", .{});
return Size.parse(str);
}
pub fn getUserSize(self: *Self) Size {
var str = interop.getStrAttribute(self, "USERSIZE", .{});
return Size.parse(str);
}
pub fn setUserSize(self: *Self, width: ?i32, height: ?i32) void {
var buffer: [128]u8 = undefined;
var value = Size.intIntToString(&buffer, width, height);
interop.setStrAttribute(self, "USERSIZE", .{}, value);
}
pub fn getPropagateFocus(self: *Self) bool {
return interop.getBoolAttribute(self, "PROPAGATEFOCUS", .{});
}
pub fn setPropagateFocus(self: *Self, arg: bool) void {
interop.setBoolAttribute(self, "PROPAGATEFOCUS", .{}, arg);
}
pub fn getFloating(self: *Self) ?Floating {
var ret = interop.getStrAttribute(self, "FLOATING", .{});
if (std.ascii.eqlIgnoreCase("YES", ret)) return .Yes;
if (std.ascii.eqlIgnoreCase("IGNORE", ret)) return .Ignore;
if (std.ascii.eqlIgnoreCase("NO", ret)) return .No;
return null;
}
pub fn setFloating(self: *Self, arg: ?Floating) void {
if (arg) |value| switch (value) {
.Yes => interop.setStrAttribute(self, "FLOATING", .{}, "YES"),
.Ignore => interop.setStrAttribute(self, "FLOATING", .{}, "IGNORE"),
.No => interop.setStrAttribute(self, "FLOATING", .{}, "NO"),
} else {
interop.clearAttribute(self, "FLOATING", .{});
}
}
///
/// NMARGIN, NCMARGIN (non inheritable): Same as MARGIN but are non inheritable.
pub fn getNMargin(self: *Self) Margin {
var str = interop.getStrAttribute(self, "NMARGIN", .{});
return Margin.parse(str);
}
///
/// NMARGIN, NCMARGIN (non inheritable): Same as MARGIN but are non inheritable.
pub fn setNMargin(self: *Self, horiz: i32, vert: i32) void {
var buffer: [128]u8 = undefined;
var value = Margin.intIntToString(&buffer, horiz, vert);
interop.setStrAttribute(self, "NMARGIN", .{}, value);
}
pub fn getNormalizerGroup(self: *Self) [:0]const u8 {
return interop.getStrAttribute(self, "NORMALIZERGROUP", .{});
}
pub fn setNormalizerGroup(self: *Self, arg: [:0]const u8) void {
interop.setStrAttribute(self, "NORMALIZERGROUP", .{}, arg);
}
pub fn getRasterSize(self: *Self) Size {
var str = interop.getStrAttribute(self, "RASTERSIZE", .{});
return Size.parse(str);
}
pub fn setRasterSize(self: *Self, width: ?i32, height: ?i32) void {
var buffer: [128]u8 = undefined;
var value = Size.intIntToString(&buffer, width, height);
interop.setStrAttribute(self, "RASTERSIZE", .{}, value);
}
pub fn getFontFace(self: *Self) [:0]const u8 {
return interop.getStrAttribute(self, "FONTFACE", .{});
}
pub fn setFontFace(self: *Self, arg: [:0]const u8) void {
interop.setStrAttribute(self, "FONTFACE", .{}, arg);
}
pub fn getName(self: *Self) [:0]const u8 {
return interop.getStrAttribute(self, "NAME", .{});
}
pub fn setName(self: *Self, arg: [:0]const u8) void {
interop.setStrAttribute(self, "NAME", .{}, arg);
}
///
/// NUMCOL (read-only): returns the number of columns when ORIENTATION=VERTICAL.
/// Returns 0 otherwise.
pub fn getNumCol(self: *Self) i32 {
return interop.getIntAttribute(self, "NUMCOL", .{});
}
pub fn getActive(self: *Self) bool {
return interop.getBoolAttribute(self, "ACTIVE", .{});
}
pub fn setActive(self: *Self, arg: bool) void {
interop.setBoolAttribute(self, "ACTIVE", .{}, arg);
}
pub fn getExpandWeight(self: *Self) f64 {
return interop.getDoubleAttribute(self, "EXPANDWEIGHT", .{});
}
pub fn setExpandWeight(self: *Self, arg: f64) void {
interop.setDoubleAttribute(self, "EXPANDWEIGHT", .{}, arg);
}
pub fn getMinSize(self: *Self) Size {
var str = interop.getStrAttribute(self, "MINSIZE", .{});
return Size.parse(str);
}
pub fn setMinSize(self: *Self, width: ?i32, height: ?i32) void {
var buffer: [128]u8 = undefined;
var value = Size.intIntToString(&buffer, width, height);
interop.setStrAttribute(self, "MINSIZE", .{}, value);
}
///
/// NUMLIN (read-only): returns the number of lines when ORIENTATION=HORIZONTAL.
/// Returns 0 otherwise.
pub fn getNumLin(self: *Self) i32 {
return interop.getIntAttribute(self, "NUMLIN", .{});
}
pub fn getNTheme(self: *Self) [:0]const u8 {
return interop.getStrAttribute(self, "NTHEME", .{});
}
pub fn setNTheme(self: *Self, arg: [:0]const u8) void {
interop.setStrAttribute(self, "NTHEME", .{}, arg);
}
pub fn getCharSize(self: *Self) Size {
var str = interop.getStrAttribute(self, "CHARSIZE", .{});
return Size.parse(str);
}
pub fn getClientSize(self: *Self) Size {
var str = interop.getStrAttribute(self, "CLIENTSIZE", .{});
return Size.parse(str);
}
pub fn getClientOffset(self: *Self) Size {
var str = interop.getStrAttribute(self, "CLIENTOFFSET", .{});
return Size.parse(str);
}
pub fn getFontStyle(self: *Self) [:0]const u8 {
return interop.getStrAttribute(self, "FONTSTYLE", .{});
}
pub fn setFontStyle(self: *Self, arg: [:0]const u8) void {
interop.setStrAttribute(self, "FONTSTYLE", .{}, arg);
}
///
/// NMARGIN, NCMARGIN (non inheritable): Same as MARGIN but are non inheritable.
pub fn getNcMargin(self: *Self) Margin {
var str = interop.getStrAttribute(self, "NCMARGIN", .{});
return Margin.parse(str);
}
///
/// NMARGIN, NCMARGIN (non inheritable): Same as MARGIN but are non inheritable.
pub fn setNcMargin(self: *Self, horiz: i32, vert: i32) void {
var buffer: [128]u8 = undefined;
var value = Margin.intIntToString(&buffer, horiz, vert);
interop.setStrAttribute(self, "NCMARGIN", .{}, value);
}
///
/// MARGIN, CMARGIN: Defines a margin in pixels, CMARGIN is in the same units
/// of the SIZE attribute.
/// Its value has the format "widthxheight", where width and height are integer
/// values corresponding to the horizontal and vertical margins, respectively.
/// Default: "0x0" (no margin).
pub fn getMargin(self: *Self) Margin {
var str = interop.getStrAttribute(self, "MARGIN", .{});
return Margin.parse(str);
}
///
/// MARGIN, CMARGIN: Defines a margin in pixels, CMARGIN is in the same units
/// of the SIZE attribute.
/// Its value has the format "widthxheight", where width and height are integer
/// values corresponding to the horizontal and vertical margins, respectively.
/// Default: "0x0" (no margin).
pub fn setMargin(self: *Self, horiz: i32, vert: i32) void {
var buffer: [128]u8 = undefined;
var value = Margin.intIntToString(&buffer, horiz, vert);
interop.setStrAttribute(self, "MARGIN", .{}, value);
}
pub fn getFont(self: *Self) [:0]const u8 {
return interop.getStrAttribute(self, "FONT", .{});
}
pub fn setFont(self: *Self, arg: [:0]const u8) void {
interop.setStrAttribute(self, "FONT", .{}, arg);
}
///
/// TABIMAGEn (non inheritable): image name to be used in the respective tab.
/// Use IupSetHandle or IupSetAttributeHandle to associate an image to a name.
/// n starts at 0.
/// See also IupImage.
/// In Motif, the image is shown only if TABTITLEn is NULL.
/// In Windows and Motif set the BGCOLOR attribute before setting the image.
/// When set after map will update the TABIMAGE attribute on the respective
/// child (since 3.10).
/// (since 3.0).
/// TABIMAGE (non inheritable) (at children only): Same as TABIMAGEn but set in
/// each child.
/// Works only if set before the child is added to the tabs.
pub fn getTabImage(self: *Self, index: i32) ?iup.Element {
if (interop.getHandleAttribute(self, "TABIMAGE", .{index})) |handle| {
return iup.Element.fromHandle(handle);
} else {
return null;
}
}
///
/// TABIMAGEn (non inheritable): image name to be used in the respective tab.
/// Use IupSetHandle or IupSetAttributeHandle to associate an image to a name.
/// n starts at 0.
/// See also IupImage.
/// In Motif, the image is shown only if TABTITLEn is NULL.
/// In Windows and Motif set the BGCOLOR attribute before setting the image.
/// When set after map will update the TABIMAGE attribute on the respective
/// child (since 3.10).
/// (since 3.0).
/// TABIMAGE (non inheritable) (at children only): Same as TABIMAGEn but set in
/// each child.
/// Works only if set before the child is added to the tabs.
pub fn setTabImage(self: *Self, index: i32, arg: anytype) !void {
try interop.validateHandle(.Image, arg);
interop.setHandleAttribute(self, "TABIMAGE", .{index}, arg);
}
pub fn setTabImageHandleName(self: *Self, index: i32, arg: [:0]const u8) void {
interop.setStrAttribute(self, "TABIMAGE", .{index}, arg);
}
///
/// TABTITLEn (non inheritable): Contains the text to be shown in the
/// respective tab title.
/// n starts at 0.
/// If this value is NULL, it will remain empty.
/// The "&" character can be used to define a mnemonic, the next character will
/// be used as key.
/// Use "&&" to show the "&" character instead on defining a mnemonic.
/// The button can be activated from any control in the dialog using the
/// "Alt+key" combination.
/// (mnemonic support since 3.3).
/// When set after map will update the TABTITLE attribute on the respective
/// child (since 3.10).
/// (since 3.0).
/// TABTITLE (non inheritable) (at children only): Same as TABTITLEn but set in
/// each child.
/// Works only if set before the child is added to the tabs.
pub fn getTabTitle(self: *Self, index: i32) [:0]const u8 {
return interop.getStrAttribute(self, "TABTITLE", .{index});
}
///
/// TABTITLEn (non inheritable): Contains the text to be shown in the
/// respective tab title.
/// n starts at 0.
/// If this value is NULL, it will remain empty.
/// The "&" character can be used to define a mnemonic, the next character will
/// be used as key.
/// Use "&&" to show the "&" character instead on defining a mnemonic.
/// The button can be activated from any control in the dialog using the
/// "Alt+key" combination.
/// (mnemonic support since 3.3).
/// When set after map will update the TABTITLE attribute on the respective
/// child (since 3.10).
/// (since 3.0).
/// TABTITLE (non inheritable) (at children only): Same as TABTITLEn but set in
/// each child.
/// Works only if set before the child is added to the tabs.
pub fn setTabTitle(self: *Self, index: i32, arg: [:0]const u8) void {
interop.setStrAttribute(self, "TABTITLE", .{index}, arg);
}
pub fn setUpDateAttribfromFontCallback(self: *Self, callback: ?OnUpDateAttribfromFontFn) void {
const Handler = CallbackHandler(Self, OnUpDateAttribfromFontFn, "UPDATEATTRIBFROMFONT_CB");
Handler.setCallback(self, callback);
}
///
/// MAP_CB MAP_CB Called right after an element is mapped and its attributes
/// updated in IupMap.
/// When the element is a dialog, it is called after the layout is updated.
/// For all other elements is called before the layout is updated, so the
/// element current size will still be 0x0 during MAP_CB (since 3.14).
/// Callback int function(Ihandle *ih); [in C] ih:map_cb() -> (ret: number) [in
/// Lua] ih: identifier of the element that activated the event.
/// Affects All that have a native representation.
pub fn setMapCallback(self: *Self, callback: ?OnMapFn) void {
const Handler = CallbackHandler(Self, OnMapFn, "MAP_CB");
Handler.setCallback(self, callback);
}
///
/// DESTROY_CB DESTROY_CB Called right before an element is destroyed.
/// Callback int function(Ihandle *ih); [in C] ih:destroy_cb() -> (ret: number)
/// [in Lua] ih: identifier of the element that activated the event.
/// Notes If the dialog is visible then it is hidden before it is destroyed.
/// The callback will be called right after it is hidden.
/// The callback will be called before all other destroy procedures.
/// For instance, if the element has children then it is called before the
/// children are destroyed.
/// For language binding implementations use the callback name "LDESTROY_CB" to
/// release memory allocated by the binding for the element.
/// Also the callback will be called before the language callback.
/// Affects All.
pub fn setDestroyCallback(self: *Self, callback: ?OnDestroyFn) void {
const Handler = CallbackHandler(Self, OnDestroyFn, "DESTROY_CB");
Handler.setCallback(self, callback);
}
///
/// UNMAP_CB UNMAP_CB Called right before an element is unmapped.
/// Callback int function(Ihandle *ih); [in C] ih:unmap_cb() -> (ret: number)
/// [in Lua] ih: identifier of the element that activated the event.
/// Affects All that have a native representation.
pub fn setUnmapCallback(self: *Self, callback: ?OnUnmapFn) void {
const Handler = CallbackHandler(Self, OnUnmapFn, "UNMAP_CB");
Handler.setCallback(self, callback);
}
pub fn setLDestroyCallback(self: *Self, callback: ?OnLDestroyFn) void {
const Handler = CallbackHandler(Self, OnLDestroyFn, "LDESTROY_CB");
Handler.setCallback(self, callback);
}
pub fn setPostMessageCallback(self: *Self, callback: ?OnPostMessageFn) void {
const Handler = CallbackHandler(Self, OnPostMessageFn, "POSTMESSAGE_CB");
Handler.setCallback(self, callback);
}
};
test "MultiBox HandleName" {
try iup.MainLoop.open();
defer iup.MainLoop.close();
var item = try (iup.MultiBox.init().setHandleName("Hello").unwrap());
defer item.deinit();
var ret = item.getHandleName();
try std.testing.expect(std.mem.eql(u8, ret, "Hello"));
}
test "MultiBox MaxSize" {
try iup.MainLoop.open();
defer iup.MainLoop.close();
var item = try (iup.MultiBox.init().setMaxSize(9, 10).unwrap());
defer item.deinit();
var ret = item.getMaxSize();
try std.testing.expect(ret.width != null and ret.width.? == 9 and ret.height != null and ret.height.? == 10);
}
test "MultiBox Position" {
try iup.MainLoop.open();
defer iup.MainLoop.close();
var item = try (iup.MultiBox.init().setPosition(9, 10).unwrap());
defer item.deinit();
var ret = item.getPosition();
try std.testing.expect(ret.x == 9 and ret.y == 10);
}
test "MultiBox CanFocus" {
try iup.MainLoop.open();
defer iup.MainLoop.close();
var item = try (iup.MultiBox.init().setCanFocus(true).unwrap());
defer item.deinit();
var ret = item.getCanFocus();
try std.testing.expect(ret == true);
}
test "MultiBox Visible" {
try iup.MainLoop.open();
defer iup.MainLoop.close();
var item = try (iup.MultiBox.init().setVisible(true).unwrap());
defer item.deinit();
var ret = item.getVisible();
try std.testing.expect(ret == true);
}
test "MultiBox Theme" {
try iup.MainLoop.open();
defer iup.MainLoop.close();
var item = try (iup.MultiBox.init().setTheme("Hello").unwrap());
defer item.deinit();
var ret = item.getTheme();
try std.testing.expect(std.mem.eql(u8, ret, "Hello"));
}
test "MultiBox CMargin" {
try iup.MainLoop.open();
defer iup.MainLoop.close();
var item = try (iup.MultiBox.init().setCMargin(9, 10).unwrap());
defer item.deinit();
var ret = item.getCMargin();
try std.testing.expect(ret.horiz == 9 and ret.vert == 10);
}
test "MultiBox Expand" {
try iup.MainLoop.open();
defer iup.MainLoop.close();
var item = try (iup.MultiBox.init().setExpand(.Yes).unwrap());
defer item.deinit();
var ret = item.getExpand();
try std.testing.expect(ret != null and ret.? == .Yes);
}
test "MultiBox Size" {
try iup.MainLoop.open();
defer iup.MainLoop.close();
var item = try (iup.MultiBox.init().setSize(9, 10).unwrap());
defer item.deinit();
var ret = item.getSize();
try std.testing.expect(ret.width != null and ret.width.? == 9 and ret.height != null and ret.height.? == 10);
}
test "MultiBox Orientation" {
try iup.MainLoop.open();
defer iup.MainLoop.close();
var item = try (iup.MultiBox.init().setOrientation(.Horizontal).unwrap());
defer item.deinit();
var ret = item.getOrientation();
try std.testing.expect(ret != null and ret.? == .Horizontal);
}
test "MultiBox FontSize" {
try iup.MainLoop.open();
defer iup.MainLoop.close();
var item = try (iup.MultiBox.init().setFontSize(42).unwrap());
defer item.deinit();
var ret = item.getFontSize();
try std.testing.expect(ret == 42);
}
test "MultiBox UserSize" {
try iup.MainLoop.open();
defer iup.MainLoop.close();
var item = try (iup.MultiBox.init().setUserSize(9, 10).unwrap());
defer item.deinit();
var ret = item.getUserSize();
try std.testing.expect(ret.width != null and ret.width.? == 9 and ret.height != null and ret.height.? == 10);
}
test "MultiBox PropagateFocus" {
try iup.MainLoop.open();
defer iup.MainLoop.close();
var item = try (iup.MultiBox.init().setPropagateFocus(true).unwrap());
defer item.deinit();
var ret = item.getPropagateFocus();
try std.testing.expect(ret == true);
}
test "MultiBox Floating" {
try iup.MainLoop.open();
defer iup.MainLoop.close();
var item = try (iup.MultiBox.init().setFloating(.Yes).unwrap());
defer item.deinit();
var ret = item.getFloating();
try std.testing.expect(ret != null and ret.? == .Yes);
}
test "MultiBox NMargin" {
try iup.MainLoop.open();
defer iup.MainLoop.close();
var item = try (iup.MultiBox.init().setNMargin(9, 10).unwrap());
defer item.deinit();
var ret = item.getNMargin();
try std.testing.expect(ret.horiz == 9 and ret.vert == 10);
}
test "MultiBox NormalizerGroup" {
try iup.MainLoop.open();
defer iup.MainLoop.close();
var item = try (iup.MultiBox.init().setNormalizerGroup("Hello").unwrap());
defer item.deinit();
var ret = item.getNormalizerGroup();
try std.testing.expect(std.mem.eql(u8, ret, "Hello"));
}
test "MultiBox RasterSize" {
try iup.MainLoop.open();
defer iup.MainLoop.close();
var item = try (iup.MultiBox.init().setRasterSize(9, 10).unwrap());
defer item.deinit();
var ret = item.getRasterSize();
try std.testing.expect(ret.width != null and ret.width.? == 9 and ret.height != null and ret.height.? == 10);
}
test "MultiBox FontFace" {
try iup.MainLoop.open();
defer iup.MainLoop.close();
var item = try (iup.MultiBox.init().setFontFace("Hello").unwrap());
defer item.deinit();
var ret = item.getFontFace();
try std.testing.expect(std.mem.eql(u8, ret, "Hello"));
}
test "MultiBox Name" {
try iup.MainLoop.open();
defer iup.MainLoop.close();
var item = try (iup.MultiBox.init().setName("Hello").unwrap());
defer item.deinit();
var ret = item.getName();
try std.testing.expect(std.mem.eql(u8, ret, "Hello"));
}
test "MultiBox Active" {
try iup.MainLoop.open();
defer iup.MainLoop.close();
var item = try (iup.MultiBox.init().setActive(true).unwrap());
defer item.deinit();
var ret = item.getActive();
try std.testing.expect(ret == true);
}
test "MultiBox ExpandWeight" {
try iup.MainLoop.open();
defer iup.MainLoop.close();
var item = try (iup.MultiBox.init().setExpandWeight(3.14).unwrap());
defer item.deinit();
var ret = item.getExpandWeight();
try std.testing.expect(ret == @as(f64, 3.14));
}
test "MultiBox MinSize" {
try iup.MainLoop.open();
defer iup.MainLoop.close();
var item = try (iup.MultiBox.init().setMinSize(9, 10).unwrap());
defer item.deinit();
var ret = item.getMinSize();
try std.testing.expect(ret.width != null and ret.width.? == 9 and ret.height != null and ret.height.? == 10);
}
test "MultiBox NTheme" {
try iup.MainLoop.open();
defer iup.MainLoop.close();
var item = try (iup.MultiBox.init().setNTheme("Hello").unwrap());
defer item.deinit();
var ret = item.getNTheme();
try std.testing.expect(std.mem.eql(u8, ret, "Hello"));
}
test "MultiBox FontStyle" {
try iup.MainLoop.open();
defer iup.MainLoop.close();
var item = try (iup.MultiBox.init().setFontStyle("Hello").unwrap());
defer item.deinit();
var ret = item.getFontStyle();
try std.testing.expect(std.mem.eql(u8, ret, "Hello"));
}
test "MultiBox NcMargin" {
try iup.MainLoop.open();
defer iup.MainLoop.close();
var item = try (iup.MultiBox.init().setNcMargin(9, 10).unwrap());
defer item.deinit();
var ret = item.getNcMargin();
try std.testing.expect(ret.horiz == 9 and ret.vert == 10);
}
test "MultiBox Margin" {
try iup.MainLoop.open();
defer iup.MainLoop.close();
var item = try (iup.MultiBox.init().setMargin(9, 10).unwrap());
defer item.deinit();
var ret = item.getMargin();
try std.testing.expect(ret.horiz == 9 and ret.vert == 10);
}
test "MultiBox Font" {
try iup.MainLoop.open();
defer iup.MainLoop.close();
var item = try (iup.MultiBox.init().setFont("Hello").unwrap());
defer item.deinit();
var ret = item.getFont();
try std.testing.expect(std.mem.eql(u8, ret, "Hello"));
} | src/elements/multi_box.zig |
pub const EC_VARIANT_TYPE_MASK = @as(u32, 127);
pub const EC_VARIANT_TYPE_ARRAY = @as(u32, 128);
pub const EC_READ_ACCESS = @as(u32, 1);
pub const EC_WRITE_ACCESS = @as(u32, 2);
pub const EC_OPEN_ALWAYS = @as(u32, 0);
pub const EC_CREATE_NEW = @as(u32, 1);
pub const EC_OPEN_EXISTING = @as(u32, 2);
//--------------------------------------------------------------------------------
// Section: Types (10)
//--------------------------------------------------------------------------------
pub const EC_SUBSCRIPTION_PROPERTY_ID = enum(i32) {
Enabled = 0,
EventSources = 1,
EventSourceAddress = 2,
EventSourceEnabled = 3,
EventSourceUserName = 4,
EventSourcePassword = 5,
Description = 6,
URI = 7,
ConfigurationMode = 8,
Expires = 9,
Query = 10,
TransportName = 11,
TransportPort = 12,
DeliveryMode = 13,
DeliveryMaxItems = 14,
DeliveryMaxLatencyTime = 15,
HeartbeatInterval = 16,
Locale = 17,
ContentFormat = 18,
LogFile = 19,
PublisherName = 20,
CredentialsType = 21,
CommonUserName = 22,
CommonPassword = 23,
HostName = 24,
ReadExistingEvents = 25,
Dialect = 26,
Type = 27,
AllowedIssuerCAs = 28,
AllowedSubjects = 29,
DeniedSubjects = 30,
AllowedSourceDomainComputers = 31,
PropertyIdEND = 32,
};
pub const EcSubscriptionEnabled = EC_SUBSCRIPTION_PROPERTY_ID.Enabled;
pub const EcSubscriptionEventSources = EC_SUBSCRIPTION_PROPERTY_ID.EventSources;
pub const EcSubscriptionEventSourceAddress = EC_SUBSCRIPTION_PROPERTY_ID.EventSourceAddress;
pub const EcSubscriptionEventSourceEnabled = EC_SUBSCRIPTION_PROPERTY_ID.EventSourceEnabled;
pub const EcSubscriptionEventSourceUserName = EC_SUBSCRIPTION_PROPERTY_ID.EventSourceUserName;
pub const EcSubscriptionEventSourcePassword = EC_SUBSCRIPTION_PROPERTY_ID.EventSourcePassword;
pub const EcSubscriptionDescription = EC_SUBSCRIPTION_PROPERTY_ID.Description;
pub const EcSubscriptionURI = EC_SUBSCRIPTION_PROPERTY_ID.URI;
pub const EcSubscriptionConfigurationMode = EC_SUBSCRIPTION_PROPERTY_ID.ConfigurationMode;
pub const EcSubscriptionExpires = EC_SUBSCRIPTION_PROPERTY_ID.Expires;
pub const EcSubscriptionQuery = EC_SUBSCRIPTION_PROPERTY_ID.Query;
pub const EcSubscriptionTransportName = EC_SUBSCRIPTION_PROPERTY_ID.TransportName;
pub const EcSubscriptionTransportPort = EC_SUBSCRIPTION_PROPERTY_ID.TransportPort;
pub const EcSubscriptionDeliveryMode = EC_SUBSCRIPTION_PROPERTY_ID.DeliveryMode;
pub const EcSubscriptionDeliveryMaxItems = EC_SUBSCRIPTION_PROPERTY_ID.DeliveryMaxItems;
pub const EcSubscriptionDeliveryMaxLatencyTime = EC_SUBSCRIPTION_PROPERTY_ID.DeliveryMaxLatencyTime;
pub const EcSubscriptionHeartbeatInterval = EC_SUBSCRIPTION_PROPERTY_ID.HeartbeatInterval;
pub const EcSubscriptionLocale = EC_SUBSCRIPTION_PROPERTY_ID.Locale;
pub const EcSubscriptionContentFormat = EC_SUBSCRIPTION_PROPERTY_ID.ContentFormat;
pub const EcSubscriptionLogFile = EC_SUBSCRIPTION_PROPERTY_ID.LogFile;
pub const EcSubscriptionPublisherName = EC_SUBSCRIPTION_PROPERTY_ID.PublisherName;
pub const EcSubscriptionCredentialsType = EC_SUBSCRIPTION_PROPERTY_ID.CredentialsType;
pub const EcSubscriptionCommonUserName = EC_SUBSCRIPTION_PROPERTY_ID.CommonUserName;
pub const EcSubscriptionCommonPassword = EC_SUBSCRIPTION_PROPERTY_ID.CommonPassword;
pub const EcSubscriptionHostName = EC_SUBSCRIPTION_PROPERTY_ID.HostName;
pub const EcSubscriptionReadExistingEvents = EC_SUBSCRIPTION_PROPERTY_ID.ReadExistingEvents;
pub const EcSubscriptionDialect = EC_SUBSCRIPTION_PROPERTY_ID.Dialect;
pub const EcSubscriptionType = EC_SUBSCRIPTION_PROPERTY_ID.Type;
pub const EcSubscriptionAllowedIssuerCAs = EC_SUBSCRIPTION_PROPERTY_ID.AllowedIssuerCAs;
pub const EcSubscriptionAllowedSubjects = EC_SUBSCRIPTION_PROPERTY_ID.AllowedSubjects;
pub const EcSubscriptionDeniedSubjects = EC_SUBSCRIPTION_PROPERTY_ID.DeniedSubjects;
pub const EcSubscriptionAllowedSourceDomainComputers = EC_SUBSCRIPTION_PROPERTY_ID.AllowedSourceDomainComputers;
pub const EcSubscriptionPropertyIdEND = EC_SUBSCRIPTION_PROPERTY_ID.PropertyIdEND;
pub const EC_SUBSCRIPTION_CREDENTIALS_TYPE = enum(i32) {
Default = 0,
Negotiate = 1,
Digest = 2,
Basic = 3,
LocalMachine = 4,
};
pub const EcSubscriptionCredDefault = EC_SUBSCRIPTION_CREDENTIALS_TYPE.Default;
pub const EcSubscriptionCredNegotiate = EC_SUBSCRIPTION_CREDENTIALS_TYPE.Negotiate;
pub const EcSubscriptionCredDigest = EC_SUBSCRIPTION_CREDENTIALS_TYPE.Digest;
pub const EcSubscriptionCredBasic = EC_SUBSCRIPTION_CREDENTIALS_TYPE.Basic;
pub const EcSubscriptionCredLocalMachine = EC_SUBSCRIPTION_CREDENTIALS_TYPE.LocalMachine;
pub const EC_SUBSCRIPTION_TYPE = enum(i32) {
SourceInitiated = 0,
CollectorInitiated = 1,
};
pub const EcSubscriptionTypeSourceInitiated = EC_SUBSCRIPTION_TYPE.SourceInitiated;
pub const EcSubscriptionTypeCollectorInitiated = EC_SUBSCRIPTION_TYPE.CollectorInitiated;
pub const EC_SUBSCRIPTION_RUNTIME_STATUS_INFO_ID = enum(i32) {
Active = 0,
LastError = 1,
LastErrorMessage = 2,
LastErrorTime = 3,
NextRetryTime = 4,
EventSources = 5,
LastHeartbeatTime = 6,
InfoIdEND = 7,
};
pub const EcSubscriptionRunTimeStatusActive = EC_SUBSCRIPTION_RUNTIME_STATUS_INFO_ID.Active;
pub const EcSubscriptionRunTimeStatusLastError = EC_SUBSCRIPTION_RUNTIME_STATUS_INFO_ID.LastError;
pub const EcSubscriptionRunTimeStatusLastErrorMessage = EC_SUBSCRIPTION_RUNTIME_STATUS_INFO_ID.LastErrorMessage;
pub const EcSubscriptionRunTimeStatusLastErrorTime = EC_SUBSCRIPTION_RUNTIME_STATUS_INFO_ID.LastErrorTime;
pub const EcSubscriptionRunTimeStatusNextRetryTime = EC_SUBSCRIPTION_RUNTIME_STATUS_INFO_ID.NextRetryTime;
pub const EcSubscriptionRunTimeStatusEventSources = EC_SUBSCRIPTION_RUNTIME_STATUS_INFO_ID.EventSources;
pub const EcSubscriptionRunTimeStatusLastHeartbeatTime = EC_SUBSCRIPTION_RUNTIME_STATUS_INFO_ID.LastHeartbeatTime;
pub const EcSubscriptionRunTimeStatusInfoIdEND = EC_SUBSCRIPTION_RUNTIME_STATUS_INFO_ID.InfoIdEND;
pub const EC_VARIANT_TYPE = enum(i32) {
TypeNull = 0,
TypeBoolean = 1,
TypeUInt32 = 2,
TypeDateTime = 3,
TypeString = 4,
ObjectArrayPropertyHandle = 5,
};
pub const EcVarTypeNull = EC_VARIANT_TYPE.TypeNull;
pub const EcVarTypeBoolean = EC_VARIANT_TYPE.TypeBoolean;
pub const EcVarTypeUInt32 = EC_VARIANT_TYPE.TypeUInt32;
pub const EcVarTypeDateTime = EC_VARIANT_TYPE.TypeDateTime;
pub const EcVarTypeString = EC_VARIANT_TYPE.TypeString;
pub const EcVarObjectArrayPropertyHandle = EC_VARIANT_TYPE.ObjectArrayPropertyHandle;
pub const EC_VARIANT = extern struct {
Anonymous: extern union {
BooleanVal: BOOL,
UInt32Val: u32,
DateTimeVal: u64,
StringVal: ?[*:0]const u16,
BinaryVal: ?*u8,
BooleanArr: ?*BOOL,
Int32Arr: ?*i32,
StringArr: ?*?PWSTR,
PropertyHandleVal: isize,
},
Count: u32,
Type: u32,
};
pub const EC_SUBSCRIPTION_CONFIGURATION_MODE = enum(i32) {
Normal = 0,
Custom = 1,
MinLatency = 2,
MinBandwidth = 3,
};
pub const EcConfigurationModeNormal = EC_SUBSCRIPTION_CONFIGURATION_MODE.Normal;
pub const EcConfigurationModeCustom = EC_SUBSCRIPTION_CONFIGURATION_MODE.Custom;
pub const EcConfigurationModeMinLatency = EC_SUBSCRIPTION_CONFIGURATION_MODE.MinLatency;
pub const EcConfigurationModeMinBandwidth = EC_SUBSCRIPTION_CONFIGURATION_MODE.MinBandwidth;
pub const EC_SUBSCRIPTION_DELIVERY_MODE = enum(i32) {
ll = 1,
sh = 2,
};
pub const EcDeliveryModePull = EC_SUBSCRIPTION_DELIVERY_MODE.ll;
pub const EcDeliveryModePush = EC_SUBSCRIPTION_DELIVERY_MODE.sh;
pub const EC_SUBSCRIPTION_CONTENT_FORMAT = enum(i32) {
Events = 1,
RenderedText = 2,
};
pub const EcContentFormatEvents = EC_SUBSCRIPTION_CONTENT_FORMAT.Events;
pub const EcContentFormatRenderedText = EC_SUBSCRIPTION_CONTENT_FORMAT.RenderedText;
pub const EC_SUBSCRIPTION_RUNTIME_STATUS_ACTIVE_STATUS = enum(i32) {
Disabled = 1,
Active = 2,
Inactive = 3,
Trying = 4,
};
pub const EcRuntimeStatusActiveStatusDisabled = EC_SUBSCRIPTION_RUNTIME_STATUS_ACTIVE_STATUS.Disabled;
pub const EcRuntimeStatusActiveStatusActive = EC_SUBSCRIPTION_RUNTIME_STATUS_ACTIVE_STATUS.Active;
pub const EcRuntimeStatusActiveStatusInactive = EC_SUBSCRIPTION_RUNTIME_STATUS_ACTIVE_STATUS.Inactive;
pub const EcRuntimeStatusActiveStatusTrying = EC_SUBSCRIPTION_RUNTIME_STATUS_ACTIVE_STATUS.Trying;
//--------------------------------------------------------------------------------
// Section: Functions (15)
//--------------------------------------------------------------------------------
// TODO: this type is limited to platform 'windows6.0.6000'
pub extern "WecApi" fn EcOpenSubscriptionEnum(
Flags: u32,
) callconv(@import("std").os.windows.WINAPI) isize;
// TODO: this type is limited to platform 'windows6.0.6000'
pub extern "WecApi" fn EcEnumNextSubscription(
SubscriptionEnum: isize,
SubscriptionNameBufferSize: u32,
SubscriptionNameBuffer: ?[*:0]u16,
SubscriptionNameBufferUsed: ?*u32,
) callconv(@import("std").os.windows.WINAPI) BOOL;
// TODO: this type is limited to platform 'windows6.0.6000'
pub extern "WecApi" fn EcOpenSubscription(
SubscriptionName: ?[*:0]const u16,
AccessMask: u32,
Flags: u32,
) callconv(@import("std").os.windows.WINAPI) isize;
// TODO: this type is limited to platform 'windows6.0.6000'
pub extern "WecApi" fn EcSetSubscriptionProperty(
Subscription: isize,
PropertyId: EC_SUBSCRIPTION_PROPERTY_ID,
Flags: u32,
PropertyValue: ?*EC_VARIANT,
) callconv(@import("std").os.windows.WINAPI) BOOL;
// TODO: this type is limited to platform 'windows6.0.6000'
pub extern "WecApi" fn EcGetSubscriptionProperty(
Subscription: isize,
PropertyId: EC_SUBSCRIPTION_PROPERTY_ID,
Flags: u32,
PropertyValueBufferSize: u32,
PropertyValueBuffer: ?*EC_VARIANT,
PropertyValueBufferUsed: ?*u32,
) callconv(@import("std").os.windows.WINAPI) BOOL;
// TODO: this type is limited to platform 'windows6.0.6000'
pub extern "WecApi" fn EcSaveSubscription(
Subscription: isize,
Flags: u32,
) callconv(@import("std").os.windows.WINAPI) BOOL;
// TODO: this type is limited to platform 'windows6.0.6000'
pub extern "WecApi" fn EcDeleteSubscription(
SubscriptionName: ?[*:0]const u16,
Flags: u32,
) callconv(@import("std").os.windows.WINAPI) BOOL;
// TODO: this type is limited to platform 'windows6.0.6000'
pub extern "WecApi" fn EcGetObjectArraySize(
ObjectArray: isize,
ObjectArraySize: ?*u32,
) callconv(@import("std").os.windows.WINAPI) BOOL;
// TODO: this type is limited to platform 'windows6.0.6000'
pub extern "WecApi" fn EcSetObjectArrayProperty(
ObjectArray: isize,
PropertyId: EC_SUBSCRIPTION_PROPERTY_ID,
ArrayIndex: u32,
Flags: u32,
PropertyValue: ?*EC_VARIANT,
) callconv(@import("std").os.windows.WINAPI) BOOL;
// TODO: this type is limited to platform 'windows6.0.6000'
pub extern "WecApi" fn EcGetObjectArrayProperty(
ObjectArray: isize,
PropertyId: EC_SUBSCRIPTION_PROPERTY_ID,
ArrayIndex: u32,
Flags: u32,
PropertyValueBufferSize: u32,
PropertyValueBuffer: ?*EC_VARIANT,
PropertyValueBufferUsed: ?*u32,
) callconv(@import("std").os.windows.WINAPI) BOOL;
// TODO: this type is limited to platform 'windows6.0.6000'
pub extern "WecApi" fn EcInsertObjectArrayElement(
ObjectArray: isize,
ArrayIndex: u32,
) callconv(@import("std").os.windows.WINAPI) BOOL;
// TODO: this type is limited to platform 'windows6.0.6000'
pub extern "WecApi" fn EcRemoveObjectArrayElement(
ObjectArray: isize,
ArrayIndex: u32,
) callconv(@import("std").os.windows.WINAPI) BOOL;
// TODO: this type is limited to platform 'windows6.0.6000'
pub extern "WecApi" fn EcGetSubscriptionRunTimeStatus(
SubscriptionName: ?[*:0]const u16,
StatusInfoId: EC_SUBSCRIPTION_RUNTIME_STATUS_INFO_ID,
EventSourceName: ?[*:0]const u16,
Flags: u32,
StatusValueBufferSize: u32,
StatusValueBuffer: ?*EC_VARIANT,
StatusValueBufferUsed: ?*u32,
) callconv(@import("std").os.windows.WINAPI) BOOL;
// TODO: this type is limited to platform 'windows6.0.6000'
pub extern "WecApi" fn EcRetrySubscription(
SubscriptionName: ?[*:0]const u16,
EventSourceName: ?[*:0]const u16,
Flags: u32,
) callconv(@import("std").os.windows.WINAPI) BOOL;
// TODO: this type is limited to platform 'windows6.0.6000'
pub extern "WecApi" fn EcClose(
Object: isize,
) callconv(@import("std").os.windows.WINAPI) BOOL;
//--------------------------------------------------------------------------------
// Section: Unicode Aliases (0)
//--------------------------------------------------------------------------------
const thismodule = @This();
pub usingnamespace switch (@import("../zig.zig").unicode_mode) {
.ansi => struct {
},
.wide => struct {
},
.unspecified => if (@import("builtin").is_test) struct {
} else struct {
},
};
//--------------------------------------------------------------------------------
// Section: Imports (2)
//--------------------------------------------------------------------------------
const BOOL = @import("../foundation.zig").BOOL;
const PWSTR = @import("../foundation.zig").PWSTR;
test {
@setEvalBranchQuota(
@import("std").meta.declarations(@This()).len * 3
);
// reference all the pub declarations
if (!@import("builtin").is_test) return;
inline for (@import("std").meta.declarations(@This())) |decl| {
if (decl.is_pub) {
_ = decl;
}
}
} | win32/system/event_collector.zig |
const std = @import("std");
const amqp = @import("zamqp");
const bytes = amqp.bytes_t.init;
const zone2json = @import("zone2json.zig");
fn logOrPanic(err: anyerror) void {
std.log.err("{}", .{err});
switch (err) {
error.OutOfMemory => {
// librabbitmq docs say it is not designed to handle OOM
std.debug.panic("out of memory", .{});
},
error.Unexpected => std.debug.panic("unexpected error", .{}),
else => {},
}
}
const ChannelState = struct {
unacked_count: u16 = 0,
last_delivery_tag: u64 = 0,
};
fn listen(alloc: *std.mem.Allocator, channel: amqp.Channel, state: *ChannelState, settings: ChannelSettings) !void {
channel.maybe_release_buffers();
var zero_timeval = std.c.timeval{ .tv_sec = 0, .tv_usec = 0 };
const block = state.unacked_count == 0;
var timeout = if (block) null else &zero_timeval;
var envelope = channel.connection.consume_message(timeout, 0) catch |err| switch (err) {
// a different frame needs to be read
error.UnexpectedState => {
const frame = try channel.connection.simple_wait_frame(null);
if (frame.frame_type == .METHOD) {
switch (frame.payload.method.id) {
.CHANNEL_CLOSE => return error.ChannelClosed,
.CONNECTION_CLOSE => return error.ConnectionClosed,
else => return error.UnexpectedMethod,
}
} else return error.UnexpectedFrame;
},
error.Timeout => {
try channel.basic_ack(state.last_delivery_tag, true);
state.unacked_count = 0;
std.log.debug("no messages, acked partial batch (delivery tag: {d})", .{state.last_delivery_tag});
return;
},
else => return err,
};
defer envelope.destroy();
const reply_to = envelope.message.properties.get(.reply_to) orelse {
try channel.basic_reject(envelope.delivery_tag, false);
return;
};
state.unacked_count += 1;
state.last_delivery_tag = envelope.delivery_tag;
var json = try std.ArrayList(u8).initCapacity(alloc, 4096);
defer json.deinit();
const valid_content_type = if (envelope.message.properties.get(.content_type)) |content_type|
std.mem.eql(u8, content_type.slice().?, "text/dns")
else
false;
if (valid_content_type) {
try zone2json.convertApi(envelope.message.body.slice().?, &json);
} else {
json.appendSliceAssumeCapacity(
\\{"error":"invalid content type"}
);
}
var properties = amqp.BasicProperties.init(.{
.content_type = bytes("application/json"),
});
if (envelope.message.properties.get(.correlation_id)) |id| {
properties.set(.correlation_id, id);
}
try channel.basic_publish(
bytes(""),
reply_to,
bytes(json.items),
properties,
.{},
);
if (state.unacked_count == settings.max_batch) {
try channel.basic_ack(state.last_delivery_tag, true);
state.unacked_count = 0;
std.log.debug("acked full batch (delivery tag: {d})", .{state.last_delivery_tag});
}
}
pub const ChannelSettings = struct {
queue: []const u8,
prefetch_count: u16,
max_batch: u16,
};
fn setupChannel(channel: amqp.Channel, settings: ChannelSettings) !void {
std.log.info("opening channel {d}", .{channel.number});
_ = try channel.open();
errdefer channel.close(.REPLY_SUCCESS) catch |err| logOrPanic(err);
std.log.info("consuming from queue {s}", .{settings.queue});
try channel.basic_qos(0, settings.prefetch_count, false);
_ = try channel.basic_consume(bytes(settings.queue), .{});
std.log.info("channel set up", .{});
}
pub const ConnectionSettings = struct {
port: c_int,
host: [*:0]const u8,
vhost: [*:0]const u8,
auth: amqp.Connection.SaslAuth,
/// null disables TLS
tls: ?struct {
ca_cert_path: [*:0]const u8,
keys: ?struct {
cert_path: [*:0]const u8,
key_path: [*:0]const u8,
},
verify_peer: bool,
verify_hostname: bool,
},
heartbeat: c_int,
};
fn setupConnection(conn: amqp.Connection, settings: ConnectionSettings) !void {
std.log.info("connecting to {s}:{d}", .{ settings.host, settings.port });
if (settings.tls) |tls| {
const sock = try amqp.SslSocket.new(conn);
sock.set_verify_peer(tls.verify_peer);
sock.set_verify_hostname(tls.verify_hostname);
try sock.set_cacert(tls.ca_cert_path);
if (tls.keys) |keys|
try sock.set_key(keys.cert_path, keys.key_path);
try sock.open(settings.host, settings.port, null);
} else {
const sock = try amqp.TcpSocket.new(conn);
try sock.open(settings.host, settings.port, null);
}
errdefer conn.close(.REPLY_SUCCESS) catch |err| logOrPanic(err);
std.log.info("logging into vhost {s} as {s}", .{ settings.vhost, settings.auth.plain.username });
try conn.login(settings.vhost, settings.auth, .{ .heartbeat = settings.heartbeat });
std.log.info("connection set up", .{});
}
const ExponentialBackoff = struct {
ns: u64,
random: *std.rand.Random,
timer: std.time.Timer,
const min = 1 * std.time.ns_per_s;
const max = 32 * std.time.ns_per_s;
const jitter = 1 * std.time.ns_per_s;
pub fn init(random: *std.rand.Random) !ExponentialBackoff {
return ExponentialBackoff{
.timer = try std.time.Timer.start(),
.random = random,
.ns = min,
};
}
pub fn sleep(self: *ExponentialBackoff) void {
self.timer.reset();
const to_sleep_ns: u64 = self.ns + self.random.uintLessThanBiased(u64, jitter);
std.time.sleep(@intCast(u64, to_sleep_ns));
while (true) {
const timer_val = self.timer.read();
if(timer_val >= to_sleep_ns) break;
// Spurious wakeup
std.time.sleep(@intCast(u64, to_sleep_ns - timer_val));
}
if (self.ns < max) self.ns *= 2;
}
pub fn reset(self: *ExponentialBackoff) void {
self.ns = min;
}
};
pub fn run(alloc: *std.mem.Allocator, con_settings: ConnectionSettings, chan_settings: ChannelSettings) !void {
var conn = try amqp.Connection.new();
defer conn.destroy() catch |err| logOrPanic(err);
var rng = std.rand.DefaultPrng.init(std.crypto.random.int(u64));
var backoff = try ExponentialBackoff.init(&rng.random);
connection: while (true) {
setupConnection(conn, con_settings) catch |err| {
logOrPanic(err);
backoff.sleep();
continue :connection;
};
defer conn.close(.REPLY_SUCCESS) catch |err| logOrPanic(err);
channel: while (true) {
const channel = conn.channel(1);
setupChannel(channel, chan_settings) catch |err| {
logOrPanic(err);
backoff.sleep();
continue :connection;
};
defer channel.close(.REPLY_SUCCESS) catch |err| logOrPanic(err);
var state = ChannelState{};
while (true) {
listen(alloc, channel, &state, chan_settings) catch |err| {
logOrPanic(err);
backoff.sleep();
if (err == error.ChannelClosed) continue :channel;
continue :connection;
};
backoff.reset();
}
}
}
} | src/server.zig |
const std = @import("std");
const xml = @import("xml.zig");
const wayland = @import("wayland.zig");
const mem = std.mem;
pub fn main() !void {
var arena = std.heap.ArenaAllocator.init(std.heap.page_allocator);
defer arena.deinit();
const allocator = arena.allocator();
const stdin = std.io.getStdIn().reader();
const input = try stdin.readAllAlloc(allocator, std.math.maxInt(usize));
defer allocator.free(input);
var protocol = try wayland.parseFile(allocator, input);
defer protocol.deinit();
var cx = Context{
.prefix = "wl_",
.out = std.ArrayList(u8).init(allocator),
.allocator = allocator,
};
try cx.emitProtocol(protocol);
try std.io.getStdOut().writer().print("{s}", .{cx.out.items});
}
const MessageKind = enum {
request,
event,
pub fn nameLower(kind: MessageKind) []const u8 {
return switch (kind) {
.request => "request",
.event => "event",
};
}
pub fn nameUpper(kind: MessageKind) []const u8 {
return switch (kind) {
.request => "Request",
.event => "Event",
};
}
};
fn isValidZigIdentifier(name: []const u8) bool {
for (name) |c, i| switch (c) {
'_', 'a'...'z', 'A'...'Z' => {},
'0'...'9' => if (i == 0) return false,
else => return false,
};
return std.zig.Token.getKeyword(name) == null;
}
const Context = struct {
prefix: []const u8,
out: std.ArrayList(u8),
allocator: mem.Allocator,
fn print(cx: *Context, comptime fmt: []const u8, args: anytype) !void {
return cx.out.writer().print(fmt, args);
}
fn trimPrefix(cx: *Context, input: []const u8) []const u8 {
var name = input;
if (mem.startsWith(u8, input, cx.prefix))
name = input[cx.prefix.len..];
return name;
}
fn recase(cx: *Context, name: []const u8, comptime initial: bool) ![]const u8 {
var new = std.ArrayList(u8).init(cx.allocator);
var upper = initial;
for (name) |c| {
if (c == '_') {
upper = true;
} else if (upper) {
try new.append(std.ascii.toUpper(c));
upper = false;
} else {
try new.append(c);
}
}
return new.toOwnedSlice();
}
fn identifier(cx: *Context, name: []const u8) ![]const u8 {
if (std.mem.eql(u8, name, "class_"))
return "class";
if (!isValidZigIdentifier(name))
return try std.fmt.allocPrint(cx.allocator, "@\"{s}\"", .{name});
return name;
}
fn snakeCase(cx: *Context, name: []const u8) ![]const u8 {
return try cx.identifier(name);
}
fn camelCase(cx: *Context, name: []const u8) ![]const u8 {
return try cx.identifier(try cx.recase(name, false));
}
fn pascalCase(cx: *Context, name: []const u8) ![]const u8 {
return try cx.identifier(try cx.recase(name, true));
}
fn argType(_: *Context, arg: wayland.Arg) ![]const u8 {
return switch (arg.kind) {
.int => "i32",
.uint => "u32",
.fixed => "f64",
.string => if (arg.allow_null) "?[:0]const u8" else "[:0]const u8",
.array => if (arg.allow_null) "?[]const u8" else "[]const u8",
.fd => "std.os.fd_t",
else => unreachable, // special
};
}
fn emitProtocol(cx: *Context, proto: wayland.Protocol) !void {
try cx.print(
\\const wl = @This();
\\const std = @import("std");
\\const wayland = @import("wayland.zig");
, .{});
for (proto.interfaces) |iface|
try cx.emitInterface(iface);
}
fn emitInterface(cx: *Context, iface: wayland.Interface) !void {
const type_name = try cx.pascalCase(cx.trimPrefix(iface.name));
try cx.print(
\\pub const {s} = struct {{
\\ id: u32,
\\ pub const interface = "{s}";
\\ pub const version = {};
, .{
type_name,
iface.name,
iface.version,
});
if (iface.requests.len != 0) {
try cx.print(
\\ pub const Request = {0s}Request;
, .{
type_name,
});
}
if (iface.events.len != 0) {
try cx.print(
\\ pub const Event = {0s}Event;
, .{
type_name,
});
}
try cx.emitDefaultHandler(iface);
try cx.emitMethods(iface, iface.requests, .request);
try cx.print(
\\}};
, .{});
try cx.emitMessageUnion(iface, iface.requests, .request);
try cx.emitMessageUnion(iface, iface.events, .event);
try cx.emitEnums(iface);
}
fn emitDefaultHandler(cx: *Context, iface: wayland.Interface) !void {
try cx.print(
\\pub fn defaultHandler(
\\ conn: *wayland.client.Connection,
\\ msg: wayland.Message,
\\ fds: *wayland.Buffer,
\\) void {{
\\ _ = conn;
\\ _ = msg;
\\ _ = fds;
, .{});
if (iface.events.len != 0) {
try cx.print(
\\const event = Event.unmarshal(conn, msg, fds);
\\const writer = std.io.getStdErr().writer();
\\@TypeOf(event).format(event, "", .{{}}, writer) catch {{}};
\\writer.print("\n", .{{}}) catch {{}};
, .{});
}
try cx.print(
\\}}
, .{});
}
fn emitMethods(cx: *Context, iface: wayland.Interface, msgs: []wayland.Message, kind: MessageKind) !void {
for (msgs) |msg|
try cx.emitMethod(iface, msg, kind);
}
fn emitMethod(cx: *Context, _: wayland.Interface, msg: wayland.Message, kind: MessageKind) !void {
try cx.print(
\\pub fn {s}(
\\ self: @This(),
\\ conn: *wayland.client.Connection,
, .{
try cx.camelCase(msg.name),
});
var return_expr: []const u8 = "";
var return_type: []const u8 = "void";
var extra_errors: []const u8 = "";
for (msg.args) |arg| {
switch (arg.kind) {
.int, .uint, .fixed, .string, .array, .fd => {
try cx.print(
\\arg_{s}: {s},
, .{
try cx.snakeCase(arg.name),
try cx.argType(arg),
});
},
.new_id => {
if (arg.interface) |iface_name| {
return_type = try cx.pascalCase(cx.trimPrefix(iface_name));
return_expr = try std.fmt.allocPrint(
cx.allocator,
"arg_{s}",
.{try cx.snakeCase(arg.name)},
);
} else {
try cx.print(
\\comptime T: anytype,
\\arg_{s}_version: u32,
, .{
try cx.snakeCase(arg.name),
});
return_type = "T";
return_expr = try std.fmt.allocPrint(
cx.allocator,
"T{{ .id = arg_{s} }}",
.{try cx.snakeCase(arg.name)},
);
}
extra_errors = ",OutOfMemory";
},
.object => {
if (arg.interface) |iface_name| {
try cx.print("arg_{s}: {s},", .{
try cx.snakeCase(arg.name),
cx.pascalCase(cx.trimPrefix(iface_name)),
});
} else {
try cx.print("arg_{s}: u32,", .{
try cx.snakeCase(arg.name),
});
}
},
}
}
try cx.print(
\\) error{{BufferFull{s}}}!{s} {{
, .{ extra_errors, return_type });
for (msg.args) |arg| {
switch (arg.kind) {
.new_id => {
if (arg.interface) |iface_name| {
try cx.print(
\\const arg_{0s}_data = try conn.object_map.create();
\\arg_{0s}_data.object.* = wayland.client.Connection.ObjectData{{
\\ .version = 1,
\\ .handler = {1s}.defaultHandler,
\\ .user_data = 0,
\\}};
\\const arg_{0s} = {1s}{{
\\ .id = arg_{0s}_data.id,
\\}};
, .{
try cx.snakeCase(arg.name),
try cx.pascalCase(cx.trimPrefix(iface_name)),
});
} else {
try cx.print(
\\const arg_{0s}_data = try conn.object_map.create();
\\arg_{0s}_data.object.* = wayland.client.Connection.ObjectData{{
\\ .version = arg_{0s}_version,
\\ .handler = T.defaultHandler,
\\ .user_data = 0,
\\}};
\\const arg_{0s} = arg_{0s}_data.id;
, .{
try cx.snakeCase(arg.name),
});
}
},
else => {},
}
}
try cx.print(
\\const {s} = {s}.{s}{{
, .{
kind.nameLower(),
kind.nameUpper(),
try cx.pascalCase(msg.name),
});
for (msg.args) |arg| {
switch (arg.kind) {
.new_id => {
if (arg.interface) |_| {} else {
try cx.print(
\\.interface = T.interface,
\\.version = arg_{0s}_version,
, .{
try cx.snakeCase(arg.name),
});
}
},
else => {},
}
try cx.print(
\\.{0s} = arg_{0s},
, .{
try cx.snakeCase(arg.name),
});
}
try cx.print(
\\}};
\\try request.marshal(self.id, &conn.wire_conn.out);
, .{});
if (return_expr.len != 0) {
try cx.print(
\\return {s};
, .{return_expr});
}
try cx.print(
\\}}
, .{});
}
fn emitMessageUnion(cx: *Context, iface: wayland.Interface, msgs: []wayland.Message, kind: MessageKind) !void {
if (msgs.len == 0)
return;
try cx.print(
\\pub const {s}{s} = union(enum(u16)) {{
\\ pub const Opcode = std.meta.Tag(@This());
, .{
try cx.pascalCase(cx.trimPrefix(iface.name)),
kind.nameUpper(),
});
for (msgs) |msg| {
try cx.print(
\\{s}: @This().{s},
, .{
try cx.snakeCase(msg.name),
try cx.pascalCase(msg.name),
});
}
for (msgs) |msg|
try cx.emitMessageStruct(iface, msg, kind);
try cx.print(
\\pub fn marshal(
\\ self: @This(),
\\ id: u32,
\\ buf: *wayland.Buffer
\\) error{{BufferFull}}!void {{
\\ return switch (self) {{
, .{});
for (msgs) |msg| {
try cx.print(
\\.{0s} => |{0s}| {0s}.marshal(id, buf),
, .{
try cx.snakeCase(msg.name),
});
}
try cx.print(
\\ }};
\\}}
, .{});
try cx.print(
\\pub fn unmarshal(
\\ conn: *wayland.client.Connection,
\\ msg: wayland.Message,
\\ fds: *wayland.Buffer,
\\) @This() {{
\\ return switch (@intToEnum(std.meta.Tag(@This()), msg.op)) {{
, .{});
for (msgs) |msg| {
try cx.print(
\\.{s} => @This(){{ .{s} = @This().{s}.unmarshal(conn, msg, fds) }},
, .{
try cx.snakeCase(msg.name),
try cx.snakeCase(msg.name),
try cx.pascalCase(msg.name),
});
}
try cx.print(
\\ }};
\\}}
, .{});
try cx.print(
\\pub fn format(
\\ self: @This(),
\\ comptime fmt: []const u8,
\\ options: std.fmt.FormatOptions,
\\ writer: anytype,
\\) !void {{
\\ return switch (self) {{
, .{});
for (msgs) |msg| {
try cx.print(
\\.{0s} => |{0s}| @TypeOf({0s}).format({0s}, fmt, options, writer),
, .{
try cx.snakeCase(msg.name),
});
}
try cx.print(
\\}};
\\}}
, .{});
try cx.print(
\\}};
, .{});
}
fn emitMessageStruct(cx: *Context, iface: wayland.Interface, msg: wayland.Message, kind: MessageKind) !void {
try cx.print(
\\pub const {s} = struct {{
, .{try cx.pascalCase(msg.name)});
for (msg.args) |arg| {
switch (arg.kind) {
.int, .uint, .fixed, .string, .array, .fd => {
try cx.print(
\\{s}: {s},
, .{
try cx.snakeCase(arg.name),
try cx.argType(arg),
});
},
.new_id => {
if (arg.interface) |iface_name| {
try cx.print("{s}: wl.{s},", .{
try cx.snakeCase(arg.name),
cx.pascalCase(cx.trimPrefix(iface_name)),
});
} else {
try cx.print("interface: []const u8, version: u32, {s}: u32,", .{
try cx.snakeCase(arg.name),
});
}
},
.object => {
if (arg.interface) |iface_name| {
try cx.print("{s}: {s}wl.{s},", .{
try cx.snakeCase(arg.name),
if (arg.allow_null) @as([]const u8, "?") else @as([]const u8, ""),
cx.pascalCase(cx.trimPrefix(iface_name)),
});
} else {
try cx.print("{s}: u32,", .{
try cx.snakeCase(arg.name),
});
}
},
}
}
try cx.emitMarshal(msg, kind);
try cx.emitUnmarshal(msg, kind);
try cx.emitFormat(iface, msg, kind);
try cx.print(
\\}};
, .{});
}
fn emitEnums(cx: *Context, iface: wayland.Interface) !void {
try cx.print(
\\pub const {s}Enum = struct {{
, .{
try cx.pascalCase(cx.trimPrefix(iface.name)),
});
for (iface.enums) |@"enum"| {
if (@"enum".bitfield)
try cx.emitBitfield(@"enum")
else
try cx.emitEnum(@"enum");
}
try cx.print(
\\}};
, .{});
}
fn emitBitfield(cx: *Context, bitfield: wayland.Enum) !void {
try cx.print(
\\pub const {s} = packed struct {{
, .{
try cx.pascalCase(bitfield.name),
});
for (bitfield.entries) |entry| {
try cx.print(
\\{s}: bool = false,
, .{
try cx.snakeCase(entry.name),
});
}
try cx.print(
\\pub fn toInt({s}: {s}) u32 {{
\\ var result: u32 = 0;
, .{
try cx.snakeCase(bitfield.name),
try cx.pascalCase(bitfield.name),
});
for (bitfield.entries) |entry| {
try cx.print(
\\if ({s}.{s})
\\ result &= {};
, .{
try cx.snakeCase(bitfield.name),
try cx.snakeCase(entry.name),
entry.value,
});
}
try cx.print(
\\ return result;
\\}}
, .{});
try cx.print(
\\pub fn fromInt(int: u32) {s} {{
\\ return {s}{{
, .{
try cx.pascalCase(bitfield.name),
try cx.pascalCase(bitfield.name),
});
for (bitfield.entries) |entry| {
try cx.print(
\\.{s} = (int & {}) != 0,
, .{
try cx.snakeCase(entry.name),
entry.value,
});
}
try cx.print(
\\}};
\\}}
, .{});
try cx.print(
\\}};
, .{});
}
fn emitEnum(cx: *Context, @"enum": wayland.Enum) !void {
try cx.print(
\\pub const {s} = enum(u32) {{
, .{
try cx.pascalCase(@"enum".name),
});
for (@"enum".entries) |entry| {
try cx.print(
\\{s} = {},
, .{
try cx.snakeCase(entry.name),
entry.value,
});
}
try cx.print(
\\ pub fn toInt({s}: {s}) u32 {{
\\ return @enumToInt({s});
\\ }}
\\ pub fn fromInt(int: u32) {s} {{
\\ return @intToEnum({s}, int);
\\ }}
\\}};
, .{
try cx.snakeCase(@"enum".name),
try cx.pascalCase(@"enum".name),
try cx.snakeCase(@"enum".name),
try cx.pascalCase(@"enum".name),
try cx.pascalCase(@"enum".name),
});
}
fn emitMarshal(cx: *Context, msg: wayland.Message, _: MessageKind) !void {
try cx.print(
\\pub fn marshal(
\\ self: @This(),
\\ id: u32,
\\ buf: *wayland.Buffer,
\\) error{{BufferFull}}!void {{
\\ _ = self;
, .{});
var size_bytes: u32 = 8;
var size_fds: u32 = 0;
var extra = std.ArrayList(u8).init(cx.allocator);
for (msg.args) |arg| switch (arg.kind) {
.new_id => {
if (arg.interface == null) {
size_bytes += 12;
try extra.writer().print("+ ((self.interface.len + 3) / 4 * 4)", .{});
} else {
size_bytes += 4;
}
},
.int, .uint, .fixed, .object => {
size_bytes += 4;
},
.string, .array => {
size_bytes += 4;
if (arg.allow_null) {
try extra.writer().print("+ (if (self.{s}) |_arg| ((_arg.len + 3) / 4 * 4) else 0)", .{
try cx.snakeCase(arg.name),
});
} else {
try extra.writer().print("+ ((self.{s}.len + 3) / 4 * 4)", .{
try cx.snakeCase(arg.name),
});
}
},
.fd => {
size_fds += 1;
},
};
try cx.print(
\\const len: usize = {0}{1s};
\\if (buf.bytes.writableLength() < len)
\\ return error.BufferFull;
\\if (buf.fds.writableLength() < {2})
\\ return error.BufferFull;
\\buf.putUInt(id) catch unreachable;
\\buf.putUInt(@intCast(u32, len << 16) | @enumToInt(Opcode.{3s})) catch unreachable;
, .{
size_bytes,
extra.items,
size_fds,
try cx.snakeCase(msg.name),
});
for (msg.args) |arg| {
switch (arg.kind) {
.new_id, .object => {
if (arg.kind == .new_id and arg.interface == null) {
try cx.print(
\\buf.putString(self.interface) catch unreachable;
\\buf.putUInt(self.version) catch unreachable;
\\buf.putUInt(self.{s}) catch unreachable;
, .{
try cx.snakeCase(arg.name),
});
} else {
try cx.print(
\\buf.putUInt(self.{s}.id) catch unreachable;
, .{
try cx.snakeCase(arg.name),
});
}
},
.int => {
try cx.print(
\\buf.putInt(self.{s}) catch unreachable;
, .{try cx.snakeCase(arg.name)});
},
.uint => {
try cx.print(
\\buf.putUInt(self.{s}) catch unreachable;
, .{try cx.snakeCase(arg.name)});
},
.fixed => {
try cx.print(
\\buf.putFixed(self.{s}) catch unreachable;
, .{try cx.snakeCase(arg.name)});
},
.string => {
try cx.print(
\\buf.putString(self.{s}) catch unreachable;
, .{try cx.snakeCase(arg.name)});
},
.array => {
try cx.print(
\\buf.putArray(self.{s}) catch unreachable;
, .{try cx.snakeCase(arg.name)});
},
.fd => {
try cx.print(
\\buf.putFd(self.{s}) catch unreachable;
, .{try cx.snakeCase(arg.name)});
},
}
}
try cx.print(
\\}}
, .{});
}
fn emitUnmarshal(cx: *Context, msg: wayland.Message, _: MessageKind) !void {
var msg_arg_name: []const u8 = "_";
var fd_arg_name: []const u8 = "_";
if (msg.args.len != 0)
msg_arg_name = "msg";
for (msg.args) |arg| {
if (arg.kind == .fd)
fd_arg_name = "fds";
}
try cx.print(
\\pub fn unmarshal(
\\ {s}: *wayland.client.Connection,
\\ {s}: wayland.Message,
\\ {s}: *wayland.Buffer,
\\) @This() {{
, .{
"_",
msg_arg_name,
fd_arg_name,
});
if (msg.args.len != 0) {
try cx.print(
\\var i: usize = 0;
, .{});
}
try cx.print(
\\return @This(){{
, .{});
for (msg.args) |arg| {
try cx.print(
\\.{s} = blk: {{
, .{
try cx.snakeCase(arg.name),
});
switch (arg.kind) {
.new_id, .object => {
if (arg.kind == .new_id and arg.interface == null) {
try cx.print(
\\break :blk undefined;
, .{});
} else {
try cx.print(
\\const arg_id = @ptrCast(*align(1) const u32, msg.data[i .. i + 4]).*;
\\i += 4;
\\break :blk arg_id;
, .{});
}
},
.int => {
try cx.print(
\\const arg = @ptrCast(*align(1) const i32, msg.data[i .. i + 4]).*;
\\i += 4;
\\break :blk arg;
, .{});
},
.uint => {
try cx.print(
\\const arg = @ptrCast(*align(1) const u32, msg.data[i .. i + 4]).*;
\\i += 4;
\\break :blk arg;
, .{});
},
.fixed => {
try cx.print(
\\const arg = @ptrCast(*align(1) const i32, msg.data[i .. i + 4]).*;
\\i += 4;
\\break :blk arg;
, .{});
},
.string => {
try cx.print(
\\const arg_len = @ptrCast(*align(1) const u32, msg.data[i .. i + 4]).*;
\\const arg_padded_len = (arg_len + 3) / 4 * 4;
\\const arg = msg.data[i + 4.. i + 4 + arg_len - 1 :0];
\\i += 4 + arg_padded_len;
\\break :blk arg;
, .{});
},
.array => {
try cx.print(
\\const arg_len = @ptrCast(*align(1) const u32, msg.data[i .. i + 4]).*;
\\const arg_padded_len = (arg_len + 3) / 4 * 4;
\\const arg = msg.data[i + 4.. i + 4 + arg_len];
\\i += 4 + arg_padded_len;
\\break :blk arg;
, .{});
},
.fd => {
try cx.print(
\\_ = fds;
\\break :blk undefined;
, .{});
},
}
try cx.print(
\\}},
, .{});
}
try cx.print(
\\}};
\\}}
, .{});
}
fn emitFormat(cx: *Context, iface: wayland.Interface, msg: wayland.Message, kind: MessageKind) !void {
const arrow = switch (kind) {
.request => "->",
.event => "<-",
};
try cx.print(
\\pub fn format(
\\ self: @This(),
\\ comptime _: []const u8,
\\ _: std.fmt.FormatOptions,
\\ writer: anytype,
\\) !void {{
\\ _ = self;
\\ try writer.print("{s} {s}.{s}(", .{{}});
, .{
arrow,
iface.name,
msg.name,
});
for (msg.args) |arg, i| {
switch (arg.kind) {
.new_id => {
try cx.print(
\\try writer.print("new_id", .{{}});
, .{});
},
.int, .uint => {
try cx.print(
\\try writer.print("{0s} {1s}: {{}}", .{{self.{1s}}});
, .{ @tagName(arg.kind), arg.name });
},
.fixed => {
try cx.print(
\\try writer.print("fixed", .{{}});
, .{});
},
.string => {
try cx.print(
\\try writer.print("{0s} {1s}: \"{{s}}\"", .{{self.{1s}}});
, .{ @tagName(arg.kind), arg.name });
},
.object => {
try cx.print(
\\try writer.print("object", .{{}});
, .{});
},
.array => {
try cx.print(
\\try writer.print("array", .{{}});
, .{});
},
.fd => {
try cx.print(
\\try writer.print("fd", .{{}});
, .{});
},
}
if (i != msg.args.len - 1) {
try cx.print(
\\try writer.print(", ", .{{}});
, .{});
}
}
try cx.print(
\\ try writer.print(")", .{{}});
\\}}
, .{});
}
}; | scanner/main.zig |
const std = @import("std");
const ops = @import("./ops.zig");
const mem = @import("./mem.zig");
const c = @cImport({
@cInclude("termios.h");
});
const Registers = mem.Registers;
const OpCodes = ops.Opcodes;
const PC = Registers.PC.val();
var original_tio: c.termios = undefined;
fn disableInputBuffering() void {
const stdin_fd = std.os.linux.STDIN_FILENO;
_ = c.tcgetattr(stdin_fd, &original_tio);
var new_tio: c.termios = original_tio;
new_tio.c_lflag &= @bitCast(c_uint, ~c.ICANON & ~c.ECHO);
_ = c.tcsetattr(stdin_fd, c.TCSANOW, &new_tio);
}
fn restoreInputBuffering() void {
const stdin_fd = std.os.linux.STDIN_FILENO;
_ = c.tcsetattr(stdin_fd, c.TCSANOW, &original_tio);
}
pub fn main() !void {
const args = std.process.args();
var posix_args = args.inner;
if (posix_args.count < 2) {
std.debug.print("USAGE: lc3vm image-file\n", .{});
std.os.exit(1);
}
_ = posix_args.next() orelse std.os.exit(1);
// TODO: need to handle absolute
const image_file_relative = posix_args.next() orelse std.os.exit(1);
const current_dir = std.fs.cwd();
const open_flags = std.fs.File.OpenFlags { .read = true };
const image_file = try current_dir.openFile(image_file_relative, open_flags);
defer image_file.close();
const reader = std.fs.File.reader(image_file);
const u16_max = std.math.maxInt(u16);
const origin = try reader.readIntBig(u16);
// Works for now
var mem_instr_index = origin;
reading: while (mem_instr_index < u16_max) {
mem.memory[mem_instr_index] = reader.readIntBig(u16) catch |err| {
switch (err) {
error.EndOfStream => break :reading,
else => std.os.abort(),
}
};
mem_instr_index += 1;
}
// Start of memory is reserved for trap routines
const PC_START = origin;
mem.reg[PC] = PC_START;
const running = true;
// std.debug.print("start {b}\n", .{ mem.reg[PC] });
disableInputBuffering();
while (running) {
const current_pc = mem.reg[PC];
const instr: u16 = mem.read(current_pc);
mem.reg[PC] = current_pc + 1;
const op: u16 = instr >> 12;
// std.debug.print("pc: {d} op: {b} instr: {b} \n", .{ current_pc, op, instr });
switch (op) {
OpCodes.ADD.val() => ops.addOp(instr),
OpCodes.BR.val() => ops.brOp(instr),
OpCodes.LD.val() => ops.ldOp(instr),
OpCodes.ST.val() => ops.stOp(instr),
OpCodes.JSR.val() => ops.jsrOp(instr),
OpCodes.AND.val() => ops.andOp(instr),
OpCodes.LDR.val() => ops.ldrOp(instr),
OpCodes.STR.val() => ops.strOp(instr),
OpCodes.RTI.val() => ops.rtiOp(instr),
OpCodes.NOT.val() => ops.notOp(instr),
OpCodes.LDI.val() => ops.ldiOp(instr),
OpCodes.STI.val() => ops.stiOp(instr),
OpCodes.JMP.val() => ops.jmpOp(instr),
OpCodes.RES.val() => ops.resOp(instr),
OpCodes.LEA.val() => ops.leaOp(instr),
OpCodes.TRAP.val() => ops.trapOp(instr),
else => std.os.abort(),
}
}
} | src/main.zig |
const std = @import("std");
const c_string = [*:0]const u8;
// clap for CLI args
const clap = @import("clap");
// cmd line getter
const cmd = @import("cmd");
// postgres wrapper
const pq = @import("postgres");
/// getParams constructs the PG connection params from the CLI args
fn getParams() anyerror!pq.ConnectionParams {
var conn = pq.ConnectionParams{};
// Parse the CLI args into the ConnectionParams
const params = comptime [_]clap.Param(clap.Help){
clap.parseParam("-h, --host <STR> Set hostname, default = localhost.") catch unreachable,
clap.parseParam("-U, --username <STR> Set username, default = postgres.") catch unreachable,
clap.parseParam("-d, --dbname <STR> Set Database name.") catch unreachable,
clap.Param(clap.Help){
.takes_value = .One,
},
};
var args = try clap.parse(clap.Help, ¶ms, std.heap.page_allocator);
defer args.deinit();
if (args.option("--host")) |hostname| {
conn.hostname = hostname;
}
if (args.option("--username")) |username| {
conn.username = username;
}
if (args.option("--dbname")) |dbname| {
conn.dbname = dbname;
}
return conn;
}
pub fn main() anyerror!void {
std.debug.print("Using PG wrapper {}\n", .{pq.version});
var params = try getParams();
var dsn = try params.dsn();
var db = pq.connect(dsn) orelse {
std.debug.print("Error connecting to db {}", .{dsn});
return;
};
var db_name = db.name();
// just loop forever, getting a command, executing it, and then quitting when the user types \q
while (true) {
var input = try cmd.prompt("ZSQL ({}): ", .{db.name()});
if (hasPrefix("\\q", input)) {
return;
}
if (hasPrefix("\\c ", input)) {
const len = std.mem.len(input);
params.dbname = input[3..len];
dsn = try params.dsn();
db = pq.connect(dsn) orelse {
std.debug.print("Error connecting to db {}", .{dsn});
return;
};
std.debug.print("new connection {}\n", .{db});
continue;
}
var res = db.exec(input);
var status = res.status();
switch (status) {
pq.ExecStatusType.PGRES_TUPLES_OK => {
const tuples = res.numTuples();
const flds = res.numFields();
var i: u8 = 0;
var fld: u8 = 0;
while (fld < flds) : (fld += 1) {
std.debug.print("{} ", .{res.fieldName(fld)});
}
std.debug.print("\n------------------------------------------------------------------\n", .{});
while (i < tuples) : (i += 1) {
fld = 0;
while (fld < flds) : (fld += 1) {
std.debug.print("{} ", .{res.get(i, fld)});
}
std.debug.print("\n", .{});
}
std.debug.print("Status: {}\n", .{res.cmdStatus()});
std.debug.print("OK\n", .{});
},
else => std.debug.print("Status: {}\n", .{status}),
}
res.clear();
}
}
fn hasPrefix(needle: c_string, haystack: c_string) bool {
var index: usize = 0;
while (needle[index] == haystack[index] and needle[index] != 0) : (index += 1) {}
if (needle[index] == 0) {
return true;
}
return false;
} | src/zsql/main.zig |
const std = @import("std");
const assert = std.debug.assert;
const expect = std.testing.expect;
const Allocator = std.mem.Allocator;
const ArrayList = std.ArrayList;
const fixedBufferStream = std.io.fixedBufferStream;
const Pixel = u8;
const Layer = struct {
pixels: []Pixel,
const Self = @This();
pub fn fromStream(alloc: *Allocator, stream: anytype, w: usize, h: usize) !Self {
var pixels = try alloc.alloc(Pixel, w * h);
for (pixels) |*p| {
var buf: [1]u8 = undefined;
if ((try stream.readAll(&buf)) == 0)
return error.EndOfStream;
p.* = try std.fmt.parseInt(u8, &buf, 10);
}
return Self{
.pixels = pixels,
};
}
pub fn countDigit(self: Self, digit: u8) usize {
var result: usize = 0;
for (self.pixels) |p| {
if (p == digit)
result += 1;
}
return result;
}
pub fn merge(self: *Self, other: Self) void {
for (self.pixels) |*p, i| {
if (p.* == 2)
p.* = other.pixels[i];
}
}
};
test "read layer" {
var arena = std.heap.ArenaAllocator.init(std.heap.page_allocator);
const allocator = &arena.allocator;
defer arena.deinit();
var reader = fixedBufferStream("001123").reader();
const lay = try Layer.fromStream(allocator, reader, 3, 2);
expect(lay.countDigit(1) == 2);
expect(lay.countDigit(0) == 2);
}
const Image = struct {
layers: []Layer,
width: usize,
const Self = @This();
pub fn fromStream(alloc: *Allocator, stream: anytype, w: usize, h: usize) !Self {
var layers = ArrayList(Layer).init(alloc);
while (Layer.fromStream(alloc, stream, w, h)) |l| {
try layers.append(l);
} else |e| switch (e) {
error.EndOfStream => {},
error.InvalidCharacter => {},
else => return e,
}
return Self{
.layers = layers.items,
.width = w,
};
}
pub fn flatten(self: *Self) void {
var i: usize = self.layers.len - 1;
while (i > 0) : (i -= 1) {
self.layers[i - 1].merge(self.layers[i]);
}
}
pub fn print(self: Self) void {
for (self.layers[0].pixels) |pix, i| {
if (pix == 0) {
std.debug.warn(" ", .{});
} else {
std.debug.warn("{}", .{pix});
}
if (i % self.width == self.width - 1)
std.debug.warn("\n", .{});
}
}
};
test "read image" {
var arena = std.heap.ArenaAllocator.init(std.heap.page_allocator);
const allocator = &arena.allocator;
defer arena.deinit();
var reader = fixedBufferStream("123456789012").reader();
const img = try Image.fromStream(allocator, reader, 3, 2);
expect(img.layers.len == 2);
}
pub fn main() !void {
var arena = std.heap.ArenaAllocator.init(std.heap.page_allocator);
const allocator = &arena.allocator;
defer arena.deinit();
const input_file = try std.fs.cwd().openFile("input08.txt", .{});
var input_stream = input_file.reader();
// read image
var img = try Image.fromStream(allocator, input_stream, 25, 6);
// flatten
img.flatten();
// print
img.print();
} | zig/08_2.zig |
const std = @import("std");
const interval = @import("interval.zig");
const debug = std.debug;
const math = std.math;
const testing = std.testing;
// TODO: We can't use comptime_int, because then all the methods on Interval don't compile
const Interval = interval.Interval(i128);
fn toInterval(comptime T: type) Interval {
return Interval{
.min = math.minInt(T),
.max = math.maxInt(T),
};
}
fn Result(comptime A: type, comptime B: type, comptime operation: @TypeOf(Interval.add)) type {
const a = toInterval(A);
const b = toInterval(B);
const res = operation(a, b);
return math.IntFittingRange(res.min, res.max);
}
pub fn add(a: var, b: var) Result(@TypeOf(a), @TypeOf(b), Interval.add) {
const Res = Result(@TypeOf(a), @TypeOf(b), Interval.add);
return @as(Res, a) + @as(Res, b);
}
fn testAdd() void {
const u64_max: u64 = math.maxInt(u64);
const u64_min: u64 = math.minInt(u64);
const i64_max: i64 = math.maxInt(i64);
const i64_min: i64 = math.minInt(i64);
testing.expectEqual(add(u64_max, u64_max), math.maxInt(u64) + math.maxInt(u64));
testing.expectEqual(add(u64_max, u64_min), math.maxInt(u64) + math.minInt(u64));
testing.expectEqual(add(u64_max, i64_max), math.maxInt(u64) + math.maxInt(i64));
testing.expectEqual(add(u64_max, i64_min), math.maxInt(u64) + math.minInt(i64));
testing.expectEqual(add(u64_min, u64_min), math.minInt(u64) + math.minInt(u64));
testing.expectEqual(add(u64_min, i64_max), math.minInt(u64) + math.maxInt(i64));
testing.expectEqual(add(u64_min, i64_min), math.minInt(u64) + math.minInt(i64));
testing.expectEqual(add(i64_max, i64_max), math.maxInt(i64) + math.maxInt(i64));
testing.expectEqual(add(i64_max, i64_min), math.maxInt(i64) + math.minInt(i64));
testing.expectEqual(add(i64_min, i64_min), math.minInt(i64) + math.minInt(i64));
}
test "math.safe.add" {
comptime testAdd();
testAdd();
}
pub fn sub(a: var, b: var) Result(@TypeOf(a), @TypeOf(b), Interval.sub) {
const Res = Result(@TypeOf(a), @TypeOf(b), Interval.sub);
return @as(Res, a) - @as(Res, b);
}
fn testSub() void {
const u64_max: u64 = math.maxInt(u64);
const u64_min: u64 = math.minInt(u64);
const i64_max: i64 = math.maxInt(i64);
const i64_min: i64 = math.minInt(i64);
testing.expectEqual(sub(u64_max, u64_max), math.maxInt(u64) - math.maxInt(u64));
testing.expectEqual(sub(u64_max, u64_min), math.maxInt(u64) - math.minInt(u64));
testing.expectEqual(sub(u64_max, i64_max), math.maxInt(u64) - math.maxInt(i64));
testing.expectEqual(sub(u64_max, i64_min), math.maxInt(u64) - math.minInt(i64));
testing.expectEqual(sub(u64_min, u64_min), math.minInt(u64) - math.minInt(u64));
testing.expectEqual(sub(u64_min, i64_max), math.minInt(u64) - math.maxInt(i64));
testing.expectEqual(sub(u64_min, i64_min), math.minInt(u64) - math.minInt(i64));
testing.expectEqual(sub(i64_max, i64_max), math.maxInt(i64) - math.maxInt(i64));
testing.expectEqual(sub(i64_max, i64_min), math.maxInt(i64) - math.minInt(i64));
testing.expectEqual(sub(i64_min, i64_min), math.minInt(i64) - math.minInt(i64));
}
test "math.safe.sub" {
comptime testSub();
testSub();
}
pub fn mul(a: var, b: var) Result(@TypeOf(a), @TypeOf(b), Interval.mul) {
const Res = Result(@TypeOf(a), @TypeOf(b), Interval.mul);
return @as(Res, a) * @as(Res, b);
}
fn testMul() void {
// TODO: Because we can only have Interval(i128), then u64 values might overflow the
// Interval.
const u32_max: u32 = math.maxInt(u32);
const u32_min: u32 = math.minInt(u32);
const i32_max: i32 = math.maxInt(i32);
const i32_min: i32 = math.minInt(i32);
testing.expectEqual(mul(u32_max, u32_max), math.maxInt(u32) * math.maxInt(u32));
testing.expectEqual(mul(u32_max, u32_min), math.maxInt(u32) * math.minInt(u32));
//testing.expectEqual(mul(u32_max, i32_max) , math.maxInt(u32) * math.maxInt(i32));
//testing.expectEqual(mul(u32_max, i32_min) , math.maxInt(u32) * math.minInt(i32));
testing.expectEqual(mul(u32_min, u32_min), math.minInt(u32) * math.minInt(u32));
//testing.expectEqual(mul(u32_min, i32_max) , math.minInt(u32) * math.maxInt(i32));
//testing.expectEqual(mul(u32_min, i32_min) , math.minInt(u32) * math.minInt(i32));
//testing.expectEqual(mul(i32_max, i32_max) , math.maxInt(i32) * math.maxInt(i32));
//testing.expectEqual(mul(i32_max, i32_min) , math.maxInt(i32) * math.minInt(i32));
//testing.expectEqual(mul(i32_min, i32_min) , math.minInt(i32) * math.minInt(i32));
}
test "math.safe.mul" {
comptime testMul();
testMul();
} | src/math/safe.zig |
const std = @import("std");
const ArrayList = std.ArrayList;
const allocator = std.heap.c_allocator;
const log = @import("../log.zig");
const file = @import("../file.zig");
const Errors = log.Errors;
const token = @import("tokens.zig");
const Token = token.Token;
const TokenType = token.TokenType;
pub const Lexer = struct {
tkns: ArrayList(Token),
lines: ArrayList(usize),
begin: usize,
index: usize,
line: usize,
col: usize,
length: usize,
file: file.SrcFile,
log_file: std.fs.File,
done: bool = false,
pub fn freeLexer(self: *Lexer) void {
self.freeLexerArrayLists();
self.freeSourceCode();
}
pub fn freeLexerArrayLists(self: *Lexer) void {
self.tkns.deinit();
self.lines.deinit();
}
pub fn freeSourceCode(self: *Lexer) void {
allocator.free(self.file.code);
}
pub fn lex(self: *Lexer) !void {
if (self.file.len < 1) {
return Errors.END_OF_FILE;
}
while (self.index < self.file.len) {
try self.single();
self.skipWhite();
}
self.done = true;
}
fn single(self: *Lexer) !void {
self.skipWhite();
const c = try self.current();
self.length = 1;
self.begin = self.index;
const save_index = self.index;
const save_line = self.line;
const save_col = self.col;
var reached_dot = false;
if (std.ascii.isDigit(c)) {
if (!self.advance()) return;
while (std.ascii.isDigit(try self.current()) or try self.current() == '.') {
if ((try self.current()) == '.') {
if (reached_dot) {
break;
} else reached_dot = true;
}
if (!self.advance()) return;
self.length += 1;
}
self.col = save_col;
self.line = save_line;
self.index = save_index;
if (reached_dot) {
self.addToken(TokenType.Float);
} else {
self.addToken(if (self.length < 10) TokenType.Integer else TokenType.Long);
}
return;
} else if (c == '"') {
if (!self.advance()) return;
while ((try self.current()) != '"') {
if ((try self.current()) == 0 or (try self.current()) == '\n') {
return Errors.NOT_CLOSED_STR;
} else if ((try self.current()) == '\\' and self.peek() == '"') {
_ = self.advance();
self.length += 1;
}
if (!self.advance()) return;
self.length += 1;
}
self.length += 1;
self.col = save_col;
self.line = save_line;
self.index = save_index;
self.addToken(TokenType.String);
return;
} else if (c == '\'') {
if (!self.advance()) return;
while ((try self.current()) != '\'') {
if ((try self.current()) == 0) {
self.length = 1;
return Errors.END_OF_FILE;
}
if (std.ascii.isSpace((try self.current())) and self.peek() != '\'') {
self.length = 1;
return Errors.NOT_CLOSED_CHAR;
}
if (self.length == 2 and self.past() == '\\' and (try self.current()) != '\\') {
if (!self.advance()) return;
self.length += 1;
break;
} else if (self.length > 1 and self.past() != '\\' and (self.peek() == '\'' or self.peek() == '\\')) {
self.length = 1;
return Errors.NOT_CLOSED_CHAR;
} else if (self.length > 1) {
self.length = 1;
return Errors.NOT_CLOSED_CHAR;
}
if (!self.advance()) return;
self.length += 1;
}
self.length += 1;
self.col = save_col;
self.line = save_line;
self.index = save_index;
self.addToken(TokenType.Char);
return;
} else switch (c) {
'=' => {
if (self.peek() == '=') {
self.length += 1;
self.addToken(TokenType.EqualEqual);
_ = self.advance();
} else {
self.addToken(TokenType.Equal);
}
},
':' => self.addToken(TokenType.Colon),
';' => self.addToken(TokenType.SemiColon),
'+' => {
if (self.peek() == '=') {
self.length += 1;
self.addToken(TokenType.AddEqual);
if (!self.advance()) return;
} else {
self.addToken(TokenType.Plus);
}
},
'-' => {
if (self.peek() == '=') {
self.length += 1;
self.addToken(TokenType.SubEqual);
if (!self.advance()) return;
} else {
self.addToken(TokenType.Minus);
}
},
'*' => {
if (self.peek() == '=') {
self.length += 1;
self.addToken(TokenType.MultEqual);
if (!self.advance()) return;
} else {
self.addToken(TokenType.Star);
}
},
'/' => {
const cc = self.peek();
if (cc == '=') {
self.length += 1;
self.addToken(TokenType.DivEqual);
if (!self.advance()) return;
} else if (cc == '/') {
while ((try self.current()) != '\n') {
if (!self.advance()) return;
}
} else {
self.addToken(TokenType.Div);
}
},
'(' => self.addToken(TokenType.LeftParen),
')' => self.addToken(TokenType.RightParen),
'{' => self.addToken(TokenType.LeftCurly),
'}' => self.addToken(TokenType.RightCurly),
'[' => self.addToken(TokenType.LeftSQRBrackets),
']' => self.addToken(TokenType.RightSQRBrackets),
'>' => {
if (self.peek() == '=') {
self.length += 1;
self.addToken(TokenType.GreaterEqual);
if (!self.advance()) return;
} else {
self.addToken(TokenType.Greater);
}
},
'<' => {
if (self.peek() == '=') {
self.length += 1;
self.addToken(TokenType.LessEqual);
if (!self.advance()) return;
} else {
self.addToken(TokenType.Less);
}
},
'.' => self.addToken(TokenType.Dot),
'!' => self.addToken(TokenType.Not),
else => {
if (c == '_' or std.ascii.isAlpha(c)) {
self.multiChar() catch |err| {
return err;
};
} else if (self.index >= self.file.len) {
return Errors.END_OF_FILE;
} else return Errors.UNKNOWN_TOKEN;
},
}
return;
}
fn notEof(self: *Lexer) bool {
if ((try self.current()) != 0) {
return true;
} else {
return false;
}
}
fn multiChar(self: *Lexer) !void {
const save_col = self.col;
const save_line = self.line;
const save_index = self.index;
const save_len = self.length;
self.length = 1;
if (!self.advance()) return;
var length: usize = 1;
while (std.ascii.isAlNum((try self.current())) or (try self.current()) == '_') {
if (!self.advance()) return;
length += 1;
}
self.length = save_len;
self.index = save_index;
self.line = save_line;
self.col = save_col;
var tkn_type = TokenType.Identifier;
const word = self.slice(length);
switch (length) {
2 => {
if (std.mem.eql(u8, "if", word)) {
tkn_type = TokenType.If;
} else if (std.mem.eql(u8, "fn", word)) {
tkn_type = TokenType.Function;
} else if (std.mem.eql(u8, "or", word)) {
tkn_type = TokenType.Or;
} else if (std.mem.eql(u8, "as", word)) {
tkn_type = TokenType.As;
}
},
3 => {
if (std.mem.eql(u8, "for", word)) {
tkn_type = TokenType.For;
} else if (std.mem.eql(u8, "let", word)) {
tkn_type = TokenType.Let;
} else if (std.mem.eql(u8, "pub", word)) {
tkn_type = TokenType.Public;
} else if (std.mem.eql(u8, "str", word)) {
tkn_type = TokenType.StringKeyword;
} else if (std.mem.eql(u8, "mut", word)) {
tkn_type = TokenType.Mutable;
} else if (std.mem.eql(u8, "int", word)) {
tkn_type = TokenType.IntKeyword;
} else if (std.mem.eql(u8, "ref", word)) {
tkn_type = TokenType.Ref;
} else if (std.mem.eql(u8, "and", word)) {
tkn_type = TokenType.And;
}
},
4 => {
if (std.mem.eql(u8, "else", word)) {
tkn_type = TokenType.Else;
} else if (std.mem.eql(u8, "true", word)) {
tkn_type = TokenType.True;
} else if (std.mem.eql(u8, "char", word)) {
tkn_type = TokenType.CharKeyword;
} else if (std.mem.eql(u8, "bool", word)) {
tkn_type = TokenType.BoolKeyword;
} else if (std.mem.eql(u8, "void", word)) {
tkn_type = TokenType.Void;
} else if (std.mem.eql(u8, "skip", word)) {
tkn_type = TokenType.Skip;
}
},
5 => {
if (std.mem.eql(u8, "while", word)) {
tkn_type = TokenType.While;
} else if (std.mem.eql(u8, "false", word)) {
tkn_type = TokenType.False;
} else if (std.mem.eql(u8, "match", word)) {
tkn_type = TokenType.Match;
} else if (std.mem.eql(u8, "break", word)) {
tkn_type = TokenType.Break;
} else if (std.mem.eql(u8, "float", word)) {
tkn_type = TokenType.FloatKeyword;
} else if (std.mem.eql(u8, "defer", word)) {
tkn_type = TokenType.Defer;
}
},
6 => {
if (std.mem.eql(u8, "return", word)) {
tkn_type = TokenType.Return;
} else if (std.mem.eql(u8, "import", word)) {
tkn_type = TokenType.Import;
} else if (std.mem.eql(u8, "struct", word)) {
tkn_type = TokenType.Struct;
}
},
7 => {
if (std.mem.eql(u8, "include", word)) {
tkn_type = TokenType.Include;
}
},
else => {},
}
self.length = length;
self.addToken(tkn_type);
}
fn addToken(self: *Lexer, token_type: TokenType) void {
self.tkns.append(.{
.pos = .{
.line = self.line,
.col = self.col,
.index = self.index,
},
.tkn_type = token_type,
.value = self.slice(self.length),
}) catch |err| {
log.logErr(@errorName(err));
};
var i: u8 = 1;
while (i <= self.length) : (i += 1) {
if (!self.advance()) break;
}
}
fn slice(self: *Lexer, len: usize) []const u8 {
return self.file.code[self.index..(self.index + len)];
}
fn next(self: *Lexer) void {
self.index += 1;
}
fn peek(self: *Lexer) u8 {
return self.file.code[self.index + 1];
}
fn past(self: *Lexer) u8 {
return self.file.code[self.index - 1];
}
fn specific(self: *Lexer, i: isize) u8 {
return self.file.code[self.index + i];
}
fn current(self: *Lexer) !u8 {
return self.file.code[self.index];
}
fn advance(self: *Lexer) bool {
const c = try self.current();
self.next();
if (c != '\n') {
self.col += 1;
} else {
self.col = 1;
self.line += 1;
self.lines.append(self.index) catch |err| {
log.logErr(@errorName(err));
return false;
};
}
return true;
}
fn skipWhite(self: *Lexer) void {
var b: bool = true;
while (self.index < self.file.len and std.ascii.isSpace(try self.current()) and b) {
b = self.advance();
}
}
fn debugPos(self: *Lexer) void {
std.debug.print("index: {d}\nline: {d}\ncol: {d}\nlen: {d}\n", .{
self.index,
self.line,
self.col,
self.length,
});
}
pub fn outputTokens(self: *Lexer) void {
std.fmt.format(self.log_file.writer(), "{s}\n## lexer \n```\n", .{"-" ** 10}) catch |err| {
log.logErr(@errorName(err));
};
for (self.tkns.items) |tkn, index| {
std.fmt.format(self.log_file.writer(), "{d: ^5}: Token: {s: <10} at {s}:{d}:{d} : \"{s}\"\n", .{
index, tkn.tkn_type.describe(), self.file.name, tkn.pos.line, tkn.pos.col, tkn.value,
}) catch |err| {
log.logErr(@errorName(err));
};
}
std.fmt.format(self.log_file.writer(), "```\n{s}\n\n", .{"-" ** 10}) catch |err| {
log.logErr(@errorName(err));
};
// for (self.lines.items) |line| {
// print("{d}\n", .{line});
// }
}
};
pub fn initLexer(filename: []const u8, logfile: std.fs.File) !Lexer {
var self = Lexer{
.tkns = undefined,
.lines = ArrayList(usize).init(allocator),
.index = 0,
.begin = 0,
.line = 1,
.col = 1,
.length = 1,
.file = undefined,
.log_file = logfile,
};
self.file = (try file.readFile(filename, logfile));
self.tkns = try ArrayList(Token).initCapacity(allocator, self.file.len / 20);
return self;
} | src/lexer/lexer.zig |
const std = @import("std");
// Root interface/implementations
pub const Interface = @import("Interface.zig");
pub const RequestAdapterOptions = Interface.RequestAdapterOptions;
pub const RequestAdapterErrorCode = Interface.RequestAdapterErrorCode;
pub const RequestAdapterError = Interface.RequestAdapterError;
pub const RequestAdapterCallback = Interface.RequestAdapterCallback;
pub const RequestAdapterResponse = Interface.RequestAdapterResponse;
pub const Adapter = @import("Adapter.zig");
pub const RequestDeviceErrorCode = Adapter.RequestDeviceErrorCode;
pub const RequestDeviceError = Adapter.RequesatDeviceError;
pub const RequestDeviceCallback = Adapter.RequestDeviceCallback;
pub const RequestDeviceResponse = Adapter.RequestDeviceResponse;
pub const NativeInstance = @import("NativeInstance.zig");
// Interfaces
pub const Device = @import("Device.zig");
pub const Surface = @import("Surface.zig");
pub const Queue = @import("Queue.zig");
pub const CommandBuffer = @import("CommandBuffer.zig");
pub const ShaderModule = @import("ShaderModule.zig");
pub const SwapChain = @import("SwapChain.zig");
pub const TextureView = @import("TextureView.zig");
pub const Texture = @import("Texture.zig");
pub const Sampler = @import("Sampler.zig");
pub const RenderPipeline = @import("RenderPipeline.zig");
pub const RenderPassEncoder = @import("RenderPassEncoder.zig");
pub const RenderBundleEncoder = @import("RenderBundleEncoder.zig");
pub const RenderBundle = @import("RenderBundle.zig");
pub const QuerySet = @import("QuerySet.zig");
pub const PipelineLayout = @import("PipelineLayout.zig");
pub const ExternalTexture = @import("ExternalTexture.zig");
pub const BindGroup = @import("BindGroup.zig");
pub const BindGroupLayout = @import("BindGroupLayout.zig");
pub const Buffer = @import("Buffer.zig");
pub const CommandEncoder = @import("CommandEncoder.zig");
pub const ComputePassEncoder = @import("ComputePassEncoder.zig");
pub const ComputePipeline = @import("ComputePipeline.zig");
// Data structures ABI-compatible with webgpu.h
pub const Limits = @import("data.zig").Limits;
pub const Color = @import("data.zig").Color;
pub const Extent3D = @import("data.zig").Extent3D;
pub const Origin3D = @import("data.zig").Origin3D;
pub const StencilFaceState = @import("data.zig").StencilFaceState;
pub const VertexAttribute = @import("data.zig").VertexAttribute;
pub const BlendComponent = @import("data.zig").BlendComponent;
pub const BlendState = @import("data.zig").BlendState;
pub const VertexBufferLayout = @import("data.zig").VertexBufferLayout;
// Data structures not ABI-compatible with webgpu.h
pub const MultisampleState = @import("structs.zig").MultisampleState;
pub const PrimitiveState = @import("structs.zig").PrimitiveState;
pub const StorageTextureBindingLayout = @import("structs.zig").StorageTextureBindingLayout;
pub const DepthStencilState = @import("structs.zig").DepthStencilState;
pub const ConstantEntry = @import("structs.zig").ConstantEntry;
pub const ProgrammableStageDescriptor = @import("structs.zig").ProgrammableStageDescriptor;
// TODO: should these be moved into ComputePassEncoder / RenderPassEncoder? If not, should
// WGPURenderPassDescriptor really be RenderPassEncoder.Descriptor?
pub const ComputePassTimestampWrite = @import("structs.zig").ComputePassTimestampWrite;
pub const RenderPassTimestampWrite = @import("structs.zig").RenderPassTimestampWrite;
pub const RenderPassDepthStencilAttachment = @import("structs.zig").RenderPassDepthStencilAttachment;
pub const RenderPassColorAttachment = @import("structs.zig").RenderPassColorAttachment;
pub const VertexState = @import("structs.zig").VertexState;
pub const FragmentState = @import("structs.zig").FragmentState;
pub const ColorTargetState = @import("structs.zig").ColorTargetState;
pub const ImageCopyBuffer = @import("structs.zig").ImageCopyBuffer;
pub const ImageCopyTexture = @import("structs.zig").ImageCopyTexture;
pub const ErrorCallback = @import("structs.zig").ErrorCallback;
pub const LoggingCallback = @import("structs.zig").LoggingCallback;
// Enumerations
pub const Feature = @import("enums.zig").Feature;
pub const PresentMode = @import("enums.zig").PresentMode;
pub const AddressMode = @import("enums.zig").AddressMode;
pub const AlphaMode = @import("enums.zig").AlphaMode;
pub const BlendFactor = @import("enums.zig").BlendFactor;
pub const BlendOperation = @import("enums.zig").BlendOperation;
pub const CompareFunction = @import("enums.zig").CompareFunction;
pub const ComputePassTimestampLocation = @import("enums.zig").ComputePassTimestampLocation;
pub const CullMode = @import("enums.zig").CullMode;
pub const ErrorFilter = @import("enums.zig").ErrorFilter;
pub const ErrorType = @import("enums.zig").ErrorType;
pub const FilterMode = @import("enums.zig").FilterMode;
pub const FrontFace = @import("enums.zig").FrontFace;
pub const IndexFormat = @import("enums.zig").IndexFormat;
pub const LoadOp = @import("enums.zig").LoadOp;
pub const LoggingType = @import("enums.zig").LoggingType;
pub const PipelineStatistic = @import("enums.zig").PipelineStatistic;
pub const PowerPreference = @import("enums.zig").PowerPreference;
pub const PredefinedColorSpace = @import("enums.zig").PredefinedColorSpace;
pub const PrimitiveTopology = @import("enums.zig").PrimitiveTopology;
pub const QueryType = @import("enums.zig").QueryType;
pub const RenderPassTimestampLocation = @import("enums.zig").RenderPassTimestampLocation;
pub const StencilOperation = @import("enums.zig").StencilOperation;
pub const StorageTextureAccess = @import("enums.zig").StorageTextureAccess;
pub const StoreOp = @import("enums.zig").StoreOp;
pub const VertexFormat = @import("enums.zig").VertexFormat;
pub const VertexStepMode = @import("enums.zig").VertexStepMode;
pub const BufferUsage = @import("enums.zig").BufferUsage;
pub const ColorWriteMask = @import("enums.zig").ColorWriteMask;
pub const ShaderStage = @import("enums.zig").ShaderStage;
// Constants
const array_layer_count_undefined: u32 = 0xffffffff;
const copy_stride_undefined: u32 = 0xffffffff;
const limit_u32_undefined: u32 = 0xffffffff;
const limit_u64_undefined: u32 = 0xffffffffffffffff;
const mip_level_count_undefined: u32 = 0xffffffff;
const stride_undefined: u32 = 0xffffffff;
const whole_map_size: u32 = std.math.maxInt(c_int);
const whole_size: u64 = 0xffffffffffffffff;
test {
// Root interface/implementations
_ = Interface;
_ = NativeInstance;
// Interfaces
_ = Adapter;
_ = Device;
_ = Surface;
_ = Limits;
_ = Queue;
_ = CommandBuffer;
_ = ShaderModule;
_ = SwapChain;
_ = TextureView;
_ = Texture;
_ = Sampler;
_ = RenderPipeline;
_ = RenderPassEncoder;
_ = RenderBundleEncoder;
_ = RenderBundle;
_ = QuerySet;
_ = PipelineLayout;
_ = ExternalTexture;
_ = BindGroup;
_ = BindGroupLayout;
_ = Buffer;
_ = CommandEncoder;
_ = ComputePassEncoder;
_ = ComputePipeline;
// Data structures ABI-compatible with webgpu.h
_ = Limits;
// Data structures not ABI-compatible with webgpu.h
_ = MultisampleState;
// Enumerations
_ = Feature;
} | gpu/src/main.zig |
const imgui = @import("../../c.zig");
pub const __time_t = c_long;
pub const time_t = __time_t;
pub const struct_tm = extern struct {
tm_sec: c_int,
tm_min: c_int,
tm_hour: c_int,
tm_mday: c_int,
tm_mon: c_int,
tm_year: c_int,
tm_wday: c_int,
tm_yday: c_int,
tm_isdst: c_int,
tm_gmtoff: c_long,
tm_zone: [*c]const u8,
};
pub const tm = struct_tm;
pub const ImPlotMarker = c_int;
pub const struct_ImPlotNextItemData = extern struct {
Colors: [5]imgui.ImVec4,
LineWeight: f32,
Marker: ImPlotMarker,
MarkerSize: f32,
MarkerWeight: f32,
FillAlpha: f32,
ErrorBarSize: f32,
ErrorBarWeight: f32,
DigitalBitHeight: f32,
DigitalBitGap: f32,
RenderLine: bool,
RenderFill: bool,
RenderMarkerLine: bool,
RenderMarkerFill: bool,
HasHidden: bool,
Hidden: bool,
HiddenCond: imgui.ImGuiCond,
};
pub const ImPlotNextItemData = struct_ImPlotNextItemData;
pub const ImPlotSubplotFlags = c_int;
pub const struct_ImVector_int = extern struct {
Size: c_int,
Capacity: c_int,
Data: [*c]c_int,
};
pub const ImVector_int = struct_ImVector_int;
pub const ImPlotLocation = c_int;
pub const ImPlotOrientation = c_int;
pub const struct_ImPlotLegendData = extern struct {
Indices: ImVector_int,
Labels: imgui.ImGuiTextBuffer,
Hovered: bool,
Outside: bool,
CanGoInside: bool,
FlipSideNextFrame: bool,
Location: ImPlotLocation,
Orientation: ImPlotOrientation,
Rect: imgui.ImRect,
};
pub const ImPlotLegendData = struct_ImPlotLegendData;
pub const struct_ImPlotItem = extern struct {
ID: imgui.ImGuiID,
Color: imgui.ImU32,
NameOffset: c_int,
Show: bool,
LegendHovered: bool,
SeenThisFrame: bool,
};
pub const ImPlotItem = struct_ImPlotItem;
pub const struct_ImVector_ImPlotItem = extern struct {
Size: c_int,
Capacity: c_int,
Data: [*c]ImPlotItem,
};
pub const ImVector_ImPlotItem = struct_ImVector_ImPlotItem;
pub const struct_ImPool_ImPlotItem = extern struct {
Buf: ImVector_ImPlotItem,
Map: imgui.ImGuiStorage,
FreeIdx: imgui.ImPoolIdx,
};
pub const ImPool_ImPlotItem = struct_ImPool_ImPlotItem;
pub const struct_ImPlotItemGroup = extern struct {
ID: imgui.ImGuiID,
Legend: ImPlotLegendData,
ItemPool: ImPool_ImPlotItem,
ColormapIdx: c_int,
};
pub const ImPlotItemGroup = struct_ImPlotItemGroup;
pub const struct_ImPlotAlignmentData = extern struct {
Orientation: ImPlotOrientation,
PadA: f32,
PadB: f32,
PadAMax: f32,
PadBMax: f32,
};
pub const ImPlotAlignmentData = struct_ImPlotAlignmentData;
pub const struct_ImVector_ImPlotAlignmentData = extern struct {
Size: c_int,
Capacity: c_int,
Data: [*c]ImPlotAlignmentData,
};
pub const ImVector_ImPlotAlignmentData = struct_ImVector_ImPlotAlignmentData;
pub const struct_ImPlotRange = extern struct {
Min: f64,
Max: f64,
};
pub const ImPlotRange = struct_ImPlotRange;
pub const struct_ImVector_ImPlotRange = extern struct {
Size: c_int,
Capacity: c_int,
Data: [*c]ImPlotRange,
};
pub const ImVector_ImPlotRange = struct_ImVector_ImPlotRange;
pub const struct_ImPlotSubplot = extern struct {
ID: imgui.ImGuiID,
Flags: ImPlotSubplotFlags,
PreviousFlags: ImPlotSubplotFlags,
Items: ImPlotItemGroup,
Rows: c_int,
Cols: c_int,
CurrentIdx: c_int,
FrameRect: imgui.ImRect,
GridRect: imgui.ImRect,
CellSize: imgui.ImVec2,
RowAlignmentData: ImVector_ImPlotAlignmentData,
ColAlignmentData: ImVector_ImPlotAlignmentData,
RowRatios: imgui.ImVector_float,
ColRatios: imgui.ImVector_float,
RowLinkData: ImVector_ImPlotRange,
ColLinkData: ImVector_ImPlotRange,
TempSizes: [2]f32,
FrameHovered: bool,
};
pub const ImPlotSubplot = struct_ImPlotSubplot;
pub const struct_ImPlotTick = extern struct {
PlotPos: f64,
PixelPos: f32,
LabelSize: imgui.ImVec2,
TextOffset: c_int,
Major: bool,
ShowLabel: bool,
Level: c_int,
};
pub const ImPlotTick = struct_ImPlotTick;
pub const struct_ImVector_ImPlotTick = extern struct {
Size: c_int,
Capacity: c_int,
Data: [*c]ImPlotTick,
};
pub const ImVector_ImPlotTick = struct_ImVector_ImPlotTick;
pub const struct_ImPlotTickCollection = extern struct {
Ticks: ImVector_ImPlotTick,
TextBuffer: imgui.ImGuiTextBuffer,
TotalWidthMax: f32,
TotalWidth: f32,
TotalHeight: f32,
MaxWidth: f32,
MaxHeight: f32,
Size: c_int,
};
pub const ImPlotTickCollection = struct_ImPlotTickCollection;
pub const struct_ImPlotAnnotation = extern struct {
Pos: imgui.ImVec2,
Offset: imgui.ImVec2,
ColorBg: imgui.ImU32,
ColorFg: imgui.ImU32,
TextOffset: c_int,
Clamp: bool,
};
pub const ImPlotAnnotation = struct_ImPlotAnnotation;
pub const struct_ImVector_ImPlotAnnotation = extern struct {
Size: c_int,
Capacity: c_int,
Data: [*c]ImPlotAnnotation,
};
pub const ImVector_ImPlotAnnotation = struct_ImVector_ImPlotAnnotation;
pub const struct_ImPlotAnnotationCollection = extern struct {
Annotations: ImVector_ImPlotAnnotation,
TextBuffer: imgui.ImGuiTextBuffer,
Size: c_int,
};
pub const ImPlotAnnotationCollection = struct_ImPlotAnnotationCollection;
pub const struct_ImPlotPointError = extern struct {
X: f64,
Y: f64,
Neg: f64,
Pos: f64,
};
pub const ImPlotPointError = struct_ImPlotPointError;
pub const struct_ImVector_bool = extern struct {
Size: c_int,
Capacity: c_int,
Data: [*c]bool,
};
pub const ImVector_bool = struct_ImVector_bool;
pub const struct_ImPlotColormapData = extern struct {
Keys: imgui.ImVector_ImU32,
KeyCounts: ImVector_int,
KeyOffsets: ImVector_int,
Tables: imgui.ImVector_ImU32,
TableSizes: ImVector_int,
TableOffsets: ImVector_int,
Text: imgui.ImGuiTextBuffer,
TextOffsets: ImVector_int,
Quals: ImVector_bool,
Map: imgui.ImGuiStorage,
Count: c_int,
};
pub const ImPlotColormapData = struct_ImPlotColormapData;
pub const struct_ImPlotTime = extern struct {
S: time_t,
Us: c_int,
};
pub const ImPlotTime = struct_ImPlotTime;
pub const ImPlotDateFmt = c_int;
pub const ImPlotTimeFmt = c_int;
pub const struct_ImPlotDateTimeFmt = extern struct {
Date: ImPlotDateFmt,
Time: ImPlotTimeFmt,
UseISO8601: bool,
Use24HourClock: bool,
};
pub const ImPlotDateTimeFmt = struct_ImPlotDateTimeFmt;
pub const struct_ImPlotInputMap = extern struct {
PanButton: imgui.ImGuiMouseButton,
PanMod: imgui.ImGuiKeyModFlags,
FitButton: imgui.ImGuiMouseButton,
ContextMenuButton: imgui.ImGuiMouseButton,
BoxSelectButton: imgui.ImGuiMouseButton,
BoxSelectMod: imgui.ImGuiKeyModFlags,
BoxSelectCancelButton: imgui.ImGuiMouseButton,
QueryButton: imgui.ImGuiMouseButton,
QueryMod: imgui.ImGuiKeyModFlags,
QueryToggleMod: imgui.ImGuiKeyModFlags,
HorizontalMod: imgui.ImGuiKeyModFlags,
VerticalMod: imgui.ImGuiKeyModFlags,
};
pub const ImPlotInputMap = struct_ImPlotInputMap;
pub const struct_ImBufferWriter = extern struct {
Buffer: [*c]u8,
Size: c_int,
Pos: c_int,
};
pub const ImBufferWriter = struct_ImBufferWriter;
pub const struct_ImPlotNextPlotData = extern struct {
XRangeCond: imgui.ImGuiCond,
YRangeCond: [3]imgui.ImGuiCond,
XRange: ImPlotRange,
YRange: [3]ImPlotRange,
HasXRange: bool,
HasYRange: [3]bool,
ShowDefaultTicksX: bool,
ShowDefaultTicksY: [3]bool,
FmtX: [16]u8,
FmtY: [3][16]u8,
HasFmtX: bool,
HasFmtY: [3]bool,
FitX: bool,
FitY: [3]bool,
LinkedXmin: [*c]f64,
LinkedXmax: [*c]f64,
LinkedYmin: [3][*c]f64,
LinkedYmax: [3][*c]f64,
};
pub const ImPlotNextPlotData = struct_ImPlotNextPlotData;
pub const ImPlotFlags = c_int;
pub const ImPlotAxisFlags = c_int;
pub const struct_ImPlotAxis = extern struct {
Flags: ImPlotAxisFlags,
PreviousFlags: ImPlotAxisFlags,
Range: ImPlotRange,
Pixels: f32,
Orientation: ImPlotOrientation,
Dragging: bool,
ExtHovered: bool,
AllHovered: bool,
Present: bool,
HasRange: bool,
LinkedMin: [*c]f64,
LinkedMax: [*c]f64,
PickerTimeMin: ImPlotTime,
PickerTimeMax: ImPlotTime,
PickerLevel: c_int,
ColorMaj: imgui.ImU32,
ColorMin: imgui.ImU32,
ColorTxt: imgui.ImU32,
RangeCond: imgui.ImGuiCond,
HoverRect: imgui.ImRect,
};
pub const ImPlotAxis = struct_ImPlotAxis;
pub const struct_ImPlotPlot = extern struct {
ID: imgui.ImGuiID,
Flags: ImPlotFlags,
PreviousFlags: ImPlotFlags,
XAxis: ImPlotAxis,
YAxis: [3]ImPlotAxis,
Items: ImPlotItemGroup,
SelectStart: imgui.ImVec2,
SelectRect: imgui.ImRect,
QueryStart: imgui.ImVec2,
QueryRect: imgui.ImRect,
Initialized: bool,
Selecting: bool,
Selected: bool,
ContextLocked: bool,
Querying: bool,
Queried: bool,
DraggingQuery: bool,
FrameHovered: bool,
FrameHeld: bool,
PlotHovered: bool,
CurrentYAxis: c_int,
MousePosLocation: ImPlotLocation,
FrameRect: imgui.ImRect,
CanvasRect: imgui.ImRect,
PlotRect: imgui.ImRect,
AxesRect: imgui.ImRect,
};
pub const ImPlotPlot = struct_ImPlotPlot;
pub const struct_ImPlotAxisColor = opaque {};
pub const ImPlotAxisColor = struct_ImPlotAxisColor;
pub const ImPlotColormap = c_int;
pub const struct_ImPlotStyle = extern struct {
LineWeight: f32,
Marker: c_int,
MarkerSize: f32,
MarkerWeight: f32,
FillAlpha: f32,
ErrorBarSize: f32,
ErrorBarWeight: f32,
DigitalBitHeight: f32,
DigitalBitGap: f32,
PlotBorderSize: f32,
MinorAlpha: f32,
MajorTickLen: imgui.ImVec2,
MinorTickLen: imgui.ImVec2,
MajorTickSize: imgui.ImVec2,
MinorTickSize: imgui.ImVec2,
MajorGridSize: imgui.ImVec2,
MinorGridSize: imgui.ImVec2,
PlotPadding: imgui.ImVec2,
LabelPadding: imgui.ImVec2,
LegendPadding: imgui.ImVec2,
LegendInnerPadding: imgui.ImVec2,
LegendSpacing: imgui.ImVec2,
MousePosPadding: imgui.ImVec2,
AnnotationPadding: imgui.ImVec2,
FitPadding: imgui.ImVec2,
PlotDefaultSize: imgui.ImVec2,
PlotMinSize: imgui.ImVec2,
Colors: [24]imgui.ImVec4,
Colormap: ImPlotColormap,
AntiAliasedLines: bool,
UseLocalTime: bool,
UseISO8601: bool,
Use24HourClock: bool,
};
pub const ImPlotStyle = struct_ImPlotStyle;
pub const struct_ImPlotLimits = extern struct {
X: ImPlotRange,
Y: ImPlotRange,
};
pub const ImPlotLimits = struct_ImPlotLimits;
pub const struct_ImPlotPoint = extern struct {
x: f64,
y: f64,
};
pub const ImPlotPoint = struct_ImPlotPoint;
pub const struct_ImVector_ImPlotPlot = extern struct {
Size: c_int,
Capacity: c_int,
Data: [*c]ImPlotPlot,
};
pub const ImVector_ImPlotPlot = struct_ImVector_ImPlotPlot;
pub const struct_ImPool_ImPlotPlot = extern struct {
Buf: ImVector_ImPlotPlot,
Map: imgui.ImGuiStorage,
FreeIdx: imgui.ImPoolIdx,
};
pub const ImPool_ImPlotPlot = struct_ImPool_ImPlotPlot;
pub const struct_ImVector_ImPlotSubplot = extern struct {
Size: c_int,
Capacity: c_int,
Data: [*c]ImPlotSubplot,
};
pub const ImVector_ImPlotSubplot = struct_ImVector_ImPlotSubplot;
pub const struct_ImPool_ImPlotSubplot = extern struct {
Buf: ImVector_ImPlotSubplot,
Map: imgui.ImGuiStorage,
FreeIdx: imgui.ImPoolIdx,
};
pub const ImPool_ImPlotSubplot = struct_ImPool_ImPlotSubplot;
pub const ImPlotScale = c_int;
pub const struct_ImVector_ImPlotColormap = extern struct {
Size: c_int,
Capacity: c_int,
Data: [*c]ImPlotColormap,
};
pub const ImVector_ImPlotColormap = struct_ImVector_ImPlotColormap;
pub const struct_ImVector_double = extern struct {
Size: c_int,
Capacity: c_int,
Data: [*c]f64,
};
pub const ImVector_double = struct_ImVector_double;
pub const struct_ImPool_ImPlotAlignmentData = extern struct {
Buf: ImVector_ImPlotAlignmentData,
Map: imgui.ImGuiStorage,
FreeIdx: imgui.ImPoolIdx,
};
pub const ImPool_ImPlotAlignmentData = struct_ImPool_ImPlotAlignmentData;
pub const struct_ImPlotContext = extern struct {
Plots: ImPool_ImPlotPlot,
Subplots: ImPool_ImPlotSubplot,
CurrentPlot: [*c]ImPlotPlot,
CurrentSubplot: [*c]ImPlotSubplot,
CurrentItems: [*c]ImPlotItemGroup,
CurrentItem: [*c]ImPlotItem,
PreviousItem: [*c]ImPlotItem,
CTicks: ImPlotTickCollection,
XTicks: ImPlotTickCollection,
YTicks: [3]ImPlotTickCollection,
YAxisReference: [3]f32,
Annotations: ImPlotAnnotationCollection,
Scales: [3]ImPlotScale,
PixelRange: [3]imgui.ImRect,
Mx: f64,
My: [3]f64,
LogDenX: f64,
LogDenY: [3]f64,
ExtentsX: ImPlotRange,
ExtentsY: [3]ImPlotRange,
FitThisFrame: bool,
FitX: bool,
FitY: [3]bool,
RenderX: bool,
RenderY: [3]bool,
ChildWindowMade: bool,
Style: ImPlotStyle,
ColorModifiers: imgui.ImVector_ImGuiColorMod,
StyleModifiers: imgui.ImVector_ImGuiStyleMod,
ColormapData: ImPlotColormapData,
ColormapModifiers: ImVector_ImPlotColormap,
Tm: tm,
Temp1: ImVector_double,
Temp2: ImVector_double,
DigitalPlotItemCnt: c_int,
DigitalPlotOffset: c_int,
NextPlotData: ImPlotNextPlotData,
NextItemData: ImPlotNextItemData,
InputMap: ImPlotInputMap,
MousePos: [3]ImPlotPoint,
AlignmentData: ImPool_ImPlotAlignmentData,
CurrentAlignmentH: [*c]ImPlotAlignmentData,
CurrentAlignmentV: [*c]ImPlotAlignmentData,
};
pub const ImPlotContext = struct_ImPlotContext;
pub const ImPlotCol = c_int;
pub const ImPlotStyleVar = c_int;
pub const ImPlotYAxis = c_int;
pub const ImPlotBin = c_int;
pub extern var GImPlot: [*c]ImPlotContext;
pub const ImPlotTimeUnit = c_int;
pub const struct_ImVector_ImS16 = extern struct {
Size: c_int,
Capacity: c_int,
Data: [*c]imgui.ImS16,
};
pub const ImVector_ImS16 = struct_ImVector_ImS16;
pub const struct_ImVector_ImS32 = extern struct {
Size: c_int,
Capacity: c_int,
Data: [*c]imgui.ImS32,
};
pub const ImVector_ImS32 = struct_ImVector_ImS32;
pub const struct_ImVector_ImS64 = extern struct {
Size: c_int,
Capacity: c_int,
Data: [*c]imgui.ImS64,
};
pub const ImVector_ImS64 = struct_ImVector_ImS64;
pub const struct_ImVector_ImS8 = extern struct {
Size: c_int,
Capacity: c_int,
Data: [*c]imgui.ImS8,
};
pub const ImVector_ImS8 = struct_ImVector_ImS8;
pub const struct_ImVector_ImU16 = extern struct {
Size: c_int,
Capacity: c_int,
Data: [*c]imgui.ImU16,
};
pub const ImVector_ImU16 = struct_ImVector_ImU16;
pub const struct_ImVector_ImU64 = extern struct {
Size: c_int,
Capacity: c_int,
Data: [*c]imgui.ImU64,
};
pub const ImVector_ImU64 = struct_ImVector_ImU64;
pub const struct_ImVector_ImU8 = extern struct {
Size: c_int,
Capacity: c_int,
Data: [*c]imgui.ImU8,
};
pub const ImVector_ImU8 = struct_ImVector_ImU8;
pub const ImPlotFlags_None: c_int = 0;
pub const ImPlotFlags_NoTitle: c_int = 1;
pub const ImPlotFlags_NoLegend: c_int = 2;
pub const ImPlotFlags_NoMenus: c_int = 4;
pub const ImPlotFlags_NoBoxSelect: c_int = 8;
pub const ImPlotFlags_NoMousePos: c_int = 16;
pub const ImPlotFlags_NoHighlight: c_int = 32;
pub const ImPlotFlags_NoChild: c_int = 64;
pub const ImPlotFlags_Equal: c_int = 128;
pub const ImPlotFlags_YAxis2: c_int = 256;
pub const ImPlotFlags_YAxis3: c_int = 512;
pub const ImPlotFlags_Query: c_int = 1024;
pub const ImPlotFlags_Crosshairs: c_int = 2048;
pub const ImPlotFlags_AntiAliased: c_int = 4096;
pub const ImPlotFlags_CanvasOnly: c_int = 31;
pub const ImPlotFlags_ = c_uint;
pub const ImPlotAxisFlags_None: c_int = 0;
pub const ImPlotAxisFlags_NoLabel: c_int = 1;
pub const ImPlotAxisFlags_NoGridLines: c_int = 2;
pub const ImPlotAxisFlags_NoTickMarks: c_int = 4;
pub const ImPlotAxisFlags_NoTickLabels: c_int = 8;
pub const ImPlotAxisFlags_Foreground: c_int = 16;
pub const ImPlotAxisFlags_LogScale: c_int = 32;
pub const ImPlotAxisFlags_Time: c_int = 64;
pub const ImPlotAxisFlags_Invert: c_int = 128;
pub const ImPlotAxisFlags_NoInitialFit: c_int = 256;
pub const ImPlotAxisFlags_AutoFit: c_int = 512;
pub const ImPlotAxisFlags_RangeFit: c_int = 1024;
pub const ImPlotAxisFlags_LockMin: c_int = 2048;
pub const ImPlotAxisFlags_LockMax: c_int = 4096;
pub const ImPlotAxisFlags_Lock: c_int = 6144;
pub const ImPlotAxisFlags_NoDecorations: c_int = 15;
pub const ImPlotAxisFlags_ = c_uint;
pub const ImPlotSubplotFlags_None: c_int = 0;
pub const ImPlotSubplotFlags_NoTitle: c_int = 1;
pub const ImPlotSubplotFlags_NoLegend: c_int = 2;
pub const ImPlotSubplotFlags_NoMenus: c_int = 4;
pub const ImPlotSubplotFlags_NoResize: c_int = 8;
pub const ImPlotSubplotFlags_NoAlign: c_int = 16;
pub const ImPlotSubplotFlags_ShareItems: c_int = 32;
pub const ImPlotSubplotFlags_LinkRows: c_int = 64;
pub const ImPlotSubplotFlags_LinkCols: c_int = 128;
pub const ImPlotSubplotFlags_LinkAllX: c_int = 256;
pub const ImPlotSubplotFlags_LinkAllY: c_int = 512;
pub const ImPlotSubplotFlags_ColMajor: c_int = 1024;
pub const ImPlotSubplotFlags_ = c_uint;
pub const ImPlotCol_Line: c_int = 0;
pub const ImPlotCol_Fill: c_int = 1;
pub const ImPlotCol_MarkerOutline: c_int = 2;
pub const ImPlotCol_MarkerFill: c_int = 3;
pub const ImPlotCol_ErrorBar: c_int = 4;
pub const ImPlotCol_FrameBg: c_int = 5;
pub const ImPlotCol_PlotBg: c_int = 6;
pub const ImPlotCol_PlotBorder: c_int = 7;
pub const ImPlotCol_LegendBg: c_int = 8;
pub const ImPlotCol_LegendBorder: c_int = 9;
pub const ImPlotCol_LegendText: c_int = 10;
pub const ImPlotCol_TitleText: c_int = 11;
pub const ImPlotCol_InlayText: c_int = 12;
pub const ImPlotCol_XAxis: c_int = 13;
pub const ImPlotCol_XAxisGrid: c_int = 14;
pub const ImPlotCol_YAxis: c_int = 15;
pub const ImPlotCol_YAxisGrid: c_int = 16;
pub const ImPlotCol_YAxis2: c_int = 17;
pub const ImPlotCol_YAxisGrid2: c_int = 18;
pub const ImPlotCol_YAxis3: c_int = 19;
pub const ImPlotCol_YAxisGrid3: c_int = 20;
pub const ImPlotCol_Selection: c_int = 21;
pub const ImPlotCol_Query: c_int = 22;
pub const ImPlotCol_Crosshairs: c_int = 23;
pub const ImPlotCol_COUNT: c_int = 24;
pub const ImPlotCol_ = c_uint;
pub const ImPlotStyleVar_LineWeight: c_int = 0;
pub const ImPlotStyleVar_Marker: c_int = 1;
pub const ImPlotStyleVar_MarkerSize: c_int = 2;
pub const ImPlotStyleVar_MarkerWeight: c_int = 3;
pub const ImPlotStyleVar_FillAlpha: c_int = 4;
pub const ImPlotStyleVar_ErrorBarSize: c_int = 5;
pub const ImPlotStyleVar_ErrorBarWeight: c_int = 6;
pub const ImPlotStyleVar_DigitalBitHeight: c_int = 7;
pub const ImPlotStyleVar_DigitalBitGap: c_int = 8;
pub const ImPlotStyleVar_PlotBorderSize: c_int = 9;
pub const ImPlotStyleVar_MinorAlpha: c_int = 10;
pub const ImPlotStyleVar_MajorTickLen: c_int = 11;
pub const ImPlotStyleVar_MinorTickLen: c_int = 12;
pub const ImPlotStyleVar_MajorTickSize: c_int = 13;
pub const ImPlotStyleVar_MinorTickSize: c_int = 14;
pub const ImPlotStyleVar_MajorGridSize: c_int = 15;
pub const ImPlotStyleVar_MinorGridSize: c_int = 16;
pub const ImPlotStyleVar_PlotPadding: c_int = 17;
pub const ImPlotStyleVar_LabelPadding: c_int = 18;
pub const ImPlotStyleVar_LegendPadding: c_int = 19;
pub const ImPlotStyleVar_LegendInnerPadding: c_int = 20;
pub const ImPlotStyleVar_LegendSpacing: c_int = 21;
pub const ImPlotStyleVar_MousePosPadding: c_int = 22;
pub const ImPlotStyleVar_AnnotationPadding: c_int = 23;
pub const ImPlotStyleVar_FitPadding: c_int = 24;
pub const ImPlotStyleVar_PlotDefaultSize: c_int = 25;
pub const ImPlotStyleVar_PlotMinSize: c_int = 26;
pub const ImPlotStyleVar_COUNT: c_int = 27;
pub const ImPlotStyleVar_ = c_uint;
pub const ImPlotMarker_None: c_int = -1;
pub const ImPlotMarker_Circle: c_int = 0;
pub const ImPlotMarker_Square: c_int = 1;
pub const ImPlotMarker_Diamond: c_int = 2;
pub const ImPlotMarker_Up: c_int = 3;
pub const ImPlotMarker_Down: c_int = 4;
pub const ImPlotMarker_Left: c_int = 5;
pub const ImPlotMarker_Right: c_int = 6;
pub const ImPlotMarker_Cross: c_int = 7;
pub const ImPlotMarker_Plus: c_int = 8;
pub const ImPlotMarker_Asterisk: c_int = 9;
pub const ImPlotMarker_COUNT: c_int = 10;
pub const ImPlotMarker_ = c_int;
pub const ImPlotColormap_Deep: c_int = 0;
pub const ImPlotColormap_Dark: c_int = 1;
pub const ImPlotColormap_Pastel: c_int = 2;
pub const ImPlotColormap_Paired: c_int = 3;
pub const ImPlotColormap_Viridis: c_int = 4;
pub const ImPlotColormap_Plasma: c_int = 5;
pub const ImPlotColormap_Hot: c_int = 6;
pub const ImPlotColormap_Cool: c_int = 7;
pub const ImPlotColormap_Pink: c_int = 8;
pub const ImPlotColormap_Jet: c_int = 9;
pub const ImPlotColormap_Twilight: c_int = 10;
pub const ImPlotColormap_RdBu: c_int = 11;
pub const ImPlotColormap_BrBG: c_int = 12;
pub const ImPlotColormap_PiYG: c_int = 13;
pub const ImPlotColormap_Spectral: c_int = 14;
pub const ImPlotColormap_Greys: c_int = 15;
pub const ImPlotColormap_ = c_uint;
pub const ImPlotLocation_Center: c_int = 0;
pub const ImPlotLocation_North: c_int = 1;
pub const ImPlotLocation_South: c_int = 2;
pub const ImPlotLocation_West: c_int = 4;
pub const ImPlotLocation_East: c_int = 8;
pub const ImPlotLocation_NorthWest: c_int = 5;
pub const ImPlotLocation_NorthEast: c_int = 9;
pub const ImPlotLocation_SouthWest: c_int = 6;
pub const ImPlotLocation_SouthEast: c_int = 10;
pub const ImPlotLocation_ = c_uint;
pub const ImPlotOrientation_Horizontal: c_int = 0;
pub const ImPlotOrientation_Vertical: c_int = 1;
pub const ImPlotOrientation_ = c_uint;
pub const ImPlotYAxis_1: c_int = 0;
pub const ImPlotYAxis_2: c_int = 1;
pub const ImPlotYAxis_3: c_int = 2;
pub const ImPlotYAxis_ = c_uint;
pub const ImPlotBin_Sqrt: c_int = -1;
pub const ImPlotBin_Sturges: c_int = -2;
pub const ImPlotBin_Rice: c_int = -3;
pub const ImPlotBin_Scott: c_int = -4;
pub const ImPlotBin_ = c_int;
pub const ImPlotScale_LinLin: c_int = 0;
pub const ImPlotScale_LogLin: c_int = 1;
pub const ImPlotScale_LinLog: c_int = 2;
pub const ImPlotScale_LogLog: c_int = 3;
pub const ImPlotScale_ = c_uint;
pub const ImPlotTimeUnit_Us: c_int = 0;
pub const ImPlotTimeUnit_Ms: c_int = 1;
pub const ImPlotTimeUnit_S: c_int = 2;
pub const ImPlotTimeUnit_Min: c_int = 3;
pub const ImPlotTimeUnit_Hr: c_int = 4;
pub const ImPlotTimeUnit_Day: c_int = 5;
pub const ImPlotTimeUnit_Mo: c_int = 6;
pub const ImPlotTimeUnit_Yr: c_int = 7;
pub const ImPlotTimeUnit_COUNT: c_int = 8;
pub const ImPlotTimeUnit_ = c_uint;
pub const ImPlotDateFmt_None: c_int = 0;
pub const ImPlotDateFmt_DayMo: c_int = 1;
pub const ImPlotDateFmt_DayMoYr: c_int = 2;
pub const ImPlotDateFmt_MoYr: c_int = 3;
pub const ImPlotDateFmt_Mo: c_int = 4;
pub const ImPlotDateFmt_Yr: c_int = 5;
pub const ImPlotDateFmt_ = c_uint;
pub const ImPlotTimeFmt_None: c_int = 0;
pub const ImPlotTimeFmt_Us: c_int = 1;
pub const ImPlotTimeFmt_SUs: c_int = 2;
pub const ImPlotTimeFmt_SMs: c_int = 3;
pub const ImPlotTimeFmt_S: c_int = 4;
pub const ImPlotTimeFmt_HrMinSMs: c_int = 5;
pub const ImPlotTimeFmt_HrMinS: c_int = 6;
pub const ImPlotTimeFmt_HrMin: c_int = 7;
pub const ImPlotTimeFmt_Hr: c_int = 8;
pub const ImPlotTimeFmt_ = c_uint;
pub extern fn ImPlotPoint_ImPlotPoint_Nil() [*c]ImPlotPoint;
pub extern fn ImPlotPoint_destroy(self: [*c]ImPlotPoint) void;
pub extern fn ImPlotPoint_ImPlotPoint_double(_x: f64, _y: f64) [*c]ImPlotPoint;
pub extern fn ImPlotPoint_ImPlotPoint_Vec2(p: imgui.ImVec2) [*c]ImPlotPoint;
pub extern fn ImPlotRange_ImPlotRange_Nil() [*c]ImPlotRange;
pub extern fn ImPlotRange_destroy(self: [*c]ImPlotRange) void;
pub extern fn ImPlotRange_ImPlotRange_double(_min: f64, _max: f64) [*c]ImPlotRange;
pub extern fn ImPlotRange_Contains(self: [*c]ImPlotRange, value: f64) bool;
pub extern fn ImPlotRange_Size(self: [*c]ImPlotRange) f64;
pub extern fn ImPlotLimits_ImPlotLimits_Nil() [*c]ImPlotLimits;
pub extern fn ImPlotLimits_destroy(self: [*c]ImPlotLimits) void;
pub extern fn ImPlotLimits_ImPlotLimits_double(x_min: f64, x_max: f64, y_min: f64, y_max: f64) [*c]ImPlotLimits;
pub extern fn ImPlotLimits_Contains_PlotPoInt(self: [*c]ImPlotLimits, p: ImPlotPoint) bool;
pub extern fn ImPlotLimits_Contains_double(self: [*c]ImPlotLimits, x: f64, y: f64) bool;
pub extern fn ImPlotLimits_Min(pOut: [*c]ImPlotPoint, self: [*c]ImPlotLimits) void;
pub extern fn ImPlotLimits_Max(pOut: [*c]ImPlotPoint, self: [*c]ImPlotLimits) void;
pub extern fn ImPlotStyle_ImPlotStyle() [*c]ImPlotStyle;
pub extern fn ImPlotStyle_destroy(self: [*c]ImPlotStyle) void;
pub extern fn ImPlot_CreateContext() [*c]ImPlotContext;
pub extern fn ImPlot_DestroyContext(ctx: [*c]ImPlotContext) void;
pub extern fn ImPlot_GetCurrentContext() [*c]ImPlotContext;
pub extern fn ImPlot_SetCurrentContext(ctx: [*c]ImPlotContext) void;
pub extern fn ImPlot_SetImGuiContext(ctx: [*c]imgui.ImGuiContext) void;
pub extern fn ImPlot_BeginPlot(title_id: [*c]const u8, x_label: [*c]const u8, y_label: [*c]const u8, size: imgui.ImVec2, flags: ImPlotFlags, x_flags: ImPlotAxisFlags, y_flags: ImPlotAxisFlags, y2_flags: ImPlotAxisFlags, y3_flags: ImPlotAxisFlags, y2_label: [*c]const u8, y3_label: [*c]const u8) bool;
pub extern fn ImPlot_EndPlot() void;
pub extern fn ImPlot_BeginSubplots(title_id: [*c]const u8, rows: c_int, cols: c_int, size: imgui.ImVec2, flags: ImPlotSubplotFlags, row_ratios: [*c]f32, col_ratios: [*c]f32) bool;
pub extern fn ImPlot_EndSubplots() void;
pub extern fn ImPlot_PlotLine_FloatPtrInt(label_id: [*c]const u8, values: [*c]const f32, count: c_int, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotLine_doublePtrInt(label_id: [*c]const u8, values: [*c]const f64, count: c_int, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotLine_S8PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImS8, count: c_int, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotLine_U8PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImU8, count: c_int, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotLine_S16PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImS16, count: c_int, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotLine_U16PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImU16, count: c_int, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotLine_S32PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImS32, count: c_int, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotLine_U32PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImU32, count: c_int, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotLine_S64PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImS64, count: c_int, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotLine_U64PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImU64, count: c_int, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotLine_FloatPtrFloatPtr(label_id: [*c]const u8, xs: [*c]const f32, ys: [*c]const f32, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotLine_doublePtrdoublePtr(label_id: [*c]const u8, xs: [*c]const f64, ys: [*c]const f64, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotLine_S8PtrS8Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS8, ys: [*c]const imgui.ImS8, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotLine_U8PtrU8Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU8, ys: [*c]const imgui.ImU8, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotLine_S16PtrS16Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS16, ys: [*c]const imgui.ImS16, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotLine_U16PtrU16Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU16, ys: [*c]const imgui.ImU16, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotLine_S32PtrS32Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS32, ys: [*c]const imgui.ImS32, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotLine_U32PtrU32Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU32, ys: [*c]const imgui.ImU32, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotLine_S64PtrS64Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS64, ys: [*c]const imgui.ImS64, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotLine_U64PtrU64Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU64, ys: [*c]const imgui.ImU64, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotScatter_FloatPtrInt(label_id: [*c]const u8, values: [*c]const f32, count: c_int, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotScatter_doublePtrInt(label_id: [*c]const u8, values: [*c]const f64, count: c_int, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotScatter_S8PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImS8, count: c_int, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotScatter_U8PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImU8, count: c_int, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotScatter_S16PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImS16, count: c_int, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotScatter_U16PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImU16, count: c_int, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotScatter_S32PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImS32, count: c_int, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotScatter_U32PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImU32, count: c_int, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotScatter_S64PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImS64, count: c_int, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotScatter_U64PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImU64, count: c_int, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotScatter_FloatPtrFloatPtr(label_id: [*c]const u8, xs: [*c]const f32, ys: [*c]const f32, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotScatter_doublePtrdoublePtr(label_id: [*c]const u8, xs: [*c]const f64, ys: [*c]const f64, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotScatter_S8PtrS8Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS8, ys: [*c]const imgui.ImS8, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotScatter_U8PtrU8Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU8, ys: [*c]const imgui.ImU8, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotScatter_S16PtrS16Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS16, ys: [*c]const imgui.ImS16, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotScatter_U16PtrU16Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU16, ys: [*c]const imgui.ImU16, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotScatter_S32PtrS32Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS32, ys: [*c]const imgui.ImS32, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotScatter_U32PtrU32Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU32, ys: [*c]const imgui.ImU32, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotScatter_S64PtrS64Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS64, ys: [*c]const imgui.ImS64, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotScatter_U64PtrU64Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU64, ys: [*c]const imgui.ImU64, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStairs_FloatPtrInt(label_id: [*c]const u8, values: [*c]const f32, count: c_int, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStairs_doublePtrInt(label_id: [*c]const u8, values: [*c]const f64, count: c_int, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStairs_S8PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImS8, count: c_int, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStairs_U8PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImU8, count: c_int, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStairs_S16PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImS16, count: c_int, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStairs_U16PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImU16, count: c_int, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStairs_S32PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImS32, count: c_int, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStairs_U32PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImU32, count: c_int, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStairs_S64PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImS64, count: c_int, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStairs_U64PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImU64, count: c_int, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStairs_FloatPtrFloatPtr(label_id: [*c]const u8, xs: [*c]const f32, ys: [*c]const f32, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStairs_doublePtrdoublePtr(label_id: [*c]const u8, xs: [*c]const f64, ys: [*c]const f64, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStairs_S8PtrS8Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS8, ys: [*c]const imgui.ImS8, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStairs_U8PtrU8Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU8, ys: [*c]const imgui.ImU8, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStairs_S16PtrS16Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS16, ys: [*c]const imgui.ImS16, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStairs_U16PtrU16Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU16, ys: [*c]const imgui.ImU16, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStairs_S32PtrS32Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS32, ys: [*c]const imgui.ImS32, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStairs_U32PtrU32Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU32, ys: [*c]const imgui.ImU32, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStairs_S64PtrS64Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS64, ys: [*c]const imgui.ImS64, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStairs_U64PtrU64Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU64, ys: [*c]const imgui.ImU64, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStairsG(label_id: [*c]const u8, getter: ?fn (?*anyopaque, c_int) callconv(.C) ImPlotPoint, data: ?*anyopaque, count: c_int) void;
pub extern fn ImPlot_PlotShaded_FloatPtrInt(label_id: [*c]const u8, values: [*c]const f32, count: c_int, y_ref: f64, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotShaded_doublePtrInt(label_id: [*c]const u8, values: [*c]const f64, count: c_int, y_ref: f64, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotShaded_S8PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImS8, count: c_int, y_ref: f64, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotShaded_U8PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImU8, count: c_int, y_ref: f64, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotShaded_S16PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImS16, count: c_int, y_ref: f64, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotShaded_U16PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImU16, count: c_int, y_ref: f64, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotShaded_S32PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImS32, count: c_int, y_ref: f64, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotShaded_U32PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImU32, count: c_int, y_ref: f64, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotShaded_S64PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImS64, count: c_int, y_ref: f64, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotShaded_U64PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImU64, count: c_int, y_ref: f64, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotShaded_FloatPtrFloatPtrInt(label_id: [*c]const u8, xs: [*c]const f32, ys: [*c]const f32, count: c_int, y_ref: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotShaded_doublePtrdoublePtrInt(label_id: [*c]const u8, xs: [*c]const f64, ys: [*c]const f64, count: c_int, y_ref: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotShaded_S8PtrS8PtrInt(label_id: [*c]const u8, xs: [*c]const imgui.ImS8, ys: [*c]const imgui.ImS8, count: c_int, y_ref: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotShaded_U8PtrU8PtrInt(label_id: [*c]const u8, xs: [*c]const imgui.ImU8, ys: [*c]const imgui.ImU8, count: c_int, y_ref: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotShaded_S16PtrS16PtrInt(label_id: [*c]const u8, xs: [*c]const imgui.ImS16, ys: [*c]const imgui.ImS16, count: c_int, y_ref: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotShaded_U16PtrU16PtrInt(label_id: [*c]const u8, xs: [*c]const imgui.ImU16, ys: [*c]const imgui.ImU16, count: c_int, y_ref: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotShaded_S32PtrS32PtrInt(label_id: [*c]const u8, xs: [*c]const imgui.ImS32, ys: [*c]const imgui.ImS32, count: c_int, y_ref: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotShaded_U32PtrU32PtrInt(label_id: [*c]const u8, xs: [*c]const imgui.ImU32, ys: [*c]const imgui.ImU32, count: c_int, y_ref: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotShaded_S64PtrS64PtrInt(label_id: [*c]const u8, xs: [*c]const imgui.ImS64, ys: [*c]const imgui.ImS64, count: c_int, y_ref: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotShaded_U64PtrU64PtrInt(label_id: [*c]const u8, xs: [*c]const imgui.ImU64, ys: [*c]const imgui.ImU64, count: c_int, y_ref: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotShaded_FloatPtrFloatPtrFloatPtr(label_id: [*c]const u8, xs: [*c]const f32, ys1: [*c]const f32, ys2: [*c]const f32, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotShaded_doublePtrdoublePtrdoublePtr(label_id: [*c]const u8, xs: [*c]const f64, ys1: [*c]const f64, ys2: [*c]const f64, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotShaded_S8PtrS8PtrS8Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS8, ys1: [*c]const imgui.ImS8, ys2: [*c]const imgui.ImS8, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotShaded_U8PtrU8PtrU8Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU8, ys1: [*c]const imgui.ImU8, ys2: [*c]const imgui.ImU8, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotShaded_S16PtrS16PtrS16Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS16, ys1: [*c]const imgui.ImS16, ys2: [*c]const imgui.ImS16, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotShaded_U16PtrU16PtrU16Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU16, ys1: [*c]const imgui.ImU16, ys2: [*c]const imgui.ImU16, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotShaded_S32PtrS32PtrS32Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS32, ys1: [*c]const imgui.ImS32, ys2: [*c]const imgui.ImS32, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotShaded_U32PtrU32PtrU32Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU32, ys1: [*c]const imgui.ImU32, ys2: [*c]const imgui.ImU32, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotShaded_S64PtrS64PtrS64Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS64, ys1: [*c]const imgui.ImS64, ys2: [*c]const imgui.ImS64, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotShaded_U64PtrU64PtrU64Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU64, ys1: [*c]const imgui.ImU64, ys2: [*c]const imgui.ImU64, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBars_FloatPtrInt(label_id: [*c]const u8, values: [*c]const f32, count: c_int, width: f64, shift: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBars_doublePtrInt(label_id: [*c]const u8, values: [*c]const f64, count: c_int, width: f64, shift: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBars_S8PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImS8, count: c_int, width: f64, shift: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBars_U8PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImU8, count: c_int, width: f64, shift: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBars_S16PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImS16, count: c_int, width: f64, shift: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBars_U16PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImU16, count: c_int, width: f64, shift: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBars_S32PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImS32, count: c_int, width: f64, shift: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBars_U32PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImU32, count: c_int, width: f64, shift: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBars_S64PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImS64, count: c_int, width: f64, shift: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBars_U64PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImU64, count: c_int, width: f64, shift: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBars_FloatPtrFloatPtr(label_id: [*c]const u8, xs: [*c]const f32, ys: [*c]const f32, count: c_int, width: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBars_doublePtrdoublePtr(label_id: [*c]const u8, xs: [*c]const f64, ys: [*c]const f64, count: c_int, width: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBars_S8PtrS8Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS8, ys: [*c]const imgui.ImS8, count: c_int, width: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBars_U8PtrU8Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU8, ys: [*c]const imgui.ImU8, count: c_int, width: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBars_S16PtrS16Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS16, ys: [*c]const imgui.ImS16, count: c_int, width: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBars_U16PtrU16Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU16, ys: [*c]const imgui.ImU16, count: c_int, width: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBars_S32PtrS32Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS32, ys: [*c]const imgui.ImS32, count: c_int, width: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBars_U32PtrU32Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU32, ys: [*c]const imgui.ImU32, count: c_int, width: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBars_S64PtrS64Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS64, ys: [*c]const imgui.ImS64, count: c_int, width: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBars_U64PtrU64Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU64, ys: [*c]const imgui.ImU64, count: c_int, width: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBarsH_FloatPtrInt(label_id: [*c]const u8, values: [*c]const f32, count: c_int, height: f64, shift: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBarsH_doublePtrInt(label_id: [*c]const u8, values: [*c]const f64, count: c_int, height: f64, shift: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBarsH_S8PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImS8, count: c_int, height: f64, shift: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBarsH_U8PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImU8, count: c_int, height: f64, shift: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBarsH_S16PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImS16, count: c_int, height: f64, shift: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBarsH_U16PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImU16, count: c_int, height: f64, shift: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBarsH_S32PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImS32, count: c_int, height: f64, shift: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBarsH_U32PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImU32, count: c_int, height: f64, shift: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBarsH_S64PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImS64, count: c_int, height: f64, shift: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBarsH_U64PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImU64, count: c_int, height: f64, shift: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBarsH_FloatPtrFloatPtr(label_id: [*c]const u8, xs: [*c]const f32, ys: [*c]const f32, count: c_int, height: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBarsH_doublePtrdoublePtr(label_id: [*c]const u8, xs: [*c]const f64, ys: [*c]const f64, count: c_int, height: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBarsH_S8PtrS8Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS8, ys: [*c]const imgui.ImS8, count: c_int, height: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBarsH_U8PtrU8Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU8, ys: [*c]const imgui.ImU8, count: c_int, height: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBarsH_S16PtrS16Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS16, ys: [*c]const imgui.ImS16, count: c_int, height: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBarsH_U16PtrU16Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU16, ys: [*c]const imgui.ImU16, count: c_int, height: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBarsH_S32PtrS32Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS32, ys: [*c]const imgui.ImS32, count: c_int, height: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBarsH_U32PtrU32Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU32, ys: [*c]const imgui.ImU32, count: c_int, height: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBarsH_S64PtrS64Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS64, ys: [*c]const imgui.ImS64, count: c_int, height: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotBarsH_U64PtrU64Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU64, ys: [*c]const imgui.ImU64, count: c_int, height: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBars_FloatPtrFloatPtrFloatPtrInt(label_id: [*c]const u8, xs: [*c]const f32, ys: [*c]const f32, err: [*c]const f32, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBars_doublePtrdoublePtrdoublePtrInt(label_id: [*c]const u8, xs: [*c]const f64, ys: [*c]const f64, err: [*c]const f64, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBars_S8PtrS8PtrS8PtrInt(label_id: [*c]const u8, xs: [*c]const imgui.ImS8, ys: [*c]const imgui.ImS8, err: [*c]const imgui.ImS8, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBars_U8PtrU8PtrU8PtrInt(label_id: [*c]const u8, xs: [*c]const imgui.ImU8, ys: [*c]const imgui.ImU8, err: [*c]const imgui.ImU8, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBars_S16PtrS16PtrS16PtrInt(label_id: [*c]const u8, xs: [*c]const imgui.ImS16, ys: [*c]const imgui.ImS16, err: [*c]const imgui.ImS16, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBars_U16PtrU16PtrU16PtrInt(label_id: [*c]const u8, xs: [*c]const imgui.ImU16, ys: [*c]const imgui.ImU16, err: [*c]const imgui.ImU16, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBars_S32PtrS32PtrS32PtrInt(label_id: [*c]const u8, xs: [*c]const imgui.ImS32, ys: [*c]const imgui.ImS32, err: [*c]const imgui.ImS32, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBars_U32PtrU32PtrU32PtrInt(label_id: [*c]const u8, xs: [*c]const imgui.ImU32, ys: [*c]const imgui.ImU32, err: [*c]const imgui.ImU32, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBars_S64PtrS64PtrS64PtrInt(label_id: [*c]const u8, xs: [*c]const imgui.ImS64, ys: [*c]const imgui.ImS64, err: [*c]const imgui.ImS64, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBars_U64PtrU64PtrU64PtrInt(label_id: [*c]const u8, xs: [*c]const imgui.ImU64, ys: [*c]const imgui.ImU64, err: [*c]const imgui.ImU64, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBars_FloatPtrFloatPtrFloatPtrFloatPtr(label_id: [*c]const u8, xs: [*c]const f32, ys: [*c]const f32, neg: [*c]const f32, pos: [*c]const f32, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBars_doublePtrdoublePtrdoublePtrdoublePtr(label_id: [*c]const u8, xs: [*c]const f64, ys: [*c]const f64, neg: [*c]const f64, pos: [*c]const f64, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBars_S8PtrS8PtrS8PtrS8Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS8, ys: [*c]const imgui.ImS8, neg: [*c]const imgui.ImS8, pos: [*c]const imgui.ImS8, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBars_U8PtrU8PtrU8PtrU8Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU8, ys: [*c]const imgui.ImU8, neg: [*c]const imgui.ImU8, pos: [*c]const imgui.ImU8, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBars_S16PtrS16PtrS16PtrS16Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS16, ys: [*c]const imgui.ImS16, neg: [*c]const imgui.ImS16, pos: [*c]const imgui.ImS16, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBars_U16PtrU16PtrU16PtrU16Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU16, ys: [*c]const imgui.ImU16, neg: [*c]const imgui.ImU16, pos: [*c]const imgui.ImU16, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBars_S32PtrS32PtrS32PtrS32Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS32, ys: [*c]const imgui.ImS32, neg: [*c]const imgui.ImS32, pos: [*c]const imgui.ImS32, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBars_U32PtrU32PtrU32PtrU32Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU32, ys: [*c]const imgui.ImU32, neg: [*c]const imgui.ImU32, pos: [*c]const imgui.ImU32, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBars_S64PtrS64PtrS64PtrS64Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS64, ys: [*c]const imgui.ImS64, neg: [*c]const imgui.ImS64, pos: [*c]const imgui.ImS64, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBars_U64PtrU64PtrU64PtrU64Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU64, ys: [*c]const imgui.ImU64, neg: [*c]const imgui.ImU64, pos: [*c]const imgui.ImU64, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBarsH_FloatPtrFloatPtrFloatPtrInt(label_id: [*c]const u8, xs: [*c]const f32, ys: [*c]const f32, err: [*c]const f32, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBarsH_doublePtrdoublePtrdoublePtrInt(label_id: [*c]const u8, xs: [*c]const f64, ys: [*c]const f64, err: [*c]const f64, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBarsH_S8PtrS8PtrS8PtrInt(label_id: [*c]const u8, xs: [*c]const imgui.ImS8, ys: [*c]const imgui.ImS8, err: [*c]const imgui.ImS8, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBarsH_U8PtrU8PtrU8PtrInt(label_id: [*c]const u8, xs: [*c]const imgui.ImU8, ys: [*c]const imgui.ImU8, err: [*c]const imgui.ImU8, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBarsH_S16PtrS16PtrS16PtrInt(label_id: [*c]const u8, xs: [*c]const imgui.ImS16, ys: [*c]const imgui.ImS16, err: [*c]const imgui.ImS16, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBarsH_U16PtrU16PtrU16PtrInt(label_id: [*c]const u8, xs: [*c]const imgui.ImU16, ys: [*c]const imgui.ImU16, err: [*c]const imgui.ImU16, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBarsH_S32PtrS32PtrS32PtrInt(label_id: [*c]const u8, xs: [*c]const imgui.ImS32, ys: [*c]const imgui.ImS32, err: [*c]const imgui.ImS32, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBarsH_U32PtrU32PtrU32PtrInt(label_id: [*c]const u8, xs: [*c]const imgui.ImU32, ys: [*c]const imgui.ImU32, err: [*c]const imgui.ImU32, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBarsH_S64PtrS64PtrS64PtrInt(label_id: [*c]const u8, xs: [*c]const imgui.ImS64, ys: [*c]const imgui.ImS64, err: [*c]const imgui.ImS64, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBarsH_U64PtrU64PtrU64PtrInt(label_id: [*c]const u8, xs: [*c]const imgui.ImU64, ys: [*c]const imgui.ImU64, err: [*c]const imgui.ImU64, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBarsH_FloatPtrFloatPtrFloatPtrFloatPtr(label_id: [*c]const u8, xs: [*c]const f32, ys: [*c]const f32, neg: [*c]const f32, pos: [*c]const f32, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBarsH_doublePtrdoublePtrdoublePtrdoublePtr(label_id: [*c]const u8, xs: [*c]const f64, ys: [*c]const f64, neg: [*c]const f64, pos: [*c]const f64, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBarsH_S8PtrS8PtrS8PtrS8Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS8, ys: [*c]const imgui.ImS8, neg: [*c]const imgui.ImS8, pos: [*c]const imgui.ImS8, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBarsH_U8PtrU8PtrU8PtrU8Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU8, ys: [*c]const imgui.ImU8, neg: [*c]const imgui.ImU8, pos: [*c]const imgui.ImU8, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBarsH_S16PtrS16PtrS16PtrS16Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS16, ys: [*c]const imgui.ImS16, neg: [*c]const imgui.ImS16, pos: [*c]const imgui.ImS16, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBarsH_U16PtrU16PtrU16PtrU16Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU16, ys: [*c]const imgui.ImU16, neg: [*c]const imgui.ImU16, pos: [*c]const imgui.ImU16, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBarsH_S32PtrS32PtrS32PtrS32Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS32, ys: [*c]const imgui.ImS32, neg: [*c]const imgui.ImS32, pos: [*c]const imgui.ImS32, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBarsH_U32PtrU32PtrU32PtrU32Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU32, ys: [*c]const imgui.ImU32, neg: [*c]const imgui.ImU32, pos: [*c]const imgui.ImU32, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBarsH_S64PtrS64PtrS64PtrS64Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS64, ys: [*c]const imgui.ImS64, neg: [*c]const imgui.ImS64, pos: [*c]const imgui.ImS64, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotErrorBarsH_U64PtrU64PtrU64PtrU64Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU64, ys: [*c]const imgui.ImU64, neg: [*c]const imgui.ImU64, pos: [*c]const imgui.ImU64, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStems_FloatPtrInt(label_id: [*c]const u8, values: [*c]const f32, count: c_int, y_ref: f64, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStems_doublePtrInt(label_id: [*c]const u8, values: [*c]const f64, count: c_int, y_ref: f64, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStems_S8PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImS8, count: c_int, y_ref: f64, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStems_U8PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImU8, count: c_int, y_ref: f64, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStems_S16PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImS16, count: c_int, y_ref: f64, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStems_U16PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImU16, count: c_int, y_ref: f64, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStems_S32PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImS32, count: c_int, y_ref: f64, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStems_U32PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImU32, count: c_int, y_ref: f64, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStems_S64PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImS64, count: c_int, y_ref: f64, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStems_U64PtrInt(label_id: [*c]const u8, values: [*c]const imgui.ImU64, count: c_int, y_ref: f64, xscale: f64, x0: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStems_FloatPtrFloatPtr(label_id: [*c]const u8, xs: [*c]const f32, ys: [*c]const f32, count: c_int, y_ref: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStems_doublePtrdoublePtr(label_id: [*c]const u8, xs: [*c]const f64, ys: [*c]const f64, count: c_int, y_ref: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStems_S8PtrS8Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS8, ys: [*c]const imgui.ImS8, count: c_int, y_ref: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStems_U8PtrU8Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU8, ys: [*c]const imgui.ImU8, count: c_int, y_ref: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStems_S16PtrS16Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS16, ys: [*c]const imgui.ImS16, count: c_int, y_ref: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStems_U16PtrU16Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU16, ys: [*c]const imgui.ImU16, count: c_int, y_ref: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStems_S32PtrS32Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS32, ys: [*c]const imgui.ImS32, count: c_int, y_ref: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStems_U32PtrU32Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU32, ys: [*c]const imgui.ImU32, count: c_int, y_ref: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStems_S64PtrS64Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS64, ys: [*c]const imgui.ImS64, count: c_int, y_ref: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotStems_U64PtrU64Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU64, ys: [*c]const imgui.ImU64, count: c_int, y_ref: f64, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotVLines_FloatPtr(label_id: [*c]const u8, xs: [*c]const f32, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotVLines_doublePtr(label_id: [*c]const u8, xs: [*c]const f64, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotVLines_S8Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS8, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotVLines_U8Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU8, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotVLines_S16Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS16, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotVLines_U16Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU16, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotVLines_S32Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS32, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotVLines_U32Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU32, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotVLines_S64Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS64, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotVLines_U64Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU64, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotHLines_FloatPtr(label_id: [*c]const u8, ys: [*c]const f32, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotHLines_doublePtr(label_id: [*c]const u8, ys: [*c]const f64, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotHLines_S8Ptr(label_id: [*c]const u8, ys: [*c]const imgui.ImS8, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotHLines_U8Ptr(label_id: [*c]const u8, ys: [*c]const imgui.ImU8, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotHLines_S16Ptr(label_id: [*c]const u8, ys: [*c]const imgui.ImS16, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotHLines_U16Ptr(label_id: [*c]const u8, ys: [*c]const imgui.ImU16, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotHLines_S32Ptr(label_id: [*c]const u8, ys: [*c]const imgui.ImS32, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotHLines_U32Ptr(label_id: [*c]const u8, ys: [*c]const imgui.ImU32, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotHLines_S64Ptr(label_id: [*c]const u8, ys: [*c]const imgui.ImS64, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotHLines_U64Ptr(label_id: [*c]const u8, ys: [*c]const imgui.ImU64, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotPieChart_FloatPtr(label_ids: [*c]const [*c]const u8, values: [*c]const f32, count: c_int, x: f64, y: f64, radius: f64, normalize: bool, label_fmt: [*c]const u8, angle0: f64) void;
pub extern fn ImPlot_PlotPieChart_doublePtr(label_ids: [*c]const [*c]const u8, values: [*c]const f64, count: c_int, x: f64, y: f64, radius: f64, normalize: bool, label_fmt: [*c]const u8, angle0: f64) void;
pub extern fn ImPlot_PlotPieChart_S8Ptr(label_ids: [*c]const [*c]const u8, values: [*c]const imgui.ImS8, count: c_int, x: f64, y: f64, radius: f64, normalize: bool, label_fmt: [*c]const u8, angle0: f64) void;
pub extern fn ImPlot_PlotPieChart_U8Ptr(label_ids: [*c]const [*c]const u8, values: [*c]const imgui.ImU8, count: c_int, x: f64, y: f64, radius: f64, normalize: bool, label_fmt: [*c]const u8, angle0: f64) void;
pub extern fn ImPlot_PlotPieChart_S16Ptr(label_ids: [*c]const [*c]const u8, values: [*c]const imgui.ImS16, count: c_int, x: f64, y: f64, radius: f64, normalize: bool, label_fmt: [*c]const u8, angle0: f64) void;
pub extern fn ImPlot_PlotPieChart_U16Ptr(label_ids: [*c]const [*c]const u8, values: [*c]const imgui.ImU16, count: c_int, x: f64, y: f64, radius: f64, normalize: bool, label_fmt: [*c]const u8, angle0: f64) void;
pub extern fn ImPlot_PlotPieChart_S32Ptr(label_ids: [*c]const [*c]const u8, values: [*c]const imgui.ImS32, count: c_int, x: f64, y: f64, radius: f64, normalize: bool, label_fmt: [*c]const u8, angle0: f64) void;
pub extern fn ImPlot_PlotPieChart_U32Ptr(label_ids: [*c]const [*c]const u8, values: [*c]const imgui.ImU32, count: c_int, x: f64, y: f64, radius: f64, normalize: bool, label_fmt: [*c]const u8, angle0: f64) void;
pub extern fn ImPlot_PlotPieChart_S64Ptr(label_ids: [*c]const [*c]const u8, values: [*c]const imgui.ImS64, count: c_int, x: f64, y: f64, radius: f64, normalize: bool, label_fmt: [*c]const u8, angle0: f64) void;
pub extern fn ImPlot_PlotPieChart_U64Ptr(label_ids: [*c]const [*c]const u8, values: [*c]const imgui.ImU64, count: c_int, x: f64, y: f64, radius: f64, normalize: bool, label_fmt: [*c]const u8, angle0: f64) void;
pub extern fn ImPlot_PlotHeatmap_FloatPtr(label_id: [*c]const u8, values: [*c]const f32, rows: c_int, cols: c_int, scale_min: f64, scale_max: f64, label_fmt: [*c]const u8, bounds_min: ImPlotPoint, bounds_max: ImPlotPoint) void;
pub extern fn ImPlot_PlotHeatmap_doublePtr(label_id: [*c]const u8, values: [*c]const f64, rows: c_int, cols: c_int, scale_min: f64, scale_max: f64, label_fmt: [*c]const u8, bounds_min: ImPlotPoint, bounds_max: ImPlotPoint) void;
pub extern fn ImPlot_PlotHeatmap_S8Ptr(label_id: [*c]const u8, values: [*c]const imgui.ImS8, rows: c_int, cols: c_int, scale_min: f64, scale_max: f64, label_fmt: [*c]const u8, bounds_min: ImPlotPoint, bounds_max: ImPlotPoint) void;
pub extern fn ImPlot_PlotHeatmap_U8Ptr(label_id: [*c]const u8, values: [*c]const imgui.ImU8, rows: c_int, cols: c_int, scale_min: f64, scale_max: f64, label_fmt: [*c]const u8, bounds_min: ImPlotPoint, bounds_max: ImPlotPoint) void;
pub extern fn ImPlot_PlotHeatmap_S16Ptr(label_id: [*c]const u8, values: [*c]const imgui.ImS16, rows: c_int, cols: c_int, scale_min: f64, scale_max: f64, label_fmt: [*c]const u8, bounds_min: ImPlotPoint, bounds_max: ImPlotPoint) void;
pub extern fn ImPlot_PlotHeatmap_U16Ptr(label_id: [*c]const u8, values: [*c]const imgui.ImU16, rows: c_int, cols: c_int, scale_min: f64, scale_max: f64, label_fmt: [*c]const u8, bounds_min: ImPlotPoint, bounds_max: ImPlotPoint) void;
pub extern fn ImPlot_PlotHeatmap_S32Ptr(label_id: [*c]const u8, values: [*c]const imgui.ImS32, rows: c_int, cols: c_int, scale_min: f64, scale_max: f64, label_fmt: [*c]const u8, bounds_min: ImPlotPoint, bounds_max: ImPlotPoint) void;
pub extern fn ImPlot_PlotHeatmap_U32Ptr(label_id: [*c]const u8, values: [*c]const imgui.ImU32, rows: c_int, cols: c_int, scale_min: f64, scale_max: f64, label_fmt: [*c]const u8, bounds_min: ImPlotPoint, bounds_max: ImPlotPoint) void;
pub extern fn ImPlot_PlotHeatmap_S64Ptr(label_id: [*c]const u8, values: [*c]const imgui.ImS64, rows: c_int, cols: c_int, scale_min: f64, scale_max: f64, label_fmt: [*c]const u8, bounds_min: ImPlotPoint, bounds_max: ImPlotPoint) void;
pub extern fn ImPlot_PlotHeatmap_U64Ptr(label_id: [*c]const u8, values: [*c]const imgui.ImU64, rows: c_int, cols: c_int, scale_min: f64, scale_max: f64, label_fmt: [*c]const u8, bounds_min: ImPlotPoint, bounds_max: ImPlotPoint) void;
pub extern fn ImPlot_PlotHistogram_FloatPtr(label_id: [*c]const u8, values: [*c]const f32, count: c_int, bins: c_int, cumulative: bool, density: bool, range: ImPlotRange, outliers: bool, bar_scale: f64) f64;
pub extern fn ImPlot_PlotHistogram_doublePtr(label_id: [*c]const u8, values: [*c]const f64, count: c_int, bins: c_int, cumulative: bool, density: bool, range: ImPlotRange, outliers: bool, bar_scale: f64) f64;
pub extern fn ImPlot_PlotHistogram_S8Ptr(label_id: [*c]const u8, values: [*c]const imgui.ImS8, count: c_int, bins: c_int, cumulative: bool, density: bool, range: ImPlotRange, outliers: bool, bar_scale: f64) f64;
pub extern fn ImPlot_PlotHistogram_U8Ptr(label_id: [*c]const u8, values: [*c]const imgui.ImU8, count: c_int, bins: c_int, cumulative: bool, density: bool, range: ImPlotRange, outliers: bool, bar_scale: f64) f64;
pub extern fn ImPlot_PlotHistogram_S16Ptr(label_id: [*c]const u8, values: [*c]const imgui.ImS16, count: c_int, bins: c_int, cumulative: bool, density: bool, range: ImPlotRange, outliers: bool, bar_scale: f64) f64;
pub extern fn ImPlot_PlotHistogram_U16Ptr(label_id: [*c]const u8, values: [*c]const imgui.ImU16, count: c_int, bins: c_int, cumulative: bool, density: bool, range: ImPlotRange, outliers: bool, bar_scale: f64) f64;
pub extern fn ImPlot_PlotHistogram_S32Ptr(label_id: [*c]const u8, values: [*c]const imgui.ImS32, count: c_int, bins: c_int, cumulative: bool, density: bool, range: ImPlotRange, outliers: bool, bar_scale: f64) f64;
pub extern fn ImPlot_PlotHistogram_U32Ptr(label_id: [*c]const u8, values: [*c]const imgui.ImU32, count: c_int, bins: c_int, cumulative: bool, density: bool, range: ImPlotRange, outliers: bool, bar_scale: f64) f64;
pub extern fn ImPlot_PlotHistogram_S64Ptr(label_id: [*c]const u8, values: [*c]const imgui.ImS64, count: c_int, bins: c_int, cumulative: bool, density: bool, range: ImPlotRange, outliers: bool, bar_scale: f64) f64;
pub extern fn ImPlot_PlotHistogram_U64Ptr(label_id: [*c]const u8, values: [*c]const imgui.ImU64, count: c_int, bins: c_int, cumulative: bool, density: bool, range: ImPlotRange, outliers: bool, bar_scale: f64) f64;
pub extern fn ImPlot_PlotHistogram2D_FloatPtr(label_id: [*c]const u8, xs: [*c]const f32, ys: [*c]const f32, count: c_int, x_bins: c_int, y_bins: c_int, density: bool, range: ImPlotLimits, outliers: bool) f64;
pub extern fn ImPlot_PlotHistogram2D_doublePtr(label_id: [*c]const u8, xs: [*c]const f64, ys: [*c]const f64, count: c_int, x_bins: c_int, y_bins: c_int, density: bool, range: ImPlotLimits, outliers: bool) f64;
pub extern fn ImPlot_PlotHistogram2D_S8Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS8, ys: [*c]const imgui.ImS8, count: c_int, x_bins: c_int, y_bins: c_int, density: bool, range: ImPlotLimits, outliers: bool) f64;
pub extern fn ImPlot_PlotHistogram2D_U8Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU8, ys: [*c]const imgui.ImU8, count: c_int, x_bins: c_int, y_bins: c_int, density: bool, range: ImPlotLimits, outliers: bool) f64;
pub extern fn ImPlot_PlotHistogram2D_S16Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS16, ys: [*c]const imgui.ImS16, count: c_int, x_bins: c_int, y_bins: c_int, density: bool, range: ImPlotLimits, outliers: bool) f64;
pub extern fn ImPlot_PlotHistogram2D_U16Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU16, ys: [*c]const imgui.ImU16, count: c_int, x_bins: c_int, y_bins: c_int, density: bool, range: ImPlotLimits, outliers: bool) f64;
pub extern fn ImPlot_PlotHistogram2D_S32Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS32, ys: [*c]const imgui.ImS32, count: c_int, x_bins: c_int, y_bins: c_int, density: bool, range: ImPlotLimits, outliers: bool) f64;
pub extern fn ImPlot_PlotHistogram2D_U32Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU32, ys: [*c]const imgui.ImU32, count: c_int, x_bins: c_int, y_bins: c_int, density: bool, range: ImPlotLimits, outliers: bool) f64;
pub extern fn ImPlot_PlotHistogram2D_S64Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS64, ys: [*c]const imgui.ImS64, count: c_int, x_bins: c_int, y_bins: c_int, density: bool, range: ImPlotLimits, outliers: bool) f64;
pub extern fn ImPlot_PlotHistogram2D_U64Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU64, ys: [*c]const imgui.ImU64, count: c_int, x_bins: c_int, y_bins: c_int, density: bool, range: ImPlotLimits, outliers: bool) f64;
pub extern fn ImPlot_PlotDigital_FloatPtr(label_id: [*c]const u8, xs: [*c]const f32, ys: [*c]const f32, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotDigital_doublePtr(label_id: [*c]const u8, xs: [*c]const f64, ys: [*c]const f64, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotDigital_S8Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS8, ys: [*c]const imgui.ImS8, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotDigital_U8Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU8, ys: [*c]const imgui.ImU8, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotDigital_S16Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS16, ys: [*c]const imgui.ImS16, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotDigital_U16Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU16, ys: [*c]const imgui.ImU16, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotDigital_S32Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS32, ys: [*c]const imgui.ImS32, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotDigital_U32Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU32, ys: [*c]const imgui.ImU32, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotDigital_S64Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImS64, ys: [*c]const imgui.ImS64, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotDigital_U64Ptr(label_id: [*c]const u8, xs: [*c]const imgui.ImU64, ys: [*c]const imgui.ImU64, count: c_int, offset: c_int, stride: c_int) void;
pub extern fn ImPlot_PlotImage(label_id: [*c]const u8, user_texture_id: imgui.ImTextureID, bounds_min: ImPlotPoint, bounds_max: ImPlotPoint, uv0: imgui.ImVec2, uv1: imgui.ImVec2, tint_col: imgui.ImVec4) void;
pub extern fn ImPlot_PlotText(text: [*c]const u8, x: f64, y: f64, vertical: bool, pix_offset: imgui.ImVec2) void;
pub extern fn ImPlot_PlotDummy(label_id: [*c]const u8) void;
pub extern fn ImPlot_SetNextPlotLimits(xmin: f64, xmax: f64, ymin: f64, ymax: f64, cond: imgui.ImGuiCond) void;
pub extern fn ImPlot_SetNextPlotLimitsX(xmin: f64, xmax: f64, cond: imgui.ImGuiCond) void;
pub extern fn ImPlot_SetNextPlotLimitsY(ymin: f64, ymax: f64, cond: imgui.ImGuiCond, y_axis: ImPlotYAxis) void;
pub extern fn ImPlot_LinkNextPlotLimits(xmin: [*c]f64, xmax: [*c]f64, ymin: [*c]f64, ymax: [*c]f64, ymin2: [*c]f64, ymax2: [*c]f64, ymin3: [*c]f64, ymax3: [*c]f64) void;
pub extern fn ImPlot_FitNextPlotAxes(x: bool, y: bool, y2: bool, y3: bool) void;
pub extern fn ImPlot_SetNextPlotTicksX_doublePtr(values: [*c]const f64, n_ticks: c_int, labels: [*c]const [*c]const u8, keep_default: bool) void;
pub extern fn ImPlot_SetNextPlotTicksX_double(x_min: f64, x_max: f64, n_ticks: c_int, labels: [*c]const [*c]const u8, keep_default: bool) void;
pub extern fn ImPlot_SetNextPlotTicksY_doublePtr(values: [*c]const f64, n_ticks: c_int, labels: [*c]const [*c]const u8, keep_default: bool, y_axis: ImPlotYAxis) void;
pub extern fn ImPlot_SetNextPlotTicksY_double(y_min: f64, y_max: f64, n_ticks: c_int, labels: [*c]const [*c]const u8, keep_default: bool, y_axis: ImPlotYAxis) void;
pub extern fn ImPlot_SetNextPlotFormatX(fmt: [*c]const u8) void;
pub extern fn ImPlot_SetNextPlotFormatY(fmt: [*c]const u8, y_axis: ImPlotYAxis) void;
pub extern fn ImPlot_SetPlotYAxis(y_axis: ImPlotYAxis) void;
pub extern fn ImPlot_HideNextItem(hidden: bool, cond: imgui.ImGuiCond) void;
pub extern fn ImPlot_PixelsToPlot_Vec2(pOut: [*c]ImPlotPoint, pix: imgui.ImVec2, y_axis: ImPlotYAxis) void;
pub extern fn ImPlot_PixelsToPlot_Float(pOut: [*c]ImPlotPoint, x: f32, y: f32, y_axis: ImPlotYAxis) void;
pub extern fn ImPlot_PlotToPixels_PlotPoInt(pOut: [*c]imgui.ImVec2, plt: ImPlotPoint, y_axis: ImPlotYAxis) void;
pub extern fn ImPlot_PlotToPixels_double(pOut: [*c]imgui.ImVec2, x: f64, y: f64, y_axis: ImPlotYAxis) void;
pub extern fn ImPlot_GetPlotPos(pOut: [*c]imgui.ImVec2) void;
pub extern fn ImPlot_GetPlotSize(pOut: [*c]imgui.ImVec2) void;
pub extern fn ImPlot_IsPlotHovered() bool;
pub extern fn ImPlot_IsPlotXAxisHovered() bool;
pub extern fn ImPlot_IsPlotYAxisHovered(y_axis: ImPlotYAxis) bool;
pub extern fn ImPlot_GetPlotMousePos(pOut: [*c]ImPlotPoint, y_axis: ImPlotYAxis) void;
pub extern fn ImPlot_GetPlotLimits(pOut: [*c]ImPlotLimits, y_axis: ImPlotYAxis) void;
pub extern fn ImPlot_IsPlotSelected() bool;
pub extern fn ImPlot_GetPlotSelection(pOut: [*c]ImPlotLimits, y_axis: ImPlotYAxis) void;
pub extern fn ImPlot_IsPlotQueried() bool;
pub extern fn ImPlot_GetPlotQuery(pOut: [*c]ImPlotLimits, y_axis: ImPlotYAxis) void;
pub extern fn ImPlot_SetPlotQuery(query: ImPlotLimits, y_axis: ImPlotYAxis) void;
pub extern fn ImPlot_IsSubplotsHovered() bool;
pub extern fn ImPlot_BeginAlignedPlots(group_id: [*c]const u8, orientation: ImPlotOrientation) bool;
pub extern fn ImPlot_EndAlignedPlots() void;
pub extern fn ImPlot_Annotate_Str(x: f64, y: f64, pix_offset: imgui.ImVec2, fmt: [*c]const u8, ...) void;
pub extern fn ImPlot_Annotate_Vec4(x: f64, y: f64, pix_offset: imgui.ImVec2, color: imgui.ImVec4, fmt: [*c]const u8, ...) void;
pub extern fn ImPlot_AnnotateClamped_Str(x: f64, y: f64, pix_offset: imgui.ImVec2, fmt: [*c]const u8, ...) void;
pub extern fn ImPlot_AnnotateClamped_Vec4(x: f64, y: f64, pix_offset: imgui.ImVec2, color: imgui.ImVec4, fmt: [*c]const u8, ...) void;
pub extern fn ImPlot_DragLineX(id: [*c]const u8, x_value: [*c]f64, show_label: bool, col: imgui.ImVec4, thickness: f32) bool;
pub extern fn ImPlot_DragLineY(id: [*c]const u8, y_value: [*c]f64, show_label: bool, col: imgui.ImVec4, thickness: f32) bool;
pub extern fn ImPlot_DragPoint(id: [*c]const u8, x: [*c]f64, y: [*c]f64, show_label: bool, col: imgui.ImVec4, radius: f32) bool;
pub extern fn ImPlot_SetLegendLocation(location: ImPlotLocation, orientation: ImPlotOrientation, outside: bool) void;
pub extern fn ImPlot_SetMousePosLocation(location: ImPlotLocation) void;
pub extern fn ImPlot_IsLegendEntryHovered(label_id: [*c]const u8) bool;
pub extern fn ImPlot_BeginLegendPopup(label_id: [*c]const u8, mouse_button: imgui.ImGuiMouseButton) bool;
pub extern fn ImPlot_EndLegendPopup() void;
pub extern fn ImPlot_BeginDragDropTarget() bool;
pub extern fn ImPlot_BeginDragDropTargetX() bool;
pub extern fn ImPlot_BeginDragDropTargetY(axis: ImPlotYAxis) bool;
pub extern fn ImPlot_BeginDragDropTargetLegend() bool;
pub extern fn ImPlot_EndDragDropTarget() void;
pub extern fn ImPlot_BeginDragDropSource(key_mods: imgui.ImGuiKeyModFlags, flags: imgui.ImGuiDragDropFlags) bool;
pub extern fn ImPlot_BeginDragDropSourceX(key_mods: imgui.ImGuiKeyModFlags, flags: imgui.ImGuiDragDropFlags) bool;
pub extern fn ImPlot_BeginDragDropSourceY(axis: ImPlotYAxis, key_mods: imgui.ImGuiKeyModFlags, flags: imgui.ImGuiDragDropFlags) bool;
pub extern fn ImPlot_BeginDragDropSourceItem(label_id: [*c]const u8, flags: imgui.ImGuiDragDropFlags) bool;
pub extern fn ImPlot_EndDragDropSource() void;
pub extern fn ImPlot_GetStyle() [*c]ImPlotStyle;
pub extern fn ImPlot_StyleColorsAuto(dst: [*c]ImPlotStyle) void;
pub extern fn ImPlot_StyleColorsClassic(dst: [*c]ImPlotStyle) void;
pub extern fn ImPlot_StyleColorsDark(dst: [*c]ImPlotStyle) void;
pub extern fn ImPlot_StyleColorsLight(dst: [*c]ImPlotStyle) void;
pub extern fn ImPlot_PushStyleColor_U32(idx: ImPlotCol, col: imgui.ImU32) void;
pub extern fn ImPlot_PushStyleColor_Vec4(idx: ImPlotCol, col: imgui.ImVec4) void;
pub extern fn ImPlot_PopStyleColor(count: c_int) void;
pub extern fn ImPlot_PushStyleVar_Float(idx: ImPlotStyleVar, val: f32) void;
pub extern fn ImPlot_PushStyleVar_Int(idx: ImPlotStyleVar, val: c_int) void;
pub extern fn ImPlot_PushStyleVar_Vec2(idx: ImPlotStyleVar, val: imgui.ImVec2) void;
pub extern fn ImPlot_PopStyleVar(count: c_int) void;
pub extern fn ImPlot_SetNextLineStyle(col: imgui.ImVec4, weight: f32) void;
pub extern fn ImPlot_SetNextFillStyle(col: imgui.ImVec4, alpha_mod: f32) void;
pub extern fn ImPlot_SetNextMarkerStyle(marker: ImPlotMarker, size: f32, fill: imgui.ImVec4, weight: f32, outline: imgui.ImVec4) void;
pub extern fn ImPlot_SetNextErrorBarStyle(col: imgui.ImVec4, size: f32, weight: f32) void;
pub extern fn ImPlot_GetLastItemColor(pOut: [*c]imgui.ImVec4) void;
pub extern fn ImPlot_GetStyleColorName(idx: ImPlotCol) [*c]const u8;
pub extern fn ImPlot_GetMarkerName(idx: ImPlotMarker) [*c]const u8;
pub extern fn ImPlot_AddColormap_Vec4Ptr(name: [*c]const u8, cols: [*c]const imgui.ImVec4, size: c_int, qual: bool) ImPlotColormap;
pub extern fn ImPlot_AddColormap_U32Ptr(name: [*c]const u8, cols: [*c]const imgui.ImU32, size: c_int, qual: bool) ImPlotColormap;
pub extern fn ImPlot_GetColormapCount() c_int;
pub extern fn ImPlot_GetColormapName(cmap: ImPlotColormap) [*c]const u8;
pub extern fn ImPlot_GetColormapIndex(name: [*c]const u8) ImPlotColormap;
pub extern fn ImPlot_PushColormap_PlotColormap(cmap: ImPlotColormap) void;
pub extern fn ImPlot_PushColormap_Str(name: [*c]const u8) void;
pub extern fn ImPlot_PopColormap(count: c_int) void;
pub extern fn ImPlot_NextColormapColor(pOut: [*c]imgui.ImVec4) void;
pub extern fn ImPlot_GetColormapSize(cmap: ImPlotColormap) c_int;
pub extern fn ImPlot_GetColormapColor(pOut: [*c]imgui.ImVec4, idx: c_int, cmap: ImPlotColormap) void;
pub extern fn ImPlot_SampleColormap(pOut: [*c]imgui.ImVec4, t: f32, cmap: ImPlotColormap) void;
pub extern fn ImPlot_ColormapScale(label: [*c]const u8, scale_min: f64, scale_max: f64, size: imgui.ImVec2, cmap: ImPlotColormap, fmt: [*c]const u8) void;
pub extern fn ImPlot_ColormapSlider(label: [*c]const u8, t: [*c]f32, out: [*c]imgui.ImVec4, format: [*c]const u8, cmap: ImPlotColormap) bool;
pub extern fn ImPlot_ColormapButton(label: [*c]const u8, size: imgui.ImVec2, cmap: ImPlotColormap) bool;
pub extern fn ImPlot_BustColorCache(plot_title_id: [*c]const u8) void;
pub extern fn ImPlot_ItemIcon_Vec4(col: imgui.ImVec4) void;
pub extern fn ImPlot_ItemIcon_U32(col: imgui.ImU32) void;
pub extern fn ImPlot_ColormapIcon(cmap: ImPlotColormap) void;
pub extern fn ImPlot_GetPlotDrawList() [*c]imgui.ImDrawList;
pub extern fn ImPlot_PushPlotClipRect(expand: f32) void;
pub extern fn ImPlot_PopPlotClipRect() void;
pub extern fn ImPlot_ShowStyleSelector(label: [*c]const u8) bool;
pub extern fn ImPlot_ShowColormapSelector(label: [*c]const u8) bool;
pub extern fn ImPlot_ShowStyleEditor(ref: [*c]ImPlotStyle) void;
pub extern fn ImPlot_ShowUserGuide() void;
pub extern fn ImPlot_ShowMetricsWindow(p_popen: [*c]bool) void;
pub extern fn ImPlot_ShowDemoWindow(p_open: [*c]bool) void;
pub extern fn ImPlot_ImLog10_Float(x: f32) f32;
pub extern fn ImPlot_ImLog10_double(x: f64) f64;
pub extern fn ImPlot_ImRemap_Float(x: f32, x0: f32, x1: f32, y0: f32, y1: f32) f32;
pub extern fn ImPlot_ImRemap_double(x: f64, x0: f64, x1: f64, y0: f64, y1: f64) f64;
pub extern fn ImPlot_ImRemap_S8(x: imgui.ImS8, x0: imgui.ImS8, x1: imgui.ImS8, y0: imgui.ImS8, y1: imgui.ImS8) imgui.ImS8;
pub extern fn ImPlot_ImRemap_U8(x: imgui.ImU8, x0: imgui.ImU8, x1: imgui.ImU8, y0: imgui.ImU8, y1: imgui.ImU8) imgui.ImU8;
pub extern fn ImPlot_ImRemap_S16(x: imgui.ImS16, x0: imgui.ImS16, x1: imgui.ImS16, y0: imgui.ImS16, y1: imgui.ImS16) imgui.ImS16;
pub extern fn ImPlot_ImRemap_U16(x: imgui.ImU16, x0: imgui.ImU16, x1: imgui.ImU16, y0: imgui.ImU16, y1: imgui.ImU16) imgui.ImU16;
pub extern fn ImPlot_ImRemap_S32(x: imgui.ImS32, x0: imgui.ImS32, x1: imgui.ImS32, y0: imgui.ImS32, y1: imgui.ImS32) imgui.ImS32;
pub extern fn ImPlot_ImRemap_U32(x: imgui.ImU32, x0: imgui.ImU32, x1: imgui.ImU32, y0: imgui.ImU32, y1: imgui.ImU32) imgui.ImU32;
pub extern fn ImPlot_ImRemap_S64(x: imgui.ImS64, x0: imgui.ImS64, x1: imgui.ImS64, y0: imgui.ImS64, y1: imgui.ImS64) imgui.ImS64;
pub extern fn ImPlot_ImRemap_U64(x: imgui.ImU64, x0: imgui.ImU64, x1: imgui.ImU64, y0: imgui.ImU64, y1: imgui.ImU64) imgui.ImU64;
pub extern fn ImPlot_ImRemap01_Float(x: f32, x0: f32, x1: f32) f32;
pub extern fn ImPlot_ImRemap01_double(x: f64, x0: f64, x1: f64) f64;
pub extern fn ImPlot_ImRemap01_S8(x: imgui.ImS8, x0: imgui.ImS8, x1: imgui.ImS8) imgui.ImS8;
pub extern fn ImPlot_ImRemap01_U8(x: imgui.ImU8, x0: imgui.ImU8, x1: imgui.ImU8) imgui.ImU8;
pub extern fn ImPlot_ImRemap01_S16(x: imgui.ImS16, x0: imgui.ImS16, x1: imgui.ImS16) imgui.ImS16;
pub extern fn ImPlot_ImRemap01_U16(x: imgui.ImU16, x0: imgui.ImU16, x1: imgui.ImU16) imgui.ImU16;
pub extern fn ImPlot_ImRemap01_S32(x: imgui.ImS32, x0: imgui.ImS32, x1: imgui.ImS32) imgui.ImS32;
pub extern fn ImPlot_ImRemap01_U32(x: imgui.ImU32, x0: imgui.ImU32, x1: imgui.ImU32) imgui.ImU32;
pub extern fn ImPlot_ImRemap01_S64(x: imgui.ImS64, x0: imgui.ImS64, x1: imgui.ImS64) imgui.ImS64;
pub extern fn ImPlot_ImRemap01_U64(x: imgui.ImU64, x0: imgui.ImU64, x1: imgui.ImU64) imgui.ImU64;
pub extern fn ImPlot_ImPosMod(l: c_int, r: c_int) c_int;
pub extern fn ImPlot_ImNanOrInf(val: f64) bool;
pub extern fn ImPlot_ImConstrainNan(val: f64) f64;
pub extern fn ImPlot_ImConstrainInf(val: f64) f64;
pub extern fn ImPlot_ImConstrainLog(val: f64) f64;
pub extern fn ImPlot_ImConstrainTime(val: f64) f64;
pub extern fn ImPlot_ImAlmostEqual(v1: f64, v2: f64, ulp: c_int) bool;
pub extern fn ImPlot_ImMinArray_FloatPtr(values: [*c]const f32, count: c_int) f32;
pub extern fn ImPlot_ImMinArray_doublePtr(values: [*c]const f64, count: c_int) f64;
pub extern fn ImPlot_ImMinArray_S8Ptr(values: [*c]const imgui.ImS8, count: c_int) imgui.ImS8;
pub extern fn ImPlot_ImMinArray_U8Ptr(values: [*c]const imgui.ImU8, count: c_int) imgui.ImU8;
pub extern fn ImPlot_ImMinArray_S16Ptr(values: [*c]const imgui.ImS16, count: c_int) imgui.ImS16;
pub extern fn ImPlot_ImMinArray_U16Ptr(values: [*c]const imgui.ImU16, count: c_int) imgui.ImU16;
pub extern fn ImPlot_ImMinArray_S32Ptr(values: [*c]const imgui.ImS32, count: c_int) imgui.ImS32;
pub extern fn ImPlot_ImMinArray_U32Ptr(values: [*c]const imgui.ImU32, count: c_int) imgui.ImU32;
pub extern fn ImPlot_ImMinArray_S64Ptr(values: [*c]const imgui.ImS64, count: c_int) imgui.ImS64;
pub extern fn ImPlot_ImMinArray_U64Ptr(values: [*c]const imgui.ImU64, count: c_int) imgui.ImU64;
pub extern fn ImPlot_ImMaxArray_FloatPtr(values: [*c]const f32, count: c_int) f32;
pub extern fn ImPlot_ImMaxArray_doublePtr(values: [*c]const f64, count: c_int) f64;
pub extern fn ImPlot_ImMaxArray_S8Ptr(values: [*c]const imgui.ImS8, count: c_int) imgui.ImS8;
pub extern fn ImPlot_ImMaxArray_U8Ptr(values: [*c]const imgui.ImU8, count: c_int) imgui.ImU8;
pub extern fn ImPlot_ImMaxArray_S16Ptr(values: [*c]const imgui.ImS16, count: c_int) imgui.ImS16;
pub extern fn ImPlot_ImMaxArray_U16Ptr(values: [*c]const imgui.ImU16, count: c_int) imgui.ImU16;
pub extern fn ImPlot_ImMaxArray_S32Ptr(values: [*c]const imgui.ImS32, count: c_int) imgui.ImS32;
pub extern fn ImPlot_ImMaxArray_U32Ptr(values: [*c]const imgui.ImU32, count: c_int) imgui.ImU32;
pub extern fn ImPlot_ImMaxArray_S64Ptr(values: [*c]const imgui.ImS64, count: c_int) imgui.ImS64;
pub extern fn ImPlot_ImMaxArray_U64Ptr(values: [*c]const imgui.ImU64, count: c_int) imgui.ImU64;
pub extern fn ImPlot_ImMinMaxArray_FloatPtr(values: [*c]const f32, count: c_int, min_out: [*c]f32, max_out: [*c]f32) void;
pub extern fn ImPlot_ImMinMaxArray_doublePtr(values: [*c]const f64, count: c_int, min_out: [*c]f64, max_out: [*c]f64) void;
pub extern fn ImPlot_ImMinMaxArray_S8Ptr(values: [*c]const imgui.ImS8, count: c_int, min_out: [*c]imgui.ImS8, max_out: [*c]imgui.ImS8) void;
pub extern fn ImPlot_ImMinMaxArray_U8Ptr(values: [*c]const imgui.ImU8, count: c_int, min_out: [*c]imgui.ImU8, max_out: [*c]imgui.ImU8) void;
pub extern fn ImPlot_ImMinMaxArray_S16Ptr(values: [*c]const imgui.ImS16, count: c_int, min_out: [*c]imgui.ImS16, max_out: [*c]imgui.ImS16) void;
pub extern fn ImPlot_ImMinMaxArray_U16Ptr(values: [*c]const imgui.ImU16, count: c_int, min_out: [*c]imgui.ImU16, max_out: [*c]imgui.ImU16) void;
pub extern fn ImPlot_ImMinMaxArray_S32Ptr(values: [*c]const imgui.ImS32, count: c_int, min_out: [*c]imgui.ImS32, max_out: [*c]imgui.ImS32) void;
pub extern fn ImPlot_ImMinMaxArray_U32Ptr(values: [*c]const imgui.ImU32, count: c_int, min_out: [*c]imgui.ImU32, max_out: [*c]imgui.ImU32) void;
pub extern fn ImPlot_ImMinMaxArray_S64Ptr(values: [*c]const imgui.ImS64, count: c_int, min_out: [*c]imgui.ImS64, max_out: [*c]imgui.ImS64) void;
pub extern fn ImPlot_ImMinMaxArray_U64Ptr(values: [*c]const imgui.ImU64, count: c_int, min_out: [*c]imgui.ImU64, max_out: [*c]imgui.ImU64) void;
pub extern fn ImPlot_ImSum_FloatPtr(values: [*c]const f32, count: c_int) f32;
pub extern fn ImPlot_ImSum_doublePtr(values: [*c]const f64, count: c_int) f64;
pub extern fn ImPlot_ImSum_S8Ptr(values: [*c]const imgui.ImS8, count: c_int) imgui.ImS8;
pub extern fn ImPlot_ImSum_U8Ptr(values: [*c]const imgui.ImU8, count: c_int) imgui.ImU8;
pub extern fn ImPlot_ImSum_S16Ptr(values: [*c]const imgui.ImS16, count: c_int) imgui.ImS16;
pub extern fn ImPlot_ImSum_U16Ptr(values: [*c]const imgui.ImU16, count: c_int) imgui.ImU16;
pub extern fn ImPlot_ImSum_S32Ptr(values: [*c]const imgui.ImS32, count: c_int) imgui.ImS32;
pub extern fn ImPlot_ImSum_U32Ptr(values: [*c]const imgui.ImU32, count: c_int) imgui.ImU32;
pub extern fn ImPlot_ImSum_S64Ptr(values: [*c]const imgui.ImS64, count: c_int) imgui.ImS64;
pub extern fn ImPlot_ImSum_U64Ptr(values: [*c]const imgui.ImU64, count: c_int) imgui.ImU64;
pub extern fn ImPlot_ImMean_FloatPtr(values: [*c]const f32, count: c_int) f64;
pub extern fn ImPlot_ImMean_doublePtr(values: [*c]const f64, count: c_int) f64;
pub extern fn ImPlot_ImMean_S8Ptr(values: [*c]const imgui.ImS8, count: c_int) f64;
pub extern fn ImPlot_ImMean_U8Ptr(values: [*c]const imgui.ImU8, count: c_int) f64;
pub extern fn ImPlot_ImMean_S16Ptr(values: [*c]const imgui.ImS16, count: c_int) f64;
pub extern fn ImPlot_ImMean_U16Ptr(values: [*c]const imgui.ImU16, count: c_int) f64;
pub extern fn ImPlot_ImMean_S32Ptr(values: [*c]const imgui.ImS32, count: c_int) f64;
pub extern fn ImPlot_ImMean_U32Ptr(values: [*c]const imgui.ImU32, count: c_int) f64;
pub extern fn ImPlot_ImMean_S64Ptr(values: [*c]const imgui.ImS64, count: c_int) f64;
pub extern fn ImPlot_ImMean_U64Ptr(values: [*c]const imgui.ImU64, count: c_int) f64;
pub extern fn ImPlot_ImStdDev_FloatPtr(values: [*c]const f32, count: c_int) f64;
pub extern fn ImPlot_ImStdDev_doublePtr(values: [*c]const f64, count: c_int) f64;
pub extern fn ImPlot_ImStdDev_S8Ptr(values: [*c]const imgui.ImS8, count: c_int) f64;
pub extern fn ImPlot_ImStdDev_U8Ptr(values: [*c]const imgui.ImU8, count: c_int) f64;
pub extern fn ImPlot_ImStdDev_S16Ptr(values: [*c]const imgui.ImS16, count: c_int) f64;
pub extern fn ImPlot_ImStdDev_U16Ptr(values: [*c]const imgui.ImU16, count: c_int) f64;
pub extern fn ImPlot_ImStdDev_S32Ptr(values: [*c]const imgui.ImS32, count: c_int) f64;
pub extern fn ImPlot_ImStdDev_U32Ptr(values: [*c]const imgui.ImU32, count: c_int) f64;
pub extern fn ImPlot_ImStdDev_S64Ptr(values: [*c]const imgui.ImS64, count: c_int) f64;
pub extern fn ImPlot_ImStdDev_U64Ptr(values: [*c]const imgui.ImU64, count: c_int) f64;
pub extern fn ImPlot_ImMixU32(a: imgui.ImU32, b: imgui.ImU32, s: imgui.ImU32) imgui.ImU32;
pub extern fn ImPlot_ImLerpU32(colors: [*c]const imgui.ImU32, size: c_int, t: f32) imgui.ImU32;
pub extern fn ImPlot_ImAlphaU32(col: imgui.ImU32, alpha: f32) imgui.ImU32;
pub extern fn ImBufferWriter_ImBufferWriter(buffer: [*c]u8, size: c_int) [*c]ImBufferWriter;
pub extern fn ImBufferWriter_destroy(self: [*c]ImBufferWriter) void;
pub extern fn ImBufferWriter_Write(self: [*c]ImBufferWriter, fmt: [*c]const u8, ...) void;
pub extern fn ImPlotInputMap_ImPlotInputMap() [*c]ImPlotInputMap;
pub extern fn ImPlotInputMap_destroy(self: [*c]ImPlotInputMap) void;
pub extern fn ImPlotDateTimeFmt_ImPlotDateTimeFmt(date_fmt: ImPlotDateFmt, time_fmt: ImPlotTimeFmt, use_24_hr_clk: bool, use_iso_8601: bool) [*c]ImPlotDateTimeFmt;
pub extern fn ImPlotDateTimeFmt_destroy(self: [*c]ImPlotDateTimeFmt) void;
pub extern fn ImPlotTime_ImPlotTime_Nil() [*c]ImPlotTime;
pub extern fn ImPlotTime_destroy(self: [*c]ImPlotTime) void;
pub extern fn ImPlotTime_ImPlotTime_time_t(s: time_t, us: c_int) [*c]ImPlotTime;
pub extern fn ImPlotTime_RollOver(self: [*c]ImPlotTime) void;
pub extern fn ImPlotTime_ToDouble(self: [*c]ImPlotTime) f64;
pub extern fn ImPlotTime_FromDouble(pOut: [*c]ImPlotTime, t: f64) void;
pub extern fn ImPlotColormapData_ImPlotColormapData() [*c]ImPlotColormapData;
pub extern fn ImPlotColormapData_destroy(self: [*c]ImPlotColormapData) void;
pub extern fn ImPlotColormapData_Append(self: [*c]ImPlotColormapData, name: [*c]const u8, keys: [*c]const imgui.ImU32, count: c_int, qual: bool) c_int;
pub extern fn ImPlotColormapData__AppendTable(self: [*c]ImPlotColormapData, cmap: ImPlotColormap) void;
pub extern fn ImPlotColormapData_RebuildTables(self: [*c]ImPlotColormapData) void;
pub extern fn ImPlotColormapData_IsQual(self: [*c]ImPlotColormapData, cmap: ImPlotColormap) bool;
pub extern fn ImPlotColormapData_GetName(self: [*c]ImPlotColormapData, cmap: ImPlotColormap) [*c]const u8;
pub extern fn ImPlotColormapData_GetIndex(self: [*c]ImPlotColormapData, name: [*c]const u8) ImPlotColormap;
pub extern fn ImPlotColormapData_GetKeys(self: [*c]ImPlotColormapData, cmap: ImPlotColormap) [*c]const imgui.ImU32;
pub extern fn ImPlotColormapData_GetKeyCount(self: [*c]ImPlotColormapData, cmap: ImPlotColormap) c_int;
pub extern fn ImPlotColormapData_GetKeyColor(self: [*c]ImPlotColormapData, cmap: ImPlotColormap, idx: c_int) imgui.ImU32;
pub extern fn ImPlotColormapData_SetKeyColor(self: [*c]ImPlotColormapData, cmap: ImPlotColormap, idx: c_int, value: imgui.ImU32) void;
pub extern fn ImPlotColormapData_GetTable(self: [*c]ImPlotColormapData, cmap: ImPlotColormap) [*c]const imgui.ImU32;
pub extern fn ImPlotColormapData_GetTableSize(self: [*c]ImPlotColormapData, cmap: ImPlotColormap) c_int;
pub extern fn ImPlotColormapData_GetTableColor(self: [*c]ImPlotColormapData, cmap: ImPlotColormap, idx: c_int) imgui.ImU32;
pub extern fn ImPlotColormapData_LerpTable(self: [*c]ImPlotColormapData, cmap: ImPlotColormap, t: f32) imgui.ImU32;
pub extern fn ImPlotPointError_ImPlotPointError(x: f64, y: f64, neg: f64, pos: f64) [*c]ImPlotPointError;
pub extern fn ImPlotPointError_destroy(self: [*c]ImPlotPointError) void;
pub extern fn ImPlotAnnotationCollection_ImPlotAnnotationCollection() [*c]ImPlotAnnotationCollection;
pub extern fn ImPlotAnnotationCollection_destroy(self: [*c]ImPlotAnnotationCollection) void;
pub extern fn ImPlotAnnotationCollection_Append(self: [*c]ImPlotAnnotationCollection, pos: imgui.ImVec2, off: imgui.ImVec2, bg: imgui.ImU32, fg: imgui.ImU32, clamp: bool, fmt: [*c]const u8, ...) void;
pub extern fn ImPlotAnnotationCollection_GetText(self: [*c]ImPlotAnnotationCollection, idx: c_int) [*c]const u8;
pub extern fn ImPlotAnnotationCollection_Reset(self: [*c]ImPlotAnnotationCollection) void;
pub extern fn ImPlotTick_ImPlotTick(value: f64, major: bool, show_label: bool) [*c]ImPlotTick;
pub extern fn ImPlotTick_destroy(self: [*c]ImPlotTick) void;
pub extern fn ImPlotTickCollection_ImPlotTickCollection() [*c]ImPlotTickCollection;
pub extern fn ImPlotTickCollection_destroy(self: [*c]ImPlotTickCollection) void;
pub extern fn ImPlotTickCollection_Append_PlotTick(self: [*c]ImPlotTickCollection, tick: ImPlotTick) [*c]const ImPlotTick;
pub extern fn ImPlotTickCollection_Append_double(self: [*c]ImPlotTickCollection, value: f64, major: bool, show_label: bool, fmt: [*c]const u8) [*c]const ImPlotTick;
pub extern fn ImPlotTickCollection_GetText(self: [*c]ImPlotTickCollection, idx: c_int) [*c]const u8;
pub extern fn ImPlotTickCollection_Reset(self: [*c]ImPlotTickCollection) void;
pub extern fn ImPlotAxis_ImPlotAxis() [*c]ImPlotAxis;
pub extern fn ImPlotAxis_destroy(self: [*c]ImPlotAxis) void;
pub extern fn ImPlotAxis_SetMin(self: [*c]ImPlotAxis, _min: f64, force: bool) bool;
pub extern fn ImPlotAxis_SetMax(self: [*c]ImPlotAxis, _max: f64, force: bool) bool;
pub extern fn ImPlotAxis_SetRange_double(self: [*c]ImPlotAxis, _min: f64, _max: f64) void;
pub extern fn ImPlotAxis_SetRange_PlotRange(self: [*c]ImPlotAxis, range: ImPlotRange) void;
pub extern fn ImPlotAxis_SetAspect(self: [*c]ImPlotAxis, unit_per_pix: f64) void;
pub extern fn ImPlotAxis_GetAspect(self: [*c]ImPlotAxis) f64;
pub extern fn ImPlotAxis_Constrain(self: [*c]ImPlotAxis) void;
pub extern fn ImPlotAxis_IsLabeled(self: [*c]ImPlotAxis) bool;
pub extern fn ImPlotAxis_IsInverted(self: [*c]ImPlotAxis) bool;
pub extern fn ImPlotAxis_IsAutoFitting(self: [*c]ImPlotAxis) bool;
pub extern fn ImPlotAxis_IsRangeLocked(self: [*c]ImPlotAxis) bool;
pub extern fn ImPlotAxis_IsLockedMin(self: [*c]ImPlotAxis) bool;
pub extern fn ImPlotAxis_IsLockedMax(self: [*c]ImPlotAxis) bool;
pub extern fn ImPlotAxis_IsLocked(self: [*c]ImPlotAxis) bool;
pub extern fn ImPlotAxis_IsInputLockedMin(self: [*c]ImPlotAxis) bool;
pub extern fn ImPlotAxis_IsInputLockedMax(self: [*c]ImPlotAxis) bool;
pub extern fn ImPlotAxis_IsInputLocked(self: [*c]ImPlotAxis) bool;
pub extern fn ImPlotAxis_IsTime(self: [*c]ImPlotAxis) bool;
pub extern fn ImPlotAxis_IsLog(self: [*c]ImPlotAxis) bool;
pub extern fn ImPlotAlignmentData_ImPlotAlignmentData() [*c]ImPlotAlignmentData;
pub extern fn ImPlotAlignmentData_destroy(self: [*c]ImPlotAlignmentData) void;
pub extern fn ImPlotAlignmentData_Begin(self: [*c]ImPlotAlignmentData) void;
pub extern fn ImPlotAlignmentData_Update(self: [*c]ImPlotAlignmentData, pad_a: [*c]f32, pad_b: [*c]f32) void;
pub extern fn ImPlotAlignmentData_End(self: [*c]ImPlotAlignmentData) void;
pub extern fn ImPlotAlignmentData_Reset(self: [*c]ImPlotAlignmentData) void;
pub extern fn ImPlotItem_ImPlotItem() [*c]ImPlotItem;
pub extern fn ImPlotItem_destroy(self: [*c]ImPlotItem) void;
pub extern fn ImPlotLegendData_ImPlotLegendData() [*c]ImPlotLegendData;
pub extern fn ImPlotLegendData_destroy(self: [*c]ImPlotLegendData) void;
pub extern fn ImPlotLegendData_Reset(self: [*c]ImPlotLegendData) void;
pub extern fn ImPlotItemGroup_ImPlotItemGroup() [*c]ImPlotItemGroup;
pub extern fn ImPlotItemGroup_destroy(self: [*c]ImPlotItemGroup) void;
pub extern fn ImPlotItemGroup_GetItemCount(self: [*c]ImPlotItemGroup) c_int;
pub extern fn ImPlotItemGroup_GetItemID(self: [*c]ImPlotItemGroup, label_id: [*c]const u8) imgui.ImGuiID;
pub extern fn ImPlotItemGroup_GetItem_ID(self: [*c]ImPlotItemGroup, id: imgui.ImGuiID) [*c]ImPlotItem;
pub extern fn ImPlotItemGroup_GetItem_Str(self: [*c]ImPlotItemGroup, label_id: [*c]const u8) [*c]ImPlotItem;
pub extern fn ImPlotItemGroup_GetOrAddItem(self: [*c]ImPlotItemGroup, id: imgui.ImGuiID) [*c]ImPlotItem;
pub extern fn ImPlotItemGroup_GetItemByIndex(self: [*c]ImPlotItemGroup, i: c_int) [*c]ImPlotItem;
pub extern fn ImPlotItemGroup_GetItemIndex(self: [*c]ImPlotItemGroup, item: [*c]ImPlotItem) c_int;
pub extern fn ImPlotItemGroup_GetLegendCount(self: [*c]ImPlotItemGroup) c_int;
pub extern fn ImPlotItemGroup_GetLegendItem(self: [*c]ImPlotItemGroup, i: c_int) [*c]ImPlotItem;
pub extern fn ImPlotItemGroup_GetLegendLabel(self: [*c]ImPlotItemGroup, i: c_int) [*c]const u8;
pub extern fn ImPlotItemGroup_Reset(self: [*c]ImPlotItemGroup) void;
pub extern fn ImPlotPlot_ImPlotPlot() [*c]ImPlotPlot;
pub extern fn ImPlotPlot_destroy(self: [*c]ImPlotPlot) void;
pub extern fn ImPlotPlot_AnyYInputLocked(self: [*c]ImPlotPlot) bool;
pub extern fn ImPlotPlot_AllYInputLocked(self: [*c]ImPlotPlot) bool;
pub extern fn ImPlotPlot_IsInputLocked(self: [*c]ImPlotPlot) bool;
pub extern fn ImPlotSubplot_ImPlotSubplot() [*c]ImPlotSubplot;
pub extern fn ImPlotSubplot_destroy(self: [*c]ImPlotSubplot) void;
pub extern fn ImPlotNextPlotData_ImPlotNextPlotData() [*c]ImPlotNextPlotData;
pub extern fn ImPlotNextPlotData_destroy(self: [*c]ImPlotNextPlotData) void;
pub extern fn ImPlotNextPlotData_Reset(self: [*c]ImPlotNextPlotData) void;
pub extern fn ImPlotNextItemData_ImPlotNextItemData() [*c]ImPlotNextItemData;
pub extern fn ImPlotNextItemData_destroy(self: [*c]ImPlotNextItemData) void;
pub extern fn ImPlotNextItemData_Reset(self: [*c]ImPlotNextItemData) void;
pub extern fn ImPlot_Initialize(ctx: [*c]ImPlotContext) void;
pub extern fn ImPlot_ResetCtxForNextPlot(ctx: [*c]ImPlotContext) void;
pub extern fn ImPlot_ResetCtxForNextAlignedPlots(ctx: [*c]ImPlotContext) void;
pub extern fn ImPlot_ResetCtxForNextSubplot(ctx: [*c]ImPlotContext) void;
pub extern fn ImPlot_GetInputMap() [*c]ImPlotInputMap;
pub extern fn ImPlot_GetPlot(title: [*c]const u8) [*c]ImPlotPlot;
pub extern fn ImPlot_GetCurrentPlot() [*c]ImPlotPlot;
pub extern fn ImPlot_BustPlotCache() void;
pub extern fn ImPlot_ShowPlotContextMenu(plot: [*c]ImPlotPlot) void;
pub extern fn ImPlot_SubplotNextCell() void;
pub extern fn ImPlot_ShowSubplotsContextMenu(subplot: [*c]ImPlotSubplot) void;
pub extern fn ImPlot_BeginItem(label_id: [*c]const u8, recolor_from: ImPlotCol) bool;
pub extern fn ImPlot_EndItem() void;
pub extern fn ImPlot_RegisterOrGetItem(label_id: [*c]const u8, just_created: [*c]bool) [*c]ImPlotItem;
pub extern fn ImPlot_GetItem(label_id: [*c]const u8) [*c]ImPlotItem;
pub extern fn ImPlot_GetCurrentItem() [*c]ImPlotItem;
pub extern fn ImPlot_BustItemCache() void;
pub extern fn ImPlot_GetCurrentYAxis() c_int;
pub extern fn ImPlot_UpdateAxisColors(axis_flag: c_int, axis: [*c]ImPlotAxis) void;
pub extern fn ImPlot_UpdateTransformCache() void;
pub extern fn ImPlot_GetCurrentScale() ImPlotScale;
pub extern fn ImPlot_FitThisFrame() bool;
pub extern fn ImPlot_FitPointAxis(axis: [*c]ImPlotAxis, ext: [*c]ImPlotRange, v: f64) void;
pub extern fn ImPlot_FitPointMultiAxis(axis: [*c]ImPlotAxis, alt: [*c]ImPlotAxis, ext: [*c]ImPlotRange, v: f64, v_alt: f64) void;
pub extern fn ImPlot_FitPointX(x: f64) void;
pub extern fn ImPlot_FitPointY(y: f64) void;
pub extern fn ImPlot_FitPoint(p: ImPlotPoint) void;
pub extern fn ImPlot_RangesOverlap(r1: ImPlotRange, r2: ImPlotRange) bool;
pub extern fn ImPlot_PushLinkedAxis(axis: [*c]ImPlotAxis) void;
pub extern fn ImPlot_PullLinkedAxis(axis: [*c]ImPlotAxis) void;
pub extern fn ImPlot_ShowAxisContextMenu(axis: [*c]ImPlotAxis, equal_axis: [*c]ImPlotAxis, time_allowed: bool) void;
pub extern fn ImPlot_GetFormatX() [*c]const u8;
pub extern fn ImPlot_GetFormatY(y: ImPlotYAxis) [*c]const u8;
pub extern fn ImPlot_GetLocationPos(pOut: [*c]imgui.ImVec2, outer_rect: imgui.ImRect, inner_size: imgui.ImVec2, location: ImPlotLocation, pad: imgui.ImVec2) void;
pub extern fn ImPlot_CalcLegendSize(pOut: [*c]imgui.ImVec2, items: [*c]ImPlotItemGroup, pad: imgui.ImVec2, spacing: imgui.ImVec2, orientation: ImPlotOrientation) void;
pub extern fn ImPlot_ShowLegendEntries(items: [*c]ImPlotItemGroup, legend_bb: imgui.ImRect, interactable: bool, pad: imgui.ImVec2, spacing: imgui.ImVec2, orientation: ImPlotOrientation, DrawList: [*c]imgui.ImDrawList) bool;
pub extern fn ImPlot_ShowAltLegend(title_id: [*c]const u8, orientation: ImPlotOrientation, size: imgui.ImVec2, interactable: bool) void;
pub extern fn ImPlot_ShowLegendContextMenu(legend: [*c]ImPlotLegendData, visible: bool) bool;
pub extern fn ImPlot_LabelTickTime(tick: [*c]ImPlotTick, buffer: [*c]imgui.ImGuiTextBuffer, t: ImPlotTime, fmt: ImPlotDateTimeFmt) void;
pub extern fn ImPlot_AddTicksDefault(range: ImPlotRange, pix: f32, orn: ImPlotOrientation, ticks: [*c]ImPlotTickCollection, fmt: [*c]const u8) void;
pub extern fn ImPlot_AddTicksLogarithmic(range: ImPlotRange, pix: f32, orn: ImPlotOrientation, ticks: [*c]ImPlotTickCollection, fmt: [*c]const u8) void;
pub extern fn ImPlot_AddTicksTime(range: ImPlotRange, plot_width: f32, ticks: [*c]ImPlotTickCollection) void;
pub extern fn ImPlot_AddTicksCustom(values: [*c]const f64, labels: [*c]const [*c]const u8, n: c_int, ticks: [*c]ImPlotTickCollection, fmt: [*c]const u8) void;
pub extern fn ImPlot_LabelAxisValue(axis: ImPlotAxis, ticks: ImPlotTickCollection, value: f64, buff: [*c]u8, size: c_int) c_int;
pub extern fn ImPlot_GetItemData() [*c]const ImPlotNextItemData;
pub extern fn ImPlot_IsColorAuto_Vec4(col: imgui.ImVec4) bool;
pub extern fn ImPlot_IsColorAuto_PlotCol(idx: ImPlotCol) bool;
pub extern fn ImPlot_GetAutoColor(pOut: [*c]imgui.ImVec4, idx: ImPlotCol) void;
pub extern fn ImPlot_GetStyleColorVec4(pOut: [*c]imgui.ImVec4, idx: ImPlotCol) void;
pub extern fn ImPlot_GetStyleColorU32(idx: ImPlotCol) imgui.ImU32;
pub extern fn ImPlot_AddTextVertical(DrawList: [*c]imgui.ImDrawList, pos: imgui.ImVec2, col: imgui.ImU32, text_begin: [*c]const u8, text_end: [*c]const u8) void;
pub extern fn ImPlot_AddTextCentered(DrawList: [*c]imgui.ImDrawList, top_center: imgui.ImVec2, col: imgui.ImU32, text_begin: [*c]const u8, text_end: [*c]const u8) void;
pub extern fn ImPlot_CalcTextSizeVertical(pOut: [*c]imgui.ImVec2, text: [*c]const u8) void;
pub extern fn ImPlot_CalcTextColor_Vec4(bg: imgui.ImVec4) imgui.ImU32;
pub extern fn ImPlot_CalcTextColor_U32(bg: imgui.ImU32) imgui.ImU32;
pub extern fn ImPlot_CalcHoverColor(col: imgui.ImU32) imgui.ImU32;
pub extern fn ImPlot_ClampLabelPos(pOut: [*c]imgui.ImVec2, pos: imgui.ImVec2, size: imgui.ImVec2, Min: imgui.ImVec2, Max: imgui.ImVec2) void;
pub extern fn ImPlot_GetColormapColorU32(idx: c_int, cmap: ImPlotColormap) imgui.ImU32;
pub extern fn ImPlot_NextColormapColorU32() imgui.ImU32;
pub extern fn ImPlot_SampleColormapU32(t: f32, cmap: ImPlotColormap) imgui.ImU32;
pub extern fn ImPlot_RenderColorBar(colors: [*c]const imgui.ImU32, size: c_int, DrawList: [*c]imgui.ImDrawList, bounds: imgui.ImRect, vert: bool, reversed: bool, continuous: bool) void;
pub extern fn ImPlot_NiceNum(x: f64, round: bool) f64;
pub extern fn ImPlot_OrderOfMagnitude(val: f64) c_int;
pub extern fn ImPlot_OrderToPrecision(order: c_int) c_int;
pub extern fn ImPlot_Precision(val: f64) c_int;
pub extern fn ImPlot_RoundTo(val: f64, prec: c_int) f64;
pub extern fn ImPlot_Intersection(pOut: [*c]imgui.ImVec2, a1: imgui.ImVec2, a2: imgui.ImVec2, b1: imgui.ImVec2, b2: imgui.ImVec2) void;
pub extern fn ImPlot_FillRange_Vector_FloatPtr(buffer: [*c]imgui.ImVector_float, n: c_int, vmin: f32, vmax: f32) void;
pub extern fn ImPlot_FillRange_Vector_doublePtr(buffer: [*c]ImVector_double, n: c_int, vmin: f64, vmax: f64) void;
pub extern fn ImPlot_FillRange_Vector_S8Ptr(buffer: [*c]ImVector_ImS8, n: c_int, vmin: imgui.ImS8, vmax: imgui.ImS8) void;
pub extern fn ImPlot_FillRange_Vector_U8Ptr(buffer: [*c]ImVector_ImU8, n: c_int, vmin: imgui.ImU8, vmax: imgui.ImU8) void;
pub extern fn ImPlot_FillRange_Vector_S16Ptr(buffer: [*c]ImVector_ImS16, n: c_int, vmin: imgui.ImS16, vmax: imgui.ImS16) void;
pub extern fn ImPlot_FillRange_Vector_U16Ptr(buffer: [*c]ImVector_ImU16, n: c_int, vmin: imgui.ImU16, vmax: imgui.ImU16) void;
pub extern fn ImPlot_FillRange_Vector_S32Ptr(buffer: [*c]ImVector_ImS32, n: c_int, vmin: imgui.ImS32, vmax: imgui.ImS32) void;
pub extern fn ImPlot_FillRange_Vector_U32Ptr(buffer: [*c]imgui.ImVector_ImU32, n: c_int, vmin: imgui.ImU32, vmax: imgui.ImU32) void;
pub extern fn ImPlot_FillRange_Vector_S64Ptr(buffer: [*c]ImVector_ImS64, n: c_int, vmin: imgui.ImS64, vmax: imgui.ImS64) void;
pub extern fn ImPlot_FillRange_Vector_U64Ptr(buffer: [*c]ImVector_ImU64, n: c_int, vmin: imgui.ImU64, vmax: imgui.ImU64) void;
pub extern fn ImPlot_CalculateBins_FloatPtr(values: [*c]const f32, count: c_int, meth: ImPlotBin, range: ImPlotRange, bins_out: [*c]c_int, width_out: [*c]f64) void;
pub extern fn ImPlot_CalculateBins_doublePtr(values: [*c]const f64, count: c_int, meth: ImPlotBin, range: ImPlotRange, bins_out: [*c]c_int, width_out: [*c]f64) void;
pub extern fn ImPlot_CalculateBins_S8Ptr(values: [*c]const imgui.ImS8, count: c_int, meth: ImPlotBin, range: ImPlotRange, bins_out: [*c]c_int, width_out: [*c]f64) void;
pub extern fn ImPlot_CalculateBins_U8Ptr(values: [*c]const imgui.ImU8, count: c_int, meth: ImPlotBin, range: ImPlotRange, bins_out: [*c]c_int, width_out: [*c]f64) void;
pub extern fn ImPlot_CalculateBins_S16Ptr(values: [*c]const imgui.ImS16, count: c_int, meth: ImPlotBin, range: ImPlotRange, bins_out: [*c]c_int, width_out: [*c]f64) void;
pub extern fn ImPlot_CalculateBins_U16Ptr(values: [*c]const imgui.ImU16, count: c_int, meth: ImPlotBin, range: ImPlotRange, bins_out: [*c]c_int, width_out: [*c]f64) void;
pub extern fn ImPlot_CalculateBins_S32Ptr(values: [*c]const imgui.ImS32, count: c_int, meth: ImPlotBin, range: ImPlotRange, bins_out: [*c]c_int, width_out: [*c]f64) void;
pub extern fn ImPlot_CalculateBins_U32Ptr(values: [*c]const imgui.ImU32, count: c_int, meth: ImPlotBin, range: ImPlotRange, bins_out: [*c]c_int, width_out: [*c]f64) void;
pub extern fn ImPlot_CalculateBins_S64Ptr(values: [*c]const imgui.ImS64, count: c_int, meth: ImPlotBin, range: ImPlotRange, bins_out: [*c]c_int, width_out: [*c]f64) void;
pub extern fn ImPlot_CalculateBins_U64Ptr(values: [*c]const imgui.ImU64, count: c_int, meth: ImPlotBin, range: ImPlotRange, bins_out: [*c]c_int, width_out: [*c]f64) void;
pub extern fn ImPlot_IsLeapYear(year: c_int) bool;
pub extern fn ImPlot_GetDaysInMonth(year: c_int, month: c_int) c_int;
pub extern fn ImPlot_MkGmtTime(pOut: [*c]ImPlotTime, ptm: [*c]struct_tm) void;
pub extern fn ImPlot_GetGmtTime(t: ImPlotTime, ptm: [*c]tm) [*c]tm;
pub extern fn ImPlot_MkLocTime(pOut: [*c]ImPlotTime, ptm: [*c]struct_tm) void;
pub extern fn ImPlot_GetLocTime(t: ImPlotTime, ptm: [*c]tm) [*c]tm;
pub extern fn ImPlot_MakeTime(pOut: [*c]ImPlotTime, year: c_int, month: c_int, day: c_int, hour: c_int, min: c_int, sec: c_int, us: c_int) void;
pub extern fn ImPlot_GetYear(t: ImPlotTime) c_int;
pub extern fn ImPlot_AddTime(pOut: [*c]ImPlotTime, t: ImPlotTime, unit: ImPlotTimeUnit, count: c_int) void;
pub extern fn ImPlot_FloorTime(pOut: [*c]ImPlotTime, t: ImPlotTime, unit: ImPlotTimeUnit) void;
pub extern fn ImPlot_CeilTime(pOut: [*c]ImPlotTime, t: ImPlotTime, unit: ImPlotTimeUnit) void;
pub extern fn ImPlot_RoundTime(pOut: [*c]ImPlotTime, t: ImPlotTime, unit: ImPlotTimeUnit) void;
pub extern fn ImPlot_CombineDateTime(pOut: [*c]ImPlotTime, date_part: ImPlotTime, time_part: ImPlotTime) void;
pub extern fn ImPlot_FormatTime(t: ImPlotTime, buffer: [*c]u8, size: c_int, fmt: ImPlotTimeFmt, use_24_hr_clk: bool) c_int;
pub extern fn ImPlot_FormatDate(t: ImPlotTime, buffer: [*c]u8, size: c_int, fmt: ImPlotDateFmt, use_iso_8601: bool) c_int;
pub extern fn ImPlot_FormatDateTime(t: ImPlotTime, buffer: [*c]u8, size: c_int, fmt: ImPlotDateTimeFmt) c_int;
pub extern fn ImPlot_ShowDatePicker(id: [*c]const u8, level: [*c]c_int, t: [*c]ImPlotTime, t1: [*c]const ImPlotTime, t2: [*c]const ImPlotTime) bool;
pub extern fn ImPlot_ShowTimePicker(id: [*c]const u8, t: [*c]ImPlotTime) bool;
pub const ImPlotPoint_getter = ?fn (?*anyopaque, c_int, [*c]ImPlotPoint) callconv(.C) ?*anyopaque;
pub extern fn ImPlot_PlotLineG(label_id: [*c]const u8, getter: ImPlotPoint_getter, data: ?*anyopaque, count: c_int) void;
pub extern fn ImPlot_PlotScatterG(label_id: [*c]const u8, getter: ImPlotPoint_getter, data: ?*anyopaque, count: c_int) void;
pub extern fn ImPlot_PlotShadedG(label_id: [*c]const u8, getter1: ImPlotPoint_getter, data1: ?*anyopaque, getter2: ImPlotPoint_getter, data2: ?*anyopaque, count: c_int) void;
pub extern fn ImPlot_PlotBarsG(label_id: [*c]const u8, getter: ImPlotPoint_getter, data: ?*anyopaque, count: c_int, width: f64) void;
pub extern fn ImPlot_PlotBarsHG(label_id: [*c]const u8, getter: ImPlotPoint_getter, data: ?*anyopaque, count: c_int, height: f64) void;
pub extern fn ImPlot_PlotDigitalG(label_id: [*c]const u8, getter: ImPlotPoint_getter, data: ?*anyopaque, count: c_int) void; | src/deps/imgui/ext/implot/c.zig |
const std = @import("std");
const assert = std.debug.assert;
const mem = std.mem;
const config = @import("../config.zig");
const StateChecker = @import("state_checker.zig").StateChecker;
const message_pool = @import("../message_pool.zig");
const MessagePool = message_pool.MessagePool;
const Message = MessagePool.Message;
const Network = @import("network.zig").Network;
const NetworkOptions = @import("network.zig").NetworkOptions;
pub const StateMachine = @import("state_machine.zig").StateMachine;
const MessageBus = @import("message_bus.zig").MessageBus;
const Storage = @import("storage.zig").Storage;
const Time = @import("time.zig").Time;
const vsr = @import("../vsr.zig");
pub const Replica = vsr.Replica(StateMachine, MessageBus, Storage, Time);
pub const Client = vsr.Client(StateMachine, MessageBus);
pub const ClusterOptions = struct {
cluster: u32,
replica_count: u8,
client_count: u8,
seed: u64,
network_options: NetworkOptions,
storage_options: Storage.Options,
};
pub const Cluster = struct {
allocator: mem.Allocator,
options: ClusterOptions,
state_machines: []StateMachine,
storages: []Storage,
times: []Time,
replicas: []Replica,
clients: []Client,
network: Network,
// TODO: Initializing these fields in main() is a bit ugly
state_checker: StateChecker = undefined,
on_change_state: fn (replica: *Replica) void = undefined,
pub fn create(allocator: mem.Allocator, prng: std.rand.Random, options: ClusterOptions) !*Cluster {
const cluster = try allocator.create(Cluster);
errdefer allocator.destroy(cluster);
{
const state_machines = try allocator.alloc(StateMachine, options.replica_count);
errdefer allocator.free(state_machines);
const storages = try allocator.alloc(Storage, options.replica_count);
errdefer allocator.free(storages);
const times = try allocator.alloc(Time, options.replica_count);
errdefer allocator.free(times);
const replicas = try allocator.alloc(Replica, options.replica_count);
errdefer allocator.free(replicas);
const clients = try allocator.alloc(Client, options.client_count);
errdefer allocator.free(clients);
const network = try Network.init(
allocator,
options.replica_count,
options.client_count,
options.network_options,
);
errdefer network.deinit();
cluster.* = .{
.allocator = allocator,
.options = options,
.state_machines = state_machines,
.storages = storages,
.times = times,
.replicas = replicas,
.clients = clients,
.network = network,
};
}
var buffer: [config.replicas_max]Storage.FaultyAreas = undefined;
const faulty_areas = Storage.generate_faulty_areas(prng, config.journal_size_max, options.replica_count, &buffer);
for (cluster.replicas) |*replica, replica_index| {
cluster.times[replica_index] = .{
.resolution = config.tick_ms * std.time.ns_per_ms,
.offset_type = .linear,
.offset_coefficient_A = 0,
.offset_coefficient_B = 0,
};
cluster.state_machines[replica_index] = StateMachine.init(options.seed);
cluster.storages[replica_index] = try Storage.init(
allocator,
config.journal_size_max,
options.storage_options,
@intCast(u8, replica_index),
faulty_areas[replica_index],
);
const message_bus = try cluster.network.init_message_bus(
options.cluster,
.{ .replica = @intCast(u8, replica_index) },
);
replica.* = try Replica.init(
allocator,
options.cluster,
options.replica_count,
@intCast(u8, replica_index),
&cluster.times[replica_index],
&cluster.storages[replica_index],
message_bus,
&cluster.state_machines[replica_index],
);
message_bus.set_on_message(*Replica, replica, Replica.on_message);
}
for (cluster.clients) |*client| {
const client_id = prng.int(u128);
const client_message_bus = try cluster.network.init_message_bus(
options.cluster,
.{ .client = client_id },
);
client.* = try Client.init(
allocator,
client_id,
options.cluster,
options.replica_count,
client_message_bus,
);
client_message_bus.set_on_message(*Client, client, Client.on_message);
}
return cluster;
}
pub fn destroy(cluster: *Cluster) void {
for (cluster.clients) |*client| client.deinit();
cluster.allocator.free(cluster.clients);
for (cluster.replicas) |*replica| replica.deinit(cluster.allocator);
cluster.allocator.free(cluster.replicas);
for (cluster.storages) |*storage| storage.deinit(cluster.allocator);
cluster.allocator.free(cluster.storages);
cluster.network.deinit();
cluster.allocator.destroy(cluster);
}
/// Reset a replica to its initial state, simulating a random crash/panic.
/// Leave the persistent storage untouched, and leave any currently
/// inflight messages to/from the replica in the network.
pub fn simulate_replica_crash(cluster: *Cluster, replica_index: u8) !void {
const replica = &cluster.replicas[replica_index];
replica.deinit(cluster.allocator);
cluster.storages[replica_index].reset();
cluster.state_machines[replica_index] = StateMachine.init(cluster.options.seed);
// The message bus and network should be left alone, as messages
// may still be inflight to/from this replica. However, we should
// do a check to ensure that we aren't leaking any messages when
// deinitializing the replica above.
const packet_simulator = &cluster.network.packet_simulator;
// The same message may be used for multiple network packets, so simply counting how
// many packets are inflight from the replica is insufficient, we need to dedup them.
var messages_in_network_set = std.AutoHashMap(*Message, void).init(cluster.allocator);
defer messages_in_network_set.deinit();
var target: u8 = 0;
while (target < packet_simulator.options.node_count) : (target += 1) {
const path = .{ .source = replica_index, .target = target };
const queue = packet_simulator.path_queue(path);
var it = queue.iterator();
while (it.next()) |data| {
try messages_in_network_set.put(data.packet.message, {});
}
}
const messages_in_network = messages_in_network_set.count();
var messages_in_pool: usize = 0;
const message_bus = cluster.network.get_message_bus(.{ .replica = replica_index });
{
var it = message_bus.pool.free_list;
while (it) |message| : (it = message.next) messages_in_pool += 1;
}
const total_messages = message_pool.messages_max_replica;
assert(messages_in_network + messages_in_pool == total_messages);
replica.* = try Replica.init(
cluster.allocator,
cluster.options.cluster,
cluster.options.replica_count,
@intCast(u8, replica_index),
&cluster.times[replica_index],
&cluster.storages[replica_index],
message_bus,
&cluster.state_machines[replica_index],
);
message_bus.set_on_message(*Replica, replica, Replica.on_message);
replica.on_change_state = cluster.on_change_state;
}
}; | src/test/cluster.zig |
const std = @import("std");
const utils = @import("utils.zig");
const Vec4 = @import("vector.zig").Vec4;
const Mat4 = @import("matrix.zig").Mat4;
const Color = @import("color.zig").Color;
const Pattern = @import("pattern.zig").Pattern;
const initVector = @import("vector.zig").initVector;
const initPoint = @import("vector.zig").initPoint;
const World = @import("world.zig").World;
const Shape = @import("shape.zig").Shape;
const Ray = @import("ray.zig").Ray;
const Intersections = @import("ray.zig").Intersections;
const Intersection = @import("ray.zig").Intersection;
const Material = @import("material.zig").Material;
const PointLight = @import("light.zig").PointLight;
const alloc = std.testing.allocator;
const MaxIterations = 5;
pub fn lighting(
object: Shape,
light: PointLight,
position: Vec4,
eyev: Vec4,
normalv: Vec4,
in_shadow: bool,
) Color {
const material = object.material;
const color = if (material.pattern) |pattern| pattern.patternAt(object, position) else material.color;
// combine surface color with light color/intensity
const effective_color = color.mult(light.intensity);
// find direction of the light source
const lightv = light.position.sub(position).normalize();
// ambient
const ambient = effective_color.scale(material.ambient);
// light_dot_normal represents cosine of the angle between
// the light vector and the normal vector.
// Negative means the light is ont he other side of the surface
const light_dot_normal = lightv.dot(normalv);
var diffuse = Color.Black;
var specular = Color.Black;
if (light_dot_normal > 0.0 and !in_shadow) {
// compute diffuse contribution
diffuse = effective_color.scale(material.diffuse * light_dot_normal);
// reflect_dot_eye represents cosine of the angle between
// reflection the vector and the eye vector.
// Negative number means the light reflects away from the eye
const reflectv = lightv.negate().reflect(normalv);
const reflect_dot_eye = reflectv.dot(eyev);
if (reflect_dot_eye > 0.0) {
const factor = std.math.pow(f64, reflect_dot_eye, material.shininess);
specular = light.intensity.scale(material.specular * factor);
}
}
return ambient.add(diffuse).add(specular);
}
test "Lighting with the eye between the light and the surface" {
const position = initPoint(0, 0, 0);
const mat = Material{};
const obj = Shape{ .material = mat };
const eyev = initVector(0, 0, -1);
const normalv = initVector(0, 0, -1);
const light = PointLight{
.position = initPoint(0, 0, -10),
.intensity = Color.init(1, 1, 1),
};
const res = lighting(obj, light, position, eyev, normalv, false);
try utils.expectColorApproxEq(Color.init(1.9, 1.9, 1.9), res);
}
test "Lighting with the eye between light and surface, eye offset 45°" {
const position = initPoint(0, 0, 0);
const mat = Material{};
const obj = Shape{ .material = mat };
const eyev = initVector(0, 1, -1).normalize();
const normalv = initVector(0, 0, -1);
const light = PointLight{
.position = initPoint(0, 0, -10),
.intensity = Color.init(1, 1, 1),
};
const res = lighting(obj, light, position, eyev, normalv, false);
try utils.expectColorApproxEq(Color.init(1.0, 1.0, 1.0), res);
}
test "Lighting with the eye opposite surface, light offset 45°" {
const position = initPoint(0, 0, 0);
const mat = Material{};
const obj = Shape{ .material = mat };
const eyev = initVector(0, 0, -1);
const normalv = initVector(0, 0, -1);
const light = PointLight{
.position = initPoint(0, 10, -10),
.intensity = Color.init(1, 1, 1),
};
const res = lighting(obj, light, position, eyev, normalv, false);
try utils.expectColorApproxEq(Color.init(0.7364, 0.7364, 0.7364), res);
}
test "Lighting with the eye in the path of the reflection vector" {
const position = initPoint(0, 0, 0);
const mat = Material{};
const obj = Shape{ .material = mat };
const eyev = initVector(0, -std.math.sqrt(2.0) / 2.0, -std.math.sqrt(2.0) / 2.0);
const normalv = initVector(0, 0, -1);
const light = PointLight{
.position = initPoint(0, 10, -10),
.intensity = Color.init(1, 1, 1),
};
const res = lighting(obj, light, position, eyev, normalv, false);
try utils.expectColorApproxEq(Color.init(1.6364, 1.6364, 1.6364), res);
}
test "Lighting with the light behind the surface" {
const position = initPoint(0, 0, 0);
const mat = Material{};
const obj = Shape{ .material = mat };
const eyev = initVector(0, 0, -1);
const normalv = initVector(0, 0, -1);
const light = PointLight{
.position = initPoint(0, 0, 10),
.intensity = Color.init(1, 1, 1),
};
const res = lighting(obj, light, position, eyev, normalv, false);
try utils.expectColorApproxEq(Color.init(0.1, 0.1, 0.1), res); // only ambient
}
test "Lighting with the surface in shadow" {
const position = initPoint(0, 0, 0);
const mat = Material{};
const obj = Shape{ .material = mat };
const eyev = initVector(0, 0, -1);
const normalv = initVector(0, 0, -1);
const light = PointLight{
.position = initPoint(0, 0, -10),
.intensity = Color.init(1, 1, 1),
};
const in_shadow = true;
const res = lighting(obj, light, position, eyev, normalv, in_shadow);
try utils.expectColorApproxEq(Color.init(0.1, 0.1, 0.1), res);
}
test "Lighting with a pattern applied" {
const a = Color.init(0.5, 0.2, 0.9);
const b = Color.init(0.2, 0.8, 1.0);
const pattern = Pattern{ .pattern = .{ .stripe = .{ .a = a, .b = b } } };
const mat = Material{
.pattern = pattern,
.ambient = 1,
.diffuse = 0,
.specular = 0,
};
const obj = Shape{ .material = mat };
const eyev = initVector(0, 0, -1);
const normalv = initVector(0, 0, -1);
const light = PointLight{
.position = initPoint(0, 0, -10),
.intensity = Color.init(1, 1, 1),
};
const in_shadow = false;
const c1 = lighting(obj, light, initPoint(0.9, 0, 0), eyev, normalv, in_shadow);
const c2 = lighting(obj, light, initPoint(1.1, 0, 0), eyev, normalv, in_shadow);
try utils.expectColorApproxEq(a, c1);
try utils.expectColorApproxEq(b, c2);
}
pub fn intersectWorld(world: World, world_ray: Ray) !Intersections {
var total_intersections = Intersections.init(world.allocator);
errdefer total_intersections.deinit();
for (world.objects.items) |object| {
var object_intersections = try object.intersect(world.allocator, world_ray);
defer object_intersections.deinit();
try total_intersections.list.appendSlice(object_intersections.list.items);
}
std.sort.sort(Intersection, total_intersections.list.items, {}, Intersections.lessThanIntersection);
return total_intersections;
}
test "Intersect a world with a ray" {
var w = try World.initDefault(alloc);
defer w.deinit();
const r = Ray.init(initPoint(0, 0, -5), initVector(0, 0, 1));
var xs = try intersectWorld(w, r);
defer xs.deinit();
try std.testing.expectEqual(@as(usize, 4), xs.list.items.len);
try utils.expectEpsilonEq(@as(f64, 4.0), xs.list.items[0].t);
try utils.expectEpsilonEq(@as(f64, 4.5), xs.list.items[1].t);
try utils.expectEpsilonEq(@as(f64, 5.5), xs.list.items[2].t);
try utils.expectEpsilonEq(@as(f64, 6.0), xs.list.items[3].t);
}
const Computations = struct {
t: f64,
object: Shape,
point: Vec4,
over_point: Vec4,
under_point: Vec4,
eyev: Vec4,
normalv: Vec4,
reflectv: Vec4,
n1: f64,
n2: f64,
inside: bool,
};
pub fn prepareComputations(intersection: Intersection, ray: Ray, xs: ?Intersections) Computations {
_ = xs;
const point = ray.position(intersection.t);
const eyev = ray.direction.negate();
var inside = false;
var normalv = intersection.object.normalAt(point);
if (normalv.dot(eyev) < 0) {
inside = true;
normalv = normalv.negate();
}
const reflectv = ray.direction.reflect(normalv);
const epsilon = 0.0001;
const over_point = point.add(normalv.scale(epsilon));
const under_point = point.sub(normalv.scale(epsilon));
var n1: f64 = 1.0;
var n2: f64 = 1.0;
if (xs != null) {
var containers = std.ArrayList(Shape).init(xs.?.allocator);
defer containers.deinit();
for (xs.?.list.items) |i| {
const is_hit = std.meta.eql(i, intersection);
if (is_hit) {
n1 = if (containers.items.len == 0) 1.0 else containers.items[containers.items.len - 1].material.refractive_index;
}
for (containers.items) |c, idx| {
if (std.meta.eql(c, i.object)) {
_ = containers.orderedRemove(idx);
break;
}
} else containers.append(i.object) catch unreachable;
if (is_hit) {
n2 = if (containers.items.len == 0) 1.0 else containers.items[containers.items.len - 1].material.refractive_index;
break;
}
}
}
return Computations{
.t = intersection.t,
.object = intersection.object,
.point = point,
.over_point = over_point,
.under_point = under_point,
.eyev = eyev,
.normalv = normalv,
.reflectv = reflectv,
.inside = inside,
.n1 = n1,
.n2 = n2,
};
}
test "Precomputing the state of an intersection" {
const r = Ray.init(initPoint(0, 0, -5), initVector(0, 0, 1));
const shape = Shape{ .geo = .{ .sphere = .{} } };
const i = Intersection{
.t = 4,
.object = shape,
};
const comps = prepareComputations(i, r, null);
try std.testing.expectEqual(@as(f64, 4.0), comps.t);
try std.testing.expectEqual(shape, comps.object);
try std.testing.expectEqual(initPoint(0, 0, -1), comps.point);
try std.testing.expectEqual(initVector(0, 0, -1), comps.eyev);
try std.testing.expectEqual(initVector(0, 0, -1), comps.normalv);
}
test "The hit, when an intersection occurs on the outside" {
const r = Ray.init(initPoint(0, 0, -5), initVector(0, 0, 1));
const shape = Shape{ .geo = .{ .sphere = .{} } };
const i = Intersection{
.t = 4,
.object = shape,
};
const comps = prepareComputations(i, r, null);
try std.testing.expectEqual(false, comps.inside);
}
test "The hit, when an intersection occurs on the inside" {
const r = Ray.init(initPoint(0, 0, 0), initVector(0, 0, 1));
const shape = Shape{ .geo = .{ .sphere = .{} } };
const i = Intersection{
.t = 1,
.object = shape,
};
const comps = prepareComputations(i, r, null);
try std.testing.expectEqual(initPoint(0, 0, 1), comps.point);
try std.testing.expectEqual(initVector(0, 0, -1), comps.eyev);
try std.testing.expectEqual(true, comps.inside);
try std.testing.expectEqual(initVector(0, 0, -1), comps.normalv);
}
test "The hit should offset the point" {
const r = Ray.init(initPoint(0, 0, -5), initVector(0, 0, 1));
const shape = Shape{
.transform = Mat4.identity().translate(0, 0, 1),
.geo = .{ .sphere = .{} },
};
const i = Intersection{
.t = 5,
.object = shape,
};
const comps = prepareComputations(i, r, null);
try std.testing.expectEqual(@as(f64, -0.0001), comps.over_point.z);
try std.testing.expect(comps.point.z > comps.over_point.z);
}
test "Precomputing the reflection vector" {
const shape = Shape{ .geo = .{ .plane = .{} } };
const r = Ray.init(initPoint(0, 0, -1), initVector(-0, -std.math.sqrt(2.0) / 2.0, std.math.sqrt(2.0) / 2.0));
const i = Intersection{
.t = std.math.sqrt(2.0),
.object = shape,
};
const comps = prepareComputations(i, r, null);
try utils.expectVec4ApproxEq(initVector(0, std.math.sqrt(2.0) / 2.0, std.math.sqrt(2.0) / 2.0), comps.reflectv);
}
pub fn initGlassSphere() Shape {
return .{
.geo = .{ .sphere = .{} },
.material = .{ .transparency = 1.0, .refractive_index = 1.5 },
};
}
test "The under point is offset below the surface" {
var shape = initGlassSphere();
shape.transform = Mat4.identity().translate(0, 0, 1);
const r = Ray.init(initPoint(0, 0, -5), initVector(0, 0, 1));
const i = Intersection{
.t = 5.0,
.object = shape,
};
const comps = prepareComputations(i, r, null);
try std.testing.expectEqual(@as(f64, 0.0001), comps.under_point.z);
try std.testing.expect(comps.point.z < comps.under_point.z);
}
test "Finding n1 and n2 at various inersections" {
const Example = struct {
index: u32,
n1: f64,
n2: f64,
};
const examples: []const Example = &[_]Example{
.{ .index = 0, .n1 = 1.0, .n2 = 1.5 },
.{ .index = 1, .n1 = 1.5, .n2 = 2.0 },
.{ .index = 2, .n1 = 2.0, .n2 = 2.5 },
.{ .index = 3, .n1 = 2.5, .n2 = 2.5 },
.{ .index = 4, .n1 = 2.5, .n2 = 1.5 },
.{ .index = 5, .n1 = 1.5, .n2 = 1.0 },
};
var a = initGlassSphere();
a.transform = Mat4.identity().scale(2, 2, 2);
a.material.refractive_index = 1.5;
var b = initGlassSphere();
b.transform = Mat4.identity().translate(0, 0, -0.25);
b.material.refractive_index = 2.0;
var c = initGlassSphere();
c.transform = Mat4.identity().translate(0, 0, 0.25);
c.material.refractive_index = 2.5;
const r = Ray.init(initPoint(0, 0, -4), initVector(0, 0, 1));
var xs = Intersections.init(alloc);
defer xs.deinit();
try xs.list.append(.{ .t = 2, .object = a });
try xs.list.append(.{ .t = 2.75, .object = b });
try xs.list.append(.{ .t = 3.25, .object = c });
try xs.list.append(.{ .t = 4.75, .object = b });
try xs.list.append(.{ .t = 5.25, .object = c });
try xs.list.append(.{ .t = 6, .object = a });
for (examples) |example| {
const i = xs.list.items[example.index];
const comps = prepareComputations(i, r, xs);
try utils.expectEpsilonEq(example.n1, comps.n1);
try utils.expectEpsilonEq(example.n2, comps.n2);
}
}
pub fn shadeHit(world: World, comps: Computations, remaining: i32) Color {
const in_shadow = isShadowed(world, comps.over_point) catch false;
const surface = lighting(
comps.object,
world.light,
comps.over_point,
comps.eyev,
comps.normalv,
in_shadow,
);
const reflected = reflectedColor(world, comps, remaining);
const refracted = refractedColor(world, comps, remaining);
const material = comps.object.material;
if (material.reflective > 0.0 and material.transparency > 0.0) {
const reflectance = schlick(comps);
return surface.add(reflected.scale(reflectance)).add(refracted.scale(1.0 - reflectance));
} else {
return surface.add(reflected).add(refracted);
}
}
test "Shading an intersection" {
var w = try World.initDefault(alloc);
defer w.deinit();
const r = Ray.init(initPoint(0, 0, -5), initVector(0, 0, 1));
const shape = w.objects.items[0];
const i = Intersection{
.t = 4,
.object = shape,
};
const comps = prepareComputations(i, r, null);
const c = shadeHit(w, comps, MaxIterations);
try utils.expectColorApproxEq(Color.init(0.38066, 0.47583, 0.2855), c);
}
test "Shading an intersection from the inside" {
var w = try World.initDefault(alloc);
defer w.deinit();
w.light = PointLight{
.position = initPoint(0, 0.25, 0),
.intensity = Color.White,
};
const r = Ray.init(initPoint(0, 0, 0), initVector(0, 0, 1));
const shape = w.objects.items[1];
const i = Intersection{
.t = 0.5,
.object = shape,
};
const comps = prepareComputations(i, r, null);
const c = shadeHit(w, comps, MaxIterations);
try utils.expectColorApproxEq(Color.init(0.90498, 0.90498, 0.90498), c);
}
test "shade_hit() is given an intersection in shadow" {
var w = World.init(alloc);
defer w.deinit();
w.light = PointLight{
.position = initPoint(0, 0, -10),
.intensity = Color.White,
};
const s1 = Shape{ .geo = .{ .sphere = .{} } };
try w.objects.append(s1);
const s2 = Shape{
.transform = Mat4.identity().translate(0, 0, 10),
.geo = .{ .sphere = .{} },
};
try w.objects.append(s2);
const r = Ray.init(initPoint(0, 0, 5), initVector(0, 0, 1));
const i = Intersection{
.t = 4,
.object = s2,
};
const comps = prepareComputations(i, r, null);
const c = shadeHit(w, comps, MaxIterations);
try utils.expectColorApproxEq(Color.init(0.1, 0.1, 0.1), c);
}
test "shade_hit() with a reflective material" {
var w = try World.initDefault(alloc);
defer w.deinit();
var shape = Shape{
.geo = .{ .plane = .{} },
.transform = Mat4.identity().translate(0, -1, 0),
.material = .{ .reflective = 0.5 },
};
try w.objects.append(shape);
const r = Ray.init(initPoint(0, 0, -3), initVector(0, -std.math.sqrt(2.0) / 2.0, std.math.sqrt(2.0) / 2.0));
const i = Intersection{
.t = std.math.sqrt(2.0),
.object = shape,
};
const comps = prepareComputations(i, r, null);
const color = shadeHit(w, comps, MaxIterations);
try utils.expectColorApproxEq(Color.init(0.87677, 0.92436, 0.82918), color);
}
test "shade_hit() with a transparent material" {
var w = try World.initDefault(alloc);
defer w.deinit();
var floor = Shape{
.geo = .{ .plane = .{} },
.transform = Mat4.identity().translate(0, -1, 0),
.material = .{
.transparency = 0.5,
.refractive_index = 1.5,
},
};
try w.objects.append(floor);
var ball = Shape{
.geo = .{ .sphere = .{} },
.transform = Mat4.identity().translate(0, -3.5, -0.5),
.material = .{
.color = Color.init(1, 0, 0),
.ambient = 0.5,
},
};
try w.objects.append(ball);
const r = Ray.init(initPoint(0, 0, -3), initVector(0, -std.math.sqrt(2.0) / 2.0, std.math.sqrt(2.0) / 2.0));
var xs = Intersections.init(alloc);
defer xs.deinit();
try xs.list.append(.{
.t = std.math.sqrt(2.0),
.object = floor,
});
const comps = prepareComputations(xs.list.items[0], r, xs);
const color = shadeHit(w, comps, MaxIterations);
try utils.expectColorApproxEq(Color.init(0.93642, 0.68642, 0.68642), color);
}
test "shade_hit() with a reflective, transparent material" {
var w = try World.initDefault(alloc);
defer w.deinit();
var floor = Shape{
.geo = .{ .plane = .{} },
.transform = Mat4.identity().translate(0, -1, 0),
.material = .{
.reflective = 0.5,
.transparency = 0.5,
.refractive_index = 1.5,
},
};
try w.objects.append(floor);
var ball = Shape{
.geo = .{ .sphere = .{} },
.transform = Mat4.identity().translate(0, -3.5, -0.5),
.material = .{
.color = Color.init(1, 0, 0),
.ambient = 0.5,
},
};
try w.objects.append(ball);
const r = Ray.init(initPoint(0, 0, -3), initVector(0, -std.math.sqrt(2.0) / 2.0, std.math.sqrt(2.0) / 2.0));
var xs = Intersections.init(alloc);
defer xs.deinit();
try xs.list.append(.{
.t = std.math.sqrt(2.0),
.object = floor,
});
const comps = prepareComputations(xs.list.items[0], r, xs);
const color = shadeHit(w, comps, MaxIterations);
try utils.expectColorApproxEq(Color.init(0.93391, 0.69643, 0.69243), color);
}
pub fn worldColorAt(world: World, ray: Ray, remaining: i32) !Color {
var xs = try intersectWorld(world, ray);
defer xs.deinit();
const hit = xs.hit();
if (hit != null) {
const comps = prepareComputations(hit.?, ray, xs);
return shadeHit(world, comps, remaining);
} else {
return Color.Black;
}
}
test "The color when a ray misses" {
var w = try World.initDefault(alloc);
defer w.deinit();
const r = Ray.init(initPoint(0, 0, -5), initVector(0, 1, 0));
const c = try worldColorAt(w, r, MaxIterations);
try utils.expectColorApproxEq(Color.init(0, 0, 0), c);
}
test "The color when a ray hits" {
var w = try World.initDefault(alloc);
defer w.deinit();
const r = Ray.init(initPoint(0, 0, -5), initVector(0, 0, 1));
const c = try worldColorAt(w, r, MaxIterations);
try utils.expectColorApproxEq(Color.init(0.38066, 0.47583, 0.2855), c);
}
test "The color with an intersection behind the ray" {
var w = try World.initDefault(alloc);
defer w.deinit();
var outer = &w.objects.items[0];
outer.material.color = Color.init(0.3, 0.3, 1.0);
outer.material.ambient = 1.0;
var inner = &w.objects.items[1];
inner.material.color = Color.init(0.5, 1.0, 0.2);
inner.material.ambient = 1.0;
const r = Ray.init(initPoint(0, 0, 0.75), initVector(0, 0, -1));
const c = try worldColorAt(w, r, MaxIterations);
try utils.expectColorApproxEq(inner.material.color, c);
}
test "worldColorAt() with mutually reflective surfaces" {
var w = World.init(alloc);
defer w.deinit();
w.light = PointLight{
.position = initPoint(0, 0, 0),
.intensity = Color.init(1, 1, 1),
};
var lower = Shape{
.geo = .{ .plane = .{} },
.transform = Mat4.identity().translate(0, -1, 0),
.material = .{ .reflective = 1 },
};
try w.objects.append(lower);
var upper = Shape{
.geo = .{ .plane = .{} },
.transform = Mat4.identity().translate(0, 1, 0),
.material = .{ .reflective = 1 },
};
try w.objects.append(upper);
const r = Ray.init(initPoint(0, 0, 0), initVector(0, 1, 1));
// should terminate
_ = try worldColorAt(w, r, MaxIterations);
}
pub fn viewTransform(from: Vec4, to: Vec4, up: Vec4) Mat4 {
const forward = to.sub(from).normalize();
const left = forward.cross(up.normalize());
const true_up = left.cross(forward);
const orientation = Mat4{
.mat = .{
.{ left.x, left.y, left.z, 0 },
.{ true_up.x, true_up.y, true_up.z, 0 },
.{ -forward.x, -forward.y, -forward.z, 0 },
.{ 0, 0, 0, 1 },
},
};
const translation = Mat4.identity().translate(-from.x, -from.y, -from.z);
return orientation.mult(translation);
}
test "The transformation matrix for the default orientiation" {
const from = initPoint(0, 0, 0);
const to = initPoint(0, 0, -1);
const up = initVector(0, 1, 0);
const t = viewTransform(from, to, up);
try utils.expectMatrixApproxEq(t, Mat4.identity());
}
test "The view transformation moves the world" {
const from = initPoint(0, 0, 8);
const to = initPoint(0, 0, 0);
const up = initVector(0, 1, 0);
const t = viewTransform(from, to, up);
try utils.expectMatrixApproxEq(t, Mat4.identity().translate(0, 0, -8));
}
test "An arbitrary view transformation" {
const from = initPoint(1, 3, 2);
const to = initPoint(4, -2, 8);
const up = initVector(1, 1, 0);
const t = viewTransform(from, to, up);
try utils.expectMatrixApproxEq(t, Mat4{
.mat = .{
.{ -0.50709, 0.50709, 0.67612, -2.36643 },
.{ 0.76772, 0.60609, 0.12122, -2.82843 },
.{ -0.35857, 0.59761, -0.71714, 0.00000 },
.{ 0.00000, 0.00000, 0.00000, 1.00000 },
},
});
}
fn isShadowed(world: World, point: Vec4) !bool {
const v = world.light.position.sub(point);
const distance = v.length();
const direction = v.normalize();
const ray = Ray.init(point, direction);
var xs = try intersectWorld(world, ray);
defer xs.deinit();
const hit = xs.hit();
return (hit != null and hit.?.t < distance);
}
test "There is no shadow when nothing is collinear with point and light" {
var w = try World.initDefault(alloc);
defer w.deinit();
const p = initPoint(0, 10, 0);
const result = try isShadowed(w, p);
try std.testing.expect(result == false);
}
test "The shadow when an object is between the point and the light" {
var w = try World.initDefault(alloc);
defer w.deinit();
const p = initPoint(10, -10, 10);
const result = try isShadowed(w, p);
try std.testing.expect(result == true);
}
test "There is no shadow when an object is behind the light" {
var w = try World.initDefault(alloc);
defer w.deinit();
const p = initPoint(-20, 20, -20);
const result = try isShadowed(w, p);
try std.testing.expect(result == false);
}
test "There is no shadow when an object is behind the point" {
var w = try World.initDefault(alloc);
defer w.deinit();
const p = initPoint(-2, 2, -2);
const result = try isShadowed(w, p);
try std.testing.expect(result == false);
}
pub fn refractedColor(world: World, comps: Computations, remaining: i32) Color {
if (remaining <= 0) {
return Color.Black;
}
if (std.math.approxEqAbs(f64, comps.object.material.transparency, 0.0, std.math.epsilon(f64))) {
return Color.Black;
}
const n_ratio = comps.n1 / comps.n2;
const cos_i = comps.eyev.dot(comps.normalv);
const sin2_t = n_ratio * n_ratio * (1 - cos_i * cos_i);
if (sin2_t > 1.0) {
// total internal reflection
return Color.Black;
}
const cos_t = std.math.sqrt(1.0 - sin2_t);
const direction = comps.normalv.scale(n_ratio * cos_i - cos_t).sub(comps.eyev.scale(n_ratio));
const refract_ray = Ray.init(comps.under_point, direction);
const color = worldColorAt(world, refract_ray, remaining - 1) catch Color.Black;
return color.scale(comps.object.material.transparency);
}
test "The refracted color with an opaque surface" {
var w = try World.initDefault(alloc);
defer w.deinit();
const r = Ray.init(initPoint(0, 0, -5), initVector(0, 0, 1));
var shape = &w.objects.items[1];
shape.material.transparency = 0.0;
const i = Intersection{
.t = 4,
.object = shape.*,
};
const comps = prepareComputations(i, r, null);
const color = refractedColor(w, comps, MaxIterations);
try utils.expectColorApproxEq(Color.Black, color);
}
test "The refracted color at maximum recursive depth" {
var w = try World.initDefault(alloc);
defer w.deinit();
var shape = &w.objects.items[0];
shape.material.transparency = 1.0;
shape.material.refractive_index = 1.5;
const r = Ray.init(initPoint(0, 0, -5), initVector(0, 0, 1));
const i = Intersection{
.t = 4,
.object = shape.*,
};
const comps = prepareComputations(i, r, null);
const color = refractedColor(w, comps, 0);
try utils.expectColorApproxEq(Color.Black, color);
}
test "The refracted color under total internal reflection" {
var w = try World.initDefault(alloc);
defer w.deinit();
var shape = &w.objects.items[0];
shape.material.transparency = 1.0;
shape.material.refractive_index = 1.5;
const r = Ray.init(initPoint(0, 0, std.math.sqrt(2.0) / 2.0), initVector(0, 1, 0));
var xs = Intersections.init(alloc);
defer xs.deinit();
try xs.list.append(.{ .t = -std.math.sqrt(2.0) / 2.0, .object = shape.* });
try xs.list.append(.{ .t = std.math.sqrt(2.0) / 2.0, .object = shape.* });
const comps = prepareComputations(xs.list.items[1], r, xs);
const color = refractedColor(w, comps, MaxIterations);
try utils.expectColorApproxEq(Color.Black, color);
}
test "The refracted color with a refracted ray" {
var w = try World.initDefault(alloc);
defer w.deinit();
var a = &w.objects.items[0];
a.material.ambient = 1.0;
a.material.pattern = .{ .pattern = .{ .point = {} } };
var b = &w.objects.items[1];
b.material.transparency = 1.0;
b.material.refractive_index = 1.5;
const r = Ray.init(initPoint(0, 0, 0.1), initVector(0, 1, 0));
var xs = Intersections.init(alloc);
defer xs.deinit();
try xs.list.append(.{ .t = -0.9899, .object = a.* });
try xs.list.append(.{ .t = -0.4899, .object = b.* });
try xs.list.append(.{ .t = 0.4899, .object = b.* });
try xs.list.append(.{ .t = 0.9899, .object = a.* });
const comps = prepareComputations(xs.list.items[2], r, xs);
const color = refractedColor(w, comps, MaxIterations);
try utils.expectColorApproxEq(Color.init(0, 0.99888, 0.04725), color);
}
pub fn reflectedColor(world: World, comps: Computations, remaining: i32) Color {
if (remaining <= 0) {
return Color.Black;
}
const reflective = comps.object.material.reflective;
if (std.math.approxEqAbs(f64, reflective, 0.0, std.math.epsilon(f64))) {
return Color.Black;
}
const reflect_ray = Ray.init(comps.over_point, comps.reflectv);
const color = worldColorAt(world, reflect_ray, remaining - 1) catch Color.Black;
return color.scale(reflective);
}
test "The reflected color for a nonreflective material" {
var w = try World.initDefault(alloc);
defer w.deinit();
const r = Ray.init(initPoint(0, 0, 0), initVector(0, 0, 1));
var shape = &w.objects.items[1];
shape.material.ambient = 1.0;
const i = Intersection{
.t = 1,
.object = shape.*,
};
const comps = prepareComputations(i, r, null);
const color = reflectedColor(w, comps, MaxIterations);
try utils.expectColorApproxEq(Color.Black, color);
}
test "The reflected color for a nonreflective material" {
var w = try World.initDefault(alloc);
defer w.deinit();
var shape = Shape{
.geo = .{ .plane = .{} },
.transform = Mat4.identity().translate(0, -1, 0),
.material = .{ .reflective = 0.5 },
};
try w.objects.append(shape);
const r = Ray.init(initPoint(0, 0, -3), initVector(0, -std.math.sqrt(2.0) / 2.0, std.math.sqrt(2.0) / 2.0));
const i = Intersection{
.t = std.math.sqrt(2.0),
.object = shape,
};
const comps = prepareComputations(i, r, null);
const color = reflectedColor(w, comps, MaxIterations);
try utils.expectColorApproxEq(Color.init(0.19032, 0.2379, 0.14274), color);
}
fn schlick(comps: Computations) f64 {
// find cosine of the angle between eye and normal vector
var cos = comps.eyev.dot(comps.normalv);
// total internal reflection can only occur if n1>n2
if (comps.n1 > comps.n2) {
const n = comps.n1 / comps.n2;
const sin2_t = n * n * (1.0 - cos * cos);
if (sin2_t > 1.0) {
return 1.0;
}
// compute cosine of theta_t using trig identity
const cos_t = std.math.sqrt(1.0 - sin2_t);
// when n1 > n2, use cos(theta_t) instead
cos = cos_t;
}
const r0 = std.math.pow(f64, (comps.n1 - comps.n2) / (comps.n1 + comps.n2), 2.0);
return r0 + (1 - r0) * std.math.pow(f64, 1 - cos, 5.0);
}
test "The schlick approximation under total internal reflection" {
const shape = initGlassSphere();
const r = Ray.init(initPoint(0, 0, std.math.sqrt(2.0) / 2.0), initVector(0, 1, 0));
var xs = Intersections.init(alloc);
defer xs.deinit();
try xs.list.append(.{ .t = -std.math.sqrt(2.0) / 2.0, .object = shape });
try xs.list.append(.{ .t = std.math.sqrt(2.0) / 2.0, .object = shape });
const comps = prepareComputations(xs.list.items[1], r, xs);
const reflectance = schlick(comps);
try std.testing.expectApproxEqAbs(@as(f64, 1.0), reflectance, 0.00001);
}
test "The Schlick approximation with a perpendicular viewing angle" {
const shape = initGlassSphere();
const r = Ray.init(initPoint(0, 0, 0), initVector(0, 1, 0));
var xs = Intersections.init(alloc);
defer xs.deinit();
try xs.list.append(.{ .t = -1, .object = shape });
try xs.list.append(.{ .t = 1, .object = shape });
const comps = prepareComputations(xs.list.items[1], r, xs);
const reflectance = schlick(comps);
try std.testing.expectApproxEqAbs(@as(f64, 0.04), reflectance, 0.00001);
}
test "The Schlick approximation with small angle and n2 > n1" {
const shape = initGlassSphere();
const r = Ray.init(initPoint(0, 0.99, -2), initVector(0, 0, 1));
var xs = Intersections.init(alloc);
defer xs.deinit();
try xs.list.append(.{ .t = 1.8589, .object = shape });
const comps = prepareComputations(xs.list.items[0], r, xs);
const reflectance = schlick(comps);
try std.testing.expectApproxEqAbs(@as(f64, 0.48873), reflectance, 0.00001);
} | calc.zig |
const std = @import("std");
const utils = @import("utils.zig");
const Vec3 = @import("vec.zig").Vec3;
const Ray = @import("ray.zig").Ray;
pub const Camera = struct {
const Self = @This();
origin: Vec3,
horizontal: Vec3,
vertical: Vec3,
lower_left_corner: Vec3,
u: Vec3,
v: Vec3,
w: Vec3,
lens_radius: f32,
pub const Args = struct {
origin: Vec3,
target: Vec3,
up: Vec3,
vertical_fov: f32,
aspect_ratio: f32,
aperture: f32,
focus_distance: f32,
};
pub fn init(args: *const Args) Self {
const theta = utils.toRadians(args.vertical_fov);
const h = std.math.tan(theta / 2);
const viewport_height = 2.0 * h;
const viewport_width = args.aspect_ratio * viewport_height;
// Calculate orthonormal camera basis.
const w = args.origin.sub(args.target).normalize();
const u = args.up.cross(w);
const v = w.cross(u);
const horizontal = u.scale(args.focus_distance * viewport_width);
const vertical = v.scale(args.focus_distance * viewport_height);
return Self{
.origin = args.origin,
.horizontal = horizontal,
.vertical = vertical,
.lower_left_corner = args.origin
.sub(horizontal.scale(0.5))
.sub(vertical.scale(0.5))
.sub(w.scale(args.focus_distance)),
.u = u,
.v = v,
.w = w,
.lens_radius = args.aperture / 2,
};
}
pub fn ray(self: *const Self, s: f32, t: f32, random: *std.rand.Random) Ray {
// Generate random rays originating from inside a disk centered at the
// camera origin to simulate defocus blur.
var disk = utils.randomVecInUnitSphere(random);
disk.z = 0;
disk = disk.scale(self.lens_radius);
const offset = self.u.scale(disk.x).add(self.u.scale(disk.y));
const origin = self.origin.add(offset);
const end = self.lower_left_corner
.add(self.horizontal.scale(s))
.add(self.vertical.scale(t));
return Ray{ .origin = origin, .dir = end.sub(origin) };
}
}; | src/camera.zig |
const std = @import("std");
const fs = std.fs;
const stdout = std.io.getStdOut().outStream();
const print = stdout.print;
const stderr = std.io.getStdErr().outStream();
const printErr = stderr.print;
const allocPrint0 = std.fmt.allocPrint0;
const Allocator = std.mem.Allocator;
const t = @import("tokenize.zig");
const tokenizeFile = t.tokenizeFile;
const streq = t.streq;
const TokenKind = t.TokenKind;
const err = @import("error.zig");
const error_at = err.error_at;
const pr = @import("parse.zig");
const parse = pr.parse;
const codegen = @import("codegen.zig").codegen;
const allocator = @import("allocator.zig");
const ZugccOption = struct {
output_path: [:0]u8,
input_path: [:0]u8,
};
pub fn main() !void {
var arena = std.heap.ArenaAllocator.init(std.heap.page_allocator);
defer arena.deinit();
allocator.setAllocator(&arena.allocator);
const option = try parseArgs(&arena.allocator);
const tokenized = try tokenizeFile(option.*.input_path);
var ti: usize = 0;
const functions = try parse(tokenized.items, &ti);
var out = openOutFile(option.*.output_path);
try out.outStream().print(".file 1 \"{}\"\n", .{option.*.input_path});
try codegen(functions, &out);
}
fn parseArgs(alloc: *Allocator) !*ZugccOption {
const args = try std.process.argsAlloc(alloc);
defer std.process.argsFree(alloc, args);
var option = try alloc.create(ZugccOption);
option.* = ZugccOption{
.input_path = "",
.output_path = "",
};
var output = false;
for (args) |arg, argi| {
if (streq(arg, "--help")) {
usage(0);
}
if (streq(arg, "-o")) {
output = true;
continue;
}
if (output) {
option.*.output_path = try allocPrint0(alloc, "{}", .{arg});
output = false;
continue;
}
if (arg.len > 1 and arg[0] == '-') {
std.debug.panic("Unknown argument: {}\n", .{arg});
}
if (argi > 0)
option.*.input_path = try allocPrint0(alloc, "{}", .{arg});
}
return option;
}
fn usage(status: u8) void {
printErr("zugcc [ -o <path> ] <file>\n", .{}) catch {};
std.os.exit(status);
}
fn openOutFile(filename: [:0]u8) fs.File {
if (filename.len == 0 or streq(filename, "-")) {
return std.io.getStdOut();
} else {
const cwd = fs.cwd();
cwd.writeFile(filename, "") catch |e| {
std.debug.panic("Unable to create file: {}\n", .{@errorName(e)});
};
return cwd.openFile(filename, .{ .write = true }) catch |e| {
std.debug.panic("Unable to open file: {}\n", .{@errorName(e)});
};
}
} | src/zugcc.zig |
// $ zig run test.zig
// serialised: { 7, 0, 0, 0, 0, 0, 0, 0, 98, 114, 111, 115, 101, 112, 104, 17,
// 0, 0, 0, 0, 0, 0, 0, 107, 105, 110, 103, 32, 111, 102, 32, 97, 108, 108, 32,
// 107, 105, 110, 103, 115, 41, 35 }
// thing name: broseph
// thing title: king of all kings
// thing hp: 9001
// $
const std = @import("std");
const MyThing = struct {
name: []u8,
title: []u8,
hp: u16,
fn init(allocator: *std.mem.Allocator, name: []const u8, title: []const u8, hp: u16) !MyThing {
var name_copy = try allocator.dupe(u8, name);
errdefer allocator.free(name_copy);
var title_copy = try allocator.dupe(u8, title);
return MyThing{
.name = name_copy,
.title = title_copy,
.hp = hp,
};
}
fn deinit(self: *MyThing, allocator: *std.mem.Allocator) void {
allocator.free(self.title);
allocator.free(self.name);
}
fn serialise(self: MyThing, writer: anytype) !void {
try writer.writeIntLittle(usize, self.name.len);
try writer.writeAll(self.name);
try writer.writeIntLittle(usize, self.title.len);
try writer.writeAll(self.title);
try writer.writeIntLittle(u16, self.hp);
}
fn deserialise(allocator: *std.mem.Allocator, reader: anytype) !MyThing {
const name_len = try reader.readIntLittle(usize);
var name = try allocator.alloc(u8, name_len);
errdefer allocator.free(name);
try reader.readNoEof(name);
const title_len = try reader.readIntLittle(usize);
var title = try allocator.alloc(u8, title_len);
errdefer allocator.free(title);
try reader.readNoEof(title);
const hp = try reader.readIntLittle(u16);
return MyThing{
.name = name,
.title = title,
.hp = hp,
};
}
};
pub fn main() !void {
var gpa = std.heap.GeneralPurposeAllocator(.{}){};
defer _ = gpa.deinit();
var buf = std.ArrayList(u8).init(&gpa.allocator);
defer buf.deinit();
{
var thing = try MyThing.init(&gpa.allocator, "broseph", "king of all kings", 9001);
defer thing.deinit(&gpa.allocator);
try thing.serialise(buf.writer());
}
std.debug.print("serialised: {any}\n", .{buf.items});
{
var thing = try MyThing.deserialise(&gpa.allocator, std.io.fixedBufferStream(buf.items).reader());
defer thing.deinit(&gpa.allocator);
std.debug.print("thing name: {s}\n", .{thing.name});
std.debug.print("thing title: {s}\n", .{thing.title});
std.debug.print("thing hp: {}\n", .{thing.hp});
}
} | src/serialize_deserialize_struct.zig |
const std = @import("std");
const zlm = @import("zlm");
const ObjExporter = @import("obj_exporter.zig").ObjExporter;
const ROM = @import("rom.zig").ROM;
const Track = @import("track/track.zig").Track;
const util = @import("util.zig");
const Viewer = @import("render/viewer.zig").Viewer;
inline fn strEq(a: []const u8, b: []const u8) bool {
return std.mem.eql(u8, a, b);
}
// TODO is this written anywhere in the ROM?
const track_count = 28;
fn decodeChar(in: u8) u8 {
return switch (in) {
0...9 => in + '0',
10...35 => in + ('a' - 10),
36 => '-',
37 => '.',
38 => '\'',
39 => '"',
255 => ' ',
else => '?',
};
}
fn processPalette(code: u16) zlm.Vec3 {
const r = code & 31;
const g = (code >> 5) & 31;
const b = (code >> 10) & 31;
return zlm.vec3(
@intToFloat(f32, r) / 31,
@intToFloat(f32, g) / 31,
@intToFloat(f32, b) / 31,
);
}
const Names = struct {
// the single buffer used to store all the names
buffer: []u8,
// slices for each name
names: [track_count][]u8,
fn deinit(self: Names, allocator: *std.mem.Allocator) void {
allocator.free(self.buffer);
}
};
fn loadNames(allocator: *std.mem.Allocator, rom: ROM) !Names {
// buffer to store names in
const name_buffer = try allocator.alloc(u8, 255 * track_count);
errdefer allocator.free(name_buffer);
// allocator to help allocate names in the buffer
var name_allocator = std.heap.FixedBufferAllocator.init(name_buffer);
// read names from memory
var name_pointers = rom.view(0x78000);
var names: [track_count][]u8 = undefined;
var hashes: [track_count][]u8 = undefined;
for (names) |*name| {
const name_location = 0x70000 + @as(u24, try name_pointers.reader().readIntLittle(u16));
var name_view = rom.view(name_location);
// we don't need to deallocate this on failure because the backing buffer is deallocated on failure
var name_slice = try name_allocator.allocator.alloc(u8, try name_view.reader().readByte());
for (name_slice) |*char| {
char.* = decodeChar(try name_view.reader().readByte());
}
// put name in array
name.* = name_slice;
}
// return names struct
return Names{
.buffer = name_buffer,
.names = names,
};
}
pub const REPL = struct {
allocator: *std.mem.Allocator,
track_names: Names,
rom: ROM,
viewer: *Viewer,
pub fn init(allocator: *std.mem.Allocator, viewer: *Viewer, rom: ROM) !REPL {
const track_names = try loadNames(allocator, rom);
errdefer track_names.deinit(allocator);
return REPL{
.allocator = allocator,
.track_names = track_names,
.rom = rom,
.viewer = viewer,
};
}
pub fn deinit(self: *REPL) void {
self.track_names.deinit(self.allocator);
}
fn yield(self: *REPL) void {
suspend self.viewer.resumer = @frame();
}
fn readLine(self: *REPL, stdin_file: std.fs.File, line_buf: []u8) !?[]u8 {
// TODO multi-platform support... no doubt a lot of people are going to want to use this on windows
// i is our index into the line buffer
var i: usize = 0;
// this pollfd structure tells the kernel we're looking for data from stdin
var pollfd = std.os.pollfd{
.fd = stdin_file.handle,
.events = std.os.POLLIN,
.revents = undefined,
};
while (true) {
// ask the kernel if we can get data right now
const n = try std.os.poll(@ptrCast(*[1]std.os.pollfd, &pollfd), 0);
if (n == 1 and pollfd.revents & std.os.POLLIN != 0) {
// add the byte, and increment i
const byte = stdin_file.reader().readByte() catch |err| switch (err) {
error.EndOfStream => return null,
else => return err,
};
// if that's the delimiter, return
if (byte == '\n') {
return line_buf[0..i];
}
// add the byte to the buffer, and incrment the index
line_buf[i] = byte;
i += 1;
// if we're out of space, signal that the stream is too long
if (i == line_buf.len) {
return error.StreamTooLong;
}
} else {
// if we're not supposed to be running, quit now
if (!self.viewer.running) {
return null;
}
// suspend so the graphics can run
self.yield();
}
}
}
fn loadPalette(self: *REPL, id: u8) !void {
// TODO battle tracks run in 4bpp mode unlike the rest of the tracks, figure out how the
// colors are mapped there, because our current method gets strange results for these tracks
// noticed that by forcing the game to load a battle track in another mode, the colors
// appear in-game as they do in this editor
// palette entries for 3d stuff are here
var palette_view = self.rom.view(try self.rom.view(0x3F649 + @as(u24, id) * 3).reader().readIntLittle(u24));
for (self.viewer.renderer.palette) |*color| {
color.* = processPalette(try palette_view.reader().readIntLittle(u16));
}
// entries for bg palette (may be used by 3d, see: sky ramp)
palette_view.pos = try self.rom.view(0x3F6F1 + @as(u24, id) * 3).reader().readIntLittle(u24);
for (self.viewer.renderer.palette[0..16]) |*color| {
color.* = processPalette(try palette_view.reader().readIntLittle(u16));
}
}
fn modelTest(self: *REPL) !void {
self.viewer.track.clear(self.allocator);
var model_id: u16 = 0xA040 + 0x1C;
var x: u8 = 0;
var y: u8 = 0;
var z: u8 = 0;
while (model_id < 0xFE88) : (model_id += 0x1C) {
try self.viewer.track.append(self.allocator, .{
.x = (@as(i16, x) - 5) * 6000,
.y = (@as(i16, y) - 5) * 6000,
.z = (@as(i16, z) - 5) * 6000,
.dir = 0,
.model_id = model_id,
.code_pointer = 0x9C5B6, // dummy code pointer so something renders
});
x += 1;
if (x == 10) {
x = 0;
y += 1;
if (y == 10) {
y = 0;
z += 1;
}
}
}
// load easy ride's palette
try self.loadPalette(0);
// yield so we don't print "> " until it's done loading
self.yield();
}
fn showOne(self: *REPL, model_id: u16) !void {
self.viewer.track.clear(self.allocator);
try self.viewer.track.append(self.allocator, .{
.x = 1000,
.y = 0,
.z = 0,
.dir = 0,
.model_id = model_id,
.code_pointer = 0x9C5B6, // hardcoded code pointer so something renders
});
// load easy ride's palette
try self.loadPalette(0);
// yield so we don't print "> " until it's done loading
self.yield();
}
fn loadTrack(self: *REPL, id: u8) !void {
var view = self.rom.view(try self.rom.view(0x3F4A5 + @as(u24, id) * 3).reader().readIntLittle(u24));
const reader = view.reader();
// http://acmlm.kafuka.org/board/thread.php?id=5441
var dir: u8 = 0;
self.viewer.track.clear(self.allocator);
while (true) {
switch (try reader.readByte()) {
0x02, 0x0C => {
const x = try reader.readIntLittle(i16);
const y = try reader.readIntLittle(i16);
const z = try reader.readIntLittle(i16);
const model_id = try reader.readIntLittle(u16);
view.pos += 2;
const code_pointer = try reader.readIntLittle(u24);
view.pos += 8;
try self.viewer.track.append(self.allocator, .{
.x = x,
.y = y,
.z = z,
.dir = dir,
.model_id = model_id,
.code_pointer = code_pointer,
});
},
0x08 => {
dir = try reader.readByte();
},
0x04 => break,
0x06 => {},
0x14, 0x1A => view.pos += 2,
0x16, 0x18 => view.pos += 3,
0x12 => view.pos += 8,
0x0A => view.pos += 24,
0x0E => view.pos += 25,
else => return error.UnrecognizedTag,
}
}
try self.loadPalette(id);
// yield so we don't print "> " until it's done loading
self.yield();
}
fn parseTrackNumberOrName(self: REPL, arg: []const u8) u8 {
const parsed_index = std.fmt.parseUnsigned(u8, arg, 10) catch 0;
if (parsed_index > 0 and parsed_index <= track_count) {
return parsed_index;
} else for (self.track_names.names) |name, i| {
if (strEq(arg, name)) {
return @intCast(u8, i) + 1;
}
} else {
return 0;
}
}
fn tryRun(self: *REPL) !void {
// get i/o
const stdin_file = std.io.getStdIn();
const stdout_file = std.io.getStdOut();
const stdin = stdin_file.reader();
const stdout = stdout_file.writer();
// display a welcoming message
try stdout.writeAll("welcome to trax viewer\ntype help for help\n");
// allocate an input buffer
const line_buf = try self.allocator.alloc(u8, 4096);
defer self.allocator.free(line_buf);
// read-eval-print-loop
while (self.viewer.running) {
// get a line from stdin
try stdout.writeAll("> ");
// break on EOF
const input = (try self.readLine(stdin_file, line_buf)) orelse break;
// process it
// TODO clean up, including catching errors per-command
if (strEq(input, "h") or strEq(input, "help")) {
try stdout.writeAll(
\\h, help | display this help
\\q, quit | quit trax viewer
\\tracks | print track names
\\load <number/name> | view a track
\\show <model_id> | view a single model, id is 4 hex digits
\\debug | test of viewing all models
\\export <filename> | export track to a .obj file (work in progress)
\\
);
} else if (strEq(input, "q") or strEq(input, "quit")) {
self.viewer.running = false;
break;
} else if (strEq(input, "tracks")) {
for (self.track_names.names) |name, i| {
try stdout.print("{: >2} {s}\n", .{ i, name });
}
} else if (strEq(input, "debug")) {
try self.modelTest();
} else if (std.mem.startsWith(u8, input, "export ")) {
const filename = input[7..];
const file = try std.fs.cwd().createFile(filename, .{});
defer file.close();
var obj_exporter = ObjExporter(std.fs.File.Writer).init(file.writer());
self.viewer.track.writeTo(self.rom, 0, &obj_exporter);
} else if (std.mem.startsWith(u8, input, "load ")) {
const i = self.parseTrackNumberOrName(input[5..]);
if (i == 0) {
try stdout.writeAll("track not found\n");
} else {
try stdout.print("loading {s}\n", .{self.track_names.names[i - 1]});
self.loadTrack(i - 1) catch |err| {
try stdout.print("error while loading track: {}\n", .{err});
if (@errorReturnTrace()) |trace| {
std.debug.dumpStackTrace(trace.*);
}
self.viewer.track.clear(self.allocator);
};
}
} else if (std.mem.startsWith(u8, input, "show ")) {
const id = if (input.len == 9) std.fmt.parseUnsigned(u16, input[5..], 16) catch null else null;
if (id) |i| {
try self.showOne(i);
} else {
try stdout.writeAll("expected a 4-digit hex id\n");
}
} else {
try stdout.writeAll("unknown command\n");
}
}
}
pub fn run(self: *REPL) void {
util.errorBoundary(self.tryRun());
self.viewer.running = false;
}
}; | src/repl.zig |
const std = @import("std");
const ascii = std.ascii;
const BufMap = std.BufMap;
const debug = std.debug;
const mem = std.mem;
const testing = std.testing;
/// Caller responsible for de-initializing returned BufMap.
/// Bytes are not kept in map.
pub fn fromBytes(allocator: mem.Allocator, bytes: []const u8) !BufMap {
var map = BufMap.init(allocator);
errdefer map.deinit();
var lines = mem.split(u8, bytes, "\n");
while (lines.next()) |line| {
var key_begin: u32 = 0;
var key_end: u32 = 0;
var value_begin: u32 = 0;
var split_location: u32 = 0;
var key: []const u8 = undefined;
var value: []const u8 = undefined;
if (line.len == 0) { continue; }
while (key_begin < line.len and ascii.isBlank(line[key_begin])) : (key_begin += 1) {}
if (key_begin == line.len or line[key_begin] == '#') { continue; }
if (line[key_begin] == '=') {
return error.MissingKey;
}
split_location = key_begin;
while (split_location < line.len and line[split_location] != '=') : (split_location += 1) {}
if (split_location == line.len) {
return error.MissingValue;
}
key_end = split_location - 1;
while (key_begin < key_end and ascii.isBlank(line[key_end])) : (key_end -= 1) {}
key_end += 1;
key = line[key_begin..key_end];
value_begin = split_location + 1;
while (value_begin < line.len and ascii.isBlank(line[value_begin])) : (value_begin += 1) {}
value = line[value_begin..];
try map.put(key, value);
}
return map;
}
/// Caller responsible for de-initializing returned BufMap
pub fn fromFile(allocator: mem.Allocator, path: []const u8, max_bytes: usize) !BufMap {
var map = BufMap.init(allocator);
errdefer map.deinit();
var file_bytes = try std.fs.cwd().readFileAlloc(allocator, path, max_bytes);
defer allocator.free(file_bytes);
return try fromBytes(allocator, file_bytes);
}
test "fromBytes parses correctly" {
const conf =
\\ thing1=banana and all that
\\ thing2=orange
\\ # this is a comment
\\ thing3=pear
\\ lots of spaces=wowza that's a lot
\\
\\ space between = the equals
\\ no value=
;
var map = try fromBytes(testing.allocator, conf);
defer map.deinit();
try testing.expectEqualStrings(map.get("thing1").?, "banana and all that");
try testing.expectEqualStrings(map.get("thing2").?, "orange");
try testing.expectEqualStrings(map.get("thing3").?, "pear");
try testing.expectEqualStrings(map.get("space between").?, "the equals");
try testing.expectEqualStrings(map.get("no value").?, "");
const missing_key =
\\ valid = good
\\ = missing key
;
var key_error_map = fromBytes(testing.allocator, missing_key);
try testing.expectError(error.MissingKey, key_error_map);
const missing_value = " nothing\n \n";
var value_missing_map = fromBytes(testing.allocator, missing_value);
try testing.expectError(error.MissingValue, value_missing_map);
}
test "fromFile doesn't leak" {
var map = try fromFile(testing.allocator, "../test/test.conf", 1024 * 1024);
defer map.deinit();
} | src/main.zig |
const memory = @import("memory.zig");
const Map = @import("map.zig").Map;
const List = @import("list.zig").List;
pub fn MappedList(comptime KeyType: type, comptime ValueType: type,
comptime eql: fn(a: KeyType, b: KeyType) bool,
comptime cmp: fn(a: KeyType, b: KeyType) bool) type {
return struct {
const Self = @This();
const MapType = Map(KeyType, *Node, eql, cmp);
const ListType = List(*Node);
const Node = struct {
map: MapType.Node,
list: ListType.Node,
value: ValueType,
};
alloc: *memory.Allocator,
map: MapType = MapType{.alloc = undefined},
list: ListType = ListType{.alloc = undefined},
pub fn len(self: *Self) usize {
if (self.map.len != self.list.len) {
@panic("MappedList len out of sync!");
}
return self.map.len;
}
pub fn find(self: *Self, key: KeyType) ?ValueType {
const node_maybe = self.map.find_node(key);
if (node_maybe == null) {
return null;
}
return node_maybe.?.value.value;
}
pub fn push_front(self: *Self, key: KeyType, value: ValueType) memory.MemoryError!void {
const node = try self.alloc.alloc(Node);
node.map.right = null;
node.map.left = null;
node.map.key = key;
node.map.value = node;
node.list.value = node;
node.value = value;
self.map.insert_node(&node.map);
self.list.push_front_node(&node.list);
}
pub fn pop_front(self: *Self) memory.MemoryError!?ValueType {
const node_maybe = self.list.pop_front_node();
if (node_maybe == null) {
return null;
}
const node = node_maybe.?.value;
self.map.remove_node(&node.map);
const value = node.value;
try self.alloc.free(node);
return value;
}
pub fn find_bump_to_front(self: *Self, key: KeyType) ?ValueType {
const node_maybe = self.map.find_node(key);
if (node_maybe == null) {
return null;
}
const node = node_maybe.?.value;
self.list.bump_node_to_front(&node.list);
return node.value;
}
pub fn push_back(self: *Self, key: KeyType, value: ValueType) memory.MemoryError!void {
const node = try self.alloc.alloc(Node);
node.map.right = null;
node.map.left = null;
node.map.key = key;
node.map.value = node;
node.list.value = node;
node.value = value;
self.map.insert_node(&node.map);
self.list.push_back_node(&node.list);
}
pub fn pop_back(self: *Self) memory.MemoryError!?ValueType {
const node_maybe = self.list.pop_back_node();
if (node_maybe == null) {
return null;
}
const node = node_maybe.?.value;
self.map.remove_node(&node.map);
const value = node.value;
try self.alloc.free(node);
return value;
}
pub fn find_bump_to_back(self: *Self, key: KeyType) ?ValueType {
const node_maybe = self.map.find_node(key);
if (node_maybe == null) {
return null;
}
const node = node_maybe.?.value;
self.list.bump_node_to_back(&node.list);
return node.value;
}
pub fn find_remove(self: *Self, key: KeyType) memory.MemoryError!?ValueType {
const node_maybe = self.map.find_node(key);
if (node_maybe == null) {
return null;
}
const node = node_maybe.?.value;
self.list.remove_node(&node.list);
self.map.remove_node(&node.map);
const value = node.value;
try self.alloc.free(node);
return value;
}
};
}
fn usize_eql(a: usize, b: usize) bool {
return a == b;
}
fn usize_cmp(a: usize, b: usize) bool {
return a > b;
}
test "MappedList" {
const std = @import("std");
const equal = std.testing.expectEqual;
var alloc = memory.UnitTestAllocator{};
alloc.init();
defer alloc.done();
const UsizeUsizeMappedList = MappedList(usize, usize, usize_eql, usize_cmp);
var ml = UsizeUsizeMappedList{.alloc = &alloc.allocator};
const nil: ?usize = null;
// Empty
try equal(@as(usize, 0), ml.len());
try equal(nil, ml.find(100));
// Push and Pop from Front
try ml.push_front(1, 2);
try equal(@as(usize, 1), ml.len());
try equal(@as(usize, 2), ml.find(1).?);
try equal(@as(usize, 2), (try ml.pop_front()).?);
try equal(@as(usize, 0), ml.len());
// Empty
try equal(@as(usize, 0), ml.len());
try equal(nil, ml.find(1));
// Push and Pop from Back
try ml.push_back(5, 7);
try equal(@as(usize, 1), ml.len());
try equal(@as(usize, 7), ml.find(5).?);
try equal(@as(usize, 7), (try ml.pop_back()).?);
try equal(@as(usize, 0), ml.len());
// Empty
try equal(@as(usize, 0), ml.len());
try equal(nil, ml.find(5));
// Push and Pop Several Times From Both Directions
try ml.push_front(11, 1);
try ml.push_front(22, 2);
try ml.push_back(123, 456);
try ml.push_back(33, 3);
try ml.push_front(44, 4);
try ml.push_back(55, 5);
// 44: 4, 22: 2, 11: 1, 123: 456, 33: 3, 55: 5
try equal(@as(usize, 456), (try ml.find_remove(123)).?);
// 44: 4, 22: 2, 11: 1, 33: 3, 55: 5
try equal(@as(usize, 5), ml.len());
try equal(@as(usize, 1), ml.find(11).?);
try equal(@as(usize, 2), ml.find(22).?);
try equal(@as(usize, 3), ml.find(33).?);
try equal(@as(usize, 4), ml.find(44).?);
try equal(@as(usize, 5), ml.find(55).?);
try equal(nil, ml.find(5));
try equal(@as(usize, 4), ml.find_bump_to_front(44).?);
try equal(@as(usize, 5), ml.find_bump_to_back(55).?);
try equal(@as(usize, 4), (try ml.pop_front()).?);
// 22: 2, 11: 1, 33: 3, 55: 5
try equal(@as(usize, 5), (try ml.pop_back()).?);
// 22: 2, 11: 1, 33: 3
try equal(@as(usize, 2), ml.find_bump_to_back(22).?);
// 11: 1, 33: 3, 22: 2
try ml.push_back(66, 6);
// 11: 1, 33: 3, 22: 2, 66: 6
try equal(@as(usize, 3), ml.find_bump_to_front(33).?);
// 33: 3, 11: 1, 22: 2, 66: 6
try equal(@as(usize, 3), ml.find(33).?);
try equal(@as(usize, 4), ml.len());
try equal(@as(usize, 6), (try ml.pop_back()).?);
// 33: 3, 11: 1, 22: 2
try equal(@as(usize, 2), (try ml.pop_back()).?);
// 33: 3, 11: 1
try equal(@as(usize, 1), (try ml.pop_back()).?);
// 33: 3
try equal(@as(usize, 3), (try ml.pop_back()).?);
// Empty
try equal(@as(usize, 0), ml.len());
try equal(nil, ml.find(5));
try equal(nil, ml.find(55));
try equal(nil, try ml.pop_back());
try equal(nil, try ml.pop_front());
} | kernel/mapped_list.zig |
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